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199 lines
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199 lines
20 KiB
HTML
4 years ago
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<div id="projectname">SAME54P20A Test Project
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<div class="summary">
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<a href="#pub-attribs">Data Fields</a> </div>
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<div class="headertitle">
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<div class="title">Tcc Struct Reference</div> </div>
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<div class="contents">
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<p>TCC hardware registers.
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<a href="structTcc.html#details">More...</a></p>
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<p><code>#include <<a class="el" href="tcc_8h_source.html">tcc.h</a>></code></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
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Data Fields</h2></td></tr>
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<tr class="memitem:a32d3c991c1c006f20a6b193618729798"><td class="memItemLeft" align="right" valign="top"><a id="a32d3c991c1c006f20a6b193618729798"></a>
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__IO <a class="el" href="unionTCC__CTRLA__Type.html">TCC_CTRLA_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcc.html#a32d3c991c1c006f20a6b193618729798">CTRLA</a></td></tr>
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<tr class="memdesc:a32d3c991c1c006f20a6b193618729798"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00 (R/W 32) Control A. <br /></td></tr>
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__IO <a class="el" href="unionTCC__CTRLBCLR__Type.html">TCC_CTRLBCLR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcc.html#a2293428bb668bc0367cbe834987eca3e">CTRLBCLR</a></td></tr>
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<tr class="memdesc:a2293428bb668bc0367cbe834987eca3e"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x04 (R/W 8) Control B Clear. <br /></td></tr>
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__IO <a class="el" href="unionTCC__CTRLBSET__Type.html">TCC_CTRLBSET_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcc.html#abfdedd396ae9f95b86ed4b4333b08464">CTRLBSET</a></td></tr>
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<tr class="memdesc:abfdedd396ae9f95b86ed4b4333b08464"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x05 (R/W 8) Control B Set. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved1</b> [0x2]</td></tr>
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__I <a class="el" href="unionTCC__SYNCBUSY__Type.html">TCC_SYNCBUSY_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcc.html#a5f372e5370e478af6eaf94095ff171fe">SYNCBUSY</a></td></tr>
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<tr class="memdesc:a5f372e5370e478af6eaf94095ff171fe"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x08 (R/ 32) Synchronization Busy. <br /></td></tr>
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__IO <a class="el" href="unionTCC__FCTRLA__Type.html">TCC_FCTRLA_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcc.html#a5abb734e3b76cfbe2e535ac65f5a205e">FCTRLA</a></td></tr>
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<tr class="memdesc:a5abb734e3b76cfbe2e535ac65f5a205e"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0C (R/W 32) Recoverable Fault A Configuration. <br /></td></tr>
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__IO <a class="el" href="unionTCC__FCTRLB__Type.html">TCC_FCTRLB_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcc.html#aff0b84e22604af0a6b12b824ab6c1ee3">FCTRLB</a></td></tr>
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<tr class="memdesc:aff0b84e22604af0a6b12b824ab6c1ee3"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x10 (R/W 32) Recoverable Fault B Configuration. <br /></td></tr>
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__IO <a class="el" href="unionTCC__WEXCTRL__Type.html">TCC_WEXCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcc.html#a07d5bc9674cead25445060479c66acd1">WEXCTRL</a></td></tr>
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<tr class="memdesc:a07d5bc9674cead25445060479c66acd1"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x14 (R/W 32) Waveform Extension Configuration. <br /></td></tr>
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<tr class="memitem:a9e19a270dad42364b5b1b3c19a31e45b"><td class="memItemLeft" align="right" valign="top"><a id="a9e19a270dad42364b5b1b3c19a31e45b"></a>
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__IO <a class="el" href="unionTCC__DRVCTRL__Type.html">TCC_DRVCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcc.html#a9e19a270dad42364b5b1b3c19a31e45b">DRVCTRL</a></td></tr>
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<tr class="memdesc:a9e19a270dad42364b5b1b3c19a31e45b"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x18 (R/W 32) Driver Control. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved2</b> [0x2]</td></tr>
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<tr class="separator:a3d46ef37ba76a0b27199b460a7d248d5"><td class="memSeparator" colspan="2"> </td></tr>
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__IO <a class="el" href="unionTCC__DBGCTRL__Type.html">TCC_DBGCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcc.html#a570f4dfd9ace6f9e31a407114d91ea98">DBGCTRL</a></td></tr>
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<tr class="memdesc:a570f4dfd9ace6f9e31a407114d91ea98"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1E (R/W 8) Debug Control. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved3</b> [0x1]</td></tr>
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<tr class="separator:a711b0d92b25bba3bfe1c521d748327c9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4b01c1033af6dc64d9c7adfbe1e6e302"><td class="memItemLeft" align="right" valign="top"><a id="a4b01c1033af6dc64d9c7adfbe1e6e302"></a>
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__IO <a class="el" href="unionTCC__EVCTRL__Type.html">TCC_EVCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcc.html#a4b01c1033af6dc64d9c7adfbe1e6e302">EVCTRL</a></td></tr>
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<tr class="memdesc:a4b01c1033af6dc64d9c7adfbe1e6e302"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x20 (R/W 32) Event Control. <br /></td></tr>
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<tr class="memitem:a9a0528a9bada8511ddc01889842aa0ef"><td class="memItemLeft" align="right" valign="top"><a id="a9a0528a9bada8511ddc01889842aa0ef"></a>
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__IO <a class="el" href="unionTCC__INTENCLR__Type.html">TCC_INTENCLR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcc.html#a9a0528a9bada8511ddc01889842aa0ef">INTENCLR</a></td></tr>
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<tr class="memdesc:a9a0528a9bada8511ddc01889842aa0ef"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x24 (R/W 32) Interrupt Enable Clear. <br /></td></tr>
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__IO <a class="el" href="unionTCC__INTENSET__Type.html">TCC_INTENSET_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcc.html#a87325a9da9bb14bbbb254f07161c3824">INTENSET</a></td></tr>
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<tr class="memdesc:a87325a9da9bb14bbbb254f07161c3824"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x28 (R/W 32) Interrupt Enable Set. <br /></td></tr>
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__IO <a class="el" href="unionTCC__INTFLAG__Type.html">TCC_INTFLAG_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcc.html#a45850dfe47f384be457edd8185d2ada0">INTFLAG</a></td></tr>
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<tr class="memdesc:a45850dfe47f384be457edd8185d2ada0"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear. <br /></td></tr>
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__IO <a class="el" href="unionTCC__STATUS__Type.html">TCC_STATUS_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcc.html#a14f0707a16105fc215acc14d786476ff">STATUS</a></td></tr>
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<tr class="memdesc:a14f0707a16105fc215acc14d786476ff"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x30 (R/W 32) Status. <br /></td></tr>
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__IO <a class="el" href="unionTCC__COUNT__Type.html">TCC_COUNT_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcc.html#a8ee2b473a9570d65643b9b3251cb31ce">COUNT</a></td></tr>
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<tr class="memdesc:a8ee2b473a9570d65643b9b3251cb31ce"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x34 (R/W 32) Count. <br /></td></tr>
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__IO <a class="el" href="unionTCC__PATT__Type.html">TCC_PATT_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcc.html#ae9045f5074f643a3f8a70c681f644be3">PATT</a></td></tr>
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<tr class="memdesc:ae9045f5074f643a3f8a70c681f644be3"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x38 (R/W 16) Pattern. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved4</b> [0x2]</td></tr>
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__IO <a class="el" href="unionTCC__WAVE__Type.html">TCC_WAVE_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcc.html#aae49d975936cde132f53115171858a97">WAVE</a></td></tr>
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<tr class="memdesc:aae49d975936cde132f53115171858a97"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x3C (R/W 32) Waveform Control. <br /></td></tr>
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__IO <a class="el" href="unionTCC__PER__Type.html">TCC_PER_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcc.html#a9ea2a8862e07c7525629412b1839c656">PER</a></td></tr>
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<tr class="memdesc:a9ea2a8862e07c7525629412b1839c656"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x40 (R/W 32) Period. <br /></td></tr>
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<tr class="memitem:a686810041e485f67c2371a5008bbff98"><td class="memItemLeft" align="right" valign="top"><a id="a686810041e485f67c2371a5008bbff98"></a>
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__IO <a class="el" href="unionTCC__CC__Type.html">TCC_CC_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcc.html#a686810041e485f67c2371a5008bbff98">CC</a> [6]</td></tr>
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<tr class="memdesc:a686810041e485f67c2371a5008bbff98"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x44 (R/W 32) Compare and Capture. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved5</b> [0x8]</td></tr>
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__IO <a class="el" href="unionTCC__PATTBUF__Type.html">TCC_PATTBUF_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcc.html#ada5157f799de1bd303dd7f5505953be0">PATTBUF</a></td></tr>
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<tr class="memdesc:ada5157f799de1bd303dd7f5505953be0"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x64 (R/W 16) Pattern Buffer. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved6</b> [0x6]</td></tr>
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<tr class="memitem:acdbad8a793639cea04f3df92e95ab19b"><td class="memItemLeft" align="right" valign="top"><a id="acdbad8a793639cea04f3df92e95ab19b"></a>
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__IO <a class="el" href="unionTCC__PERBUF__Type.html">TCC_PERBUF_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcc.html#acdbad8a793639cea04f3df92e95ab19b">PERBUF</a></td></tr>
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<tr class="memdesc:acdbad8a793639cea04f3df92e95ab19b"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x6C (R/W 32) Period Buffer. <br /></td></tr>
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<tr class="memitem:a2e47d37d25bb97e8b4f1033a6823a348"><td class="memItemLeft" align="right" valign="top"><a id="a2e47d37d25bb97e8b4f1033a6823a348"></a>
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__IO <a class="el" href="unionTCC__CCBUF__Type.html">TCC_CCBUF_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcc.html#a2e47d37d25bb97e8b4f1033a6823a348">CCBUF</a> [6]</td></tr>
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<tr class="memdesc:a2e47d37d25bb97e8b4f1033a6823a348"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x70 (R/W 32) Compare and Capture Buffer. <br /></td></tr>
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<tr class="separator:a2e47d37d25bb97e8b4f1033a6823a348"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>TCC hardware registers. </p>
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<p class="definition">Definition at line <a class="el" href="tcc_8h_source.html#l01728">1728</a> of file <a class="el" href="tcc_8h_source.html">tcc.h</a>.</p>
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</div><hr/>The documentation for this struct was generated from the following file:<ul>
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<li>/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/<a class="el" href="tcc_8h_source.html">tcc.h</a></li>
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</ul>
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</small></address>
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