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90 lines
5.6 KiB
C
90 lines
5.6 KiB
C
5 years ago
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/**
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* \file
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*
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* \brief Instance description for ADC
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*
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* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMD21_ADC_INSTANCE_
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#define _SAMD21_ADC_INSTANCE_
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/* ========== Register definition for ADC peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_ADC_CTRLA (0x42004000U) /**< \brief (ADC) Control A */
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#define REG_ADC_REFCTRL (0x42004001U) /**< \brief (ADC) Reference Control */
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#define REG_ADC_AVGCTRL (0x42004002U) /**< \brief (ADC) Average Control */
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#define REG_ADC_SAMPCTRL (0x42004003U) /**< \brief (ADC) Sampling Time Control */
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#define REG_ADC_CTRLB (0x42004004U) /**< \brief (ADC) Control B */
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#define REG_ADC_WINCTRL (0x42004008U) /**< \brief (ADC) Window Monitor Control */
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#define REG_ADC_SWTRIG (0x4200400CU) /**< \brief (ADC) Software Trigger */
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#define REG_ADC_INPUTCTRL (0x42004010U) /**< \brief (ADC) Input Control */
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#define REG_ADC_EVCTRL (0x42004014U) /**< \brief (ADC) Event Control */
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#define REG_ADC_INTENCLR (0x42004016U) /**< \brief (ADC) Interrupt Enable Clear */
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#define REG_ADC_INTENSET (0x42004017U) /**< \brief (ADC) Interrupt Enable Set */
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#define REG_ADC_INTFLAG (0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear */
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#define REG_ADC_STATUS (0x42004019U) /**< \brief (ADC) Status */
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#define REG_ADC_RESULT (0x4200401AU) /**< \brief (ADC) Result */
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#define REG_ADC_WINLT (0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold */
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#define REG_ADC_WINUT (0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold */
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#define REG_ADC_GAINCORR (0x42004024U) /**< \brief (ADC) Gain Correction */
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#define REG_ADC_OFFSETCORR (0x42004026U) /**< \brief (ADC) Offset Correction */
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#define REG_ADC_CALIB (0x42004028U) /**< \brief (ADC) Calibration */
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#define REG_ADC_DBGCTRL (0x4200402AU) /**< \brief (ADC) Debug Control */
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#else
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#define REG_ADC_CTRLA (*(RwReg8 *)0x42004000U) /**< \brief (ADC) Control A */
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#define REG_ADC_REFCTRL (*(RwReg8 *)0x42004001U) /**< \brief (ADC) Reference Control */
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#define REG_ADC_AVGCTRL (*(RwReg8 *)0x42004002U) /**< \brief (ADC) Average Control */
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#define REG_ADC_SAMPCTRL (*(RwReg8 *)0x42004003U) /**< \brief (ADC) Sampling Time Control */
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#define REG_ADC_CTRLB (*(RwReg16*)0x42004004U) /**< \brief (ADC) Control B */
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#define REG_ADC_WINCTRL (*(RwReg8 *)0x42004008U) /**< \brief (ADC) Window Monitor Control */
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#define REG_ADC_SWTRIG (*(RwReg8 *)0x4200400CU) /**< \brief (ADC) Software Trigger */
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#define REG_ADC_INPUTCTRL (*(RwReg *)0x42004010U) /**< \brief (ADC) Input Control */
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#define REG_ADC_EVCTRL (*(RwReg8 *)0x42004014U) /**< \brief (ADC) Event Control */
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#define REG_ADC_INTENCLR (*(RwReg8 *)0x42004016U) /**< \brief (ADC) Interrupt Enable Clear */
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#define REG_ADC_INTENSET (*(RwReg8 *)0x42004017U) /**< \brief (ADC) Interrupt Enable Set */
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#define REG_ADC_INTFLAG (*(RwReg8 *)0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear */
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#define REG_ADC_STATUS (*(RoReg8 *)0x42004019U) /**< \brief (ADC) Status */
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#define REG_ADC_RESULT (*(RoReg16*)0x4200401AU) /**< \brief (ADC) Result */
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#define REG_ADC_WINLT (*(RwReg16*)0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold */
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#define REG_ADC_WINUT (*(RwReg16*)0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold */
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#define REG_ADC_GAINCORR (*(RwReg16*)0x42004024U) /**< \brief (ADC) Gain Correction */
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#define REG_ADC_OFFSETCORR (*(RwReg16*)0x42004026U) /**< \brief (ADC) Offset Correction */
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#define REG_ADC_CALIB (*(RwReg16*)0x42004028U) /**< \brief (ADC) Calibration */
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#define REG_ADC_DBGCTRL (*(RwReg8 *)0x4200402AU) /**< \brief (ADC) Debug Control */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for ADC peripheral ========== */
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#define ADC_DMAC_ID_RESRDY 39 // Index of DMA RESRDY trigger
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#define ADC_EXTCHANNEL_MSB 19 // Number of external channels
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#define ADC_GCLK_ID 30 // Index of Generic Clock
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#define ADC_RESULT_BITS 16 // Size of RESULT.RESULT bitfield
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#define ADC_RESULT_MSB 15 // Size of Result
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#endif /* _SAMD21_ADC_INSTANCE_ */
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