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389 lines
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389 lines
23 KiB
HTML
4 years ago
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<html lang="en">
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<head>
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<title>ARC Options - Using the GNU Compiler Collection (GCC)</title>
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<meta http-equiv="Content-Type" content="text/html">
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<meta name="description" content="Using the GNU Compiler Collection (GCC)">
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<meta name="generator" content="makeinfo 4.13">
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<link title="Top" rel="start" href="index.html#Top">
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<link rel="up" href="Submodel-Options.html#Submodel-Options" title="Submodel Options">
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<link rel="prev" href="Adapteva-Epiphany-Options.html#Adapteva-Epiphany-Options" title="Adapteva Epiphany Options">
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<link rel="next" href="ARM-Options.html#ARM-Options" title="ARM Options">
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<link href="http://www.gnu.org/software/texinfo/" rel="generator-home" title="Texinfo Homepage">
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Copyright (C) 1988-2015 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.3 or
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any later version published by the Free Software Foundation; with the
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Invariant Sections being ``Funding Free Software'', the Front-Cover
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Texts being (a) (see below), and with the Back-Cover Texts being (b)
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(see below). A copy of the license is included in the section entitled
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``GNU Free Documentation License''.
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(a) The FSF's Front-Cover Text is:
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A GNU Manual
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(b) The FSF's Back-Cover Text is:
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You have freedom to copy and modify this GNU Manual, like GNU
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funds for GNU development.-->
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--></style>
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</head>
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<body>
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<div class="node">
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<a name="ARC-Options"></a>
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<p>
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Next: <a rel="next" accesskey="n" href="ARM-Options.html#ARM-Options">ARM Options</a>,
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Previous: <a rel="previous" accesskey="p" href="Adapteva-Epiphany-Options.html#Adapteva-Epiphany-Options">Adapteva Epiphany Options</a>,
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Up: <a rel="up" accesskey="u" href="Submodel-Options.html#Submodel-Options">Submodel Options</a>
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<hr>
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</div>
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<h4 class="subsection">3.17.3 ARC Options</h4>
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<p><a name="index-ARC-options-1310"></a>
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The following options control the architecture variant for which code
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is being compiled:
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<!-- architecture variants -->
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<dl>
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<dt><code>-mbarrel-shifter</code><dd><a name="index-mbarrel_002dshifter-1311"></a>Generate instructions supported by barrel shifter. This is the default
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unless <samp><span class="option">-mcpu=ARC601</span></samp> is in effect.
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<br><dt><code>-mcpu=</code><var>cpu</var><dd><a name="index-mcpu-1312"></a>Set architecture type, register usage, and instruction scheduling
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parameters for <var>cpu</var>. There are also shortcut alias options
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available for backward compatibility and convenience. Supported
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values for <var>cpu</var> are
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<a name="index-mA6-1313"></a>
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<a name="index-mARC600-1314"></a>
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<dl><dt>‘<samp><span class="samp">ARC600</span></samp>’<dd>Compile for ARC600. Aliases: <samp><span class="option">-mA6</span></samp>, <samp><span class="option">-mARC600</span></samp>.
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<br><dt>‘<samp><span class="samp">ARC601</span></samp>’<dd><a name="index-mARC601-1315"></a>Compile for ARC601. Alias: <samp><span class="option">-mARC601</span></samp>.
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<br><dt>‘<samp><span class="samp">ARC700</span></samp>’<dd><a name="index-mA7-1316"></a><a name="index-mARC700-1317"></a>Compile for ARC700. Aliases: <samp><span class="option">-mA7</span></samp>, <samp><span class="option">-mARC700</span></samp>.
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This is the default when configured with <samp><span class="option">--with-cpu=arc700</span></samp>.
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</dl>
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<br><dt><code>-mdpfp</code><dd><a name="index-mdpfp-1318"></a><dt><code>-mdpfp-compact</code><dd><a name="index-mdpfp_002dcompact-1319"></a>FPX: Generate Double Precision FPX instructions, tuned for the compact
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implementation.
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<br><dt><code>-mdpfp-fast</code><dd><a name="index-mdpfp_002dfast-1320"></a>FPX: Generate Double Precision FPX instructions, tuned for the fast
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implementation.
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<br><dt><code>-mno-dpfp-lrsr</code><dd><a name="index-mno_002ddpfp_002dlrsr-1321"></a>Disable LR and SR instructions from using FPX extension aux registers.
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<br><dt><code>-mea</code><dd><a name="index-mea-1322"></a>Generate Extended arithmetic instructions. Currently only
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<code>divaw</code>, <code>adds</code>, <code>subs</code>, and <code>sat16</code> are
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supported. This is always enabled for <samp><span class="option">-mcpu=ARC700</span></samp>.
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<br><dt><code>-mno-mpy</code><dd><a name="index-mno_002dmpy-1323"></a>Do not generate mpy instructions for ARC700.
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<br><dt><code>-mmul32x16</code><dd><a name="index-mmul32x16-1324"></a>Generate 32x16 bit multiply and mac instructions.
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<br><dt><code>-mmul64</code><dd><a name="index-mmul64-1325"></a>Generate mul64 and mulu64 instructions. Only valid for <samp><span class="option">-mcpu=ARC600</span></samp>.
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<br><dt><code>-mnorm</code><dd><a name="index-mnorm-1326"></a>Generate norm instruction. This is the default if <samp><span class="option">-mcpu=ARC700</span></samp>
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is in effect.
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<br><dt><code>-mspfp</code><dd><a name="index-mspfp-1327"></a><dt><code>-mspfp-compact</code><dd><a name="index-mspfp_002dcompact-1328"></a>FPX: Generate Single Precision FPX instructions, tuned for the compact
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implementation.
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<br><dt><code>-mspfp-fast</code><dd><a name="index-mspfp_002dfast-1329"></a>FPX: Generate Single Precision FPX instructions, tuned for the fast
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implementation.
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<br><dt><code>-msimd</code><dd><a name="index-msimd-1330"></a>Enable generation of ARC SIMD instructions via target-specific
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builtins. Only valid for <samp><span class="option">-mcpu=ARC700</span></samp>.
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<br><dt><code>-msoft-float</code><dd><a name="index-msoft_002dfloat-1331"></a>This option ignored; it is provided for compatibility purposes only.
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Software floating point code is emitted by default, and this default
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can overridden by FPX options; ‘<samp><span class="samp">mspfp</span></samp>’, ‘<samp><span class="samp">mspfp-compact</span></samp>’, or
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‘<samp><span class="samp">mspfp-fast</span></samp>’ for single precision, and ‘<samp><span class="samp">mdpfp</span></samp>’,
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‘<samp><span class="samp">mdpfp-compact</span></samp>’, or ‘<samp><span class="samp">mdpfp-fast</span></samp>’ for double precision.
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<br><dt><code>-mswap</code><dd><a name="index-mswap-1332"></a>Generate swap instructions.
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</dl>
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<p>The following options are passed through to the assembler, and also
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define preprocessor macro symbols.
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<!-- Flags used by the assembler, but for which we define preprocessor -->
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<!-- macro symbols as well. -->
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<dl>
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<dt><code>-mdsp-packa</code><dd><a name="index-mdsp_002dpacka-1333"></a>Passed down to the assembler to enable the DSP Pack A extensions.
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Also sets the preprocessor symbol <code>__Xdsp_packa</code>.
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<br><dt><code>-mdvbf</code><dd><a name="index-mdvbf-1334"></a>Passed down to the assembler to enable the dual viterbi butterfly
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extension. Also sets the preprocessor symbol <code>__Xdvbf</code>.
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<!-- ARC700 4.10 extension instruction -->
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<br><dt><code>-mlock</code><dd><a name="index-mlock-1335"></a>Passed down to the assembler to enable the Locked Load/Store
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Conditional extension. Also sets the preprocessor symbol
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<code>__Xlock</code>.
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<br><dt><code>-mmac-d16</code><dd><a name="index-mmac_002dd16-1336"></a>Passed down to the assembler. Also sets the preprocessor symbol
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<code>__Xxmac_d16</code>.
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<br><dt><code>-mmac-24</code><dd><a name="index-mmac_002d24-1337"></a>Passed down to the assembler. Also sets the preprocessor symbol
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<code>__Xxmac_24</code>.
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<!-- ARC700 4.10 extension instruction -->
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<br><dt><code>-mrtsc</code><dd><a name="index-mrtsc-1338"></a>Passed down to the assembler to enable the 64-bit Time-Stamp Counter
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extension instruction. Also sets the preprocessor symbol
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<code>__Xrtsc</code>.
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<!-- ARC700 4.10 extension instruction -->
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<br><dt><code>-mswape</code><dd><a name="index-mswape-1339"></a>Passed down to the assembler to enable the swap byte ordering
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extension instruction. Also sets the preprocessor symbol
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<code>__Xswape</code>.
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<br><dt><code>-mtelephony</code><dd><a name="index-mtelephony-1340"></a>Passed down to the assembler to enable dual and single operand
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instructions for telephony. Also sets the preprocessor symbol
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<code>__Xtelephony</code>.
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<br><dt><code>-mxy</code><dd><a name="index-mxy-1341"></a>Passed down to the assembler to enable the XY Memory extension. Also
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sets the preprocessor symbol <code>__Xxy</code>.
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</dl>
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<p>The following options control how the assembly code is annotated:
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<!-- Assembly annotation options -->
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<dl>
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<dt><code>-misize</code><dd><a name="index-misize-1342"></a>Annotate assembler instructions with estimated addresses.
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<br><dt><code>-mannotate-align</code><dd><a name="index-mannotate_002dalign-1343"></a>Explain what alignment considerations lead to the decision to make an
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instruction short or long.
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</dl>
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<p>The following options are passed through to the linker:
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<!-- options passed through to the linker -->
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<dl>
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<dt><code>-marclinux</code><dd><a name="index-marclinux-1344"></a>Passed through to the linker, to specify use of the <code>arclinux</code> emulation.
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This option is enabled by default in tool chains built for
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<code>arc-linux-uclibc</code><!-- /@w --> and <code>arceb-linux-uclibc</code><!-- /@w --> targets
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when profiling is not requested.
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<br><dt><code>-marclinux_prof</code><dd><a name="index-marclinux_005fprof-1345"></a>Passed through to the linker, to specify use of the
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<code>arclinux_prof</code> emulation. This option is enabled by default in
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tool chains built for <code>arc-linux-uclibc</code><!-- /@w --> and
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<code>arceb-linux-uclibc</code><!-- /@w --> targets when profiling is requested.
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</dl>
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<p>The following options control the semantics of generated code:
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<!-- semantically relevant code generation options -->
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<dl>
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<dt><code>-mepilogue-cfi</code><dd><a name="index-mepilogue_002dcfi-1346"></a>Enable generation of call frame information for epilogues.
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<br><dt><code>-mno-epilogue-cfi</code><dd><a name="index-mno_002depilogue_002dcfi-1347"></a>Disable generation of call frame information for epilogues.
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<br><dt><code>-mlong-calls</code><dd><a name="index-mlong_002dcalls-1348"></a>Generate call insns as register indirect calls, thus providing access
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to the full 32-bit address range.
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<br><dt><code>-mmedium-calls</code><dd><a name="index-mmedium_002dcalls-1349"></a>Don't use less than 25 bit addressing range for calls, which is the
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offset available for an unconditional branch-and-link
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instruction. Conditional execution of function calls is suppressed, to
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allow use of the 25-bit range, rather than the 21-bit range with
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conditional branch-and-link. This is the default for tool chains built
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for <code>arc-linux-uclibc</code><!-- /@w --> and <code>arceb-linux-uclibc</code><!-- /@w --> targets.
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<br><dt><code>-mno-sdata</code><dd><a name="index-mno_002dsdata-1350"></a>Do not generate sdata references. This is the default for tool chains
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built for <code>arc-linux-uclibc</code><!-- /@w --> and <code>arceb-linux-uclibc</code><!-- /@w -->
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targets.
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<br><dt><code>-mucb-mcount</code><dd><a name="index-mucb_002dmcount-1351"></a>Instrument with mcount calls as used in UCB code. I.e. do the
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counting in the callee, not the caller. By default ARC instrumentation
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counts in the caller.
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<br><dt><code>-mvolatile-cache</code><dd><a name="index-mvolatile_002dcache-1352"></a>Use ordinarily cached memory accesses for volatile references. This is the
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default.
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<br><dt><code>-mno-volatile-cache</code><dd><a name="index-mno_002dvolatile_002dcache-1353"></a>Enable cache bypass for volatile references.
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</dl>
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<p>The following options fine tune code generation:
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<!-- code generation tuning options -->
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<dl>
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<dt><code>-malign-call</code><dd><a name="index-malign_002dcall-1354"></a>Do alignment optimizations for call instructions.
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<br><dt><code>-mauto-modify-reg</code><dd><a name="index-mauto_002dmodify_002dreg-1355"></a>Enable the use of pre/post modify with register displacement.
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<br><dt><code>-mbbit-peephole</code><dd><a name="index-mbbit_002dpeephole-1356"></a>Enable bbit peephole2.
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<br><dt><code>-mno-brcc</code><dd><a name="index-mno_002dbrcc-1357"></a>This option disables a target-specific pass in <samp><span class="file">arc_reorg</span></samp> to
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generate <code>BRcc</code> instructions. It has no effect on <code>BRcc</code>
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generation driven by the combiner pass.
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<br><dt><code>-mcase-vector-pcrel</code><dd><a name="index-mcase_002dvector_002dpcrel-1358"></a>Use pc-relative switch case tables - this enables case table shortening.
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This is the default for <samp><span class="option">-Os</span></samp>.
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<br><dt><code>-mcompact-casesi</code><dd><a name="index-mcompact_002dcasesi-1359"></a>Enable compact casesi pattern.
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This is the default for <samp><span class="option">-Os</span></samp>.
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<br><dt><code>-mno-cond-exec</code><dd><a name="index-mno_002dcond_002dexec-1360"></a>Disable ARCompact specific pass to generate conditional execution instructions.
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Due to delay slot scheduling and interactions between operand numbers,
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literal sizes, instruction lengths, and the support for conditional execution,
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the target-independent pass to generate conditional execution is often lacking,
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so the ARC port has kept a special pass around that tries to find more
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conditional execution generating opportunities after register allocation,
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branch shortening, and delay slot scheduling have been done. This pass
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generally, but not always, improves performance and code size, at the cost of
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extra compilation time, which is why there is an option to switch it off.
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If you have a problem with call instructions exceeding their allowable
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offset range because they are conditionalized, you should consider using
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<samp><span class="option">-mmedium-calls</span></samp> instead.
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<br><dt><code>-mearly-cbranchsi</code><dd><a name="index-mearly_002dcbranchsi-1361"></a>Enable pre-reload use of the cbranchsi pattern.
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<br><dt><code>-mexpand-adddi</code><dd><a name="index-mexpand_002dadddi-1362"></a>Expand <code>adddi3</code> and <code>subdi3</code> at rtl generation time into
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<code>add.f</code>, <code>adc</code> etc.
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<br><dt><code>-mindexed-loads</code><dd><a name="index-mindexed_002dloads-1363"></a>Enable the use of indexed loads. This can be problematic because some
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optimizers then assume that indexed stores exist, which is not
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the case.
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<br><dt><code>-mlra</code><dd><a name="index-mlra-1364"></a>Enable Local Register Allocation. This is still experimental for ARC,
|
||
|
|
so by default the compiler uses standard reload
|
||
|
|
(i.e. <samp><span class="option">-mno-lra</span></samp>).
|
||
|
|
|
||
|
|
<br><dt><code>-mlra-priority-none</code><dd><a name="index-mlra_002dpriority_002dnone-1365"></a>Don't indicate any priority for target registers.
|
||
|
|
|
||
|
|
<br><dt><code>-mlra-priority-compact</code><dd><a name="index-mlra_002dpriority_002dcompact-1366"></a>Indicate target register priority for r0..r3 / r12..r15.
|
||
|
|
|
||
|
|
<br><dt><code>-mlra-priority-noncompact</code><dd><a name="index-mlra_002dpriority_002dnoncompact-1367"></a>Reduce target regsiter priority for r0..r3 / r12..r15.
|
||
|
|
|
||
|
|
<br><dt><code>-mno-millicode</code><dd><a name="index-mno_002dmillicode-1368"></a>When optimizing for size (using <samp><span class="option">-Os</span></samp>), prologues and epilogues
|
||
|
|
that have to save or restore a large number of registers are often
|
||
|
|
shortened by using call to a special function in libgcc; this is
|
||
|
|
referred to as a <em>millicode</em> call. As these calls can pose
|
||
|
|
performance issues, and/or cause linking issues when linking in a
|
||
|
|
nonstandard way, this option is provided to turn off millicode call
|
||
|
|
generation.
|
||
|
|
|
||
|
|
<br><dt><code>-mmixed-code</code><dd><a name="index-mmixed_002dcode-1369"></a>Tweak register allocation to help 16-bit instruction generation.
|
||
|
|
This generally has the effect of decreasing the average instruction size
|
||
|
|
while increasing the instruction count.
|
||
|
|
|
||
|
|
<br><dt><code>-mq-class</code><dd><a name="index-mq_002dclass-1370"></a>Enable 'q' instruction alternatives.
|
||
|
|
This is the default for <samp><span class="option">-Os</span></samp>.
|
||
|
|
|
||
|
|
<br><dt><code>-mRcq</code><dd><a name="index-mRcq-1371"></a>Enable Rcq constraint handling - most short code generation depends on this.
|
||
|
|
This is the default.
|
||
|
|
|
||
|
|
<br><dt><code>-mRcw</code><dd><a name="index-mRcw-1372"></a>Enable Rcw constraint handling - ccfsm condexec mostly depends on this.
|
||
|
|
This is the default.
|
||
|
|
|
||
|
|
<br><dt><code>-msize-level=</code><var>level</var><dd><a name="index-msize_002dlevel-1373"></a>Fine-tune size optimization with regards to instruction lengths and alignment.
|
||
|
|
The recognized values for <var>level</var> are:
|
||
|
|
<dl>
|
||
|
|
<dt>‘<samp><span class="samp">0</span></samp>’<dd>No size optimization. This level is deprecated and treated like ‘<samp><span class="samp">1</span></samp>’.
|
||
|
|
|
||
|
|
<br><dt>‘<samp><span class="samp">1</span></samp>’<dd>Short instructions are used opportunistically.
|
||
|
|
|
||
|
|
<br><dt>‘<samp><span class="samp">2</span></samp>’<dd>In addition, alignment of loops and of code after barriers are dropped.
|
||
|
|
|
||
|
|
<br><dt>‘<samp><span class="samp">3</span></samp>’<dd>In addition, optional data alignment is dropped, and the option <samp><span class="option">Os</span></samp> is enabled.
|
||
|
|
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<p>This defaults to ‘<samp><span class="samp">3</span></samp>’ when <samp><span class="option">-Os</span></samp> is in effect. Otherwise,
|
||
|
|
the behavior when this is not set is equivalent to level ‘<samp><span class="samp">1</span></samp>’.
|
||
|
|
|
||
|
|
<br><dt><code>-mtune=</code><var>cpu</var><dd><a name="index-mtune-1374"></a>Set instruction scheduling parameters for <var>cpu</var>, overriding any implied
|
||
|
|
by <samp><span class="option">-mcpu=</span></samp>.
|
||
|
|
|
||
|
|
<p>Supported values for <var>cpu</var> are
|
||
|
|
|
||
|
|
<dl>
|
||
|
|
<dt>‘<samp><span class="samp">ARC600</span></samp>’<dd>Tune for ARC600 cpu.
|
||
|
|
|
||
|
|
<br><dt>‘<samp><span class="samp">ARC601</span></samp>’<dd>Tune for ARC601 cpu.
|
||
|
|
|
||
|
|
<br><dt>‘<samp><span class="samp">ARC700</span></samp>’<dd>Tune for ARC700 cpu with standard multiplier block.
|
||
|
|
|
||
|
|
<br><dt>‘<samp><span class="samp">ARC700-xmac</span></samp>’<dd>Tune for ARC700 cpu with XMAC block.
|
||
|
|
|
||
|
|
<br><dt>‘<samp><span class="samp">ARC725D</span></samp>’<dd>Tune for ARC725D cpu.
|
||
|
|
|
||
|
|
<br><dt>‘<samp><span class="samp">ARC750D</span></samp>’<dd>Tune for ARC750D cpu.
|
||
|
|
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<br><dt><code>-mmultcost=</code><var>num</var><dd><a name="index-mmultcost-1375"></a>Cost to assume for a multiply instruction, with ‘<samp><span class="samp">4</span></samp>’ being equal to a
|
||
|
|
normal instruction.
|
||
|
|
|
||
|
|
<br><dt><code>-munalign-prob-threshold=</code><var>probability</var><dd><a name="index-munalign_002dprob_002dthreshold-1376"></a>Set probability threshold for unaligning branches.
|
||
|
|
When tuning for ‘<samp><span class="samp">ARC700</span></samp>’ and optimizing for speed, branches without
|
||
|
|
filled delay slot are preferably emitted unaligned and long, unless
|
||
|
|
profiling indicates that the probability for the branch to be taken
|
||
|
|
is below <var>probability</var>. See <a href="Cross_002dprofiling.html#Cross_002dprofiling">Cross-profiling</a>.
|
||
|
|
The default is (REG_BR_PROB_BASE/2), i.e. 5000.
|
||
|
|
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<p>The following options are maintained for backward compatibility, but
|
||
|
|
are now deprecated and will be removed in a future release:
|
||
|
|
|
||
|
|
<!-- Deprecated options -->
|
||
|
|
<dl>
|
||
|
|
<dt><code>-margonaut</code><dd><a name="index-margonaut-1377"></a>Obsolete FPX.
|
||
|
|
|
||
|
|
<br><dt><code>-mbig-endian</code><dd><a name="index-mbig_002dendian-1378"></a><dt><code>-EB</code><dd><a name="index-EB-1379"></a>Compile code for big endian targets. Use of these options is now
|
||
|
|
deprecated. Users wanting big-endian code, should use the
|
||
|
|
<code>arceb-elf32</code><!-- /@w --> and <code>arceb-linux-uclibc</code><!-- /@w --> targets when
|
||
|
|
building the tool chain, for which big-endian is the default.
|
||
|
|
|
||
|
|
<br><dt><code>-mlittle-endian</code><dd><a name="index-mlittle_002dendian-1380"></a><dt><code>-EL</code><dd><a name="index-EL-1381"></a>Compile code for little endian targets. Use of these options is now
|
||
|
|
deprecated. Users wanting little-endian code should use the
|
||
|
|
<code>arc-elf32</code><!-- /@w --> and <code>arc-linux-uclibc</code><!-- /@w --> targets when
|
||
|
|
building the tool chain, for which little-endian is the default.
|
||
|
|
|
||
|
|
<br><dt><code>-mbarrel_shifter</code><dd><a name="index-mbarrel_005fshifter-1382"></a>Replaced by <samp><span class="option">-mbarrel-shifter</span></samp>.
|
||
|
|
|
||
|
|
<br><dt><code>-mdpfp_compact</code><dd><a name="index-mdpfp_005fcompact-1383"></a>Replaced by <samp><span class="option">-mdpfp-compact</span></samp>.
|
||
|
|
|
||
|
|
<br><dt><code>-mdpfp_fast</code><dd><a name="index-mdpfp_005ffast-1384"></a>Replaced by <samp><span class="option">-mdpfp-fast</span></samp>.
|
||
|
|
|
||
|
|
<br><dt><code>-mdsp_packa</code><dd><a name="index-mdsp_005fpacka-1385"></a>Replaced by <samp><span class="option">-mdsp-packa</span></samp>.
|
||
|
|
|
||
|
|
<br><dt><code>-mEA</code><dd><a name="index-mEA-1386"></a>Replaced by <samp><span class="option">-mea</span></samp>.
|
||
|
|
|
||
|
|
<br><dt><code>-mmac_24</code><dd><a name="index-mmac_005f24-1387"></a>Replaced by <samp><span class="option">-mmac-24</span></samp>.
|
||
|
|
|
||
|
|
<br><dt><code>-mmac_d16</code><dd><a name="index-mmac_005fd16-1388"></a>Replaced by <samp><span class="option">-mmac-d16</span></samp>.
|
||
|
|
|
||
|
|
<br><dt><code>-mspfp_compact</code><dd><a name="index-mspfp_005fcompact-1389"></a>Replaced by <samp><span class="option">-mspfp-compact</span></samp>.
|
||
|
|
|
||
|
|
<br><dt><code>-mspfp_fast</code><dd><a name="index-mspfp_005ffast-1390"></a>Replaced by <samp><span class="option">-mspfp-fast</span></samp>.
|
||
|
|
|
||
|
|
<br><dt><code>-mtune=</code><var>cpu</var><dd><a name="index-mtune-1391"></a>Values ‘<samp><span class="samp">arc600</span></samp>’, ‘<samp><span class="samp">arc601</span></samp>’, ‘<samp><span class="samp">arc700</span></samp>’ and
|
||
|
|
‘<samp><span class="samp">arc700-xmac</span></samp>’ for <var>cpu</var> are replaced by ‘<samp><span class="samp">ARC600</span></samp>’,
|
||
|
|
‘<samp><span class="samp">ARC601</span></samp>’, ‘<samp><span class="samp">ARC700</span></samp>’ and ‘<samp><span class="samp">ARC700-xmac</span></samp>’ respectively
|
||
|
|
|
||
|
|
<br><dt><code>-multcost=</code><var>num</var><dd><a name="index-multcost-1392"></a>Replaced by <samp><span class="option">-mmultcost</span></samp>.
|
||
|
|
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
</body></html>
|
||
|
|
|