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42 lines
1.2 KiB
Groff
42 lines
1.2 KiB
Groff
4 years ago
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.TH "power.h" 3 "24 Jun 2019" "Version 2.0.0" "avr-libc" \" -*- nroff -*-
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.ad l
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.nh
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.SH NAME
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power.h \-
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.SH SYNOPSIS
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.br
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.PP
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.SS "Defines"
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.in +1c
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.ti -1c
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.RI "#define \fBclock_prescale_get\fP() (clock_div_t)(CLKPR & (\fBuint8_t\fP)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)|(1<<CLKPS3)))"
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.br
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.in -1c
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.SS "Functions"
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.in +1c
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.ti -1c
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.RI "static __inline void \fB__attribute__\fP ((__always_inline__)) __power_all_enable()"
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.br
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.ti -1c
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.RI "void \fBclock_prescale_set\fP (clock_div_t __x)"
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.br
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.in -1c
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.SH "Detailed Description"
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.PP
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.SH "Define Documentation"
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.PP
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.SS "#define clock_prescale_get() (clock_div_t)(CLKPR & (\fBuint8_t\fP)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)|(1<<CLKPS3)))"Gets and returns the clock prescaler register setting. The return type is \fCclock_div_t\fP.
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.PP
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\fBNote:\fP
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.RS 4
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For device with XTAL Divide Control Register (XDIV), return can actually range from 1 to 129. Care should be taken has the return value could differ from the typedef enum clock_div_t. This should only happen if clock_prescale_set was previously called with a value other than those defined by \fCclock_div_t\fP.
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.RE
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.PP
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.SH "Author"
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.PP
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Generated automatically by Doxygen for avr-libc from the source code.
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