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70 lines
3.7 KiB
C
70 lines
3.7 KiB
C
5 years ago
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/**
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* \file
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*
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* \brief Instance description for GCLK
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*
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* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMD21_GCLK_INSTANCE_
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#define _SAMD21_GCLK_INSTANCE_
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/* ========== Register definition for GCLK peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_GCLK_CTRL (0x40000C00U) /**< \brief (GCLK) Control */
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#define REG_GCLK_STATUS (0x40000C01U) /**< \brief (GCLK) Status */
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#define REG_GCLK_CLKCTRL (0x40000C02U) /**< \brief (GCLK) Generic Clock Control */
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#define REG_GCLK_GENCTRL (0x40000C04U) /**< \brief (GCLK) Generic Clock Generator Control */
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#define REG_GCLK_GENDIV (0x40000C08U) /**< \brief (GCLK) Generic Clock Generator Division */
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#else
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#define REG_GCLK_CTRL (*(RwReg8 *)0x40000C00U) /**< \brief (GCLK) Control */
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#define REG_GCLK_STATUS (*(RoReg8 *)0x40000C01U) /**< \brief (GCLK) Status */
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#define REG_GCLK_CLKCTRL (*(RwReg16*)0x40000C02U) /**< \brief (GCLK) Generic Clock Control */
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#define REG_GCLK_GENCTRL (*(RwReg *)0x40000C04U) /**< \brief (GCLK) Generic Clock Generator Control */
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#define REG_GCLK_GENDIV (*(RwReg *)0x40000C08U) /**< \brief (GCLK) Generic Clock Generator Division */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for GCLK peripheral ========== */
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#define GCLK_GENDIV_BITS 16
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#define GCLK_GEN_NUM 9 // Number of Generic Clock Generators
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#define GCLK_GEN_NUM_MSB 8 // Number of Generic Clock Generators - 1
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#define GCLK_GEN_SOURCE_NUM_MSB 8 // Number of Generic Clock Sources - 1
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#define GCLK_NUM 37 // Number of Generic Clock Users
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#define GCLK_SOURCE_DFLL48M 7 // DFLL48M output
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#define GCLK_SOURCE_FDPLL 8 // FDPLL output
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#define GCLK_SOURCE_GCLKGEN1 2 // Generic clock generator 1 output
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#define GCLK_SOURCE_GCLKIN 1 // Generator input pad
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#define GCLK_SOURCE_NUM 9 // Number of Generic Clock Sources
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#define GCLK_SOURCE_OSCULP32K 3 // OSCULP32K oscillator output
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#define GCLK_SOURCE_OSC8M 6 // OSC8M oscillator output
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#define GCLK_SOURCE_OSC32K 4 // OSC32K oscillator outpur
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#define GCLK_SOURCE_XOSC 0 // XOSC oscillator output
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#define GCLK_SOURCE_XOSC32K 5 // XOSC32K oscillator output
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#endif /* _SAMD21_GCLK_INSTANCE_ */
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