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650 lines
74 KiB
C
650 lines
74 KiB
C
4 years ago
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/**
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* \brief Component description for ADC
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*
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* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
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*
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* Subject to your compliance with these terms, you may use Microchip software and any derivatives
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* exclusively with Microchip products. It is your responsibility to comply with third party license
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* terms applicable to your use of third party software (including open source software) that may
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* accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
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* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
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* FITNESS FOR A PARTICULAR PURPOSE.
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*
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* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
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* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
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* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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*/
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/* file generated from device description version 2020-03-12T17:27:04Z */
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#ifndef _SAME54_ADC_COMPONENT_H_
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#define _SAME54_ADC_COMPONENT_H_
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/* ************************************************************************** */
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/* SOFTWARE API DEFINITION FOR ADC */
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/* ************************************************************************** */
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/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 16) Control A -------- */
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#define ADC_CTRLA_RESETVALUE _U_(0x00) /**< (ADC_CTRLA) Control A Reset Value */
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#define ADC_CTRLA_SWRST_Pos _U_(0) /**< (ADC_CTRLA) Software Reset Position */
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#define ADC_CTRLA_SWRST_Msk (_U_(0x1) << ADC_CTRLA_SWRST_Pos) /**< (ADC_CTRLA) Software Reset Mask */
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#define ADC_CTRLA_SWRST(value) (ADC_CTRLA_SWRST_Msk & ((value) << ADC_CTRLA_SWRST_Pos))
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#define ADC_CTRLA_ENABLE_Pos _U_(1) /**< (ADC_CTRLA) Enable Position */
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#define ADC_CTRLA_ENABLE_Msk (_U_(0x1) << ADC_CTRLA_ENABLE_Pos) /**< (ADC_CTRLA) Enable Mask */
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#define ADC_CTRLA_ENABLE(value) (ADC_CTRLA_ENABLE_Msk & ((value) << ADC_CTRLA_ENABLE_Pos))
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#define ADC_CTRLA_DUALSEL_Pos _U_(3) /**< (ADC_CTRLA) Dual Mode Trigger Selection Position */
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#define ADC_CTRLA_DUALSEL_Msk (_U_(0x3) << ADC_CTRLA_DUALSEL_Pos) /**< (ADC_CTRLA) Dual Mode Trigger Selection Mask */
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#define ADC_CTRLA_DUALSEL(value) (ADC_CTRLA_DUALSEL_Msk & ((value) << ADC_CTRLA_DUALSEL_Pos))
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#define ADC_CTRLA_DUALSEL_BOTH_Val _U_(0x0) /**< (ADC_CTRLA) Start event or software trigger will start a conversion on both ADCs */
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#define ADC_CTRLA_DUALSEL_INTERLEAVE_Val _U_(0x1) /**< (ADC_CTRLA) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 */
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#define ADC_CTRLA_DUALSEL_BOTH (ADC_CTRLA_DUALSEL_BOTH_Val << ADC_CTRLA_DUALSEL_Pos) /**< (ADC_CTRLA) Start event or software trigger will start a conversion on both ADCs Position */
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#define ADC_CTRLA_DUALSEL_INTERLEAVE (ADC_CTRLA_DUALSEL_INTERLEAVE_Val << ADC_CTRLA_DUALSEL_Pos) /**< (ADC_CTRLA) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 Position */
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#define ADC_CTRLA_SLAVEEN_Pos _U_(5) /**< (ADC_CTRLA) Slave Enable Position */
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#define ADC_CTRLA_SLAVEEN_Msk (_U_(0x1) << ADC_CTRLA_SLAVEEN_Pos) /**< (ADC_CTRLA) Slave Enable Mask */
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#define ADC_CTRLA_SLAVEEN(value) (ADC_CTRLA_SLAVEEN_Msk & ((value) << ADC_CTRLA_SLAVEEN_Pos))
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#define ADC_CTRLA_RUNSTDBY_Pos _U_(6) /**< (ADC_CTRLA) Run in Standby Position */
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#define ADC_CTRLA_RUNSTDBY_Msk (_U_(0x1) << ADC_CTRLA_RUNSTDBY_Pos) /**< (ADC_CTRLA) Run in Standby Mask */
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#define ADC_CTRLA_RUNSTDBY(value) (ADC_CTRLA_RUNSTDBY_Msk & ((value) << ADC_CTRLA_RUNSTDBY_Pos))
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#define ADC_CTRLA_ONDEMAND_Pos _U_(7) /**< (ADC_CTRLA) On Demand Control Position */
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#define ADC_CTRLA_ONDEMAND_Msk (_U_(0x1) << ADC_CTRLA_ONDEMAND_Pos) /**< (ADC_CTRLA) On Demand Control Mask */
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#define ADC_CTRLA_ONDEMAND(value) (ADC_CTRLA_ONDEMAND_Msk & ((value) << ADC_CTRLA_ONDEMAND_Pos))
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#define ADC_CTRLA_PRESCALER_Pos _U_(8) /**< (ADC_CTRLA) Prescaler Configuration Position */
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#define ADC_CTRLA_PRESCALER_Msk (_U_(0x7) << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Prescaler Configuration Mask */
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#define ADC_CTRLA_PRESCALER(value) (ADC_CTRLA_PRESCALER_Msk & ((value) << ADC_CTRLA_PRESCALER_Pos))
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#define ADC_CTRLA_PRESCALER_DIV2_Val _U_(0x0) /**< (ADC_CTRLA) Peripheral clock divided by 2 */
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#define ADC_CTRLA_PRESCALER_DIV4_Val _U_(0x1) /**< (ADC_CTRLA) Peripheral clock divided by 4 */
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#define ADC_CTRLA_PRESCALER_DIV8_Val _U_(0x2) /**< (ADC_CTRLA) Peripheral clock divided by 8 */
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#define ADC_CTRLA_PRESCALER_DIV16_Val _U_(0x3) /**< (ADC_CTRLA) Peripheral clock divided by 16 */
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#define ADC_CTRLA_PRESCALER_DIV32_Val _U_(0x4) /**< (ADC_CTRLA) Peripheral clock divided by 32 */
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#define ADC_CTRLA_PRESCALER_DIV64_Val _U_(0x5) /**< (ADC_CTRLA) Peripheral clock divided by 64 */
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#define ADC_CTRLA_PRESCALER_DIV128_Val _U_(0x6) /**< (ADC_CTRLA) Peripheral clock divided by 128 */
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#define ADC_CTRLA_PRESCALER_DIV256_Val _U_(0x7) /**< (ADC_CTRLA) Peripheral clock divided by 256 */
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#define ADC_CTRLA_PRESCALER_DIV2 (ADC_CTRLA_PRESCALER_DIV2_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 2 Position */
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#define ADC_CTRLA_PRESCALER_DIV4 (ADC_CTRLA_PRESCALER_DIV4_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 4 Position */
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#define ADC_CTRLA_PRESCALER_DIV8 (ADC_CTRLA_PRESCALER_DIV8_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 8 Position */
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#define ADC_CTRLA_PRESCALER_DIV16 (ADC_CTRLA_PRESCALER_DIV16_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 16 Position */
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#define ADC_CTRLA_PRESCALER_DIV32 (ADC_CTRLA_PRESCALER_DIV32_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 32 Position */
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#define ADC_CTRLA_PRESCALER_DIV64 (ADC_CTRLA_PRESCALER_DIV64_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 64 Position */
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#define ADC_CTRLA_PRESCALER_DIV128 (ADC_CTRLA_PRESCALER_DIV128_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 128 Position */
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#define ADC_CTRLA_PRESCALER_DIV256 (ADC_CTRLA_PRESCALER_DIV256_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 256 Position */
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#define ADC_CTRLA_R2R_Pos _U_(15) /**< (ADC_CTRLA) Rail to Rail Operation Enable Position */
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#define ADC_CTRLA_R2R_Msk (_U_(0x1) << ADC_CTRLA_R2R_Pos) /**< (ADC_CTRLA) Rail to Rail Operation Enable Mask */
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#define ADC_CTRLA_R2R(value) (ADC_CTRLA_R2R_Msk & ((value) << ADC_CTRLA_R2R_Pos))
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#define ADC_CTRLA_Msk _U_(0x87FB) /**< (ADC_CTRLA) Register Mask */
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/* -------- ADC_EVCTRL : (ADC Offset: 0x02) (R/W 8) Event Control -------- */
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#define ADC_EVCTRL_RESETVALUE _U_(0x00) /**< (ADC_EVCTRL) Event Control Reset Value */
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#define ADC_EVCTRL_FLUSHEI_Pos _U_(0) /**< (ADC_EVCTRL) Flush Event Input Enable Position */
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#define ADC_EVCTRL_FLUSHEI_Msk (_U_(0x1) << ADC_EVCTRL_FLUSHEI_Pos) /**< (ADC_EVCTRL) Flush Event Input Enable Mask */
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#define ADC_EVCTRL_FLUSHEI(value) (ADC_EVCTRL_FLUSHEI_Msk & ((value) << ADC_EVCTRL_FLUSHEI_Pos))
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#define ADC_EVCTRL_STARTEI_Pos _U_(1) /**< (ADC_EVCTRL) Start Conversion Event Input Enable Position */
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#define ADC_EVCTRL_STARTEI_Msk (_U_(0x1) << ADC_EVCTRL_STARTEI_Pos) /**< (ADC_EVCTRL) Start Conversion Event Input Enable Mask */
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#define ADC_EVCTRL_STARTEI(value) (ADC_EVCTRL_STARTEI_Msk & ((value) << ADC_EVCTRL_STARTEI_Pos))
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#define ADC_EVCTRL_FLUSHINV_Pos _U_(2) /**< (ADC_EVCTRL) Flush Event Invert Enable Position */
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#define ADC_EVCTRL_FLUSHINV_Msk (_U_(0x1) << ADC_EVCTRL_FLUSHINV_Pos) /**< (ADC_EVCTRL) Flush Event Invert Enable Mask */
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#define ADC_EVCTRL_FLUSHINV(value) (ADC_EVCTRL_FLUSHINV_Msk & ((value) << ADC_EVCTRL_FLUSHINV_Pos))
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#define ADC_EVCTRL_STARTINV_Pos _U_(3) /**< (ADC_EVCTRL) Start Conversion Event Invert Enable Position */
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#define ADC_EVCTRL_STARTINV_Msk (_U_(0x1) << ADC_EVCTRL_STARTINV_Pos) /**< (ADC_EVCTRL) Start Conversion Event Invert Enable Mask */
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#define ADC_EVCTRL_STARTINV(value) (ADC_EVCTRL_STARTINV_Msk & ((value) << ADC_EVCTRL_STARTINV_Pos))
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#define ADC_EVCTRL_RESRDYEO_Pos _U_(4) /**< (ADC_EVCTRL) Result Ready Event Out Position */
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#define ADC_EVCTRL_RESRDYEO_Msk (_U_(0x1) << ADC_EVCTRL_RESRDYEO_Pos) /**< (ADC_EVCTRL) Result Ready Event Out Mask */
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#define ADC_EVCTRL_RESRDYEO(value) (ADC_EVCTRL_RESRDYEO_Msk & ((value) << ADC_EVCTRL_RESRDYEO_Pos))
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#define ADC_EVCTRL_WINMONEO_Pos _U_(5) /**< (ADC_EVCTRL) Window Monitor Event Out Position */
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#define ADC_EVCTRL_WINMONEO_Msk (_U_(0x1) << ADC_EVCTRL_WINMONEO_Pos) /**< (ADC_EVCTRL) Window Monitor Event Out Mask */
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#define ADC_EVCTRL_WINMONEO(value) (ADC_EVCTRL_WINMONEO_Msk & ((value) << ADC_EVCTRL_WINMONEO_Pos))
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#define ADC_EVCTRL_Msk _U_(0x3F) /**< (ADC_EVCTRL) Register Mask */
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/* -------- ADC_DBGCTRL : (ADC Offset: 0x03) (R/W 8) Debug Control -------- */
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#define ADC_DBGCTRL_RESETVALUE _U_(0x00) /**< (ADC_DBGCTRL) Debug Control Reset Value */
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#define ADC_DBGCTRL_DBGRUN_Pos _U_(0) /**< (ADC_DBGCTRL) Debug Run Position */
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#define ADC_DBGCTRL_DBGRUN_Msk (_U_(0x1) << ADC_DBGCTRL_DBGRUN_Pos) /**< (ADC_DBGCTRL) Debug Run Mask */
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#define ADC_DBGCTRL_DBGRUN(value) (ADC_DBGCTRL_DBGRUN_Msk & ((value) << ADC_DBGCTRL_DBGRUN_Pos))
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#define ADC_DBGCTRL_Msk _U_(0x01) /**< (ADC_DBGCTRL) Register Mask */
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/* -------- ADC_INPUTCTRL : (ADC Offset: 0x04) (R/W 16) Input Control -------- */
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#define ADC_INPUTCTRL_RESETVALUE _U_(0x00) /**< (ADC_INPUTCTRL) Input Control Reset Value */
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#define ADC_INPUTCTRL_MUXPOS_Pos _U_(0) /**< (ADC_INPUTCTRL) Positive Mux Input Selection Position */
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#define ADC_INPUTCTRL_MUXPOS_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) Positive Mux Input Selection Mask */
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#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos))
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#define ADC_INPUTCTRL_MUXPOS_AIN0_Val _U_(0x0) /**< (ADC_INPUTCTRL) ADC AIN0 Pin */
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#define ADC_INPUTCTRL_MUXPOS_AIN1_Val _U_(0x1) /**< (ADC_INPUTCTRL) ADC AIN1 Pin */
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#define ADC_INPUTCTRL_MUXPOS_AIN2_Val _U_(0x2) /**< (ADC_INPUTCTRL) ADC AIN2 Pin */
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#define ADC_INPUTCTRL_MUXPOS_AIN3_Val _U_(0x3) /**< (ADC_INPUTCTRL) ADC AIN3 Pin */
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#define ADC_INPUTCTRL_MUXPOS_AIN4_Val _U_(0x4) /**< (ADC_INPUTCTRL) ADC AIN4 Pin */
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#define ADC_INPUTCTRL_MUXPOS_AIN5_Val _U_(0x5) /**< (ADC_INPUTCTRL) ADC AIN5 Pin */
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#define ADC_INPUTCTRL_MUXPOS_AIN6_Val _U_(0x6) /**< (ADC_INPUTCTRL) ADC AIN6 Pin */
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#define ADC_INPUTCTRL_MUXPOS_AIN7_Val _U_(0x7) /**< (ADC_INPUTCTRL) ADC AIN7 Pin */
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#define ADC_INPUTCTRL_MUXPOS_AIN8_Val _U_(0x8) /**< (ADC_INPUTCTRL) ADC AIN8 Pin */
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#define ADC_INPUTCTRL_MUXPOS_AIN9_Val _U_(0x9) /**< (ADC_INPUTCTRL) ADC AIN9 Pin */
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#define ADC_INPUTCTRL_MUXPOS_AIN10_Val _U_(0xA) /**< (ADC_INPUTCTRL) ADC AIN10 Pin */
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#define ADC_INPUTCTRL_MUXPOS_AIN11_Val _U_(0xB) /**< (ADC_INPUTCTRL) ADC AIN11 Pin */
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#define ADC_INPUTCTRL_MUXPOS_AIN12_Val _U_(0xC) /**< (ADC_INPUTCTRL) ADC AIN12 Pin */
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#define ADC_INPUTCTRL_MUXPOS_AIN13_Val _U_(0xD) /**< (ADC_INPUTCTRL) ADC AIN13 Pin */
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#define ADC_INPUTCTRL_MUXPOS_AIN14_Val _U_(0xE) /**< (ADC_INPUTCTRL) ADC AIN14 Pin */
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#define ADC_INPUTCTRL_MUXPOS_AIN15_Val _U_(0xF) /**< (ADC_INPUTCTRL) ADC AIN15 Pin */
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#define ADC_INPUTCTRL_MUXPOS_AIN16_Val _U_(0x10) /**< (ADC_INPUTCTRL) ADC AIN16 Pin */
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#define ADC_INPUTCTRL_MUXPOS_AIN17_Val _U_(0x11) /**< (ADC_INPUTCTRL) ADC AIN17 Pin */
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#define ADC_INPUTCTRL_MUXPOS_AIN18_Val _U_(0x12) /**< (ADC_INPUTCTRL) ADC AIN18 Pin */
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#define ADC_INPUTCTRL_MUXPOS_AIN19_Val _U_(0x13) /**< (ADC_INPUTCTRL) ADC AIN19 Pin */
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#define ADC_INPUTCTRL_MUXPOS_AIN20_Val _U_(0x14) /**< (ADC_INPUTCTRL) ADC AIN20 Pin */
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#define ADC_INPUTCTRL_MUXPOS_AIN21_Val _U_(0x15) /**< (ADC_INPUTCTRL) ADC AIN21 Pin */
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#define ADC_INPUTCTRL_MUXPOS_AIN22_Val _U_(0x16) /**< (ADC_INPUTCTRL) ADC AIN22 Pin */
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#define ADC_INPUTCTRL_MUXPOS_AIN23_Val _U_(0x17) /**< (ADC_INPUTCTRL) ADC AIN23 Pin */
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#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U_(0x18) /**< (ADC_INPUTCTRL) 1/4 Scaled Core Supply */
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#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val _U_(0x19) /**< (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply */
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#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U_(0x1A) /**< (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */
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#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U_(0x1B) /**< (ADC_INPUTCTRL) Bandgap Voltage */
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#define ADC_INPUTCTRL_MUXPOS_PTAT_Val _U_(0x1C) /**< (ADC_INPUTCTRL) Temperature Sensor TSENSP */
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#define ADC_INPUTCTRL_MUXPOS_CTAT_Val _U_(0x1D) /**< (ADC_INPUTCTRL) Temperature Sensor TSENSC */
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#define ADC_INPUTCTRL_MUXPOS_DAC_Val _U_(0x1E) /**< (ADC_INPUTCTRL) DAC Output */
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#define ADC_INPUTCTRL_MUXPOS_PTC_Val _U_(0x1F) /**< (ADC_INPUTCTRL) PTC output (only on ADC0) */
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#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN0 Pin Position */
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#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN1 Pin Position */
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#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN2 Pin Position */
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#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN3 Pin Position */
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#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN4 Pin Position */
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#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN5 Pin Position */
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#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN6 Pin Position */
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#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN7 Pin Position */
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#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN8 Pin Position */
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#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN9 Pin Position */
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#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN10 Pin Position */
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#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN11 Pin Position */
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#define ADC_INPUTCTRL_MUXPOS_AIN12 (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN12 Pin Position */
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#define ADC_INPUTCTRL_MUXPOS_AIN13 (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN13 Pin Position */
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#define ADC_INPUTCTRL_MUXPOS_AIN14 (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN14 Pin Position */
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#define ADC_INPUTCTRL_MUXPOS_AIN15 (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN15 Pin Position */
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#define ADC_INPUTCTRL_MUXPOS_AIN16 (ADC_INPUTCTRL_MUXPOS_AIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN16 Pin Position */
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#define ADC_INPUTCTRL_MUXPOS_AIN17 (ADC_INPUTCTRL_MUXPOS_AIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN17 Pin Position */
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#define ADC_INPUTCTRL_MUXPOS_AIN18 (ADC_INPUTCTRL_MUXPOS_AIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN18 Pin Position */
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#define ADC_INPUTCTRL_MUXPOS_AIN19 (ADC_INPUTCTRL_MUXPOS_AIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN19 Pin Position */
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#define ADC_INPUTCTRL_MUXPOS_AIN20 (ADC_INPUTCTRL_MUXPOS_AIN20_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN20 Pin Position */
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#define ADC_INPUTCTRL_MUXPOS_AIN21 (ADC_INPUTCTRL_MUXPOS_AIN21_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN21 Pin Position */
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#define ADC_INPUTCTRL_MUXPOS_AIN22 (ADC_INPUTCTRL_MUXPOS_AIN22_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN22 Pin Position */
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#define ADC_INPUTCTRL_MUXPOS_AIN23 (ADC_INPUTCTRL_MUXPOS_AIN23_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN23 Pin Position */
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#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) 1/4 Scaled Core Supply Position */
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#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT (ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply Position */
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#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) 1/4 Scaled I/O Supply Position */
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#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) Bandgap Voltage Position */
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#define ADC_INPUTCTRL_MUXPOS_PTAT (ADC_INPUTCTRL_MUXPOS_PTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) Temperature Sensor TSENSP Position */
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#define ADC_INPUTCTRL_MUXPOS_CTAT (ADC_INPUTCTRL_MUXPOS_CTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) Temperature Sensor TSENSC Position */
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#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) DAC Output Position */
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#define ADC_INPUTCTRL_MUXPOS_PTC (ADC_INPUTCTRL_MUXPOS_PTC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) PTC output (only on ADC0) Position */
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#define ADC_INPUTCTRL_DIFFMODE_Pos _U_(7) /**< (ADC_INPUTCTRL) Differential Mode Position */
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#define ADC_INPUTCTRL_DIFFMODE_Msk (_U_(0x1) << ADC_INPUTCTRL_DIFFMODE_Pos) /**< (ADC_INPUTCTRL) Differential Mode Mask */
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#define ADC_INPUTCTRL_DIFFMODE(value) (ADC_INPUTCTRL_DIFFMODE_Msk & ((value) << ADC_INPUTCTRL_DIFFMODE_Pos))
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#define ADC_INPUTCTRL_MUXNEG_Pos _U_(8) /**< (ADC_INPUTCTRL) Negative Mux Input Selection Position */
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#define ADC_INPUTCTRL_MUXNEG_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) Negative Mux Input Selection Mask */
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#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos))
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#define ADC_INPUTCTRL_MUXNEG_AIN0_Val _U_(0x0) /**< (ADC_INPUTCTRL) ADC AIN0 Pin */
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#define ADC_INPUTCTRL_MUXNEG_AIN1_Val _U_(0x1) /**< (ADC_INPUTCTRL) ADC AIN1 Pin */
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#define ADC_INPUTCTRL_MUXNEG_AIN2_Val _U_(0x2) /**< (ADC_INPUTCTRL) ADC AIN2 Pin */
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#define ADC_INPUTCTRL_MUXNEG_AIN3_Val _U_(0x3) /**< (ADC_INPUTCTRL) ADC AIN3 Pin */
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#define ADC_INPUTCTRL_MUXNEG_AIN4_Val _U_(0x4) /**< (ADC_INPUTCTRL) ADC AIN4 Pin */
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#define ADC_INPUTCTRL_MUXNEG_AIN5_Val _U_(0x5) /**< (ADC_INPUTCTRL) ADC AIN5 Pin */
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#define ADC_INPUTCTRL_MUXNEG_AIN6_Val _U_(0x6) /**< (ADC_INPUTCTRL) ADC AIN6 Pin */
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#define ADC_INPUTCTRL_MUXNEG_AIN7_Val _U_(0x7) /**< (ADC_INPUTCTRL) ADC AIN7 Pin */
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#define ADC_INPUTCTRL_MUXNEG_GND_Val _U_(0x18) /**< (ADC_INPUTCTRL) Internal Ground */
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#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN0 Pin Position */
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#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN1 Pin Position */
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#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN2 Pin Position */
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#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN3 Pin Position */
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#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN4 Pin Position */
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#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN5 Pin Position */
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#define ADC_INPUTCTRL_MUXNEG_AIN6 (ADC_INPUTCTRL_MUXNEG_AIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN6 Pin Position */
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#define ADC_INPUTCTRL_MUXNEG_AIN7 (ADC_INPUTCTRL_MUXNEG_AIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN7 Pin Position */
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#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) Internal Ground Position */
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#define ADC_INPUTCTRL_DSEQSTOP_Pos _U_(15) /**< (ADC_INPUTCTRL) Stop DMA Sequencing Position */
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#define ADC_INPUTCTRL_DSEQSTOP_Msk (_U_(0x1) << ADC_INPUTCTRL_DSEQSTOP_Pos) /**< (ADC_INPUTCTRL) Stop DMA Sequencing Mask */
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#define ADC_INPUTCTRL_DSEQSTOP(value) (ADC_INPUTCTRL_DSEQSTOP_Msk & ((value) << ADC_INPUTCTRL_DSEQSTOP_Pos))
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#define ADC_INPUTCTRL_Msk _U_(0x9F9F) /**< (ADC_INPUTCTRL) Register Mask */
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/* -------- ADC_CTRLB : (ADC Offset: 0x06) (R/W 16) Control B -------- */
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#define ADC_CTRLB_RESETVALUE _U_(0x00) /**< (ADC_CTRLB) Control B Reset Value */
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#define ADC_CTRLB_LEFTADJ_Pos _U_(0) /**< (ADC_CTRLB) Left-Adjusted Result Position */
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#define ADC_CTRLB_LEFTADJ_Msk (_U_(0x1) << ADC_CTRLB_LEFTADJ_Pos) /**< (ADC_CTRLB) Left-Adjusted Result Mask */
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#define ADC_CTRLB_LEFTADJ(value) (ADC_CTRLB_LEFTADJ_Msk & ((value) << ADC_CTRLB_LEFTADJ_Pos))
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#define ADC_CTRLB_FREERUN_Pos _U_(1) /**< (ADC_CTRLB) Free Running Mode Position */
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#define ADC_CTRLB_FREERUN_Msk (_U_(0x1) << ADC_CTRLB_FREERUN_Pos) /**< (ADC_CTRLB) Free Running Mode Mask */
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#define ADC_CTRLB_FREERUN(value) (ADC_CTRLB_FREERUN_Msk & ((value) << ADC_CTRLB_FREERUN_Pos))
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#define ADC_CTRLB_CORREN_Pos _U_(2) /**< (ADC_CTRLB) Digital Correction Logic Enable Position */
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#define ADC_CTRLB_CORREN_Msk (_U_(0x1) << ADC_CTRLB_CORREN_Pos) /**< (ADC_CTRLB) Digital Correction Logic Enable Mask */
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#define ADC_CTRLB_CORREN(value) (ADC_CTRLB_CORREN_Msk & ((value) << ADC_CTRLB_CORREN_Pos))
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#define ADC_CTRLB_RESSEL_Pos _U_(3) /**< (ADC_CTRLB) Conversion Result Resolution Position */
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#define ADC_CTRLB_RESSEL_Msk (_U_(0x3) << ADC_CTRLB_RESSEL_Pos) /**< (ADC_CTRLB) Conversion Result Resolution Mask */
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#define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos))
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#define ADC_CTRLB_RESSEL_12BIT_Val _U_(0x0) /**< (ADC_CTRLB) 12-bit result */
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#define ADC_CTRLB_RESSEL_16BIT_Val _U_(0x1) /**< (ADC_CTRLB) For averaging mode output */
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#define ADC_CTRLB_RESSEL_10BIT_Val _U_(0x2) /**< (ADC_CTRLB) 10-bit result */
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#define ADC_CTRLB_RESSEL_8BIT_Val _U_(0x3) /**< (ADC_CTRLB) 8-bit result */
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#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos) /**< (ADC_CTRLB) 12-bit result Position */
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#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos) /**< (ADC_CTRLB) For averaging mode output Position */
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#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos) /**< (ADC_CTRLB) 10-bit result Position */
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#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos) /**< (ADC_CTRLB) 8-bit result Position */
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#define ADC_CTRLB_WINMODE_Pos _U_(8) /**< (ADC_CTRLB) Window Monitor Mode Position */
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#define ADC_CTRLB_WINMODE_Msk (_U_(0x7) << ADC_CTRLB_WINMODE_Pos) /**< (ADC_CTRLB) Window Monitor Mode Mask */
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#define ADC_CTRLB_WINMODE(value) (ADC_CTRLB_WINMODE_Msk & ((value) << ADC_CTRLB_WINMODE_Pos))
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#define ADC_CTRLB_WINMODE_DISABLE_Val _U_(0x0) /**< (ADC_CTRLB) No window mode (default) */
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#define ADC_CTRLB_WINMODE_MODE1_Val _U_(0x1) /**< (ADC_CTRLB) RESULT > WINLT */
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#define ADC_CTRLB_WINMODE_MODE2_Val _U_(0x2) /**< (ADC_CTRLB) RESULT < WINUT */
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#define ADC_CTRLB_WINMODE_MODE3_Val _U_(0x3) /**< (ADC_CTRLB) WINLT < RESULT < WINUT */
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#define ADC_CTRLB_WINMODE_MODE4_Val _U_(0x4) /**< (ADC_CTRLB) !(WINLT < RESULT < WINUT) */
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#define ADC_CTRLB_WINMODE_DISABLE (ADC_CTRLB_WINMODE_DISABLE_Val << ADC_CTRLB_WINMODE_Pos) /**< (ADC_CTRLB) No window mode (default) Position */
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#define ADC_CTRLB_WINMODE_MODE1 (ADC_CTRLB_WINMODE_MODE1_Val << ADC_CTRLB_WINMODE_Pos) /**< (ADC_CTRLB) RESULT > WINLT Position */
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#define ADC_CTRLB_WINMODE_MODE2 (ADC_CTRLB_WINMODE_MODE2_Val << ADC_CTRLB_WINMODE_Pos) /**< (ADC_CTRLB) RESULT < WINUT Position */
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#define ADC_CTRLB_WINMODE_MODE3 (ADC_CTRLB_WINMODE_MODE3_Val << ADC_CTRLB_WINMODE_Pos) /**< (ADC_CTRLB) WINLT < RESULT < WINUT Position */
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#define ADC_CTRLB_WINMODE_MODE4 (ADC_CTRLB_WINMODE_MODE4_Val << ADC_CTRLB_WINMODE_Pos) /**< (ADC_CTRLB) !(WINLT < RESULT < WINUT) Position */
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#define ADC_CTRLB_WINSS_Pos _U_(11) /**< (ADC_CTRLB) Window Single Sample Position */
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#define ADC_CTRLB_WINSS_Msk (_U_(0x1) << ADC_CTRLB_WINSS_Pos) /**< (ADC_CTRLB) Window Single Sample Mask */
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#define ADC_CTRLB_WINSS(value) (ADC_CTRLB_WINSS_Msk & ((value) << ADC_CTRLB_WINSS_Pos))
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#define ADC_CTRLB_Msk _U_(0x0F1F) /**< (ADC_CTRLB) Register Mask */
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/* -------- ADC_REFCTRL : (ADC Offset: 0x08) (R/W 8) Reference Control -------- */
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#define ADC_REFCTRL_RESETVALUE _U_(0x00) /**< (ADC_REFCTRL) Reference Control Reset Value */
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#define ADC_REFCTRL_REFSEL_Pos _U_(0) /**< (ADC_REFCTRL) Reference Selection Position */
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#define ADC_REFCTRL_REFSEL_Msk (_U_(0xF) << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) Reference Selection Mask */
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#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos))
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#define ADC_REFCTRL_REFSEL_INTREF_Val _U_(0x0) /**< (ADC_REFCTRL) Internal Bandgap Reference */
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#define ADC_REFCTRL_REFSEL_INTVCC0_Val _U_(0x2) /**< (ADC_REFCTRL) 1/2 VDDANA */
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#define ADC_REFCTRL_REFSEL_INTVCC1_Val _U_(0x3) /**< (ADC_REFCTRL) VDDANA */
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#define ADC_REFCTRL_REFSEL_AREFA_Val _U_(0x4) /**< (ADC_REFCTRL) External Reference A */
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#define ADC_REFCTRL_REFSEL_AREFB_Val _U_(0x5) /**< (ADC_REFCTRL) External Reference B */
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#define ADC_REFCTRL_REFSEL_AREFC_Val _U_(0x6) /**< (ADC_REFCTRL) External Reference C (only on ADC1) */
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#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) Internal Bandgap Reference Position */
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#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) 1/2 VDDANA Position */
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#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) VDDANA Position */
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#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) External Reference A Position */
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#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) External Reference B Position */
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#define ADC_REFCTRL_REFSEL_AREFC (ADC_REFCTRL_REFSEL_AREFC_Val << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) External Reference C (only on ADC1) Position */
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#define ADC_REFCTRL_REFCOMP_Pos _U_(7) /**< (ADC_REFCTRL) Reference Buffer Offset Compensation Enable Position */
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#define ADC_REFCTRL_REFCOMP_Msk (_U_(0x1) << ADC_REFCTRL_REFCOMP_Pos) /**< (ADC_REFCTRL) Reference Buffer Offset Compensation Enable Mask */
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#define ADC_REFCTRL_REFCOMP(value) (ADC_REFCTRL_REFCOMP_Msk & ((value) << ADC_REFCTRL_REFCOMP_Pos))
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#define ADC_REFCTRL_Msk _U_(0x8F) /**< (ADC_REFCTRL) Register Mask */
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/* -------- ADC_AVGCTRL : (ADC Offset: 0x0A) (R/W 8) Average Control -------- */
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#define ADC_AVGCTRL_RESETVALUE _U_(0x00) /**< (ADC_AVGCTRL) Average Control Reset Value */
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#define ADC_AVGCTRL_SAMPLENUM_Pos _U_(0) /**< (ADC_AVGCTRL) Number of Samples to be Collected Position */
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#define ADC_AVGCTRL_SAMPLENUM_Msk (_U_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) Number of Samples to be Collected Mask */
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#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos))
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#define ADC_AVGCTRL_SAMPLENUM_1_Val _U_(0x0) /**< (ADC_AVGCTRL) 1 sample */
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#define ADC_AVGCTRL_SAMPLENUM_2_Val _U_(0x1) /**< (ADC_AVGCTRL) 2 samples */
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#define ADC_AVGCTRL_SAMPLENUM_4_Val _U_(0x2) /**< (ADC_AVGCTRL) 4 samples */
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#define ADC_AVGCTRL_SAMPLENUM_8_Val _U_(0x3) /**< (ADC_AVGCTRL) 8 samples */
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#define ADC_AVGCTRL_SAMPLENUM_16_Val _U_(0x4) /**< (ADC_AVGCTRL) 16 samples */
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#define ADC_AVGCTRL_SAMPLENUM_32_Val _U_(0x5) /**< (ADC_AVGCTRL) 32 samples */
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#define ADC_AVGCTRL_SAMPLENUM_64_Val _U_(0x6) /**< (ADC_AVGCTRL) 64 samples */
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#define ADC_AVGCTRL_SAMPLENUM_128_Val _U_(0x7) /**< (ADC_AVGCTRL) 128 samples */
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#define ADC_AVGCTRL_SAMPLENUM_256_Val _U_(0x8) /**< (ADC_AVGCTRL) 256 samples */
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#define ADC_AVGCTRL_SAMPLENUM_512_Val _U_(0x9) /**< (ADC_AVGCTRL) 512 samples */
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#define ADC_AVGCTRL_SAMPLENUM_1024_Val _U_(0xA) /**< (ADC_AVGCTRL) 1024 samples */
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#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 1 sample Position */
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#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 2 samples Position */
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#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 4 samples Position */
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#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 8 samples Position */
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#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 16 samples Position */
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#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 32 samples Position */
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#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 64 samples Position */
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#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 128 samples Position */
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#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 256 samples Position */
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#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 512 samples Position */
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#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 1024 samples Position */
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#define ADC_AVGCTRL_ADJRES_Pos _U_(4) /**< (ADC_AVGCTRL) Adjusting Result / Division Coefficient Position */
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#define ADC_AVGCTRL_ADJRES_Msk (_U_(0x7) << ADC_AVGCTRL_ADJRES_Pos) /**< (ADC_AVGCTRL) Adjusting Result / Division Coefficient Mask */
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#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos))
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#define ADC_AVGCTRL_Msk _U_(0x7F) /**< (ADC_AVGCTRL) Register Mask */
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/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0B) (R/W 8) Sample Time Control -------- */
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#define ADC_SAMPCTRL_RESETVALUE _U_(0x00) /**< (ADC_SAMPCTRL) Sample Time Control Reset Value */
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#define ADC_SAMPCTRL_SAMPLEN_Pos _U_(0) /**< (ADC_SAMPCTRL) Sampling Time Length Position */
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#define ADC_SAMPCTRL_SAMPLEN_Msk (_U_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos) /**< (ADC_SAMPCTRL) Sampling Time Length Mask */
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#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos))
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#define ADC_SAMPCTRL_OFFCOMP_Pos _U_(7) /**< (ADC_SAMPCTRL) Comparator Offset Compensation Enable Position */
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#define ADC_SAMPCTRL_OFFCOMP_Msk (_U_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos) /**< (ADC_SAMPCTRL) Comparator Offset Compensation Enable Mask */
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#define ADC_SAMPCTRL_OFFCOMP(value) (ADC_SAMPCTRL_OFFCOMP_Msk & ((value) << ADC_SAMPCTRL_OFFCOMP_Pos))
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#define ADC_SAMPCTRL_Msk _U_(0xBF) /**< (ADC_SAMPCTRL) Register Mask */
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/* -------- ADC_WINLT : (ADC Offset: 0x0C) (R/W 16) Window Monitor Lower Threshold -------- */
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#define ADC_WINLT_RESETVALUE _U_(0x00) /**< (ADC_WINLT) Window Monitor Lower Threshold Reset Value */
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#define ADC_WINLT_WINLT_Pos _U_(0) /**< (ADC_WINLT) Window Lower Threshold Position */
|
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|
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#define ADC_WINLT_WINLT_Msk (_U_(0xFFFF) << ADC_WINLT_WINLT_Pos) /**< (ADC_WINLT) Window Lower Threshold Mask */
|
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|
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#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos))
|
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|
|
#define ADC_WINLT_Msk _U_(0xFFFF) /**< (ADC_WINLT) Register Mask */
|
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|
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|
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|
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/* -------- ADC_WINUT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Upper Threshold -------- */
|
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|
|
#define ADC_WINUT_RESETVALUE _U_(0x00) /**< (ADC_WINUT) Window Monitor Upper Threshold Reset Value */
|
||
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|
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|
|
#define ADC_WINUT_WINUT_Pos _U_(0) /**< (ADC_WINUT) Window Upper Threshold Position */
|
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|
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#define ADC_WINUT_WINUT_Msk (_U_(0xFFFF) << ADC_WINUT_WINUT_Pos) /**< (ADC_WINUT) Window Upper Threshold Mask */
|
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|
|
#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos))
|
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|
|
#define ADC_WINUT_Msk _U_(0xFFFF) /**< (ADC_WINUT) Register Mask */
|
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|
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|
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/* -------- ADC_GAINCORR : (ADC Offset: 0x10) (R/W 16) Gain Correction -------- */
|
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|
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#define ADC_GAINCORR_RESETVALUE _U_(0x00) /**< (ADC_GAINCORR) Gain Correction Reset Value */
|
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|
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|
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#define ADC_GAINCORR_GAINCORR_Pos _U_(0) /**< (ADC_GAINCORR) Gain Correction Value Position */
|
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|
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#define ADC_GAINCORR_GAINCORR_Msk (_U_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos) /**< (ADC_GAINCORR) Gain Correction Value Mask */
|
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|
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#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos))
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|
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#define ADC_GAINCORR_Msk _U_(0x0FFF) /**< (ADC_GAINCORR) Register Mask */
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|
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/* -------- ADC_OFFSETCORR : (ADC Offset: 0x12) (R/W 16) Offset Correction -------- */
|
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|
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#define ADC_OFFSETCORR_RESETVALUE _U_(0x00) /**< (ADC_OFFSETCORR) Offset Correction Reset Value */
|
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|
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|
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#define ADC_OFFSETCORR_OFFSETCORR_Pos _U_(0) /**< (ADC_OFFSETCORR) Offset Correction Value Position */
|
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|
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#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos) /**< (ADC_OFFSETCORR) Offset Correction Value Mask */
|
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|
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#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos))
|
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|
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#define ADC_OFFSETCORR_Msk _U_(0x0FFF) /**< (ADC_OFFSETCORR) Register Mask */
|
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/* -------- ADC_SWTRIG : (ADC Offset: 0x14) (R/W 8) Software Trigger -------- */
|
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|
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#define ADC_SWTRIG_RESETVALUE _U_(0x00) /**< (ADC_SWTRIG) Software Trigger Reset Value */
|
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|
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|
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#define ADC_SWTRIG_FLUSH_Pos _U_(0) /**< (ADC_SWTRIG) ADC Conversion Flush Position */
|
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|
|
#define ADC_SWTRIG_FLUSH_Msk (_U_(0x1) << ADC_SWTRIG_FLUSH_Pos) /**< (ADC_SWTRIG) ADC Conversion Flush Mask */
|
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|
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#define ADC_SWTRIG_FLUSH(value) (ADC_SWTRIG_FLUSH_Msk & ((value) << ADC_SWTRIG_FLUSH_Pos))
|
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|
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#define ADC_SWTRIG_START_Pos _U_(1) /**< (ADC_SWTRIG) Start ADC Conversion Position */
|
||
|
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#define ADC_SWTRIG_START_Msk (_U_(0x1) << ADC_SWTRIG_START_Pos) /**< (ADC_SWTRIG) Start ADC Conversion Mask */
|
||
|
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#define ADC_SWTRIG_START(value) (ADC_SWTRIG_START_Msk & ((value) << ADC_SWTRIG_START_Pos))
|
||
|
|
#define ADC_SWTRIG_Msk _U_(0x03) /**< (ADC_SWTRIG) Register Mask */
|
||
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|
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|
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|
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/* -------- ADC_INTENCLR : (ADC Offset: 0x2C) (R/W 8) Interrupt Enable Clear -------- */
|
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|
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#define ADC_INTENCLR_RESETVALUE _U_(0x00) /**< (ADC_INTENCLR) Interrupt Enable Clear Reset Value */
|
||
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|
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|
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#define ADC_INTENCLR_RESRDY_Pos _U_(0) /**< (ADC_INTENCLR) Result Ready Interrupt Disable Position */
|
||
|
|
#define ADC_INTENCLR_RESRDY_Msk (_U_(0x1) << ADC_INTENCLR_RESRDY_Pos) /**< (ADC_INTENCLR) Result Ready Interrupt Disable Mask */
|
||
|
|
#define ADC_INTENCLR_RESRDY(value) (ADC_INTENCLR_RESRDY_Msk & ((value) << ADC_INTENCLR_RESRDY_Pos))
|
||
|
|
#define ADC_INTENCLR_OVERRUN_Pos _U_(1) /**< (ADC_INTENCLR) Overrun Interrupt Disable Position */
|
||
|
|
#define ADC_INTENCLR_OVERRUN_Msk (_U_(0x1) << ADC_INTENCLR_OVERRUN_Pos) /**< (ADC_INTENCLR) Overrun Interrupt Disable Mask */
|
||
|
|
#define ADC_INTENCLR_OVERRUN(value) (ADC_INTENCLR_OVERRUN_Msk & ((value) << ADC_INTENCLR_OVERRUN_Pos))
|
||
|
|
#define ADC_INTENCLR_WINMON_Pos _U_(2) /**< (ADC_INTENCLR) Window Monitor Interrupt Disable Position */
|
||
|
|
#define ADC_INTENCLR_WINMON_Msk (_U_(0x1) << ADC_INTENCLR_WINMON_Pos) /**< (ADC_INTENCLR) Window Monitor Interrupt Disable Mask */
|
||
|
|
#define ADC_INTENCLR_WINMON(value) (ADC_INTENCLR_WINMON_Msk & ((value) << ADC_INTENCLR_WINMON_Pos))
|
||
|
|
#define ADC_INTENCLR_Msk _U_(0x07) /**< (ADC_INTENCLR) Register Mask */
|
||
|
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|
||
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|
||
|
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/* -------- ADC_INTENSET : (ADC Offset: 0x2D) (R/W 8) Interrupt Enable Set -------- */
|
||
|
|
#define ADC_INTENSET_RESETVALUE _U_(0x00) /**< (ADC_INTENSET) Interrupt Enable Set Reset Value */
|
||
|
|
|
||
|
|
#define ADC_INTENSET_RESRDY_Pos _U_(0) /**< (ADC_INTENSET) Result Ready Interrupt Enable Position */
|
||
|
|
#define ADC_INTENSET_RESRDY_Msk (_U_(0x1) << ADC_INTENSET_RESRDY_Pos) /**< (ADC_INTENSET) Result Ready Interrupt Enable Mask */
|
||
|
|
#define ADC_INTENSET_RESRDY(value) (ADC_INTENSET_RESRDY_Msk & ((value) << ADC_INTENSET_RESRDY_Pos))
|
||
|
|
#define ADC_INTENSET_OVERRUN_Pos _U_(1) /**< (ADC_INTENSET) Overrun Interrupt Enable Position */
|
||
|
|
#define ADC_INTENSET_OVERRUN_Msk (_U_(0x1) << ADC_INTENSET_OVERRUN_Pos) /**< (ADC_INTENSET) Overrun Interrupt Enable Mask */
|
||
|
|
#define ADC_INTENSET_OVERRUN(value) (ADC_INTENSET_OVERRUN_Msk & ((value) << ADC_INTENSET_OVERRUN_Pos))
|
||
|
|
#define ADC_INTENSET_WINMON_Pos _U_(2) /**< (ADC_INTENSET) Window Monitor Interrupt Enable Position */
|
||
|
|
#define ADC_INTENSET_WINMON_Msk (_U_(0x1) << ADC_INTENSET_WINMON_Pos) /**< (ADC_INTENSET) Window Monitor Interrupt Enable Mask */
|
||
|
|
#define ADC_INTENSET_WINMON(value) (ADC_INTENSET_WINMON_Msk & ((value) << ADC_INTENSET_WINMON_Pos))
|
||
|
|
#define ADC_INTENSET_Msk _U_(0x07) /**< (ADC_INTENSET) Register Mask */
|
||
|
|
|
||
|
|
|
||
|
|
/* -------- ADC_INTFLAG : (ADC Offset: 0x2E) (R/W 8) Interrupt Flag Status and Clear -------- */
|
||
|
|
#define ADC_INTFLAG_RESETVALUE _U_(0x00) /**< (ADC_INTFLAG) Interrupt Flag Status and Clear Reset Value */
|
||
|
|
|
||
|
|
#define ADC_INTFLAG_RESRDY_Pos _U_(0) /**< (ADC_INTFLAG) Result Ready Interrupt Flag Position */
|
||
|
|
#define ADC_INTFLAG_RESRDY_Msk (_U_(0x1) << ADC_INTFLAG_RESRDY_Pos) /**< (ADC_INTFLAG) Result Ready Interrupt Flag Mask */
|
||
|
|
#define ADC_INTFLAG_RESRDY(value) (ADC_INTFLAG_RESRDY_Msk & ((value) << ADC_INTFLAG_RESRDY_Pos))
|
||
|
|
#define ADC_INTFLAG_OVERRUN_Pos _U_(1) /**< (ADC_INTFLAG) Overrun Interrupt Flag Position */
|
||
|
|
#define ADC_INTFLAG_OVERRUN_Msk (_U_(0x1) << ADC_INTFLAG_OVERRUN_Pos) /**< (ADC_INTFLAG) Overrun Interrupt Flag Mask */
|
||
|
|
#define ADC_INTFLAG_OVERRUN(value) (ADC_INTFLAG_OVERRUN_Msk & ((value) << ADC_INTFLAG_OVERRUN_Pos))
|
||
|
|
#define ADC_INTFLAG_WINMON_Pos _U_(2) /**< (ADC_INTFLAG) Window Monitor Interrupt Flag Position */
|
||
|
|
#define ADC_INTFLAG_WINMON_Msk (_U_(0x1) << ADC_INTFLAG_WINMON_Pos) /**< (ADC_INTFLAG) Window Monitor Interrupt Flag Mask */
|
||
|
|
#define ADC_INTFLAG_WINMON(value) (ADC_INTFLAG_WINMON_Msk & ((value) << ADC_INTFLAG_WINMON_Pos))
|
||
|
|
#define ADC_INTFLAG_Msk _U_(0x07) /**< (ADC_INTFLAG) Register Mask */
|
||
|
|
|
||
|
|
|
||
|
|
/* -------- ADC_STATUS : (ADC Offset: 0x2F) ( R/ 8) Status -------- */
|
||
|
|
#define ADC_STATUS_RESETVALUE _U_(0x00) /**< (ADC_STATUS) Status Reset Value */
|
||
|
|
|
||
|
|
#define ADC_STATUS_ADCBUSY_Pos _U_(0) /**< (ADC_STATUS) ADC Busy Status Position */
|
||
|
|
#define ADC_STATUS_ADCBUSY_Msk (_U_(0x1) << ADC_STATUS_ADCBUSY_Pos) /**< (ADC_STATUS) ADC Busy Status Mask */
|
||
|
|
#define ADC_STATUS_ADCBUSY(value) (ADC_STATUS_ADCBUSY_Msk & ((value) << ADC_STATUS_ADCBUSY_Pos))
|
||
|
|
#define ADC_STATUS_WCC_Pos _U_(2) /**< (ADC_STATUS) Window Comparator Counter Position */
|
||
|
|
#define ADC_STATUS_WCC_Msk (_U_(0x3F) << ADC_STATUS_WCC_Pos) /**< (ADC_STATUS) Window Comparator Counter Mask */
|
||
|
|
#define ADC_STATUS_WCC(value) (ADC_STATUS_WCC_Msk & ((value) << ADC_STATUS_WCC_Pos))
|
||
|
|
#define ADC_STATUS_Msk _U_(0xFD) /**< (ADC_STATUS) Register Mask */
|
||
|
|
|
||
|
|
|
||
|
|
/* -------- ADC_SYNCBUSY : (ADC Offset: 0x30) ( R/ 32) Synchronization Busy -------- */
|
||
|
|
#define ADC_SYNCBUSY_RESETVALUE _U_(0x00) /**< (ADC_SYNCBUSY) Synchronization Busy Reset Value */
|
||
|
|
|
||
|
|
#define ADC_SYNCBUSY_SWRST_Pos _U_(0) /**< (ADC_SYNCBUSY) SWRST Synchronization Busy Position */
|
||
|
|
#define ADC_SYNCBUSY_SWRST_Msk (_U_(0x1) << ADC_SYNCBUSY_SWRST_Pos) /**< (ADC_SYNCBUSY) SWRST Synchronization Busy Mask */
|
||
|
|
#define ADC_SYNCBUSY_SWRST(value) (ADC_SYNCBUSY_SWRST_Msk & ((value) << ADC_SYNCBUSY_SWRST_Pos))
|
||
|
|
#define ADC_SYNCBUSY_ENABLE_Pos _U_(1) /**< (ADC_SYNCBUSY) ENABLE Synchronization Busy Position */
|
||
|
|
#define ADC_SYNCBUSY_ENABLE_Msk (_U_(0x1) << ADC_SYNCBUSY_ENABLE_Pos) /**< (ADC_SYNCBUSY) ENABLE Synchronization Busy Mask */
|
||
|
|
#define ADC_SYNCBUSY_ENABLE(value) (ADC_SYNCBUSY_ENABLE_Msk & ((value) << ADC_SYNCBUSY_ENABLE_Pos))
|
||
|
|
#define ADC_SYNCBUSY_INPUTCTRL_Pos _U_(2) /**< (ADC_SYNCBUSY) Input Control Synchronization Busy Position */
|
||
|
|
#define ADC_SYNCBUSY_INPUTCTRL_Msk (_U_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos) /**< (ADC_SYNCBUSY) Input Control Synchronization Busy Mask */
|
||
|
|
#define ADC_SYNCBUSY_INPUTCTRL(value) (ADC_SYNCBUSY_INPUTCTRL_Msk & ((value) << ADC_SYNCBUSY_INPUTCTRL_Pos))
|
||
|
|
#define ADC_SYNCBUSY_CTRLB_Pos _U_(3) /**< (ADC_SYNCBUSY) Control B Synchronization Busy Position */
|
||
|
|
#define ADC_SYNCBUSY_CTRLB_Msk (_U_(0x1) << ADC_SYNCBUSY_CTRLB_Pos) /**< (ADC_SYNCBUSY) Control B Synchronization Busy Mask */
|
||
|
|
#define ADC_SYNCBUSY_CTRLB(value) (ADC_SYNCBUSY_CTRLB_Msk & ((value) << ADC_SYNCBUSY_CTRLB_Pos))
|
||
|
|
#define ADC_SYNCBUSY_REFCTRL_Pos _U_(4) /**< (ADC_SYNCBUSY) Reference Control Synchronization Busy Position */
|
||
|
|
#define ADC_SYNCBUSY_REFCTRL_Msk (_U_(0x1) << ADC_SYNCBUSY_REFCTRL_Pos) /**< (ADC_SYNCBUSY) Reference Control Synchronization Busy Mask */
|
||
|
|
#define ADC_SYNCBUSY_REFCTRL(value) (ADC_SYNCBUSY_REFCTRL_Msk & ((value) << ADC_SYNCBUSY_REFCTRL_Pos))
|
||
|
|
#define ADC_SYNCBUSY_AVGCTRL_Pos _U_(5) /**< (ADC_SYNCBUSY) Average Control Synchronization Busy Position */
|
||
|
|
#define ADC_SYNCBUSY_AVGCTRL_Msk (_U_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos) /**< (ADC_SYNCBUSY) Average Control Synchronization Busy Mask */
|
||
|
|
#define ADC_SYNCBUSY_AVGCTRL(value) (ADC_SYNCBUSY_AVGCTRL_Msk & ((value) << ADC_SYNCBUSY_AVGCTRL_Pos))
|
||
|
|
#define ADC_SYNCBUSY_SAMPCTRL_Pos _U_(6) /**< (ADC_SYNCBUSY) Sampling Time Control Synchronization Busy Position */
|
||
|
|
#define ADC_SYNCBUSY_SAMPCTRL_Msk (_U_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos) /**< (ADC_SYNCBUSY) Sampling Time Control Synchronization Busy Mask */
|
||
|
|
#define ADC_SYNCBUSY_SAMPCTRL(value) (ADC_SYNCBUSY_SAMPCTRL_Msk & ((value) << ADC_SYNCBUSY_SAMPCTRL_Pos))
|
||
|
|
#define ADC_SYNCBUSY_WINLT_Pos _U_(7) /**< (ADC_SYNCBUSY) Window Monitor Lower Threshold Synchronization Busy Position */
|
||
|
|
#define ADC_SYNCBUSY_WINLT_Msk (_U_(0x1) << ADC_SYNCBUSY_WINLT_Pos) /**< (ADC_SYNCBUSY) Window Monitor Lower Threshold Synchronization Busy Mask */
|
||
|
|
#define ADC_SYNCBUSY_WINLT(value) (ADC_SYNCBUSY_WINLT_Msk & ((value) << ADC_SYNCBUSY_WINLT_Pos))
|
||
|
|
#define ADC_SYNCBUSY_WINUT_Pos _U_(8) /**< (ADC_SYNCBUSY) Window Monitor Upper Threshold Synchronization Busy Position */
|
||
|
|
#define ADC_SYNCBUSY_WINUT_Msk (_U_(0x1) << ADC_SYNCBUSY_WINUT_Pos) /**< (ADC_SYNCBUSY) Window Monitor Upper Threshold Synchronization Busy Mask */
|
||
|
|
#define ADC_SYNCBUSY_WINUT(value) (ADC_SYNCBUSY_WINUT_Msk & ((value) << ADC_SYNCBUSY_WINUT_Pos))
|
||
|
|
#define ADC_SYNCBUSY_GAINCORR_Pos _U_(9) /**< (ADC_SYNCBUSY) Gain Correction Synchronization Busy Position */
|
||
|
|
#define ADC_SYNCBUSY_GAINCORR_Msk (_U_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos) /**< (ADC_SYNCBUSY) Gain Correction Synchronization Busy Mask */
|
||
|
|
#define ADC_SYNCBUSY_GAINCORR(value) (ADC_SYNCBUSY_GAINCORR_Msk & ((value) << ADC_SYNCBUSY_GAINCORR_Pos))
|
||
|
|
#define ADC_SYNCBUSY_OFFSETCORR_Pos _U_(10) /**< (ADC_SYNCBUSY) Offset Correction Synchronization Busy Position */
|
||
|
|
#define ADC_SYNCBUSY_OFFSETCORR_Msk (_U_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos) /**< (ADC_SYNCBUSY) Offset Correction Synchronization Busy Mask */
|
||
|
|
#define ADC_SYNCBUSY_OFFSETCORR(value) (ADC_SYNCBUSY_OFFSETCORR_Msk & ((value) << ADC_SYNCBUSY_OFFSETCORR_Pos))
|
||
|
|
#define ADC_SYNCBUSY_SWTRIG_Pos _U_(11) /**< (ADC_SYNCBUSY) Software Trigger Synchronization Busy Position */
|
||
|
|
#define ADC_SYNCBUSY_SWTRIG_Msk (_U_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos) /**< (ADC_SYNCBUSY) Software Trigger Synchronization Busy Mask */
|
||
|
|
#define ADC_SYNCBUSY_SWTRIG(value) (ADC_SYNCBUSY_SWTRIG_Msk & ((value) << ADC_SYNCBUSY_SWTRIG_Pos))
|
||
|
|
#define ADC_SYNCBUSY_Msk _U_(0x00000FFF) /**< (ADC_SYNCBUSY) Register Mask */
|
||
|
|
|
||
|
|
|
||
|
|
/* -------- ADC_DSEQDATA : (ADC Offset: 0x34) ( /W 32) DMA Sequencial Data -------- */
|
||
|
|
#define ADC_DSEQDATA_RESETVALUE _U_(0x00) /**< (ADC_DSEQDATA) DMA Sequencial Data Reset Value */
|
||
|
|
|
||
|
|
#define ADC_DSEQDATA_DATA_Pos _U_(0) /**< (ADC_DSEQDATA) DMA Sequential Data Position */
|
||
|
|
#define ADC_DSEQDATA_DATA_Msk (_U_(0xFFFFFFFF) << ADC_DSEQDATA_DATA_Pos) /**< (ADC_DSEQDATA) DMA Sequential Data Mask */
|
||
|
|
#define ADC_DSEQDATA_DATA(value) (ADC_DSEQDATA_DATA_Msk & ((value) << ADC_DSEQDATA_DATA_Pos))
|
||
|
|
#define ADC_DSEQDATA_Msk _U_(0xFFFFFFFF) /**< (ADC_DSEQDATA) Register Mask */
|
||
|
|
|
||
|
|
|
||
|
|
/* -------- ADC_DSEQCTRL : (ADC Offset: 0x38) (R/W 32) DMA Sequential Control -------- */
|
||
|
|
#define ADC_DSEQCTRL_RESETVALUE _U_(0x00) /**< (ADC_DSEQCTRL) DMA Sequential Control Reset Value */
|
||
|
|
|
||
|
|
#define ADC_DSEQCTRL_INPUTCTRL_Pos _U_(0) /**< (ADC_DSEQCTRL) Input Control Position */
|
||
|
|
#define ADC_DSEQCTRL_INPUTCTRL_Msk (_U_(0x1) << ADC_DSEQCTRL_INPUTCTRL_Pos) /**< (ADC_DSEQCTRL) Input Control Mask */
|
||
|
|
#define ADC_DSEQCTRL_INPUTCTRL(value) (ADC_DSEQCTRL_INPUTCTRL_Msk & ((value) << ADC_DSEQCTRL_INPUTCTRL_Pos))
|
||
|
|
#define ADC_DSEQCTRL_CTRLB_Pos _U_(1) /**< (ADC_DSEQCTRL) Control B Position */
|
||
|
|
#define ADC_DSEQCTRL_CTRLB_Msk (_U_(0x1) << ADC_DSEQCTRL_CTRLB_Pos) /**< (ADC_DSEQCTRL) Control B Mask */
|
||
|
|
#define ADC_DSEQCTRL_CTRLB(value) (ADC_DSEQCTRL_CTRLB_Msk & ((value) << ADC_DSEQCTRL_CTRLB_Pos))
|
||
|
|
#define ADC_DSEQCTRL_REFCTRL_Pos _U_(2) /**< (ADC_DSEQCTRL) Reference Control Position */
|
||
|
|
#define ADC_DSEQCTRL_REFCTRL_Msk (_U_(0x1) << ADC_DSEQCTRL_REFCTRL_Pos) /**< (ADC_DSEQCTRL) Reference Control Mask */
|
||
|
|
#define ADC_DSEQCTRL_REFCTRL(value) (ADC_DSEQCTRL_REFCTRL_Msk & ((value) << ADC_DSEQCTRL_REFCTRL_Pos))
|
||
|
|
#define ADC_DSEQCTRL_AVGCTRL_Pos _U_(3) /**< (ADC_DSEQCTRL) Average Control Position */
|
||
|
|
#define ADC_DSEQCTRL_AVGCTRL_Msk (_U_(0x1) << ADC_DSEQCTRL_AVGCTRL_Pos) /**< (ADC_DSEQCTRL) Average Control Mask */
|
||
|
|
#define ADC_DSEQCTRL_AVGCTRL(value) (ADC_DSEQCTRL_AVGCTRL_Msk & ((value) << ADC_DSEQCTRL_AVGCTRL_Pos))
|
||
|
|
#define ADC_DSEQCTRL_SAMPCTRL_Pos _U_(4) /**< (ADC_DSEQCTRL) Sampling Time Control Position */
|
||
|
|
#define ADC_DSEQCTRL_SAMPCTRL_Msk (_U_(0x1) << ADC_DSEQCTRL_SAMPCTRL_Pos) /**< (ADC_DSEQCTRL) Sampling Time Control Mask */
|
||
|
|
#define ADC_DSEQCTRL_SAMPCTRL(value) (ADC_DSEQCTRL_SAMPCTRL_Msk & ((value) << ADC_DSEQCTRL_SAMPCTRL_Pos))
|
||
|
|
#define ADC_DSEQCTRL_WINLT_Pos _U_(5) /**< (ADC_DSEQCTRL) Window Monitor Lower Threshold Position */
|
||
|
|
#define ADC_DSEQCTRL_WINLT_Msk (_U_(0x1) << ADC_DSEQCTRL_WINLT_Pos) /**< (ADC_DSEQCTRL) Window Monitor Lower Threshold Mask */
|
||
|
|
#define ADC_DSEQCTRL_WINLT(value) (ADC_DSEQCTRL_WINLT_Msk & ((value) << ADC_DSEQCTRL_WINLT_Pos))
|
||
|
|
#define ADC_DSEQCTRL_WINUT_Pos _U_(6) /**< (ADC_DSEQCTRL) Window Monitor Upper Threshold Position */
|
||
|
|
#define ADC_DSEQCTRL_WINUT_Msk (_U_(0x1) << ADC_DSEQCTRL_WINUT_Pos) /**< (ADC_DSEQCTRL) Window Monitor Upper Threshold Mask */
|
||
|
|
#define ADC_DSEQCTRL_WINUT(value) (ADC_DSEQCTRL_WINUT_Msk & ((value) << ADC_DSEQCTRL_WINUT_Pos))
|
||
|
|
#define ADC_DSEQCTRL_GAINCORR_Pos _U_(7) /**< (ADC_DSEQCTRL) Gain Correction Position */
|
||
|
|
#define ADC_DSEQCTRL_GAINCORR_Msk (_U_(0x1) << ADC_DSEQCTRL_GAINCORR_Pos) /**< (ADC_DSEQCTRL) Gain Correction Mask */
|
||
|
|
#define ADC_DSEQCTRL_GAINCORR(value) (ADC_DSEQCTRL_GAINCORR_Msk & ((value) << ADC_DSEQCTRL_GAINCORR_Pos))
|
||
|
|
#define ADC_DSEQCTRL_OFFSETCORR_Pos _U_(8) /**< (ADC_DSEQCTRL) Offset Correction Position */
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#define ADC_DSEQCTRL_OFFSETCORR_Msk (_U_(0x1) << ADC_DSEQCTRL_OFFSETCORR_Pos) /**< (ADC_DSEQCTRL) Offset Correction Mask */
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#define ADC_DSEQCTRL_OFFSETCORR(value) (ADC_DSEQCTRL_OFFSETCORR_Msk & ((value) << ADC_DSEQCTRL_OFFSETCORR_Pos))
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#define ADC_DSEQCTRL_AUTOSTART_Pos _U_(31) /**< (ADC_DSEQCTRL) ADC Auto-Start Conversion Position */
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#define ADC_DSEQCTRL_AUTOSTART_Msk (_U_(0x1) << ADC_DSEQCTRL_AUTOSTART_Pos) /**< (ADC_DSEQCTRL) ADC Auto-Start Conversion Mask */
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#define ADC_DSEQCTRL_AUTOSTART(value) (ADC_DSEQCTRL_AUTOSTART_Msk & ((value) << ADC_DSEQCTRL_AUTOSTART_Pos))
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#define ADC_DSEQCTRL_Msk _U_(0x800001FF) /**< (ADC_DSEQCTRL) Register Mask */
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/* -------- ADC_DSEQSTAT : (ADC Offset: 0x3C) ( R/ 32) DMA Sequencial Status -------- */
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#define ADC_DSEQSTAT_RESETVALUE _U_(0x00) /**< (ADC_DSEQSTAT) DMA Sequencial Status Reset Value */
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#define ADC_DSEQSTAT_INPUTCTRL_Pos _U_(0) /**< (ADC_DSEQSTAT) Input Control Position */
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#define ADC_DSEQSTAT_INPUTCTRL_Msk (_U_(0x1) << ADC_DSEQSTAT_INPUTCTRL_Pos) /**< (ADC_DSEQSTAT) Input Control Mask */
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#define ADC_DSEQSTAT_INPUTCTRL(value) (ADC_DSEQSTAT_INPUTCTRL_Msk & ((value) << ADC_DSEQSTAT_INPUTCTRL_Pos))
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#define ADC_DSEQSTAT_CTRLB_Pos _U_(1) /**< (ADC_DSEQSTAT) Control B Position */
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#define ADC_DSEQSTAT_CTRLB_Msk (_U_(0x1) << ADC_DSEQSTAT_CTRLB_Pos) /**< (ADC_DSEQSTAT) Control B Mask */
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#define ADC_DSEQSTAT_CTRLB(value) (ADC_DSEQSTAT_CTRLB_Msk & ((value) << ADC_DSEQSTAT_CTRLB_Pos))
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#define ADC_DSEQSTAT_REFCTRL_Pos _U_(2) /**< (ADC_DSEQSTAT) Reference Control Position */
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#define ADC_DSEQSTAT_REFCTRL_Msk (_U_(0x1) << ADC_DSEQSTAT_REFCTRL_Pos) /**< (ADC_DSEQSTAT) Reference Control Mask */
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#define ADC_DSEQSTAT_REFCTRL(value) (ADC_DSEQSTAT_REFCTRL_Msk & ((value) << ADC_DSEQSTAT_REFCTRL_Pos))
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#define ADC_DSEQSTAT_AVGCTRL_Pos _U_(3) /**< (ADC_DSEQSTAT) Average Control Position */
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#define ADC_DSEQSTAT_AVGCTRL_Msk (_U_(0x1) << ADC_DSEQSTAT_AVGCTRL_Pos) /**< (ADC_DSEQSTAT) Average Control Mask */
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#define ADC_DSEQSTAT_AVGCTRL(value) (ADC_DSEQSTAT_AVGCTRL_Msk & ((value) << ADC_DSEQSTAT_AVGCTRL_Pos))
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#define ADC_DSEQSTAT_SAMPCTRL_Pos _U_(4) /**< (ADC_DSEQSTAT) Sampling Time Control Position */
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#define ADC_DSEQSTAT_SAMPCTRL_Msk (_U_(0x1) << ADC_DSEQSTAT_SAMPCTRL_Pos) /**< (ADC_DSEQSTAT) Sampling Time Control Mask */
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#define ADC_DSEQSTAT_SAMPCTRL(value) (ADC_DSEQSTAT_SAMPCTRL_Msk & ((value) << ADC_DSEQSTAT_SAMPCTRL_Pos))
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#define ADC_DSEQSTAT_WINLT_Pos _U_(5) /**< (ADC_DSEQSTAT) Window Monitor Lower Threshold Position */
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#define ADC_DSEQSTAT_WINLT_Msk (_U_(0x1) << ADC_DSEQSTAT_WINLT_Pos) /**< (ADC_DSEQSTAT) Window Monitor Lower Threshold Mask */
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#define ADC_DSEQSTAT_WINLT(value) (ADC_DSEQSTAT_WINLT_Msk & ((value) << ADC_DSEQSTAT_WINLT_Pos))
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#define ADC_DSEQSTAT_WINUT_Pos _U_(6) /**< (ADC_DSEQSTAT) Window Monitor Upper Threshold Position */
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#define ADC_DSEQSTAT_WINUT_Msk (_U_(0x1) << ADC_DSEQSTAT_WINUT_Pos) /**< (ADC_DSEQSTAT) Window Monitor Upper Threshold Mask */
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#define ADC_DSEQSTAT_WINUT(value) (ADC_DSEQSTAT_WINUT_Msk & ((value) << ADC_DSEQSTAT_WINUT_Pos))
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#define ADC_DSEQSTAT_GAINCORR_Pos _U_(7) /**< (ADC_DSEQSTAT) Gain Correction Position */
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#define ADC_DSEQSTAT_GAINCORR_Msk (_U_(0x1) << ADC_DSEQSTAT_GAINCORR_Pos) /**< (ADC_DSEQSTAT) Gain Correction Mask */
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#define ADC_DSEQSTAT_GAINCORR(value) (ADC_DSEQSTAT_GAINCORR_Msk & ((value) << ADC_DSEQSTAT_GAINCORR_Pos))
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#define ADC_DSEQSTAT_OFFSETCORR_Pos _U_(8) /**< (ADC_DSEQSTAT) Offset Correction Position */
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#define ADC_DSEQSTAT_OFFSETCORR_Msk (_U_(0x1) << ADC_DSEQSTAT_OFFSETCORR_Pos) /**< (ADC_DSEQSTAT) Offset Correction Mask */
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#define ADC_DSEQSTAT_OFFSETCORR(value) (ADC_DSEQSTAT_OFFSETCORR_Msk & ((value) << ADC_DSEQSTAT_OFFSETCORR_Pos))
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#define ADC_DSEQSTAT_BUSY_Pos _U_(31) /**< (ADC_DSEQSTAT) DMA Sequencing Busy Position */
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#define ADC_DSEQSTAT_BUSY_Msk (_U_(0x1) << ADC_DSEQSTAT_BUSY_Pos) /**< (ADC_DSEQSTAT) DMA Sequencing Busy Mask */
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#define ADC_DSEQSTAT_BUSY(value) (ADC_DSEQSTAT_BUSY_Msk & ((value) << ADC_DSEQSTAT_BUSY_Pos))
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#define ADC_DSEQSTAT_Msk _U_(0x800001FF) /**< (ADC_DSEQSTAT) Register Mask */
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/* -------- ADC_RESULT : (ADC Offset: 0x40) ( R/ 16) Result Conversion Value -------- */
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#define ADC_RESULT_RESETVALUE _U_(0x00) /**< (ADC_RESULT) Result Conversion Value Reset Value */
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#define ADC_RESULT_RESULT_Pos _U_(0) /**< (ADC_RESULT) Result Conversion Value Position */
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#define ADC_RESULT_RESULT_Msk (_U_(0xFFFF) << ADC_RESULT_RESULT_Pos) /**< (ADC_RESULT) Result Conversion Value Mask */
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#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos))
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#define ADC_RESULT_Msk _U_(0xFFFF) /**< (ADC_RESULT) Register Mask */
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/* -------- ADC_RESS : (ADC Offset: 0x44) ( R/ 16) Last Sample Result -------- */
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#define ADC_RESS_RESETVALUE _U_(0x00) /**< (ADC_RESS) Last Sample Result Reset Value */
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#define ADC_RESS_RESS_Pos _U_(0) /**< (ADC_RESS) Last ADC conversion result Position */
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#define ADC_RESS_RESS_Msk (_U_(0xFFFF) << ADC_RESS_RESS_Pos) /**< (ADC_RESS) Last ADC conversion result Mask */
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#define ADC_RESS_RESS(value) (ADC_RESS_RESS_Msk & ((value) << ADC_RESS_RESS_Pos))
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#define ADC_RESS_Msk _U_(0xFFFF) /**< (ADC_RESS) Register Mask */
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/* -------- ADC_CALIB : (ADC Offset: 0x48) (R/W 16) Calibration -------- */
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#define ADC_CALIB_RESETVALUE _U_(0x00) /**< (ADC_CALIB) Calibration Reset Value */
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#define ADC_CALIB_BIASCOMP_Pos _U_(0) /**< (ADC_CALIB) Bias Comparator Scaling Position */
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#define ADC_CALIB_BIASCOMP_Msk (_U_(0x7) << ADC_CALIB_BIASCOMP_Pos) /**< (ADC_CALIB) Bias Comparator Scaling Mask */
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#define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos))
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#define ADC_CALIB_BIASR2R_Pos _U_(4) /**< (ADC_CALIB) Bias R2R Ampli scaling Position */
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#define ADC_CALIB_BIASR2R_Msk (_U_(0x7) << ADC_CALIB_BIASR2R_Pos) /**< (ADC_CALIB) Bias R2R Ampli scaling Mask */
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#define ADC_CALIB_BIASR2R(value) (ADC_CALIB_BIASR2R_Msk & ((value) << ADC_CALIB_BIASR2R_Pos))
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#define ADC_CALIB_BIASREFBUF_Pos _U_(8) /**< (ADC_CALIB) Bias Reference Buffer Scaling Position */
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#define ADC_CALIB_BIASREFBUF_Msk (_U_(0x7) << ADC_CALIB_BIASREFBUF_Pos) /**< (ADC_CALIB) Bias Reference Buffer Scaling Mask */
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#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos))
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#define ADC_CALIB_Msk _U_(0x0777) /**< (ADC_CALIB) Register Mask */
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/** \brief ADC register offsets definitions */
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#define ADC_CTRLA_REG_OFST (0x00) /**< (ADC_CTRLA) Control A Offset */
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#define ADC_EVCTRL_REG_OFST (0x02) /**< (ADC_EVCTRL) Event Control Offset */
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#define ADC_DBGCTRL_REG_OFST (0x03) /**< (ADC_DBGCTRL) Debug Control Offset */
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#define ADC_INPUTCTRL_REG_OFST (0x04) /**< (ADC_INPUTCTRL) Input Control Offset */
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#define ADC_CTRLB_REG_OFST (0x06) /**< (ADC_CTRLB) Control B Offset */
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#define ADC_REFCTRL_REG_OFST (0x08) /**< (ADC_REFCTRL) Reference Control Offset */
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#define ADC_AVGCTRL_REG_OFST (0x0A) /**< (ADC_AVGCTRL) Average Control Offset */
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#define ADC_SAMPCTRL_REG_OFST (0x0B) /**< (ADC_SAMPCTRL) Sample Time Control Offset */
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#define ADC_WINLT_REG_OFST (0x0C) /**< (ADC_WINLT) Window Monitor Lower Threshold Offset */
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#define ADC_WINUT_REG_OFST (0x0E) /**< (ADC_WINUT) Window Monitor Upper Threshold Offset */
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#define ADC_GAINCORR_REG_OFST (0x10) /**< (ADC_GAINCORR) Gain Correction Offset */
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#define ADC_OFFSETCORR_REG_OFST (0x12) /**< (ADC_OFFSETCORR) Offset Correction Offset */
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#define ADC_SWTRIG_REG_OFST (0x14) /**< (ADC_SWTRIG) Software Trigger Offset */
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#define ADC_INTENCLR_REG_OFST (0x2C) /**< (ADC_INTENCLR) Interrupt Enable Clear Offset */
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#define ADC_INTENSET_REG_OFST (0x2D) /**< (ADC_INTENSET) Interrupt Enable Set Offset */
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#define ADC_INTFLAG_REG_OFST (0x2E) /**< (ADC_INTFLAG) Interrupt Flag Status and Clear Offset */
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#define ADC_STATUS_REG_OFST (0x2F) /**< (ADC_STATUS) Status Offset */
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#define ADC_SYNCBUSY_REG_OFST (0x30) /**< (ADC_SYNCBUSY) Synchronization Busy Offset */
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#define ADC_DSEQDATA_REG_OFST (0x34) /**< (ADC_DSEQDATA) DMA Sequencial Data Offset */
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#define ADC_DSEQCTRL_REG_OFST (0x38) /**< (ADC_DSEQCTRL) DMA Sequential Control Offset */
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#define ADC_DSEQSTAT_REG_OFST (0x3C) /**< (ADC_DSEQSTAT) DMA Sequencial Status Offset */
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#define ADC_RESULT_REG_OFST (0x40) /**< (ADC_RESULT) Result Conversion Value Offset */
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#define ADC_RESS_REG_OFST (0x44) /**< (ADC_RESS) Last Sample Result Offset */
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#define ADC_CALIB_REG_OFST (0x48) /**< (ADC_CALIB) Calibration Offset */
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#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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/** \brief ADC register API structure */
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typedef struct
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{ /* Analog Digital Converter */
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__IO uint16_t ADC_CTRLA; /**< Offset: 0x00 (R/W 16) Control A */
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__IO uint8_t ADC_EVCTRL; /**< Offset: 0x02 (R/W 8) Event Control */
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__IO uint8_t ADC_DBGCTRL; /**< Offset: 0x03 (R/W 8) Debug Control */
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__IO uint16_t ADC_INPUTCTRL; /**< Offset: 0x04 (R/W 16) Input Control */
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__IO uint16_t ADC_CTRLB; /**< Offset: 0x06 (R/W 16) Control B */
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__IO uint8_t ADC_REFCTRL; /**< Offset: 0x08 (R/W 8) Reference Control */
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__I uint8_t Reserved1[0x01];
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__IO uint8_t ADC_AVGCTRL; /**< Offset: 0x0A (R/W 8) Average Control */
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__IO uint8_t ADC_SAMPCTRL; /**< Offset: 0x0B (R/W 8) Sample Time Control */
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__IO uint16_t ADC_WINLT; /**< Offset: 0x0C (R/W 16) Window Monitor Lower Threshold */
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__IO uint16_t ADC_WINUT; /**< Offset: 0x0E (R/W 16) Window Monitor Upper Threshold */
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__IO uint16_t ADC_GAINCORR; /**< Offset: 0x10 (R/W 16) Gain Correction */
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__IO uint16_t ADC_OFFSETCORR; /**< Offset: 0x12 (R/W 16) Offset Correction */
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__IO uint8_t ADC_SWTRIG; /**< Offset: 0x14 (R/W 8) Software Trigger */
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__I uint8_t Reserved2[0x17];
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__IO uint8_t ADC_INTENCLR; /**< Offset: 0x2C (R/W 8) Interrupt Enable Clear */
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__IO uint8_t ADC_INTENSET; /**< Offset: 0x2D (R/W 8) Interrupt Enable Set */
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__IO uint8_t ADC_INTFLAG; /**< Offset: 0x2E (R/W 8) Interrupt Flag Status and Clear */
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__I uint8_t ADC_STATUS; /**< Offset: 0x2F (R/ 8) Status */
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__I uint32_t ADC_SYNCBUSY; /**< Offset: 0x30 (R/ 32) Synchronization Busy */
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__O uint32_t ADC_DSEQDATA; /**< Offset: 0x34 ( /W 32) DMA Sequencial Data */
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__IO uint32_t ADC_DSEQCTRL; /**< Offset: 0x38 (R/W 32) DMA Sequential Control */
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__I uint32_t ADC_DSEQSTAT; /**< Offset: 0x3C (R/ 32) DMA Sequencial Status */
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__I uint16_t ADC_RESULT; /**< Offset: 0x40 (R/ 16) Result Conversion Value */
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__I uint8_t Reserved3[0x02];
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__I uint16_t ADC_RESS; /**< Offset: 0x44 (R/ 16) Last Sample Result */
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__I uint8_t Reserved4[0x02];
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__IO uint16_t ADC_CALIB; /**< Offset: 0x48 (R/W 16) Calibration */
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} adc_registers_t;
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#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAME54_ADC_COMPONENT_H_ */
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