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151 lines
12 KiB
C
151 lines
12 KiB
C
4 years ago
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/**
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* \brief Component description for FREQM
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*
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* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
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*
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* Subject to your compliance with these terms, you may use Microchip software and any derivatives
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* exclusively with Microchip products. It is your responsibility to comply with third party license
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* terms applicable to your use of third party software (including open source software) that may
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* accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
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* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
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* FITNESS FOR A PARTICULAR PURPOSE.
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*
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* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
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* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
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* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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*/
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/* file generated from device description version 2020-09-28T13:45:00Z */
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#ifndef _SAMD51_FREQM_COMPONENT_H_
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#define _SAMD51_FREQM_COMPONENT_H_
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/* ************************************************************************** */
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/* SOFTWARE API DEFINITION FOR FREQM */
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/* ************************************************************************** */
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/* -------- FREQM_CTRLA : (FREQM Offset: 0x00) (R/W 8) Control A Register -------- */
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#define FREQM_CTRLA_RESETVALUE _U_(0x00) /**< (FREQM_CTRLA) Control A Register Reset Value */
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#define FREQM_CTRLA_SWRST_Pos _U_(0) /**< (FREQM_CTRLA) Software Reset Position */
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#define FREQM_CTRLA_SWRST_Msk (_U_(0x1) << FREQM_CTRLA_SWRST_Pos) /**< (FREQM_CTRLA) Software Reset Mask */
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#define FREQM_CTRLA_SWRST(value) (FREQM_CTRLA_SWRST_Msk & ((value) << FREQM_CTRLA_SWRST_Pos))
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#define FREQM_CTRLA_ENABLE_Pos _U_(1) /**< (FREQM_CTRLA) Enable Position */
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#define FREQM_CTRLA_ENABLE_Msk (_U_(0x1) << FREQM_CTRLA_ENABLE_Pos) /**< (FREQM_CTRLA) Enable Mask */
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#define FREQM_CTRLA_ENABLE(value) (FREQM_CTRLA_ENABLE_Msk & ((value) << FREQM_CTRLA_ENABLE_Pos))
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#define FREQM_CTRLA_Msk _U_(0x03) /**< (FREQM_CTRLA) Register Mask */
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/* -------- FREQM_CTRLB : (FREQM Offset: 0x01) ( /W 8) Control B Register -------- */
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#define FREQM_CTRLB_RESETVALUE _U_(0x00) /**< (FREQM_CTRLB) Control B Register Reset Value */
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#define FREQM_CTRLB_START_Pos _U_(0) /**< (FREQM_CTRLB) Start Measurement Position */
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#define FREQM_CTRLB_START_Msk (_U_(0x1) << FREQM_CTRLB_START_Pos) /**< (FREQM_CTRLB) Start Measurement Mask */
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#define FREQM_CTRLB_START(value) (FREQM_CTRLB_START_Msk & ((value) << FREQM_CTRLB_START_Pos))
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#define FREQM_CTRLB_Msk _U_(0x01) /**< (FREQM_CTRLB) Register Mask */
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/* -------- FREQM_CFGA : (FREQM Offset: 0x02) (R/W 16) Config A register -------- */
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#define FREQM_CFGA_RESETVALUE _U_(0x00) /**< (FREQM_CFGA) Config A register Reset Value */
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#define FREQM_CFGA_REFNUM_Pos _U_(0) /**< (FREQM_CFGA) Number of Reference Clock Cycles Position */
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#define FREQM_CFGA_REFNUM_Msk (_U_(0xFF) << FREQM_CFGA_REFNUM_Pos) /**< (FREQM_CFGA) Number of Reference Clock Cycles Mask */
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#define FREQM_CFGA_REFNUM(value) (FREQM_CFGA_REFNUM_Msk & ((value) << FREQM_CFGA_REFNUM_Pos))
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#define FREQM_CFGA_Msk _U_(0x00FF) /**< (FREQM_CFGA) Register Mask */
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/* -------- FREQM_INTENCLR : (FREQM Offset: 0x08) (R/W 8) Interrupt Enable Clear Register -------- */
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#define FREQM_INTENCLR_RESETVALUE _U_(0x00) /**< (FREQM_INTENCLR) Interrupt Enable Clear Register Reset Value */
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#define FREQM_INTENCLR_DONE_Pos _U_(0) /**< (FREQM_INTENCLR) Measurement Done Interrupt Enable Position */
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#define FREQM_INTENCLR_DONE_Msk (_U_(0x1) << FREQM_INTENCLR_DONE_Pos) /**< (FREQM_INTENCLR) Measurement Done Interrupt Enable Mask */
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#define FREQM_INTENCLR_DONE(value) (FREQM_INTENCLR_DONE_Msk & ((value) << FREQM_INTENCLR_DONE_Pos))
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#define FREQM_INTENCLR_Msk _U_(0x01) /**< (FREQM_INTENCLR) Register Mask */
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/* -------- FREQM_INTENSET : (FREQM Offset: 0x09) (R/W 8) Interrupt Enable Set Register -------- */
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#define FREQM_INTENSET_RESETVALUE _U_(0x00) /**< (FREQM_INTENSET) Interrupt Enable Set Register Reset Value */
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#define FREQM_INTENSET_DONE_Pos _U_(0) /**< (FREQM_INTENSET) Measurement Done Interrupt Enable Position */
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#define FREQM_INTENSET_DONE_Msk (_U_(0x1) << FREQM_INTENSET_DONE_Pos) /**< (FREQM_INTENSET) Measurement Done Interrupt Enable Mask */
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#define FREQM_INTENSET_DONE(value) (FREQM_INTENSET_DONE_Msk & ((value) << FREQM_INTENSET_DONE_Pos))
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#define FREQM_INTENSET_Msk _U_(0x01) /**< (FREQM_INTENSET) Register Mask */
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/* -------- FREQM_INTFLAG : (FREQM Offset: 0x0A) (R/W 8) Interrupt Flag Register -------- */
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#define FREQM_INTFLAG_RESETVALUE _U_(0x00) /**< (FREQM_INTFLAG) Interrupt Flag Register Reset Value */
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#define FREQM_INTFLAG_DONE_Pos _U_(0) /**< (FREQM_INTFLAG) Measurement Done Position */
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#define FREQM_INTFLAG_DONE_Msk (_U_(0x1) << FREQM_INTFLAG_DONE_Pos) /**< (FREQM_INTFLAG) Measurement Done Mask */
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#define FREQM_INTFLAG_DONE(value) (FREQM_INTFLAG_DONE_Msk & ((value) << FREQM_INTFLAG_DONE_Pos))
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#define FREQM_INTFLAG_Msk _U_(0x01) /**< (FREQM_INTFLAG) Register Mask */
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/* -------- FREQM_STATUS : (FREQM Offset: 0x0B) (R/W 8) Status Register -------- */
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#define FREQM_STATUS_RESETVALUE _U_(0x00) /**< (FREQM_STATUS) Status Register Reset Value */
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#define FREQM_STATUS_BUSY_Pos _U_(0) /**< (FREQM_STATUS) FREQM Status Position */
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#define FREQM_STATUS_BUSY_Msk (_U_(0x1) << FREQM_STATUS_BUSY_Pos) /**< (FREQM_STATUS) FREQM Status Mask */
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#define FREQM_STATUS_BUSY(value) (FREQM_STATUS_BUSY_Msk & ((value) << FREQM_STATUS_BUSY_Pos))
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#define FREQM_STATUS_OVF_Pos _U_(1) /**< (FREQM_STATUS) Sticky Count Value Overflow Position */
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#define FREQM_STATUS_OVF_Msk (_U_(0x1) << FREQM_STATUS_OVF_Pos) /**< (FREQM_STATUS) Sticky Count Value Overflow Mask */
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#define FREQM_STATUS_OVF(value) (FREQM_STATUS_OVF_Msk & ((value) << FREQM_STATUS_OVF_Pos))
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#define FREQM_STATUS_Msk _U_(0x03) /**< (FREQM_STATUS) Register Mask */
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/* -------- FREQM_SYNCBUSY : (FREQM Offset: 0x0C) ( R/ 32) Synchronization Busy Register -------- */
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#define FREQM_SYNCBUSY_RESETVALUE _U_(0x00) /**< (FREQM_SYNCBUSY) Synchronization Busy Register Reset Value */
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#define FREQM_SYNCBUSY_SWRST_Pos _U_(0) /**< (FREQM_SYNCBUSY) Software Reset Position */
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#define FREQM_SYNCBUSY_SWRST_Msk (_U_(0x1) << FREQM_SYNCBUSY_SWRST_Pos) /**< (FREQM_SYNCBUSY) Software Reset Mask */
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#define FREQM_SYNCBUSY_SWRST(value) (FREQM_SYNCBUSY_SWRST_Msk & ((value) << FREQM_SYNCBUSY_SWRST_Pos))
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#define FREQM_SYNCBUSY_ENABLE_Pos _U_(1) /**< (FREQM_SYNCBUSY) Enable Position */
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#define FREQM_SYNCBUSY_ENABLE_Msk (_U_(0x1) << FREQM_SYNCBUSY_ENABLE_Pos) /**< (FREQM_SYNCBUSY) Enable Mask */
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#define FREQM_SYNCBUSY_ENABLE(value) (FREQM_SYNCBUSY_ENABLE_Msk & ((value) << FREQM_SYNCBUSY_ENABLE_Pos))
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#define FREQM_SYNCBUSY_Msk _U_(0x00000003) /**< (FREQM_SYNCBUSY) Register Mask */
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/* -------- FREQM_VALUE : (FREQM Offset: 0x10) ( R/ 32) Count Value Register -------- */
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#define FREQM_VALUE_RESETVALUE _U_(0x00) /**< (FREQM_VALUE) Count Value Register Reset Value */
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#define FREQM_VALUE_VALUE_Pos _U_(0) /**< (FREQM_VALUE) Measurement Value Position */
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#define FREQM_VALUE_VALUE_Msk (_U_(0xFFFFFF) << FREQM_VALUE_VALUE_Pos) /**< (FREQM_VALUE) Measurement Value Mask */
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#define FREQM_VALUE_VALUE(value) (FREQM_VALUE_VALUE_Msk & ((value) << FREQM_VALUE_VALUE_Pos))
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#define FREQM_VALUE_Msk _U_(0x00FFFFFF) /**< (FREQM_VALUE) Register Mask */
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/** \brief FREQM register offsets definitions */
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#define FREQM_CTRLA_REG_OFST (0x00) /**< (FREQM_CTRLA) Control A Register Offset */
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#define FREQM_CTRLB_REG_OFST (0x01) /**< (FREQM_CTRLB) Control B Register Offset */
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#define FREQM_CFGA_REG_OFST (0x02) /**< (FREQM_CFGA) Config A register Offset */
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#define FREQM_INTENCLR_REG_OFST (0x08) /**< (FREQM_INTENCLR) Interrupt Enable Clear Register Offset */
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#define FREQM_INTENSET_REG_OFST (0x09) /**< (FREQM_INTENSET) Interrupt Enable Set Register Offset */
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#define FREQM_INTFLAG_REG_OFST (0x0A) /**< (FREQM_INTFLAG) Interrupt Flag Register Offset */
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#define FREQM_STATUS_REG_OFST (0x0B) /**< (FREQM_STATUS) Status Register Offset */
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#define FREQM_SYNCBUSY_REG_OFST (0x0C) /**< (FREQM_SYNCBUSY) Synchronization Busy Register Offset */
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#define FREQM_VALUE_REG_OFST (0x10) /**< (FREQM_VALUE) Count Value Register Offset */
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#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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/** \brief FREQM register API structure */
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typedef struct
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{ /* Frequency Meter */
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__IO uint8_t FREQM_CTRLA; /**< Offset: 0x00 (R/W 8) Control A Register */
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__O uint8_t FREQM_CTRLB; /**< Offset: 0x01 ( /W 8) Control B Register */
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__IO uint16_t FREQM_CFGA; /**< Offset: 0x02 (R/W 16) Config A register */
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__I uint8_t Reserved1[0x04];
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__IO uint8_t FREQM_INTENCLR; /**< Offset: 0x08 (R/W 8) Interrupt Enable Clear Register */
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__IO uint8_t FREQM_INTENSET; /**< Offset: 0x09 (R/W 8) Interrupt Enable Set Register */
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__IO uint8_t FREQM_INTFLAG; /**< Offset: 0x0A (R/W 8) Interrupt Flag Register */
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__IO uint8_t FREQM_STATUS; /**< Offset: 0x0B (R/W 8) Status Register */
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__I uint32_t FREQM_SYNCBUSY; /**< Offset: 0x0C (R/ 32) Synchronization Busy Register */
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__I uint32_t FREQM_VALUE; /**< Offset: 0x10 (R/ 32) Count Value Register */
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} freqm_registers_t;
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#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAMD51_FREQM_COMPONENT_H_ */
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