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108 lines
5.5 KiB
HTML
108 lines
5.5 KiB
HTML
4 years ago
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<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
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<html>
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<!-- Copyright (C) 1988-2019 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.3 or
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any later version published by the Free Software Foundation; with the
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Invariant Sections being "Free Software" and "Free Software Needs
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Free Documentation", with the Front-Cover Texts being "A GNU Manual,"
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and with the Back-Cover Texts as in (a) below.
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(a) The FSF's Back-Cover Text is: "You are free to copy and modify
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this GNU Manual. Buying copies from GNU Press supports the FSF in
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developing GNU and promoting software freedom." -->
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<!-- Created by GNU Texinfo 6.4, http://www.gnu.org/software/texinfo/ -->
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<head>
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<title>RISC-V Features (Debugging with GDB)</title>
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<meta name="description" content="RISC-V Features (Debugging with GDB)">
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<meta name="keywords" content="RISC-V Features (Debugging with GDB)">
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<meta name="distribution" content="global">
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<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
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<link href="index.html#Top" rel="start" title="Top">
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<link href="Concept-Index.html#Concept-Index" rel="index" title="Concept Index">
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<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">
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<link href="Standard-Target-Features.html#Standard-Target-Features" rel="up" title="Standard Target Features">
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<link href="S_002f390-and-System-z-Features.html#S_002f390-and-System-z-Features" rel="next" title="S/390 and System z Features">
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<link href="PowerPC-Features.html#PowerPC-Features" rel="prev" title="PowerPC Features">
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</head>
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<body lang="en">
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<a name="RISC_002dV-Features"></a>
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<div class="header">
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<p>
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Next: <a href="S_002f390-and-System-z-Features.html#S_002f390-and-System-z-Features" accesskey="n" rel="next">S/390 and System z Features</a>, Previous: <a href="PowerPC-Features.html#PowerPC-Features" accesskey="p" rel="prev">PowerPC Features</a>, Up: <a href="Standard-Target-Features.html#Standard-Target-Features" accesskey="u" rel="up">Standard Target Features</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Concept-Index.html#Concept-Index" title="Index" rel="index">Index</a>]</p>
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</div>
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<hr>
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<a name="RISC_002dV-Features-1"></a>
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<h4 class="subsection">G.5.12 RISC-V Features</h4>
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<a name="index-target-descriptions_002c-RISC_002dV-Features"></a>
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<p>The ‘<samp>org.gnu.gdb.riscv.cpu</samp>’ feature is required for RISC-V
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targets. It should contain the registers ‘<samp>x0</samp>’ through
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‘<samp>x31</samp>’, and ‘<samp>pc</samp>’. Either the architectural names (‘<samp>x0</samp>’,
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‘<samp>x1</samp>’, etc) can be used, or the ABI names (‘<samp>zero</samp>’, ‘<samp>ra</samp>’,
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etc).
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</p>
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<p>The ‘<samp>org.gnu.gdb.riscv.fpu</samp>’ feature is optional. If present, it
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should contain registers ‘<samp>f0</samp>’ through ‘<samp>f31</samp>’, ‘<samp>fflags</samp>’,
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‘<samp>frm</samp>’, and ‘<samp>fcsr</samp>’. As with the cpu feature, either the
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architectural register names, or the ABI names can be used.
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</p>
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<p>The ‘<samp>org.gnu.gdb.riscv.virtual</samp>’ feature is optional. If present,
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it should contain registers that are not backed by real registers on
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the target, but are instead virtual, where the register value is
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derived from other target state. In many ways these are like
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<small>GDB</small>s pseudo-registers, except implemented by the target.
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Currently the only register expected in this set is the one byte
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‘<samp>priv</samp>’ register that contains the target’s privilege level in the
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least significant two bits.
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</p>
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<p>The ‘<samp>org.gnu.gdb.riscv.csr</samp>’ feature is optional. If present, it
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should contain all of the target’s standard CSRs. Standard CSRs are
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those defined in the RISC-V specification documents. There is some
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overlap between this feature and the fpu feature; the ‘<samp>fflags</samp>’,
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‘<samp>frm</samp>’, and ‘<samp>fcsr</samp>’ registers could be in either feature. The
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expectation is that these registers will be in the fpu feature if the
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target has floating point hardware, but can be moved into the csr
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feature if the target has the floating point control registers, but no
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other floating point hardware.
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</p>
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</body>
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</html>
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