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<a name="MIPS-Register-Packet-Format"></a>
<h4 class="subsubsection">E.5.2.1 <acronym>MIPS</acronym> Register Packet Format</h4>
<a name="index-register-packet-format_002c-MIPS"></a>
<p>The following <code>g</code>/<code>G</code> packets have previously been defined.
In the below, some thirty-two bit registers are transferred as
sixty-four bits. Those registers should be zero/sign extended (which?)
to fill the space allocated. Register bytes are transferred in target
byte order. The two nibbles within a register byte are transferred
most-significant &ndash; least-significant.
</p>
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<dt><span class="roman">MIPS32</span></dt>
<dd><p>All registers are transferred as thirty-two bit quantities in the order:
32 general-purpose; sr; lo; hi; bad; cause; pc; 32 floating-point
registers; fsr; fir; fp.
</p>
</dd>
<dt><span class="roman">MIPS64</span></dt>
<dd><p>All registers are transferred as sixty-four bit quantities (including
thirty-two bit registers such as <code>sr</code>). The ordering is the same
as <code>MIPS32</code>.
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