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318 lines
15 KiB
HTML
318 lines
15 KiB
HTML
4 years ago
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<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
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<html>
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<!-- Copyright (C) 1988-2018 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.3 or
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any later version published by the Free Software Foundation; with the
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Invariant Sections being "Funding Free Software", the Front-Cover
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Texts being (a) (see below), and with the Back-Cover Texts being (b)
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(see below). A copy of the license is included in the section entitled
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"GNU Free Documentation License".
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(a) The FSF's Front-Cover Text is:
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A GNU Manual
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(b) The FSF's Back-Cover Text is:
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You have freedom to copy and modify this GNU Manual, like GNU
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software. Copies published by the Free Software Foundation raise
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funds for GNU development. -->
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<!-- Created by GNU Texinfo 6.4, http://www.gnu.org/software/texinfo/ -->
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<head>
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<title>Insn Splitting (GNU Compiler Collection (GCC) Internals)</title>
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<meta name="description" content="Insn Splitting (GNU Compiler Collection (GCC) Internals)">
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<meta name="keywords" content="Insn Splitting (GNU Compiler Collection (GCC) Internals)">
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<meta name="resource-type" content="document">
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<meta name="distribution" content="global">
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<meta name="Generator" content="makeinfo">
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<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
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<link href="index.html#Top" rel="start" title="Top">
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<link href="Option-Index.html#Option-Index" rel="index" title="Option Index">
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<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">
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<link href="Machine-Desc.html#Machine-Desc" rel="up" title="Machine Desc">
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<link href="Including-Patterns.html#Including-Patterns" rel="next" title="Including Patterns">
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<link href="Expander-Definitions.html#Expander-Definitions" rel="prev" title="Expander Definitions">
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<style type="text/css">
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<!--
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a.summary-letter {text-decoration: none}
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div.example {margin-left: 3.2em}
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kbd {font-style: oblique}
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pre.smallformat {font-family: inherit; font-size: smaller}
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pre.smalllisp {font-size: smaller}
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span.nolinebreak {white-space: nowrap}
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ul.no-bullet {list-style: none}
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-->
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</style>
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</head>
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<body lang="en">
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<a name="Insn-Splitting"></a>
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<div class="header">
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<p>
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Next: <a href="Including-Patterns.html#Including-Patterns" accesskey="n" rel="next">Including Patterns</a>, Previous: <a href="Expander-Definitions.html#Expander-Definitions" accesskey="p" rel="prev">Expander Definitions</a>, Up: <a href="Machine-Desc.html#Machine-Desc" accesskey="u" rel="up">Machine Desc</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
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</div>
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<hr>
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<a name="Defining-How-to-Split-Instructions"></a>
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<h3 class="section">17.16 Defining How to Split Instructions</h3>
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<a name="index-insn-splitting"></a>
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<a name="index-instruction-splitting"></a>
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<a name="index-splitting-instructions"></a>
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<p>There are two cases where you should specify how to split a pattern
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into multiple insns. On machines that have instructions requiring
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delay slots (see <a href="Delay-Slots.html#Delay-Slots">Delay Slots</a>) or that have instructions whose
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output is not available for multiple cycles (see <a href="Processor-pipeline-description.html#Processor-pipeline-description">Processor pipeline description</a>), the compiler phases that optimize these cases need to
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be able to move insns into one-instruction delay slots. However, some
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insns may generate more than one machine instruction. These insns
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cannot be placed into a delay slot.
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</p>
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<p>Often you can rewrite the single insn as a list of individual insns,
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each corresponding to one machine instruction. The disadvantage of
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doing so is that it will cause the compilation to be slower and require
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more space. If the resulting insns are too complex, it may also
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suppress some optimizations. The compiler splits the insn if there is a
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reason to believe that it might improve instruction or delay slot
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scheduling.
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</p>
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<p>The insn combiner phase also splits putative insns. If three insns are
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merged into one insn with a complex expression that cannot be matched by
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some <code>define_insn</code> pattern, the combiner phase attempts to split
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the complex pattern into two insns that are recognized. Usually it can
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break the complex pattern into two patterns by splitting out some
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subexpression. However, in some other cases, such as performing an
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addition of a large constant in two insns on a RISC machine, the way to
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split the addition into two insns is machine-dependent.
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</p>
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<a name="index-define_005fsplit"></a>
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<p>The <code>define_split</code> definition tells the compiler how to split a
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complex insn into several simpler insns. It looks like this:
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</p>
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<div class="smallexample">
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<pre class="smallexample">(define_split
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[<var>insn-pattern</var>]
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"<var>condition</var>"
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[<var>new-insn-pattern-1</var>
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<var>new-insn-pattern-2</var>
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…]
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"<var>preparation-statements</var>")
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</pre></div>
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<p><var>insn-pattern</var> is a pattern that needs to be split and
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<var>condition</var> is the final condition to be tested, as in a
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<code>define_insn</code>. When an insn matching <var>insn-pattern</var> and
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satisfying <var>condition</var> is found, it is replaced in the insn list
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with the insns given by <var>new-insn-pattern-1</var>,
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<var>new-insn-pattern-2</var>, etc.
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</p>
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<p>The <var>preparation-statements</var> are similar to those statements that
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are specified for <code>define_expand</code> (see <a href="Expander-Definitions.html#Expander-Definitions">Expander Definitions</a>)
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and are executed before the new RTL is generated to prepare for the
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generated code or emit some insns whose pattern is not fixed. Unlike
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those in <code>define_expand</code>, however, these statements must not
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generate any new pseudo-registers. Once reload has completed, they also
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must not allocate any space in the stack frame.
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</p>
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<p>Patterns are matched against <var>insn-pattern</var> in two different
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circumstances. If an insn needs to be split for delay slot scheduling
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or insn scheduling, the insn is already known to be valid, which means
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that it must have been matched by some <code>define_insn</code> and, if
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<code>reload_completed</code> is nonzero, is known to satisfy the constraints
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of that <code>define_insn</code>. In that case, the new insn patterns must
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also be insns that are matched by some <code>define_insn</code> and, if
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<code>reload_completed</code> is nonzero, must also satisfy the constraints
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of those definitions.
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</p>
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<p>As an example of this usage of <code>define_split</code>, consider the following
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example from <samp>a29k.md</samp>, which splits a <code>sign_extend</code> from
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<code>HImode</code> to <code>SImode</code> into a pair of shift insns:
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</p>
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<div class="smallexample">
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<pre class="smallexample">(define_split
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[(set (match_operand:SI 0 "gen_reg_operand" "")
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(sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
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""
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[(set (match_dup 0)
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(ashift:SI (match_dup 1)
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(const_int 16)))
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(set (match_dup 0)
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(ashiftrt:SI (match_dup 0)
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(const_int 16)))]
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"
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{ operands[1] = gen_lowpart (SImode, operands[1]); }")
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</pre></div>
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<p>When the combiner phase tries to split an insn pattern, it is always the
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case that the pattern is <em>not</em> matched by any <code>define_insn</code>.
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The combiner pass first tries to split a single <code>set</code> expression
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and then the same <code>set</code> expression inside a <code>parallel</code>, but
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followed by a <code>clobber</code> of a pseudo-reg to use as a scratch
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register. In these cases, the combiner expects exactly two new insn
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patterns to be generated. It will verify that these patterns match some
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<code>define_insn</code> definitions, so you need not do this test in the
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<code>define_split</code> (of course, there is no point in writing a
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<code>define_split</code> that will never produce insns that match).
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</p>
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<p>Here is an example of this use of <code>define_split</code>, taken from
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<samp>rs6000.md</samp>:
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</p>
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<div class="smallexample">
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<pre class="smallexample">(define_split
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[(set (match_operand:SI 0 "gen_reg_operand" "")
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(plus:SI (match_operand:SI 1 "gen_reg_operand" "")
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(match_operand:SI 2 "non_add_cint_operand" "")))]
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""
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[(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
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(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
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"
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{
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int low = INTVAL (operands[2]) & 0xffff;
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int high = (unsigned) INTVAL (operands[2]) >> 16;
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if (low & 0x8000)
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high++, low |= 0xffff0000;
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operands[3] = GEN_INT (high << 16);
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operands[4] = GEN_INT (low);
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}")
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</pre></div>
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<p>Here the predicate <code>non_add_cint_operand</code> matches any
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<code>const_int</code> that is <em>not</em> a valid operand of a single add
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insn. The add with the smaller displacement is written so that it
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can be substituted into the address of a subsequent operation.
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</p>
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<p>An example that uses a scratch register, from the same file, generates
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an equality comparison of a register and a large constant:
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</p>
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<div class="smallexample">
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<pre class="smallexample">(define_split
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[(set (match_operand:CC 0 "cc_reg_operand" "")
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(compare:CC (match_operand:SI 1 "gen_reg_operand" "")
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(match_operand:SI 2 "non_short_cint_operand" "")))
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(clobber (match_operand:SI 3 "gen_reg_operand" ""))]
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"find_single_use (operands[0], insn, 0)
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&& (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
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|| GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
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[(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
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(set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
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"
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{
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/* <span class="roman">Get the constant we are comparing against, C, and see what it
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looks like sign-extended to 16 bits. Then see what constant
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could be XOR’ed with C to get the sign-extended value.</span> */
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int c = INTVAL (operands[2]);
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int sextc = (c << 16) >> 16;
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int xorv = c ^ sextc;
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operands[4] = GEN_INT (xorv);
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operands[5] = GEN_INT (sextc);
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}")
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</pre></div>
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<p>To avoid confusion, don’t write a single <code>define_split</code> that
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accepts some insns that match some <code>define_insn</code> as well as some
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insns that don’t. Instead, write two separate <code>define_split</code>
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definitions, one for the insns that are valid and one for the insns that
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are not valid.
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</p>
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<p>The splitter is allowed to split jump instructions into sequence of
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jumps or create new jumps in while splitting non-jump instructions. As
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the control flow graph and branch prediction information needs to be updated,
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several restriction apply.
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</p>
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<p>Splitting of jump instruction into sequence that over by another jump
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instruction is always valid, as compiler expect identical behavior of new
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jump. When new sequence contains multiple jump instructions or new labels,
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more assistance is needed. Splitter is required to create only unconditional
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jumps, or simple conditional jump instructions. Additionally it must attach a
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<code>REG_BR_PROB</code> note to each conditional jump. A global variable
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<code>split_branch_probability</code> holds the probability of the original branch in case
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it was a simple conditional jump, -1 otherwise. To simplify
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recomputing of edge frequencies, the new sequence is required to have only
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forward jumps to the newly created labels.
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</p>
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<a name="index-define_005finsn_005fand_005fsplit"></a>
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<p>For the common case where the pattern of a define_split exactly matches the
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pattern of a define_insn, use <code>define_insn_and_split</code>. It looks like
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this:
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</p>
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<div class="smallexample">
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<pre class="smallexample">(define_insn_and_split
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[<var>insn-pattern</var>]
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"<var>condition</var>"
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"<var>output-template</var>"
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"<var>split-condition</var>"
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[<var>new-insn-pattern-1</var>
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<var>new-insn-pattern-2</var>
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…]
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"<var>preparation-statements</var>"
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[<var>insn-attributes</var>])
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</pre></div>
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<p><var>insn-pattern</var>, <var>condition</var>, <var>output-template</var>, and
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<var>insn-attributes</var> are used as in <code>define_insn</code>. The
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<var>new-insn-pattern</var> vector and the <var>preparation-statements</var> are used as
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in a <code>define_split</code>. The <var>split-condition</var> is also used as in
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<code>define_split</code>, with the additional behavior that if the condition starts
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with ‘<samp>&&</samp>’, the condition used for the split will be the constructed as a
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logical “and” of the split condition with the insn condition. For example,
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from i386.md:
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</p>
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<div class="smallexample">
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<pre class="smallexample">(define_insn_and_split "zero_extendhisi2_and"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
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(clobber (reg:CC 17))]
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"TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
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"#"
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"&& reload_completed"
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[(parallel [(set (match_dup 0)
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(and:SI (match_dup 0) (const_int 65535)))
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(clobber (reg:CC 17))])]
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""
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[(set_attr "type" "alu1")])
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</pre></div>
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<p>In this case, the actual split condition will be
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‘<samp>TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed</samp>’.
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</p>
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<p>The <code>define_insn_and_split</code> construction provides exactly the same
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functionality as two separate <code>define_insn</code> and <code>define_split</code>
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patterns. It exists for compactness, and as a maintenance tool to prevent
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having to ensure the two patterns’ templates match.
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</p>
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<hr>
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<div class="header">
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<p>
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Next: <a href="Including-Patterns.html#Including-Patterns" accesskey="n" rel="next">Including Patterns</a>, Previous: <a href="Expander-Definitions.html#Expander-Definitions" accesskey="p" rel="prev">Expander Definitions</a>, Up: <a href="Machine-Desc.html#Machine-Desc" accesskey="u" rel="up">Machine Desc</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
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</body>
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