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160 lines
7.7 KiB
HTML
160 lines
7.7 KiB
HTML
4 years ago
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<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
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<html>
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<!-- Copyright (C) 1988-2018 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.3 or
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any later version published by the Free Software Foundation; with the
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Invariant Sections being "Funding Free Software", the Front-Cover
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Texts being (a) (see below), and with the Back-Cover Texts being (b)
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(see below). A copy of the license is included in the section entitled
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"GNU Free Documentation License".
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(a) The FSF's Front-Cover Text is:
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A GNU Manual
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(b) The FSF's Back-Cover Text is:
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You have freedom to copy and modify this GNU Manual, like GNU
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software. Copies published by the Free Software Foundation raise
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funds for GNU development. -->
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<!-- Created by GNU Texinfo 6.4, http://www.gnu.org/software/texinfo/ -->
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<head>
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<title>Delay Slots (GNU Compiler Collection (GCC) Internals)</title>
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<meta name="description" content="Delay Slots (GNU Compiler Collection (GCC) Internals)">
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<meta name="keywords" content="Delay Slots (GNU Compiler Collection (GCC) Internals)">
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<meta name="resource-type" content="document">
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<meta name="distribution" content="global">
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<meta name="Generator" content="makeinfo">
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<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
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<link href="index.html#Top" rel="start" title="Top">
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<link href="Option-Index.html#Option-Index" rel="index" title="Option Index">
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<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">
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<link href="Insn-Attributes.html#Insn-Attributes" rel="up" title="Insn Attributes">
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<link href="Processor-pipeline-description.html#Processor-pipeline-description" rel="next" title="Processor pipeline description">
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<link href="Mnemonic-Attribute.html#Mnemonic-Attribute" rel="prev" title="Mnemonic Attribute">
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</style>
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</head>
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<body lang="en">
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<a name="Delay-Slots"></a>
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<div class="header">
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<p>
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Next: <a href="Processor-pipeline-description.html#Processor-pipeline-description" accesskey="n" rel="next">Processor pipeline description</a>, Previous: <a href="Mnemonic-Attribute.html#Mnemonic-Attribute" accesskey="p" rel="prev">Mnemonic Attribute</a>, Up: <a href="Insn-Attributes.html#Insn-Attributes" accesskey="u" rel="up">Insn Attributes</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
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</div>
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<hr>
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<a name="Delay-Slot-Scheduling"></a>
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<h4 class="subsection">17.19.8 Delay Slot Scheduling</h4>
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<a name="index-delay-slots_002c-defining"></a>
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<p>The insn attribute mechanism can be used to specify the requirements for
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delay slots, if any, on a target machine. An instruction is said to
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require a <em>delay slot</em> if some instructions that are physically
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after the instruction are executed as if they were located before it.
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Classic examples are branch and call instructions, which often execute
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the following instruction before the branch or call is performed.
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</p>
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<p>On some machines, conditional branch instructions can optionally
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<em>annul</em> instructions in the delay slot. This means that the
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instruction will not be executed for certain branch outcomes. Both
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instructions that annul if the branch is true and instructions that
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annul if the branch is false are supported.
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</p>
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<p>Delay slot scheduling differs from instruction scheduling in that
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determining whether an instruction needs a delay slot is dependent only
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on the type of instruction being generated, not on data flow between the
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instructions. See the next section for a discussion of data-dependent
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instruction scheduling.
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</p>
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<a name="index-define_005fdelay"></a>
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<p>The requirement of an insn needing one or more delay slots is indicated
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via the <code>define_delay</code> expression. It has the following form:
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</p>
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<div class="smallexample">
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<pre class="smallexample">(define_delay <var>test</var>
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[<var>delay-1</var> <var>annul-true-1</var> <var>annul-false-1</var>
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<var>delay-2</var> <var>annul-true-2</var> <var>annul-false-2</var>
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…])
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</pre></div>
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<p><var>test</var> is an attribute test that indicates whether this
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<code>define_delay</code> applies to a particular insn. If so, the number of
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required delay slots is determined by the length of the vector specified
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as the second argument. An insn placed in delay slot <var>n</var> must
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satisfy attribute test <var>delay-n</var>. <var>annul-true-n</var> is an
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attribute test that specifies which insns may be annulled if the branch
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is true. Similarly, <var>annul-false-n</var> specifies which insns in the
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delay slot may be annulled if the branch is false. If annulling is not
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supported for that delay slot, <code>(nil)</code> should be coded.
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</p>
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<p>For example, in the common case where branch and call insns require
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a single delay slot, which may contain any insn other than a branch or
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call, the following would be placed in the <samp>md</samp> file:
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</p>
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<div class="smallexample">
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<pre class="smallexample">(define_delay (eq_attr "type" "branch,call")
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[(eq_attr "type" "!branch,call") (nil) (nil)])
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</pre></div>
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<p>Multiple <code>define_delay</code> expressions may be specified. In this
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case, each such expression specifies different delay slot requirements
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and there must be no insn for which tests in two <code>define_delay</code>
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expressions are both true.
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</p>
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<p>For example, if we have a machine that requires one delay slot for branches
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but two for calls, no delay slot can contain a branch or call insn,
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and any valid insn in the delay slot for the branch can be annulled if the
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branch is true, we might represent this as follows:
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</p>
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<div class="smallexample">
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<pre class="smallexample">(define_delay (eq_attr "type" "branch")
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[(eq_attr "type" "!branch,call")
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(eq_attr "type" "!branch,call")
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(nil)])
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(define_delay (eq_attr "type" "call")
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[(eq_attr "type" "!branch,call") (nil) (nil)
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(eq_attr "type" "!branch,call") (nil) (nil)])
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</pre></div>
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<hr>
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<div class="header">
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<p>
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Next: <a href="Processor-pipeline-description.html#Processor-pipeline-description" accesskey="n" rel="next">Processor pipeline description</a>, Previous: <a href="Mnemonic-Attribute.html#Mnemonic-Attribute" accesskey="p" rel="prev">Mnemonic Attribute</a>, Up: <a href="Insn-Attributes.html#Insn-Attributes" accesskey="u" rel="up">Insn Attributes</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
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</div>
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</body>
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</html>
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