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605 lines
24 KiB
HTML
605 lines
24 KiB
HTML
4 years ago
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<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
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<html>
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<!-- Copyright (C) 1988-2018 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.3 or
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any later version published by the Free Software Foundation; with the
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Invariant Sections being "Funding Free Software", the Front-Cover
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Texts being (a) (see below), and with the Back-Cover Texts being (b)
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(see below). A copy of the license is included in the section entitled
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"GNU Free Documentation License".
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(a) The FSF's Front-Cover Text is:
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A GNU Manual
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(b) The FSF's Back-Cover Text is:
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You have freedom to copy and modify this GNU Manual, like GNU
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software. Copies published by the Free Software Foundation raise
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funds for GNU development. -->
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<!-- Created by GNU Texinfo 6.4, http://www.gnu.org/software/texinfo/ -->
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<head>
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<title>SH Options (Using the GNU Compiler Collection (GCC))</title>
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<meta name="description" content="SH Options (Using the GNU Compiler Collection (GCC))">
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<meta name="keywords" content="SH Options (Using the GNU Compiler Collection (GCC))">
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<meta name="resource-type" content="document">
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<meta name="distribution" content="global">
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<meta name="Generator" content="makeinfo">
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<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
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<link href="index.html#Top" rel="start" title="Top">
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<link href="Option-Index.html#Option-Index" rel="index" title="Option Index">
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<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">
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<link href="Submodel-Options.html#Submodel-Options" rel="up" title="Submodel Options">
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<link href="Solaris-2-Options.html#Solaris-2-Options" rel="next" title="Solaris 2 Options">
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<link href="Score-Options.html#Score-Options" rel="prev" title="Score Options">
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<style type="text/css">
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<!--
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a.summary-letter {text-decoration: none}
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blockquote.indentedblock {margin-right: 0em}
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blockquote.smallindentedblock {margin-right: 0em; font-size: smaller}
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blockquote.smallquotation {font-size: smaller}
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div.display {margin-left: 3.2em}
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div.example {margin-left: 3.2em}
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div.lisp {margin-left: 3.2em}
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div.smalldisplay {margin-left: 3.2em}
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div.smallexample {margin-left: 3.2em}
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div.smalllisp {margin-left: 3.2em}
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kbd {font-style: oblique}
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pre.display {font-family: inherit}
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pre.format {font-family: inherit}
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pre.menu-comment {font-family: serif}
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pre.menu-preformatted {font-family: serif}
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pre.smalldisplay {font-family: inherit; font-size: smaller}
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pre.smallexample {font-size: smaller}
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pre.smallformat {font-family: inherit; font-size: smaller}
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pre.smalllisp {font-size: smaller}
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span.nolinebreak {white-space: nowrap}
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span.roman {font-family: initial; font-weight: normal}
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span.sansserif {font-family: sans-serif; font-weight: normal}
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ul.no-bullet {list-style: none}
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-->
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</style>
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</head>
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<body lang="en">
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<a name="SH-Options"></a>
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<div class="header">
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<p>
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Next: <a href="Solaris-2-Options.html#Solaris-2-Options" accesskey="n" rel="next">Solaris 2 Options</a>, Previous: <a href="Score-Options.html#Score-Options" accesskey="p" rel="prev">Score Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
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</div>
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<hr>
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<a name="SH-Options-1"></a>
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<h4 class="subsection">3.18.44 SH Options</h4>
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<p>These ‘<samp>-m</samp>’ options are defined for the SH implementations:
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</p>
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<dl compact="compact">
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<dt><code>-m1</code></dt>
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<dd><a name="index-m1"></a>
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<p>Generate code for the SH1.
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</p>
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</dd>
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<dt><code>-m2</code></dt>
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<dd><a name="index-m2"></a>
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<p>Generate code for the SH2.
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</p>
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</dd>
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<dt><code>-m2e</code></dt>
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<dd><p>Generate code for the SH2e.
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</p>
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</dd>
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<dt><code>-m2a-nofpu</code></dt>
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<dd><a name="index-m2a_002dnofpu"></a>
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<p>Generate code for the SH2a without FPU, or for a SH2a-FPU in such a way
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that the floating-point unit is not used.
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</p>
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</dd>
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<dt><code>-m2a-single-only</code></dt>
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<dd><a name="index-m2a_002dsingle_002donly"></a>
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<p>Generate code for the SH2a-FPU, in such a way that no double-precision
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floating-point operations are used.
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</p>
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</dd>
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<dt><code>-m2a-single</code></dt>
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<dd><a name="index-m2a_002dsingle"></a>
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<p>Generate code for the SH2a-FPU assuming the floating-point unit is in
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single-precision mode by default.
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</p>
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</dd>
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<dt><code>-m2a</code></dt>
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<dd><a name="index-m2a"></a>
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<p>Generate code for the SH2a-FPU assuming the floating-point unit is in
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double-precision mode by default.
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</p>
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</dd>
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<dt><code>-m3</code></dt>
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<dd><a name="index-m3"></a>
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<p>Generate code for the SH3.
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</p>
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</dd>
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<dt><code>-m3e</code></dt>
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<dd><a name="index-m3e"></a>
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<p>Generate code for the SH3e.
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</p>
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</dd>
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<dt><code>-m4-nofpu</code></dt>
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<dd><a name="index-m4_002dnofpu"></a>
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<p>Generate code for the SH4 without a floating-point unit.
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</p>
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</dd>
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<dt><code>-m4-single-only</code></dt>
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<dd><a name="index-m4_002dsingle_002donly"></a>
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<p>Generate code for the SH4 with a floating-point unit that only
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supports single-precision arithmetic.
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</p>
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</dd>
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<dt><code>-m4-single</code></dt>
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<dd><a name="index-m4_002dsingle"></a>
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<p>Generate code for the SH4 assuming the floating-point unit is in
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single-precision mode by default.
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</p>
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</dd>
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<dt><code>-m4</code></dt>
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<dd><a name="index-m4"></a>
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<p>Generate code for the SH4.
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</p>
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</dd>
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<dt><code>-m4-100</code></dt>
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<dd><a name="index-m4_002d100"></a>
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<p>Generate code for SH4-100.
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</p>
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</dd>
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<dt><code>-m4-100-nofpu</code></dt>
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<dd><a name="index-m4_002d100_002dnofpu"></a>
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<p>Generate code for SH4-100 in such a way that the
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floating-point unit is not used.
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</p>
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</dd>
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<dt><code>-m4-100-single</code></dt>
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<dd><a name="index-m4_002d100_002dsingle"></a>
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<p>Generate code for SH4-100 assuming the floating-point unit is in
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single-precision mode by default.
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</p>
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</dd>
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<dt><code>-m4-100-single-only</code></dt>
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<dd><a name="index-m4_002d100_002dsingle_002donly"></a>
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<p>Generate code for SH4-100 in such a way that no double-precision
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floating-point operations are used.
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</p>
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</dd>
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<dt><code>-m4-200</code></dt>
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<dd><a name="index-m4_002d200"></a>
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<p>Generate code for SH4-200.
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</p>
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</dd>
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<dt><code>-m4-200-nofpu</code></dt>
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<dd><a name="index-m4_002d200_002dnofpu"></a>
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<p>Generate code for SH4-200 without in such a way that the
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floating-point unit is not used.
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</p>
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</dd>
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<dt><code>-m4-200-single</code></dt>
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<dd><a name="index-m4_002d200_002dsingle"></a>
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<p>Generate code for SH4-200 assuming the floating-point unit is in
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single-precision mode by default.
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</p>
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</dd>
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<dt><code>-m4-200-single-only</code></dt>
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<dd><a name="index-m4_002d200_002dsingle_002donly"></a>
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<p>Generate code for SH4-200 in such a way that no double-precision
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floating-point operations are used.
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</p>
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</dd>
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<dt><code>-m4-300</code></dt>
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<dd><a name="index-m4_002d300"></a>
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<p>Generate code for SH4-300.
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</p>
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</dd>
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<dt><code>-m4-300-nofpu</code></dt>
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<dd><a name="index-m4_002d300_002dnofpu"></a>
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<p>Generate code for SH4-300 without in such a way that the
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floating-point unit is not used.
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</p>
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</dd>
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<dt><code>-m4-300-single</code></dt>
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<dd><a name="index-m4_002d300_002dsingle"></a>
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<p>Generate code for SH4-300 in such a way that no double-precision
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floating-point operations are used.
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</p>
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</dd>
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<dt><code>-m4-300-single-only</code></dt>
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<dd><a name="index-m4_002d300_002dsingle_002donly"></a>
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<p>Generate code for SH4-300 in such a way that no double-precision
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floating-point operations are used.
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</p>
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</dd>
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<dt><code>-m4-340</code></dt>
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<dd><a name="index-m4_002d340"></a>
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<p>Generate code for SH4-340 (no MMU, no FPU).
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</p>
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</dd>
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<dt><code>-m4-500</code></dt>
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<dd><a name="index-m4_002d500"></a>
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<p>Generate code for SH4-500 (no FPU). Passes <samp>-isa=sh4-nofpu</samp> to the
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assembler.
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</p>
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</dd>
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<dt><code>-m4a-nofpu</code></dt>
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<dd><a name="index-m4a_002dnofpu"></a>
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<p>Generate code for the SH4al-dsp, or for a SH4a in such a way that the
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floating-point unit is not used.
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</p>
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</dd>
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<dt><code>-m4a-single-only</code></dt>
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<dd><a name="index-m4a_002dsingle_002donly"></a>
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<p>Generate code for the SH4a, in such a way that no double-precision
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floating-point operations are used.
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</p>
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</dd>
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<dt><code>-m4a-single</code></dt>
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<dd><a name="index-m4a_002dsingle"></a>
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<p>Generate code for the SH4a assuming the floating-point unit is in
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single-precision mode by default.
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</p>
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</dd>
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<dt><code>-m4a</code></dt>
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<dd><a name="index-m4a"></a>
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<p>Generate code for the SH4a.
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</p>
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</dd>
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<dt><code>-m4al</code></dt>
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<dd><a name="index-m4al"></a>
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<p>Same as <samp>-m4a-nofpu</samp>, except that it implicitly passes
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<samp>-dsp</samp> to the assembler. GCC doesn’t generate any DSP
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instructions at the moment.
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</p>
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</dd>
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<dt><code>-mb</code></dt>
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<dd><a name="index-mb"></a>
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<p>Compile code for the processor in big-endian mode.
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</p>
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</dd>
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<dt><code>-ml</code></dt>
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<dd><a name="index-ml-1"></a>
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<p>Compile code for the processor in little-endian mode.
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</p>
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</dd>
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<dt><code>-mdalign</code></dt>
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<dd><a name="index-mdalign"></a>
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<p>Align doubles at 64-bit boundaries. Note that this changes the calling
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conventions, and thus some functions from the standard C library do
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not work unless you recompile it first with <samp>-mdalign</samp>.
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</p>
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</dd>
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<dt><code>-mrelax</code></dt>
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<dd><a name="index-mrelax-6"></a>
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<p>Shorten some address references at link time, when possible; uses the
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linker option <samp>-relax</samp>.
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</p>
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</dd>
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<dt><code>-mbigtable</code></dt>
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<dd><a name="index-mbigtable"></a>
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<p>Use 32-bit offsets in <code>switch</code> tables. The default is to use
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16-bit offsets.
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</p>
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</dd>
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<dt><code>-mbitops</code></dt>
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<dd><a name="index-mbitops-1"></a>
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<p>Enable the use of bit manipulation instructions on SH2A.
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</p>
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</dd>
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<dt><code>-mfmovd</code></dt>
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<dd><a name="index-mfmovd"></a>
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<p>Enable the use of the instruction <code>fmovd</code>. Check <samp>-mdalign</samp> for
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alignment constraints.
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</p>
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</dd>
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<dt><code>-mrenesas</code></dt>
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<dd><a name="index-mrenesas"></a>
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<p>Comply with the calling conventions defined by Renesas.
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</p>
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</dd>
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<dt><code>-mno-renesas</code></dt>
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<dd><a name="index-mno_002drenesas"></a>
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<p>Comply with the calling conventions defined for GCC before the Renesas
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conventions were available. This option is the default for all
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targets of the SH toolchain.
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</p>
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</dd>
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<dt><code>-mnomacsave</code></dt>
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<dd><a name="index-mnomacsave"></a>
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<p>Mark the <code>MAC</code> register as call-clobbered, even if
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<samp>-mrenesas</samp> is given.
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</p>
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|
</dd>
|
||
|
|
<dt><code>-mieee</code></dt>
|
||
|
|
<dt><code>-mno-ieee</code></dt>
|
||
|
|
<dd><a name="index-mieee-1"></a>
|
||
|
|
<a name="index-mno_002dieee"></a>
|
||
|
|
<p>Control the IEEE compliance of floating-point comparisons, which affects the
|
||
|
|
handling of cases where the result of a comparison is unordered. By default
|
||
|
|
<samp>-mieee</samp> is implicitly enabled. If <samp>-ffinite-math-only</samp> is
|
||
|
|
enabled <samp>-mno-ieee</samp> is implicitly set, which results in faster
|
||
|
|
floating-point greater-equal and less-equal comparisons. The implicit settings
|
||
|
|
can be overridden by specifying either <samp>-mieee</samp> or <samp>-mno-ieee</samp>.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-minline-ic_invalidate</code></dt>
|
||
|
|
<dd><a name="index-minline_002dic_005finvalidate"></a>
|
||
|
|
<p>Inline code to invalidate instruction cache entries after setting up
|
||
|
|
nested function trampolines.
|
||
|
|
This option has no effect if <samp>-musermode</samp> is in effect and the selected
|
||
|
|
code generation option (e.g. <samp>-m4</samp>) does not allow the use of the <code>icbi</code>
|
||
|
|
instruction.
|
||
|
|
If the selected code generation option does not allow the use of the <code>icbi</code>
|
||
|
|
instruction, and <samp>-musermode</samp> is not in effect, the inlined code
|
||
|
|
manipulates the instruction cache address array directly with an associative
|
||
|
|
write. This not only requires privileged mode at run time, but it also
|
||
|
|
fails if the cache line had been mapped via the TLB and has become unmapped.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-misize</code></dt>
|
||
|
|
<dd><a name="index-misize-1"></a>
|
||
|
|
<p>Dump instruction size and location in the assembly code.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mpadstruct</code></dt>
|
||
|
|
<dd><a name="index-mpadstruct"></a>
|
||
|
|
<p>This option is deprecated. It pads structures to multiple of 4 bytes,
|
||
|
|
which is incompatible with the SH ABI.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-matomic-model=<var>model</var></code></dt>
|
||
|
|
<dd><a name="index-matomic_002dmodel_003dmodel"></a>
|
||
|
|
<p>Sets the model of atomic operations and additional parameters as a comma
|
||
|
|
separated list. For details on the atomic built-in functions see
|
||
|
|
<a href="_005f_005fatomic-Builtins.html#g_t_005f_005fatomic-Builtins">__atomic Builtins</a>. The following models and parameters are supported:
|
||
|
|
</p>
|
||
|
|
<dl compact="compact">
|
||
|
|
<dt>‘<samp>none</samp>’</dt>
|
||
|
|
<dd><p>Disable compiler generated atomic sequences and emit library calls for atomic
|
||
|
|
operations. This is the default if the target is not <code>sh*-*-linux*</code>.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt>‘<samp>soft-gusa</samp>’</dt>
|
||
|
|
<dd><p>Generate GNU/Linux compatible gUSA software atomic sequences for the atomic
|
||
|
|
built-in functions. The generated atomic sequences require additional support
|
||
|
|
from the interrupt/exception handling code of the system and are only suitable
|
||
|
|
for SH3* and SH4* single-core systems. This option is enabled by default when
|
||
|
|
the target is <code>sh*-*-linux*</code> and SH3* or SH4*. When the target is SH4A,
|
||
|
|
this option also partially utilizes the hardware atomic instructions
|
||
|
|
<code>movli.l</code> and <code>movco.l</code> to create more efficient code, unless
|
||
|
|
‘<samp>strict</samp>’ is specified.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt>‘<samp>soft-tcb</samp>’</dt>
|
||
|
|
<dd><p>Generate software atomic sequences that use a variable in the thread control
|
||
|
|
block. This is a variation of the gUSA sequences which can also be used on
|
||
|
|
SH1* and SH2* targets. The generated atomic sequences require additional
|
||
|
|
support from the interrupt/exception handling code of the system and are only
|
||
|
|
suitable for single-core systems. When using this model, the ‘<samp>gbr-offset=</samp>’
|
||
|
|
parameter has to be specified as well.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt>‘<samp>soft-imask</samp>’</dt>
|
||
|
|
<dd><p>Generate software atomic sequences that temporarily disable interrupts by
|
||
|
|
setting <code>SR.IMASK = 1111</code>. This model works only when the program runs
|
||
|
|
in privileged mode and is only suitable for single-core systems. Additional
|
||
|
|
support from the interrupt/exception handling code of the system is not
|
||
|
|
required. This model is enabled by default when the target is
|
||
|
|
<code>sh*-*-linux*</code> and SH1* or SH2*.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt>‘<samp>hard-llcs</samp>’</dt>
|
||
|
|
<dd><p>Generate hardware atomic sequences using the <code>movli.l</code> and <code>movco.l</code>
|
||
|
|
instructions only. This is only available on SH4A and is suitable for
|
||
|
|
multi-core systems. Since the hardware instructions support only 32 bit atomic
|
||
|
|
variables access to 8 or 16 bit variables is emulated with 32 bit accesses.
|
||
|
|
Code compiled with this option is also compatible with other software
|
||
|
|
atomic model interrupt/exception handling systems if executed on an SH4A
|
||
|
|
system. Additional support from the interrupt/exception handling code of the
|
||
|
|
system is not required for this model.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt>‘<samp>gbr-offset=</samp>’</dt>
|
||
|
|
<dd><p>This parameter specifies the offset in bytes of the variable in the thread
|
||
|
|
control block structure that should be used by the generated atomic sequences
|
||
|
|
when the ‘<samp>soft-tcb</samp>’ model has been selected. For other models this
|
||
|
|
parameter is ignored. The specified value must be an integer multiple of four
|
||
|
|
and in the range 0-1020.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt>‘<samp>strict</samp>’</dt>
|
||
|
|
<dd><p>This parameter prevents mixed usage of multiple atomic models, even if they
|
||
|
|
are compatible, and makes the compiler generate atomic sequences of the
|
||
|
|
specified model only.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mtas</code></dt>
|
||
|
|
<dd><a name="index-mtas"></a>
|
||
|
|
<p>Generate the <code>tas.b</code> opcode for <code>__atomic_test_and_set</code>.
|
||
|
|
Notice that depending on the particular hardware and software configuration
|
||
|
|
this can degrade overall performance due to the operand cache line flushes
|
||
|
|
that are implied by the <code>tas.b</code> instruction. On multi-core SH4A
|
||
|
|
processors the <code>tas.b</code> instruction must be used with caution since it
|
||
|
|
can result in data corruption for certain cache configurations.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mprefergot</code></dt>
|
||
|
|
<dd><a name="index-mprefergot"></a>
|
||
|
|
<p>When generating position-independent code, emit function calls using
|
||
|
|
the Global Offset Table instead of the Procedure Linkage Table.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-musermode</code></dt>
|
||
|
|
<dt><code>-mno-usermode</code></dt>
|
||
|
|
<dd><a name="index-musermode"></a>
|
||
|
|
<a name="index-mno_002dusermode"></a>
|
||
|
|
<p>Don’t allow (allow) the compiler generating privileged mode code. Specifying
|
||
|
|
<samp>-musermode</samp> also implies <samp>-mno-inline-ic_invalidate</samp> if the
|
||
|
|
inlined code would not work in user mode. <samp>-musermode</samp> is the default
|
||
|
|
when the target is <code>sh*-*-linux*</code>. If the target is SH1* or SH2*
|
||
|
|
<samp>-musermode</samp> has no effect, since there is no user mode.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-multcost=<var>number</var></code></dt>
|
||
|
|
<dd><a name="index-multcost_003dnumber"></a>
|
||
|
|
<p>Set the cost to assume for a multiply insn.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mdiv=<var>strategy</var></code></dt>
|
||
|
|
<dd><a name="index-mdiv_003dstrategy"></a>
|
||
|
|
<p>Set the division strategy to be used for integer division operations.
|
||
|
|
<var>strategy</var> can be one of:
|
||
|
|
</p>
|
||
|
|
<dl compact="compact">
|
||
|
|
<dt>‘<samp>call-div1</samp>’</dt>
|
||
|
|
<dd><p>Calls a library function that uses the single-step division instruction
|
||
|
|
<code>div1</code> to perform the operation. Division by zero calculates an
|
||
|
|
unspecified result and does not trap. This is the default except for SH4,
|
||
|
|
SH2A and SHcompact.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt>‘<samp>call-fp</samp>’</dt>
|
||
|
|
<dd><p>Calls a library function that performs the operation in double precision
|
||
|
|
floating point. Division by zero causes a floating-point exception. This is
|
||
|
|
the default for SHcompact with FPU. Specifying this for targets that do not
|
||
|
|
have a double precision FPU defaults to <code>call-div1</code>.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt>‘<samp>call-table</samp>’</dt>
|
||
|
|
<dd><p>Calls a library function that uses a lookup table for small divisors and
|
||
|
|
the <code>div1</code> instruction with case distinction for larger divisors. Division
|
||
|
|
by zero calculates an unspecified result and does not trap. This is the default
|
||
|
|
for SH4. Specifying this for targets that do not have dynamic shift
|
||
|
|
instructions defaults to <code>call-div1</code>.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<p>When a division strategy has not been specified the default strategy is
|
||
|
|
selected based on the current target. For SH2A the default strategy is to
|
||
|
|
use the <code>divs</code> and <code>divu</code> instructions instead of library function
|
||
|
|
calls.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-maccumulate-outgoing-args</code></dt>
|
||
|
|
<dd><a name="index-maccumulate_002doutgoing_002dargs"></a>
|
||
|
|
<p>Reserve space once for outgoing arguments in the function prologue rather
|
||
|
|
than around each call. Generally beneficial for performance and size. Also
|
||
|
|
needed for unwinding to avoid changing the stack frame around conditional code.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mdivsi3_libfunc=<var>name</var></code></dt>
|
||
|
|
<dd><a name="index-mdivsi3_005flibfunc_003dname"></a>
|
||
|
|
<p>Set the name of the library function used for 32-bit signed division to
|
||
|
|
<var>name</var>.
|
||
|
|
This only affects the name used in the ‘<samp>call</samp>’ division strategies, and
|
||
|
|
the compiler still expects the same sets of input/output/clobbered registers as
|
||
|
|
if this option were not present.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mfixed-range=<var>register-range</var></code></dt>
|
||
|
|
<dd><a name="index-mfixed_002drange-2"></a>
|
||
|
|
<p>Generate code treating the given register range as fixed registers.
|
||
|
|
A fixed register is one that the register allocator can not use. This is
|
||
|
|
useful when compiling kernel code. A register range is specified as
|
||
|
|
two registers separated by a dash. Multiple register ranges can be
|
||
|
|
specified separated by a comma.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mbranch-cost=<var>num</var></code></dt>
|
||
|
|
<dd><a name="index-mbranch_002dcost_003dnum"></a>
|
||
|
|
<p>Assume <var>num</var> to be the cost for a branch instruction. Higher numbers
|
||
|
|
make the compiler try to generate more branch-free code if possible.
|
||
|
|
If not specified the value is selected depending on the processor type that
|
||
|
|
is being compiled for.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mzdcbranch</code></dt>
|
||
|
|
<dt><code>-mno-zdcbranch</code></dt>
|
||
|
|
<dd><a name="index-mzdcbranch"></a>
|
||
|
|
<a name="index-mno_002dzdcbranch"></a>
|
||
|
|
<p>Assume (do not assume) that zero displacement conditional branch instructions
|
||
|
|
<code>bt</code> and <code>bf</code> are fast. If <samp>-mzdcbranch</samp> is specified, the
|
||
|
|
compiler prefers zero displacement branch code sequences. This is
|
||
|
|
enabled by default when generating code for SH4 and SH4A. It can be explicitly
|
||
|
|
disabled by specifying <samp>-mno-zdcbranch</samp>.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mcbranch-force-delay-slot</code></dt>
|
||
|
|
<dd><a name="index-mcbranch_002dforce_002ddelay_002dslot"></a>
|
||
|
|
<p>Force the usage of delay slots for conditional branches, which stuffs the delay
|
||
|
|
slot with a <code>nop</code> if a suitable instruction cannot be found. By default
|
||
|
|
this option is disabled. It can be enabled to work around hardware bugs as
|
||
|
|
found in the original SH7055.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mfused-madd</code></dt>
|
||
|
|
<dt><code>-mno-fused-madd</code></dt>
|
||
|
|
<dd><a name="index-mfused_002dmadd-5"></a>
|
||
|
|
<a name="index-mno_002dfused_002dmadd-5"></a>
|
||
|
|
<p>Generate code that uses (does not use) the floating-point multiply and
|
||
|
|
accumulate instructions. These instructions are generated by default
|
||
|
|
if hardware floating point is used. The machine-dependent
|
||
|
|
<samp>-mfused-madd</samp> option is now mapped to the machine-independent
|
||
|
|
<samp>-ffp-contract=fast</samp> option, and <samp>-mno-fused-madd</samp> is
|
||
|
|
mapped to <samp>-ffp-contract=off</samp>.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mfsca</code></dt>
|
||
|
|
<dt><code>-mno-fsca</code></dt>
|
||
|
|
<dd><a name="index-mfsca"></a>
|
||
|
|
<a name="index-mno_002dfsca"></a>
|
||
|
|
<p>Allow or disallow the compiler to emit the <code>fsca</code> instruction for sine
|
||
|
|
and cosine approximations. The option <samp>-mfsca</samp> must be used in
|
||
|
|
combination with <samp>-funsafe-math-optimizations</samp>. It is enabled by default
|
||
|
|
when generating code for SH4A. Using <samp>-mno-fsca</samp> disables sine and cosine
|
||
|
|
approximations even if <samp>-funsafe-math-optimizations</samp> is in effect.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mfsrra</code></dt>
|
||
|
|
<dt><code>-mno-fsrra</code></dt>
|
||
|
|
<dd><a name="index-mfsrra"></a>
|
||
|
|
<a name="index-mno_002dfsrra"></a>
|
||
|
|
<p>Allow or disallow the compiler to emit the <code>fsrra</code> instruction for
|
||
|
|
reciprocal square root approximations. The option <samp>-mfsrra</samp> must be used
|
||
|
|
in combination with <samp>-funsafe-math-optimizations</samp> and
|
||
|
|
<samp>-ffinite-math-only</samp>. It is enabled by default when generating code for
|
||
|
|
SH4A. Using <samp>-mno-fsrra</samp> disables reciprocal square root approximations
|
||
|
|
even if <samp>-funsafe-math-optimizations</samp> and <samp>-ffinite-math-only</samp> are
|
||
|
|
in effect.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mpretend-cmove</code></dt>
|
||
|
|
<dd><a name="index-mpretend_002dcmove"></a>
|
||
|
|
<p>Prefer zero-displacement conditional branches for conditional move instruction
|
||
|
|
patterns. This can result in faster code on the SH4 processor.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mfdpic</code></dt>
|
||
|
|
<dd><a name="index-fdpic"></a>
|
||
|
|
<p>Generate code using the FDPIC ABI.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<hr>
|
||
|
|
<div class="header">
|
||
|
|
<p>
|
||
|
|
Next: <a href="Solaris-2-Options.html#Solaris-2-Options" accesskey="n" rel="next">Solaris 2 Options</a>, Previous: <a href="Score-Options.html#Score-Options" accesskey="p" rel="prev">Score Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
</body>
|
||
|
|
</html>
|