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244 lines
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244 lines
11 KiB
HTML
4 years ago
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<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
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<html>
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<!-- Copyright (C) 1988-2018 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.3 or
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any later version published by the Free Software Foundation; with the
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Invariant Sections being "Funding Free Software", the Front-Cover
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Texts being (a) (see below), and with the Back-Cover Texts being (b)
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(see below). A copy of the license is included in the section entitled
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"GNU Free Documentation License".
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(a) The FSF's Front-Cover Text is:
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A GNU Manual
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(b) The FSF's Back-Cover Text is:
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You have freedom to copy and modify this GNU Manual, like GNU
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software. Copies published by the Free Software Foundation raise
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funds for GNU development. -->
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<!-- Created by GNU Texinfo 6.4, http://www.gnu.org/software/texinfo/ -->
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<head>
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<title>RISC-V Options (Using the GNU Compiler Collection (GCC))</title>
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<meta name="description" content="RISC-V Options (Using the GNU Compiler Collection (GCC))">
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<meta name="keywords" content="RISC-V Options (Using the GNU Compiler Collection (GCC))">
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<meta name="resource-type" content="document">
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<meta name="distribution" content="global">
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<meta name="Generator" content="makeinfo">
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<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
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<link href="index.html#Top" rel="start" title="Top">
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<link href="Option-Index.html#Option-Index" rel="index" title="Option Index">
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<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">
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<link href="Submodel-Options.html#Submodel-Options" rel="up" title="Submodel Options">
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<link href="RL78-Options.html#RL78-Options" rel="next" title="RL78 Options">
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<link href="PowerPC-SPE-Options.html#PowerPC-SPE-Options" rel="prev" title="PowerPC SPE Options">
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</style>
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</head>
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<body lang="en">
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<a name="RISC_002dV-Options"></a>
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<div class="header">
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<p>
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Next: <a href="RL78-Options.html#RL78-Options" accesskey="n" rel="next">RL78 Options</a>, Previous: <a href="PowerPC-SPE-Options.html#PowerPC-SPE-Options" accesskey="p" rel="prev">PowerPC SPE Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
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</div>
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<hr>
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<a name="RISC_002dV-Options-1"></a>
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<h4 class="subsection">3.18.38 RISC-V Options</h4>
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<a name="index-RISC_002dV-Options"></a>
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<p>These command-line options are defined for RISC-V targets:
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</p>
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<dl compact="compact">
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<dt><code>-mbranch-cost=<var>n</var></code></dt>
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<dd><a name="index-mbranch_002dcost-3"></a>
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<p>Set the cost of branches to roughly <var>n</var> instructions.
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</p>
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</dd>
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<dt><code>-mplt</code></dt>
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<dt><code>-mno-plt</code></dt>
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<dd><a name="index-plt"></a>
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<p>When generating PIC code, do or don’t allow the use of PLTs. Ignored for
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non-PIC. The default is <samp>-mplt</samp>.
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</p>
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</dd>
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<dt><code>-mabi=<var>ABI-string</var></code></dt>
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<dd><a name="index-mabi-3"></a>
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<p>Specify integer and floating-point calling convention. <var>ABI-string</var>
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contains two parts: the size of integer types and the registers used for
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floating-point types. For example ‘<samp>-march=rv64ifd -mabi=lp64d</samp>’ means that
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‘<samp>long</samp>’ and pointers are 64-bit (implicitly defining ‘<samp>int</samp>’ to be
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32-bit), and that floating-point values up to 64 bits wide are passed in F
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registers. Contrast this with ‘<samp>-march=rv64ifd -mabi=lp64f</samp>’, which still
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allows the compiler to generate code that uses the F and D extensions but only
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allows floating-point values up to 32 bits long to be passed in registers; or
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‘<samp>-march=rv64ifd -mabi=lp64</samp>’, in which no floating-point arguments will be
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passed in registers.
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</p>
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<p>The default for this argument is system dependent, users who want a specific
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calling convention should specify one explicitly. The valid calling
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conventions are: ‘<samp>ilp32</samp>’, ‘<samp>ilp32f</samp>’, ‘<samp>ilp32d</samp>’, ‘<samp>lp64</samp>’,
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‘<samp>lp64f</samp>’, and ‘<samp>lp64d</samp>’. Some calling conventions are impossible to
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implement on some ISAs: for example, ‘<samp>-march=rv32if -mabi=ilp32d</samp>’ is
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invalid because the ABI requires 64-bit values be passed in F registers, but F
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registers are only 32 bits wide. There is also the ‘<samp>ilp32e</samp>’ ABI that can
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only be used with the ‘<samp>rv32e</samp>’ architecture. This ABI is not well
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specified at present, and is subject to change.
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</p>
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</dd>
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<dt><code>-mfdiv</code></dt>
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<dt><code>-mno-fdiv</code></dt>
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<dd><a name="index-mfdiv"></a>
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<p>Do or don’t use hardware floating-point divide and square root instructions.
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This requires the F or D extensions for floating-point registers. The default
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is to use them if the specified architecture has these instructions.
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</p>
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</dd>
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<dt><code>-mdiv</code></dt>
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<dt><code>-mno-div</code></dt>
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<dd><a name="index-mdiv-3"></a>
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<p>Do or don’t use hardware instructions for integer division. This requires the
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M extension. The default is to use them if the specified architecture has
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these instructions.
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</p>
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</dd>
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<dt><code>-march=<var>ISA-string</var></code></dt>
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<dd><a name="index-march-10"></a>
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<p>Generate code for given RISC-V ISA (e.g. ‘<samp>rv64im</samp>’). ISA strings must be
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lower-case. Examples include ‘<samp>rv64i</samp>’, ‘<samp>rv32g</samp>’, ‘<samp>rv32e</samp>’, and
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‘<samp>rv32imaf</samp>’.
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</p>
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</dd>
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<dt><code>-mtune=<var>processor-string</var></code></dt>
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<dd><a name="index-mtune-11"></a>
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<p>Optimize the output for the given processor, specified by microarchitecture
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name. Permissible values for this option are: ‘<samp>rocket</samp>’,
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‘<samp>sifive-3-series</samp>’, ‘<samp>sifive-5-series</samp>’, ‘<samp>sifive-7-series</samp>’,
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and ‘<samp>size</samp>’.
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</p>
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<p>When <samp>-mtune=</samp> is not specified, the default is ‘<samp>rocket</samp>’.
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</p>
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<p>The ‘<samp>size</samp>’ choice is not intended for use by end-users. This is used
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when <samp>-Os</samp> is specified. It overrides the instruction cost info
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provided by <samp>-mtune=</samp>, but does not override the pipeline info. This
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helps reduce code size while still giving good performance.
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</p>
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</dd>
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<dt><code>-mpreferred-stack-boundary=<var>num</var></code></dt>
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<dd><a name="index-mpreferred_002dstack_002dboundary"></a>
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<p>Attempt to keep the stack boundary aligned to a 2 raised to <var>num</var>
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byte boundary. If <samp>-mpreferred-stack-boundary</samp> is not specified,
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the default is 4 (16 bytes or 128-bits).
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</p>
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<p><strong>Warning:</strong> If you use this switch, then you must build all modules with
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the same value, including any libraries. This includes the system libraries
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and startup modules.
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</p>
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</dd>
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<dt><code>-msmall-data-limit=<var>n</var></code></dt>
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<dd><a name="index-msmall_002ddata_002dlimit"></a>
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<p>Put global and static data smaller than <var>n</var> bytes into a special section
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(on some targets).
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</p>
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</dd>
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<dt><code>-msave-restore</code></dt>
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<dt><code>-mno-save-restore</code></dt>
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<dd><a name="index-msave_002drestore"></a>
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<p>Do or don’t use smaller but slower prologue and epilogue code that uses
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library function calls. The default is to use fast inline prologues and
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epilogues.
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</p>
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</dd>
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<dt><code>-mstrict-align</code></dt>
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<dt><code>-mno-strict-align</code></dt>
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<dd><a name="index-mstrict_002dalign-3"></a>
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<p>Do not or do generate unaligned memory accesses. The default is set depending
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on whether the processor we are optimizing for supports fast unaligned access
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or not.
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</p>
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</dd>
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<dt><code>-mcmodel=medlow</code></dt>
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<dd><a name="index-mcmodel_003dmedlow"></a>
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<p>Generate code for the medium-low code model. The program and its statically
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defined symbols must lie within a single 2 GiB address range and must lie
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between absolute addresses -2 GiB and +2 GiB. Programs can be
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statically or dynamically linked. This is the default code model.
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</p>
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</dd>
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<dt><code>-mcmodel=medany</code></dt>
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<dd><a name="index-mcmodel_003dmedany"></a>
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<p>Generate code for the medium-any code model. The program and its statically
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defined symbols must be within any single 2 GiB address range. Programs can be
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statically or dynamically linked.
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</p>
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</dd>
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<dt><code>-mexplicit-relocs</code></dt>
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<dt><code>-mno-exlicit-relocs</code></dt>
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<dd><p>Use or do not use assembler relocation operators when dealing with symbolic
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addresses. The alternative is to use assembler macros instead, which may
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limit optimization.
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</p>
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</dd>
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<dt><code>-mrelax</code></dt>
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<dt><code>-mno-relax</code></dt>
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<dd><p>Take advantage of linker relaxations to reduce the number of instructions
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required to materialize symbol addresses. The default is to take advantage of
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linker relaxations.
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</p>
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</dd>
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<dt><code>-memit-attribute</code></dt>
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<dt><code>-mno-emit-attribute</code></dt>
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<dd><p>Emit (do not emit) RISC-V attribute to record extra information into ELF
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objects. This feature requires at least binutils 2.32.
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</p>
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</dd>
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<dt><code>-malign-data=<var>type</var></code></dt>
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<dd><a name="index-malign_002ddata"></a>
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<p>Control how GCC aligns variables and constants of array, structure, or union
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types. Supported values for <var>type</var> are ‘<samp>xlen</samp>’ which uses x register
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width as the alignment value, and ‘<samp>natural</samp>’ which uses natural alignment.
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‘<samp>xlen</samp>’ is the default.
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</p></dd>
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</dl>
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<hr>
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<div class="header">
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<p>
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Next: <a href="RL78-Options.html#RL78-Options" accesskey="n" rel="next">RL78 Options</a>, Previous: <a href="PowerPC-SPE-Options.html#PowerPC-SPE-Options" accesskey="p" rel="prev">PowerPC SPE Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
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</div>
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</body>
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</html>
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