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305 lines
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305 lines
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HTML
4 years ago
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<!-- Copyright (C) 1988-2018 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.3 or
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any later version published by the Free Software Foundation; with the
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Invariant Sections being "Funding Free Software", the Front-Cover
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(see below). A copy of the license is included in the section entitled
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"GNU Free Documentation License".
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(a) The FSF's Front-Cover Text is:
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A GNU Manual
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(b) The FSF's Back-Cover Text is:
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You have freedom to copy and modify this GNU Manual, like GNU
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<!-- Created by GNU Texinfo 6.4, http://www.gnu.org/software/texinfo/ -->
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<head>
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<title>PowerPC Hardware Transactional Memory Built-in Functions (Using the GNU Compiler Collection (GCC))</title>
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<meta name="description" content="PowerPC Hardware Transactional Memory Built-in Functions (Using the GNU Compiler Collection (GCC))">
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<link href="index.html#Top" rel="start" title="Top">
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<link href="Option-Index.html#Option-Index" rel="index" title="Option Index">
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<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">
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<link href="Target-Builtins.html#Target-Builtins" rel="up" title="Target Builtins">
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<link href="PowerPC-Atomic-Memory-Operation-Functions.html#PowerPC-Atomic-Memory-Operation-Functions" rel="next" title="PowerPC Atomic Memory Operation Functions">
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<link href="PowerPC-AltiVec_002fVSX-Built_002din-Functions.html#PowerPC-AltiVec_002fVSX-Built_002din-Functions" rel="prev" title="PowerPC AltiVec/VSX Built-in Functions">
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<body lang="en">
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<a name="PowerPC-Hardware-Transactional-Memory-Built_002din-Functions"></a>
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<div class="header">
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<p>
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Next: <a href="PowerPC-Atomic-Memory-Operation-Functions.html#PowerPC-Atomic-Memory-Operation-Functions" accesskey="n" rel="next">PowerPC Atomic Memory Operation Functions</a>, Previous: <a href="PowerPC-AltiVec_002fVSX-Built_002din-Functions.html#PowerPC-AltiVec_002fVSX-Built_002din-Functions" accesskey="p" rel="prev">PowerPC AltiVec/VSX Built-in Functions</a>, Up: <a href="Target-Builtins.html#Target-Builtins" accesskey="u" rel="up">Target Builtins</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
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</div>
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<hr>
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<a name="PowerPC-Hardware-Transactional-Memory-Built_002din-Functions-1"></a>
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<h4 class="subsection">6.59.23 PowerPC Hardware Transactional Memory Built-in Functions</h4>
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<p>GCC provides two interfaces for accessing the Hardware Transactional
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Memory (HTM) instructions available on some of the PowerPC family
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of processors (eg, POWER8). The two interfaces come in a low level
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interface, consisting of built-in functions specific to PowerPC and a
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higher level interface consisting of inline functions that are common
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between PowerPC and S/390.
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</p>
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<a name="PowerPC-HTM-Low-Level-Built_002din-Functions"></a>
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<h4 class="subsubsection">6.59.23.1 PowerPC HTM Low Level Built-in Functions</h4>
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<p>The following low level built-in functions are available with
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<samp>-mhtm</samp> or <samp>-mcpu=CPU</samp> where CPU is ‘power8’ or later.
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They all generate the machine instruction that is part of the name.
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</p>
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<p>The HTM builtins (with the exception of <code>__builtin_tbegin</code>) return
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the full 4-bit condition register value set by their associated hardware
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instruction. The header file <code>htmintrin.h</code> defines some macros that can
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be used to decipher the return value. The <code>__builtin_tbegin</code> builtin
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returns a simple true or false value depending on whether a transaction was
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successfully started or not. The arguments of the builtins match exactly the
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type and order of the associated hardware instruction’s operands, except for
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the <code>__builtin_tcheck</code> builtin, which does not take any input arguments.
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Refer to the ISA manual for a description of each instruction’s operands.
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</p>
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<div class="smallexample">
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<pre class="smallexample">unsigned int __builtin_tbegin (unsigned int)
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unsigned int __builtin_tend (unsigned int)
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unsigned int __builtin_tabort (unsigned int)
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unsigned int __builtin_tabortdc (unsigned int, unsigned int, unsigned int)
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unsigned int __builtin_tabortdci (unsigned int, unsigned int, int)
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unsigned int __builtin_tabortwc (unsigned int, unsigned int, unsigned int)
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unsigned int __builtin_tabortwci (unsigned int, unsigned int, int)
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unsigned int __builtin_tcheck (void)
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unsigned int __builtin_treclaim (unsigned int)
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unsigned int __builtin_trechkpt (void)
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unsigned int __builtin_tsr (unsigned int)
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</pre></div>
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<p>In addition to the above HTM built-ins, we have added built-ins for
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some common extended mnemonics of the HTM instructions:
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</p>
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<div class="smallexample">
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<pre class="smallexample">unsigned int __builtin_tendall (void)
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unsigned int __builtin_tresume (void)
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unsigned int __builtin_tsuspend (void)
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</pre></div>
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<p>Note that the semantics of the above HTM builtins are required to mimic
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the locking semantics used for critical sections. Builtins that are used
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to create a new transaction or restart a suspended transaction must have
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lock acquisition like semantics while those builtins that end or suspend a
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transaction must have lock release like semantics. Specifically, this must
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mimic lock semantics as specified by C++11, for example: Lock acquisition is
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as-if an execution of __atomic_exchange_n(&globallock,1,__ATOMIC_ACQUIRE)
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that returns 0, and lock release is as-if an execution of
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__atomic_store(&globallock,0,__ATOMIC_RELEASE), with globallock being an
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implicit implementation-defined lock used for all transactions. The HTM
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instructions associated with with the builtins inherently provide the
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correct acquisition and release hardware barriers required. However,
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the compiler must also be prohibited from moving loads and stores across
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the builtins in a way that would violate their semantics. This has been
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accomplished by adding memory barriers to the associated HTM instructions
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(which is a conservative approach to provide acquire and release semantics).
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Earlier versions of the compiler did not treat the HTM instructions as
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memory barriers. A <code>__TM_FENCE__</code> macro has been added, which can
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be used to determine whether the current compiler treats HTM instructions
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as memory barriers or not. This allows the user to explicitly add memory
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barriers to their code when using an older version of the compiler.
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</p>
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<p>The following set of built-in functions are available to gain access
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to the HTM specific special purpose registers.
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</p>
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<div class="smallexample">
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<pre class="smallexample">unsigned long __builtin_get_texasr (void)
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unsigned long __builtin_get_texasru (void)
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unsigned long __builtin_get_tfhar (void)
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unsigned long __builtin_get_tfiar (void)
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void __builtin_set_texasr (unsigned long);
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void __builtin_set_texasru (unsigned long);
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void __builtin_set_tfhar (unsigned long);
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void __builtin_set_tfiar (unsigned long);
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</pre></div>
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<p>Example usage of these low level built-in functions may look like:
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</p>
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<div class="smallexample">
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<pre class="smallexample">#include <htmintrin.h>
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int num_retries = 10;
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while (1)
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{
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if (__builtin_tbegin (0))
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{
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/* Transaction State Initiated. */
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if (is_locked (lock))
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__builtin_tabort (0);
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... transaction code...
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__builtin_tend (0);
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break;
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}
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else
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{
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/* Transaction State Failed. Use locks if the transaction
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failure is "persistent" or we've tried too many times. */
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if (num_retries-- <= 0
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|| _TEXASRU_FAILURE_PERSISTENT (__builtin_get_texasru ()))
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{
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acquire_lock (lock);
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... non transactional fallback path...
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release_lock (lock);
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break;
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}
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}
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}
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</pre></div>
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<p>One final built-in function has been added that returns the value of
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the 2-bit Transaction State field of the Machine Status Register (MSR)
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as stored in <code>CR0</code>.
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</p>
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<div class="smallexample">
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<pre class="smallexample">unsigned long __builtin_ttest (void)
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</pre></div>
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<p>This built-in can be used to determine the current transaction state
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using the following code example:
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</p>
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<div class="smallexample">
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<pre class="smallexample">#include <htmintrin.h>
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unsigned char tx_state = _HTM_STATE (__builtin_ttest ());
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if (tx_state == _HTM_TRANSACTIONAL)
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{
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/* Code to use in transactional state. */
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}
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else if (tx_state == _HTM_NONTRANSACTIONAL)
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{
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/* Code to use in non-transactional state. */
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}
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else if (tx_state == _HTM_SUSPENDED)
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{
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/* Code to use in transaction suspended state. */
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}
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</pre></div>
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<a name="PowerPC-HTM-High-Level-Inline-Functions"></a>
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<h4 class="subsubsection">6.59.23.2 PowerPC HTM High Level Inline Functions</h4>
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<p>The following high level HTM interface is made available by including
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<code><htmxlintrin.h></code> and using <samp>-mhtm</samp> or <samp>-mcpu=CPU</samp>
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where CPU is ‘power8’ or later. This interface is common between PowerPC
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and S/390, allowing users to write one HTM source implementation that
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can be compiled and executed on either system.
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</p>
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<div class="smallexample">
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<pre class="smallexample">long __TM_simple_begin (void)
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long __TM_begin (void* const TM_buff)
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long __TM_end (void)
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void __TM_abort (void)
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void __TM_named_abort (unsigned char const code)
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void __TM_resume (void)
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void __TM_suspend (void)
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long __TM_is_user_abort (void* const TM_buff)
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long __TM_is_named_user_abort (void* const TM_buff, unsigned char *code)
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long __TM_is_illegal (void* const TM_buff)
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long __TM_is_footprint_exceeded (void* const TM_buff)
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long __TM_nesting_depth (void* const TM_buff)
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long __TM_is_nested_too_deep(void* const TM_buff)
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long __TM_is_conflict(void* const TM_buff)
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long __TM_is_failure_persistent(void* const TM_buff)
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long __TM_failure_address(void* const TM_buff)
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long long __TM_failure_code(void* const TM_buff)
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</pre></div>
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<p>Using these common set of HTM inline functions, we can create
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a more portable version of the HTM example in the previous
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section that will work on either PowerPC or S/390:
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</p>
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<div class="smallexample">
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<pre class="smallexample">#include <htmxlintrin.h>
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int num_retries = 10;
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TM_buff_type TM_buff;
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while (1)
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{
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if (__TM_begin (TM_buff) == _HTM_TBEGIN_STARTED)
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{
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/* Transaction State Initiated. */
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if (is_locked (lock))
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__TM_abort ();
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... transaction code...
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__TM_end ();
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break;
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}
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else
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{
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/* Transaction State Failed. Use locks if the transaction
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failure is "persistent" or we've tried too many times. */
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if (num_retries-- <= 0
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|| __TM_is_failure_persistent (TM_buff))
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{
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acquire_lock (lock);
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... non transactional fallback path...
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release_lock (lock);
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break;
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}
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}
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}
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</pre></div>
|
||
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<hr>
|
||
|
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<div class="header">
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||
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<p>
|
||
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|
Next: <a href="PowerPC-Atomic-Memory-Operation-Functions.html#PowerPC-Atomic-Memory-Operation-Functions" accesskey="n" rel="next">PowerPC Atomic Memory Operation Functions</a>, Previous: <a href="PowerPC-AltiVec_002fVSX-Built_002din-Functions.html#PowerPC-AltiVec_002fVSX-Built_002din-Functions" accesskey="p" rel="prev">PowerPC AltiVec/VSX Built-in Functions</a>, Up: <a href="Target-Builtins.html#Target-Builtins" accesskey="u" rel="up">Target Builtins</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
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</div>
|
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</body>
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</html>
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