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313 lines
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HTML
313 lines
14 KiB
HTML
4 years ago
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<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
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<html>
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<!-- Copyright (C) 1988-2018 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.3 or
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any later version published by the Free Software Foundation; with the
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Invariant Sections being "Funding Free Software", the Front-Cover
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Texts being (a) (see below), and with the Back-Cover Texts being (b)
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(see below). A copy of the license is included in the section entitled
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"GNU Free Documentation License".
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(a) The FSF's Front-Cover Text is:
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A GNU Manual
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(b) The FSF's Back-Cover Text is:
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You have freedom to copy and modify this GNU Manual, like GNU
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software. Copies published by the Free Software Foundation raise
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funds for GNU development. -->
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<!-- Created by GNU Texinfo 6.4, http://www.gnu.org/software/texinfo/ -->
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<head>
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<title>Blackfin Options (Using the GNU Compiler Collection (GCC))</title>
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<meta name="description" content="Blackfin Options (Using the GNU Compiler Collection (GCC))">
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<meta name="keywords" content="Blackfin Options (Using the GNU Compiler Collection (GCC))">
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<meta name="resource-type" content="document">
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<meta name="distribution" content="global">
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<meta name="Generator" content="makeinfo">
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<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
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<link href="index.html#Top" rel="start" title="Top">
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<link href="Option-Index.html#Option-Index" rel="index" title="Option Index">
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<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">
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<link href="Submodel-Options.html#Submodel-Options" rel="up" title="Submodel Options">
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<link href="C6X-Options.html#C6X-Options" rel="next" title="C6X Options">
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<link href="AVR-Options.html#AVR-Options" rel="prev" title="AVR Options">
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<style type="text/css">
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div.example {margin-left: 3.2em}
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kbd {font-style: oblique}
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pre.display {font-family: inherit}
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pre.format {font-family: inherit}
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pre.menu-comment {font-family: serif}
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pre.smalllisp {font-size: smaller}
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span.nolinebreak {white-space: nowrap}
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span.roman {font-family: initial; font-weight: normal}
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span.sansserif {font-family: sans-serif; font-weight: normal}
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ul.no-bullet {list-style: none}
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-->
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</style>
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</head>
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<body lang="en">
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<a name="Blackfin-Options"></a>
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<div class="header">
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<p>
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Next: <a href="C6X-Options.html#C6X-Options" accesskey="n" rel="next">C6X Options</a>, Previous: <a href="AVR-Options.html#AVR-Options" accesskey="p" rel="prev">AVR Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
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</div>
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<hr>
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<a name="Blackfin-Options-1"></a>
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<h4 class="subsection">3.18.6 Blackfin Options</h4>
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<a name="index-Blackfin-Options"></a>
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<dl compact="compact">
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<dt><code>-mcpu=<var>cpu</var><span class="roman">[</span>-<var>sirevision</var><span class="roman">]</span></code></dt>
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<dd><a name="index-mcpu_003d"></a>
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<p>Specifies the name of the target Blackfin processor. Currently, <var>cpu</var>
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can be one of ‘<samp>bf512</samp>’, ‘<samp>bf514</samp>’, ‘<samp>bf516</samp>’, ‘<samp>bf518</samp>’,
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‘<samp>bf522</samp>’, ‘<samp>bf523</samp>’, ‘<samp>bf524</samp>’, ‘<samp>bf525</samp>’, ‘<samp>bf526</samp>’,
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‘<samp>bf527</samp>’, ‘<samp>bf531</samp>’, ‘<samp>bf532</samp>’, ‘<samp>bf533</samp>’,
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‘<samp>bf534</samp>’, ‘<samp>bf536</samp>’, ‘<samp>bf537</samp>’, ‘<samp>bf538</samp>’, ‘<samp>bf539</samp>’,
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‘<samp>bf542</samp>’, ‘<samp>bf544</samp>’, ‘<samp>bf547</samp>’, ‘<samp>bf548</samp>’, ‘<samp>bf549</samp>’,
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‘<samp>bf542m</samp>’, ‘<samp>bf544m</samp>’, ‘<samp>bf547m</samp>’, ‘<samp>bf548m</samp>’, ‘<samp>bf549m</samp>’,
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‘<samp>bf561</samp>’, ‘<samp>bf592</samp>’.
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</p>
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<p>The optional <var>sirevision</var> specifies the silicon revision of the target
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Blackfin processor. Any workarounds available for the targeted silicon revision
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are enabled. If <var>sirevision</var> is ‘<samp>none</samp>’, no workarounds are enabled.
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If <var>sirevision</var> is ‘<samp>any</samp>’, all workarounds for the targeted processor
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are enabled. The <code>__SILICON_REVISION__</code> macro is defined to two
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hexadecimal digits representing the major and minor numbers in the silicon
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revision. If <var>sirevision</var> is ‘<samp>none</samp>’, the <code>__SILICON_REVISION__</code>
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is not defined. If <var>sirevision</var> is ‘<samp>any</samp>’, the
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<code>__SILICON_REVISION__</code> is defined to be <code>0xffff</code>.
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If this optional <var>sirevision</var> is not used, GCC assumes the latest known
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silicon revision of the targeted Blackfin processor.
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</p>
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<p>GCC defines a preprocessor macro for the specified <var>cpu</var>.
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For the ‘<samp>bfin-elf</samp>’ toolchain, this option causes the hardware BSP
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provided by libgloss to be linked in if <samp>-msim</samp> is not given.
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</p>
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<p>Without this option, ‘<samp>bf532</samp>’ is used as the processor by default.
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</p>
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<p>Note that support for ‘<samp>bf561</samp>’ is incomplete. For ‘<samp>bf561</samp>’,
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only the preprocessor macro is defined.
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</p>
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</dd>
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<dt><code>-msim</code></dt>
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<dd><a name="index-msim"></a>
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<p>Specifies that the program will be run on the simulator. This causes
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the simulator BSP provided by libgloss to be linked in. This option
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has effect only for ‘<samp>bfin-elf</samp>’ toolchain.
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Certain other options, such as <samp>-mid-shared-library</samp> and
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<samp>-mfdpic</samp>, imply <samp>-msim</samp>.
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</p>
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</dd>
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<dt><code>-momit-leaf-frame-pointer</code></dt>
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<dd><a name="index-momit_002dleaf_002dframe_002dpointer-1"></a>
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<p>Don’t keep the frame pointer in a register for leaf functions. This
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avoids the instructions to save, set up and restore frame pointers and
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makes an extra register available in leaf functions.
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</p>
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</dd>
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<dt><code>-mspecld-anomaly</code></dt>
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<dd><a name="index-mspecld_002danomaly"></a>
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<p>When enabled, the compiler ensures that the generated code does not
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contain speculative loads after jump instructions. If this option is used,
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<code>__WORKAROUND_SPECULATIVE_LOADS</code> is defined.
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</p>
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</dd>
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<dt><code>-mno-specld-anomaly</code></dt>
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<dd><a name="index-mno_002dspecld_002danomaly"></a>
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<p>Don’t generate extra code to prevent speculative loads from occurring.
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</p>
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</dd>
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<dt><code>-mcsync-anomaly</code></dt>
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<dd><a name="index-mcsync_002danomaly"></a>
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<p>When enabled, the compiler ensures that the generated code does not
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contain CSYNC or SSYNC instructions too soon after conditional branches.
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If this option is used, <code>__WORKAROUND_SPECULATIVE_SYNCS</code> is defined.
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</p>
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</dd>
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<dt><code>-mno-csync-anomaly</code></dt>
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<dd><a name="index-mno_002dcsync_002danomaly"></a>
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<p>Don’t generate extra code to prevent CSYNC or SSYNC instructions from
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occurring too soon after a conditional branch.
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</p>
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</dd>
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<dt><code>-mlow-64k</code></dt>
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<dd><a name="index-mlow_002d64k"></a>
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<p>When enabled, the compiler is free to take advantage of the knowledge that
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the entire program fits into the low 64k of memory.
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</p>
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</dd>
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<dt><code>-mno-low-64k</code></dt>
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<dd><a name="index-mno_002dlow_002d64k"></a>
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<p>Assume that the program is arbitrarily large. This is the default.
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</p>
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</dd>
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<dt><code>-mstack-check-l1</code></dt>
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<dd><a name="index-mstack_002dcheck_002dl1"></a>
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<p>Do stack checking using information placed into L1 scratchpad memory by the
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uClinux kernel.
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</p>
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</dd>
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<dt><code>-mid-shared-library</code></dt>
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<dd><a name="index-mid_002dshared_002dlibrary"></a>
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<p>Generate code that supports shared libraries via the library ID method.
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This allows for execute in place and shared libraries in an environment
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without virtual memory management. This option implies <samp>-fPIC</samp>.
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With a ‘<samp>bfin-elf</samp>’ target, this option implies <samp>-msim</samp>.
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</p>
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</dd>
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<dt><code>-mno-id-shared-library</code></dt>
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<dd><a name="index-mno_002did_002dshared_002dlibrary"></a>
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<p>Generate code that doesn’t assume ID-based shared libraries are being used.
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This is the default.
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</p>
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</dd>
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<dt><code>-mleaf-id-shared-library</code></dt>
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<dd><a name="index-mleaf_002did_002dshared_002dlibrary"></a>
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<p>Generate code that supports shared libraries via the library ID method,
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but assumes that this library or executable won’t link against any other
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ID shared libraries. That allows the compiler to use faster code for jumps
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and calls.
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</p>
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</dd>
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<dt><code>-mno-leaf-id-shared-library</code></dt>
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<dd><a name="index-mno_002dleaf_002did_002dshared_002dlibrary"></a>
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<p>Do not assume that the code being compiled won’t link against any ID shared
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libraries. Slower code is generated for jump and call insns.
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</p>
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</dd>
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<dt><code>-mshared-library-id=n</code></dt>
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<dd><a name="index-mshared_002dlibrary_002did"></a>
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<p>Specifies the identification number of the ID-based shared library being
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compiled. Specifying a value of 0 generates more compact code; specifying
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other values forces the allocation of that number to the current
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library but is no more space- or time-efficient than omitting this option.
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</p>
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</dd>
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<dt><code>-msep-data</code></dt>
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<dd><a name="index-msep_002ddata"></a>
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<p>Generate code that allows the data segment to be located in a different
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area of memory from the text segment. This allows for execute in place in
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an environment without virtual memory management by eliminating relocations
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against the text section.
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</p>
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</dd>
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<dt><code>-mno-sep-data</code></dt>
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<dd><a name="index-mno_002dsep_002ddata"></a>
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<p>Generate code that assumes that the data segment follows the text segment.
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This is the default.
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</p>
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</dd>
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<dt><code>-mlong-calls</code></dt>
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<dt><code>-mno-long-calls</code></dt>
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<dd><a name="index-mlong_002dcalls-3"></a>
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<a name="index-mno_002dlong_002dcalls-1"></a>
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<p>Tells the compiler to perform function calls by first loading the
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address of the function into a register and then performing a subroutine
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call on this register. This switch is needed if the target function
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lies outside of the 24-bit addressing range of the offset-based
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version of subroutine call instruction.
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</p>
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<p>This feature is not enabled by default. Specifying
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<samp>-mno-long-calls</samp> restores the default behavior. Note these
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switches have no effect on how the compiler generates code to handle
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function calls via function pointers.
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</p>
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</dd>
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<dt><code>-mfast-fp</code></dt>
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<dd><a name="index-mfast_002dfp"></a>
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<p>Link with the fast floating-point library. This library relaxes some of
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the IEEE floating-point standard’s rules for checking inputs against
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Not-a-Number (NAN), in the interest of performance.
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</p>
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</dd>
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<dt><code>-minline-plt</code></dt>
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<dd><a name="index-minline_002dplt"></a>
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<p>Enable inlining of PLT entries in function calls to functions that are
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not known to bind locally. It has no effect without <samp>-mfdpic</samp>.
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</p>
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</dd>
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<dt><code>-mmulticore</code></dt>
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<dd><a name="index-mmulticore"></a>
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<p>Build a standalone application for multicore Blackfin processors.
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This option causes proper start files and link scripts supporting
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multicore to be used, and defines the macro <code>__BFIN_MULTICORE</code>.
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It can only be used with <samp>-mcpu=bf561<span class="roman">[</span>-<var>sirevision</var><span class="roman">]</span></samp>.
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</p>
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<p>This option can be used with <samp>-mcorea</samp> or <samp>-mcoreb</samp>, which
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selects the one-application-per-core programming model. Without
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<samp>-mcorea</samp> or <samp>-mcoreb</samp>, the single-application/dual-core
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programming model is used. In this model, the main function of Core B
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should be named as <code>coreb_main</code>.
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</p>
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<p>If this option is not used, the single-core application programming
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model is used.
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</p>
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</dd>
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<dt><code>-mcorea</code></dt>
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<dd><a name="index-mcorea"></a>
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<p>Build a standalone application for Core A of BF561 when using
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the one-application-per-core programming model. Proper start files
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and link scripts are used to support Core A, and the macro
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<code>__BFIN_COREA</code> is defined.
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This option can only be used in conjunction with <samp>-mmulticore</samp>.
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</p>
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</dd>
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<dt><code>-mcoreb</code></dt>
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<dd><a name="index-mcoreb"></a>
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<p>Build a standalone application for Core B of BF561 when using
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the one-application-per-core programming model. Proper start files
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and link scripts are used to support Core B, and the macro
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<code>__BFIN_COREB</code> is defined. When this option is used, <code>coreb_main</code>
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should be used instead of <code>main</code>.
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|
|
This option can only be used in conjunction with <samp>-mmulticore</samp>.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-msdram</code></dt>
|
||
|
|
<dd><a name="index-msdram"></a>
|
||
|
|
<p>Build a standalone application for SDRAM. Proper start files and
|
||
|
|
link scripts are used to put the application into SDRAM, and the macro
|
||
|
|
<code>__BFIN_SDRAM</code> is defined.
|
||
|
|
The loader should initialize SDRAM before loading the application.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-micplb</code></dt>
|
||
|
|
<dd><a name="index-micplb"></a>
|
||
|
|
<p>Assume that ICPLBs are enabled at run time. This has an effect on certain
|
||
|
|
anomaly workarounds. For Linux targets, the default is to assume ICPLBs
|
||
|
|
are enabled; for standalone applications the default is off.
|
||
|
|
</p></dd>
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<hr>
|
||
|
|
<div class="header">
|
||
|
|
<p>
|
||
|
|
Next: <a href="C6X-Options.html#C6X-Options" accesskey="n" rel="next">C6X Options</a>, Previous: <a href="AVR-Options.html#AVR-Options" accesskey="p" rel="prev">AVR Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
|
||
|
|
</div>
|
||
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|
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</body>
|
||
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</html>
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