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263 lines
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263 lines
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HTML
4 years ago
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<html>
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<!-- Copyright (C) 1988-2018 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.3 or
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any later version published by the Free Software Foundation; with the
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Invariant Sections being "Funding Free Software", the Front-Cover
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Texts being (a) (see below), and with the Back-Cover Texts being (b)
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(see below). A copy of the license is included in the section entitled
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"GNU Free Documentation License".
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(a) The FSF's Front-Cover Text is:
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A GNU Manual
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(b) The FSF's Back-Cover Text is:
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You have freedom to copy and modify this GNU Manual, like GNU
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<!-- Created by GNU Texinfo 6.4, http://www.gnu.org/software/texinfo/ -->
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<head>
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<title>Adapteva Epiphany Options (Using the GNU Compiler Collection (GCC))</title>
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<meta name="description" content="Adapteva Epiphany Options (Using the GNU Compiler Collection (GCC))">
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<meta name="keywords" content="Adapteva Epiphany Options (Using the GNU Compiler Collection (GCC))">
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<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
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<link href="index.html#Top" rel="start" title="Top">
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<link href="Option-Index.html#Option-Index" rel="index" title="Option Index">
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<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">
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<link href="Submodel-Options.html#Submodel-Options" rel="up" title="Submodel Options">
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<link href="ARC-Options.html#ARC-Options" rel="next" title="ARC Options">
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<link href="AArch64-Options.html#AArch64-Options" rel="prev" title="AArch64 Options">
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</head>
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<body lang="en">
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<a name="Adapteva-Epiphany-Options"></a>
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<div class="header">
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<p>
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Next: <a href="ARC-Options.html#ARC-Options" accesskey="n" rel="next">ARC Options</a>, Previous: <a href="AArch64-Options.html#AArch64-Options" accesskey="p" rel="prev">AArch64 Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
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</div>
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<hr>
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<a name="Adapteva-Epiphany-Options-1"></a>
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<h4 class="subsection">3.18.2 Adapteva Epiphany Options</h4>
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<p>These ‘<samp>-m</samp>’ options are defined for Adapteva Epiphany:
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</p>
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<dl compact="compact">
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<dt><code>-mhalf-reg-file</code></dt>
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<dd><a name="index-mhalf_002dreg_002dfile"></a>
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<p>Don’t allocate any register in the range <code>r32</code>…<code>r63</code>.
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That allows code to run on hardware variants that lack these registers.
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</p>
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</dd>
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<dt><code>-mprefer-short-insn-regs</code></dt>
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<dd><a name="index-mprefer_002dshort_002dinsn_002dregs"></a>
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<p>Preferentially allocate registers that allow short instruction generation.
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This can result in increased instruction count, so this may either reduce or
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increase overall code size.
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</p>
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</dd>
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<dt><code>-mbranch-cost=<var>num</var></code></dt>
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<dd><a name="index-mbranch_002dcost"></a>
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<p>Set the cost of branches to roughly <var>num</var> “simple” instructions.
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This cost is only a heuristic and is not guaranteed to produce
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consistent results across releases.
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</p>
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</dd>
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<dt><code>-mcmove</code></dt>
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<dd><a name="index-mcmove"></a>
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<p>Enable the generation of conditional moves.
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</p>
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</dd>
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<dt><code>-mnops=<var>num</var></code></dt>
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<dd><a name="index-mnops"></a>
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<p>Emit <var>num</var> NOPs before every other generated instruction.
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</p>
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</dd>
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<dt><code>-mno-soft-cmpsf</code></dt>
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<dd><a name="index-mno_002dsoft_002dcmpsf"></a>
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<p>For single-precision floating-point comparisons, emit an <code>fsub</code> instruction
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and test the flags. This is faster than a software comparison, but can
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get incorrect results in the presence of NaNs, or when two different small
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numbers are compared such that their difference is calculated as zero.
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The default is <samp>-msoft-cmpsf</samp>, which uses slower, but IEEE-compliant,
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software comparisons.
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</p>
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</dd>
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<dt><code>-mstack-offset=<var>num</var></code></dt>
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<dd><a name="index-mstack_002doffset"></a>
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<p>Set the offset between the top of the stack and the stack pointer.
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E.g., a value of 8 means that the eight bytes in the range <code>sp+0…sp+7</code>
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can be used by leaf functions without stack allocation.
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Values other than ‘<samp>8</samp>’ or ‘<samp>16</samp>’ are untested and unlikely to work.
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Note also that this option changes the ABI; compiling a program with a
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different stack offset than the libraries have been compiled with
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generally does not work.
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This option can be useful if you want to evaluate if a different stack
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offset would give you better code, but to actually use a different stack
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offset to build working programs, it is recommended to configure the
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toolchain with the appropriate <samp>--with-stack-offset=<var>num</var></samp> option.
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</p>
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</dd>
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<dt><code>-mno-round-nearest</code></dt>
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<dd><a name="index-mno_002dround_002dnearest"></a>
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<p>Make the scheduler assume that the rounding mode has been set to
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truncating. The default is <samp>-mround-nearest</samp>.
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</p>
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</dd>
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<dt><code>-mlong-calls</code></dt>
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<dd><a name="index-mlong_002dcalls"></a>
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<p>If not otherwise specified by an attribute, assume all calls might be beyond
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the offset range of the <code>b</code> / <code>bl</code> instructions, and therefore load the
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function address into a register before performing a (otherwise direct) call.
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This is the default.
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</p>
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</dd>
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<dt><code>-mshort-calls</code></dt>
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<dd><a name="index-short_002dcalls"></a>
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<p>If not otherwise specified by an attribute, assume all direct calls are
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in the range of the <code>b</code> / <code>bl</code> instructions, so use these instructions
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for direct calls. The default is <samp>-mlong-calls</samp>.
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</p>
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</dd>
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<dt><code>-msmall16</code></dt>
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<dd><a name="index-msmall16"></a>
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<p>Assume addresses can be loaded as 16-bit unsigned values. This does not
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apply to function addresses for which <samp>-mlong-calls</samp> semantics
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are in effect.
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</p>
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</dd>
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<dt><code>-mfp-mode=<var>mode</var></code></dt>
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<dd><a name="index-mfp_002dmode"></a>
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<p>Set the prevailing mode of the floating-point unit.
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This determines the floating-point mode that is provided and expected
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at function call and return time. Making this mode match the mode you
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predominantly need at function start can make your programs smaller and
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faster by avoiding unnecessary mode switches.
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</p>
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<p><var>mode</var> can be set to one the following values:
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</p>
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<dl compact="compact">
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<dt>‘<samp>caller</samp>’</dt>
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<dd><p>Any mode at function entry is valid, and retained or restored when
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the function returns, and when it calls other functions.
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This mode is useful for compiling libraries or other compilation units
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you might want to incorporate into different programs with different
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prevailing FPU modes, and the convenience of being able to use a single
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object file outweighs the size and speed overhead for any extra
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mode switching that might be needed, compared with what would be needed
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with a more specific choice of prevailing FPU mode.
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</p>
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</dd>
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<dt>‘<samp>truncate</samp>’</dt>
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<dd><p>This is the mode used for floating-point calculations with
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truncating (i.e. round towards zero) rounding mode. That includes
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conversion from floating point to integer.
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</p>
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</dd>
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<dt>‘<samp>round-nearest</samp>’</dt>
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<dd><p>This is the mode used for floating-point calculations with
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round-to-nearest-or-even rounding mode.
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</p>
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</dd>
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<dt>‘<samp>int</samp>’</dt>
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<dd><p>This is the mode used to perform integer calculations in the FPU, e.g.
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integer multiply, or integer multiply-and-accumulate.
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</p></dd>
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</dl>
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<p>The default is <samp>-mfp-mode=caller</samp>
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</p>
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</dd>
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<dt><code>-mnosplit-lohi</code></dt>
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<dt><code>-mno-postinc</code></dt>
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<dt><code>-mno-postmodify</code></dt>
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<dd><a name="index-mnosplit_002dlohi"></a>
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<a name="index-mno_002dpostinc"></a>
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<a name="index-mno_002dpostmodify"></a>
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<p>Code generation tweaks that disable, respectively, splitting of 32-bit
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loads, generation of post-increment addresses, and generation of
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post-modify addresses. The defaults are <samp>msplit-lohi</samp>,
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<samp>-mpost-inc</samp>, and <samp>-mpost-modify</samp>.
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</p>
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</dd>
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<dt><code>-mnovect-double</code></dt>
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<dd><a name="index-mno_002dvect_002ddouble"></a>
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<p>Change the preferred SIMD mode to SImode. The default is
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<samp>-mvect-double</samp>, which uses DImode as preferred SIMD mode.
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</p>
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</dd>
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<dt><code>-max-vect-align=<var>num</var></code></dt>
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<dd><a name="index-max_002dvect_002dalign"></a>
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<p>The maximum alignment for SIMD vector mode types.
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<var>num</var> may be 4 or 8. The default is 8.
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Note that this is an ABI change, even though many library function
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interfaces are unaffected if they don’t use SIMD vector modes
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in places that affect size and/or alignment of relevant types.
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</p>
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</dd>
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<dt><code>-msplit-vecmove-early</code></dt>
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<dd><a name="index-msplit_002dvecmove_002dearly"></a>
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<p>Split vector moves into single word moves before reload. In theory this
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can give better register allocation, but so far the reverse seems to be
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generally the case.
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</p>
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</dd>
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<dt><code>-m1reg-<var>reg</var></code></dt>
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<dd><a name="index-m1reg_002d"></a>
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<p>Specify a register to hold the constant -1, which makes loading small negative
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constants and certain bitmasks faster.
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Allowable values for <var>reg</var> are ‘<samp>r43</samp>’ and ‘<samp>r63</samp>’,
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which specify use of that register as a fixed register,
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and ‘<samp>none</samp>’, which means that no register is used for this
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purpose. The default is <samp>-m1reg-none</samp>.
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</p>
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</dd>
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</dl>
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<hr>
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<div class="header">
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<p>
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Next: <a href="ARC-Options.html#ARC-Options" accesskey="n" rel="next">ARC Options</a>, Previous: <a href="AArch64-Options.html#AArch64-Options" accesskey="p" rel="prev">AArch64 Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
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</div>
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</body>
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</html>
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