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984 lines
34 KiB
HTML
984 lines
34 KiB
HTML
4 years ago
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<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
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<html>
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<!-- Copyright (C) 1988-2018 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.3 or
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any later version published by the Free Software Foundation; with the
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Invariant Sections being "Funding Free Software", the Front-Cover
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Texts being (a) (see below), and with the Back-Cover Texts being (b)
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(see below). A copy of the license is included in the section entitled
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"GNU Free Documentation License".
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(a) The FSF's Front-Cover Text is:
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A GNU Manual
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(b) The FSF's Back-Cover Text is:
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You have freedom to copy and modify this GNU Manual, like GNU
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software. Copies published by the Free Software Foundation raise
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funds for GNU development. -->
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<!-- Created by GNU Texinfo 6.4, http://www.gnu.org/software/texinfo/ -->
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<head>
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<title>ARC Options (Using the GNU Compiler Collection (GCC))</title>
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<meta name="description" content="ARC Options (Using the GNU Compiler Collection (GCC))">
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<meta name="keywords" content="ARC Options (Using the GNU Compiler Collection (GCC))">
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<meta name="resource-type" content="document">
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<meta name="distribution" content="global">
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<meta name="Generator" content="makeinfo">
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<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
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<link href="index.html#Top" rel="start" title="Top">
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<link href="Option-Index.html#Option-Index" rel="index" title="Option Index">
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<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">
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<link href="Submodel-Options.html#Submodel-Options" rel="up" title="Submodel Options">
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<link href="ARM-Options.html#ARM-Options" rel="next" title="ARM Options">
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<link href="Adapteva-Epiphany-Options.html#Adapteva-Epiphany-Options" rel="prev" title="Adapteva Epiphany Options">
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<style type="text/css">
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a.summary-letter {text-decoration: none}
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blockquote.smallindentedblock {margin-right: 0em; font-size: smaller}
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blockquote.smallquotation {font-size: smaller}
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div.display {margin-left: 3.2em}
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div.example {margin-left: 3.2em}
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div.lisp {margin-left: 3.2em}
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div.smalldisplay {margin-left: 3.2em}
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div.smalllisp {margin-left: 3.2em}
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kbd {font-style: oblique}
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pre.display {font-family: inherit}
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pre.format {font-family: inherit}
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pre.menu-comment {font-family: serif}
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pre.menu-preformatted {font-family: serif}
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pre.smalldisplay {font-family: inherit; font-size: smaller}
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pre.smallexample {font-size: smaller}
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pre.smallformat {font-family: inherit; font-size: smaller}
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pre.smalllisp {font-size: smaller}
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span.nolinebreak {white-space: nowrap}
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span.roman {font-family: initial; font-weight: normal}
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ul.no-bullet {list-style: none}
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-->
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</style>
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</head>
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<body lang="en">
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<a name="ARC-Options"></a>
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<div class="header">
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<p>
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Next: <a href="ARM-Options.html#ARM-Options" accesskey="n" rel="next">ARM Options</a>, Previous: <a href="Adapteva-Epiphany-Options.html#Adapteva-Epiphany-Options" accesskey="p" rel="prev">Adapteva Epiphany Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
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</div>
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<hr>
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<a name="ARC-Options-1"></a>
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<h4 class="subsection">3.18.3 ARC Options</h4>
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<a name="index-ARC-options"></a>
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<p>The following options control the architecture variant for which code
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is being compiled:
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</p>
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<dl compact="compact">
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<dt><code>-mbarrel-shifter</code></dt>
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<dd><a name="index-mbarrel_002dshifter"></a>
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<p>Generate instructions supported by barrel shifter. This is the default
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unless <samp>-mcpu=ARC601</samp> or ‘<samp>-mcpu=ARCEM</samp>’ is in effect.
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</p>
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</dd>
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<dt><code>-mjli-always</code></dt>
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<dd><a name="index-mjli_002dalawys"></a>
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<p>Force to call a function using jli_s instruction. This option is
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valid only for ARCv2 architecture.
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</p>
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</dd>
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<dt><code>-mcpu=<var>cpu</var></code></dt>
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<dd><a name="index-mcpu-1"></a>
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<p>Set architecture type, register usage, and instruction scheduling
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parameters for <var>cpu</var>. There are also shortcut alias options
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available for backward compatibility and convenience. Supported
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values for <var>cpu</var> are
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</p>
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<dl compact="compact">
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<dd><a name="index-mA6"></a>
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<a name="index-mARC600"></a>
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</dd>
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<dt>‘<samp>arc600</samp>’</dt>
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<dd><p>Compile for ARC600. Aliases: <samp>-mA6</samp>, <samp>-mARC600</samp>.
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</p>
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</dd>
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<dt>‘<samp>arc601</samp>’</dt>
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<dd><a name="index-mARC601"></a>
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<p>Compile for ARC601. Alias: <samp>-mARC601</samp>.
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</p>
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</dd>
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<dt>‘<samp>arc700</samp>’</dt>
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<dd><a name="index-mA7"></a>
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<a name="index-mARC700"></a>
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<p>Compile for ARC700. Aliases: <samp>-mA7</samp>, <samp>-mARC700</samp>.
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This is the default when configured with <samp>--with-cpu=arc700</samp>.
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</p>
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</dd>
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<dt>‘<samp>arcem</samp>’</dt>
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<dd><p>Compile for ARC EM.
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</p>
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</dd>
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<dt>‘<samp>archs</samp>’</dt>
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<dd><p>Compile for ARC HS.
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</p>
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</dd>
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<dt>‘<samp>em</samp>’</dt>
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<dd><p>Compile for ARC EM CPU with no hardware extensions.
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</p>
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</dd>
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<dt>‘<samp>em4</samp>’</dt>
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<dd><p>Compile for ARC EM4 CPU.
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</p>
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</dd>
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<dt>‘<samp>em4_dmips</samp>’</dt>
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<dd><p>Compile for ARC EM4 DMIPS CPU.
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</p>
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</dd>
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<dt>‘<samp>em4_fpus</samp>’</dt>
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<dd><p>Compile for ARC EM4 DMIPS CPU with the single-precision floating-point
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extension.
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</p>
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</dd>
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<dt>‘<samp>em4_fpuda</samp>’</dt>
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<dd><p>Compile for ARC EM4 DMIPS CPU with single-precision floating-point and
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double assist instructions.
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</p>
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</dd>
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<dt>‘<samp>hs</samp>’</dt>
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<dd><p>Compile for ARC HS CPU with no hardware extensions except the atomic
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instructions.
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</p>
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</dd>
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<dt>‘<samp>hs34</samp>’</dt>
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<dd><p>Compile for ARC HS34 CPU.
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</p>
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</dd>
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<dt>‘<samp>hs38</samp>’</dt>
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<dd><p>Compile for ARC HS38 CPU.
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</p>
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</dd>
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<dt>‘<samp>hs38_linux</samp>’</dt>
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<dd><p>Compile for ARC HS38 CPU with all hardware extensions on.
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</p>
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</dd>
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<dt>‘<samp>arc600_norm</samp>’</dt>
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<dd><p>Compile for ARC 600 CPU with <code>norm</code> instructions enabled.
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</p>
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</dd>
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<dt>‘<samp>arc600_mul32x16</samp>’</dt>
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<dd><p>Compile for ARC 600 CPU with <code>norm</code> and 32x16-bit multiply
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instructions enabled.
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</p>
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</dd>
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<dt>‘<samp>arc600_mul64</samp>’</dt>
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<dd><p>Compile for ARC 600 CPU with <code>norm</code> and <code>mul64</code>-family
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instructions enabled.
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||
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</p>
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||
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</dd>
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<dt>‘<samp>arc601_norm</samp>’</dt>
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<dd><p>Compile for ARC 601 CPU with <code>norm</code> instructions enabled.
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||
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</p>
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||
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</dd>
|
||
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<dt>‘<samp>arc601_mul32x16</samp>’</dt>
|
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<dd><p>Compile for ARC 601 CPU with <code>norm</code> and 32x16-bit multiply
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instructions enabled.
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||
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</p>
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||
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</dd>
|
||
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<dt>‘<samp>arc601_mul64</samp>’</dt>
|
||
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<dd><p>Compile for ARC 601 CPU with <code>norm</code> and <code>mul64</code>-family
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instructions enabled.
|
||
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</p>
|
||
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</dd>
|
||
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<dt>‘<samp>nps400</samp>’</dt>
|
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<dd><p>Compile for ARC 700 on NPS400 chip.
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||
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</p>
|
||
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</dd>
|
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<dt>‘<samp>em_mini</samp>’</dt>
|
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<dd><p>Compile for ARC EM minimalist configuration featuring reduced register
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set.
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</p>
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</dd>
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</dl>
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</dd>
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<dt><code>-mdpfp</code></dt>
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<dd><a name="index-mdpfp"></a>
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</dd>
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||
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<dt><code>-mdpfp-compact</code></dt>
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||
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<dd><a name="index-mdpfp_002dcompact"></a>
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<p>Generate double-precision FPX instructions, tuned for the compact
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implementation.
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</p>
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</dd>
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<dt><code>-mdpfp-fast</code></dt>
|
||
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<dd><a name="index-mdpfp_002dfast"></a>
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<p>Generate double-precision FPX instructions, tuned for the fast
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implementation.
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||
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</p>
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</dd>
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<dt><code>-mno-dpfp-lrsr</code></dt>
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<dd><a name="index-mno_002ddpfp_002dlrsr"></a>
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<p>Disable <code>lr</code> and <code>sr</code> instructions from using FPX extension
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aux registers.
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</p>
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||
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</dd>
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<dt><code>-mea</code></dt>
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<dd><a name="index-mea"></a>
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<p>Generate extended arithmetic instructions. Currently only
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<code>divaw</code>, <code>adds</code>, <code>subs</code>, and <code>sat16</code> are
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supported. This is always enabled for <samp>-mcpu=ARC700</samp>.
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</p>
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</dd>
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<dt><code>-mno-mpy</code></dt>
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<dd><a name="index-mno_002dmpy"></a>
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<p>Do not generate <code>mpy</code>-family instructions for ARC700. This option is
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deprecated.
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</p>
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||
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</dd>
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||
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<dt><code>-mmul32x16</code></dt>
|
||
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<dd><a name="index-mmul32x16"></a>
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||
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<p>Generate 32x16-bit multiply and multiply-accumulate instructions.
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</p>
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||
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</dd>
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<dt><code>-mmul64</code></dt>
|
||
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<dd><a name="index-mmul64"></a>
|
||
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<p>Generate <code>mul64</code> and <code>mulu64</code> instructions.
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||
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Only valid for <samp>-mcpu=ARC600</samp>.
|
||
|
|
</p>
|
||
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</dd>
|
||
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<dt><code>-mnorm</code></dt>
|
||
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<dd><a name="index-mnorm"></a>
|
||
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<p>Generate <code>norm</code> instructions. This is the default if <samp>-mcpu=ARC700</samp>
|
||
|
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is in effect.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
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<dt><code>-mspfp</code></dt>
|
||
|
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<dd><a name="index-mspfp"></a>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mspfp-compact</code></dt>
|
||
|
|
<dd><a name="index-mspfp_002dcompact"></a>
|
||
|
|
<p>Generate single-precision FPX instructions, tuned for the compact
|
||
|
|
implementation.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mspfp-fast</code></dt>
|
||
|
|
<dd><a name="index-mspfp_002dfast"></a>
|
||
|
|
<p>Generate single-precision FPX instructions, tuned for the fast
|
||
|
|
implementation.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-msimd</code></dt>
|
||
|
|
<dd><a name="index-msimd"></a>
|
||
|
|
<p>Enable generation of ARC SIMD instructions via target-specific
|
||
|
|
builtins. Only valid for <samp>-mcpu=ARC700</samp>.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-msoft-float</code></dt>
|
||
|
|
<dd><a name="index-msoft_002dfloat"></a>
|
||
|
|
<p>This option ignored; it is provided for compatibility purposes only.
|
||
|
|
Software floating-point code is emitted by default, and this default
|
||
|
|
can overridden by FPX options; <samp>-mspfp</samp>, <samp>-mspfp-compact</samp>, or
|
||
|
|
<samp>-mspfp-fast</samp> for single precision, and <samp>-mdpfp</samp>,
|
||
|
|
<samp>-mdpfp-compact</samp>, or <samp>-mdpfp-fast</samp> for double precision.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mswap</code></dt>
|
||
|
|
<dd><a name="index-mswap"></a>
|
||
|
|
<p>Generate <code>swap</code> instructions.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-matomic</code></dt>
|
||
|
|
<dd><a name="index-matomic"></a>
|
||
|
|
<p>This enables use of the locked load/store conditional extension to implement
|
||
|
|
atomic memory built-in functions. Not available for ARC 6xx or ARC
|
||
|
|
EM cores.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mdiv-rem</code></dt>
|
||
|
|
<dd><a name="index-mdiv_002drem"></a>
|
||
|
|
<p>Enable <code>div</code> and <code>rem</code> instructions for ARCv2 cores.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mcode-density</code></dt>
|
||
|
|
<dd><a name="index-mcode_002ddensity"></a>
|
||
|
|
<p>Enable code density instructions for ARC EM.
|
||
|
|
This option is on by default for ARC HS.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mll64</code></dt>
|
||
|
|
<dd><a name="index-mll64"></a>
|
||
|
|
<p>Enable double load/store operations for ARC HS cores.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mtp-regno=<var>regno</var></code></dt>
|
||
|
|
<dd><a name="index-mtp_002dregno"></a>
|
||
|
|
<p>Specify thread pointer register number.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mmpy-option=<var>multo</var></code></dt>
|
||
|
|
<dd><a name="index-mmpy_002doption"></a>
|
||
|
|
<p>Compile ARCv2 code with a multiplier design option. You can specify
|
||
|
|
the option using either a string or numeric value for <var>multo</var>.
|
||
|
|
‘<samp>wlh1</samp>’ is the default value. The recognized values are:
|
||
|
|
</p>
|
||
|
|
<dl compact="compact">
|
||
|
|
<dt>‘<samp>0</samp>’</dt>
|
||
|
|
<dt>‘<samp>none</samp>’</dt>
|
||
|
|
<dd><p>No multiplier available.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt>‘<samp>1</samp>’</dt>
|
||
|
|
<dt>‘<samp>w</samp>’</dt>
|
||
|
|
<dd><p>16x16 multiplier, fully pipelined.
|
||
|
|
The following instructions are enabled: <code>mpyw</code> and <code>mpyuw</code>.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt>‘<samp>2</samp>’</dt>
|
||
|
|
<dt>‘<samp>wlh1</samp>’</dt>
|
||
|
|
<dd><p>32x32 multiplier, fully
|
||
|
|
pipelined (1 stage). The following instructions are additionally
|
||
|
|
enabled: <code>mpy</code>, <code>mpyu</code>, <code>mpym</code>, <code>mpymu</code>, and <code>mpy_s</code>.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt>‘<samp>3</samp>’</dt>
|
||
|
|
<dt>‘<samp>wlh2</samp>’</dt>
|
||
|
|
<dd><p>32x32 multiplier, fully pipelined
|
||
|
|
(2 stages). The following instructions are additionally enabled: <code>mpy</code>,
|
||
|
|
<code>mpyu</code>, <code>mpym</code>, <code>mpymu</code>, and <code>mpy_s</code>.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt>‘<samp>4</samp>’</dt>
|
||
|
|
<dt>‘<samp>wlh3</samp>’</dt>
|
||
|
|
<dd><p>Two 16x16 multipliers, blocking,
|
||
|
|
sequential. The following instructions are additionally enabled: <code>mpy</code>,
|
||
|
|
<code>mpyu</code>, <code>mpym</code>, <code>mpymu</code>, and <code>mpy_s</code>.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt>‘<samp>5</samp>’</dt>
|
||
|
|
<dt>‘<samp>wlh4</samp>’</dt>
|
||
|
|
<dd><p>One 16x16 multiplier, blocking,
|
||
|
|
sequential. The following instructions are additionally enabled: <code>mpy</code>,
|
||
|
|
<code>mpyu</code>, <code>mpym</code>, <code>mpymu</code>, and <code>mpy_s</code>.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt>‘<samp>6</samp>’</dt>
|
||
|
|
<dt>‘<samp>wlh5</samp>’</dt>
|
||
|
|
<dd><p>One 32x4 multiplier, blocking,
|
||
|
|
sequential. The following instructions are additionally enabled: <code>mpy</code>,
|
||
|
|
<code>mpyu</code>, <code>mpym</code>, <code>mpymu</code>, and <code>mpy_s</code>.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt>‘<samp>7</samp>’</dt>
|
||
|
|
<dt>‘<samp>plus_dmpy</samp>’</dt>
|
||
|
|
<dd><p>ARC HS SIMD support.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt>‘<samp>8</samp>’</dt>
|
||
|
|
<dt>‘<samp>plus_macd</samp>’</dt>
|
||
|
|
<dd><p>ARC HS SIMD support.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt>‘<samp>9</samp>’</dt>
|
||
|
|
<dt>‘<samp>plus_qmacw</samp>’</dt>
|
||
|
|
<dd><p>ARC HS SIMD support.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<p>This option is only available for ARCv2 cores.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mfpu=<var>fpu</var></code></dt>
|
||
|
|
<dd><a name="index-mfpu"></a>
|
||
|
|
<p>Enables support for specific floating-point hardware extensions for ARCv2
|
||
|
|
cores. Supported values for <var>fpu</var> are:
|
||
|
|
</p>
|
||
|
|
<dl compact="compact">
|
||
|
|
<dt>‘<samp>fpus</samp>’</dt>
|
||
|
|
<dd><p>Enables support for single-precision floating-point hardware
|
||
|
|
extensions.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt>‘<samp>fpud</samp>’</dt>
|
||
|
|
<dd><p>Enables support for double-precision floating-point hardware
|
||
|
|
extensions. The single-precision floating-point extension is also
|
||
|
|
enabled. Not available for ARC EM.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt>‘<samp>fpuda</samp>’</dt>
|
||
|
|
<dd><p>Enables support for double-precision floating-point hardware
|
||
|
|
extensions using double-precision assist instructions. The single-precision
|
||
|
|
floating-point extension is also enabled. This option is
|
||
|
|
only available for ARC EM.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt>‘<samp>fpuda_div</samp>’</dt>
|
||
|
|
<dd><p>Enables support for double-precision floating-point hardware
|
||
|
|
extensions using double-precision assist instructions.
|
||
|
|
The single-precision floating-point, square-root, and divide
|
||
|
|
extensions are also enabled. This option is
|
||
|
|
only available for ARC EM.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt>‘<samp>fpuda_fma</samp>’</dt>
|
||
|
|
<dd><p>Enables support for double-precision floating-point hardware
|
||
|
|
extensions using double-precision assist instructions.
|
||
|
|
The single-precision floating-point and fused multiply and add
|
||
|
|
hardware extensions are also enabled. This option is
|
||
|
|
only available for ARC EM.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt>‘<samp>fpuda_all</samp>’</dt>
|
||
|
|
<dd><p>Enables support for double-precision floating-point hardware
|
||
|
|
extensions using double-precision assist instructions.
|
||
|
|
All single-precision floating-point hardware extensions are also
|
||
|
|
enabled. This option is only available for ARC EM.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt>‘<samp>fpus_div</samp>’</dt>
|
||
|
|
<dd><p>Enables support for single-precision floating-point, square-root and divide
|
||
|
|
hardware extensions.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt>‘<samp>fpud_div</samp>’</dt>
|
||
|
|
<dd><p>Enables support for double-precision floating-point, square-root and divide
|
||
|
|
hardware extensions. This option
|
||
|
|
includes option ‘<samp>fpus_div</samp>’. Not available for ARC EM.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt>‘<samp>fpus_fma</samp>’</dt>
|
||
|
|
<dd><p>Enables support for single-precision floating-point and
|
||
|
|
fused multiply and add hardware extensions.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt>‘<samp>fpud_fma</samp>’</dt>
|
||
|
|
<dd><p>Enables support for double-precision floating-point and
|
||
|
|
fused multiply and add hardware extensions. This option
|
||
|
|
includes option ‘<samp>fpus_fma</samp>’. Not available for ARC EM.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt>‘<samp>fpus_all</samp>’</dt>
|
||
|
|
<dd><p>Enables support for all single-precision floating-point hardware
|
||
|
|
extensions.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt>‘<samp>fpud_all</samp>’</dt>
|
||
|
|
<dd><p>Enables support for all single- and double-precision floating-point
|
||
|
|
hardware extensions. Not available for ARC EM.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mirq-ctrl-saved=<var>register-range</var>, <var>blink</var>, <var>lp_count</var></code></dt>
|
||
|
|
<dd><a name="index-mirq_002dctrl_002dsaved"></a>
|
||
|
|
<p>Specifies general-purposes registers that the processor automatically
|
||
|
|
saves/restores on interrupt entry and exit. <var>register-range</var> is
|
||
|
|
specified as two registers separated by a dash. The register range
|
||
|
|
always starts with <code>r0</code>, the upper limit is <code>fp</code> register.
|
||
|
|
<var>blink</var> and <var>lp_count</var> are optional. This option is only
|
||
|
|
valid for ARC EM and ARC HS cores.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mrgf-banked-regs=<var>number</var></code></dt>
|
||
|
|
<dd><a name="index-mrgf_002dbanked_002dregs"></a>
|
||
|
|
<p>Specifies the number of registers replicated in second register bank
|
||
|
|
on entry to fast interrupt. Fast interrupts are interrupts with the
|
||
|
|
highest priority level P0. These interrupts save only PC and STATUS32
|
||
|
|
registers to avoid memory transactions during interrupt entry and exit
|
||
|
|
sequences. Use this option when you are using fast interrupts in an
|
||
|
|
ARC V2 family processor. Permitted values are 4, 8, 16, and 32.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mlpc-width=<var>width</var></code></dt>
|
||
|
|
<dd><a name="index-mlpc_002dwidth"></a>
|
||
|
|
<p>Specify the width of the <code>lp_count</code> register. Valid values for
|
||
|
|
<var>width</var> are 8, 16, 20, 24, 28 and 32 bits. The default width is
|
||
|
|
fixed to 32 bits. If the width is less than 32, the compiler does not
|
||
|
|
attempt to transform loops in your program to use the zero-delay loop
|
||
|
|
mechanism unless it is known that the <code>lp_count</code> register can
|
||
|
|
hold the required loop-counter value. Depending on the width
|
||
|
|
specified, the compiler and run-time library might continue to use the
|
||
|
|
loop mechanism for various needs. This option defines macro
|
||
|
|
<code>__ARC_LPC_WIDTH__</code> with the value of <var>width</var>.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mrf16</code></dt>
|
||
|
|
<dd><a name="index-mrf16"></a>
|
||
|
|
<p>This option instructs the compiler to generate code for a 16-entry
|
||
|
|
register file. This option defines the <code>__ARC_RF16__</code>
|
||
|
|
preprocessor macro.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<p>The following options are passed through to the assembler, and also
|
||
|
|
define preprocessor macro symbols.
|
||
|
|
</p>
|
||
|
|
<dl compact="compact">
|
||
|
|
<dt><code>-mdsp-packa</code></dt>
|
||
|
|
<dd><a name="index-mdsp_002dpacka"></a>
|
||
|
|
<p>Passed down to the assembler to enable the DSP Pack A extensions.
|
||
|
|
Also sets the preprocessor symbol <code>__Xdsp_packa</code>. This option is
|
||
|
|
deprecated.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mdvbf</code></dt>
|
||
|
|
<dd><a name="index-mdvbf"></a>
|
||
|
|
<p>Passed down to the assembler to enable the dual Viterbi butterfly
|
||
|
|
extension. Also sets the preprocessor symbol <code>__Xdvbf</code>. This
|
||
|
|
option is deprecated.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mlock</code></dt>
|
||
|
|
<dd><a name="index-mlock"></a>
|
||
|
|
<p>Passed down to the assembler to enable the locked load/store
|
||
|
|
conditional extension. Also sets the preprocessor symbol
|
||
|
|
<code>__Xlock</code>.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mmac-d16</code></dt>
|
||
|
|
<dd><a name="index-mmac_002dd16"></a>
|
||
|
|
<p>Passed down to the assembler. Also sets the preprocessor symbol
|
||
|
|
<code>__Xxmac_d16</code>. This option is deprecated.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mmac-24</code></dt>
|
||
|
|
<dd><a name="index-mmac_002d24"></a>
|
||
|
|
<p>Passed down to the assembler. Also sets the preprocessor symbol
|
||
|
|
<code>__Xxmac_24</code>. This option is deprecated.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mrtsc</code></dt>
|
||
|
|
<dd><a name="index-mrtsc"></a>
|
||
|
|
<p>Passed down to the assembler to enable the 64-bit time-stamp counter
|
||
|
|
extension instruction. Also sets the preprocessor symbol
|
||
|
|
<code>__Xrtsc</code>. This option is deprecated.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mswape</code></dt>
|
||
|
|
<dd><a name="index-mswape"></a>
|
||
|
|
<p>Passed down to the assembler to enable the swap byte ordering
|
||
|
|
extension instruction. Also sets the preprocessor symbol
|
||
|
|
<code>__Xswape</code>.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mtelephony</code></dt>
|
||
|
|
<dd><a name="index-mtelephony"></a>
|
||
|
|
<p>Passed down to the assembler to enable dual- and single-operand
|
||
|
|
instructions for telephony. Also sets the preprocessor symbol
|
||
|
|
<code>__Xtelephony</code>. This option is deprecated.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mxy</code></dt>
|
||
|
|
<dd><a name="index-mxy"></a>
|
||
|
|
<p>Passed down to the assembler to enable the XY memory extension. Also
|
||
|
|
sets the preprocessor symbol <code>__Xxy</code>.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<p>The following options control how the assembly code is annotated:
|
||
|
|
</p>
|
||
|
|
<dl compact="compact">
|
||
|
|
<dt><code>-misize</code></dt>
|
||
|
|
<dd><a name="index-misize"></a>
|
||
|
|
<p>Annotate assembler instructions with estimated addresses.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mannotate-align</code></dt>
|
||
|
|
<dd><a name="index-mannotate_002dalign"></a>
|
||
|
|
<p>Explain what alignment considerations lead to the decision to make an
|
||
|
|
instruction short or long.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<p>The following options are passed through to the linker:
|
||
|
|
</p>
|
||
|
|
<dl compact="compact">
|
||
|
|
<dt><code>-marclinux</code></dt>
|
||
|
|
<dd><a name="index-marclinux"></a>
|
||
|
|
<p>Passed through to the linker, to specify use of the <code>arclinux</code> emulation.
|
||
|
|
This option is enabled by default in tool chains built for
|
||
|
|
<code><span class="nolinebreak">arc-linux-uclibc</span></code><!-- /@w --> and <code><span class="nolinebreak">arceb-linux-uclibc</span></code><!-- /@w --> targets
|
||
|
|
when profiling is not requested.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-marclinux_prof</code></dt>
|
||
|
|
<dd><a name="index-marclinux_005fprof"></a>
|
||
|
|
<p>Passed through to the linker, to specify use of the
|
||
|
|
<code>arclinux_prof</code> emulation. This option is enabled by default in
|
||
|
|
tool chains built for <code><span class="nolinebreak">arc-linux-uclibc</span></code><!-- /@w --> and
|
||
|
|
<code><span class="nolinebreak">arceb-linux-uclibc</span></code><!-- /@w --> targets when profiling is requested.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<p>The following options control the semantics of generated code:
|
||
|
|
</p>
|
||
|
|
<dl compact="compact">
|
||
|
|
<dt><code>-mlong-calls</code></dt>
|
||
|
|
<dd><a name="index-mlong_002dcalls-1"></a>
|
||
|
|
<p>Generate calls as register indirect calls, thus providing access
|
||
|
|
to the full 32-bit address range.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mmedium-calls</code></dt>
|
||
|
|
<dd><a name="index-mmedium_002dcalls"></a>
|
||
|
|
<p>Don’t use less than 25-bit addressing range for calls, which is the
|
||
|
|
offset available for an unconditional branch-and-link
|
||
|
|
instruction. Conditional execution of function calls is suppressed, to
|
||
|
|
allow use of the 25-bit range, rather than the 21-bit range with
|
||
|
|
conditional branch-and-link. This is the default for tool chains built
|
||
|
|
for <code><span class="nolinebreak">arc-linux-uclibc</span></code><!-- /@w --> and <code><span class="nolinebreak">arceb-linux-uclibc</span></code><!-- /@w --> targets.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-G <var>num</var></code></dt>
|
||
|
|
<dd><a name="index-G"></a>
|
||
|
|
<p>Put definitions of externally-visible data in a small data section if
|
||
|
|
that data is no bigger than <var>num</var> bytes. The default value of
|
||
|
|
<var>num</var> is 4 for any ARC configuration, or 8 when we have double
|
||
|
|
load/store operations.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mno-sdata</code></dt>
|
||
|
|
<dd><a name="index-mno_002dsdata"></a>
|
||
|
|
<p>Do not generate sdata references. This is the default for tool chains
|
||
|
|
built for <code><span class="nolinebreak">arc-linux-uclibc</span></code><!-- /@w --> and <code><span class="nolinebreak">arceb-linux-uclibc</span></code><!-- /@w -->
|
||
|
|
targets.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mvolatile-cache</code></dt>
|
||
|
|
<dd><a name="index-mvolatile_002dcache"></a>
|
||
|
|
<p>Use ordinarily cached memory accesses for volatile references. This is the
|
||
|
|
default.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mno-volatile-cache</code></dt>
|
||
|
|
<dd><a name="index-mno_002dvolatile_002dcache"></a>
|
||
|
|
<p>Enable cache bypass for volatile references.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<p>The following options fine tune code generation:
|
||
|
|
</p><dl compact="compact">
|
||
|
|
<dt><code>-malign-call</code></dt>
|
||
|
|
<dd><a name="index-malign_002dcall"></a>
|
||
|
|
<p>Do alignment optimizations for call instructions.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mauto-modify-reg</code></dt>
|
||
|
|
<dd><a name="index-mauto_002dmodify_002dreg"></a>
|
||
|
|
<p>Enable the use of pre/post modify with register displacement.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mbbit-peephole</code></dt>
|
||
|
|
<dd><a name="index-mbbit_002dpeephole"></a>
|
||
|
|
<p>Enable bbit peephole2.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mno-brcc</code></dt>
|
||
|
|
<dd><a name="index-mno_002dbrcc"></a>
|
||
|
|
<p>This option disables a target-specific pass in <samp>arc_reorg</samp> to
|
||
|
|
generate compare-and-branch (<code>br<var>cc</var></code>) instructions.
|
||
|
|
It has no effect on
|
||
|
|
generation of these instructions driven by the combiner pass.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mcase-vector-pcrel</code></dt>
|
||
|
|
<dd><a name="index-mcase_002dvector_002dpcrel"></a>
|
||
|
|
<p>Use PC-relative switch case tables to enable case table shortening.
|
||
|
|
This is the default for <samp>-Os</samp>.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mcompact-casesi</code></dt>
|
||
|
|
<dd><a name="index-mcompact_002dcasesi"></a>
|
||
|
|
<p>Enable compact <code>casesi</code> pattern. This is the default for <samp>-Os</samp>,
|
||
|
|
and only available for ARCv1 cores.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mno-cond-exec</code></dt>
|
||
|
|
<dd><a name="index-mno_002dcond_002dexec"></a>
|
||
|
|
<p>Disable the ARCompact-specific pass to generate conditional
|
||
|
|
execution instructions.
|
||
|
|
</p>
|
||
|
|
<p>Due to delay slot scheduling and interactions between operand numbers,
|
||
|
|
literal sizes, instruction lengths, and the support for conditional execution,
|
||
|
|
the target-independent pass to generate conditional execution is often lacking,
|
||
|
|
so the ARC port has kept a special pass around that tries to find more
|
||
|
|
conditional execution generation opportunities after register allocation,
|
||
|
|
branch shortening, and delay slot scheduling have been done. This pass
|
||
|
|
generally, but not always, improves performance and code size, at the cost of
|
||
|
|
extra compilation time, which is why there is an option to switch it off.
|
||
|
|
If you have a problem with call instructions exceeding their allowable
|
||
|
|
offset range because they are conditionalized, you should consider using
|
||
|
|
<samp>-mmedium-calls</samp> instead.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mearly-cbranchsi</code></dt>
|
||
|
|
<dd><a name="index-mearly_002dcbranchsi"></a>
|
||
|
|
<p>Enable pre-reload use of the <code>cbranchsi</code> pattern.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mexpand-adddi</code></dt>
|
||
|
|
<dd><a name="index-mexpand_002dadddi"></a>
|
||
|
|
<p>Expand <code>adddi3</code> and <code>subdi3</code> at RTL generation time into
|
||
|
|
<code>add.f</code>, <code>adc</code> etc. This option is deprecated.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mindexed-loads</code></dt>
|
||
|
|
<dd><a name="index-mindexed_002dloads"></a>
|
||
|
|
<p>Enable the use of indexed loads. This can be problematic because some
|
||
|
|
optimizers then assume that indexed stores exist, which is not
|
||
|
|
the case.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mlra</code></dt>
|
||
|
|
<dd><a name="index-mlra"></a>
|
||
|
|
<p>Enable Local Register Allocation. This is still experimental for ARC,
|
||
|
|
so by default the compiler uses standard reload
|
||
|
|
(i.e. <samp>-mno-lra</samp>).
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mlra-priority-none</code></dt>
|
||
|
|
<dd><a name="index-mlra_002dpriority_002dnone"></a>
|
||
|
|
<p>Don’t indicate any priority for target registers.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mlra-priority-compact</code></dt>
|
||
|
|
<dd><a name="index-mlra_002dpriority_002dcompact"></a>
|
||
|
|
<p>Indicate target register priority for r0..r3 / r12..r15.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mlra-priority-noncompact</code></dt>
|
||
|
|
<dd><a name="index-mlra_002dpriority_002dnoncompact"></a>
|
||
|
|
<p>Reduce target register priority for r0..r3 / r12..r15.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mno-millicode</code></dt>
|
||
|
|
<dd><a name="index-mno_002dmillicode"></a>
|
||
|
|
<p>When optimizing for size (using <samp>-Os</samp>), prologues and epilogues
|
||
|
|
that have to save or restore a large number of registers are often
|
||
|
|
shortened by using call to a special function in libgcc; this is
|
||
|
|
referred to as a <em>millicode</em> call. As these calls can pose
|
||
|
|
performance issues, and/or cause linking issues when linking in a
|
||
|
|
nonstandard way, this option is provided to turn off millicode call
|
||
|
|
generation.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mmixed-code</code></dt>
|
||
|
|
<dd><a name="index-mmixed_002dcode"></a>
|
||
|
|
<p>Tweak register allocation to help 16-bit instruction generation.
|
||
|
|
This generally has the effect of decreasing the average instruction size
|
||
|
|
while increasing the instruction count.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mq-class</code></dt>
|
||
|
|
<dd><a name="index-mq_002dclass"></a>
|
||
|
|
<p>Enable ‘<samp>q</samp>’ instruction alternatives.
|
||
|
|
This is the default for <samp>-Os</samp>.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mRcq</code></dt>
|
||
|
|
<dd><a name="index-mRcq"></a>
|
||
|
|
<p>Enable ‘<samp>Rcq</samp>’ constraint handling.
|
||
|
|
Most short code generation depends on this.
|
||
|
|
This is the default.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mRcw</code></dt>
|
||
|
|
<dd><a name="index-mRcw"></a>
|
||
|
|
<p>Enable ‘<samp>Rcw</samp>’ constraint handling.
|
||
|
|
Most ccfsm condexec mostly depends on this.
|
||
|
|
This is the default.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-msize-level=<var>level</var></code></dt>
|
||
|
|
<dd><a name="index-msize_002dlevel"></a>
|
||
|
|
<p>Fine-tune size optimization with regards to instruction lengths and alignment.
|
||
|
|
The recognized values for <var>level</var> are:
|
||
|
|
</p><dl compact="compact">
|
||
|
|
<dt>‘<samp>0</samp>’</dt>
|
||
|
|
<dd><p>No size optimization. This level is deprecated and treated like ‘<samp>1</samp>’.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt>‘<samp>1</samp>’</dt>
|
||
|
|
<dd><p>Short instructions are used opportunistically.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt>‘<samp>2</samp>’</dt>
|
||
|
|
<dd><p>In addition, alignment of loops and of code after barriers are dropped.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt>‘<samp>3</samp>’</dt>
|
||
|
|
<dd><p>In addition, optional data alignment is dropped, and the option <samp>Os</samp> is enabled.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<p>This defaults to ‘<samp>3</samp>’ when <samp>-Os</samp> is in effect. Otherwise,
|
||
|
|
the behavior when this is not set is equivalent to level ‘<samp>1</samp>’.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mtune=<var>cpu</var></code></dt>
|
||
|
|
<dd><a name="index-mtune-1"></a>
|
||
|
|
<p>Set instruction scheduling parameters for <var>cpu</var>, overriding any implied
|
||
|
|
by <samp>-mcpu=</samp>.
|
||
|
|
</p>
|
||
|
|
<p>Supported values for <var>cpu</var> are
|
||
|
|
</p>
|
||
|
|
<dl compact="compact">
|
||
|
|
<dt>‘<samp>ARC600</samp>’</dt>
|
||
|
|
<dd><p>Tune for ARC600 CPU.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt>‘<samp>ARC601</samp>’</dt>
|
||
|
|
<dd><p>Tune for ARC601 CPU.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt>‘<samp>ARC700</samp>’</dt>
|
||
|
|
<dd><p>Tune for ARC700 CPU with standard multiplier block.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt>‘<samp>ARC700-xmac</samp>’</dt>
|
||
|
|
<dd><p>Tune for ARC700 CPU with XMAC block.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt>‘<samp>ARC725D</samp>’</dt>
|
||
|
|
<dd><p>Tune for ARC725D CPU.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt>‘<samp>ARC750D</samp>’</dt>
|
||
|
|
<dd><p>Tune for ARC750D CPU.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mmultcost=<var>num</var></code></dt>
|
||
|
|
<dd><a name="index-mmultcost"></a>
|
||
|
|
<p>Cost to assume for a multiply instruction, with ‘<samp>4</samp>’ being equal to a
|
||
|
|
normal instruction.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-munalign-prob-threshold=<var>probability</var></code></dt>
|
||
|
|
<dd><a name="index-munalign_002dprob_002dthreshold"></a>
|
||
|
|
<p>Set probability threshold for unaligning branches.
|
||
|
|
When tuning for ‘<samp>ARC700</samp>’ and optimizing for speed, branches without
|
||
|
|
filled delay slot are preferably emitted unaligned and long, unless
|
||
|
|
profiling indicates that the probability for the branch to be taken
|
||
|
|
is below <var>probability</var>. See <a href="Cross_002dprofiling.html#Cross_002dprofiling">Cross-profiling</a>.
|
||
|
|
The default is (REG_BR_PROB_BASE/2), i.e. 5000.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<p>The following options are maintained for backward compatibility, but
|
||
|
|
are now deprecated and will be removed in a future release:
|
||
|
|
</p>
|
||
|
|
<dl compact="compact">
|
||
|
|
<dt><code>-margonaut</code></dt>
|
||
|
|
<dd><a name="index-margonaut"></a>
|
||
|
|
<p>Obsolete FPX.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mbig-endian</code></dt>
|
||
|
|
<dd><a name="index-mbig_002dendian-1"></a>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-EB</code></dt>
|
||
|
|
<dd><a name="index-EB"></a>
|
||
|
|
<p>Compile code for big-endian targets. Use of these options is now
|
||
|
|
deprecated. Big-endian code is supported by configuring GCC to build
|
||
|
|
<code><span class="nolinebreak">arceb-elf32</span></code><!-- /@w --> and <code><span class="nolinebreak">arceb-linux-uclibc</span></code><!-- /@w --> targets,
|
||
|
|
for which big endian is the default.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mlittle-endian</code></dt>
|
||
|
|
<dd><a name="index-mlittle_002dendian-1"></a>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-EL</code></dt>
|
||
|
|
<dd><a name="index-EL"></a>
|
||
|
|
<p>Compile code for little-endian targets. Use of these options is now
|
||
|
|
deprecated. Little-endian code is supported by configuring GCC to build
|
||
|
|
<code><span class="nolinebreak">arc-elf32</span></code><!-- /@w --> and <code><span class="nolinebreak">arc-linux-uclibc</span></code><!-- /@w --> targets,
|
||
|
|
for which little endian is the default.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mbarrel_shifter</code></dt>
|
||
|
|
<dd><a name="index-mbarrel_005fshifter"></a>
|
||
|
|
<p>Replaced by <samp>-mbarrel-shifter</samp>.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mdpfp_compact</code></dt>
|
||
|
|
<dd><a name="index-mdpfp_005fcompact"></a>
|
||
|
|
<p>Replaced by <samp>-mdpfp-compact</samp>.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mdpfp_fast</code></dt>
|
||
|
|
<dd><a name="index-mdpfp_005ffast"></a>
|
||
|
|
<p>Replaced by <samp>-mdpfp-fast</samp>.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mdsp_packa</code></dt>
|
||
|
|
<dd><a name="index-mdsp_005fpacka"></a>
|
||
|
|
<p>Replaced by <samp>-mdsp-packa</samp>.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mEA</code></dt>
|
||
|
|
<dd><a name="index-mEA"></a>
|
||
|
|
<p>Replaced by <samp>-mea</samp>.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mmac_24</code></dt>
|
||
|
|
<dd><a name="index-mmac_005f24"></a>
|
||
|
|
<p>Replaced by <samp>-mmac-24</samp>.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mmac_d16</code></dt>
|
||
|
|
<dd><a name="index-mmac_005fd16"></a>
|
||
|
|
<p>Replaced by <samp>-mmac-d16</samp>.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mspfp_compact</code></dt>
|
||
|
|
<dd><a name="index-mspfp_005fcompact"></a>
|
||
|
|
<p>Replaced by <samp>-mspfp-compact</samp>.
|
||
|
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</p>
|
||
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</dd>
|
||
|
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<dt><code>-mspfp_fast</code></dt>
|
||
|
|
<dd><a name="index-mspfp_005ffast"></a>
|
||
|
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<p>Replaced by <samp>-mspfp-fast</samp>.
|
||
|
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</p>
|
||
|
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</dd>
|
||
|
|
<dt><code>-mtune=<var>cpu</var></code></dt>
|
||
|
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<dd><a name="index-mtune-2"></a>
|
||
|
|
<p>Values ‘<samp>arc600</samp>’, ‘<samp>arc601</samp>’, ‘<samp>arc700</samp>’ and
|
||
|
|
‘<samp>arc700-xmac</samp>’ for <var>cpu</var> are replaced by ‘<samp>ARC600</samp>’,
|
||
|
|
‘<samp>ARC601</samp>’, ‘<samp>ARC700</samp>’ and ‘<samp>ARC700-xmac</samp>’ respectively.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
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<dt><code>-multcost=<var>num</var></code></dt>
|
||
|
|
<dd><a name="index-multcost"></a>
|
||
|
|
<p>Replaced by <samp>-mmultcost</samp>.
|
||
|
|
</p>
|
||
|
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</dd>
|
||
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</dl>
|
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<hr>
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<div class="header">
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||
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<p>
|
||
|
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Next: <a href="ARM-Options.html#ARM-Options" accesskey="n" rel="next">ARM Options</a>, Previous: <a href="Adapteva-Epiphany-Options.html#Adapteva-Epiphany-Options" accesskey="p" rel="prev">Adapteva Epiphany Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
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</div>
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</body>
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</html>
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