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193 lines
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HTML
4 years ago
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<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
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<html>
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<!-- This file documents the GNU Assembler "as".
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Copyright (C) 1991-2019 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.3
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or any later version published by the Free Software Foundation;
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with no Invariant Sections, with no Front-Cover Texts, and with no
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Back-Cover Texts. A copy of the license is included in the
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section entitled "GNU Free Documentation License".
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<!-- Created by GNU Texinfo 6.4, http://www.gnu.org/software/texinfo/ -->
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<head>
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<title>i386-Mnemonics (Using as)</title>
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<meta name="description" content="i386-Mnemonics (Using as)">
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<meta name="keywords" content="i386-Mnemonics (Using as)">
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<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
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<link href="index.html#Top" rel="start" title="Top">
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<link href="AS-Index.html#AS-Index" rel="index" title="AS Index">
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<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">
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<link href="i386_002dDependent.html#i386_002dDependent" rel="up" title="i386-Dependent">
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<link href="i386_002dRegs.html#i386_002dRegs" rel="next" title="i386-Regs">
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<link href="i386_002dChars.html#i386_002dChars" rel="prev" title="i386-Chars">
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</head>
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<body lang="en">
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<a name="i386_002dMnemonics"></a>
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<div class="header">
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<p>
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Next: <a href="i386_002dRegs.html#i386_002dRegs" accesskey="n" rel="next">i386-Regs</a>, Previous: <a href="i386_002dSyntax.html#i386_002dSyntax" accesskey="p" rel="prev">i386-Syntax</a>, Up: <a href="i386_002dDependent.html#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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</div>
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<hr>
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<a name="i386_002dMnemonics-1"></a>
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<h4 class="subsection">9.15.4 i386-Mnemonics</h4>
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<a name="Instruction-Naming"></a>
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<h4 class="subsubsection">9.15.4.1 Instruction Naming</h4>
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<a name="index-i386-instruction-naming"></a>
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<a name="index-instruction-naming_002c-i386"></a>
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<a name="index-x86_002d64-instruction-naming"></a>
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<a name="index-instruction-naming_002c-x86_002d64"></a>
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<p>Instruction mnemonics are suffixed with one character modifiers which
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specify the size of operands. The letters ‘<samp>b</samp>’, ‘<samp>w</samp>’, ‘<samp>l</samp>’
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and ‘<samp>q</samp>’ specify byte, word, long and quadruple word operands. If
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no suffix is specified by an instruction then <code>as</code> tries to
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fill in the missing suffix based on the destination register operand
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(the last one by convention). Thus, ‘<samp>mov %ax, %bx</samp>’ is equivalent
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to ‘<samp>movw %ax, %bx</samp>’; also, ‘<samp>mov $1, %bx</samp>’ is equivalent to
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‘<samp>movw $1, bx</samp>’. Note that this is incompatible with the AT&T Unix
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assembler which assumes that a missing mnemonic suffix implies long
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operand size. (This incompatibility does not affect compiler output
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since compilers always explicitly specify the mnemonic suffix.)
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</p>
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<p>Almost all instructions have the same names in AT&T and Intel format.
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There are a few exceptions. The sign extend and zero extend
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instructions need two sizes to specify them. They need a size to
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sign/zero extend <em>from</em> and a size to zero extend <em>to</em>. This
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is accomplished by using two instruction mnemonic suffixes in AT&T
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syntax. Base names for sign extend and zero extend are
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‘<samp>movs…</samp>’ and ‘<samp>movz…</samp>’ in AT&T syntax (‘<samp>movsx</samp>’
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and ‘<samp>movzx</samp>’ in Intel syntax). The instruction mnemonic suffixes
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are tacked on to this base name, the <em>from</em> suffix before the
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<em>to</em> suffix. Thus, ‘<samp>movsbl %al, %edx</samp>’ is AT&T syntax for
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“move sign extend <em>from</em> %al <em>to</em> %edx.” Possible suffixes,
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thus, are ‘<samp>bl</samp>’ (from byte to long), ‘<samp>bw</samp>’ (from byte to word),
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‘<samp>wl</samp>’ (from word to long), ‘<samp>bq</samp>’ (from byte to quadruple word),
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‘<samp>wq</samp>’ (from word to quadruple word), and ‘<samp>lq</samp>’ (from long to
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quadruple word).
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</p>
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<a name="index-encoding-options_002c-i386"></a>
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<a name="index-encoding-options_002c-x86_002d64"></a>
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<p>Different encoding options can be specified via pseudo prefixes:
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</p>
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<ul>
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<li> ‘<samp>{disp8}</samp>’ – prefer 8-bit displacement.
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</li><li> ‘<samp>{disp32}</samp>’ – prefer 32-bit displacement.
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</li><li> ‘<samp>{load}</samp>’ – prefer load-form instruction.
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</li><li> ‘<samp>{store}</samp>’ – prefer store-form instruction.
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</li><li> ‘<samp>{vex2}</samp>’ – prefer 2-byte VEX prefix for VEX instruction.
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</li><li> ‘<samp>{vex3}</samp>’ – prefer 3-byte VEX prefix for VEX instruction.
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</li><li> ‘<samp>{evex}</samp>’ – encode with EVEX prefix.
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</li><li> ‘<samp>{rex}</samp>’ – prefer REX prefix for integer and legacy vector
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instructions (x86-64 only). Note that this differs from the ‘<samp>rex</samp>’
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prefix which generates REX prefix unconditionally.
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</li><li> ‘<samp>{nooptimize}</samp>’ – disable instruction size optimization.
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</li></ul>
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<a name="index-conversion-instructions_002c-i386"></a>
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<a name="index-i386-conversion-instructions"></a>
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<a name="index-conversion-instructions_002c-x86_002d64"></a>
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<a name="index-x86_002d64-conversion-instructions"></a>
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<p>The Intel-syntax conversion instructions
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</p>
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<ul>
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<li> ‘<samp>cbw</samp>’ — sign-extend byte in ‘<samp>%al</samp>’ to word in ‘<samp>%ax</samp>’,
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</li><li> ‘<samp>cwde</samp>’ — sign-extend word in ‘<samp>%ax</samp>’ to long in ‘<samp>%eax</samp>’,
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</li><li> ‘<samp>cwd</samp>’ — sign-extend word in ‘<samp>%ax</samp>’ to long in ‘<samp>%dx:%ax</samp>’,
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</li><li> ‘<samp>cdq</samp>’ — sign-extend dword in ‘<samp>%eax</samp>’ to quad in ‘<samp>%edx:%eax</samp>’,
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</li><li> ‘<samp>cdqe</samp>’ — sign-extend dword in ‘<samp>%eax</samp>’ to quad in ‘<samp>%rax</samp>’
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(x86-64 only),
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</li><li> ‘<samp>cqo</samp>’ — sign-extend quad in ‘<samp>%rax</samp>’ to octuple in
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‘<samp>%rdx:%rax</samp>’ (x86-64 only),
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</li></ul>
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<p>are called ‘<samp>cbtw</samp>’, ‘<samp>cwtl</samp>’, ‘<samp>cwtd</samp>’, ‘<samp>cltd</samp>’, ‘<samp>cltq</samp>’, and
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‘<samp>cqto</samp>’ in AT&T naming. <code>as</code> accepts either naming for these
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instructions.
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</p>
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<a name="index-jump-instructions_002c-i386"></a>
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<a name="index-call-instructions_002c-i386"></a>
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<a name="index-jump-instructions_002c-x86_002d64"></a>
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<a name="index-call-instructions_002c-x86_002d64"></a>
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<p>Far call/jump instructions are ‘<samp>lcall</samp>’ and ‘<samp>ljmp</samp>’ in
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AT&T syntax, but are ‘<samp>call far</samp>’ and ‘<samp>jump far</samp>’ in Intel
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convention.
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</p>
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<a name="AT_0026T-Mnemonic-versus-Intel-Mnemonic"></a>
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<h4 class="subsubsection">9.15.4.2 AT&T Mnemonic versus Intel Mnemonic</h4>
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<a name="index-i386-mnemonic-compatibility"></a>
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<a name="index-mnemonic-compatibility_002c-i386"></a>
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<p><code>as</code> supports assembly using Intel mnemonic.
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<code>.intel_mnemonic</code> selects Intel mnemonic with Intel syntax, and
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<code>.att_mnemonic</code> switches back to the usual AT&T mnemonic with AT&T
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syntax for compatibility with the output of <code>gcc</code>.
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Several x87 instructions, ‘<samp>fadd</samp>’, ‘<samp>fdiv</samp>’, ‘<samp>fdivp</samp>’,
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‘<samp>fdivr</samp>’, ‘<samp>fdivrp</samp>’, ‘<samp>fmul</samp>’, ‘<samp>fsub</samp>’, ‘<samp>fsubp</samp>’,
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‘<samp>fsubr</samp>’ and ‘<samp>fsubrp</samp>’, are implemented in AT&T System V/386
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assembler with different mnemonics from those in Intel IA32 specification.
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<code>gcc</code> generates those instructions with AT&T mnemonic.
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</p>
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<hr>
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<div class="header">
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<p>
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Next: <a href="i386_002dRegs.html#i386_002dRegs" accesskey="n" rel="next">i386-Regs</a>, Previous: <a href="i386_002dSyntax.html#i386_002dSyntax" accesskey="p" rel="prev">i386-Syntax</a>, Up: <a href="i386_002dDependent.html#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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</div>
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