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238 lines
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HTML
4 years ago
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<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
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<!-- This file documents the GNU Assembler "as".
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Copyright (C) 1991-2019 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.3
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or any later version published by the Free Software Foundation;
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with no Invariant Sections, with no Front-Cover Texts, and with no
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<!-- Created by GNU Texinfo 6.4, http://www.gnu.org/software/texinfo/ -->
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<head>
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<title>Sparc-Opts (Using as)</title>
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<meta name="description" content="Sparc-Opts (Using as)">
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<meta name="keywords" content="Sparc-Opts (Using as)">
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<link href="index.html#Top" rel="start" title="Top">
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<link href="AS-Index.html#AS-Index" rel="index" title="AS Index">
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<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">
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<link href="Sparc_002dDependent.html#Sparc_002dDependent" rel="up" title="Sparc-Dependent">
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<link href="Sparc_002dAligned_002dData.html#Sparc_002dAligned_002dData" rel="next" title="Sparc-Aligned-Data">
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<link href="Sparc_002dDependent.html#Sparc_002dDependent" rel="prev" title="Sparc-Dependent">
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</head>
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<body lang="en">
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<a name="Sparc_002dOpts"></a>
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<div class="header">
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<p>
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Next: <a href="Sparc_002dAligned_002dData.html#Sparc_002dAligned_002dData" accesskey="n" rel="next">Sparc-Aligned-Data</a>, Up: <a href="Sparc_002dDependent.html#Sparc_002dDependent" accesskey="u" rel="up">Sparc-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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</div>
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<hr>
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<a name="Options-23"></a>
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<h4 class="subsection">9.43.1 Options</h4>
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<a name="index-options-for-SPARC"></a>
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<a name="index-SPARC-options"></a>
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<a name="index-architectures_002c-SPARC"></a>
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<a name="index-SPARC-architectures"></a>
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<p>The SPARC chip family includes several successive versions, using the same
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core instruction set, but including a few additional instructions at
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each version. There are exceptions to this however. For details on what
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instructions each variant supports, please see the chip’s architecture
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reference manual.
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</p>
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<p>By default, <code>as</code> assumes the core instruction set (SPARC
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v6), but “bumps” the architecture level as needed: it switches to
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successively higher architectures as it encounters instructions that
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only exist in the higher levels.
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</p>
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<p>If not configured for SPARC v9 (<code>sparc64-*-*</code>) GAS will not bump
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past sparclite by default, an option must be passed to enable the
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v9 instructions.
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</p>
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<p>GAS treats sparclite as being compatible with v8, unless an architecture
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is explicitly requested. SPARC v9 is always incompatible with sparclite.
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</p>
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<dl compact="compact">
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<dd><a name="index-_002dAv6"></a>
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<a name="index-_002dAv7"></a>
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<a name="index-_002dAv8"></a>
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<a name="index-_002dAleon"></a>
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<a name="index-_002dAsparclet"></a>
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<a name="index-_002dAsparclite"></a>
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<a name="index-_002dAv9"></a>
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<a name="index-_002dAv9a"></a>
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<a name="index-_002dAv9b"></a>
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<a name="index-_002dAv9c"></a>
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<a name="index-_002dAv9d"></a>
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<a name="index-_002dAv9e"></a>
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<a name="index-_002dAv9v"></a>
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<a name="index-_002dAv9m"></a>
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<a name="index-_002dAsparc"></a>
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<a name="index-_002dAsparcvis"></a>
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<a name="index-_002dAsparcvis2"></a>
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<a name="index-_002dAsparcfmaf"></a>
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<a name="index-_002dAsparcima"></a>
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<a name="index-_002dAsparcvis3"></a>
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<a name="index-_002dAsparcvis3r"></a>
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</dd>
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<dt><code>-Av6 | -Av7 | -Av8 | -Aleon | -Asparclet | -Asparclite</code></dt>
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<dt><code>-Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd |</code></dt>
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<dt><code>-Av8plusv | -Av8plusm | -Av8plusm8</code></dt>
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<dt><code>-Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9e | -Av9v | -Av9m | -Av9m8</code></dt>
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<dt><code>-Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima</code></dt>
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<dt><code>-Asparcvis3 | -Asparcvis3r | -Asparc5 | -Asparc6</code></dt>
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<dd><p>Use one of the ‘<samp>-A</samp>’ options to select one of the SPARC
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architectures explicitly. If you select an architecture explicitly,
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<code>as</code> reports a fatal error if it encounters an instruction
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or feature requiring an incompatible or higher level.
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</p>
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<p>‘<samp>-Av8plus</samp>’, ‘<samp>-Av8plusa</samp>’, ‘<samp>-Av8plusb</samp>’, ‘<samp>-Av8plusc</samp>’,
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‘<samp>-Av8plusd</samp>’, and ‘<samp>-Av8plusv</samp>’ select a 32 bit environment.
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</p>
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<p>‘<samp>-Av9</samp>’, ‘<samp>-Av9a</samp>’, ‘<samp>-Av9b</samp>’, ‘<samp>-Av9c</samp>’, ‘<samp>-Av9d</samp>’,
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‘<samp>-Av9e</samp>’, ‘<samp>-Av9v</samp>’ and ‘<samp>-Av9m</samp>’ select a 64 bit
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environment and are not available unless GAS is explicitly configured
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with 64 bit environment support.
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</p>
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<p>‘<samp>-Av8plusa</samp>’ and ‘<samp>-Av9a</samp>’ enable the SPARC V9 instruction set with
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UltraSPARC VIS 1.0 extensions.
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</p>
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<p>‘<samp>-Av8plusb</samp>’ and ‘<samp>-Av9b</samp>’ enable the UltraSPARC VIS 2.0 instructions,
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as well as the instructions enabled by ‘<samp>-Av8plusa</samp>’ and ‘<samp>-Av9a</samp>’.
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</p>
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<p>‘<samp>-Av8plusc</samp>’ and ‘<samp>-Av9c</samp>’ enable the UltraSPARC Niagara instructions,
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as well as the instructions enabled by ‘<samp>-Av8plusb</samp>’ and ‘<samp>-Av9b</samp>’.
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</p>
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<p>‘<samp>-Av8plusd</samp>’ and ‘<samp>-Av9d</samp>’ enable the floating point fused
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multiply-add, VIS 3.0, and HPC extension instructions, as well as the
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instructions enabled by ‘<samp>-Av8plusc</samp>’ and ‘<samp>-Av9c</samp>’.
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</p>
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<p>‘<samp>-Av8pluse</samp>’ and ‘<samp>-Av9e</samp>’ enable the cryptographic
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instructions, as well as the instructions enabled by ‘<samp>-Av8plusd</samp>’
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and ‘<samp>-Av9d</samp>’.
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</p>
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<p>‘<samp>-Av8plusv</samp>’ and ‘<samp>-Av9v</samp>’ enable floating point unfused
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multiply-add, and integer multiply-add, as well as the instructions
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enabled by ‘<samp>-Av8pluse</samp>’ and ‘<samp>-Av9e</samp>’.
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</p>
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<p>‘<samp>-Av8plusm</samp>’ and ‘<samp>-Av9m</samp>’ enable the VIS 4.0, subtract extended,
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xmpmul, xmontmul and xmontsqr instructions, as well as the instructions
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enabled by ‘<samp>-Av8plusv</samp>’ and ‘<samp>-Av9v</samp>’.
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</p>
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<p>‘<samp>-Av8plusm8</samp>’ and ‘<samp>-Av9m8</samp>’ enable the instructions introduced
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in the Oracle SPARC Architecture 2017 and the M8 processor, as
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well as the instructions enabled by ‘<samp>-Av8plusm</samp>’ and ‘<samp>-Av9m</samp>’.
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</p>
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<p>‘<samp>-Asparc</samp>’ specifies a v9 environment. It is equivalent to
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‘<samp>-Av9</samp>’ if the word size is 64-bit, and ‘<samp>-Av8plus</samp>’ otherwise.
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</p>
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<p>‘<samp>-Asparcvis</samp>’ specifies a v9a environment. It is equivalent to
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‘<samp>-Av9a</samp>’ if the word size is 64-bit, and ‘<samp>-Av8plusa</samp>’ otherwise.
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</p>
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<p>‘<samp>-Asparcvis2</samp>’ specifies a v9b environment. It is equivalent to
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‘<samp>-Av9b</samp>’ if the word size is 64-bit, and ‘<samp>-Av8plusb</samp>’ otherwise.
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</p>
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<p>‘<samp>-Asparcfmaf</samp>’ specifies a v9b environment with the floating point
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fused multiply-add instructions enabled.
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</p>
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<p>‘<samp>-Asparcima</samp>’ specifies a v9b environment with the integer
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multiply-add instructions enabled.
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</p>
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<p>‘<samp>-Asparcvis3</samp>’ specifies a v9b environment with the VIS 3.0,
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HPC , and floating point fused multiply-add instructions enabled.
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</p>
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<p>‘<samp>-Asparcvis3r</samp>’ specifies a v9b environment with the VIS 3.0, HPC,
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and floating point unfused multiply-add instructions enabled.
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</p>
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<p>‘<samp>-Asparc5</samp>’ is equivalent to ‘<samp>-Av9m</samp>’.
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</p>
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<p>‘<samp>-Asparc6</samp>’ is equivalent to ‘<samp>-Av9m8</samp>’.
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</p>
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</dd>
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<dt><code>-xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc</code></dt>
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<dt><code>-xarch=v8plusd | -xarch=v8plusv | -xarch=v8plusm |</code></dt>
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<dt><code>-xarch=v8plusm8 | -xarch=v9 | -xarch=v9a | -xarch=v9b</code></dt>
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<dt><code>-xarch=v9c | -xarch=v9d | -xarch=v9e | -xarch=v9v</code></dt>
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<dt><code>-xarch=v9m | -xarch=v9m8</code></dt>
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<dt><code>-xarch=sparc | -xarch=sparcvis | -xarch=sparcvis2</code></dt>
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<dt><code>-xarch=sparcfmaf | -xarch=sparcima | -xarch=sparcvis3</code></dt>
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<dt><code>-xarch=sparcvis3r | -xarch=sparc5 | -xarch=sparc6</code></dt>
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<dd><p>For compatibility with the SunOS v9 assembler. These options are
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equivalent to -Av8plus, -Av8plusa, -Av8plusb, -Av8plusc, -Av8plusd,
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-Av8plusv, -Av8plusm, -Av8plusm8, -Av9, -Av9a, -Av9b, -Av9c, -Av9d,
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-Av9e, -Av9v, -Av9m, -Av9m8, -Asparc, -Asparcvis, -Asparcvis2,
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-Asparcfmaf, -Asparcima, -Asparcvis3, -Asparcvis3r, -Asparc5 and
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-Asparc6 respectively.
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</p>
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</dd>
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<dt><code>-bump</code></dt>
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<dd><p>Warn whenever it is necessary to switch to another level.
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If an architecture level is explicitly requested, GAS will not issue
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warnings until that level is reached, and will then bump the level
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as required (except between incompatible levels).
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</p>
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</dd>
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<dt><code>-32 | -64</code></dt>
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<dd><p>Select the word size, either 32 bits or 64 bits.
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These options are only available with the ELF object file format,
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and require that the necessary BFD support has been included.
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</p>
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</dd>
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<dt><code>--dcti-couples-detect</code></dt>
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<dd><p>Warn if a DCTI (delayed control transfer instruction) couple is found
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when generating code for a variant of the SPARC architecture in which
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the execution of the couple is unpredictable, or very slow. This is
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disabled by default.
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</p></dd>
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</dl>
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<hr>
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<div class="header">
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<p>
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Next: <a href="Sparc_002dAligned_002dData.html#Sparc_002dAligned_002dData" accesskey="n" rel="next">Sparc-Aligned-Data</a>, Up: <a href="Sparc_002dDependent.html#Sparc_002dDependent" accesskey="u" rel="up">Sparc-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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</div>
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</body>
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</html>
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