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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_0e02049879cfa95c4b33945e3bf1e6f2.html">pio</a></li> </ul>
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<div class="title">same54n20a.h File Reference</div> </div>
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<p>Peripheral I/O description for SAME54N20A.
<a href="#details">More...</a></p>
<p><a href="pio_2same54n20a_8h_source.html">Go to the source code of this file.</a></p>
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Macros</h2></td></tr>
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<tr class="memitem:a0d86f5c542131de55bff6d9ba96ae4fb"><td class="memItemLeft" align="right" valign="top"><a id="a0d86f5c542131de55bff6d9ba96ae4fb"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0d86f5c542131de55bff6d9ba96ae4fb">PORT_PA11</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 11)</td></tr>
<tr class="memdesc:a0d86f5c542131de55bff6d9ba96ae4fb"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PA11. <br /></td></tr>
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<tr class="memitem:a2ffb0dfd383bdc2f6e8f41a9ef0d4955"><td class="memItemLeft" align="right" valign="top"><a id="a2ffb0dfd383bdc2f6e8f41a9ef0d4955"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2ffb0dfd383bdc2f6e8f41a9ef0d4955">PIN_PA12</a>&#160;&#160;&#160;12</td></tr>
<tr class="memdesc:a2ffb0dfd383bdc2f6e8f41a9ef0d4955"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PA12. <br /></td></tr>
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<tr class="memitem:a484876b223a5e7f3f58eb14a32e69295"><td class="memItemLeft" align="right" valign="top"><a id="a484876b223a5e7f3f58eb14a32e69295"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a484876b223a5e7f3f58eb14a32e69295">PORT_PA12</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 12)</td></tr>
<tr class="memdesc:a484876b223a5e7f3f58eb14a32e69295"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PA12. <br /></td></tr>
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<tr class="memitem:a4180bdc6fd7252cff2ffe28176866028"><td class="memItemLeft" align="right" valign="top"><a id="a4180bdc6fd7252cff2ffe28176866028"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4180bdc6fd7252cff2ffe28176866028">PIN_PA13</a>&#160;&#160;&#160;13</td></tr>
<tr class="memdesc:a4180bdc6fd7252cff2ffe28176866028"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PA13. <br /></td></tr>
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<tr class="memitem:aec93b60ace96611ab9e9a926eafc7e2e"><td class="memItemLeft" align="right" valign="top"><a id="aec93b60ace96611ab9e9a926eafc7e2e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aec93b60ace96611ab9e9a926eafc7e2e">PORT_PA13</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 13)</td></tr>
<tr class="memdesc:aec93b60ace96611ab9e9a926eafc7e2e"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PA13. <br /></td></tr>
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<tr class="memitem:ad71083de279943a97f0a159c824c290b"><td class="memItemLeft" align="right" valign="top"><a id="ad71083de279943a97f0a159c824c290b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad71083de279943a97f0a159c824c290b">PIN_PA14</a>&#160;&#160;&#160;14</td></tr>
<tr class="memdesc:ad71083de279943a97f0a159c824c290b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PA14. <br /></td></tr>
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<tr class="memitem:a93290c47fdda2baa183e0540d79dda0c"><td class="memItemLeft" align="right" valign="top"><a id="a93290c47fdda2baa183e0540d79dda0c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a93290c47fdda2baa183e0540d79dda0c">PORT_PA14</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 14)</td></tr>
<tr class="memdesc:a93290c47fdda2baa183e0540d79dda0c"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PA14. <br /></td></tr>
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<tr class="memitem:abaad308f0408bf5d3f1fe558f3d26e5e"><td class="memItemLeft" align="right" valign="top"><a id="abaad308f0408bf5d3f1fe558f3d26e5e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#abaad308f0408bf5d3f1fe558f3d26e5e">PIN_PA15</a>&#160;&#160;&#160;15</td></tr>
<tr class="memdesc:abaad308f0408bf5d3f1fe558f3d26e5e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PA15. <br /></td></tr>
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<tr class="memitem:ad3db381b789793febb5224d4d6d98584"><td class="memItemLeft" align="right" valign="top"><a id="ad3db381b789793febb5224d4d6d98584"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad3db381b789793febb5224d4d6d98584">PORT_PA15</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 15)</td></tr>
<tr class="memdesc:ad3db381b789793febb5224d4d6d98584"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PA15. <br /></td></tr>
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<tr class="memitem:af95063d900dacae04c7700184f817d88"><td class="memItemLeft" align="right" valign="top"><a id="af95063d900dacae04c7700184f817d88"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af95063d900dacae04c7700184f817d88">PIN_PA16</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:af95063d900dacae04c7700184f817d88"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PA16. <br /></td></tr>
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<tr class="memitem:ab60c2f0e015476f7dd36d8a522deab85"><td class="memItemLeft" align="right" valign="top"><a id="ab60c2f0e015476f7dd36d8a522deab85"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab60c2f0e015476f7dd36d8a522deab85">PORT_PA16</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 16)</td></tr>
<tr class="memdesc:ab60c2f0e015476f7dd36d8a522deab85"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PA16. <br /></td></tr>
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<tr class="memitem:a66f8d032baf3fb0bc60f2dc70ef0e587"><td class="memItemLeft" align="right" valign="top"><a id="a66f8d032baf3fb0bc60f2dc70ef0e587"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a66f8d032baf3fb0bc60f2dc70ef0e587">PIN_PA17</a>&#160;&#160;&#160;17</td></tr>
<tr class="memdesc:a66f8d032baf3fb0bc60f2dc70ef0e587"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PA17. <br /></td></tr>
<tr class="separator:a66f8d032baf3fb0bc60f2dc70ef0e587"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a54d352801be55a1f99b1bd17e7183702"><td class="memItemLeft" align="right" valign="top"><a id="a54d352801be55a1f99b1bd17e7183702"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a54d352801be55a1f99b1bd17e7183702">PORT_PA17</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 17)</td></tr>
<tr class="memdesc:a54d352801be55a1f99b1bd17e7183702"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PA17. <br /></td></tr>
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<tr class="memitem:a9695bdcd8129ad83a871ad6b259dfcd5"><td class="memItemLeft" align="right" valign="top"><a id="a9695bdcd8129ad83a871ad6b259dfcd5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a9695bdcd8129ad83a871ad6b259dfcd5">PIN_PA18</a>&#160;&#160;&#160;18</td></tr>
<tr class="memdesc:a9695bdcd8129ad83a871ad6b259dfcd5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PA18. <br /></td></tr>
<tr class="separator:a9695bdcd8129ad83a871ad6b259dfcd5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adfd9c418c179cff56c445c46e6b15a25"><td class="memItemLeft" align="right" valign="top"><a id="adfd9c418c179cff56c445c46e6b15a25"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#adfd9c418c179cff56c445c46e6b15a25">PORT_PA18</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 18)</td></tr>
<tr class="memdesc:adfd9c418c179cff56c445c46e6b15a25"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PA18. <br /></td></tr>
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<tr class="memitem:a58254064b915fd09ca35601ceebcf27f"><td class="memItemLeft" align="right" valign="top"><a id="a58254064b915fd09ca35601ceebcf27f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a58254064b915fd09ca35601ceebcf27f">PIN_PA19</a>&#160;&#160;&#160;19</td></tr>
<tr class="memdesc:a58254064b915fd09ca35601ceebcf27f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PA19. <br /></td></tr>
<tr class="separator:a58254064b915fd09ca35601ceebcf27f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa6c67ad40f0ffeef27f4a4fc7b1bb9f7"><td class="memItemLeft" align="right" valign="top"><a id="aa6c67ad40f0ffeef27f4a4fc7b1bb9f7"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa6c67ad40f0ffeef27f4a4fc7b1bb9f7">PORT_PA19</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 19)</td></tr>
<tr class="memdesc:aa6c67ad40f0ffeef27f4a4fc7b1bb9f7"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PA19. <br /></td></tr>
<tr class="separator:aa6c67ad40f0ffeef27f4a4fc7b1bb9f7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a00c77a5c19a99cee2402fc83b04c02d5"><td class="memItemLeft" align="right" valign="top"><a id="a00c77a5c19a99cee2402fc83b04c02d5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a00c77a5c19a99cee2402fc83b04c02d5">PIN_PA20</a>&#160;&#160;&#160;20</td></tr>
<tr class="memdesc:a00c77a5c19a99cee2402fc83b04c02d5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PA20. <br /></td></tr>
<tr class="separator:a00c77a5c19a99cee2402fc83b04c02d5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aba99808fe0ae7db4067a8ffdd4eba36b"><td class="memItemLeft" align="right" valign="top"><a id="aba99808fe0ae7db4067a8ffdd4eba36b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aba99808fe0ae7db4067a8ffdd4eba36b">PORT_PA20</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 20)</td></tr>
<tr class="memdesc:aba99808fe0ae7db4067a8ffdd4eba36b"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PA20. <br /></td></tr>
<tr class="separator:aba99808fe0ae7db4067a8ffdd4eba36b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af985624239bfbec119533432376256b8"><td class="memItemLeft" align="right" valign="top"><a id="af985624239bfbec119533432376256b8"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af985624239bfbec119533432376256b8">PIN_PA21</a>&#160;&#160;&#160;21</td></tr>
<tr class="memdesc:af985624239bfbec119533432376256b8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PA21. <br /></td></tr>
<tr class="separator:af985624239bfbec119533432376256b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a99affd47a6238969d3f2775cd75818a9"><td class="memItemLeft" align="right" valign="top"><a id="a99affd47a6238969d3f2775cd75818a9"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a99affd47a6238969d3f2775cd75818a9">PORT_PA21</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 21)</td></tr>
<tr class="memdesc:a99affd47a6238969d3f2775cd75818a9"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PA21. <br /></td></tr>
<tr class="separator:a99affd47a6238969d3f2775cd75818a9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac9cc1f345184e86b5481800a38f67b73"><td class="memItemLeft" align="right" valign="top"><a id="ac9cc1f345184e86b5481800a38f67b73"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac9cc1f345184e86b5481800a38f67b73">PIN_PA22</a>&#160;&#160;&#160;22</td></tr>
<tr class="memdesc:ac9cc1f345184e86b5481800a38f67b73"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PA22. <br /></td></tr>
<tr class="separator:ac9cc1f345184e86b5481800a38f67b73"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a91346dac1f98836d316f1a38aea7cbd6"><td class="memItemLeft" align="right" valign="top"><a id="a91346dac1f98836d316f1a38aea7cbd6"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a91346dac1f98836d316f1a38aea7cbd6">PORT_PA22</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 22)</td></tr>
<tr class="memdesc:a91346dac1f98836d316f1a38aea7cbd6"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PA22. <br /></td></tr>
<tr class="separator:a91346dac1f98836d316f1a38aea7cbd6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6ca014c55f45ce023918c585433c67af"><td class="memItemLeft" align="right" valign="top"><a id="a6ca014c55f45ce023918c585433c67af"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6ca014c55f45ce023918c585433c67af">PIN_PA23</a>&#160;&#160;&#160;23</td></tr>
<tr class="memdesc:a6ca014c55f45ce023918c585433c67af"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PA23. <br /></td></tr>
<tr class="separator:a6ca014c55f45ce023918c585433c67af"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3de7ac24ce6b0e80e842e55d41250842"><td class="memItemLeft" align="right" valign="top"><a id="a3de7ac24ce6b0e80e842e55d41250842"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3de7ac24ce6b0e80e842e55d41250842">PORT_PA23</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 23)</td></tr>
<tr class="memdesc:a3de7ac24ce6b0e80e842e55d41250842"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PA23. <br /></td></tr>
<tr class="separator:a3de7ac24ce6b0e80e842e55d41250842"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abee6df88d9fba25b98a4421947f6b358"><td class="memItemLeft" align="right" valign="top"><a id="abee6df88d9fba25b98a4421947f6b358"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#abee6df88d9fba25b98a4421947f6b358">PIN_PA24</a>&#160;&#160;&#160;24</td></tr>
<tr class="memdesc:abee6df88d9fba25b98a4421947f6b358"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PA24. <br /></td></tr>
<tr class="separator:abee6df88d9fba25b98a4421947f6b358"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6d0bd987a61b4fc97aa25d05fe08ceb6"><td class="memItemLeft" align="right" valign="top"><a id="a6d0bd987a61b4fc97aa25d05fe08ceb6"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6d0bd987a61b4fc97aa25d05fe08ceb6">PORT_PA24</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 24)</td></tr>
<tr class="memdesc:a6d0bd987a61b4fc97aa25d05fe08ceb6"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PA24. <br /></td></tr>
<tr class="separator:a6d0bd987a61b4fc97aa25d05fe08ceb6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abf0af39e3f1759f7806d7d4678c1652b"><td class="memItemLeft" align="right" valign="top"><a id="abf0af39e3f1759f7806d7d4678c1652b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#abf0af39e3f1759f7806d7d4678c1652b">PIN_PA25</a>&#160;&#160;&#160;25</td></tr>
<tr class="memdesc:abf0af39e3f1759f7806d7d4678c1652b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PA25. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0b41284cc6b961106eb1bc1f2d885421">PORT_PA25</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 25)</td></tr>
<tr class="memdesc:a0b41284cc6b961106eb1bc1f2d885421"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PA25. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3794cc9242203d349103ba1249e5d587">PIN_PA27</a>&#160;&#160;&#160;27</td></tr>
<tr class="memdesc:a3794cc9242203d349103ba1249e5d587"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PA27. <br /></td></tr>
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<tr class="memitem:a2fc26d65fb6c211495737354784f321c"><td class="memItemLeft" align="right" valign="top"><a id="a2fc26d65fb6c211495737354784f321c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2fc26d65fb6c211495737354784f321c">PORT_PA27</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 27)</td></tr>
<tr class="memdesc:a2fc26d65fb6c211495737354784f321c"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PA27. <br /></td></tr>
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<tr class="memitem:aabc7384a581a9f8558c32585582f1be1"><td class="memItemLeft" align="right" valign="top"><a id="aabc7384a581a9f8558c32585582f1be1"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aabc7384a581a9f8558c32585582f1be1">PIN_PA30</a>&#160;&#160;&#160;30</td></tr>
<tr class="memdesc:aabc7384a581a9f8558c32585582f1be1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PA30. <br /></td></tr>
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<tr class="memitem:a8b04708887ae99c0822c2ef30c210cde"><td class="memItemLeft" align="right" valign="top"><a id="a8b04708887ae99c0822c2ef30c210cde"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8b04708887ae99c0822c2ef30c210cde">PORT_PA30</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 30)</td></tr>
<tr class="memdesc:a8b04708887ae99c0822c2ef30c210cde"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PA30. <br /></td></tr>
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<tr class="memitem:a151d10c7fdacaac78b00e59dee16cd6f"><td class="memItemLeft" align="right" valign="top"><a id="a151d10c7fdacaac78b00e59dee16cd6f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a151d10c7fdacaac78b00e59dee16cd6f">PIN_PA31</a>&#160;&#160;&#160;31</td></tr>
<tr class="memdesc:a151d10c7fdacaac78b00e59dee16cd6f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PA31. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a667ef2f989f05c60028945244e000274">PORT_PA31</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 31)</td></tr>
<tr class="memdesc:a667ef2f989f05c60028945244e000274"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PA31. <br /></td></tr>
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<tr class="memitem:aaee350eaf010d48a2c6efae0a1632f7c"><td class="memItemLeft" align="right" valign="top"><a id="aaee350eaf010d48a2c6efae0a1632f7c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aaee350eaf010d48a2c6efae0a1632f7c">PIN_PB00</a>&#160;&#160;&#160;32</td></tr>
<tr class="memdesc:aaee350eaf010d48a2c6efae0a1632f7c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PB00. <br /></td></tr>
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<tr class="memitem:a24a20b3fea76e7a8b04d12dec26cb027"><td class="memItemLeft" align="right" valign="top"><a id="a24a20b3fea76e7a8b04d12dec26cb027"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a24a20b3fea76e7a8b04d12dec26cb027">PORT_PB00</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 0)</td></tr>
<tr class="memdesc:a24a20b3fea76e7a8b04d12dec26cb027"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PB00. <br /></td></tr>
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<tr class="memitem:aa599b1c1a8440ecffbf5fba215984c75"><td class="memItemLeft" align="right" valign="top"><a id="aa599b1c1a8440ecffbf5fba215984c75"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa599b1c1a8440ecffbf5fba215984c75">PIN_PB01</a>&#160;&#160;&#160;33</td></tr>
<tr class="memdesc:aa599b1c1a8440ecffbf5fba215984c75"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PB01. <br /></td></tr>
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<tr class="memitem:a3e6fdff2c294277f350d50fd2c68bab3"><td class="memItemLeft" align="right" valign="top"><a id="a3e6fdff2c294277f350d50fd2c68bab3"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3e6fdff2c294277f350d50fd2c68bab3">PORT_PB01</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 1)</td></tr>
<tr class="memdesc:a3e6fdff2c294277f350d50fd2c68bab3"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PB01. <br /></td></tr>
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<tr class="memitem:a19ef30fcec1b8ad27ff954975a005850"><td class="memItemLeft" align="right" valign="top"><a id="a19ef30fcec1b8ad27ff954975a005850"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a19ef30fcec1b8ad27ff954975a005850">PIN_PB02</a>&#160;&#160;&#160;34</td></tr>
<tr class="memdesc:a19ef30fcec1b8ad27ff954975a005850"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PB02. <br /></td></tr>
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<tr class="memitem:ab203d5081034b1a5ed00cc6dc17ae95d"><td class="memItemLeft" align="right" valign="top"><a id="ab203d5081034b1a5ed00cc6dc17ae95d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab203d5081034b1a5ed00cc6dc17ae95d">PORT_PB02</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 2)</td></tr>
<tr class="memdesc:ab203d5081034b1a5ed00cc6dc17ae95d"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PB02. <br /></td></tr>
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<tr class="memitem:ab8f19878aac1648cb688cfcf0eec3fb5"><td class="memItemLeft" align="right" valign="top"><a id="ab8f19878aac1648cb688cfcf0eec3fb5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab8f19878aac1648cb688cfcf0eec3fb5">PIN_PB03</a>&#160;&#160;&#160;35</td></tr>
<tr class="memdesc:ab8f19878aac1648cb688cfcf0eec3fb5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PB03. <br /></td></tr>
<tr class="separator:ab8f19878aac1648cb688cfcf0eec3fb5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a15fc59f02619ede74c6b608a5a16ef62"><td class="memItemLeft" align="right" valign="top"><a id="a15fc59f02619ede74c6b608a5a16ef62"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a15fc59f02619ede74c6b608a5a16ef62">PORT_PB03</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 3)</td></tr>
<tr class="memdesc:a15fc59f02619ede74c6b608a5a16ef62"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PB03. <br /></td></tr>
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<tr class="memitem:ab4f72feca4eed2b50fb246dc2d59241d"><td class="memItemLeft" align="right" valign="top"><a id="ab4f72feca4eed2b50fb246dc2d59241d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab4f72feca4eed2b50fb246dc2d59241d">PIN_PB04</a>&#160;&#160;&#160;36</td></tr>
<tr class="memdesc:ab4f72feca4eed2b50fb246dc2d59241d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PB04. <br /></td></tr>
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<tr class="memitem:ab5ff6aadaa17e6ce8d11529ddb86e913"><td class="memItemLeft" align="right" valign="top"><a id="ab5ff6aadaa17e6ce8d11529ddb86e913"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab5ff6aadaa17e6ce8d11529ddb86e913">PORT_PB04</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 4)</td></tr>
<tr class="memdesc:ab5ff6aadaa17e6ce8d11529ddb86e913"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PB04. <br /></td></tr>
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<tr class="memitem:ae62ed501d1f5f6cdc6bf605742aeb778"><td class="memItemLeft" align="right" valign="top"><a id="ae62ed501d1f5f6cdc6bf605742aeb778"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae62ed501d1f5f6cdc6bf605742aeb778">PIN_PB05</a>&#160;&#160;&#160;37</td></tr>
<tr class="memdesc:ae62ed501d1f5f6cdc6bf605742aeb778"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PB05. <br /></td></tr>
<tr class="separator:ae62ed501d1f5f6cdc6bf605742aeb778"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5829d2e80f94c709ce3c81cd96eba594"><td class="memItemLeft" align="right" valign="top"><a id="a5829d2e80f94c709ce3c81cd96eba594"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5829d2e80f94c709ce3c81cd96eba594">PORT_PB05</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 5)</td></tr>
<tr class="memdesc:a5829d2e80f94c709ce3c81cd96eba594"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PB05. <br /></td></tr>
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<tr class="memitem:a342eea40b1bafb1afe71ff68854d9747"><td class="memItemLeft" align="right" valign="top"><a id="a342eea40b1bafb1afe71ff68854d9747"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a342eea40b1bafb1afe71ff68854d9747">PIN_PB06</a>&#160;&#160;&#160;38</td></tr>
<tr class="memdesc:a342eea40b1bafb1afe71ff68854d9747"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PB06. <br /></td></tr>
<tr class="separator:a342eea40b1bafb1afe71ff68854d9747"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aaec9efecd9a29f2cfc1f4099c79efcd7"><td class="memItemLeft" align="right" valign="top"><a id="aaec9efecd9a29f2cfc1f4099c79efcd7"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aaec9efecd9a29f2cfc1f4099c79efcd7">PORT_PB06</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 6)</td></tr>
<tr class="memdesc:aaec9efecd9a29f2cfc1f4099c79efcd7"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PB06. <br /></td></tr>
<tr class="separator:aaec9efecd9a29f2cfc1f4099c79efcd7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a381a8ad61ecb02a4d455cd92a5a5fb1e"><td class="memItemLeft" align="right" valign="top"><a id="a381a8ad61ecb02a4d455cd92a5a5fb1e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a381a8ad61ecb02a4d455cd92a5a5fb1e">PIN_PB07</a>&#160;&#160;&#160;39</td></tr>
<tr class="memdesc:a381a8ad61ecb02a4d455cd92a5a5fb1e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PB07. <br /></td></tr>
<tr class="separator:a381a8ad61ecb02a4d455cd92a5a5fb1e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a90db5e987c3e8d9bf6d07aca7ed3ca93"><td class="memItemLeft" align="right" valign="top"><a id="a90db5e987c3e8d9bf6d07aca7ed3ca93"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a90db5e987c3e8d9bf6d07aca7ed3ca93">PORT_PB07</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 7)</td></tr>
<tr class="memdesc:a90db5e987c3e8d9bf6d07aca7ed3ca93"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PB07. <br /></td></tr>
<tr class="separator:a90db5e987c3e8d9bf6d07aca7ed3ca93"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8b8f5e8b769787a4ce5a9b53388acc0e"><td class="memItemLeft" align="right" valign="top"><a id="a8b8f5e8b769787a4ce5a9b53388acc0e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8b8f5e8b769787a4ce5a9b53388acc0e">PIN_PB08</a>&#160;&#160;&#160;40</td></tr>
<tr class="memdesc:a8b8f5e8b769787a4ce5a9b53388acc0e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PB08. <br /></td></tr>
<tr class="separator:a8b8f5e8b769787a4ce5a9b53388acc0e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8f41524b9dee7a9ed113322b5f8e2663"><td class="memItemLeft" align="right" valign="top"><a id="a8f41524b9dee7a9ed113322b5f8e2663"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8f41524b9dee7a9ed113322b5f8e2663">PORT_PB08</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 8)</td></tr>
<tr class="memdesc:a8f41524b9dee7a9ed113322b5f8e2663"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PB08. <br /></td></tr>
<tr class="separator:a8f41524b9dee7a9ed113322b5f8e2663"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a123a2189653c39f91fc0231945166826"><td class="memItemLeft" align="right" valign="top"><a id="a123a2189653c39f91fc0231945166826"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a123a2189653c39f91fc0231945166826">PIN_PB09</a>&#160;&#160;&#160;41</td></tr>
<tr class="memdesc:a123a2189653c39f91fc0231945166826"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PB09. <br /></td></tr>
<tr class="separator:a123a2189653c39f91fc0231945166826"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2306731061c4957fb522091fab1fcbde"><td class="memItemLeft" align="right" valign="top"><a id="a2306731061c4957fb522091fab1fcbde"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2306731061c4957fb522091fab1fcbde">PORT_PB09</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 9)</td></tr>
<tr class="memdesc:a2306731061c4957fb522091fab1fcbde"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PB09. <br /></td></tr>
<tr class="separator:a2306731061c4957fb522091fab1fcbde"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ace5077df47f85d8716961068d23999f9"><td class="memItemLeft" align="right" valign="top"><a id="ace5077df47f85d8716961068d23999f9"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ace5077df47f85d8716961068d23999f9">PIN_PB10</a>&#160;&#160;&#160;42</td></tr>
<tr class="memdesc:ace5077df47f85d8716961068d23999f9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PB10. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0b997f045f6040bd59acdef30f6f7110">PORT_PB10</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa67c3fe74fde6a524858a0dd54809391">PIN_PB11</a>&#160;&#160;&#160;43</td></tr>
<tr class="memdesc:aa67c3fe74fde6a524858a0dd54809391"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PB11. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1ccf3cd8ad10fc9741c4b312067ddc79">PORT_PB11</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 11)</td></tr>
<tr class="memdesc:a1ccf3cd8ad10fc9741c4b312067ddc79"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PB11. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4c73054a65245b26b8d56438c269a5f8">PIN_PB12</a>&#160;&#160;&#160;44</td></tr>
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<tr class="memitem:ad7faa5aa61654ec1cc9b73c6c891e63d"><td class="memItemLeft" align="right" valign="top"><a id="ad7faa5aa61654ec1cc9b73c6c891e63d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad7faa5aa61654ec1cc9b73c6c891e63d">PORT_PB12</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aac822122271e05b08d918692cd81ebe9">PIN_PB13</a>&#160;&#160;&#160;45</td></tr>
<tr class="memdesc:aac822122271e05b08d918692cd81ebe9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PB13. <br /></td></tr>
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<tr class="memitem:ab8c288952382d41b0f988263f2431f5e"><td class="memItemLeft" align="right" valign="top"><a id="ab8c288952382d41b0f988263f2431f5e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab8c288952382d41b0f988263f2431f5e">PORT_PB13</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 13)</td></tr>
<tr class="memdesc:ab8c288952382d41b0f988263f2431f5e"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PB13. <br /></td></tr>
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<tr class="memitem:a886b07fd0b01a62c7236bfac719c0d85"><td class="memItemLeft" align="right" valign="top"><a id="a886b07fd0b01a62c7236bfac719c0d85"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a886b07fd0b01a62c7236bfac719c0d85">PIN_PB14</a>&#160;&#160;&#160;46</td></tr>
<tr class="memdesc:a886b07fd0b01a62c7236bfac719c0d85"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PB14. <br /></td></tr>
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<tr class="memitem:a32bc1dd688c97d54a2a9e9d34f1e5cc3"><td class="memItemLeft" align="right" valign="top"><a id="a32bc1dd688c97d54a2a9e9d34f1e5cc3"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a32bc1dd688c97d54a2a9e9d34f1e5cc3">PORT_PB14</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2dfe52fc70c0fa20c50efcb5260b7f6e">PIN_PB15</a>&#160;&#160;&#160;47</td></tr>
<tr class="memdesc:a2dfe52fc70c0fa20c50efcb5260b7f6e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PB15. <br /></td></tr>
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<tr class="memitem:af09dfb22f84aca0ec53dd7c0354ea5a8"><td class="memItemLeft" align="right" valign="top"><a id="af09dfb22f84aca0ec53dd7c0354ea5a8"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af09dfb22f84aca0ec53dd7c0354ea5a8">PORT_PB15</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 15)</td></tr>
<tr class="memdesc:af09dfb22f84aca0ec53dd7c0354ea5a8"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PB15. <br /></td></tr>
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<tr class="memitem:a2638b944d2f382c990e0a4c6810aea1e"><td class="memItemLeft" align="right" valign="top"><a id="a2638b944d2f382c990e0a4c6810aea1e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2638b944d2f382c990e0a4c6810aea1e">PIN_PB16</a>&#160;&#160;&#160;48</td></tr>
<tr class="memdesc:a2638b944d2f382c990e0a4c6810aea1e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PB16. <br /></td></tr>
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<tr class="memitem:a78ca7ff8dfdbaaaac7d25499b54dcc19"><td class="memItemLeft" align="right" valign="top"><a id="a78ca7ff8dfdbaaaac7d25499b54dcc19"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a78ca7ff8dfdbaaaac7d25499b54dcc19">PORT_PB16</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 16)</td></tr>
<tr class="memdesc:a78ca7ff8dfdbaaaac7d25499b54dcc19"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PB16. <br /></td></tr>
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<tr class="memitem:a7589e10e4bc65e51d370b6fb985d8f2c"><td class="memItemLeft" align="right" valign="top"><a id="a7589e10e4bc65e51d370b6fb985d8f2c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7589e10e4bc65e51d370b6fb985d8f2c">PIN_PB17</a>&#160;&#160;&#160;49</td></tr>
<tr class="memdesc:a7589e10e4bc65e51d370b6fb985d8f2c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PB17. <br /></td></tr>
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<tr class="memitem:acdd1bb42d5a959b7f69d87d8b491d28e"><td class="memItemLeft" align="right" valign="top"><a id="acdd1bb42d5a959b7f69d87d8b491d28e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#acdd1bb42d5a959b7f69d87d8b491d28e">PORT_PB17</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 17)</td></tr>
<tr class="memdesc:acdd1bb42d5a959b7f69d87d8b491d28e"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PB17. <br /></td></tr>
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<tr class="memitem:a5b1dde7ce3380c9ccaebded4d6169a8a"><td class="memItemLeft" align="right" valign="top"><a id="a5b1dde7ce3380c9ccaebded4d6169a8a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5b1dde7ce3380c9ccaebded4d6169a8a">PIN_PB18</a>&#160;&#160;&#160;50</td></tr>
<tr class="memdesc:a5b1dde7ce3380c9ccaebded4d6169a8a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PB18. <br /></td></tr>
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<tr class="memitem:a80afd65b4a2022a58f03ee893c4093a7"><td class="memItemLeft" align="right" valign="top"><a id="a80afd65b4a2022a58f03ee893c4093a7"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a80afd65b4a2022a58f03ee893c4093a7">PORT_PB18</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 18)</td></tr>
<tr class="memdesc:a80afd65b4a2022a58f03ee893c4093a7"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PB18. <br /></td></tr>
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<tr class="memitem:acc8605a048a9bed0bef57e14d7443cd2"><td class="memItemLeft" align="right" valign="top"><a id="acc8605a048a9bed0bef57e14d7443cd2"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#acc8605a048a9bed0bef57e14d7443cd2">PIN_PB19</a>&#160;&#160;&#160;51</td></tr>
<tr class="memdesc:acc8605a048a9bed0bef57e14d7443cd2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PB19. <br /></td></tr>
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<tr class="memitem:aeb3e0516ff8cd5e6cddfac6deccd6618"><td class="memItemLeft" align="right" valign="top"><a id="aeb3e0516ff8cd5e6cddfac6deccd6618"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aeb3e0516ff8cd5e6cddfac6deccd6618">PORT_PB19</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 19)</td></tr>
<tr class="memdesc:aeb3e0516ff8cd5e6cddfac6deccd6618"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PB19. <br /></td></tr>
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<tr class="memitem:af7836380ea76d57950f3bf4237e778c9"><td class="memItemLeft" align="right" valign="top"><a id="af7836380ea76d57950f3bf4237e778c9"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af7836380ea76d57950f3bf4237e778c9">PIN_PB20</a>&#160;&#160;&#160;52</td></tr>
<tr class="memdesc:af7836380ea76d57950f3bf4237e778c9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PB20. <br /></td></tr>
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<tr class="memitem:a6b03947ff8645b11acba69970ceaad46"><td class="memItemLeft" align="right" valign="top"><a id="a6b03947ff8645b11acba69970ceaad46"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6b03947ff8645b11acba69970ceaad46">PORT_PB20</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 20)</td></tr>
<tr class="memdesc:a6b03947ff8645b11acba69970ceaad46"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PB20. <br /></td></tr>
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<tr class="memitem:a03a2942cf80fd3bd4dcbac6cd406a2a0"><td class="memItemLeft" align="right" valign="top"><a id="a03a2942cf80fd3bd4dcbac6cd406a2a0"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a03a2942cf80fd3bd4dcbac6cd406a2a0">PIN_PB21</a>&#160;&#160;&#160;53</td></tr>
<tr class="memdesc:a03a2942cf80fd3bd4dcbac6cd406a2a0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PB21. <br /></td></tr>
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<tr class="memitem:a8e399c6b3ff8105829beca75120784a8"><td class="memItemLeft" align="right" valign="top"><a id="a8e399c6b3ff8105829beca75120784a8"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8e399c6b3ff8105829beca75120784a8">PORT_PB21</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 21)</td></tr>
<tr class="memdesc:a8e399c6b3ff8105829beca75120784a8"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PB21. <br /></td></tr>
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<tr class="memitem:a5f8249fb7d7568f6ac27dd4e38171724"><td class="memItemLeft" align="right" valign="top"><a id="a5f8249fb7d7568f6ac27dd4e38171724"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5f8249fb7d7568f6ac27dd4e38171724">PIN_PB22</a>&#160;&#160;&#160;54</td></tr>
<tr class="memdesc:a5f8249fb7d7568f6ac27dd4e38171724"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PB22. <br /></td></tr>
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<tr class="memitem:a95a4b81bf0cc07bbb8a655b9ddf26a72"><td class="memItemLeft" align="right" valign="top"><a id="a95a4b81bf0cc07bbb8a655b9ddf26a72"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a95a4b81bf0cc07bbb8a655b9ddf26a72">PORT_PB22</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 22)</td></tr>
<tr class="memdesc:a95a4b81bf0cc07bbb8a655b9ddf26a72"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PB22. <br /></td></tr>
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<tr class="memitem:a78443bb5df689db4f8d87386e31775db"><td class="memItemLeft" align="right" valign="top"><a id="a78443bb5df689db4f8d87386e31775db"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a78443bb5df689db4f8d87386e31775db">PIN_PB23</a>&#160;&#160;&#160;55</td></tr>
<tr class="memdesc:a78443bb5df689db4f8d87386e31775db"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PB23. <br /></td></tr>
<tr class="separator:a78443bb5df689db4f8d87386e31775db"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a91aa71a43b5c03cfde8f8f8957a7bcbe"><td class="memItemLeft" align="right" valign="top"><a id="a91aa71a43b5c03cfde8f8f8957a7bcbe"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a91aa71a43b5c03cfde8f8f8957a7bcbe">PORT_PB23</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 23)</td></tr>
<tr class="memdesc:a91aa71a43b5c03cfde8f8f8957a7bcbe"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PB23. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a717e2ab04772dbf3c0e00416a5e373d4">PIN_PB24</a>&#160;&#160;&#160;56</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae1b80241734d6ccb2ffe2a96d25fe0f7">PORT_PB24</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 24)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab7eb0e34282b5fbcd617566cb8ce47f8">PIN_PB25</a>&#160;&#160;&#160;57</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a69f2f7dbd3584ce22441ca4c3033106e">PORT_PB25</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 25)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5ff751a11f710f459e0ccb12b6db3e29">PIN_PB30</a>&#160;&#160;&#160;62</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a72a0012b6ea518e8159189ee2168a78d">PIN_PB31</a>&#160;&#160;&#160;63</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa83c53d5443d75e444f99bfb30ba6fac">PORT_PB31</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 31)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aff1ff6d0b345cc4df265248e7477fbe1">PIN_PC00</a>&#160;&#160;&#160;64</td></tr>
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<tr class="memitem:a11c2ad8d86644aed31f81d4f8c28c058"><td class="memItemLeft" align="right" valign="top"><a id="a11c2ad8d86644aed31f81d4f8c28c058"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a11c2ad8d86644aed31f81d4f8c28c058">PORT_PC00</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a660f2c4b8185501aedfb0ffcc7d7b5e5">PIN_PC01</a>&#160;&#160;&#160;65</td></tr>
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<tr class="memitem:a6bbc571416914e21fc6886d985de7d45"><td class="memItemLeft" align="right" valign="top"><a id="a6bbc571416914e21fc6886d985de7d45"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6bbc571416914e21fc6886d985de7d45">PORT_PC01</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a00962afe8103e69f974c3e0b2d8b5460">PIN_PC02</a>&#160;&#160;&#160;66</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0bae21ce0219c7b02ed1f8cc7fa8eb0e">PORT_PC02</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 2)</td></tr>
<tr class="memdesc:a0bae21ce0219c7b02ed1f8cc7fa8eb0e"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PC02. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#abd5606317bd1a2b543feb22345d24dce">PIN_PC03</a>&#160;&#160;&#160;67</td></tr>
<tr class="memdesc:abd5606317bd1a2b543feb22345d24dce"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PC03. <br /></td></tr>
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<tr class="memitem:a713db11fba4c30b49c3ba91694ce7005"><td class="memItemLeft" align="right" valign="top"><a id="a713db11fba4c30b49c3ba91694ce7005"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a713db11fba4c30b49c3ba91694ce7005">PORT_PC03</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 3)</td></tr>
<tr class="memdesc:a713db11fba4c30b49c3ba91694ce7005"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PC03. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a113284b163f89067ff5cbeca3064d635">PIN_PC05</a>&#160;&#160;&#160;69</td></tr>
<tr class="memdesc:a113284b163f89067ff5cbeca3064d635"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PC05. <br /></td></tr>
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<tr class="memitem:a1c3caebf2592426330ddbc91613dbe3f"><td class="memItemLeft" align="right" valign="top"><a id="a1c3caebf2592426330ddbc91613dbe3f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1c3caebf2592426330ddbc91613dbe3f">PORT_PC05</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 5)</td></tr>
<tr class="memdesc:a1c3caebf2592426330ddbc91613dbe3f"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PC05. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac482b80449bc985c512a6070377e63a0">PIN_PC06</a>&#160;&#160;&#160;70</td></tr>
<tr class="memdesc:ac482b80449bc985c512a6070377e63a0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PC06. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a00badc056aab21797bcf477e27000e59">PORT_PC06</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 6)</td></tr>
<tr class="memdesc:a00badc056aab21797bcf477e27000e59"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PC06. <br /></td></tr>
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<tr class="memitem:a2f88164c5c1d9f191d8ab143a4a93b8f"><td class="memItemLeft" align="right" valign="top"><a id="a2f88164c5c1d9f191d8ab143a4a93b8f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2f88164c5c1d9f191d8ab143a4a93b8f">PIN_PC07</a>&#160;&#160;&#160;71</td></tr>
<tr class="memdesc:a2f88164c5c1d9f191d8ab143a4a93b8f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PC07. <br /></td></tr>
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<tr class="memitem:ad47864c04a5f2f463c67f73e2797b4a1"><td class="memItemLeft" align="right" valign="top"><a id="ad47864c04a5f2f463c67f73e2797b4a1"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad47864c04a5f2f463c67f73e2797b4a1">PORT_PC07</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 7)</td></tr>
<tr class="memdesc:ad47864c04a5f2f463c67f73e2797b4a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PC07. <br /></td></tr>
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<tr class="memitem:aff6b265d92a4e897c638c1eee384ec8c"><td class="memItemLeft" align="right" valign="top"><a id="aff6b265d92a4e897c638c1eee384ec8c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aff6b265d92a4e897c638c1eee384ec8c">PIN_PC10</a>&#160;&#160;&#160;74</td></tr>
<tr class="memdesc:aff6b265d92a4e897c638c1eee384ec8c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PC10. <br /></td></tr>
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<tr class="memitem:a0d556ea272a97d6e5dfa4aef4efa6120"><td class="memItemLeft" align="right" valign="top"><a id="a0d556ea272a97d6e5dfa4aef4efa6120"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0d556ea272a97d6e5dfa4aef4efa6120">PORT_PC10</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 10)</td></tr>
<tr class="memdesc:a0d556ea272a97d6e5dfa4aef4efa6120"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PC10. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af5383801c643a912e585fd88a5e74355">PIN_PC11</a>&#160;&#160;&#160;75</td></tr>
<tr class="memdesc:af5383801c643a912e585fd88a5e74355"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PC11. <br /></td></tr>
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<tr class="memitem:ab26bfe978997514d19bf0774f7ac8886"><td class="memItemLeft" align="right" valign="top"><a id="ab26bfe978997514d19bf0774f7ac8886"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab26bfe978997514d19bf0774f7ac8886">PORT_PC11</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 11)</td></tr>
<tr class="memdesc:ab26bfe978997514d19bf0774f7ac8886"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PC11. <br /></td></tr>
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<tr class="memitem:a3cd7dc7eacdf635f5961b88cf8e9615c"><td class="memItemLeft" align="right" valign="top"><a id="a3cd7dc7eacdf635f5961b88cf8e9615c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3cd7dc7eacdf635f5961b88cf8e9615c">PIN_PC12</a>&#160;&#160;&#160;76</td></tr>
<tr class="memdesc:a3cd7dc7eacdf635f5961b88cf8e9615c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PC12. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a905c16857a69276631ade450d5cd7773">PORT_PC12</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8b2bddce7b7c86858425a98b38b66f72">PIN_PC13</a>&#160;&#160;&#160;77</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6d2def8b2e60b67f9143d64cb1dc6c41">PORT_PC13</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 13)</td></tr>
<tr class="memdesc:a6d2def8b2e60b67f9143d64cb1dc6c41"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PC13. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4b5d8d4c929b4211beaf0c37369192e1">PIN_PC14</a>&#160;&#160;&#160;78</td></tr>
<tr class="memdesc:a4b5d8d4c929b4211beaf0c37369192e1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PC14. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a081fad1e7cbd9b3a45b2337b99044087">PORT_PC14</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a67fdf6e33ae3300beb2300d92faf106a">PIN_PC15</a>&#160;&#160;&#160;79</td></tr>
<tr class="memdesc:a67fdf6e33ae3300beb2300d92faf106a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PC15. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#adb50ba68b94556d52f19e689442c20e9">PORT_PC15</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 15)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a34f523d2ae97243b4c35725ef40b902d">PIN_PC16</a>&#160;&#160;&#160;80</td></tr>
<tr class="memdesc:a34f523d2ae97243b4c35725ef40b902d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PC16. <br /></td></tr>
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<tr class="memitem:a2bac9beedae61de427547a9c1c717e2b"><td class="memItemLeft" align="right" valign="top"><a id="a2bac9beedae61de427547a9c1c717e2b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2bac9beedae61de427547a9c1c717e2b">PORT_PC16</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 16)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a74254fd4866b493faed97034af306210">PIN_PC17</a>&#160;&#160;&#160;81</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad6518af86729aa8ff01df7e35fd79ae3">PORT_PC17</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 17)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a92d75c7dac26934a8687165c023c542b">PIN_PC18</a>&#160;&#160;&#160;82</td></tr>
<tr class="memdesc:a92d75c7dac26934a8687165c023c542b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PC18. <br /></td></tr>
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<tr class="memitem:ae3d795043c31e9ff3166671f9d2f4bdf"><td class="memItemLeft" align="right" valign="top"><a id="ae3d795043c31e9ff3166671f9d2f4bdf"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae3d795043c31e9ff3166671f9d2f4bdf">PORT_PC18</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 18)</td></tr>
<tr class="memdesc:ae3d795043c31e9ff3166671f9d2f4bdf"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PC18. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aaed3b1e599aec3466f800bf9ce0d81b4">PIN_PC19</a>&#160;&#160;&#160;83</td></tr>
<tr class="memdesc:aaed3b1e599aec3466f800bf9ce0d81b4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PC19. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a46d059dbfb05f60216f1bf806999c68c">PORT_PC19</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 19)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa7b1542f26578e30975a3a87cc25de30">PIN_PC20</a>&#160;&#160;&#160;84</td></tr>
<tr class="memdesc:aa7b1542f26578e30975a3a87cc25de30"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PC20. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a114010c47944330971bab1bf0d022f5b">PORT_PC20</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 20)</td></tr>
<tr class="memdesc:a114010c47944330971bab1bf0d022f5b"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PC20. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8dce6d205cc0732e2f3223c4cf95b474">PIN_PC21</a>&#160;&#160;&#160;85</td></tr>
<tr class="memdesc:a8dce6d205cc0732e2f3223c4cf95b474"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PC21. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aba86406cdfef8644b1bccd64e613dbd0">PORT_PC21</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 21)</td></tr>
<tr class="memdesc:aba86406cdfef8644b1bccd64e613dbd0"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PC21. <br /></td></tr>
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<tr class="memitem:aacb6b9d263b7f09938ebbaa80e6bc073"><td class="memItemLeft" align="right" valign="top"><a id="aacb6b9d263b7f09938ebbaa80e6bc073"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aacb6b9d263b7f09938ebbaa80e6bc073">PIN_PC24</a>&#160;&#160;&#160;88</td></tr>
<tr class="memdesc:aacb6b9d263b7f09938ebbaa80e6bc073"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PC24. <br /></td></tr>
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<tr class="memitem:a68381d5e1c3a845e0aa0a5da77435fa8"><td class="memItemLeft" align="right" valign="top"><a id="a68381d5e1c3a845e0aa0a5da77435fa8"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a68381d5e1c3a845e0aa0a5da77435fa8">PORT_PC24</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 24)</td></tr>
<tr class="memdesc:a68381d5e1c3a845e0aa0a5da77435fa8"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PC24. <br /></td></tr>
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<tr class="memitem:a716f129b19cde1b4c7d6010f31d1916c"><td class="memItemLeft" align="right" valign="top"><a id="a716f129b19cde1b4c7d6010f31d1916c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a716f129b19cde1b4c7d6010f31d1916c">PIN_PC25</a>&#160;&#160;&#160;89</td></tr>
<tr class="memdesc:a716f129b19cde1b4c7d6010f31d1916c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PC25. <br /></td></tr>
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<tr class="memitem:a3aebbd81aa907d14cf796d637dde8ac5"><td class="memItemLeft" align="right" valign="top"><a id="a3aebbd81aa907d14cf796d637dde8ac5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3aebbd81aa907d14cf796d637dde8ac5">PORT_PC25</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 25)</td></tr>
<tr class="memdesc:a3aebbd81aa907d14cf796d637dde8ac5"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PC25. <br /></td></tr>
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<tr class="memitem:a7d2a96003b5360413e5d28fa4974a565"><td class="memItemLeft" align="right" valign="top"><a id="a7d2a96003b5360413e5d28fa4974a565"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7d2a96003b5360413e5d28fa4974a565">PIN_PC26</a>&#160;&#160;&#160;90</td></tr>
<tr class="memdesc:a7d2a96003b5360413e5d28fa4974a565"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PC26. <br /></td></tr>
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<tr class="memitem:a588ed15e3f1c67b8a14b27b57062b0a5"><td class="memItemLeft" align="right" valign="top"><a id="a588ed15e3f1c67b8a14b27b57062b0a5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a588ed15e3f1c67b8a14b27b57062b0a5">PORT_PC26</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 26)</td></tr>
<tr class="memdesc:a588ed15e3f1c67b8a14b27b57062b0a5"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PC26. <br /></td></tr>
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<tr class="memitem:a5b4e751041e7b348eddfea3b2f7b226d"><td class="memItemLeft" align="right" valign="top"><a id="a5b4e751041e7b348eddfea3b2f7b226d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5b4e751041e7b348eddfea3b2f7b226d">PIN_PC27</a>&#160;&#160;&#160;91</td></tr>
<tr class="memdesc:a5b4e751041e7b348eddfea3b2f7b226d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PC27. <br /></td></tr>
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<tr class="memitem:a1f8da01ce32bc343dba25fc04b12b803"><td class="memItemLeft" align="right" valign="top"><a id="a1f8da01ce32bc343dba25fc04b12b803"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1f8da01ce32bc343dba25fc04b12b803">PORT_PC27</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 27)</td></tr>
<tr class="memdesc:a1f8da01ce32bc343dba25fc04b12b803"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PC27. <br /></td></tr>
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<tr class="memitem:a6446765e7207e11ed7d52629fc5894d9"><td class="memItemLeft" align="right" valign="top"><a id="a6446765e7207e11ed7d52629fc5894d9"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6446765e7207e11ed7d52629fc5894d9">PIN_PC28</a>&#160;&#160;&#160;92</td></tr>
<tr class="memdesc:a6446765e7207e11ed7d52629fc5894d9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pin Number for PC28. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8849ed04d8c4488e2e2c74b150049ce4">PORT_PC28</a>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 28)</td></tr>
<tr class="memdesc:a8849ed04d8c4488e2e2c74b150049ce4"><td class="mdescLeft">&#160;</td><td class="mdescRight">PORT Mask for PC28. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac30d97ce1522129bc0b1f36d2b3716a6">PIN_PA30H_CM4_SWCLK</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(30)</td></tr>
<tr class="memdesc:ac30d97ce1522129bc0b1f36d2b3716a6"><td class="mdescLeft">&#160;</td><td class="mdescRight">CM4 signal: SWCLK on PA30 mux H. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA30H_CM4_SWCLK</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA30H_CM4_SWCLK</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ac30d97ce1522129bc0b1f36d2b3716a6">PIN_PA30H_CM4_SWCLK</a> &lt;&lt; 16) | MUX_PA30H_CM4_SWCLK)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA30H_CM4_SWCLK</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 30)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8071d6e81449cdd3b4270600468e02e7">PIN_PC27M_CM4_SWO</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(91)</td></tr>
<tr class="memdesc:a8071d6e81449cdd3b4270600468e02e7"><td class="mdescLeft">&#160;</td><td class="mdescRight">CM4 signal: SWO on PC27 mux M. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC27M_CM4_SWO</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC27M_CM4_SWO</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a8071d6e81449cdd3b4270600468e02e7">PIN_PC27M_CM4_SWO</a> &lt;&lt; 16) | MUX_PC27M_CM4_SWO)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC27M_CM4_SWO</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 27)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3a8561e0a90e065dd61d350761cd1eaf">PIN_PB30H_CM4_SWO</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(62)</td></tr>
<tr class="memdesc:a3a8561e0a90e065dd61d350761cd1eaf"><td class="mdescLeft">&#160;</td><td class="mdescRight">CM4 signal: SWO on PB30 mux H. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB30H_CM4_SWO</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB30H_CM4_SWO</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a3a8561e0a90e065dd61d350761cd1eaf">PIN_PB30H_CM4_SWO</a> &lt;&lt; 16) | MUX_PB30H_CM4_SWO)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB30H_CM4_SWO</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 30)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa1ca59541b63748b4fbcc23bd1224e71">PIN_PC27H_CM4_TRACECLK</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(91)</td></tr>
<tr class="memdesc:aa1ca59541b63748b4fbcc23bd1224e71"><td class="mdescLeft">&#160;</td><td class="mdescRight">CM4 signal: TRACECLK on PC27 mux H. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC27H_CM4_TRACECLK</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC27H_CM4_TRACECLK</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aa1ca59541b63748b4fbcc23bd1224e71">PIN_PC27H_CM4_TRACECLK</a> &lt;&lt; 16) | MUX_PC27H_CM4_TRACECLK)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC27H_CM4_TRACECLK</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 27)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae01143cd9657810e8f27788a0c5df0c3">PIN_PC28H_CM4_TRACEDATA0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(92)</td></tr>
<tr class="memdesc:ae01143cd9657810e8f27788a0c5df0c3"><td class="mdescLeft">&#160;</td><td class="mdescRight">CM4 signal: TRACEDATA0 on PC28 mux H. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC28H_CM4_TRACEDATA0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC28H_CM4_TRACEDATA0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ae01143cd9657810e8f27788a0c5df0c3">PIN_PC28H_CM4_TRACEDATA0</a> &lt;&lt; 16) | MUX_PC28H_CM4_TRACEDATA0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC28H_CM4_TRACEDATA0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 28)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3adc9d84ffc839f073d5e8e8b8670060">PIN_PC26H_CM4_TRACEDATA1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(90)</td></tr>
<tr class="memdesc:a3adc9d84ffc839f073d5e8e8b8670060"><td class="mdescLeft">&#160;</td><td class="mdescRight">CM4 signal: TRACEDATA1 on PC26 mux H. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC26H_CM4_TRACEDATA1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC26H_CM4_TRACEDATA1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a3adc9d84ffc839f073d5e8e8b8670060">PIN_PC26H_CM4_TRACEDATA1</a> &lt;&lt; 16) | MUX_PC26H_CM4_TRACEDATA1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC26H_CM4_TRACEDATA1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 26)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae7aa796f50af9fcf9fd32a26580011d8">PIN_PC25H_CM4_TRACEDATA2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(89)</td></tr>
<tr class="memdesc:ae7aa796f50af9fcf9fd32a26580011d8"><td class="mdescLeft">&#160;</td><td class="mdescRight">CM4 signal: TRACEDATA2 on PC25 mux H. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC25H_CM4_TRACEDATA2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ae7aa796f50af9fcf9fd32a26580011d8">PIN_PC25H_CM4_TRACEDATA2</a> &lt;&lt; 16) | MUX_PC25H_CM4_TRACEDATA2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC25H_CM4_TRACEDATA2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 25)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a915cf57cd29849d3110a2251e203c99d">PIN_PC24H_CM4_TRACEDATA3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(88)</td></tr>
<tr class="memdesc:a915cf57cd29849d3110a2251e203c99d"><td class="mdescLeft">&#160;</td><td class="mdescRight">CM4 signal: TRACEDATA3 on PC24 mux H. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC24H_CM4_TRACEDATA3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a915cf57cd29849d3110a2251e203c99d">PIN_PC24H_CM4_TRACEDATA3</a> &lt;&lt; 16) | MUX_PC24H_CM4_TRACEDATA3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC24H_CM4_TRACEDATA3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 24)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a762acdd8b05ad3c153f614b1f2ea9ca9">PIN_PA03B_ANAREF_VREF0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
<tr class="memdesc:a762acdd8b05ad3c153f614b1f2ea9ca9"><td class="mdescLeft">&#160;</td><td class="mdescRight">ANAREF signal: VREF0 on PA03 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA03B_ANAREF_VREF0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA03B_ANAREF_VREF0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a762acdd8b05ad3c153f614b1f2ea9ca9">PIN_PA03B_ANAREF_VREF0</a> &lt;&lt; 16) | MUX_PA03B_ANAREF_VREF0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA03B_ANAREF_VREF0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a45b296ef4b8ce5a77d37fe26b1c6d517">PIN_PA04B_ANAREF_VREF1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
<tr class="memdesc:a45b296ef4b8ce5a77d37fe26b1c6d517"><td class="mdescLeft">&#160;</td><td class="mdescRight">ANAREF signal: VREF1 on PA04 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA04B_ANAREF_VREF1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA04B_ANAREF_VREF1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a45b296ef4b8ce5a77d37fe26b1c6d517">PIN_PA04B_ANAREF_VREF1</a> &lt;&lt; 16) | MUX_PA04B_ANAREF_VREF1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA04B_ANAREF_VREF1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aae159b86068948394d159978d9026b73">PIN_PA06B_ANAREF_VREF2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
<tr class="memdesc:aae159b86068948394d159978d9026b73"><td class="mdescLeft">&#160;</td><td class="mdescRight">ANAREF signal: VREF2 on PA06 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA06B_ANAREF_VREF2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA06B_ANAREF_VREF2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aae159b86068948394d159978d9026b73">PIN_PA06B_ANAREF_VREF2</a> &lt;&lt; 16) | MUX_PA06B_ANAREF_VREF2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA06B_ANAREF_VREF2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 6)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab9a874d00e015ca69f9a1a21e0a0620a">PIN_PA30M_GCLK_IO0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(30)</td></tr>
<tr class="memdesc:ab9a874d00e015ca69f9a1a21e0a0620a"><td class="mdescLeft">&#160;</td><td class="mdescRight">GCLK signal: IO0 on PA30 mux M. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA30M_GCLK_IO0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA30M_GCLK_IO0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ab9a874d00e015ca69f9a1a21e0a0620a">PIN_PA30M_GCLK_IO0</a> &lt;&lt; 16) | MUX_PA30M_GCLK_IO0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA30M_GCLK_IO0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 30)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1e5d68018ee6a759db41160940c972df">PIN_PB14M_GCLK_IO0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(46)</td></tr>
<tr class="memdesc:a1e5d68018ee6a759db41160940c972df"><td class="mdescLeft">&#160;</td><td class="mdescRight">GCLK signal: IO0 on PB14 mux M. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB14M_GCLK_IO0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB14M_GCLK_IO0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a1e5d68018ee6a759db41160940c972df">PIN_PB14M_GCLK_IO0</a> &lt;&lt; 16) | MUX_PB14M_GCLK_IO0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB14M_GCLK_IO0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac696ca40352e783026f12d10d5e0e519">PIN_PA14M_GCLK_IO0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
<tr class="memdesc:ac696ca40352e783026f12d10d5e0e519"><td class="mdescLeft">&#160;</td><td class="mdescRight">GCLK signal: IO0 on PA14 mux M. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA14M_GCLK_IO0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA14M_GCLK_IO0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ac696ca40352e783026f12d10d5e0e519">PIN_PA14M_GCLK_IO0</a> &lt;&lt; 16) | MUX_PA14M_GCLK_IO0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA14M_GCLK_IO0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5b559a0afd7254c03927b5373902d1e8">PIN_PB22M_GCLK_IO0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(54)</td></tr>
<tr class="memdesc:a5b559a0afd7254c03927b5373902d1e8"><td class="mdescLeft">&#160;</td><td class="mdescRight">GCLK signal: IO0 on PB22 mux M. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB22M_GCLK_IO0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB22M_GCLK_IO0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a5b559a0afd7254c03927b5373902d1e8">PIN_PB22M_GCLK_IO0</a> &lt;&lt; 16) | MUX_PB22M_GCLK_IO0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB22M_GCLK_IO0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 22)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4a63ef1b82dfcb6701b8ffe412264a22">PIN_PB15M_GCLK_IO1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(47)</td></tr>
<tr class="memdesc:a4a63ef1b82dfcb6701b8ffe412264a22"><td class="mdescLeft">&#160;</td><td class="mdescRight">GCLK signal: IO1 on PB15 mux M. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB15M_GCLK_IO1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB15M_GCLK_IO1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a4a63ef1b82dfcb6701b8ffe412264a22">PIN_PB15M_GCLK_IO1</a> &lt;&lt; 16) | MUX_PB15M_GCLK_IO1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB15M_GCLK_IO1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 15)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6e20628fc876d9117bf503d6eaa942a1">PIN_PA15M_GCLK_IO1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(15)</td></tr>
<tr class="memdesc:a6e20628fc876d9117bf503d6eaa942a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">GCLK signal: IO1 on PA15 mux M. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA15M_GCLK_IO1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA15M_GCLK_IO1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a6e20628fc876d9117bf503d6eaa942a1">PIN_PA15M_GCLK_IO1</a> &lt;&lt; 16) | MUX_PA15M_GCLK_IO1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA15M_GCLK_IO1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 15)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#adc21f08982588ae0cd26d31112a9afb6">PIN_PB23M_GCLK_IO1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(55)</td></tr>
<tr class="memdesc:adc21f08982588ae0cd26d31112a9afb6"><td class="mdescLeft">&#160;</td><td class="mdescRight">GCLK signal: IO1 on PB23 mux M. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB23M_GCLK_IO1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB23M_GCLK_IO1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#adc21f08982588ae0cd26d31112a9afb6">PIN_PB23M_GCLK_IO1</a> &lt;&lt; 16) | MUX_PB23M_GCLK_IO1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB23M_GCLK_IO1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 23)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad00930c9669ccac44b6079fae3d367a5">PIN_PA27M_GCLK_IO1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(27)</td></tr>
<tr class="memdesc:ad00930c9669ccac44b6079fae3d367a5"><td class="mdescLeft">&#160;</td><td class="mdescRight">GCLK signal: IO1 on PA27 mux M. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA27M_GCLK_IO1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA27M_GCLK_IO1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ad00930c9669ccac44b6079fae3d367a5">PIN_PA27M_GCLK_IO1</a> &lt;&lt; 16) | MUX_PA27M_GCLK_IO1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA27M_GCLK_IO1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 27)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a457dc2d8c6bd8fc1cc7c6c0729537699">PIN_PA16M_GCLK_IO2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(16)</td></tr>
<tr class="memdesc:a457dc2d8c6bd8fc1cc7c6c0729537699"><td class="mdescLeft">&#160;</td><td class="mdescRight">GCLK signal: IO2 on PA16 mux M. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA16M_GCLK_IO2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA16M_GCLK_IO2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a457dc2d8c6bd8fc1cc7c6c0729537699">PIN_PA16M_GCLK_IO2</a> &lt;&lt; 16) | MUX_PA16M_GCLK_IO2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA16M_GCLK_IO2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 16)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2753ed51490a54b091736203342d418e">PIN_PB16M_GCLK_IO2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(48)</td></tr>
<tr class="memdesc:a2753ed51490a54b091736203342d418e"><td class="mdescLeft">&#160;</td><td class="mdescRight">GCLK signal: IO2 on PB16 mux M. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB16M_GCLK_IO2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB16M_GCLK_IO2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a2753ed51490a54b091736203342d418e">PIN_PB16M_GCLK_IO2</a> &lt;&lt; 16) | MUX_PB16M_GCLK_IO2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB16M_GCLK_IO2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 16)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8d867fb31bb6b5bc4decdf980784c5b1">PIN_PA17M_GCLK_IO3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(17)</td></tr>
<tr class="memdesc:a8d867fb31bb6b5bc4decdf980784c5b1"><td class="mdescLeft">&#160;</td><td class="mdescRight">GCLK signal: IO3 on PA17 mux M. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA17M_GCLK_IO3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA17M_GCLK_IO3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a8d867fb31bb6b5bc4decdf980784c5b1">PIN_PA17M_GCLK_IO3</a> &lt;&lt; 16) | MUX_PA17M_GCLK_IO3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA17M_GCLK_IO3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 17)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3894cd80572f34d2fc8d2efc36a713a5">PIN_PB17M_GCLK_IO3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(49)</td></tr>
<tr class="memdesc:a3894cd80572f34d2fc8d2efc36a713a5"><td class="mdescLeft">&#160;</td><td class="mdescRight">GCLK signal: IO3 on PB17 mux M. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB17M_GCLK_IO3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB17M_GCLK_IO3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a3894cd80572f34d2fc8d2efc36a713a5">PIN_PB17M_GCLK_IO3</a> &lt;&lt; 16) | MUX_PB17M_GCLK_IO3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB17M_GCLK_IO3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 17)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aee4918311027732854180cbdf54c2d8e">PIN_PA10M_GCLK_IO4</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
<tr class="memdesc:aee4918311027732854180cbdf54c2d8e"><td class="mdescLeft">&#160;</td><td class="mdescRight">GCLK signal: IO4 on PA10 mux M. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA10M_GCLK_IO4</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA10M_GCLK_IO4</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aee4918311027732854180cbdf54c2d8e">PIN_PA10M_GCLK_IO4</a> &lt;&lt; 16) | MUX_PA10M_GCLK_IO4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA10M_GCLK_IO4</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 10)</td></tr>
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<tr class="memdesc:a88cb37ac0bd1a5c7723311306be5e642"><td class="mdescLeft">&#160;</td><td class="mdescRight">GCLK signal: IO4 on PB10 mux M. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB10M_GCLK_IO4</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB10M_GCLK_IO4</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a88cb37ac0bd1a5c7723311306be5e642">PIN_PB10M_GCLK_IO4</a> &lt;&lt; 16) | MUX_PB10M_GCLK_IO4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB10M_GCLK_IO4</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4ad767bc21897dddf65164822d66481a">PIN_PB18M_GCLK_IO4</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(50)</td></tr>
<tr class="memdesc:a4ad767bc21897dddf65164822d66481a"><td class="mdescLeft">&#160;</td><td class="mdescRight">GCLK signal: IO4 on PB18 mux M. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB18M_GCLK_IO4</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB18M_GCLK_IO4</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a4ad767bc21897dddf65164822d66481a">PIN_PB18M_GCLK_IO4</a> &lt;&lt; 16) | MUX_PB18M_GCLK_IO4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB18M_GCLK_IO4</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 18)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a37854bd98ef7819fa2b03209a7aad89c">PIN_PA11M_GCLK_IO5</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
<tr class="memdesc:a37854bd98ef7819fa2b03209a7aad89c"><td class="mdescLeft">&#160;</td><td class="mdescRight">GCLK signal: IO5 on PA11 mux M. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA11M_GCLK_IO5</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA11M_GCLK_IO5</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a37854bd98ef7819fa2b03209a7aad89c">PIN_PA11M_GCLK_IO5</a> &lt;&lt; 16) | MUX_PA11M_GCLK_IO5)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA11M_GCLK_IO5</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a35918243c25bab659d09ffa49b4c9405">PIN_PB11M_GCLK_IO5</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(43)</td></tr>
<tr class="memdesc:a35918243c25bab659d09ffa49b4c9405"><td class="mdescLeft">&#160;</td><td class="mdescRight">GCLK signal: IO5 on PB11 mux M. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB11M_GCLK_IO5</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB11M_GCLK_IO5</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a35918243c25bab659d09ffa49b4c9405">PIN_PB11M_GCLK_IO5</a> &lt;&lt; 16) | MUX_PB11M_GCLK_IO5)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB11M_GCLK_IO5</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aaea9a8b767bdae695a011935e8d39355">PIN_PB19M_GCLK_IO5</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(51)</td></tr>
<tr class="memdesc:aaea9a8b767bdae695a011935e8d39355"><td class="mdescLeft">&#160;</td><td class="mdescRight">GCLK signal: IO5 on PB19 mux M. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB19M_GCLK_IO5</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB19M_GCLK_IO5</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aaea9a8b767bdae695a011935e8d39355">PIN_PB19M_GCLK_IO5</a> &lt;&lt; 16) | MUX_PB19M_GCLK_IO5)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB19M_GCLK_IO5</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 19)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a683f912ed6abbaf0791f577933b56d5c">PIN_PB12M_GCLK_IO6</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(44)</td></tr>
<tr class="memdesc:a683f912ed6abbaf0791f577933b56d5c"><td class="mdescLeft">&#160;</td><td class="mdescRight">GCLK signal: IO6 on PB12 mux M. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB12M_GCLK_IO6</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB12M_GCLK_IO6</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a683f912ed6abbaf0791f577933b56d5c">PIN_PB12M_GCLK_IO6</a> &lt;&lt; 16) | MUX_PB12M_GCLK_IO6)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB12M_GCLK_IO6</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a073dada98d20a9c650ad8c7af49137e4">PIN_PB20M_GCLK_IO6</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(52)</td></tr>
<tr class="memdesc:a073dada98d20a9c650ad8c7af49137e4"><td class="mdescLeft">&#160;</td><td class="mdescRight">GCLK signal: IO6 on PB20 mux M. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB20M_GCLK_IO6</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB20M_GCLK_IO6</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a073dada98d20a9c650ad8c7af49137e4">PIN_PB20M_GCLK_IO6</a> &lt;&lt; 16) | MUX_PB20M_GCLK_IO6)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB20M_GCLK_IO6</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 20)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6510bd93510d1d8abfcd8d8abcd64746">PIN_PB13M_GCLK_IO7</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(45)</td></tr>
<tr class="memdesc:a6510bd93510d1d8abfcd8d8abcd64746"><td class="mdescLeft">&#160;</td><td class="mdescRight">GCLK signal: IO7 on PB13 mux M. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB13M_GCLK_IO7</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB13M_GCLK_IO7</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a6510bd93510d1d8abfcd8d8abcd64746">PIN_PB13M_GCLK_IO7</a> &lt;&lt; 16) | MUX_PB13M_GCLK_IO7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB13M_GCLK_IO7</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1b42da4c72c1e5e4aef2cb417bfa88b1">PIN_PB21M_GCLK_IO7</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(53)</td></tr>
<tr class="memdesc:a1b42da4c72c1e5e4aef2cb417bfa88b1"><td class="mdescLeft">&#160;</td><td class="mdescRight">GCLK signal: IO7 on PB21 mux M. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB21M_GCLK_IO7</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB21M_GCLK_IO7</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a1b42da4c72c1e5e4aef2cb417bfa88b1">PIN_PB21M_GCLK_IO7</a> &lt;&lt; 16) | MUX_PB21M_GCLK_IO7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB21M_GCLK_IO7</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 21)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a283c31c34ebe58501071a14230504e28">PIN_PA00A_EIC_EXTINT0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
<tr class="memdesc:a283c31c34ebe58501071a14230504e28"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT0 on PA00 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA00A_EIC_EXTINT0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a283c31c34ebe58501071a14230504e28">PIN_PA00A_EIC_EXTINT0</a> &lt;&lt; 16) | MUX_PA00A_EIC_EXTINT0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA00A_EIC_EXTINT0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aef1ff14a903c5484430241fdcb78475e">PIN_PA00A_EIC_EXTINT_NUM</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
<tr class="memdesc:aef1ff14a903c5484430241fdcb78475e"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PA00 External Interrupt Line. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0d770aa7d3ddd4cad47c946b1a3da6c9">PIN_PA16A_EIC_EXTINT0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(16)</td></tr>
<tr class="memdesc:a0d770aa7d3ddd4cad47c946b1a3da6c9"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT0 on PA16 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA16A_EIC_EXTINT0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA16A_EIC_EXTINT0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a0d770aa7d3ddd4cad47c946b1a3da6c9">PIN_PA16A_EIC_EXTINT0</a> &lt;&lt; 16) | MUX_PA16A_EIC_EXTINT0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA16A_EIC_EXTINT0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 16)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#afc2fba86df87333e6fdc40b51773849e">PIN_PA16A_EIC_EXTINT_NUM</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
<tr class="memdesc:afc2fba86df87333e6fdc40b51773849e"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PA16 External Interrupt Line. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab4dde340f20a4cf17a79fbf78915221e">PIN_PB00A_EIC_EXTINT0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(32)</td></tr>
<tr class="memdesc:ab4dde340f20a4cf17a79fbf78915221e"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT0 on PB00 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB00A_EIC_EXTINT0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB00A_EIC_EXTINT0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ab4dde340f20a4cf17a79fbf78915221e">PIN_PB00A_EIC_EXTINT0</a> &lt;&lt; 16) | MUX_PB00A_EIC_EXTINT0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB00A_EIC_EXTINT0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 0)</td></tr>
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<tr class="memdesc:a8583a3ee73c8d6a94d17a06fdad7610c"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PB00 External Interrupt Line. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3cdb969253e905e519355e82aff95ba5">PIN_PB16A_EIC_EXTINT0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(48)</td></tr>
<tr class="memdesc:a3cdb969253e905e519355e82aff95ba5"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT0 on PB16 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB16A_EIC_EXTINT0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a3cdb969253e905e519355e82aff95ba5">PIN_PB16A_EIC_EXTINT0</a> &lt;&lt; 16) | MUX_PB16A_EIC_EXTINT0)</td></tr>
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<tr class="memdesc:a43d653f1eac9c2bfb0a5bd347f1e45f5"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PB16 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a44cd6df5789f3992386fb18f1c6574f6"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT0 on PC00 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC00A_EIC_EXTINT0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a44cd6df5789f3992386fb18f1c6574f6">PIN_PC00A_EIC_EXTINT0</a> &lt;&lt; 16) | MUX_PC00A_EIC_EXTINT0)</td></tr>
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<tr class="memdesc:ab845418a9f9b8cb51139923c37ba67c3"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PC00 External Interrupt Line. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4577c1ecbc3142a5c7cd489371c88670">PIN_PC16A_EIC_EXTINT0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(80)</td></tr>
<tr class="memdesc:a4577c1ecbc3142a5c7cd489371c88670"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT0 on PC16 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC16A_EIC_EXTINT0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC16A_EIC_EXTINT0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a4577c1ecbc3142a5c7cd489371c88670">PIN_PC16A_EIC_EXTINT0</a> &lt;&lt; 16) | MUX_PC16A_EIC_EXTINT0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC16A_EIC_EXTINT0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 16)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a997b3fa16417fa67f725ac5c8559a036">PIN_PC16A_EIC_EXTINT_NUM</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
<tr class="memdesc:a997b3fa16417fa67f725ac5c8559a036"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PC16 External Interrupt Line. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a256def0777a25758382d17d13cdb78fc">PIN_PA01A_EIC_EXTINT1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
<tr class="memdesc:a256def0777a25758382d17d13cdb78fc"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT1 on PA01 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA01A_EIC_EXTINT1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA01A_EIC_EXTINT1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a256def0777a25758382d17d13cdb78fc">PIN_PA01A_EIC_EXTINT1</a> &lt;&lt; 16) | MUX_PA01A_EIC_EXTINT1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA01A_EIC_EXTINT1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1886a08201ef40b8f967b8e093144cf2">PIN_PA01A_EIC_EXTINT_NUM</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
<tr class="memdesc:a1886a08201ef40b8f967b8e093144cf2"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PA01 External Interrupt Line. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af79887da5633d1254eb6c8b333c47db6">PIN_PA17A_EIC_EXTINT1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(17)</td></tr>
<tr class="memdesc:af79887da5633d1254eb6c8b333c47db6"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT1 on PA17 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA17A_EIC_EXTINT1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA17A_EIC_EXTINT1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#af79887da5633d1254eb6c8b333c47db6">PIN_PA17A_EIC_EXTINT1</a> &lt;&lt; 16) | MUX_PA17A_EIC_EXTINT1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA17A_EIC_EXTINT1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 17)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2e6eb3b0e73b998c18da45bf342f359a">PIN_PA17A_EIC_EXTINT_NUM</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
<tr class="memdesc:a2e6eb3b0e73b998c18da45bf342f359a"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PA17 External Interrupt Line. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#afaf80286ec3dd70e08637188c66b6a0a">PIN_PB01A_EIC_EXTINT1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(33)</td></tr>
<tr class="memdesc:afaf80286ec3dd70e08637188c66b6a0a"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT1 on PB01 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB01A_EIC_EXTINT1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB01A_EIC_EXTINT1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#afaf80286ec3dd70e08637188c66b6a0a">PIN_PB01A_EIC_EXTINT1</a> &lt;&lt; 16) | MUX_PB01A_EIC_EXTINT1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB01A_EIC_EXTINT1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a21d47712199a969466553ab3597f04c2">PIN_PB01A_EIC_EXTINT_NUM</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
<tr class="memdesc:a21d47712199a969466553ab3597f04c2"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PB01 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:afa4edebc2d5a45eb26b3d1cec0a71960"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT1 on PB17 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB17A_EIC_EXTINT1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#afa4edebc2d5a45eb26b3d1cec0a71960">PIN_PB17A_EIC_EXTINT1</a> &lt;&lt; 16) | MUX_PB17A_EIC_EXTINT1)</td></tr>
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<tr class="memdesc:a4e4b9e5ee67364d1135dfb55d7bc0db4"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PB17 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a320a5efa3dd816ea43d7edf1d66723a4"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT1 on PC01 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC01A_EIC_EXTINT1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a320a5efa3dd816ea43d7edf1d66723a4">PIN_PC01A_EIC_EXTINT1</a> &lt;&lt; 16) | MUX_PC01A_EIC_EXTINT1)</td></tr>
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<tr class="memdesc:af1230535ca94de25c2346a1a6e25d372"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PC01 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:aaf8d7c6a329bd1361e6d7868046f1834"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT1 on PC17 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC17A_EIC_EXTINT1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aaf8d7c6a329bd1361e6d7868046f1834">PIN_PC17A_EIC_EXTINT1</a> &lt;&lt; 16) | MUX_PC17A_EIC_EXTINT1)</td></tr>
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<tr class="memdesc:a5e9f7f738e5df9c1a8cae678a2b809c4"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PC17 External Interrupt Line. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aea7fe40459b7796f18577ecfc01f8a47">PIN_PA02A_EIC_EXTINT2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
<tr class="memdesc:aea7fe40459b7796f18577ecfc01f8a47"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT2 on PA02 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA02A_EIC_EXTINT2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aea7fe40459b7796f18577ecfc01f8a47">PIN_PA02A_EIC_EXTINT2</a> &lt;&lt; 16) | MUX_PA02A_EIC_EXTINT2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac72f6cd470f25893de46ce66022ac430">PIN_PA02A_EIC_EXTINT_NUM</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
<tr class="memdesc:ac72f6cd470f25893de46ce66022ac430"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PA02 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a60fce7e2f63922c011117e19a3d85191"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT2 on PA18 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA18A_EIC_EXTINT2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a60fce7e2f63922c011117e19a3d85191">PIN_PA18A_EIC_EXTINT2</a> &lt;&lt; 16) | MUX_PA18A_EIC_EXTINT2)</td></tr>
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<tr class="memdesc:a869336c0bb7a7af7f36e7d01343b9740"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PA18 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a8c14eeab8dec7db30a3a08d9b4f65d94"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT2 on PB02 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB02A_EIC_EXTINT2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB02A_EIC_EXTINT2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a8c14eeab8dec7db30a3a08d9b4f65d94">PIN_PB02A_EIC_EXTINT2</a> &lt;&lt; 16) | MUX_PB02A_EIC_EXTINT2)</td></tr>
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<tr class="memdesc:a44892b8dfdec0c99ceb1c2619d4a008d"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PB02 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a408a2a17c0e02ea6d30cd4b47776b67b"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT2 on PB18 mux A. <br /></td></tr>
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<tr class="memdesc:a912a1c19c620af64c76728d4c4f33a66"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PB18 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:aa823536240b45e7eca5a7ac3b394cb9b"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT2 on PC02 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC02A_EIC_EXTINT2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aa823536240b45e7eca5a7ac3b394cb9b">PIN_PC02A_EIC_EXTINT2</a> &lt;&lt; 16) | MUX_PC02A_EIC_EXTINT2)</td></tr>
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<tr class="memdesc:a774f55a73a80e6912d6b69693c88163b"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PC02 External Interrupt Line. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a293c09db7067876174ae2b5aa59cce0b">PIN_PC18A_EIC_EXTINT2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(82)</td></tr>
<tr class="memdesc:a293c09db7067876174ae2b5aa59cce0b"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT2 on PC18 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC18A_EIC_EXTINT2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a293c09db7067876174ae2b5aa59cce0b">PIN_PC18A_EIC_EXTINT2</a> &lt;&lt; 16) | MUX_PC18A_EIC_EXTINT2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa9c4ff69b685ce241c7b911b91b36f4a">PIN_PC18A_EIC_EXTINT_NUM</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
<tr class="memdesc:aa9c4ff69b685ce241c7b911b91b36f4a"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PC18 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a42aaac29dcc7aa7033b8626b04be9b22"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT3 on PA03 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA03A_EIC_EXTINT3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a42aaac29dcc7aa7033b8626b04be9b22">PIN_PA03A_EIC_EXTINT3</a> &lt;&lt; 16) | MUX_PA03A_EIC_EXTINT3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac8e49fd7497460bfe7fbfb958547af00">PIN_PA03A_EIC_EXTINT_NUM</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
<tr class="memdesc:ac8e49fd7497460bfe7fbfb958547af00"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PA03 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a87bc382027baedde18eb6502dec9a3b9"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT3 on PA19 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA19A_EIC_EXTINT3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA19A_EIC_EXTINT3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a87bc382027baedde18eb6502dec9a3b9">PIN_PA19A_EIC_EXTINT3</a> &lt;&lt; 16) | MUX_PA19A_EIC_EXTINT3)</td></tr>
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<tr class="memdesc:a3e66edf4111ce73457ba2c4466dcb69f"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PA19 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a3dcd20be32a645261f5975e310086298"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT3 on PB03 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB03A_EIC_EXTINT3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a3dcd20be32a645261f5975e310086298">PIN_PB03A_EIC_EXTINT3</a> &lt;&lt; 16) | MUX_PB03A_EIC_EXTINT3)</td></tr>
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<tr class="memdesc:a8406108b540b453e6116fbf2204f023a"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PB03 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:ac0b122ae8a806ac50ee7e8d6809e3d06"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT3 on PB19 mux A. <br /></td></tr>
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<tr class="memdesc:a2be5ac46af5d8688b6de379d2a226c2b"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PB19 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:abc5c80949166cae594213904371cf97a"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT3 on PC03 mux A. <br /></td></tr>
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<tr class="memdesc:a5f2b5bd0a2210b716700abfc04e6e049"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PC03 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a7dc953f6e486ad0b220a992377fa3f0a"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT3 on PC19 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC19A_EIC_EXTINT3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a7dc953f6e486ad0b220a992377fa3f0a">PIN_PC19A_EIC_EXTINT3</a> &lt;&lt; 16) | MUX_PC19A_EIC_EXTINT3)</td></tr>
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<tr class="memdesc:a0a3819d4def71f3c9e050a10135ec2f0"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PC19 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a11527baace52338b39921887a555e478"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT4 on PA04 mux A. <br /></td></tr>
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<tr class="memdesc:a1f0f4a3dafb40f7230781e4c4ce2702c"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PA04 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a5ea1669d366f3cba00fb9d875d6c324c"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT4 on PA20 mux A. <br /></td></tr>
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<tr class="memdesc:a73f5a2d7f2b1096fb1db71c984108ef8"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PA20 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a2fc2cfd9a8382477493f71f73bfb7455"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT4 on PB04 mux A. <br /></td></tr>
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<tr class="memdesc:ac18cf3795486541d5eb1e0dbfc889193"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PB04 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a940a059f979672aa696603fa8f96d882"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT4 on PB20 mux A. <br /></td></tr>
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<tr class="memdesc:aaeb10a8a35fdb068eee286e52ee02af4"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PB20 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a10685b6be087f0b8fbd969cf8d166325"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT4 on PC20 mux A. <br /></td></tr>
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<tr class="memdesc:afc62543d33955913a0ad181b6ad806ab"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PC20 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:ab3a5812b14b4e665e37fe7feffc2ca28"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT5 on PA05 mux A. <br /></td></tr>
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<tr class="memdesc:aa627ad4fb760883d9d2415eb5f281bf7"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PA05 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a3b3b91c79d4686e749c0fd1db1451ab3"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT5 on PA21 mux A. <br /></td></tr>
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<tr class="memdesc:a0c457ef450e9143703eea4a0f32c2e5f"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PA21 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a1784ce6f743bcf2969d6f8e8f68ddb6e"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT5 on PB05 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB05A_EIC_EXTINT5</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a1784ce6f743bcf2969d6f8e8f68ddb6e">PIN_PB05A_EIC_EXTINT5</a> &lt;&lt; 16) | MUX_PB05A_EIC_EXTINT5)</td></tr>
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<tr class="memdesc:a2ea02d04015a7dcf12f503abbc00e96b"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PB05 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a4108f90fa6f73a09eaffaaa1bce9ff82"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT5 on PB21 mux A. <br /></td></tr>
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<tr class="memdesc:aa60a17a6b56b26d23018ed497514bb10"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PB21 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:afb3a787a6d8ac84e614a4b1ea48ae35b"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT5 on PC05 mux A. <br /></td></tr>
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<tr class="memdesc:a0ae7530209f4c97c662d2d19161c87bd"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PC05 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:ab37b60dceb30edb3b9b228b2f8639a7c"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT5 on PC21 mux A. <br /></td></tr>
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<tr class="memdesc:a754c03e54d118ce8af8bb3891992f5b3"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PC21 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a5840dd08c2b6e1baf335ef2078c14bce"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT6 on PA06 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA06A_EIC_EXTINT6</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a5840dd08c2b6e1baf335ef2078c14bce">PIN_PA06A_EIC_EXTINT6</a> &lt;&lt; 16) | MUX_PA06A_EIC_EXTINT6)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a42510dcf38687fa280faa25504561fb7">PIN_PA06A_EIC_EXTINT_NUM</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
<tr class="memdesc:a42510dcf38687fa280faa25504561fb7"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PA06 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:ab3bc619f3136780a6c4a3b0050c1c378"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT6 on PA22 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA22A_EIC_EXTINT6</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 22)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a328966c338ba0a96eaaf67690e5617e7">PIN_PA22A_EIC_EXTINT_NUM</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
<tr class="memdesc:a328966c338ba0a96eaaf67690e5617e7"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PA22 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:ad95c6f9a2f84236bfbb75eae2511fd3a"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT6 on PB06 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB06A_EIC_EXTINT6</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ad95c6f9a2f84236bfbb75eae2511fd3a">PIN_PB06A_EIC_EXTINT6</a> &lt;&lt; 16) | MUX_PB06A_EIC_EXTINT6)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB06A_EIC_EXTINT6</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 6)</td></tr>
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<tr class="memdesc:acb0d8efe496f54a2f4fd8a85ac5e62e6"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PB06 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a3d86b2b73a6ea21b68f1c04389b6c27a"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT6 on PB22 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB22A_EIC_EXTINT6</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB22A_EIC_EXTINT6</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a3d86b2b73a6ea21b68f1c04389b6c27a">PIN_PB22A_EIC_EXTINT6</a> &lt;&lt; 16) | MUX_PB22A_EIC_EXTINT6)</td></tr>
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<tr class="memdesc:aa23bff92eaba130a68175901064e7960"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PB22 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a21443ac8d7d6084c91f10c3e61d5a057"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT6 on PC06 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC06A_EIC_EXTINT6</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a21443ac8d7d6084c91f10c3e61d5a057">PIN_PC06A_EIC_EXTINT6</a> &lt;&lt; 16) | MUX_PC06A_EIC_EXTINT6)</td></tr>
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<tr class="memdesc:a4f5a33ca3710ef24b0b080bd0a8c369b"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PC06 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:afdb42a71714800264c9e3df2059ddc66"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT7 on PA07 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA07A_EIC_EXTINT7</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#afdb42a71714800264c9e3df2059ddc66">PIN_PA07A_EIC_EXTINT7</a> &lt;&lt; 16) | MUX_PA07A_EIC_EXTINT7)</td></tr>
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<tr class="memdesc:a93a0531700ef575536efd7099dbe4042"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PA07 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a6dfe39bc5e36bf0ab08a94f59df5b5ca"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT7 on PA23 mux A. <br /></td></tr>
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<tr class="memdesc:aec7c5d6aa48f6b16ad2e33c5a0839906"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PA23 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:aebbb52da93fec5f213a6a128aec88636"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT7 on PB07 mux A. <br /></td></tr>
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<tr class="memdesc:a74530ce5c1d26c86980bb3909094e656"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PB07 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a4def37025a5b72ef3c5d8c3dfb02a114"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT7 on PB23 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB23A_EIC_EXTINT7</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a4def37025a5b72ef3c5d8c3dfb02a114">PIN_PB23A_EIC_EXTINT7</a> &lt;&lt; 16) | MUX_PB23A_EIC_EXTINT7)</td></tr>
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<tr class="memdesc:af38be5fde44dfd55bbdcf4bf7ca4b58a"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PB23 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a5392ffb9d2a08114d04e6c902b08b167"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT8 on PA24 mux A. <br /></td></tr>
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<tr class="memdesc:a4709be5f65733369b1dcbc2b6563656e"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PA24 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:ad61d23a293dd02bc4fa8c32841f0a8a2"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT8 on PB08 mux A. <br /></td></tr>
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<tr class="memdesc:ab53200d5efdcb033f3da26a7be70e8f3"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PB08 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a3b2bef04d823b1f5eb2e1013d93eae13"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT8 on PB24 mux A. <br /></td></tr>
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<tr class="memdesc:ae4a7b797304e5f352d073fd4673376d9"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PB24 External Interrupt Line. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a891a9e1bb27a399c9aa9097085059ddb">PIN_PC24A_EIC_EXTINT8</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(88)</td></tr>
<tr class="memdesc:a891a9e1bb27a399c9aa9097085059ddb"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT8 on PC24 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC24A_EIC_EXTINT8</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC24A_EIC_EXTINT8</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a891a9e1bb27a399c9aa9097085059ddb">PIN_PC24A_EIC_EXTINT8</a> &lt;&lt; 16) | MUX_PC24A_EIC_EXTINT8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC24A_EIC_EXTINT8</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 24)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a058921d5bed2542797dbd7dfd192f4fe">PIN_PC24A_EIC_EXTINT_NUM</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
<tr class="memdesc:a058921d5bed2542797dbd7dfd192f4fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PC24 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a1e78051967cbcffa4986bbcd1bd69c4b"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT9 on PA09 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA09A_EIC_EXTINT9</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA09A_EIC_EXTINT9</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a1e78051967cbcffa4986bbcd1bd69c4b">PIN_PA09A_EIC_EXTINT9</a> &lt;&lt; 16) | MUX_PA09A_EIC_EXTINT9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA09A_EIC_EXTINT9</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a10b3e3f45849bd53593acf73431f9b4d">PIN_PA09A_EIC_EXTINT_NUM</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
<tr class="memdesc:a10b3e3f45849bd53593acf73431f9b4d"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PA09 External Interrupt Line. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a39df155b7196d41fd91a93b55c1a3b4d">PIN_PA25A_EIC_EXTINT9</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(25)</td></tr>
<tr class="memdesc:a39df155b7196d41fd91a93b55c1a3b4d"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT9 on PA25 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA25A_EIC_EXTINT9</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA25A_EIC_EXTINT9</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a39df155b7196d41fd91a93b55c1a3b4d">PIN_PA25A_EIC_EXTINT9</a> &lt;&lt; 16) | MUX_PA25A_EIC_EXTINT9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA25A_EIC_EXTINT9</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 25)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab8ee9293ffea6d03e4b0307f129469bb">PIN_PA25A_EIC_EXTINT_NUM</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
<tr class="memdesc:ab8ee9293ffea6d03e4b0307f129469bb"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PA25 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a54511e0d8c786b2e9f9254986fd0218c"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT9 on PB09 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB09A_EIC_EXTINT9</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB09A_EIC_EXTINT9</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a54511e0d8c786b2e9f9254986fd0218c">PIN_PB09A_EIC_EXTINT9</a> &lt;&lt; 16) | MUX_PB09A_EIC_EXTINT9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB09A_EIC_EXTINT9</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 9)</td></tr>
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<tr class="memdesc:a10bc7a34f5797ee1e596b87ce0a5a673"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PB09 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:aa027e3d920e60849d3bc0b8be0e2d584"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT9 on PB25 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB25A_EIC_EXTINT9</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aa027e3d920e60849d3bc0b8be0e2d584">PIN_PB25A_EIC_EXTINT9</a> &lt;&lt; 16) | MUX_PB25A_EIC_EXTINT9)</td></tr>
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<tr class="memdesc:a559b557f5767773de2aef70fc2091e09"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PB25 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a9b1f615d6c036a90f8c3f2073726b4d8"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT9 on PC07 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC07A_EIC_EXTINT9</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC07A_EIC_EXTINT9</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a9b1f615d6c036a90f8c3f2073726b4d8">PIN_PC07A_EIC_EXTINT9</a> &lt;&lt; 16) | MUX_PC07A_EIC_EXTINT9)</td></tr>
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<tr class="memdesc:ae77819da8fb6731812fa964ca75638a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PC07 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a34924d3f1c67b2324255389b25651bdb"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT9 on PC25 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC25A_EIC_EXTINT9</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a34924d3f1c67b2324255389b25651bdb">PIN_PC25A_EIC_EXTINT9</a> &lt;&lt; 16) | MUX_PC25A_EIC_EXTINT9)</td></tr>
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<tr class="memdesc:a3a70e4355e455509a04587815d09b282"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PC25 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a8b2c811c3267616edc080b0bff76d475"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT10 on PA10 mux A. <br /></td></tr>
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<tr class="memdesc:ac63edbcc5aa61044348f6c140f9b5d93"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PA10 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a0bbc187130701ad43c72a960b24e2a12"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT10 on PB10 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB10A_EIC_EXTINT10</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a0bbc187130701ad43c72a960b24e2a12">PIN_PB10A_EIC_EXTINT10</a> &lt;&lt; 16) | MUX_PB10A_EIC_EXTINT10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a299b82012bb5d767607e5b17432f56fe">PIN_PB10A_EIC_EXTINT_NUM</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
<tr class="memdesc:a299b82012bb5d767607e5b17432f56fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PB10 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a69f1e93024e115b1c5c7dd0aabc34007"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT10 on PC10 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC10A_EIC_EXTINT10</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a69f1e93024e115b1c5c7dd0aabc34007">PIN_PC10A_EIC_EXTINT10</a> &lt;&lt; 16) | MUX_PC10A_EIC_EXTINT10)</td></tr>
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<tr class="memdesc:aba72c1c36fef61558ece1c1b55966203"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PC10 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:adbc1d8036ba72a5dc9aa4ed8e9c16bf4"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT10 on PC26 mux A. <br /></td></tr>
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<tr class="memdesc:a850b82f73b12eb38b0996dd0f3f50cb5"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PC26 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a3657e3eaf7afcbeb5f745b100e1b7553"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT11 on PA11 mux A. <br /></td></tr>
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<tr class="memdesc:a07f5583af3fda141d507c62491604576"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PA11 External Interrupt Line. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a82d3925fbe91ae83d5696cecee79bd0f">PIN_PA27A_EIC_EXTINT11</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(27)</td></tr>
<tr class="memdesc:a82d3925fbe91ae83d5696cecee79bd0f"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT11 on PA27 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA27A_EIC_EXTINT11</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a82d3925fbe91ae83d5696cecee79bd0f">PIN_PA27A_EIC_EXTINT11</a> &lt;&lt; 16) | MUX_PA27A_EIC_EXTINT11)</td></tr>
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<tr class="memdesc:a629eb4033ad4c842b29a72a2be4f61d9"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PA27 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:ac2c2a072fc6ccf668486f50d41045b78"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT11 on PB11 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB11A_EIC_EXTINT11</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ac2c2a072fc6ccf668486f50d41045b78">PIN_PB11A_EIC_EXTINT11</a> &lt;&lt; 16) | MUX_PB11A_EIC_EXTINT11)</td></tr>
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<tr class="memdesc:aa8771096fea5a2bbf5781b1365b40b9a"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PB11 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a9eeb1998bf1a323d3c93c33c05c3e366"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT11 on PC11 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC11A_EIC_EXTINT11</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a9eeb1998bf1a323d3c93c33c05c3e366">PIN_PC11A_EIC_EXTINT11</a> &lt;&lt; 16) | MUX_PC11A_EIC_EXTINT11)</td></tr>
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<tr class="memdesc:a61460200c4f743e3d81b0092498dd7d4"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PC11 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a30ded42b8250b74e112c5362b83e32ac"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT11 on PC27 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC27A_EIC_EXTINT11</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a30ded42b8250b74e112c5362b83e32ac">PIN_PC27A_EIC_EXTINT11</a> &lt;&lt; 16) | MUX_PC27A_EIC_EXTINT11)</td></tr>
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<tr class="memdesc:a53caacf24a9b4c7d592c1c68a521fa9d"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PC27 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a419f1aea38758fba2ad9508d1e8915ab"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT12 on PA12 mux A. <br /></td></tr>
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<tr class="memdesc:a945f93983309a0fc25eae757bc4a5dcb"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PA12 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a622fd72ad9576c628a9c01207688df4d"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT12 on PB12 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB12A_EIC_EXTINT12</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a622fd72ad9576c628a9c01207688df4d">PIN_PB12A_EIC_EXTINT12</a> &lt;&lt; 16) | MUX_PB12A_EIC_EXTINT12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a20213283160ed1e94398c3caf0f47f80">PIN_PB12A_EIC_EXTINT_NUM</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
<tr class="memdesc:a20213283160ed1e94398c3caf0f47f80"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PB12 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:af07f4f0f8321b7cda8f9b0fd675f0af3"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT12 on PC12 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC12A_EIC_EXTINT12</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC12A_EIC_EXTINT12</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#af07f4f0f8321b7cda8f9b0fd675f0af3">PIN_PC12A_EIC_EXTINT12</a> &lt;&lt; 16) | MUX_PC12A_EIC_EXTINT12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC12A_EIC_EXTINT12</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a904bd02861f200a708506d64bc8b1054">PIN_PC12A_EIC_EXTINT_NUM</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
<tr class="memdesc:a904bd02861f200a708506d64bc8b1054"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PC12 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a20effc1231f3a2798443f6bc6b670bec"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT12 on PC28 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC28A_EIC_EXTINT12</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC28A_EIC_EXTINT12</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a20effc1231f3a2798443f6bc6b670bec">PIN_PC28A_EIC_EXTINT12</a> &lt;&lt; 16) | MUX_PC28A_EIC_EXTINT12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC28A_EIC_EXTINT12</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 28)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae12a87002c813f473f3601d6f4a26180">PIN_PC28A_EIC_EXTINT_NUM</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
<tr class="memdesc:ae12a87002c813f473f3601d6f4a26180"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PC28 External Interrupt Line. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a9a43983f5cd1bfedf36b9c6dfcc4e80c">PIN_PA13A_EIC_EXTINT13</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
<tr class="memdesc:a9a43983f5cd1bfedf36b9c6dfcc4e80c"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT13 on PA13 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA13A_EIC_EXTINT13</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA13A_EIC_EXTINT13</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a9a43983f5cd1bfedf36b9c6dfcc4e80c">PIN_PA13A_EIC_EXTINT13</a> &lt;&lt; 16) | MUX_PA13A_EIC_EXTINT13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA13A_EIC_EXTINT13</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7b27ffa7e40d98061e8f87e6d2938543">PIN_PA13A_EIC_EXTINT_NUM</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
<tr class="memdesc:a7b27ffa7e40d98061e8f87e6d2938543"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PA13 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a30ef1606e3c2432323e5296bbf806969"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT13 on PB13 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB13A_EIC_EXTINT13</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB13A_EIC_EXTINT13</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a30ef1606e3c2432323e5296bbf806969">PIN_PB13A_EIC_EXTINT13</a> &lt;&lt; 16) | MUX_PB13A_EIC_EXTINT13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#abc2373bc00dc6426c18883d73cd921e4">PIN_PB13A_EIC_EXTINT_NUM</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
<tr class="memdesc:abc2373bc00dc6426c18883d73cd921e4"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PB13 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a4c7e68b1de314167020c22878192a4ee"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT13 on PC13 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC13A_EIC_EXTINT13</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a4c7e68b1de314167020c22878192a4ee">PIN_PC13A_EIC_EXTINT13</a> &lt;&lt; 16) | MUX_PC13A_EIC_EXTINT13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC13A_EIC_EXTINT13</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af133e675c28b62bc17622079cc5ad73c">PIN_PC13A_EIC_EXTINT_NUM</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
<tr class="memdesc:af133e675c28b62bc17622079cc5ad73c"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PC13 External Interrupt Line. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab929da45737573301da1d2fdaf47258f">PIN_PA30A_EIC_EXTINT14</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(30)</td></tr>
<tr class="memdesc:ab929da45737573301da1d2fdaf47258f"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT14 on PA30 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA30A_EIC_EXTINT14</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ab929da45737573301da1d2fdaf47258f">PIN_PA30A_EIC_EXTINT14</a> &lt;&lt; 16) | MUX_PA30A_EIC_EXTINT14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA30A_EIC_EXTINT14</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 30)</td></tr>
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<tr class="memdesc:a47e6e6a6f95588257a6dfdb1f9ed4e57"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PA30 External Interrupt Line. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a97b02a75f517744286a792170b1b7007">PIN_PB14A_EIC_EXTINT14</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(46)</td></tr>
<tr class="memdesc:a97b02a75f517744286a792170b1b7007"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT14 on PB14 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB14A_EIC_EXTINT14</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a97b02a75f517744286a792170b1b7007">PIN_PB14A_EIC_EXTINT14</a> &lt;&lt; 16) | MUX_PB14A_EIC_EXTINT14)</td></tr>
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<tr class="memdesc:a1da4ac8484e7935c6b8bdac5293cb17e"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PB14 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a01cb0425b89b425f6281cf047d07d5c5"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT14 on PB30 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB30A_EIC_EXTINT14</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB30A_EIC_EXTINT14</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a01cb0425b89b425f6281cf047d07d5c5">PIN_PB30A_EIC_EXTINT14</a> &lt;&lt; 16) | MUX_PB30A_EIC_EXTINT14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB30A_EIC_EXTINT14</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 30)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a92135bc9b73d6bf0b069ad66f4567d3d">PIN_PB30A_EIC_EXTINT_NUM</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
<tr class="memdesc:a92135bc9b73d6bf0b069ad66f4567d3d"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PB30 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:ad508de42194b497772ad8bb605b9325a"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT14 on PC14 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC14A_EIC_EXTINT14</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ad508de42194b497772ad8bb605b9325a">PIN_PC14A_EIC_EXTINT14</a> &lt;&lt; 16) | MUX_PC14A_EIC_EXTINT14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC14A_EIC_EXTINT14</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 14)</td></tr>
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<tr class="memdesc:a3a4cb92927b0055d3d527ca6ebc74caf"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PC14 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:aa46158d922bcbc88aa8a9f8a5adac460"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT14 on PA14 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA14A_EIC_EXTINT14</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA14A_EIC_EXTINT14</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aa46158d922bcbc88aa8a9f8a5adac460">PIN_PA14A_EIC_EXTINT14</a> &lt;&lt; 16) | MUX_PA14A_EIC_EXTINT14)</td></tr>
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<tr class="memdesc:a1bbcdf32200b0955ec73f1282beb45cd"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PA14 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a6cf6ad0634cbb035d1c78c40cfc0ed7e"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT15 on PA15 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA15A_EIC_EXTINT15</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a6cf6ad0634cbb035d1c78c40cfc0ed7e">PIN_PA15A_EIC_EXTINT15</a> &lt;&lt; 16) | MUX_PA15A_EIC_EXTINT15)</td></tr>
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<tr class="memdesc:a04708a0ba5288c8c83fa7f9951e67108"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PA15 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a6cd3d723ca05fcfd7304061e94ab9ba5"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT15 on PA31 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA31A_EIC_EXTINT15</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a6cd3d723ca05fcfd7304061e94ab9ba5">PIN_PA31A_EIC_EXTINT15</a> &lt;&lt; 16) | MUX_PA31A_EIC_EXTINT15)</td></tr>
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<tr class="memdesc:ac167894f3689f4ed6bb85f957a075458"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PA31 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a2c1ca8280e17a6d444adcd97451e4bbf"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT15 on PB15 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB15A_EIC_EXTINT15</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB15A_EIC_EXTINT15</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a2c1ca8280e17a6d444adcd97451e4bbf">PIN_PB15A_EIC_EXTINT15</a> &lt;&lt; 16) | MUX_PB15A_EIC_EXTINT15)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB15A_EIC_EXTINT15</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 15)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a05751f6bb89213029c029c1c044b55a1">PIN_PB15A_EIC_EXTINT_NUM</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(15)</td></tr>
<tr class="memdesc:a05751f6bb89213029c029c1c044b55a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PB15 External Interrupt Line. <br /></td></tr>
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<tr class="memdesc:a7b7eedd2bc11496a2d6e3b0ce088b1a8"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT15 on PB31 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB31A_EIC_EXTINT15</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB31A_EIC_EXTINT15</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a7b7eedd2bc11496a2d6e3b0ce088b1a8">PIN_PB31A_EIC_EXTINT15</a> &lt;&lt; 16) | MUX_PB31A_EIC_EXTINT15)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB31A_EIC_EXTINT15</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 31)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#abc5b58d0f258b283d19c693854b815b2">PIN_PB31A_EIC_EXTINT_NUM</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(15)</td></tr>
<tr class="memdesc:abc5b58d0f258b283d19c693854b815b2"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PB31 External Interrupt Line. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7ddcaa66fca7de1e5b0478242247c162">PIN_PC15A_EIC_EXTINT15</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(79)</td></tr>
<tr class="memdesc:a7ddcaa66fca7de1e5b0478242247c162"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: EXTINT15 on PC15 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC15A_EIC_EXTINT15</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC15A_EIC_EXTINT15</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a7ddcaa66fca7de1e5b0478242247c162">PIN_PC15A_EIC_EXTINT15</a> &lt;&lt; 16) | MUX_PC15A_EIC_EXTINT15)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC15A_EIC_EXTINT15</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 15)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aab2fbc27e2c4dac81f43ccafd97fc1ac">PIN_PC15A_EIC_EXTINT_NUM</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(15)</td></tr>
<tr class="memdesc:aab2fbc27e2c4dac81f43ccafd97fc1ac"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: PIN_PC15 External Interrupt Line. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1082084482a49eaf19b717ea1a7bb3ad">PIN_PA08A_EIC_NMI</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
<tr class="memdesc:a1082084482a49eaf19b717ea1a7bb3ad"><td class="mdescLeft">&#160;</td><td class="mdescRight">EIC signal: NMI on PA08 mux A. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA08A_EIC_NMI</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA08A_EIC_NMI</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a1082084482a49eaf19b717ea1a7bb3ad">PIN_PA08A_EIC_NMI</a> &lt;&lt; 16) | MUX_PA08A_EIC_NMI)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA08A_EIC_NMI</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a179ea5ec9f89f81e55c6888eb824d068">PIN_PA04D_SERCOM0_PAD0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
<tr class="memdesc:a179ea5ec9f89f81e55c6888eb824d068"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM0 signal: PAD0 on PA04 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA04D_SERCOM0_PAD0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA04D_SERCOM0_PAD0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a179ea5ec9f89f81e55c6888eb824d068">PIN_PA04D_SERCOM0_PAD0</a> &lt;&lt; 16) | MUX_PA04D_SERCOM0_PAD0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA04D_SERCOM0_PAD0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af82f0b07767c68a5157629f3b61921fb">PIN_PC17D_SERCOM0_PAD0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(81)</td></tr>
<tr class="memdesc:af82f0b07767c68a5157629f3b61921fb"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM0 signal: PAD0 on PC17 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC17D_SERCOM0_PAD0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC17D_SERCOM0_PAD0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#af82f0b07767c68a5157629f3b61921fb">PIN_PC17D_SERCOM0_PAD0</a> &lt;&lt; 16) | MUX_PC17D_SERCOM0_PAD0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC17D_SERCOM0_PAD0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 17)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7932baad01e0dab934e930095d07bcd6">PIN_PA08C_SERCOM0_PAD0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
<tr class="memdesc:a7932baad01e0dab934e930095d07bcd6"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM0 signal: PAD0 on PA08 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA08C_SERCOM0_PAD0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA08C_SERCOM0_PAD0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a7932baad01e0dab934e930095d07bcd6">PIN_PA08C_SERCOM0_PAD0</a> &lt;&lt; 16) | MUX_PA08C_SERCOM0_PAD0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA08C_SERCOM0_PAD0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a68c65cb9314acd3059939a65386da260">PIN_PB24C_SERCOM0_PAD0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(56)</td></tr>
<tr class="memdesc:a68c65cb9314acd3059939a65386da260"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM0 signal: PAD0 on PB24 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB24C_SERCOM0_PAD0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB24C_SERCOM0_PAD0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a68c65cb9314acd3059939a65386da260">PIN_PB24C_SERCOM0_PAD0</a> &lt;&lt; 16) | MUX_PB24C_SERCOM0_PAD0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB24C_SERCOM0_PAD0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 24)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad4d21dc85a7896730e71d86ef2257ce7">PIN_PA05D_SERCOM0_PAD1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
<tr class="memdesc:ad4d21dc85a7896730e71d86ef2257ce7"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM0 signal: PAD1 on PA05 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA05D_SERCOM0_PAD1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA05D_SERCOM0_PAD1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ad4d21dc85a7896730e71d86ef2257ce7">PIN_PA05D_SERCOM0_PAD1</a> &lt;&lt; 16) | MUX_PA05D_SERCOM0_PAD1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA05D_SERCOM0_PAD1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 5)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af1f93a79bbac9d49650c6f2eda340468">PIN_PC16D_SERCOM0_PAD1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(80)</td></tr>
<tr class="memdesc:af1f93a79bbac9d49650c6f2eda340468"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM0 signal: PAD1 on PC16 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC16D_SERCOM0_PAD1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC16D_SERCOM0_PAD1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#af1f93a79bbac9d49650c6f2eda340468">PIN_PC16D_SERCOM0_PAD1</a> &lt;&lt; 16) | MUX_PC16D_SERCOM0_PAD1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC16D_SERCOM0_PAD1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 16)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a9f5d8762f7ec6b0dcac7c7b86fb12601">PIN_PA09C_SERCOM0_PAD1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
<tr class="memdesc:a9f5d8762f7ec6b0dcac7c7b86fb12601"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM0 signal: PAD1 on PA09 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA09C_SERCOM0_PAD1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA09C_SERCOM0_PAD1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a9f5d8762f7ec6b0dcac7c7b86fb12601">PIN_PA09C_SERCOM0_PAD1</a> &lt;&lt; 16) | MUX_PA09C_SERCOM0_PAD1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA09C_SERCOM0_PAD1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a027cd8b69276dbef2c76f5e793d8e3d5">PIN_PB25C_SERCOM0_PAD1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(57)</td></tr>
<tr class="memdesc:a027cd8b69276dbef2c76f5e793d8e3d5"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM0 signal: PAD1 on PB25 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB25C_SERCOM0_PAD1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB25C_SERCOM0_PAD1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a027cd8b69276dbef2c76f5e793d8e3d5">PIN_PB25C_SERCOM0_PAD1</a> &lt;&lt; 16) | MUX_PB25C_SERCOM0_PAD1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB25C_SERCOM0_PAD1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 25)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a98a180a87e96b753c4f160089bb07718">PIN_PA06D_SERCOM0_PAD2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
<tr class="memdesc:a98a180a87e96b753c4f160089bb07718"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM0 signal: PAD2 on PA06 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA06D_SERCOM0_PAD2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA06D_SERCOM0_PAD2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a98a180a87e96b753c4f160089bb07718">PIN_PA06D_SERCOM0_PAD2</a> &lt;&lt; 16) | MUX_PA06D_SERCOM0_PAD2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA06D_SERCOM0_PAD2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 6)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a852521514fdecc6b2c89ba04401095f7">PIN_PC18D_SERCOM0_PAD2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(82)</td></tr>
<tr class="memdesc:a852521514fdecc6b2c89ba04401095f7"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM0 signal: PAD2 on PC18 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC18D_SERCOM0_PAD2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC18D_SERCOM0_PAD2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a852521514fdecc6b2c89ba04401095f7">PIN_PC18D_SERCOM0_PAD2</a> &lt;&lt; 16) | MUX_PC18D_SERCOM0_PAD2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC18D_SERCOM0_PAD2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 18)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aaf92a25fb30b2f6e4aa133df5bab7e4d">PIN_PA10C_SERCOM0_PAD2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
<tr class="memdesc:aaf92a25fb30b2f6e4aa133df5bab7e4d"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM0 signal: PAD2 on PA10 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA10C_SERCOM0_PAD2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA10C_SERCOM0_PAD2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aaf92a25fb30b2f6e4aa133df5bab7e4d">PIN_PA10C_SERCOM0_PAD2</a> &lt;&lt; 16) | MUX_PA10C_SERCOM0_PAD2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA10C_SERCOM0_PAD2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a464743cf87518ab58841dbb67cdcf839">PIN_PC24C_SERCOM0_PAD2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(88)</td></tr>
<tr class="memdesc:a464743cf87518ab58841dbb67cdcf839"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM0 signal: PAD2 on PC24 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC24C_SERCOM0_PAD2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC24C_SERCOM0_PAD2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a464743cf87518ab58841dbb67cdcf839">PIN_PC24C_SERCOM0_PAD2</a> &lt;&lt; 16) | MUX_PC24C_SERCOM0_PAD2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC24C_SERCOM0_PAD2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 24)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab0d8d9333afa2bfd599a2b08a3af2997">PIN_PA07D_SERCOM0_PAD3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
<tr class="memdesc:ab0d8d9333afa2bfd599a2b08a3af2997"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM0 signal: PAD3 on PA07 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA07D_SERCOM0_PAD3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA07D_SERCOM0_PAD3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ab0d8d9333afa2bfd599a2b08a3af2997">PIN_PA07D_SERCOM0_PAD3</a> &lt;&lt; 16) | MUX_PA07D_SERCOM0_PAD3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA07D_SERCOM0_PAD3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7c38c4bae42bda928c5cc59815707783">PIN_PC19D_SERCOM0_PAD3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(83)</td></tr>
<tr class="memdesc:a7c38c4bae42bda928c5cc59815707783"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM0 signal: PAD3 on PC19 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC19D_SERCOM0_PAD3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC19D_SERCOM0_PAD3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a7c38c4bae42bda928c5cc59815707783">PIN_PC19D_SERCOM0_PAD3</a> &lt;&lt; 16) | MUX_PC19D_SERCOM0_PAD3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC19D_SERCOM0_PAD3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 19)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a60e3a9a915d036f33dc5e928877f81b8">PIN_PA11C_SERCOM0_PAD3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
<tr class="memdesc:a60e3a9a915d036f33dc5e928877f81b8"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM0 signal: PAD3 on PA11 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA11C_SERCOM0_PAD3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA11C_SERCOM0_PAD3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a60e3a9a915d036f33dc5e928877f81b8">PIN_PA11C_SERCOM0_PAD3</a> &lt;&lt; 16) | MUX_PA11C_SERCOM0_PAD3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA11C_SERCOM0_PAD3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a433553a16e011f69a5cd45b84ab93927">PIN_PC25C_SERCOM0_PAD3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(89)</td></tr>
<tr class="memdesc:a433553a16e011f69a5cd45b84ab93927"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM0 signal: PAD3 on PC25 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC25C_SERCOM0_PAD3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC25C_SERCOM0_PAD3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a433553a16e011f69a5cd45b84ab93927">PIN_PC25C_SERCOM0_PAD3</a> &lt;&lt; 16) | MUX_PC25C_SERCOM0_PAD3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC25C_SERCOM0_PAD3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 25)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7f1a5fa24eb08e5056d1eb8eefe6a14c">PIN_PA00D_SERCOM1_PAD0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
<tr class="memdesc:a7f1a5fa24eb08e5056d1eb8eefe6a14c"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM1 signal: PAD0 on PA00 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA00D_SERCOM1_PAD0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA00D_SERCOM1_PAD0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a7f1a5fa24eb08e5056d1eb8eefe6a14c">PIN_PA00D_SERCOM1_PAD0</a> &lt;&lt; 16) | MUX_PA00D_SERCOM1_PAD0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA00D_SERCOM1_PAD0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#afe7b3ffb79c98ff2acbeec19eccfe9d0">PIN_PA16C_SERCOM1_PAD0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(16)</td></tr>
<tr class="memdesc:afe7b3ffb79c98ff2acbeec19eccfe9d0"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM1 signal: PAD0 on PA16 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA16C_SERCOM1_PAD0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA16C_SERCOM1_PAD0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#afe7b3ffb79c98ff2acbeec19eccfe9d0">PIN_PA16C_SERCOM1_PAD0</a> &lt;&lt; 16) | MUX_PA16C_SERCOM1_PAD0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA16C_SERCOM1_PAD0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 16)</td></tr>
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<tr class="memitem:addd37b78a4a3156ed361f5ac6f7d3d1c"><td class="memItemLeft" align="right" valign="top"><a id="addd37b78a4a3156ed361f5ac6f7d3d1c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#addd37b78a4a3156ed361f5ac6f7d3d1c">PIN_PC27C_SERCOM1_PAD0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(91)</td></tr>
<tr class="memdesc:addd37b78a4a3156ed361f5ac6f7d3d1c"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM1 signal: PAD0 on PC27 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC27C_SERCOM1_PAD0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC27C_SERCOM1_PAD0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#addd37b78a4a3156ed361f5ac6f7d3d1c">PIN_PC27C_SERCOM1_PAD0</a> &lt;&lt; 16) | MUX_PC27C_SERCOM1_PAD0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC27C_SERCOM1_PAD0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 27)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aea8ebe3945e66f4e86d3ef17c82d1035">PIN_PA01D_SERCOM1_PAD1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
<tr class="memdesc:aea8ebe3945e66f4e86d3ef17c82d1035"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM1 signal: PAD1 on PA01 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA01D_SERCOM1_PAD1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA01D_SERCOM1_PAD1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aea8ebe3945e66f4e86d3ef17c82d1035">PIN_PA01D_SERCOM1_PAD1</a> &lt;&lt; 16) | MUX_PA01D_SERCOM1_PAD1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA01D_SERCOM1_PAD1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab5870755f6280141bd85ff709b97c71b">PIN_PA17C_SERCOM1_PAD1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(17)</td></tr>
<tr class="memdesc:ab5870755f6280141bd85ff709b97c71b"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM1 signal: PAD1 on PA17 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA17C_SERCOM1_PAD1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA17C_SERCOM1_PAD1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ab5870755f6280141bd85ff709b97c71b">PIN_PA17C_SERCOM1_PAD1</a> &lt;&lt; 16) | MUX_PA17C_SERCOM1_PAD1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA17C_SERCOM1_PAD1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 17)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae6cc937345ff396800352e1403b3df6e">PIN_PC28C_SERCOM1_PAD1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(92)</td></tr>
<tr class="memdesc:ae6cc937345ff396800352e1403b3df6e"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM1 signal: PAD1 on PC28 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC28C_SERCOM1_PAD1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC28C_SERCOM1_PAD1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ae6cc937345ff396800352e1403b3df6e">PIN_PC28C_SERCOM1_PAD1</a> &lt;&lt; 16) | MUX_PC28C_SERCOM1_PAD1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC28C_SERCOM1_PAD1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 28)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a174823ce52f5a2bd5c316b7a8bddf1f8">PIN_PA30D_SERCOM1_PAD2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(30)</td></tr>
<tr class="memdesc:a174823ce52f5a2bd5c316b7a8bddf1f8"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM1 signal: PAD2 on PA30 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA30D_SERCOM1_PAD2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA30D_SERCOM1_PAD2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a174823ce52f5a2bd5c316b7a8bddf1f8">PIN_PA30D_SERCOM1_PAD2</a> &lt;&lt; 16) | MUX_PA30D_SERCOM1_PAD2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA30D_SERCOM1_PAD2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 30)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3288224f49ad40a523bb06d304fb139d">PIN_PA18C_SERCOM1_PAD2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(18)</td></tr>
<tr class="memdesc:a3288224f49ad40a523bb06d304fb139d"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM1 signal: PAD2 on PA18 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA18C_SERCOM1_PAD2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA18C_SERCOM1_PAD2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a3288224f49ad40a523bb06d304fb139d">PIN_PA18C_SERCOM1_PAD2</a> &lt;&lt; 16) | MUX_PA18C_SERCOM1_PAD2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA18C_SERCOM1_PAD2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 18)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a876739751d00a5e098bc52d03378669a">PIN_PB22C_SERCOM1_PAD2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(54)</td></tr>
<tr class="memdesc:a876739751d00a5e098bc52d03378669a"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM1 signal: PAD2 on PB22 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB22C_SERCOM1_PAD2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB22C_SERCOM1_PAD2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a876739751d00a5e098bc52d03378669a">PIN_PB22C_SERCOM1_PAD2</a> &lt;&lt; 16) | MUX_PB22C_SERCOM1_PAD2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB22C_SERCOM1_PAD2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 22)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa462211d59fefd3ceccb2f5ce40d800b">PIN_PA31D_SERCOM1_PAD3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(31)</td></tr>
<tr class="memdesc:aa462211d59fefd3ceccb2f5ce40d800b"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM1 signal: PAD3 on PA31 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA31D_SERCOM1_PAD3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA31D_SERCOM1_PAD3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aa462211d59fefd3ceccb2f5ce40d800b">PIN_PA31D_SERCOM1_PAD3</a> &lt;&lt; 16) | MUX_PA31D_SERCOM1_PAD3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA31D_SERCOM1_PAD3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 31)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8605e46feb172377bc736e2c869009fe">PIN_PA19C_SERCOM1_PAD3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(19)</td></tr>
<tr class="memdesc:a8605e46feb172377bc736e2c869009fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM1 signal: PAD3 on PA19 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA19C_SERCOM1_PAD3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA19C_SERCOM1_PAD3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a8605e46feb172377bc736e2c869009fe">PIN_PA19C_SERCOM1_PAD3</a> &lt;&lt; 16) | MUX_PA19C_SERCOM1_PAD3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA19C_SERCOM1_PAD3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 19)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae12453a3e26c6af1bfbdfda91112470c">PIN_PB23C_SERCOM1_PAD3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(55)</td></tr>
<tr class="memdesc:ae12453a3e26c6af1bfbdfda91112470c"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM1 signal: PAD3 on PB23 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB23C_SERCOM1_PAD3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB23C_SERCOM1_PAD3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ae12453a3e26c6af1bfbdfda91112470c">PIN_PB23C_SERCOM1_PAD3</a> &lt;&lt; 16) | MUX_PB23C_SERCOM1_PAD3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB23C_SERCOM1_PAD3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 23)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a96cb98a981bc9c4f238d9a9f03fddc02">PIN_PA04E_TC0_WO0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
<tr class="memdesc:a96cb98a981bc9c4f238d9a9f03fddc02"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC0 signal: WO0 on PA04 mux E. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA04E_TC0_WO0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA04E_TC0_WO0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a96cb98a981bc9c4f238d9a9f03fddc02">PIN_PA04E_TC0_WO0</a> &lt;&lt; 16) | MUX_PA04E_TC0_WO0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA04E_TC0_WO0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a49ff4304622eae5e2c1b0480a9bd0fd1">PIN_PA08E_TC0_WO0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
<tr class="memdesc:a49ff4304622eae5e2c1b0480a9bd0fd1"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC0 signal: WO0 on PA08 mux E. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA08E_TC0_WO0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA08E_TC0_WO0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a49ff4304622eae5e2c1b0480a9bd0fd1">PIN_PA08E_TC0_WO0</a> &lt;&lt; 16) | MUX_PA08E_TC0_WO0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA08E_TC0_WO0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#addd26211e641ab0933399ed1b89fb2fd">PIN_PB30E_TC0_WO0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(62)</td></tr>
<tr class="memdesc:addd26211e641ab0933399ed1b89fb2fd"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC0 signal: WO0 on PB30 mux E. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB30E_TC0_WO0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB30E_TC0_WO0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#addd26211e641ab0933399ed1b89fb2fd">PIN_PB30E_TC0_WO0</a> &lt;&lt; 16) | MUX_PB30E_TC0_WO0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB30E_TC0_WO0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 30)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a690d541b2f41b5cd008524c402a3ba07">PIN_PA05E_TC0_WO1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
<tr class="memdesc:a690d541b2f41b5cd008524c402a3ba07"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC0 signal: WO1 on PA05 mux E. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA05E_TC0_WO1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA05E_TC0_WO1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a690d541b2f41b5cd008524c402a3ba07">PIN_PA05E_TC0_WO1</a> &lt;&lt; 16) | MUX_PA05E_TC0_WO1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA05E_TC0_WO1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 5)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7efda3b84fd3ef46234de7e3f0ae867d">PIN_PA09E_TC0_WO1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
<tr class="memdesc:a7efda3b84fd3ef46234de7e3f0ae867d"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC0 signal: WO1 on PA09 mux E. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA09E_TC0_WO1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA09E_TC0_WO1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a7efda3b84fd3ef46234de7e3f0ae867d">PIN_PA09E_TC0_WO1</a> &lt;&lt; 16) | MUX_PA09E_TC0_WO1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA09E_TC0_WO1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5e4a347ac0c282ef3d940f5c18bd6fec">PIN_PB31E_TC0_WO1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(63)</td></tr>
<tr class="memdesc:a5e4a347ac0c282ef3d940f5c18bd6fec"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC0 signal: WO1 on PB31 mux E. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB31E_TC0_WO1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB31E_TC0_WO1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a5e4a347ac0c282ef3d940f5c18bd6fec">PIN_PB31E_TC0_WO1</a> &lt;&lt; 16) | MUX_PB31E_TC0_WO1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB31E_TC0_WO1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 31)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0b1a620114f9f8556b888ef1b4b44589">PIN_PA06E_TC1_WO0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
<tr class="memdesc:a0b1a620114f9f8556b888ef1b4b44589"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC1 signal: WO0 on PA06 mux E. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA06E_TC1_WO0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA06E_TC1_WO0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a0b1a620114f9f8556b888ef1b4b44589">PIN_PA06E_TC1_WO0</a> &lt;&lt; 16) | MUX_PA06E_TC1_WO0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA06E_TC1_WO0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 6)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a769ef151929a870e73e8d41f6a241768">PIN_PA10E_TC1_WO0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
<tr class="memdesc:a769ef151929a870e73e8d41f6a241768"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC1 signal: WO0 on PA10 mux E. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA10E_TC1_WO0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA10E_TC1_WO0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a769ef151929a870e73e8d41f6a241768">PIN_PA10E_TC1_WO0</a> &lt;&lt; 16) | MUX_PA10E_TC1_WO0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA10E_TC1_WO0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#abc7767be99b0228b55d59c09ad446b8a">PIN_PA07E_TC1_WO1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
<tr class="memdesc:abc7767be99b0228b55d59c09ad446b8a"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC1 signal: WO1 on PA07 mux E. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA07E_TC1_WO1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA07E_TC1_WO1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#abc7767be99b0228b55d59c09ad446b8a">PIN_PA07E_TC1_WO1</a> &lt;&lt; 16) | MUX_PA07E_TC1_WO1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA07E_TC1_WO1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2b4d6bddd8eba6f8cc18c90f4993f581">PIN_PA11E_TC1_WO1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
<tr class="memdesc:a2b4d6bddd8eba6f8cc18c90f4993f581"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC1 signal: WO1 on PA11 mux E. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA11E_TC1_WO1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA11E_TC1_WO1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a2b4d6bddd8eba6f8cc18c90f4993f581">PIN_PA11E_TC1_WO1</a> &lt;&lt; 16) | MUX_PA11E_TC1_WO1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA11E_TC1_WO1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0b8e7ed3fcaff1e2b5ade0945d8a7eb0">PIN_PA24H_USB_DM</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(24)</td></tr>
<tr class="memdesc:a0b8e7ed3fcaff1e2b5ade0945d8a7eb0"><td class="mdescLeft">&#160;</td><td class="mdescRight">USB signal: DM on PA24 mux H. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA24H_USB_DM</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA24H_USB_DM</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a0b8e7ed3fcaff1e2b5ade0945d8a7eb0">PIN_PA24H_USB_DM</a> &lt;&lt; 16) | MUX_PA24H_USB_DM)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA24H_USB_DM</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 24)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#afeea74fc39b7f158ef211aa25cedee4c">PIN_PA25H_USB_DP</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(25)</td></tr>
<tr class="memdesc:afeea74fc39b7f158ef211aa25cedee4c"><td class="mdescLeft">&#160;</td><td class="mdescRight">USB signal: DP on PA25 mux H. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA25H_USB_DP</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA25H_USB_DP</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#afeea74fc39b7f158ef211aa25cedee4c">PIN_PA25H_USB_DP</a> &lt;&lt; 16) | MUX_PA25H_USB_DP)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA25H_USB_DP</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 25)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4d9b36157980753639c3a13102d315d3">PIN_PA23H_USB_SOF_1KHZ</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(23)</td></tr>
<tr class="memdesc:a4d9b36157980753639c3a13102d315d3"><td class="mdescLeft">&#160;</td><td class="mdescRight">USB signal: SOF_1KHZ on PA23 mux H. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA23H_USB_SOF_1KHZ</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA23H_USB_SOF_1KHZ</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a4d9b36157980753639c3a13102d315d3">PIN_PA23H_USB_SOF_1KHZ</a> &lt;&lt; 16) | MUX_PA23H_USB_SOF_1KHZ)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA23H_USB_SOF_1KHZ</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 23)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aaa6e047e0d2ef0f90256ce2e4a7e6265">PIN_PB22H_USB_SOF_1KHZ</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(54)</td></tr>
<tr class="memdesc:aaa6e047e0d2ef0f90256ce2e4a7e6265"><td class="mdescLeft">&#160;</td><td class="mdescRight">USB signal: SOF_1KHZ on PB22 mux H. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB22H_USB_SOF_1KHZ</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB22H_USB_SOF_1KHZ</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aaa6e047e0d2ef0f90256ce2e4a7e6265">PIN_PB22H_USB_SOF_1KHZ</a> &lt;&lt; 16) | MUX_PB22H_USB_SOF_1KHZ)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB22H_USB_SOF_1KHZ</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 22)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac5de783a40bb1bca0e1f78da985977d2">PIN_PA09D_SERCOM2_PAD0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
<tr class="memdesc:ac5de783a40bb1bca0e1f78da985977d2"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM2 signal: PAD0 on PA09 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA09D_SERCOM2_PAD0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ac5de783a40bb1bca0e1f78da985977d2">PIN_PA09D_SERCOM2_PAD0</a> &lt;&lt; 16) | MUX_PA09D_SERCOM2_PAD0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA09D_SERCOM2_PAD0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad9efbe6a006569dc39d2c545bea4b244">PIN_PB25D_SERCOM2_PAD0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(57)</td></tr>
<tr class="memdesc:ad9efbe6a006569dc39d2c545bea4b244"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM2 signal: PAD0 on PB25 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB25D_SERCOM2_PAD0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB25D_SERCOM2_PAD0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ad9efbe6a006569dc39d2c545bea4b244">PIN_PB25D_SERCOM2_PAD0</a> &lt;&lt; 16) | MUX_PB25D_SERCOM2_PAD0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB25D_SERCOM2_PAD0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 25)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3d84d25427ce818aa6d829f84c947024">PIN_PA12C_SERCOM2_PAD0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
<tr class="memdesc:a3d84d25427ce818aa6d829f84c947024"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM2 signal: PAD0 on PA12 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA12C_SERCOM2_PAD0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA12C_SERCOM2_PAD0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a3d84d25427ce818aa6d829f84c947024">PIN_PA12C_SERCOM2_PAD0</a> &lt;&lt; 16) | MUX_PA12C_SERCOM2_PAD0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA12C_SERCOM2_PAD0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6169a872ff65b63047f9b1fd6d7f0872">PIN_PA08D_SERCOM2_PAD1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
<tr class="memdesc:a6169a872ff65b63047f9b1fd6d7f0872"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM2 signal: PAD1 on PA08 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA08D_SERCOM2_PAD1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA08D_SERCOM2_PAD1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a6169a872ff65b63047f9b1fd6d7f0872">PIN_PA08D_SERCOM2_PAD1</a> &lt;&lt; 16) | MUX_PA08D_SERCOM2_PAD1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA08D_SERCOM2_PAD1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aace4ee51952113c11b2af1ed5299185e">PIN_PB24D_SERCOM2_PAD1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(56)</td></tr>
<tr class="memdesc:aace4ee51952113c11b2af1ed5299185e"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM2 signal: PAD1 on PB24 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB24D_SERCOM2_PAD1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB24D_SERCOM2_PAD1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aace4ee51952113c11b2af1ed5299185e">PIN_PB24D_SERCOM2_PAD1</a> &lt;&lt; 16) | MUX_PB24D_SERCOM2_PAD1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB24D_SERCOM2_PAD1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 24)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7db12df2b3d1bdd361857143b1bb54ba">PIN_PA13C_SERCOM2_PAD1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
<tr class="memdesc:a7db12df2b3d1bdd361857143b1bb54ba"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM2 signal: PAD1 on PA13 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA13C_SERCOM2_PAD1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA13C_SERCOM2_PAD1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a7db12df2b3d1bdd361857143b1bb54ba">PIN_PA13C_SERCOM2_PAD1</a> &lt;&lt; 16) | MUX_PA13C_SERCOM2_PAD1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA13C_SERCOM2_PAD1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a074dbb37fca09ab1f66650959a41fd2c">PIN_PA10D_SERCOM2_PAD2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
<tr class="memdesc:a074dbb37fca09ab1f66650959a41fd2c"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM2 signal: PAD2 on PA10 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA10D_SERCOM2_PAD2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA10D_SERCOM2_PAD2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a074dbb37fca09ab1f66650959a41fd2c">PIN_PA10D_SERCOM2_PAD2</a> &lt;&lt; 16) | MUX_PA10D_SERCOM2_PAD2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA10D_SERCOM2_PAD2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2d3cc3363669ba47a8dafebe1e10ef61">PIN_PC24D_SERCOM2_PAD2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(88)</td></tr>
<tr class="memdesc:a2d3cc3363669ba47a8dafebe1e10ef61"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM2 signal: PAD2 on PC24 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC24D_SERCOM2_PAD2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC24D_SERCOM2_PAD2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a2d3cc3363669ba47a8dafebe1e10ef61">PIN_PC24D_SERCOM2_PAD2</a> &lt;&lt; 16) | MUX_PC24D_SERCOM2_PAD2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC24D_SERCOM2_PAD2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 24)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac0e1daf7ba564bd868fdb4b53ada5751">PIN_PA14C_SERCOM2_PAD2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
<tr class="memdesc:ac0e1daf7ba564bd868fdb4b53ada5751"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM2 signal: PAD2 on PA14 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA14C_SERCOM2_PAD2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA14C_SERCOM2_PAD2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ac0e1daf7ba564bd868fdb4b53ada5751">PIN_PA14C_SERCOM2_PAD2</a> &lt;&lt; 16) | MUX_PA14C_SERCOM2_PAD2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA14C_SERCOM2_PAD2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac266976ecf2df78224be648346faf789">PIN_PA11D_SERCOM2_PAD3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
<tr class="memdesc:ac266976ecf2df78224be648346faf789"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM2 signal: PAD3 on PA11 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA11D_SERCOM2_PAD3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA11D_SERCOM2_PAD3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ac266976ecf2df78224be648346faf789">PIN_PA11D_SERCOM2_PAD3</a> &lt;&lt; 16) | MUX_PA11D_SERCOM2_PAD3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA11D_SERCOM2_PAD3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#abfdc4d762c99b2e90ba5fcbbb486f47c">PIN_PC25D_SERCOM2_PAD3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(89)</td></tr>
<tr class="memdesc:abfdc4d762c99b2e90ba5fcbbb486f47c"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM2 signal: PAD3 on PC25 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC25D_SERCOM2_PAD3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC25D_SERCOM2_PAD3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#abfdc4d762c99b2e90ba5fcbbb486f47c">PIN_PC25D_SERCOM2_PAD3</a> &lt;&lt; 16) | MUX_PC25D_SERCOM2_PAD3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC25D_SERCOM2_PAD3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 25)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af8dfa9adfe5ca9c951d4914889e0cda4">PIN_PA15C_SERCOM2_PAD3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(15)</td></tr>
<tr class="memdesc:af8dfa9adfe5ca9c951d4914889e0cda4"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM2 signal: PAD3 on PA15 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA15C_SERCOM2_PAD3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA15C_SERCOM2_PAD3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#af8dfa9adfe5ca9c951d4914889e0cda4">PIN_PA15C_SERCOM2_PAD3</a> &lt;&lt; 16) | MUX_PA15C_SERCOM2_PAD3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA15C_SERCOM2_PAD3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 15)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a35a80f6f9d1bbc67e5481643bbb0bb83">PIN_PA17D_SERCOM3_PAD0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(17)</td></tr>
<tr class="memdesc:a35a80f6f9d1bbc67e5481643bbb0bb83"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM3 signal: PAD0 on PA17 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA17D_SERCOM3_PAD0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA17D_SERCOM3_PAD0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a35a80f6f9d1bbc67e5481643bbb0bb83">PIN_PA17D_SERCOM3_PAD0</a> &lt;&lt; 16) | MUX_PA17D_SERCOM3_PAD0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA17D_SERCOM3_PAD0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 17)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a9cd984c9db10e1b847bfc4224b7d324b">PIN_PA22C_SERCOM3_PAD0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(22)</td></tr>
<tr class="memdesc:a9cd984c9db10e1b847bfc4224b7d324b"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM3 signal: PAD0 on PA22 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA22C_SERCOM3_PAD0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA22C_SERCOM3_PAD0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a9cd984c9db10e1b847bfc4224b7d324b">PIN_PA22C_SERCOM3_PAD0</a> &lt;&lt; 16) | MUX_PA22C_SERCOM3_PAD0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA22C_SERCOM3_PAD0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 22)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a11b6ccdb29c02edd24e4083791682106">PIN_PB20C_SERCOM3_PAD0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(52)</td></tr>
<tr class="memdesc:a11b6ccdb29c02edd24e4083791682106"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM3 signal: PAD0 on PB20 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB20C_SERCOM3_PAD0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB20C_SERCOM3_PAD0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a11b6ccdb29c02edd24e4083791682106">PIN_PB20C_SERCOM3_PAD0</a> &lt;&lt; 16) | MUX_PB20C_SERCOM3_PAD0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB20C_SERCOM3_PAD0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 20)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7496dfac12b0c3c3379324b02df308a0">PIN_PA16D_SERCOM3_PAD1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(16)</td></tr>
<tr class="memdesc:a7496dfac12b0c3c3379324b02df308a0"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM3 signal: PAD1 on PA16 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA16D_SERCOM3_PAD1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA16D_SERCOM3_PAD1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a7496dfac12b0c3c3379324b02df308a0">PIN_PA16D_SERCOM3_PAD1</a> &lt;&lt; 16) | MUX_PA16D_SERCOM3_PAD1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA16D_SERCOM3_PAD1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 16)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af3317ce41a4529ece8179416b7c1a56f">PIN_PA23C_SERCOM3_PAD1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(23)</td></tr>
<tr class="memdesc:af3317ce41a4529ece8179416b7c1a56f"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM3 signal: PAD1 on PA23 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA23C_SERCOM3_PAD1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA23C_SERCOM3_PAD1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#af3317ce41a4529ece8179416b7c1a56f">PIN_PA23C_SERCOM3_PAD1</a> &lt;&lt; 16) | MUX_PA23C_SERCOM3_PAD1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA23C_SERCOM3_PAD1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 23)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8d808bf85acfcc204156347146aa7118">PIN_PB21C_SERCOM3_PAD1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(53)</td></tr>
<tr class="memdesc:a8d808bf85acfcc204156347146aa7118"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM3 signal: PAD1 on PB21 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB21C_SERCOM3_PAD1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB21C_SERCOM3_PAD1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a8d808bf85acfcc204156347146aa7118">PIN_PB21C_SERCOM3_PAD1</a> &lt;&lt; 16) | MUX_PB21C_SERCOM3_PAD1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB21C_SERCOM3_PAD1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 21)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa99a01237c215665208d0d29b17a27d3">PIN_PA18D_SERCOM3_PAD2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(18)</td></tr>
<tr class="memdesc:aa99a01237c215665208d0d29b17a27d3"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM3 signal: PAD2 on PA18 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA18D_SERCOM3_PAD2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA18D_SERCOM3_PAD2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aa99a01237c215665208d0d29b17a27d3">PIN_PA18D_SERCOM3_PAD2</a> &lt;&lt; 16) | MUX_PA18D_SERCOM3_PAD2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA18D_SERCOM3_PAD2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 18)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab474048e84d45a520ab940f5a02dd7a8">PIN_PA20D_SERCOM3_PAD2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(20)</td></tr>
<tr class="memdesc:ab474048e84d45a520ab940f5a02dd7a8"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM3 signal: PAD2 on PA20 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA20D_SERCOM3_PAD2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA20D_SERCOM3_PAD2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ab474048e84d45a520ab940f5a02dd7a8">PIN_PA20D_SERCOM3_PAD2</a> &lt;&lt; 16) | MUX_PA20D_SERCOM3_PAD2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA20D_SERCOM3_PAD2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 20)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af84b9177a74b0cbce8cef9dbd7e2114b">PIN_PA24C_SERCOM3_PAD2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(24)</td></tr>
<tr class="memdesc:af84b9177a74b0cbce8cef9dbd7e2114b"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM3 signal: PAD2 on PA24 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA24C_SERCOM3_PAD2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA24C_SERCOM3_PAD2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#af84b9177a74b0cbce8cef9dbd7e2114b">PIN_PA24C_SERCOM3_PAD2</a> &lt;&lt; 16) | MUX_PA24C_SERCOM3_PAD2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA24C_SERCOM3_PAD2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 24)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2ed5bb59474047684f40617d5ecfd461">PIN_PA19D_SERCOM3_PAD3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(19)</td></tr>
<tr class="memdesc:a2ed5bb59474047684f40617d5ecfd461"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM3 signal: PAD3 on PA19 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA19D_SERCOM3_PAD3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA19D_SERCOM3_PAD3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a2ed5bb59474047684f40617d5ecfd461">PIN_PA19D_SERCOM3_PAD3</a> &lt;&lt; 16) | MUX_PA19D_SERCOM3_PAD3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA19D_SERCOM3_PAD3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 19)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3852b08953bca00e4840cf4017d856f6">PIN_PA21D_SERCOM3_PAD3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(21)</td></tr>
<tr class="memdesc:a3852b08953bca00e4840cf4017d856f6"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM3 signal: PAD3 on PA21 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA21D_SERCOM3_PAD3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA21D_SERCOM3_PAD3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a3852b08953bca00e4840cf4017d856f6">PIN_PA21D_SERCOM3_PAD3</a> &lt;&lt; 16) | MUX_PA21D_SERCOM3_PAD3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA21D_SERCOM3_PAD3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 21)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7f86d5f1e4d85d8c3888682c2505a33f">PIN_PA25C_SERCOM3_PAD3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(25)</td></tr>
<tr class="memdesc:a7f86d5f1e4d85d8c3888682c2505a33f"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM3 signal: PAD3 on PA25 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA25C_SERCOM3_PAD3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA25C_SERCOM3_PAD3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a7f86d5f1e4d85d8c3888682c2505a33f">PIN_PA25C_SERCOM3_PAD3</a> &lt;&lt; 16) | MUX_PA25C_SERCOM3_PAD3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA25C_SERCOM3_PAD3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 25)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1447d994a01689c1f405ab71251dd10c">PIN_PA20G_TCC0_WO0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(20)</td></tr>
<tr class="memdesc:a1447d994a01689c1f405ab71251dd10c"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC0 signal: WO0 on PA20 mux G. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA20G_TCC0_WO0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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<tr class="memdesc:a29b479f14d4f419d7128c72481adaa69"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC0 signal: WO0 on PB12 mux G. <br /></td></tr>
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<tr class="memdesc:a9bc32b65378a98bb6a0a33ac17503a9b"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC0 signal: WO0 on PA08 mux F. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6ceeee3627613c8b5b8beeb576f782b9">PIN_PC10F_TCC0_WO0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(74)</td></tr>
<tr class="memdesc:a6ceeee3627613c8b5b8beeb576f782b9"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC0 signal: WO0 on PC10 mux F. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC10F_TCC0_WO0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a6ceeee3627613c8b5b8beeb576f782b9">PIN_PC10F_TCC0_WO0</a> &lt;&lt; 16) | MUX_PC10F_TCC0_WO0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab90dfd1c85797cfecee5618da9d2c8e1">PIN_PC16F_TCC0_WO0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(80)</td></tr>
<tr class="memdesc:ab90dfd1c85797cfecee5618da9d2c8e1"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC0 signal: WO0 on PC16 mux F. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC16F_TCC0_WO0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ab90dfd1c85797cfecee5618da9d2c8e1">PIN_PC16F_TCC0_WO0</a> &lt;&lt; 16) | MUX_PC16F_TCC0_WO0)</td></tr>
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<tr class="memdesc:a19850f46bc2077f7468e9c9122aff45b"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC0 signal: WO1 on PA21 mux G. <br /></td></tr>
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<tr class="memdesc:a344342f987fb95c5f8fcd7c5c563d6c6"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC0 signal: WO1 on PB13 mux G. <br /></td></tr>
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<tr class="memdesc:ad84013705279dd82d320a31f8973c20d"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC0 signal: WO1 on PA09 mux F. <br /></td></tr>
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<tr class="memdesc:a8e0a101968ddee1f7d3183b108c18bdb"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC0 signal: WO1 on PC11 mux F. <br /></td></tr>
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<tr class="memdesc:a08989fda0b125c2861bd331a33f02f9c"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC0 signal: WO3 on PC13 mux F. <br /></td></tr>
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<tr class="memdesc:a46190b2208f375c663b37bc37dcbdfcc"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC0 signal: WO4 on PC14 mux F. <br /></td></tr>
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<tr class="memdesc:a6a91473ab529126eacf6a59913ae3a76"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC0 signal: WO4 on PC20 mux F. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC20F_TCC0_WO4</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a6a91473ab529126eacf6a59913ae3a76">PIN_PC20F_TCC0_WO4</a> &lt;&lt; 16) | MUX_PC20F_TCC0_WO4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC20F_TCC0_WO4</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 20)</td></tr>
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<tr class="memdesc:a93942ed172fd0c8e8cbe233cca49c7ae"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC0 signal: WO5 on PA17 mux G. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA17G_TCC0_WO5</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a93942ed172fd0c8e8cbe233cca49c7ae">PIN_PA17G_TCC0_WO5</a> &lt;&lt; 16) | MUX_PA17G_TCC0_WO5)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA17G_TCC0_WO5</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 17)</td></tr>
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<tr class="memdesc:a29e9e728fc3f3361eafff32f81910739"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC0 signal: WO5 on PB17 mux G. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB17G_TCC0_WO5</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a29e9e728fc3f3361eafff32f81910739">PIN_PB17G_TCC0_WO5</a> &lt;&lt; 16) | MUX_PB17G_TCC0_WO5)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB17G_TCC0_WO5</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 17)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a53b3ae2877edaff5fdc3d34f8ebddab0">PIN_PB11F_TCC0_WO5</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(43)</td></tr>
<tr class="memdesc:a53b3ae2877edaff5fdc3d34f8ebddab0"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC0 signal: WO5 on PB11 mux F. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB11F_TCC0_WO5</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a53b3ae2877edaff5fdc3d34f8ebddab0">PIN_PB11F_TCC0_WO5</a> &lt;&lt; 16) | MUX_PB11F_TCC0_WO5)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB11F_TCC0_WO5</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa9885f60f08de80c908068a654bc7e91">PIN_PC15F_TCC0_WO5</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(79)</td></tr>
<tr class="memdesc:aa9885f60f08de80c908068a654bc7e91"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC0 signal: WO5 on PC15 mux F. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC15F_TCC0_WO5</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aa9885f60f08de80c908068a654bc7e91">PIN_PC15F_TCC0_WO5</a> &lt;&lt; 16) | MUX_PC15F_TCC0_WO5)</td></tr>
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<tr class="memdesc:a8b7983d112e62bf3ad40f6f63887f6c5"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC0 signal: WO5 on PC21 mux F. <br /></td></tr>
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<tr class="memdesc:ada6ef2e4e4def6c96f1b1108ce0f934c"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC0 signal: WO6 on PA18 mux G. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA18G_TCC0_WO6</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ada6ef2e4e4def6c96f1b1108ce0f934c">PIN_PA18G_TCC0_WO6</a> &lt;&lt; 16) | MUX_PA18G_TCC0_WO6)</td></tr>
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<tr class="memdesc:a882b1b416376154d24e207f02b56d0e7"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC0 signal: WO6 on PB30 mux G. <br /></td></tr>
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<tr class="memdesc:a809f70a2f3aa323f63066eac22b626d9"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC0 signal: WO6 on PA12 mux F. <br /></td></tr>
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<tr class="memdesc:aca1f8264ff07ed2a77f3b89f7d000aef"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC0 signal: WO7 on PB31 mux G. <br /></td></tr>
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<tr class="memdesc:a3894371599a07265b37600df157d1d49"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC1 signal: WO0 on PB10 mux G. <br /></td></tr>
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<tr class="memdesc:a82aabf58d9a048b474d306bd3c7f0a13"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC1 signal: WO0 on PC14 mux G. <br /></td></tr>
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<tr class="memdesc:a2fb8a8cc8d8886a6b688a8ea597ad112"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC1 signal: WO1 on PC15 mux G. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC15G_TCC1_WO1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a2fb8a8cc8d8886a6b688a8ea597ad112">PIN_PC15G_TCC1_WO1</a> &lt;&lt; 16) | MUX_PC15G_TCC1_WO1)</td></tr>
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<tr class="memdesc:aa42a8593f2233adb8b91b85272c4051d"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC1 signal: WO1 on PA17 mux F. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA17F_TCC1_WO1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aa42a8593f2233adb8b91b85272c4051d">PIN_PA17F_TCC1_WO1</a> &lt;&lt; 16) | MUX_PA17F_TCC1_WO1)</td></tr>
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<tr class="memdesc:a91769fd831aced51b7bc7f2c931a16d6"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC1 signal: WO1 on PB19 mux F. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB19F_TCC1_WO1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a91769fd831aced51b7bc7f2c931a16d6">PIN_PB19F_TCC1_WO1</a> &lt;&lt; 16) | MUX_PB19F_TCC1_WO1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6cb1ea1431c1af56edd96f2f70e517a3">PIN_PA12G_TCC1_WO2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
<tr class="memdesc:a6cb1ea1431c1af56edd96f2f70e517a3"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC1 signal: WO2 on PA12 mux G. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA12G_TCC1_WO2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a6cb1ea1431c1af56edd96f2f70e517a3">PIN_PA12G_TCC1_WO2</a> &lt;&lt; 16) | MUX_PA12G_TCC1_WO2)</td></tr>
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<tr class="memdesc:a72f18803bcfe991b76bd7796818b2bdb"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC1 signal: WO2 on PA14 mux G. <br /></td></tr>
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<tr class="memdesc:a43238670ea540fb013e9d1f3235401bc"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC1 signal: WO2 on PA18 mux F. <br /></td></tr>
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<tr class="memdesc:a60770bf3d3cbdecf6ce2743a62875a83"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC1 signal: WO2 on PB20 mux F. <br /></td></tr>
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<tr class="memdesc:a2f32f7220f69342cfd259de16180d3e7"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC1 signal: WO3 on PA13 mux G. <br /></td></tr>
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<tr class="memdesc:ad69cf734b6bdef0e9edab0eac14156b7"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC1 signal: WO3 on PA19 mux F. <br /></td></tr>
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<tr class="memdesc:af12e704c23f113594a0d323e035ce3df"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC1 signal: WO3 on PB21 mux F. <br /></td></tr>
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<tr class="memdesc:aad716983261739485a92fb5e554befcf"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC1 signal: WO4 on PA08 mux G. <br /></td></tr>
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<tr class="memdesc:a7bceef27f65e38d27ddb39710633de66"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC1 signal: WO4 on PC10 mux G. <br /></td></tr>
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<tr class="memdesc:a2fefa33580727587333b52f159af7556"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC1 signal: WO5 on PA09 mux G. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC11G_TCC1_WO5</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ab4a2fd55ec4b67b41d9801c71279fbc6">PIN_PC11G_TCC1_WO5</a> &lt;&lt; 16) | MUX_PC11G_TCC1_WO5)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA21F_TCC1_WO5</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ad828de97f945f3acfc68a0a616433d3e">PIN_PA21F_TCC1_WO5</a> &lt;&lt; 16) | MUX_PA21F_TCC1_WO5)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0b5c35beb3b82628543b2e3dda2af769">PIN_PA10G_TCC1_WO6</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
<tr class="memdesc:a0b5c35beb3b82628543b2e3dda2af769"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC1 signal: WO6 on PA10 mux G. <br /></td></tr>
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<tr class="memdesc:a5d4e4164de6400a9fdcb98ce2d37408f"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC1 signal: WO6 on PC12 mux G. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC12G_TCC1_WO6</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a5d4e4164de6400a9fdcb98ce2d37408f">PIN_PC12G_TCC1_WO6</a> &lt;&lt; 16) | MUX_PC12G_TCC1_WO6)</td></tr>
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<tr class="memdesc:a3dc60af5cdbe8f66dc2bcac771ed1ea0"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC1 signal: WO6 on PA22 mux F. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA22F_TCC1_WO6</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a3dc60af5cdbe8f66dc2bcac771ed1ea0">PIN_PA22F_TCC1_WO6</a> &lt;&lt; 16) | MUX_PA22F_TCC1_WO6)</td></tr>
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<tr class="memdesc:a4b791e77a8fa7a3c1a40f55262c771f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC1 signal: WO7 on PA11 mux G. <br /></td></tr>
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<tr class="memdesc:ad9bf895100c37405ff6e98c89edd189c"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC1 signal: WO7 on PC13 mux G. <br /></td></tr>
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<tr class="memdesc:a314ab3a9ff0f51027281c79227c26078"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC1 signal: WO7 on PA23 mux F. <br /></td></tr>
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<tr class="memdesc:aa761970c4cdbf930364f75bef19e7ef5"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC2 signal: WO0 on PA12 mux E. <br /></td></tr>
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<tr class="memdesc:a8d7eddbf3d5b6030518ae474afc417a4"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC2 signal: WO0 on PA16 mux E. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA16E_TC2_WO0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a8d7eddbf3d5b6030518ae474afc417a4">PIN_PA16E_TC2_WO0</a> &lt;&lt; 16) | MUX_PA16E_TC2_WO0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a9992a46283cbefd638c25c11299473e6">PIN_PA00E_TC2_WO0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
<tr class="memdesc:a9992a46283cbefd638c25c11299473e6"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC2 signal: WO0 on PA00 mux E. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA00E_TC2_WO0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a9992a46283cbefd638c25c11299473e6">PIN_PA00E_TC2_WO0</a> &lt;&lt; 16) | MUX_PA00E_TC2_WO0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA00E_TC2_WO0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 0)</td></tr>
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<tr class="memdesc:adf9ba2f85b9f5683706a12af451d037e"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC2 signal: WO1 on PA01 mux E. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA01E_TC2_WO1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#adf9ba2f85b9f5683706a12af451d037e">PIN_PA01E_TC2_WO1</a> &lt;&lt; 16) | MUX_PA01E_TC2_WO1)</td></tr>
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<tr class="memdesc:a4ad884ff60803c898735bfbc4b9b6a01"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC2 signal: WO1 on PA13 mux E. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA13E_TC2_WO1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a4ad884ff60803c898735bfbc4b9b6a01">PIN_PA13E_TC2_WO1</a> &lt;&lt; 16) | MUX_PA13E_TC2_WO1)</td></tr>
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<tr class="memdesc:a4c473a6ac59c3836decf88485c83d7d4"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC2 signal: WO1 on PA17 mux E. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA17E_TC2_WO1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a4c473a6ac59c3836decf88485c83d7d4">PIN_PA17E_TC2_WO1</a> &lt;&lt; 16) | MUX_PA17E_TC2_WO1)</td></tr>
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<tr class="memdesc:a939926952c9ac148cafb3711de6c49bb"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC3 signal: WO0 on PA18 mux E. <br /></td></tr>
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<tr class="memdesc:a0cfe738890e6273b42dc25d87ceacab9"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC3 signal: WO0 on PA14 mux E. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA14E_TC3_WO0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a0cfe738890e6273b42dc25d87ceacab9">PIN_PA14E_TC3_WO0</a> &lt;&lt; 16) | MUX_PA14E_TC3_WO0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4cd9c042fff6cc0355d62086367932ec">PIN_PA15E_TC3_WO1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(15)</td></tr>
<tr class="memdesc:a4cd9c042fff6cc0355d62086367932ec"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC3 signal: WO1 on PA15 mux E. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA15E_TC3_WO1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a4cd9c042fff6cc0355d62086367932ec">PIN_PA15E_TC3_WO1</a> &lt;&lt; 16) | MUX_PA15E_TC3_WO1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA15E_TC3_WO1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 15)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac3c5208b6eeef04e542f16e30e5b2e95">PIN_PA19E_TC3_WO1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(19)</td></tr>
<tr class="memdesc:ac3c5208b6eeef04e542f16e30e5b2e95"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC3 signal: WO1 on PA19 mux E. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA19E_TC3_WO1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ac3c5208b6eeef04e542f16e30e5b2e95">PIN_PA19E_TC3_WO1</a> &lt;&lt; 16) | MUX_PA19E_TC3_WO1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA19E_TC3_WO1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 19)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0ab1381e84165e9ed82ff6e5d11c8888">PIN_PA23I_CAN0_RX</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(23)</td></tr>
<tr class="memdesc:a0ab1381e84165e9ed82ff6e5d11c8888"><td class="mdescLeft">&#160;</td><td class="mdescRight">CAN0 signal: RX on PA23 mux I. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA23I_CAN0_RX</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a0ab1381e84165e9ed82ff6e5d11c8888">PIN_PA23I_CAN0_RX</a> &lt;&lt; 16) | MUX_PA23I_CAN0_RX)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA23I_CAN0_RX</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 23)</td></tr>
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<tr class="memdesc:ab3258c13b0ff5caa156ef75c35541558"><td class="mdescLeft">&#160;</td><td class="mdescRight">CAN0 signal: RX on PA25 mux I. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA25I_CAN0_RX</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA25I_CAN0_RX</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ab3258c13b0ff5caa156ef75c35541558">PIN_PA25I_CAN0_RX</a> &lt;&lt; 16) | MUX_PA25I_CAN0_RX)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA25I_CAN0_RX</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 25)</td></tr>
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<tr class="memdesc:a183b5e8cc25edc54870599afd59da7cb"><td class="mdescLeft">&#160;</td><td class="mdescRight">CAN0 signal: TX on PA22 mux I. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA22I_CAN0_TX</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA22I_CAN0_TX</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a183b5e8cc25edc54870599afd59da7cb">PIN_PA22I_CAN0_TX</a> &lt;&lt; 16) | MUX_PA22I_CAN0_TX)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA22I_CAN0_TX</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 22)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae2dcca4d5a79efc615601c5219eebd38">PIN_PA24I_CAN0_TX</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(24)</td></tr>
<tr class="memdesc:ae2dcca4d5a79efc615601c5219eebd38"><td class="mdescLeft">&#160;</td><td class="mdescRight">CAN0 signal: TX on PA24 mux I. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA24I_CAN0_TX</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA24I_CAN0_TX</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ae2dcca4d5a79efc615601c5219eebd38">PIN_PA24I_CAN0_TX</a> &lt;&lt; 16) | MUX_PA24I_CAN0_TX)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA24I_CAN0_TX</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 24)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a584ca0a63440951c28f70dbd39e056e6">PIN_PB13H_CAN1_RX</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(45)</td></tr>
<tr class="memdesc:a584ca0a63440951c28f70dbd39e056e6"><td class="mdescLeft">&#160;</td><td class="mdescRight">CAN1 signal: RX on PB13 mux H. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB13H_CAN1_RX</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB13H_CAN1_RX</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a584ca0a63440951c28f70dbd39e056e6">PIN_PB13H_CAN1_RX</a> &lt;&lt; 16) | MUX_PB13H_CAN1_RX)</td></tr>
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<tr class="memdesc:a90ba5deec4794ccbbf409a41eab91338"><td class="mdescLeft">&#160;</td><td class="mdescRight">CAN1 signal: RX on PB15 mux H. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB15H_CAN1_RX</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a90ba5deec4794ccbbf409a41eab91338">PIN_PB15H_CAN1_RX</a> &lt;&lt; 16) | MUX_PB15H_CAN1_RX)</td></tr>
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<tr class="memdesc:ae09e0cb0f9f4f021767197f474747eb3"><td class="mdescLeft">&#160;</td><td class="mdescRight">CAN1 signal: TX on PB12 mux H. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB12H_CAN1_TX</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ae09e0cb0f9f4f021767197f474747eb3">PIN_PB12H_CAN1_TX</a> &lt;&lt; 16) | MUX_PB12H_CAN1_TX)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB12H_CAN1_TX</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad1d2bc25031f28aca25bf7faad2751d7">PIN_PB14H_CAN1_TX</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(46)</td></tr>
<tr class="memdesc:ad1d2bc25031f28aca25bf7faad2751d7"><td class="mdescLeft">&#160;</td><td class="mdescRight">CAN1 signal: TX on PB14 mux H. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB14H_CAN1_TX</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ad1d2bc25031f28aca25bf7faad2751d7">PIN_PB14H_CAN1_TX</a> &lt;&lt; 16) | MUX_PB14H_CAN1_TX)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB14H_CAN1_TX</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a115c1290a606c9eefaff58992feaefa5">PIN_PC21L_GMAC_GCOL</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(85)</td></tr>
<tr class="memdesc:a115c1290a606c9eefaff58992feaefa5"><td class="mdescLeft">&#160;</td><td class="mdescRight">GMAC signal: GCOL on PC21 mux L. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC21L_GMAC_GCOL</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC21L_GMAC_GCOL</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a115c1290a606c9eefaff58992feaefa5">PIN_PC21L_GMAC_GCOL</a> &lt;&lt; 16) | MUX_PC21L_GMAC_GCOL)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC21L_GMAC_GCOL</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 21)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a30a52fd41f3541a332b1a097fa9958f0">PIN_PA16L_GMAC_GCRS</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(16)</td></tr>
<tr class="memdesc:a30a52fd41f3541a332b1a097fa9958f0"><td class="mdescLeft">&#160;</td><td class="mdescRight">GMAC signal: GCRS on PA16 mux L. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA16L_GMAC_GCRS</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA16L_GMAC_GCRS</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a30a52fd41f3541a332b1a097fa9958f0">PIN_PA16L_GMAC_GCRS</a> &lt;&lt; 16) | MUX_PA16L_GMAC_GCRS)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA16L_GMAC_GCRS</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 16)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8af84b30c55efdfb5a821fb897ce7a06">PIN_PA20L_GMAC_GMDC</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(20)</td></tr>
<tr class="memdesc:a8af84b30c55efdfb5a821fb897ce7a06"><td class="mdescLeft">&#160;</td><td class="mdescRight">GMAC signal: GMDC on PA20 mux L. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA20L_GMAC_GMDC</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA20L_GMAC_GMDC</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a8af84b30c55efdfb5a821fb897ce7a06">PIN_PA20L_GMAC_GMDC</a> &lt;&lt; 16) | MUX_PA20L_GMAC_GMDC)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA20L_GMAC_GMDC</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 20)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#adc71e6b89c3acd2f53fa4511a57af468">PIN_PB14L_GMAC_GMDC</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(46)</td></tr>
<tr class="memdesc:adc71e6b89c3acd2f53fa4511a57af468"><td class="mdescLeft">&#160;</td><td class="mdescRight">GMAC signal: GMDC on PB14 mux L. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB14L_GMAC_GMDC</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB14L_GMAC_GMDC</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#adc71e6b89c3acd2f53fa4511a57af468">PIN_PB14L_GMAC_GMDC</a> &lt;&lt; 16) | MUX_PB14L_GMAC_GMDC)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB14L_GMAC_GMDC</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a36f561d868f4a6c82e176311732a79c1">PIN_PC11L_GMAC_GMDC</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(75)</td></tr>
<tr class="memdesc:a36f561d868f4a6c82e176311732a79c1"><td class="mdescLeft">&#160;</td><td class="mdescRight">GMAC signal: GMDC on PC11 mux L. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC11L_GMAC_GMDC</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a36f561d868f4a6c82e176311732a79c1">PIN_PC11L_GMAC_GMDC</a> &lt;&lt; 16) | MUX_PC11L_GMAC_GMDC)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1111da8cfd48df4f4e3119744075b4a1">PIN_PA21L_GMAC_GMDIO</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(21)</td></tr>
<tr class="memdesc:a1111da8cfd48df4f4e3119744075b4a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">GMAC signal: GMDIO on PA21 mux L. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA21L_GMAC_GMDIO</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a1111da8cfd48df4f4e3119744075b4a1">PIN_PA21L_GMAC_GMDIO</a> &lt;&lt; 16) | MUX_PA21L_GMAC_GMDIO)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#afa846cf5d0331debc99f1dbc8387a36e">PIN_PB15L_GMAC_GMDIO</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(47)</td></tr>
<tr class="memdesc:afa846cf5d0331debc99f1dbc8387a36e"><td class="mdescLeft">&#160;</td><td class="mdescRight">GMAC signal: GMDIO on PB15 mux L. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB15L_GMAC_GMDIO</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#afa846cf5d0331debc99f1dbc8387a36e">PIN_PB15L_GMAC_GMDIO</a> &lt;&lt; 16) | MUX_PB15L_GMAC_GMDIO)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB15L_GMAC_GMDIO</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 15)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a54ec704f5561b7da7e544b787ef26df7">PIN_PC12L_GMAC_GMDIO</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(76)</td></tr>
<tr class="memdesc:a54ec704f5561b7da7e544b787ef26df7"><td class="mdescLeft">&#160;</td><td class="mdescRight">GMAC signal: GMDIO on PC12 mux L. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC12L_GMAC_GMDIO</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC12L_GMAC_GMDIO</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a54ec704f5561b7da7e544b787ef26df7">PIN_PC12L_GMAC_GMDIO</a> &lt;&lt; 16) | MUX_PC12L_GMAC_GMDIO)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC12L_GMAC_GMDIO</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3d056a847e807035865ed436adc526b5">PIN_PA13L_GMAC_GRX0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
<tr class="memdesc:a3d056a847e807035865ed436adc526b5"><td class="mdescLeft">&#160;</td><td class="mdescRight">GMAC signal: GRX0 on PA13 mux L. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA13L_GMAC_GRX0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA13L_GMAC_GRX0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a3d056a847e807035865ed436adc526b5">PIN_PA13L_GMAC_GRX0</a> &lt;&lt; 16) | MUX_PA13L_GMAC_GRX0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA13L_GMAC_GRX0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a52ea5e39f29541db121496db418c807c">PIN_PA12L_GMAC_GRX1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
<tr class="memdesc:a52ea5e39f29541db121496db418c807c"><td class="mdescLeft">&#160;</td><td class="mdescRight">GMAC signal: GRX1 on PA12 mux L. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA12L_GMAC_GRX1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA12L_GMAC_GRX1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a52ea5e39f29541db121496db418c807c">PIN_PA12L_GMAC_GRX1</a> &lt;&lt; 16) | MUX_PA12L_GMAC_GRX1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA12L_GMAC_GRX1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a53fbb225398a1ff984b8672582b20703">PIN_PC15L_GMAC_GRX2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(79)</td></tr>
<tr class="memdesc:a53fbb225398a1ff984b8672582b20703"><td class="mdescLeft">&#160;</td><td class="mdescRight">GMAC signal: GRX2 on PC15 mux L. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC15L_GMAC_GRX2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC15L_GMAC_GRX2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a53fbb225398a1ff984b8672582b20703">PIN_PC15L_GMAC_GRX2</a> &lt;&lt; 16) | MUX_PC15L_GMAC_GRX2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC15L_GMAC_GRX2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 15)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a980218818061ced2a630067ecf434bf2">PIN_PC14L_GMAC_GRX3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(78)</td></tr>
<tr class="memdesc:a980218818061ced2a630067ecf434bf2"><td class="mdescLeft">&#160;</td><td class="mdescRight">GMAC signal: GRX3 on PC14 mux L. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC14L_GMAC_GRX3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC14L_GMAC_GRX3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a980218818061ced2a630067ecf434bf2">PIN_PC14L_GMAC_GRX3</a> &lt;&lt; 16) | MUX_PC14L_GMAC_GRX3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC14L_GMAC_GRX3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a044d4c611bed186005ab1d48c0415402">PIN_PC18L_GMAC_GRXCK</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(82)</td></tr>
<tr class="memdesc:a044d4c611bed186005ab1d48c0415402"><td class="mdescLeft">&#160;</td><td class="mdescRight">GMAC signal: GRXCK on PC18 mux L. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC18L_GMAC_GRXCK</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC18L_GMAC_GRXCK</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a044d4c611bed186005ab1d48c0415402">PIN_PC18L_GMAC_GRXCK</a> &lt;&lt; 16) | MUX_PC18L_GMAC_GRXCK)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC18L_GMAC_GRXCK</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 18)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a229488f377e575ee45b2e979d7b43524">PIN_PC20L_GMAC_GRXDV</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(84)</td></tr>
<tr class="memdesc:a229488f377e575ee45b2e979d7b43524"><td class="mdescLeft">&#160;</td><td class="mdescRight">GMAC signal: GRXDV on PC20 mux L. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC20L_GMAC_GRXDV</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC20L_GMAC_GRXDV</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a229488f377e575ee45b2e979d7b43524">PIN_PC20L_GMAC_GRXDV</a> &lt;&lt; 16) | MUX_PC20L_GMAC_GRXDV)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC20L_GMAC_GRXDV</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 20)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab38fbd555279a84084dd4411daf47ed0">PIN_PA15L_GMAC_GRXER</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(15)</td></tr>
<tr class="memdesc:ab38fbd555279a84084dd4411daf47ed0"><td class="mdescLeft">&#160;</td><td class="mdescRight">GMAC signal: GRXER on PA15 mux L. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA15L_GMAC_GRXER</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA15L_GMAC_GRXER</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ab38fbd555279a84084dd4411daf47ed0">PIN_PA15L_GMAC_GRXER</a> &lt;&lt; 16) | MUX_PA15L_GMAC_GRXER)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA15L_GMAC_GRXER</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 15)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a19e3ba66a99a24b2b4eeb4a0c661af0c">PIN_PA18L_GMAC_GTX0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(18)</td></tr>
<tr class="memdesc:a19e3ba66a99a24b2b4eeb4a0c661af0c"><td class="mdescLeft">&#160;</td><td class="mdescRight">GMAC signal: GTX0 on PA18 mux L. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA18L_GMAC_GTX0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA18L_GMAC_GTX0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a19e3ba66a99a24b2b4eeb4a0c661af0c">PIN_PA18L_GMAC_GTX0</a> &lt;&lt; 16) | MUX_PA18L_GMAC_GTX0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA18L_GMAC_GTX0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 18)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa379452684952e8b6e874ec782be44a4">PIN_PA19L_GMAC_GTX1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(19)</td></tr>
<tr class="memdesc:aa379452684952e8b6e874ec782be44a4"><td class="mdescLeft">&#160;</td><td class="mdescRight">GMAC signal: GTX1 on PA19 mux L. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA19L_GMAC_GTX1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA19L_GMAC_GTX1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aa379452684952e8b6e874ec782be44a4">PIN_PA19L_GMAC_GTX1</a> &lt;&lt; 16) | MUX_PA19L_GMAC_GTX1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA19L_GMAC_GTX1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 19)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab10a78f9bbdcaf1d4e89c89b78b5cc2c">PIN_PC16L_GMAC_GTX2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(80)</td></tr>
<tr class="memdesc:ab10a78f9bbdcaf1d4e89c89b78b5cc2c"><td class="mdescLeft">&#160;</td><td class="mdescRight">GMAC signal: GTX2 on PC16 mux L. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC16L_GMAC_GTX2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC16L_GMAC_GTX2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ab10a78f9bbdcaf1d4e89c89b78b5cc2c">PIN_PC16L_GMAC_GTX2</a> &lt;&lt; 16) | MUX_PC16L_GMAC_GTX2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC16L_GMAC_GTX2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 16)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a039cbb68078932607f57e5b0e82c1125">PIN_PC17L_GMAC_GTX3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(81)</td></tr>
<tr class="memdesc:a039cbb68078932607f57e5b0e82c1125"><td class="mdescLeft">&#160;</td><td class="mdescRight">GMAC signal: GTX3 on PC17 mux L. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC17L_GMAC_GTX3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC17L_GMAC_GTX3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a039cbb68078932607f57e5b0e82c1125">PIN_PC17L_GMAC_GTX3</a> &lt;&lt; 16) | MUX_PC17L_GMAC_GTX3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC17L_GMAC_GTX3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 17)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aab984c5af62b27d4dc46d7206a53804c">PIN_PA14L_GMAC_GTXCK</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
<tr class="memdesc:aab984c5af62b27d4dc46d7206a53804c"><td class="mdescLeft">&#160;</td><td class="mdescRight">GMAC signal: GTXCK on PA14 mux L. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA14L_GMAC_GTXCK</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA14L_GMAC_GTXCK</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aab984c5af62b27d4dc46d7206a53804c">PIN_PA14L_GMAC_GTXCK</a> &lt;&lt; 16) | MUX_PA14L_GMAC_GTXCK)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA14L_GMAC_GTXCK</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a91ca86d30c57c664d734ca145699e43f">PIN_PA17L_GMAC_GTXEN</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(17)</td></tr>
<tr class="memdesc:a91ca86d30c57c664d734ca145699e43f"><td class="mdescLeft">&#160;</td><td class="mdescRight">GMAC signal: GTXEN on PA17 mux L. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA17L_GMAC_GTXEN</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA17L_GMAC_GTXEN</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a91ca86d30c57c664d734ca145699e43f">PIN_PA17L_GMAC_GTXEN</a> &lt;&lt; 16) | MUX_PA17L_GMAC_GTXEN)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA17L_GMAC_GTXEN</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 17)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad41704e2ca1173d39afcb2e451ace3aa">PIN_PC19L_GMAC_GTXER</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(83)</td></tr>
<tr class="memdesc:ad41704e2ca1173d39afcb2e451ace3aa"><td class="mdescLeft">&#160;</td><td class="mdescRight">GMAC signal: GTXER on PC19 mux L. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC19L_GMAC_GTXER</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC19L_GMAC_GTXER</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ad41704e2ca1173d39afcb2e451ace3aa">PIN_PC19L_GMAC_GTXER</a> &lt;&lt; 16) | MUX_PC19L_GMAC_GTXER)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC19L_GMAC_GTXER</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 19)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5d94ca9b5e5a77c255a7b431e27670e5">PIN_PA14F_TCC2_WO0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
<tr class="memdesc:a5d94ca9b5e5a77c255a7b431e27670e5"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC2 signal: WO0 on PA14 mux F. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB13F_TCC3_WO1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ab75b553315a9ef7d5fd966c9d3ad1ea4">PIN_PB13F_TCC3_WO1</a> &lt;&lt; 16) | MUX_PB13F_TCC3_WO1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB13F_TCC3_WO1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ace6df54793a54cda67265be42b6add36">PIN_PB17F_TCC3_WO1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(49)</td></tr>
<tr class="memdesc:ace6df54793a54cda67265be42b6add36"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC3 signal: WO1 on PB17 mux F. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB17F_TCC3_WO1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB17F_TCC3_WO1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ace6df54793a54cda67265be42b6add36">PIN_PB17F_TCC3_WO1</a> &lt;&lt; 16) | MUX_PB17F_TCC3_WO1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB17F_TCC3_WO1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 17)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa61338ee45dceb3ba53886cce92e37a2">PIN_PA22E_TC4_WO0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(22)</td></tr>
<tr class="memdesc:aa61338ee45dceb3ba53886cce92e37a2"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC4 signal: WO0 on PA22 mux E. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA22E_TC4_WO0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aa61338ee45dceb3ba53886cce92e37a2">PIN_PA22E_TC4_WO0</a> &lt;&lt; 16) | MUX_PA22E_TC4_WO0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA22E_TC4_WO0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 22)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5653360fe2e5042da32f829936f8daaf">PIN_PB08E_TC4_WO0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(40)</td></tr>
<tr class="memdesc:a5653360fe2e5042da32f829936f8daaf"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC4 signal: WO0 on PB08 mux E. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB08E_TC4_WO0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB08E_TC4_WO0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a5653360fe2e5042da32f829936f8daaf">PIN_PB08E_TC4_WO0</a> &lt;&lt; 16) | MUX_PB08E_TC4_WO0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB08E_TC4_WO0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab6b809fa2a40673cd40cbbc7bd930a9d">PIN_PB12E_TC4_WO0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(44)</td></tr>
<tr class="memdesc:ab6b809fa2a40673cd40cbbc7bd930a9d"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC4 signal: WO0 on PB12 mux E. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB12E_TC4_WO0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB12E_TC4_WO0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ab6b809fa2a40673cd40cbbc7bd930a9d">PIN_PB12E_TC4_WO0</a> &lt;&lt; 16) | MUX_PB12E_TC4_WO0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB12E_TC4_WO0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab3b4ecc178d179b8b043c03dcb378e2b">PIN_PA23E_TC4_WO1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(23)</td></tr>
<tr class="memdesc:ab3b4ecc178d179b8b043c03dcb378e2b"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC4 signal: WO1 on PA23 mux E. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA23E_TC4_WO1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA23E_TC4_WO1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ab3b4ecc178d179b8b043c03dcb378e2b">PIN_PA23E_TC4_WO1</a> &lt;&lt; 16) | MUX_PA23E_TC4_WO1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac40d76856e1b03f2b9a73d245a502d9e">PIN_PB09E_TC4_WO1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(41)</td></tr>
<tr class="memdesc:ac40d76856e1b03f2b9a73d245a502d9e"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC4 signal: WO1 on PB09 mux E. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB09E_TC4_WO1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ac40d76856e1b03f2b9a73d245a502d9e">PIN_PB09E_TC4_WO1</a> &lt;&lt; 16) | MUX_PB09E_TC4_WO1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB09E_TC4_WO1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab17c34e5d668dc3db35fdfe4ec67c91d">PIN_PB13E_TC4_WO1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(45)</td></tr>
<tr class="memdesc:ab17c34e5d668dc3db35fdfe4ec67c91d"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC4 signal: WO1 on PB13 mux E. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB13E_TC4_WO1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ab17c34e5d668dc3db35fdfe4ec67c91d">PIN_PB13E_TC4_WO1</a> &lt;&lt; 16) | MUX_PB13E_TC4_WO1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB13E_TC4_WO1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7fd3dfb1f952256b6f8b84dd50170639">PIN_PA24E_TC5_WO0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(24)</td></tr>
<tr class="memdesc:a7fd3dfb1f952256b6f8b84dd50170639"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC5 signal: WO0 on PA24 mux E. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA24E_TC5_WO0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a7fd3dfb1f952256b6f8b84dd50170639">PIN_PA24E_TC5_WO0</a> &lt;&lt; 16) | MUX_PA24E_TC5_WO0)</td></tr>
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<tr class="memdesc:a507c6e9336a7c1ce63a4fa939dbd6bb4"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC5 signal: WO0 on PB10 mux E. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB10E_TC5_WO0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a507c6e9336a7c1ce63a4fa939dbd6bb4">PIN_PB10E_TC5_WO0</a> &lt;&lt; 16) | MUX_PB10E_TC5_WO0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB10E_TC5_WO0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 10)</td></tr>
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<tr class="memdesc:a24eb8bf26a40daa34a83d0f7e413ab99"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC5 signal: WO0 on PB14 mux E. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB14E_TC5_WO0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a24eb8bf26a40daa34a83d0f7e413ab99">PIN_PB14E_TC5_WO0</a> &lt;&lt; 16) | MUX_PB14E_TC5_WO0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB14E_TC5_WO0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab22c202ad376d93dd79a9913ee9fcf90">PIN_PA25E_TC5_WO1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(25)</td></tr>
<tr class="memdesc:ab22c202ad376d93dd79a9913ee9fcf90"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC5 signal: WO1 on PA25 mux E. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA25E_TC5_WO1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ab22c202ad376d93dd79a9913ee9fcf90">PIN_PA25E_TC5_WO1</a> &lt;&lt; 16) | MUX_PA25E_TC5_WO1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA25E_TC5_WO1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 25)</td></tr>
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<tr class="memdesc:a72371b5ea4bd771cb2b96e82f412e65d"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC5 signal: WO1 on PB11 mux E. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB11E_TC5_WO1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a72371b5ea4bd771cb2b96e82f412e65d">PIN_PB11E_TC5_WO1</a> &lt;&lt; 16) | MUX_PB11E_TC5_WO1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB11E_TC5_WO1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 11)</td></tr>
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<tr class="memdesc:ad46dc3d5731ff0d9169795cf7e83b68a"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC5 signal: WO1 on PB15 mux E. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB15E_TC5_WO1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB15E_TC5_WO1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ad46dc3d5731ff0d9169795cf7e83b68a">PIN_PB15E_TC5_WO1</a> &lt;&lt; 16) | MUX_PB15E_TC5_WO1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac7fb39e38573e6a4b0ebeba213408fa7">PIN_PB18G_PDEC_QDI0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(50)</td></tr>
<tr class="memdesc:ac7fb39e38573e6a4b0ebeba213408fa7"><td class="mdescLeft">&#160;</td><td class="mdescRight">PDEC signal: QDI0 on PB18 mux G. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB18G_PDEC_QDI0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ac7fb39e38573e6a4b0ebeba213408fa7">PIN_PB18G_PDEC_QDI0</a> &lt;&lt; 16) | MUX_PB18G_PDEC_QDI0)</td></tr>
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<tr class="memdesc:a9e5853b7e4c261377514699da2408225"><td class="mdescLeft">&#160;</td><td class="mdescRight">PDEC signal: QDI0 on PB23 mux G. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB23G_PDEC_QDI0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a9e5853b7e4c261377514699da2408225">PIN_PB23G_PDEC_QDI0</a> &lt;&lt; 16) | MUX_PB23G_PDEC_QDI0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a529504f16c061580273255e241dec40f">PIN_PC16G_PDEC_QDI0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(80)</td></tr>
<tr class="memdesc:a529504f16c061580273255e241dec40f"><td class="mdescLeft">&#160;</td><td class="mdescRight">PDEC signal: QDI0 on PC16 mux G. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC16G_PDEC_QDI0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a529504f16c061580273255e241dec40f">PIN_PC16G_PDEC_QDI0</a> &lt;&lt; 16) | MUX_PC16G_PDEC_QDI0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC16G_PDEC_QDI0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 16)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4ab63287710ede1aa24534d7233705c8">PIN_PA24G_PDEC_QDI0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(24)</td></tr>
<tr class="memdesc:a4ab63287710ede1aa24534d7233705c8"><td class="mdescLeft">&#160;</td><td class="mdescRight">PDEC signal: QDI0 on PA24 mux G. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA24G_PDEC_QDI0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA24G_PDEC_QDI0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a4ab63287710ede1aa24534d7233705c8">PIN_PA24G_PDEC_QDI0</a> &lt;&lt; 16) | MUX_PA24G_PDEC_QDI0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA24G_PDEC_QDI0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 24)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7d280f8e7d1efece39af6e3871e96fd5">PIN_PB19G_PDEC_QDI1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(51)</td></tr>
<tr class="memdesc:a7d280f8e7d1efece39af6e3871e96fd5"><td class="mdescLeft">&#160;</td><td class="mdescRight">PDEC signal: QDI1 on PB19 mux G. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB19G_PDEC_QDI1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB19G_PDEC_QDI1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a7d280f8e7d1efece39af6e3871e96fd5">PIN_PB19G_PDEC_QDI1</a> &lt;&lt; 16) | MUX_PB19G_PDEC_QDI1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB19G_PDEC_QDI1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 19)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a492a10d4f50b4521d2bb265177b44576">PIN_PB24G_PDEC_QDI1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(56)</td></tr>
<tr class="memdesc:a492a10d4f50b4521d2bb265177b44576"><td class="mdescLeft">&#160;</td><td class="mdescRight">PDEC signal: QDI1 on PB24 mux G. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB24G_PDEC_QDI1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB24G_PDEC_QDI1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a492a10d4f50b4521d2bb265177b44576">PIN_PB24G_PDEC_QDI1</a> &lt;&lt; 16) | MUX_PB24G_PDEC_QDI1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB24G_PDEC_QDI1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 24)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa139d121508ad7acd366f4bd04da16c8">PIN_PC17G_PDEC_QDI1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(81)</td></tr>
<tr class="memdesc:aa139d121508ad7acd366f4bd04da16c8"><td class="mdescLeft">&#160;</td><td class="mdescRight">PDEC signal: QDI1 on PC17 mux G. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC17G_PDEC_QDI1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC17G_PDEC_QDI1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aa139d121508ad7acd366f4bd04da16c8">PIN_PC17G_PDEC_QDI1</a> &lt;&lt; 16) | MUX_PC17G_PDEC_QDI1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC17G_PDEC_QDI1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 17)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af9c611769bfd63f638c8471a6f3a66d8">PIN_PA25G_PDEC_QDI1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(25)</td></tr>
<tr class="memdesc:af9c611769bfd63f638c8471a6f3a66d8"><td class="mdescLeft">&#160;</td><td class="mdescRight">PDEC signal: QDI1 on PA25 mux G. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA25G_PDEC_QDI1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA25G_PDEC_QDI1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#af9c611769bfd63f638c8471a6f3a66d8">PIN_PA25G_PDEC_QDI1</a> &lt;&lt; 16) | MUX_PA25G_PDEC_QDI1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA25G_PDEC_QDI1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 25)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a858c1f15237c51c39dc8abcefef51f69">PIN_PB20G_PDEC_QDI2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(52)</td></tr>
<tr class="memdesc:a858c1f15237c51c39dc8abcefef51f69"><td class="mdescLeft">&#160;</td><td class="mdescRight">PDEC signal: QDI2 on PB20 mux G. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB20G_PDEC_QDI2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB20G_PDEC_QDI2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a858c1f15237c51c39dc8abcefef51f69">PIN_PB20G_PDEC_QDI2</a> &lt;&lt; 16) | MUX_PB20G_PDEC_QDI2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB20G_PDEC_QDI2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 20)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5689f57f16a33f29e98f56ec349b63fb">PIN_PB25G_PDEC_QDI2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(57)</td></tr>
<tr class="memdesc:a5689f57f16a33f29e98f56ec349b63fb"><td class="mdescLeft">&#160;</td><td class="mdescRight">PDEC signal: QDI2 on PB25 mux G. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB25G_PDEC_QDI2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a5689f57f16a33f29e98f56ec349b63fb">PIN_PB25G_PDEC_QDI2</a> &lt;&lt; 16) | MUX_PB25G_PDEC_QDI2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB25G_PDEC_QDI2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 25)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3c8d21b2d16e98d8be25c7386b3736a8">PIN_PC18G_PDEC_QDI2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(82)</td></tr>
<tr class="memdesc:a3c8d21b2d16e98d8be25c7386b3736a8"><td class="mdescLeft">&#160;</td><td class="mdescRight">PDEC signal: QDI2 on PC18 mux G. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC18G_PDEC_QDI2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a3c8d21b2d16e98d8be25c7386b3736a8">PIN_PC18G_PDEC_QDI2</a> &lt;&lt; 16) | MUX_PC18G_PDEC_QDI2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC18G_PDEC_QDI2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 18)</td></tr>
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<tr class="memitem:a7abeb51ca7fbfe8ec88df7a4f4d2933f"><td class="memItemLeft" align="right" valign="top"><a id="a7abeb51ca7fbfe8ec88df7a4f4d2933f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7abeb51ca7fbfe8ec88df7a4f4d2933f">PIN_PB22G_PDEC_QDI2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(54)</td></tr>
<tr class="memdesc:a7abeb51ca7fbfe8ec88df7a4f4d2933f"><td class="mdescLeft">&#160;</td><td class="mdescRight">PDEC signal: QDI2 on PB22 mux G. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB22G_PDEC_QDI2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB22G_PDEC_QDI2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a7abeb51ca7fbfe8ec88df7a4f4d2933f">PIN_PB22G_PDEC_QDI2</a> &lt;&lt; 16) | MUX_PB22G_PDEC_QDI2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB22G_PDEC_QDI2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 22)</td></tr>
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<tr class="memitem:a181e0a4f47f8e8f3b1d79d02176dd26c"><td class="memItemLeft" align="right" valign="top"><a id="a181e0a4f47f8e8f3b1d79d02176dd26c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a181e0a4f47f8e8f3b1d79d02176dd26c">PIN_PA04B_AC_AIN0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
<tr class="memdesc:a181e0a4f47f8e8f3b1d79d02176dd26c"><td class="mdescLeft">&#160;</td><td class="mdescRight">AC signal: AIN0 on PA04 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA04B_AC_AIN0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA04B_AC_AIN0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a181e0a4f47f8e8f3b1d79d02176dd26c">PIN_PA04B_AC_AIN0</a> &lt;&lt; 16) | MUX_PA04B_AC_AIN0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA04B_AC_AIN0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a371630f713d57b3f41f708b1320358c9">PIN_PA05B_AC_AIN1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
<tr class="memdesc:a371630f713d57b3f41f708b1320358c9"><td class="mdescLeft">&#160;</td><td class="mdescRight">AC signal: AIN1 on PA05 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA05B_AC_AIN1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA05B_AC_AIN1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a371630f713d57b3f41f708b1320358c9">PIN_PA05B_AC_AIN1</a> &lt;&lt; 16) | MUX_PA05B_AC_AIN1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA05B_AC_AIN1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 5)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a323ca7764bd09f550c2564a3913d50e0">PIN_PA06B_AC_AIN2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
<tr class="memdesc:a323ca7764bd09f550c2564a3913d50e0"><td class="mdescLeft">&#160;</td><td class="mdescRight">AC signal: AIN2 on PA06 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA06B_AC_AIN2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA06B_AC_AIN2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a323ca7764bd09f550c2564a3913d50e0">PIN_PA06B_AC_AIN2</a> &lt;&lt; 16) | MUX_PA06B_AC_AIN2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA06B_AC_AIN2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 6)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aac4b0dec1c1c7442f3027aad45560115">PIN_PA07B_AC_AIN3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
<tr class="memdesc:aac4b0dec1c1c7442f3027aad45560115"><td class="mdescLeft">&#160;</td><td class="mdescRight">AC signal: AIN3 on PA07 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA07B_AC_AIN3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA07B_AC_AIN3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aac4b0dec1c1c7442f3027aad45560115">PIN_PA07B_AC_AIN3</a> &lt;&lt; 16) | MUX_PA07B_AC_AIN3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA07B_AC_AIN3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 7)</td></tr>
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<tr class="memitem:a14be1724e7f5ef5b9c94c94f3c8b4fd0"><td class="memItemLeft" align="right" valign="top"><a id="a14be1724e7f5ef5b9c94c94f3c8b4fd0"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a14be1724e7f5ef5b9c94c94f3c8b4fd0">PIN_PA12M_AC_CMP0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
<tr class="memdesc:a14be1724e7f5ef5b9c94c94f3c8b4fd0"><td class="mdescLeft">&#160;</td><td class="mdescRight">AC signal: CMP0 on PA12 mux M. <br /></td></tr>
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<tr class="memitem:acee7247ab010a5856e3cd8b1602ddeb7"><td class="memItemLeft" align="right" valign="top"><a id="acee7247ab010a5856e3cd8b1602ddeb7"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA12M_AC_CMP0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA12M_AC_CMP0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a14be1724e7f5ef5b9c94c94f3c8b4fd0">PIN_PA12M_AC_CMP0</a> &lt;&lt; 16) | MUX_PA12M_AC_CMP0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA12M_AC_CMP0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 12)</td></tr>
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<tr class="memitem:a818e97d15fffe182de3dfea2734b2b0f"><td class="memItemLeft" align="right" valign="top"><a id="a818e97d15fffe182de3dfea2734b2b0f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a818e97d15fffe182de3dfea2734b2b0f">PIN_PA18M_AC_CMP0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(18)</td></tr>
<tr class="memdesc:a818e97d15fffe182de3dfea2734b2b0f"><td class="mdescLeft">&#160;</td><td class="mdescRight">AC signal: CMP0 on PA18 mux M. <br /></td></tr>
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<tr class="memitem:a86119d9c5aa593aeed40cf5741ae0b26"><td class="memItemLeft" align="right" valign="top"><a id="a86119d9c5aa593aeed40cf5741ae0b26"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA18M_AC_CMP0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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<tr class="memitem:a22e9dab18d78a691044d475144467ebc"><td class="memItemLeft" align="right" valign="top"><a id="a22e9dab18d78a691044d475144467ebc"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA18M_AC_CMP0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a818e97d15fffe182de3dfea2734b2b0f">PIN_PA18M_AC_CMP0</a> &lt;&lt; 16) | MUX_PA18M_AC_CMP0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA18M_AC_CMP0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 18)</td></tr>
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<tr class="memitem:ac70e3e86e7648bfffd389730ef2d0245"><td class="memItemLeft" align="right" valign="top"><a id="ac70e3e86e7648bfffd389730ef2d0245"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac70e3e86e7648bfffd389730ef2d0245">PIN_PB24M_AC_CMP0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(56)</td></tr>
<tr class="memdesc:ac70e3e86e7648bfffd389730ef2d0245"><td class="mdescLeft">&#160;</td><td class="mdescRight">AC signal: CMP0 on PB24 mux M. <br /></td></tr>
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<tr class="memitem:aab1f62904b93ce23bbfe7b083c0d835f"><td class="memItemLeft" align="right" valign="top"><a id="aab1f62904b93ce23bbfe7b083c0d835f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB24M_AC_CMP0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB24M_AC_CMP0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ac70e3e86e7648bfffd389730ef2d0245">PIN_PB24M_AC_CMP0</a> &lt;&lt; 16) | MUX_PB24M_AC_CMP0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB24M_AC_CMP0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 24)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad505695604c6c01ae2a05a53226d943d">PIN_PA13M_AC_CMP1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
<tr class="memdesc:ad505695604c6c01ae2a05a53226d943d"><td class="mdescLeft">&#160;</td><td class="mdescRight">AC signal: CMP1 on PA13 mux M. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA13M_AC_CMP1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA13M_AC_CMP1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ad505695604c6c01ae2a05a53226d943d">PIN_PA13M_AC_CMP1</a> &lt;&lt; 16) | MUX_PA13M_AC_CMP1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA13M_AC_CMP1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab51a18fff0ed4e12fcc1d3e8c4480a72">PIN_PA19M_AC_CMP1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(19)</td></tr>
<tr class="memdesc:ab51a18fff0ed4e12fcc1d3e8c4480a72"><td class="mdescLeft">&#160;</td><td class="mdescRight">AC signal: CMP1 on PA19 mux M. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA19M_AC_CMP1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA19M_AC_CMP1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ab51a18fff0ed4e12fcc1d3e8c4480a72">PIN_PA19M_AC_CMP1</a> &lt;&lt; 16) | MUX_PA19M_AC_CMP1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA19M_AC_CMP1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 19)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8a8370fd0a4d204daa83434d1fa58b4e">PIN_PB25M_AC_CMP1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(57)</td></tr>
<tr class="memdesc:a8a8370fd0a4d204daa83434d1fa58b4e"><td class="mdescLeft">&#160;</td><td class="mdescRight">AC signal: CMP1 on PB25 mux M. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB25M_AC_CMP1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB25M_AC_CMP1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a8a8370fd0a4d204daa83434d1fa58b4e">PIN_PB25M_AC_CMP1</a> &lt;&lt; 16) | MUX_PB25M_AC_CMP1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB25M_AC_CMP1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 25)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a31aec5c24c374327fac16080b33f8df8">PIN_PB11H_QSPI_CS</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(43)</td></tr>
<tr class="memdesc:a31aec5c24c374327fac16080b33f8df8"><td class="mdescLeft">&#160;</td><td class="mdescRight">QSPI signal: CS on PB11 mux H. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB11H_QSPI_CS</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB11H_QSPI_CS</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a31aec5c24c374327fac16080b33f8df8">PIN_PB11H_QSPI_CS</a> &lt;&lt; 16) | MUX_PB11H_QSPI_CS)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB11H_QSPI_CS</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1f56c929190a5353af478c2809e83a34">PIN_PA08H_QSPI_DATA0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
<tr class="memdesc:a1f56c929190a5353af478c2809e83a34"><td class="mdescLeft">&#160;</td><td class="mdescRight">QSPI signal: DATA0 on PA08 mux H. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA08H_QSPI_DATA0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA08H_QSPI_DATA0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a1f56c929190a5353af478c2809e83a34">PIN_PA08H_QSPI_DATA0</a> &lt;&lt; 16) | MUX_PA08H_QSPI_DATA0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA08H_QSPI_DATA0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3e393e86e8f99532da9af298966efb53">PIN_PA09H_QSPI_DATA1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
<tr class="memdesc:a3e393e86e8f99532da9af298966efb53"><td class="mdescLeft">&#160;</td><td class="mdescRight">QSPI signal: DATA1 on PA09 mux H. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA09H_QSPI_DATA1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA09H_QSPI_DATA1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a3e393e86e8f99532da9af298966efb53">PIN_PA09H_QSPI_DATA1</a> &lt;&lt; 16) | MUX_PA09H_QSPI_DATA1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA09H_QSPI_DATA1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#add1fac6b593768731ee682263f4eeb03">PIN_PA10H_QSPI_DATA2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
<tr class="memdesc:add1fac6b593768731ee682263f4eeb03"><td class="mdescLeft">&#160;</td><td class="mdescRight">QSPI signal: DATA2 on PA10 mux H. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA10H_QSPI_DATA2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA10H_QSPI_DATA2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#add1fac6b593768731ee682263f4eeb03">PIN_PA10H_QSPI_DATA2</a> &lt;&lt; 16) | MUX_PA10H_QSPI_DATA2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA10H_QSPI_DATA2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa3da6ee8cf028b61b4987e27609f971c">PIN_PA11H_QSPI_DATA3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
<tr class="memdesc:aa3da6ee8cf028b61b4987e27609f971c"><td class="mdescLeft">&#160;</td><td class="mdescRight">QSPI signal: DATA3 on PA11 mux H. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA11H_QSPI_DATA3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA11H_QSPI_DATA3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aa3da6ee8cf028b61b4987e27609f971c">PIN_PA11H_QSPI_DATA3</a> &lt;&lt; 16) | MUX_PA11H_QSPI_DATA3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA11H_QSPI_DATA3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aede71f5b54f159a1effe424366833e17">PIN_PB10H_QSPI_SCK</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(42)</td></tr>
<tr class="memdesc:aede71f5b54f159a1effe424366833e17"><td class="mdescLeft">&#160;</td><td class="mdescRight">QSPI signal: SCK on PB10 mux H. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB10H_QSPI_SCK</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB10H_QSPI_SCK</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aede71f5b54f159a1effe424366833e17">PIN_PB10H_QSPI_SCK</a> &lt;&lt; 16) | MUX_PB10H_QSPI_SCK)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB10H_QSPI_SCK</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a42187440e16ef275ae5cd6c2357ad694">PIN_PA04N_CCL_IN0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
<tr class="memdesc:a42187440e16ef275ae5cd6c2357ad694"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: IN0 on PA04 mux N. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA04N_CCL_IN0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA04N_CCL_IN0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a42187440e16ef275ae5cd6c2357ad694">PIN_PA04N_CCL_IN0</a> &lt;&lt; 16) | MUX_PA04N_CCL_IN0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA04N_CCL_IN0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad912a8ab729ff9e3592013be39a5a8d4">PIN_PA16N_CCL_IN0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(16)</td></tr>
<tr class="memdesc:ad912a8ab729ff9e3592013be39a5a8d4"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: IN0 on PA16 mux N. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA16N_CCL_IN0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA16N_CCL_IN0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ad912a8ab729ff9e3592013be39a5a8d4">PIN_PA16N_CCL_IN0</a> &lt;&lt; 16) | MUX_PA16N_CCL_IN0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA16N_CCL_IN0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 16)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa02cfb0c81f3c0f99f3ac828ed8aea71">PIN_PB22N_CCL_IN0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(54)</td></tr>
<tr class="memdesc:aa02cfb0c81f3c0f99f3ac828ed8aea71"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: IN0 on PB22 mux N. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB22N_CCL_IN0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB22N_CCL_IN0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aa02cfb0c81f3c0f99f3ac828ed8aea71">PIN_PB22N_CCL_IN0</a> &lt;&lt; 16) | MUX_PB22N_CCL_IN0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB22N_CCL_IN0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 22)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa2cf0ddb8d47e79b6405245a359dcd51">PIN_PA05N_CCL_IN1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
<tr class="memdesc:aa2cf0ddb8d47e79b6405245a359dcd51"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: IN1 on PA05 mux N. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA05N_CCL_IN1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA05N_CCL_IN1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aa2cf0ddb8d47e79b6405245a359dcd51">PIN_PA05N_CCL_IN1</a> &lt;&lt; 16) | MUX_PA05N_CCL_IN1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA05N_CCL_IN1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 5)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a26704bd685973b7b55bcd94a1b648b28">PIN_PA17N_CCL_IN1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(17)</td></tr>
<tr class="memdesc:a26704bd685973b7b55bcd94a1b648b28"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: IN1 on PA17 mux N. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA17N_CCL_IN1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA17N_CCL_IN1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a26704bd685973b7b55bcd94a1b648b28">PIN_PA17N_CCL_IN1</a> &lt;&lt; 16) | MUX_PA17N_CCL_IN1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA17N_CCL_IN1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 17)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0bd45176e0dce96a567d47fd10740ffd">PIN_PB00N_CCL_IN1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(32)</td></tr>
<tr class="memdesc:a0bd45176e0dce96a567d47fd10740ffd"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: IN1 on PB00 mux N. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB00N_CCL_IN1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB00N_CCL_IN1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a0bd45176e0dce96a567d47fd10740ffd">PIN_PB00N_CCL_IN1</a> &lt;&lt; 16) | MUX_PB00N_CCL_IN1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB00N_CCL_IN1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a30783890bdbe4487b6ec911d5b25c0f7">PIN_PA06N_CCL_IN2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
<tr class="memdesc:a30783890bdbe4487b6ec911d5b25c0f7"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: IN2 on PA06 mux N. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA06N_CCL_IN2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA06N_CCL_IN2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a30783890bdbe4487b6ec911d5b25c0f7">PIN_PA06N_CCL_IN2</a> &lt;&lt; 16) | MUX_PA06N_CCL_IN2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA06N_CCL_IN2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 6)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a523b999dbb4c541f10d84e41f41f9fec">PIN_PA18N_CCL_IN2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(18)</td></tr>
<tr class="memdesc:a523b999dbb4c541f10d84e41f41f9fec"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: IN2 on PA18 mux N. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA18N_CCL_IN2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA18N_CCL_IN2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a523b999dbb4c541f10d84e41f41f9fec">PIN_PA18N_CCL_IN2</a> &lt;&lt; 16) | MUX_PA18N_CCL_IN2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA18N_CCL_IN2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 18)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a75820aa12407e7562b27165c0f019f68">PIN_PB01N_CCL_IN2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(33)</td></tr>
<tr class="memdesc:a75820aa12407e7562b27165c0f019f68"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: IN2 on PB01 mux N. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB01N_CCL_IN2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB01N_CCL_IN2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a75820aa12407e7562b27165c0f019f68">PIN_PB01N_CCL_IN2</a> &lt;&lt; 16) | MUX_PB01N_CCL_IN2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB01N_CCL_IN2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab8abb6052c59b4f4a406bed9cfc061a6">PIN_PA08N_CCL_IN3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
<tr class="memdesc:ab8abb6052c59b4f4a406bed9cfc061a6"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: IN3 on PA08 mux N. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA08N_CCL_IN3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA08N_CCL_IN3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ab8abb6052c59b4f4a406bed9cfc061a6">PIN_PA08N_CCL_IN3</a> &lt;&lt; 16) | MUX_PA08N_CCL_IN3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA08N_CCL_IN3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a209a21781acd42a4266a726971ce4715">PIN_PA30N_CCL_IN3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(30)</td></tr>
<tr class="memdesc:a209a21781acd42a4266a726971ce4715"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: IN3 on PA30 mux N. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA30N_CCL_IN3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA30N_CCL_IN3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a209a21781acd42a4266a726971ce4715">PIN_PA30N_CCL_IN3</a> &lt;&lt; 16) | MUX_PA30N_CCL_IN3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA30N_CCL_IN3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 30)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0fdd8f70cb065100975d214e1e5297f4">PIN_PA09N_CCL_IN4</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
<tr class="memdesc:a0fdd8f70cb065100975d214e1e5297f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: IN4 on PA09 mux N. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA09N_CCL_IN4</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA09N_CCL_IN4</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a0fdd8f70cb065100975d214e1e5297f4">PIN_PA09N_CCL_IN4</a> &lt;&lt; 16) | MUX_PA09N_CCL_IN4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA09N_CCL_IN4</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4671f73b47879a0ee57c7a7185f80965">PIN_PC27N_CCL_IN4</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(91)</td></tr>
<tr class="memdesc:a4671f73b47879a0ee57c7a7185f80965"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: IN4 on PC27 mux N. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC27N_CCL_IN4</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC27N_CCL_IN4</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a4671f73b47879a0ee57c7a7185f80965">PIN_PC27N_CCL_IN4</a> &lt;&lt; 16) | MUX_PC27N_CCL_IN4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC27N_CCL_IN4</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 27)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab5ab8798d19eb2220273f493b8a48832">PIN_PA10N_CCL_IN5</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
<tr class="memdesc:ab5ab8798d19eb2220273f493b8a48832"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: IN5 on PA10 mux N. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA10N_CCL_IN5</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA10N_CCL_IN5</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ab5ab8798d19eb2220273f493b8a48832">PIN_PA10N_CCL_IN5</a> &lt;&lt; 16) | MUX_PA10N_CCL_IN5)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA10N_CCL_IN5</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7f1fc902563874dc2cfb0d987299767f">PIN_PC28N_CCL_IN5</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(92)</td></tr>
<tr class="memdesc:a7f1fc902563874dc2cfb0d987299767f"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: IN5 on PC28 mux N. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC28N_CCL_IN5</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC28N_CCL_IN5</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a7f1fc902563874dc2cfb0d987299767f">PIN_PC28N_CCL_IN5</a> &lt;&lt; 16) | MUX_PC28N_CCL_IN5)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC28N_CCL_IN5</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 28)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8b830511de49d9d970838acd37a2c813">PIN_PA22N_CCL_IN6</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(22)</td></tr>
<tr class="memdesc:a8b830511de49d9d970838acd37a2c813"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: IN6 on PA22 mux N. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA22N_CCL_IN6</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA22N_CCL_IN6</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a8b830511de49d9d970838acd37a2c813">PIN_PA22N_CCL_IN6</a> &lt;&lt; 16) | MUX_PA22N_CCL_IN6)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA22N_CCL_IN6</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 22)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a783d8f4923536ff311297369b3e632f4">PIN_PB06N_CCL_IN6</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(38)</td></tr>
<tr class="memdesc:a783d8f4923536ff311297369b3e632f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: IN6 on PB06 mux N. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB06N_CCL_IN6</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB06N_CCL_IN6</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a783d8f4923536ff311297369b3e632f4">PIN_PB06N_CCL_IN6</a> &lt;&lt; 16) | MUX_PB06N_CCL_IN6)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB06N_CCL_IN6</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 6)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4b6446e2cefb7c5e027e0a138f2c56af">PIN_PA23N_CCL_IN7</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(23)</td></tr>
<tr class="memdesc:a4b6446e2cefb7c5e027e0a138f2c56af"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: IN7 on PA23 mux N. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA23N_CCL_IN7</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA23N_CCL_IN7</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a4b6446e2cefb7c5e027e0a138f2c56af">PIN_PA23N_CCL_IN7</a> &lt;&lt; 16) | MUX_PA23N_CCL_IN7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA23N_CCL_IN7</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 23)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#adbf0080b72bf2877f4b3297fe85836a7">PIN_PB07N_CCL_IN7</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(39)</td></tr>
<tr class="memdesc:adbf0080b72bf2877f4b3297fe85836a7"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: IN7 on PB07 mux N. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB07N_CCL_IN7</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB07N_CCL_IN7</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#adbf0080b72bf2877f4b3297fe85836a7">PIN_PB07N_CCL_IN7</a> &lt;&lt; 16) | MUX_PB07N_CCL_IN7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB07N_CCL_IN7</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa71902621f48e409ca79bfbae325d1ac">PIN_PA24N_CCL_IN8</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(24)</td></tr>
<tr class="memdesc:aa71902621f48e409ca79bfbae325d1ac"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: IN8 on PA24 mux N. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA24N_CCL_IN8</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA24N_CCL_IN8</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aa71902621f48e409ca79bfbae325d1ac">PIN_PA24N_CCL_IN8</a> &lt;&lt; 16) | MUX_PA24N_CCL_IN8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA24N_CCL_IN8</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 24)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a19c266acf1544e888fc19f9a73fe9dd4">PIN_PB08N_CCL_IN8</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(40)</td></tr>
<tr class="memdesc:a19c266acf1544e888fc19f9a73fe9dd4"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: IN8 on PB08 mux N. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB08N_CCL_IN8</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB08N_CCL_IN8</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a19c266acf1544e888fc19f9a73fe9dd4">PIN_PB08N_CCL_IN8</a> &lt;&lt; 16) | MUX_PB08N_CCL_IN8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB08N_CCL_IN8</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7d6cc99ec8997e28bd7bcb464adc4c99">PIN_PB14N_CCL_IN9</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(46)</td></tr>
<tr class="memdesc:a7d6cc99ec8997e28bd7bcb464adc4c99"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: IN9 on PB14 mux N. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB14N_CCL_IN9</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB14N_CCL_IN9</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a7d6cc99ec8997e28bd7bcb464adc4c99">PIN_PB14N_CCL_IN9</a> &lt;&lt; 16) | MUX_PB14N_CCL_IN9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB14N_CCL_IN9</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#acb93478906ebd008e9928c5b9b935e18">PIN_PC20N_CCL_IN9</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(84)</td></tr>
<tr class="memdesc:acb93478906ebd008e9928c5b9b935e18"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: IN9 on PC20 mux N. <br /></td></tr>
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<tr class="memitem:af6245db7b31c6d225c29547fa9b73c93"><td class="memItemLeft" align="right" valign="top"><a id="af6245db7b31c6d225c29547fa9b73c93"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC20N_CCL_IN9</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC20N_CCL_IN9</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#acb93478906ebd008e9928c5b9b935e18">PIN_PC20N_CCL_IN9</a> &lt;&lt; 16) | MUX_PC20N_CCL_IN9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC20N_CCL_IN9</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 20)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a700bb325b3d756f29e71da236d0bf601">PIN_PB15N_CCL_IN10</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(47)</td></tr>
<tr class="memdesc:a700bb325b3d756f29e71da236d0bf601"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: IN10 on PB15 mux N. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB15N_CCL_IN10</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB15N_CCL_IN10</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a700bb325b3d756f29e71da236d0bf601">PIN_PB15N_CCL_IN10</a> &lt;&lt; 16) | MUX_PB15N_CCL_IN10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB15N_CCL_IN10</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 15)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a932a786ccb928b78e5892ca25c985d5b">PIN_PC21N_CCL_IN10</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(85)</td></tr>
<tr class="memdesc:a932a786ccb928b78e5892ca25c985d5b"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: IN10 on PC21 mux N. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC21N_CCL_IN10</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC21N_CCL_IN10</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a932a786ccb928b78e5892ca25c985d5b">PIN_PC21N_CCL_IN10</a> &lt;&lt; 16) | MUX_PC21N_CCL_IN10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC21N_CCL_IN10</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 21)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a57e976436dcca255984160c11f790587">PIN_PB10N_CCL_IN11</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(42)</td></tr>
<tr class="memdesc:a57e976436dcca255984160c11f790587"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: IN11 on PB10 mux N. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB10N_CCL_IN11</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB10N_CCL_IN11</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a57e976436dcca255984160c11f790587">PIN_PB10N_CCL_IN11</a> &lt;&lt; 16) | MUX_PB10N_CCL_IN11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB10N_CCL_IN11</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#adffa67672dca7de317d99e378c565cc4">PIN_PB16N_CCL_IN11</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(48)</td></tr>
<tr class="memdesc:adffa67672dca7de317d99e378c565cc4"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: IN11 on PB16 mux N. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB16N_CCL_IN11</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB16N_CCL_IN11</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#adffa67672dca7de317d99e378c565cc4">PIN_PB16N_CCL_IN11</a> &lt;&lt; 16) | MUX_PB16N_CCL_IN11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB16N_CCL_IN11</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 16)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad20d3d27162954c40d356c868fc7d3f1">PIN_PA07N_CCL_OUT0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
<tr class="memdesc:ad20d3d27162954c40d356c868fc7d3f1"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: OUT0 on PA07 mux N. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA07N_CCL_OUT0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA07N_CCL_OUT0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ad20d3d27162954c40d356c868fc7d3f1">PIN_PA07N_CCL_OUT0</a> &lt;&lt; 16) | MUX_PA07N_CCL_OUT0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA07N_CCL_OUT0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aade9982add158f20548b2ce342abad88">PIN_PA19N_CCL_OUT0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(19)</td></tr>
<tr class="memdesc:aade9982add158f20548b2ce342abad88"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: OUT0 on PA19 mux N. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA19N_CCL_OUT0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA19N_CCL_OUT0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aade9982add158f20548b2ce342abad88">PIN_PA19N_CCL_OUT0</a> &lt;&lt; 16) | MUX_PA19N_CCL_OUT0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA19N_CCL_OUT0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 19)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab1ea2a0cc5b2d3742ca72b7d5abfcc26">PIN_PB02N_CCL_OUT0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(34)</td></tr>
<tr class="memdesc:ab1ea2a0cc5b2d3742ca72b7d5abfcc26"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: OUT0 on PB02 mux N. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB02N_CCL_OUT0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB02N_CCL_OUT0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ab1ea2a0cc5b2d3742ca72b7d5abfcc26">PIN_PB02N_CCL_OUT0</a> &lt;&lt; 16) | MUX_PB02N_CCL_OUT0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB02N_CCL_OUT0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1662f35acda7be5a74ee3bcf48e649be">PIN_PB23N_CCL_OUT0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(55)</td></tr>
<tr class="memdesc:a1662f35acda7be5a74ee3bcf48e649be"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: OUT0 on PB23 mux N. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB23N_CCL_OUT0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB23N_CCL_OUT0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a1662f35acda7be5a74ee3bcf48e649be">PIN_PB23N_CCL_OUT0</a> &lt;&lt; 16) | MUX_PB23N_CCL_OUT0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB23N_CCL_OUT0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 23)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a929038a135f9dc48781e4312cea2ae7f">PIN_PA11N_CCL_OUT1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
<tr class="memdesc:a929038a135f9dc48781e4312cea2ae7f"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: OUT1 on PA11 mux N. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA11N_CCL_OUT1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA11N_CCL_OUT1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a929038a135f9dc48781e4312cea2ae7f">PIN_PA11N_CCL_OUT1</a> &lt;&lt; 16) | MUX_PA11N_CCL_OUT1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA11N_CCL_OUT1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aeccac5005432ac3417358e9102fcc097">PIN_PA31N_CCL_OUT1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(31)</td></tr>
<tr class="memdesc:aeccac5005432ac3417358e9102fcc097"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: OUT1 on PA31 mux N. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA31N_CCL_OUT1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA31N_CCL_OUT1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aeccac5005432ac3417358e9102fcc097">PIN_PA31N_CCL_OUT1</a> &lt;&lt; 16) | MUX_PA31N_CCL_OUT1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA31N_CCL_OUT1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 31)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af660ed9079305934dd6792f8980c4445">PIN_PB11N_CCL_OUT1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(43)</td></tr>
<tr class="memdesc:af660ed9079305934dd6792f8980c4445"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: OUT1 on PB11 mux N. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB11N_CCL_OUT1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB11N_CCL_OUT1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#af660ed9079305934dd6792f8980c4445">PIN_PB11N_CCL_OUT1</a> &lt;&lt; 16) | MUX_PB11N_CCL_OUT1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB11N_CCL_OUT1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3065540517f9d77ce9c1246641adee78">PIN_PA25N_CCL_OUT2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(25)</td></tr>
<tr class="memdesc:a3065540517f9d77ce9c1246641adee78"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: OUT2 on PA25 mux N. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA25N_CCL_OUT2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA25N_CCL_OUT2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a3065540517f9d77ce9c1246641adee78">PIN_PA25N_CCL_OUT2</a> &lt;&lt; 16) | MUX_PA25N_CCL_OUT2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA25N_CCL_OUT2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 25)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#adc546271aa4df02baa2d6c6ebf21a469">PIN_PB09N_CCL_OUT2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(41)</td></tr>
<tr class="memdesc:adc546271aa4df02baa2d6c6ebf21a469"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: OUT2 on PB09 mux N. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB09N_CCL_OUT2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB09N_CCL_OUT2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#adc546271aa4df02baa2d6c6ebf21a469">PIN_PB09N_CCL_OUT2</a> &lt;&lt; 16) | MUX_PB09N_CCL_OUT2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB09N_CCL_OUT2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5d7e30b30f819cffa135a1577ff524b8">PIN_PB17N_CCL_OUT3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(49)</td></tr>
<tr class="memdesc:a5d7e30b30f819cffa135a1577ff524b8"><td class="mdescLeft">&#160;</td><td class="mdescRight">CCL signal: OUT3 on PB17 mux N. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB17N_CCL_OUT3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB17N_CCL_OUT3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a5d7e30b30f819cffa135a1577ff524b8">PIN_PB17N_CCL_OUT3</a> &lt;&lt; 16) | MUX_PB17N_CCL_OUT3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB17N_CCL_OUT3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 17)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac17fd817a95b4a91465d6ca092c56c70">PIN_PA13D_SERCOM4_PAD0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
<tr class="memdesc:ac17fd817a95b4a91465d6ca092c56c70"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM4 signal: PAD0 on PA13 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA13D_SERCOM4_PAD0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA13D_SERCOM4_PAD0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ac17fd817a95b4a91465d6ca092c56c70">PIN_PA13D_SERCOM4_PAD0</a> &lt;&lt; 16) | MUX_PA13D_SERCOM4_PAD0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA13D_SERCOM4_PAD0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a00d36c9207483de0ce5012e4cacf2c61">PIN_PB08D_SERCOM4_PAD0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(40)</td></tr>
<tr class="memdesc:a00d36c9207483de0ce5012e4cacf2c61"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM4 signal: PAD0 on PB08 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB08D_SERCOM4_PAD0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB08D_SERCOM4_PAD0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a00d36c9207483de0ce5012e4cacf2c61">PIN_PB08D_SERCOM4_PAD0</a> &lt;&lt; 16) | MUX_PB08D_SERCOM4_PAD0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB08D_SERCOM4_PAD0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3943d5aae1022310555f13af84222558">PIN_PB12C_SERCOM4_PAD0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(44)</td></tr>
<tr class="memdesc:a3943d5aae1022310555f13af84222558"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM4 signal: PAD0 on PB12 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB12C_SERCOM4_PAD0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB12C_SERCOM4_PAD0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a3943d5aae1022310555f13af84222558">PIN_PB12C_SERCOM4_PAD0</a> &lt;&lt; 16) | MUX_PB12C_SERCOM4_PAD0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB12C_SERCOM4_PAD0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a191299504058ede84452ce4eebb11fa7">PIN_PA12D_SERCOM4_PAD1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
<tr class="memdesc:a191299504058ede84452ce4eebb11fa7"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM4 signal: PAD1 on PA12 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA12D_SERCOM4_PAD1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA12D_SERCOM4_PAD1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a191299504058ede84452ce4eebb11fa7">PIN_PA12D_SERCOM4_PAD1</a> &lt;&lt; 16) | MUX_PA12D_SERCOM4_PAD1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA12D_SERCOM4_PAD1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a731ba4400fdcde718248eb560959d4b9">PIN_PB09D_SERCOM4_PAD1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(41)</td></tr>
<tr class="memdesc:a731ba4400fdcde718248eb560959d4b9"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM4 signal: PAD1 on PB09 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB09D_SERCOM4_PAD1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB09D_SERCOM4_PAD1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a731ba4400fdcde718248eb560959d4b9">PIN_PB09D_SERCOM4_PAD1</a> &lt;&lt; 16) | MUX_PB09D_SERCOM4_PAD1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB09D_SERCOM4_PAD1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2587d8ece4ca92375cef72a5d46621ef">PIN_PB13C_SERCOM4_PAD1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(45)</td></tr>
<tr class="memdesc:a2587d8ece4ca92375cef72a5d46621ef"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM4 signal: PAD1 on PB13 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB13C_SERCOM4_PAD1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB13C_SERCOM4_PAD1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a2587d8ece4ca92375cef72a5d46621ef">PIN_PB13C_SERCOM4_PAD1</a> &lt;&lt; 16) | MUX_PB13C_SERCOM4_PAD1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB13C_SERCOM4_PAD1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1ceb3030544fbf98f84a5941172cb9a8">PIN_PA14D_SERCOM4_PAD2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
<tr class="memdesc:a1ceb3030544fbf98f84a5941172cb9a8"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM4 signal: PAD2 on PA14 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA14D_SERCOM4_PAD2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA14D_SERCOM4_PAD2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a1ceb3030544fbf98f84a5941172cb9a8">PIN_PA14D_SERCOM4_PAD2</a> &lt;&lt; 16) | MUX_PA14D_SERCOM4_PAD2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA14D_SERCOM4_PAD2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#abef8943e52365d8a67b831f23e66a7e5">PIN_PB10D_SERCOM4_PAD2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(42)</td></tr>
<tr class="memdesc:abef8943e52365d8a67b831f23e66a7e5"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM4 signal: PAD2 on PB10 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB10D_SERCOM4_PAD2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB10D_SERCOM4_PAD2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#abef8943e52365d8a67b831f23e66a7e5">PIN_PB10D_SERCOM4_PAD2</a> &lt;&lt; 16) | MUX_PB10D_SERCOM4_PAD2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB10D_SERCOM4_PAD2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab22cc54f3de871416b0aa14707f24d63">PIN_PB14C_SERCOM4_PAD2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(46)</td></tr>
<tr class="memdesc:ab22cc54f3de871416b0aa14707f24d63"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM4 signal: PAD2 on PB14 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB14C_SERCOM4_PAD2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB14C_SERCOM4_PAD2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ab22cc54f3de871416b0aa14707f24d63">PIN_PB14C_SERCOM4_PAD2</a> &lt;&lt; 16) | MUX_PB14C_SERCOM4_PAD2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB14C_SERCOM4_PAD2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aaeffcbb860a8c25bd2675e6a726bb74e">PIN_PB11D_SERCOM4_PAD3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(43)</td></tr>
<tr class="memdesc:aaeffcbb860a8c25bd2675e6a726bb74e"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM4 signal: PAD3 on PB11 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB11D_SERCOM4_PAD3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB11D_SERCOM4_PAD3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aaeffcbb860a8c25bd2675e6a726bb74e">PIN_PB11D_SERCOM4_PAD3</a> &lt;&lt; 16) | MUX_PB11D_SERCOM4_PAD3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB11D_SERCOM4_PAD3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af75797a9c76ee2bc7584bf135abd3e89">PIN_PA15D_SERCOM4_PAD3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(15)</td></tr>
<tr class="memdesc:af75797a9c76ee2bc7584bf135abd3e89"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM4 signal: PAD3 on PA15 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA15D_SERCOM4_PAD3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA15D_SERCOM4_PAD3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#af75797a9c76ee2bc7584bf135abd3e89">PIN_PA15D_SERCOM4_PAD3</a> &lt;&lt; 16) | MUX_PA15D_SERCOM4_PAD3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA15D_SERCOM4_PAD3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 15)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae419108a03b25c2afae73f0f9997f5be">PIN_PB15C_SERCOM4_PAD3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(47)</td></tr>
<tr class="memdesc:ae419108a03b25c2afae73f0f9997f5be"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM4 signal: PAD3 on PB15 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB15C_SERCOM4_PAD3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB15C_SERCOM4_PAD3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ae419108a03b25c2afae73f0f9997f5be">PIN_PB15C_SERCOM4_PAD3</a> &lt;&lt; 16) | MUX_PB15C_SERCOM4_PAD3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB15C_SERCOM4_PAD3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 15)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6a66aa24e1c1ce5389755efda32fa6d6">PIN_PA23D_SERCOM5_PAD0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(23)</td></tr>
<tr class="memdesc:a6a66aa24e1c1ce5389755efda32fa6d6"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM5 signal: PAD0 on PA23 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA23D_SERCOM5_PAD0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA23D_SERCOM5_PAD0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a6a66aa24e1c1ce5389755efda32fa6d6">PIN_PA23D_SERCOM5_PAD0</a> &lt;&lt; 16) | MUX_PA23D_SERCOM5_PAD0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA23D_SERCOM5_PAD0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 23)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af69d1d9d5528bdd41985a4d50557bbca">PIN_PB02D_SERCOM5_PAD0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(34)</td></tr>
<tr class="memdesc:af69d1d9d5528bdd41985a4d50557bbca"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM5 signal: PAD0 on PB02 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB02D_SERCOM5_PAD0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB02D_SERCOM5_PAD0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#af69d1d9d5528bdd41985a4d50557bbca">PIN_PB02D_SERCOM5_PAD0</a> &lt;&lt; 16) | MUX_PB02D_SERCOM5_PAD0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB02D_SERCOM5_PAD0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a89bd93933c5de9c9838a9826b87aa904">PIN_PB31D_SERCOM5_PAD0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(63)</td></tr>
<tr class="memdesc:a89bd93933c5de9c9838a9826b87aa904"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM5 signal: PAD0 on PB31 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB31D_SERCOM5_PAD0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB31D_SERCOM5_PAD0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a89bd93933c5de9c9838a9826b87aa904">PIN_PB31D_SERCOM5_PAD0</a> &lt;&lt; 16) | MUX_PB31D_SERCOM5_PAD0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB31D_SERCOM5_PAD0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 31)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8e6af1b0167518136dcd1048721e4b6a">PIN_PB16C_SERCOM5_PAD0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(48)</td></tr>
<tr class="memdesc:a8e6af1b0167518136dcd1048721e4b6a"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM5 signal: PAD0 on PB16 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB16C_SERCOM5_PAD0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB16C_SERCOM5_PAD0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a8e6af1b0167518136dcd1048721e4b6a">PIN_PB16C_SERCOM5_PAD0</a> &lt;&lt; 16) | MUX_PB16C_SERCOM5_PAD0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB16C_SERCOM5_PAD0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 16)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a36cf7aac3bab2634d92473bf3ca624e0">PIN_PA22D_SERCOM5_PAD1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(22)</td></tr>
<tr class="memdesc:a36cf7aac3bab2634d92473bf3ca624e0"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM5 signal: PAD1 on PA22 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA22D_SERCOM5_PAD1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA22D_SERCOM5_PAD1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a36cf7aac3bab2634d92473bf3ca624e0">PIN_PA22D_SERCOM5_PAD1</a> &lt;&lt; 16) | MUX_PA22D_SERCOM5_PAD1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA22D_SERCOM5_PAD1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 22)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac737d7b2418abd8d9f66e0a5bb32c86e">PIN_PB03D_SERCOM5_PAD1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(35)</td></tr>
<tr class="memdesc:ac737d7b2418abd8d9f66e0a5bb32c86e"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM5 signal: PAD1 on PB03 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB03D_SERCOM5_PAD1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB03D_SERCOM5_PAD1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ac737d7b2418abd8d9f66e0a5bb32c86e">PIN_PB03D_SERCOM5_PAD1</a> &lt;&lt; 16) | MUX_PB03D_SERCOM5_PAD1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB03D_SERCOM5_PAD1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0c40598a613b940aad3079642c102a46">PIN_PB30D_SERCOM5_PAD1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(62)</td></tr>
<tr class="memdesc:a0c40598a613b940aad3079642c102a46"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM5 signal: PAD1 on PB30 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB30D_SERCOM5_PAD1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB30D_SERCOM5_PAD1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a0c40598a613b940aad3079642c102a46">PIN_PB30D_SERCOM5_PAD1</a> &lt;&lt; 16) | MUX_PB30D_SERCOM5_PAD1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB30D_SERCOM5_PAD1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 30)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac57849d68459dbd1da81ab7ea173df27">PIN_PB17C_SERCOM5_PAD1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(49)</td></tr>
<tr class="memdesc:ac57849d68459dbd1da81ab7ea173df27"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM5 signal: PAD1 on PB17 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB17C_SERCOM5_PAD1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB17C_SERCOM5_PAD1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ac57849d68459dbd1da81ab7ea173df27">PIN_PB17C_SERCOM5_PAD1</a> &lt;&lt; 16) | MUX_PB17C_SERCOM5_PAD1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB17C_SERCOM5_PAD1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 17)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a9b038b75caa4528984846d96e597f3ad">PIN_PA24D_SERCOM5_PAD2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(24)</td></tr>
<tr class="memdesc:a9b038b75caa4528984846d96e597f3ad"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM5 signal: PAD2 on PA24 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA24D_SERCOM5_PAD2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA24D_SERCOM5_PAD2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a9b038b75caa4528984846d96e597f3ad">PIN_PA24D_SERCOM5_PAD2</a> &lt;&lt; 16) | MUX_PA24D_SERCOM5_PAD2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA24D_SERCOM5_PAD2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 24)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a18549908e5cbd012a1e2f5fd05bd6eb8">PIN_PB00D_SERCOM5_PAD2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(32)</td></tr>
<tr class="memdesc:a18549908e5cbd012a1e2f5fd05bd6eb8"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM5 signal: PAD2 on PB00 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB00D_SERCOM5_PAD2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB00D_SERCOM5_PAD2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a18549908e5cbd012a1e2f5fd05bd6eb8">PIN_PB00D_SERCOM5_PAD2</a> &lt;&lt; 16) | MUX_PB00D_SERCOM5_PAD2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB00D_SERCOM5_PAD2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aff8763497dcca10009b2d7b42f65e066">PIN_PB22D_SERCOM5_PAD2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(54)</td></tr>
<tr class="memdesc:aff8763497dcca10009b2d7b42f65e066"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM5 signal: PAD2 on PB22 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB22D_SERCOM5_PAD2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB22D_SERCOM5_PAD2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aff8763497dcca10009b2d7b42f65e066">PIN_PB22D_SERCOM5_PAD2</a> &lt;&lt; 16) | MUX_PB22D_SERCOM5_PAD2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB22D_SERCOM5_PAD2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 22)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aeaebb673d7ad82b8d5199a3dbbe820d3">PIN_PA20C_SERCOM5_PAD2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(20)</td></tr>
<tr class="memdesc:aeaebb673d7ad82b8d5199a3dbbe820d3"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM5 signal: PAD2 on PA20 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA20C_SERCOM5_PAD2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA20C_SERCOM5_PAD2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aeaebb673d7ad82b8d5199a3dbbe820d3">PIN_PA20C_SERCOM5_PAD2</a> &lt;&lt; 16) | MUX_PA20C_SERCOM5_PAD2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA20C_SERCOM5_PAD2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 20)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab3c960528e3aa1c5065abd0514df2f0f">PIN_PB18C_SERCOM5_PAD2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(50)</td></tr>
<tr class="memdesc:ab3c960528e3aa1c5065abd0514df2f0f"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM5 signal: PAD2 on PB18 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB18C_SERCOM5_PAD2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB18C_SERCOM5_PAD2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ab3c960528e3aa1c5065abd0514df2f0f">PIN_PB18C_SERCOM5_PAD2</a> &lt;&lt; 16) | MUX_PB18C_SERCOM5_PAD2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB18C_SERCOM5_PAD2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 18)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa8cca3dc8884d7066c6dbd183fc417e5">PIN_PA25D_SERCOM5_PAD3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(25)</td></tr>
<tr class="memdesc:aa8cca3dc8884d7066c6dbd183fc417e5"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM5 signal: PAD3 on PA25 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA25D_SERCOM5_PAD3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA25D_SERCOM5_PAD3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aa8cca3dc8884d7066c6dbd183fc417e5">PIN_PA25D_SERCOM5_PAD3</a> &lt;&lt; 16) | MUX_PA25D_SERCOM5_PAD3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA25D_SERCOM5_PAD3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 25)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af0bbf7659e338b4d68a5751d12fa6483">PIN_PB01D_SERCOM5_PAD3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(33)</td></tr>
<tr class="memdesc:af0bbf7659e338b4d68a5751d12fa6483"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM5 signal: PAD3 on PB01 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB01D_SERCOM5_PAD3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB01D_SERCOM5_PAD3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#af0bbf7659e338b4d68a5751d12fa6483">PIN_PB01D_SERCOM5_PAD3</a> &lt;&lt; 16) | MUX_PB01D_SERCOM5_PAD3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB01D_SERCOM5_PAD3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a80814067d3f472cc8398917ad9c0131a">PIN_PB23D_SERCOM5_PAD3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(55)</td></tr>
<tr class="memdesc:a80814067d3f472cc8398917ad9c0131a"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM5 signal: PAD3 on PB23 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB23D_SERCOM5_PAD3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB23D_SERCOM5_PAD3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a80814067d3f472cc8398917ad9c0131a">PIN_PB23D_SERCOM5_PAD3</a> &lt;&lt; 16) | MUX_PB23D_SERCOM5_PAD3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB23D_SERCOM5_PAD3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 23)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aae41f3cd9fbb8c529a608996f9840a13">PIN_PA21C_SERCOM5_PAD3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(21)</td></tr>
<tr class="memdesc:aae41f3cd9fbb8c529a608996f9840a13"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM5 signal: PAD3 on PA21 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA21C_SERCOM5_PAD3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA21C_SERCOM5_PAD3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aae41f3cd9fbb8c529a608996f9840a13">PIN_PA21C_SERCOM5_PAD3</a> &lt;&lt; 16) | MUX_PA21C_SERCOM5_PAD3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA21C_SERCOM5_PAD3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 21)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#adb385009a35fac5fa0c5f45ae64708df">PIN_PB19C_SERCOM5_PAD3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(51)</td></tr>
<tr class="memdesc:adb385009a35fac5fa0c5f45ae64708df"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM5 signal: PAD3 on PB19 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB19C_SERCOM5_PAD3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB19C_SERCOM5_PAD3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#adb385009a35fac5fa0c5f45ae64708df">PIN_PB19C_SERCOM5_PAD3</a> &lt;&lt; 16) | MUX_PB19C_SERCOM5_PAD3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB19C_SERCOM5_PAD3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 19)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#add09905d2ccada956af8cca7fd172732">PIN_PC13D_SERCOM6_PAD0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(77)</td></tr>
<tr class="memdesc:add09905d2ccada956af8cca7fd172732"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM6 signal: PAD0 on PC13 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC13D_SERCOM6_PAD0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC13D_SERCOM6_PAD0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#add09905d2ccada956af8cca7fd172732">PIN_PC13D_SERCOM6_PAD0</a> &lt;&lt; 16) | MUX_PC13D_SERCOM6_PAD0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC13D_SERCOM6_PAD0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6f0654016b08bb056b7e8aa5ce30898d">PIN_PC16C_SERCOM6_PAD0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(80)</td></tr>
<tr class="memdesc:a6f0654016b08bb056b7e8aa5ce30898d"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM6 signal: PAD0 on PC16 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC16C_SERCOM6_PAD0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC16C_SERCOM6_PAD0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a6f0654016b08bb056b7e8aa5ce30898d">PIN_PC16C_SERCOM6_PAD0</a> &lt;&lt; 16) | MUX_PC16C_SERCOM6_PAD0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC16C_SERCOM6_PAD0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 16)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a9d35c0504131f2769abe7f184ec151e2">PIN_PC12D_SERCOM6_PAD1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(76)</td></tr>
<tr class="memdesc:a9d35c0504131f2769abe7f184ec151e2"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM6 signal: PAD1 on PC12 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC12D_SERCOM6_PAD1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC12D_SERCOM6_PAD1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a9d35c0504131f2769abe7f184ec151e2">PIN_PC12D_SERCOM6_PAD1</a> &lt;&lt; 16) | MUX_PC12D_SERCOM6_PAD1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC12D_SERCOM6_PAD1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad36b5a7e806584fb77ccd3727c63e199">PIN_PC05C_SERCOM6_PAD1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(69)</td></tr>
<tr class="memdesc:ad36b5a7e806584fb77ccd3727c63e199"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM6 signal: PAD1 on PC05 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC05C_SERCOM6_PAD1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC05C_SERCOM6_PAD1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ad36b5a7e806584fb77ccd3727c63e199">PIN_PC05C_SERCOM6_PAD1</a> &lt;&lt; 16) | MUX_PC05C_SERCOM6_PAD1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC05C_SERCOM6_PAD1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 5)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a47adc4dc76282eec950bbb955334dc23">PIN_PC17C_SERCOM6_PAD1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(81)</td></tr>
<tr class="memdesc:a47adc4dc76282eec950bbb955334dc23"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM6 signal: PAD1 on PC17 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC17C_SERCOM6_PAD1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC17C_SERCOM6_PAD1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a47adc4dc76282eec950bbb955334dc23">PIN_PC17C_SERCOM6_PAD1</a> &lt;&lt; 16) | MUX_PC17C_SERCOM6_PAD1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC17C_SERCOM6_PAD1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 17)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3d52138a024ab1a1aae99d512d77308b">PIN_PC14D_SERCOM6_PAD2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(78)</td></tr>
<tr class="memdesc:a3d52138a024ab1a1aae99d512d77308b"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM6 signal: PAD2 on PC14 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC14D_SERCOM6_PAD2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC14D_SERCOM6_PAD2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a3d52138a024ab1a1aae99d512d77308b">PIN_PC14D_SERCOM6_PAD2</a> &lt;&lt; 16) | MUX_PC14D_SERCOM6_PAD2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC14D_SERCOM6_PAD2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a70adfb0f739f5b4c0428cc3fad707fe2">PIN_PC06C_SERCOM6_PAD2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(70)</td></tr>
<tr class="memdesc:a70adfb0f739f5b4c0428cc3fad707fe2"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM6 signal: PAD2 on PC06 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC06C_SERCOM6_PAD2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC06C_SERCOM6_PAD2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a70adfb0f739f5b4c0428cc3fad707fe2">PIN_PC06C_SERCOM6_PAD2</a> &lt;&lt; 16) | MUX_PC06C_SERCOM6_PAD2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC06C_SERCOM6_PAD2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 6)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aabbf8386c6fc00ec4ae5b0e38ee77347">PIN_PC10C_SERCOM6_PAD2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(74)</td></tr>
<tr class="memdesc:aabbf8386c6fc00ec4ae5b0e38ee77347"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM6 signal: PAD2 on PC10 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC10C_SERCOM6_PAD2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC10C_SERCOM6_PAD2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aabbf8386c6fc00ec4ae5b0e38ee77347">PIN_PC10C_SERCOM6_PAD2</a> &lt;&lt; 16) | MUX_PC10C_SERCOM6_PAD2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC10C_SERCOM6_PAD2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#afa584864df2456aa525ce49ab697f751">PIN_PC18C_SERCOM6_PAD2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(82)</td></tr>
<tr class="memdesc:afa584864df2456aa525ce49ab697f751"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM6 signal: PAD2 on PC18 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC18C_SERCOM6_PAD2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC18C_SERCOM6_PAD2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#afa584864df2456aa525ce49ab697f751">PIN_PC18C_SERCOM6_PAD2</a> &lt;&lt; 16) | MUX_PC18C_SERCOM6_PAD2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC18C_SERCOM6_PAD2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 18)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a22792353d9edc0691c3075bdbf84331e">PIN_PC15D_SERCOM6_PAD3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(79)</td></tr>
<tr class="memdesc:a22792353d9edc0691c3075bdbf84331e"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM6 signal: PAD3 on PC15 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC15D_SERCOM6_PAD3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC15D_SERCOM6_PAD3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a22792353d9edc0691c3075bdbf84331e">PIN_PC15D_SERCOM6_PAD3</a> &lt;&lt; 16) | MUX_PC15D_SERCOM6_PAD3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC15D_SERCOM6_PAD3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 15)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5559dc4fa2bdf05f8265c08d828ff37a">PIN_PC07C_SERCOM6_PAD3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(71)</td></tr>
<tr class="memdesc:a5559dc4fa2bdf05f8265c08d828ff37a"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM6 signal: PAD3 on PC07 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC07C_SERCOM6_PAD3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC07C_SERCOM6_PAD3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a5559dc4fa2bdf05f8265c08d828ff37a">PIN_PC07C_SERCOM6_PAD3</a> &lt;&lt; 16) | MUX_PC07C_SERCOM6_PAD3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC07C_SERCOM6_PAD3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a703016701829ef29cdee31c325c510d1">PIN_PC11C_SERCOM6_PAD3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(75)</td></tr>
<tr class="memdesc:a703016701829ef29cdee31c325c510d1"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM6 signal: PAD3 on PC11 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC11C_SERCOM6_PAD3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC11C_SERCOM6_PAD3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a703016701829ef29cdee31c325c510d1">PIN_PC11C_SERCOM6_PAD3</a> &lt;&lt; 16) | MUX_PC11C_SERCOM6_PAD3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC11C_SERCOM6_PAD3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae9c65aecc2c2ea4dc952682aace4d14e">PIN_PC19C_SERCOM6_PAD3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(83)</td></tr>
<tr class="memdesc:ae9c65aecc2c2ea4dc952682aace4d14e"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM6 signal: PAD3 on PC19 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC19C_SERCOM6_PAD3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC19C_SERCOM6_PAD3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ae9c65aecc2c2ea4dc952682aace4d14e">PIN_PC19C_SERCOM6_PAD3</a> &lt;&lt; 16) | MUX_PC19C_SERCOM6_PAD3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC19C_SERCOM6_PAD3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 19)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a314a50f60a5a450e1bb306c1d67bfd40">PIN_PB21D_SERCOM7_PAD0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(53)</td></tr>
<tr class="memdesc:a314a50f60a5a450e1bb306c1d67bfd40"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM7 signal: PAD0 on PB21 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB21D_SERCOM7_PAD0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB21D_SERCOM7_PAD0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a314a50f60a5a450e1bb306c1d67bfd40">PIN_PB21D_SERCOM7_PAD0</a> &lt;&lt; 16) | MUX_PB21D_SERCOM7_PAD0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB21D_SERCOM7_PAD0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 21)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a31aea605cce72c75ac6a5634032cae16">PIN_PB30C_SERCOM7_PAD0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(62)</td></tr>
<tr class="memdesc:a31aea605cce72c75ac6a5634032cae16"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM7 signal: PAD0 on PB30 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB30C_SERCOM7_PAD0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB30C_SERCOM7_PAD0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a31aea605cce72c75ac6a5634032cae16">PIN_PB30C_SERCOM7_PAD0</a> &lt;&lt; 16) | MUX_PB30C_SERCOM7_PAD0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB30C_SERCOM7_PAD0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 30)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a99f2657f578b26c2aa214b320a2629b4">PIN_PC12C_SERCOM7_PAD0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(76)</td></tr>
<tr class="memdesc:a99f2657f578b26c2aa214b320a2629b4"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM7 signal: PAD0 on PC12 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC12C_SERCOM7_PAD0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC12C_SERCOM7_PAD0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a99f2657f578b26c2aa214b320a2629b4">PIN_PC12C_SERCOM7_PAD0</a> &lt;&lt; 16) | MUX_PC12C_SERCOM7_PAD0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC12C_SERCOM7_PAD0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a71d7e6904f7aa4687a6f46d44477fec8">PIN_PB20D_SERCOM7_PAD1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(52)</td></tr>
<tr class="memdesc:a71d7e6904f7aa4687a6f46d44477fec8"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM7 signal: PAD1 on PB20 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB20D_SERCOM7_PAD1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB20D_SERCOM7_PAD1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a71d7e6904f7aa4687a6f46d44477fec8">PIN_PB20D_SERCOM7_PAD1</a> &lt;&lt; 16) | MUX_PB20D_SERCOM7_PAD1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB20D_SERCOM7_PAD1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 20)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6dd84e1c95ed39e08526375c27e9b6f5">PIN_PB31C_SERCOM7_PAD1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(63)</td></tr>
<tr class="memdesc:a6dd84e1c95ed39e08526375c27e9b6f5"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM7 signal: PAD1 on PB31 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB31C_SERCOM7_PAD1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB31C_SERCOM7_PAD1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a6dd84e1c95ed39e08526375c27e9b6f5">PIN_PB31C_SERCOM7_PAD1</a> &lt;&lt; 16) | MUX_PB31C_SERCOM7_PAD1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB31C_SERCOM7_PAD1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 31)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#addbe554ac2caf90827680817593a6554">PIN_PC13C_SERCOM7_PAD1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(77)</td></tr>
<tr class="memdesc:addbe554ac2caf90827680817593a6554"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM7 signal: PAD1 on PC13 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC13C_SERCOM7_PAD1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC13C_SERCOM7_PAD1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#addbe554ac2caf90827680817593a6554">PIN_PC13C_SERCOM7_PAD1</a> &lt;&lt; 16) | MUX_PC13C_SERCOM7_PAD1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC13C_SERCOM7_PAD1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aca2dc7884a7f52b6a1fd5816846b37bb">PIN_PB18D_SERCOM7_PAD2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(50)</td></tr>
<tr class="memdesc:aca2dc7884a7f52b6a1fd5816846b37bb"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM7 signal: PAD2 on PB18 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB18D_SERCOM7_PAD2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB18D_SERCOM7_PAD2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aca2dc7884a7f52b6a1fd5816846b37bb">PIN_PB18D_SERCOM7_PAD2</a> &lt;&lt; 16) | MUX_PB18D_SERCOM7_PAD2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB18D_SERCOM7_PAD2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 18)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a12a0e719c774f873abe1b6479f6a3980">PIN_PC10D_SERCOM7_PAD2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(74)</td></tr>
<tr class="memdesc:a12a0e719c774f873abe1b6479f6a3980"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM7 signal: PAD2 on PC10 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC10D_SERCOM7_PAD2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC10D_SERCOM7_PAD2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a12a0e719c774f873abe1b6479f6a3980">PIN_PC10D_SERCOM7_PAD2</a> &lt;&lt; 16) | MUX_PC10D_SERCOM7_PAD2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC10D_SERCOM7_PAD2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a497eb8d6c380a8ce96bf2e2b68a88895">PIN_PC14C_SERCOM7_PAD2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(78)</td></tr>
<tr class="memdesc:a497eb8d6c380a8ce96bf2e2b68a88895"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM7 signal: PAD2 on PC14 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC14C_SERCOM7_PAD2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC14C_SERCOM7_PAD2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a497eb8d6c380a8ce96bf2e2b68a88895">PIN_PC14C_SERCOM7_PAD2</a> &lt;&lt; 16) | MUX_PC14C_SERCOM7_PAD2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC14C_SERCOM7_PAD2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a016b93cd689a15f8bca86b848da12cf5">PIN_PA30C_SERCOM7_PAD2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(30)</td></tr>
<tr class="memdesc:a016b93cd689a15f8bca86b848da12cf5"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM7 signal: PAD2 on PA30 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA30C_SERCOM7_PAD2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA30C_SERCOM7_PAD2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a016b93cd689a15f8bca86b848da12cf5">PIN_PA30C_SERCOM7_PAD2</a> &lt;&lt; 16) | MUX_PA30C_SERCOM7_PAD2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA30C_SERCOM7_PAD2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 30)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a59f36df94d518fb2b35179e75c03b340">PIN_PB19D_SERCOM7_PAD3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(51)</td></tr>
<tr class="memdesc:a59f36df94d518fb2b35179e75c03b340"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM7 signal: PAD3 on PB19 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB19D_SERCOM7_PAD3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB19D_SERCOM7_PAD3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a59f36df94d518fb2b35179e75c03b340">PIN_PB19D_SERCOM7_PAD3</a> &lt;&lt; 16) | MUX_PB19D_SERCOM7_PAD3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB19D_SERCOM7_PAD3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 19)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a9177b92af11ad6d206f1c9ac42c6eb23">PIN_PC11D_SERCOM7_PAD3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(75)</td></tr>
<tr class="memdesc:a9177b92af11ad6d206f1c9ac42c6eb23"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM7 signal: PAD3 on PC11 mux D. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC11D_SERCOM7_PAD3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC11D_SERCOM7_PAD3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a9177b92af11ad6d206f1c9ac42c6eb23">PIN_PC11D_SERCOM7_PAD3</a> &lt;&lt; 16) | MUX_PC11D_SERCOM7_PAD3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC11D_SERCOM7_PAD3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a9b9e4938d5438d890a9b7bffe681a2ce">PIN_PC15C_SERCOM7_PAD3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(79)</td></tr>
<tr class="memdesc:a9b9e4938d5438d890a9b7bffe681a2ce"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM7 signal: PAD3 on PC15 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC15C_SERCOM7_PAD3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC15C_SERCOM7_PAD3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a9b9e4938d5438d890a9b7bffe681a2ce">PIN_PC15C_SERCOM7_PAD3</a> &lt;&lt; 16) | MUX_PC15C_SERCOM7_PAD3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC15C_SERCOM7_PAD3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 15)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a196a0ea737307d8b617352b5dd2503f6">PIN_PA31C_SERCOM7_PAD3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(31)</td></tr>
<tr class="memdesc:a196a0ea737307d8b617352b5dd2503f6"><td class="mdescLeft">&#160;</td><td class="mdescRight">SERCOM7 signal: PAD3 on PA31 mux C. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA31C_SERCOM7_PAD3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA31C_SERCOM7_PAD3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a196a0ea737307d8b617352b5dd2503f6">PIN_PA31C_SERCOM7_PAD3</a> &lt;&lt; 16) | MUX_PA31C_SERCOM7_PAD3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA31C_SERCOM7_PAD3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 31)</td></tr>
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<tr class="memdesc:a45c558122b07ae69d598a702e9bcee37"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCC4 signal: WO1 on PB31 mux F. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a736f98c161da8fef1fb8087a188d243d">PIN_PB03E_TC6_WO1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(35)</td></tr>
<tr class="memdesc:a736f98c161da8fef1fb8087a188d243d"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC6 signal: WO1 on PB03 mux E. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB03E_TC6_WO1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a736f98c161da8fef1fb8087a188d243d">PIN_PB03E_TC6_WO1</a> &lt;&lt; 16) | MUX_PB03E_TC6_WO1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB03E_TC6_WO1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8126fc0f4d180275a7e4c3aef91e2269">PIN_PB17E_TC6_WO1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(49)</td></tr>
<tr class="memdesc:a8126fc0f4d180275a7e4c3aef91e2269"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC6 signal: WO1 on PB17 mux E. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB17E_TC6_WO1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a8126fc0f4d180275a7e4c3aef91e2269">PIN_PB17E_TC6_WO1</a> &lt;&lt; 16) | MUX_PB17E_TC6_WO1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB17E_TC6_WO1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 17)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5ed47c4c324e78f4d390de181498d172">PIN_PA20E_TC7_WO0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(20)</td></tr>
<tr class="memdesc:a5ed47c4c324e78f4d390de181498d172"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC7 signal: WO0 on PA20 mux E. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA20E_TC7_WO0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 20)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae6ca0cdff6526b2875f7daa54c28c43b">PIN_PB00E_TC7_WO0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(32)</td></tr>
<tr class="memdesc:ae6ca0cdff6526b2875f7daa54c28c43b"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC7 signal: WO0 on PB00 mux E. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB00E_TC7_WO0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ae6ca0cdff6526b2875f7daa54c28c43b">PIN_PB00E_TC7_WO0</a> &lt;&lt; 16) | MUX_PB00E_TC7_WO0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB00E_TC7_WO0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 0)</td></tr>
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<tr class="memdesc:a8b7186e321d915f19f227b0821d12a86"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC7 signal: WO0 on PB22 mux E. <br /></td></tr>
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<tr class="memdesc:a3d2eb46dffd583f9060dac1f53fa0efb"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC7 signal: WO1 on PA21 mux E. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA21E_TC7_WO1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 21)</td></tr>
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<tr class="memdesc:a277b372d1c6db240f7c21f54e4c53a92"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC7 signal: WO1 on PB01 mux E. <br /></td></tr>
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<tr class="memdesc:ac37fae76336321409e8f41d1be7e6f13"><td class="mdescLeft">&#160;</td><td class="mdescRight">TC7 signal: WO1 on PB23 mux E. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a55aa8756eecc8c65d6c95d39bbd66286">PIN_PA02B_ADC0_AIN0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
<tr class="memdesc:a55aa8756eecc8c65d6c95d39bbd66286"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: AIN0 on PA02 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA02B_ADC0_AIN0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA02B_ADC0_AIN0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a55aa8756eecc8c65d6c95d39bbd66286">PIN_PA02B_ADC0_AIN0</a> &lt;&lt; 16) | MUX_PA02B_ADC0_AIN0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA02B_ADC0_AIN0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#adb81a4cb3598f661d6c9fb07e3b4e5e0">PIN_PA03B_ADC0_AIN1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
<tr class="memdesc:adb81a4cb3598f661d6c9fb07e3b4e5e0"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: AIN1 on PA03 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA03B_ADC0_AIN1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA03B_ADC0_AIN1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#adb81a4cb3598f661d6c9fb07e3b4e5e0">PIN_PA03B_ADC0_AIN1</a> &lt;&lt; 16) | MUX_PA03B_ADC0_AIN1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA03B_ADC0_AIN1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2ff39fa0925103b3cb98db8ecf0a395c">PIN_PB08B_ADC0_AIN2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(40)</td></tr>
<tr class="memdesc:a2ff39fa0925103b3cb98db8ecf0a395c"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: AIN2 on PB08 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB08B_ADC0_AIN2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB08B_ADC0_AIN2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a2ff39fa0925103b3cb98db8ecf0a395c">PIN_PB08B_ADC0_AIN2</a> &lt;&lt; 16) | MUX_PB08B_ADC0_AIN2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB08B_ADC0_AIN2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a344be42bc25dfe9da3a92e6be8e22388">PIN_PB09B_ADC0_AIN3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(41)</td></tr>
<tr class="memdesc:a344be42bc25dfe9da3a92e6be8e22388"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: AIN3 on PB09 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB09B_ADC0_AIN3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB09B_ADC0_AIN3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a344be42bc25dfe9da3a92e6be8e22388">PIN_PB09B_ADC0_AIN3</a> &lt;&lt; 16) | MUX_PB09B_ADC0_AIN3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB09B_ADC0_AIN3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae7658465a04a6228aff76a710fbb9e70">PIN_PA04B_ADC0_AIN4</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
<tr class="memdesc:ae7658465a04a6228aff76a710fbb9e70"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: AIN4 on PA04 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA04B_ADC0_AIN4</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA04B_ADC0_AIN4</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ae7658465a04a6228aff76a710fbb9e70">PIN_PA04B_ADC0_AIN4</a> &lt;&lt; 16) | MUX_PA04B_ADC0_AIN4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA04B_ADC0_AIN4</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab2e318da4ce6d2ddc1b402f1406b2d3b">PIN_PA05B_ADC0_AIN5</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
<tr class="memdesc:ab2e318da4ce6d2ddc1b402f1406b2d3b"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: AIN5 on PA05 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA05B_ADC0_AIN5</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA05B_ADC0_AIN5</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ab2e318da4ce6d2ddc1b402f1406b2d3b">PIN_PA05B_ADC0_AIN5</a> &lt;&lt; 16) | MUX_PA05B_ADC0_AIN5)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA05B_ADC0_AIN5</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 5)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5778cab227620cfc715daa694db8288e">PIN_PA06B_ADC0_AIN6</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
<tr class="memdesc:a5778cab227620cfc715daa694db8288e"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: AIN6 on PA06 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA06B_ADC0_AIN6</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA06B_ADC0_AIN6</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a5778cab227620cfc715daa694db8288e">PIN_PA06B_ADC0_AIN6</a> &lt;&lt; 16) | MUX_PA06B_ADC0_AIN6)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA06B_ADC0_AIN6</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 6)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a501e38aef181b2f595a4ef613e8a98a2">PIN_PA07B_ADC0_AIN7</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
<tr class="memdesc:a501e38aef181b2f595a4ef613e8a98a2"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: AIN7 on PA07 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA07B_ADC0_AIN7</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA07B_ADC0_AIN7</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a501e38aef181b2f595a4ef613e8a98a2">PIN_PA07B_ADC0_AIN7</a> &lt;&lt; 16) | MUX_PA07B_ADC0_AIN7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA07B_ADC0_AIN7</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aceccfd85cf1a03db216038eb4e32fcf3">PIN_PA08B_ADC0_AIN8</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
<tr class="memdesc:aceccfd85cf1a03db216038eb4e32fcf3"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: AIN8 on PA08 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA08B_ADC0_AIN8</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA08B_ADC0_AIN8</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aceccfd85cf1a03db216038eb4e32fcf3">PIN_PA08B_ADC0_AIN8</a> &lt;&lt; 16) | MUX_PA08B_ADC0_AIN8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA08B_ADC0_AIN8</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1caa71383e0270741e1963c68e9e426f">PIN_PA09B_ADC0_AIN9</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
<tr class="memdesc:a1caa71383e0270741e1963c68e9e426f"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: AIN9 on PA09 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA09B_ADC0_AIN9</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA09B_ADC0_AIN9</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a1caa71383e0270741e1963c68e9e426f">PIN_PA09B_ADC0_AIN9</a> &lt;&lt; 16) | MUX_PA09B_ADC0_AIN9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA09B_ADC0_AIN9</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3f73d5fad9e51355712d6d30b5ef60e9">PIN_PA10B_ADC0_AIN10</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
<tr class="memdesc:a3f73d5fad9e51355712d6d30b5ef60e9"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: AIN10 on PA10 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA10B_ADC0_AIN10</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA10B_ADC0_AIN10</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a3f73d5fad9e51355712d6d30b5ef60e9">PIN_PA10B_ADC0_AIN10</a> &lt;&lt; 16) | MUX_PA10B_ADC0_AIN10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA10B_ADC0_AIN10</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a22fb1aa44b045a1b736bbea7e4d76702">PIN_PA11B_ADC0_AIN11</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
<tr class="memdesc:a22fb1aa44b045a1b736bbea7e4d76702"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: AIN11 on PA11 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA11B_ADC0_AIN11</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA11B_ADC0_AIN11</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a22fb1aa44b045a1b736bbea7e4d76702">PIN_PA11B_ADC0_AIN11</a> &lt;&lt; 16) | MUX_PA11B_ADC0_AIN11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA11B_ADC0_AIN11</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad610d6f46c5904a343c4895e77ec2949">PIN_PB00B_ADC0_AIN12</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(32)</td></tr>
<tr class="memdesc:ad610d6f46c5904a343c4895e77ec2949"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: AIN12 on PB00 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB00B_ADC0_AIN12</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB00B_ADC0_AIN12</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ad610d6f46c5904a343c4895e77ec2949">PIN_PB00B_ADC0_AIN12</a> &lt;&lt; 16) | MUX_PB00B_ADC0_AIN12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB00B_ADC0_AIN12</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a82a0605e63164a955a0772cee1e8a704">PIN_PB01B_ADC0_AIN13</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(33)</td></tr>
<tr class="memdesc:a82a0605e63164a955a0772cee1e8a704"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: AIN13 on PB01 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB01B_ADC0_AIN13</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB01B_ADC0_AIN13</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a82a0605e63164a955a0772cee1e8a704">PIN_PB01B_ADC0_AIN13</a> &lt;&lt; 16) | MUX_PB01B_ADC0_AIN13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB01B_ADC0_AIN13</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a186f71c64030c54a707bbc042853cc55">PIN_PB02B_ADC0_AIN14</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(34)</td></tr>
<tr class="memdesc:a186f71c64030c54a707bbc042853cc55"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: AIN14 on PB02 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB02B_ADC0_AIN14</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB02B_ADC0_AIN14</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a186f71c64030c54a707bbc042853cc55">PIN_PB02B_ADC0_AIN14</a> &lt;&lt; 16) | MUX_PB02B_ADC0_AIN14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB02B_ADC0_AIN14</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0202f983c48cb8e31c11d7ef33dc9834">PIN_PB03B_ADC0_AIN15</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(35)</td></tr>
<tr class="memdesc:a0202f983c48cb8e31c11d7ef33dc9834"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: AIN15 on PB03 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB03B_ADC0_AIN15</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB03B_ADC0_AIN15</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a0202f983c48cb8e31c11d7ef33dc9834">PIN_PB03B_ADC0_AIN15</a> &lt;&lt; 16) | MUX_PB03B_ADC0_AIN15)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB03B_ADC0_AIN15</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1963fad1ea7cddab4e49b18e91b2845c">PIN_PA03O_ADC0_DRV0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
<tr class="memdesc:a1963fad1ea7cddab4e49b18e91b2845c"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: DRV0 on PA03 mux O. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA03O_ADC0_DRV0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA03O_ADC0_DRV0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a1963fad1ea7cddab4e49b18e91b2845c">PIN_PA03O_ADC0_DRV0</a> &lt;&lt; 16) | MUX_PA03O_ADC0_DRV0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA03O_ADC0_DRV0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae6a23d3195ef6cae571dbd18854ee478">PIN_PB08O_ADC0_DRV1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(40)</td></tr>
<tr class="memdesc:ae6a23d3195ef6cae571dbd18854ee478"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: DRV1 on PB08 mux O. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB08O_ADC0_DRV1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB08O_ADC0_DRV1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ae6a23d3195ef6cae571dbd18854ee478">PIN_PB08O_ADC0_DRV1</a> &lt;&lt; 16) | MUX_PB08O_ADC0_DRV1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB08O_ADC0_DRV1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#adbcae59b905267c17a16368c5e8a9d00">PIN_PB09O_ADC0_DRV2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(41)</td></tr>
<tr class="memdesc:adbcae59b905267c17a16368c5e8a9d00"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: DRV2 on PB09 mux O. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB09O_ADC0_DRV2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB09O_ADC0_DRV2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#adbcae59b905267c17a16368c5e8a9d00">PIN_PB09O_ADC0_DRV2</a> &lt;&lt; 16) | MUX_PB09O_ADC0_DRV2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB09O_ADC0_DRV2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa62a95d8db5ca1dbc9a85483b3027611">PIN_PA04O_ADC0_DRV3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
<tr class="memdesc:aa62a95d8db5ca1dbc9a85483b3027611"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: DRV3 on PA04 mux O. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA04O_ADC0_DRV3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA04O_ADC0_DRV3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aa62a95d8db5ca1dbc9a85483b3027611">PIN_PA04O_ADC0_DRV3</a> &lt;&lt; 16) | MUX_PA04O_ADC0_DRV3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA04O_ADC0_DRV3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a40eeff97d976588dd0e28a948d512cae">PIN_PA06O_ADC0_DRV4</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
<tr class="memdesc:a40eeff97d976588dd0e28a948d512cae"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: DRV4 on PA06 mux O. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA06O_ADC0_DRV4</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA06O_ADC0_DRV4</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a40eeff97d976588dd0e28a948d512cae">PIN_PA06O_ADC0_DRV4</a> &lt;&lt; 16) | MUX_PA06O_ADC0_DRV4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA06O_ADC0_DRV4</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 6)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac04245040a82cd4257029dda90a8c9ec">PIN_PA07O_ADC0_DRV5</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
<tr class="memdesc:ac04245040a82cd4257029dda90a8c9ec"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: DRV5 on PA07 mux O. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA07O_ADC0_DRV5</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA07O_ADC0_DRV5</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ac04245040a82cd4257029dda90a8c9ec">PIN_PA07O_ADC0_DRV5</a> &lt;&lt; 16) | MUX_PA07O_ADC0_DRV5)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA07O_ADC0_DRV5</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aab74c1ba4559893c6bba93e0e2494f15">PIN_PA08O_ADC0_DRV6</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
<tr class="memdesc:aab74c1ba4559893c6bba93e0e2494f15"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: DRV6 on PA08 mux O. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA08O_ADC0_DRV6</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA08O_ADC0_DRV6</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aab74c1ba4559893c6bba93e0e2494f15">PIN_PA08O_ADC0_DRV6</a> &lt;&lt; 16) | MUX_PA08O_ADC0_DRV6)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA08O_ADC0_DRV6</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6f0d54ffbea8dcf8806b72e40f98286b">PIN_PA09O_ADC0_DRV7</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
<tr class="memdesc:a6f0d54ffbea8dcf8806b72e40f98286b"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: DRV7 on PA09 mux O. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA09O_ADC0_DRV7</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA09O_ADC0_DRV7</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a6f0d54ffbea8dcf8806b72e40f98286b">PIN_PA09O_ADC0_DRV7</a> &lt;&lt; 16) | MUX_PA09O_ADC0_DRV7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA09O_ADC0_DRV7</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa94b8eef3c555c383c4c707a0a289542">PIN_PA10O_ADC0_DRV8</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
<tr class="memdesc:aa94b8eef3c555c383c4c707a0a289542"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: DRV8 on PA10 mux O. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA10O_ADC0_DRV8</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA10O_ADC0_DRV8</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aa94b8eef3c555c383c4c707a0a289542">PIN_PA10O_ADC0_DRV8</a> &lt;&lt; 16) | MUX_PA10O_ADC0_DRV8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA10O_ADC0_DRV8</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aaf6ac5bda3d9ed2febd75c023946c5a0">PIN_PA11O_ADC0_DRV9</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
<tr class="memdesc:aaf6ac5bda3d9ed2febd75c023946c5a0"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: DRV9 on PA11 mux O. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA11O_ADC0_DRV9</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA11O_ADC0_DRV9</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aaf6ac5bda3d9ed2febd75c023946c5a0">PIN_PA11O_ADC0_DRV9</a> &lt;&lt; 16) | MUX_PA11O_ADC0_DRV9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA11O_ADC0_DRV9</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1f5f104ea785c9aecc1ed67dc7fd4c10">PIN_PA16O_ADC0_DRV10</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(16)</td></tr>
<tr class="memdesc:a1f5f104ea785c9aecc1ed67dc7fd4c10"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: DRV10 on PA16 mux O. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA16O_ADC0_DRV10</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA16O_ADC0_DRV10</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a1f5f104ea785c9aecc1ed67dc7fd4c10">PIN_PA16O_ADC0_DRV10</a> &lt;&lt; 16) | MUX_PA16O_ADC0_DRV10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA16O_ADC0_DRV10</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 16)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a29189eb1f11badca6dddd687f622efe9">PIN_PA17O_ADC0_DRV11</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(17)</td></tr>
<tr class="memdesc:a29189eb1f11badca6dddd687f622efe9"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: DRV11 on PA17 mux O. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA17O_ADC0_DRV11</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA17O_ADC0_DRV11</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a29189eb1f11badca6dddd687f622efe9">PIN_PA17O_ADC0_DRV11</a> &lt;&lt; 16) | MUX_PA17O_ADC0_DRV11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA17O_ADC0_DRV11</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 17)</td></tr>
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<tr class="memdesc:ac1724252c005911ccb381594f734ee50"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: DRV12 on PA18 mux O. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA18O_ADC0_DRV12</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA18O_ADC0_DRV12</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ac1724252c005911ccb381594f734ee50">PIN_PA18O_ADC0_DRV12</a> &lt;&lt; 16) | MUX_PA18O_ADC0_DRV12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA18O_ADC0_DRV12</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 18)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a75580c9e71023e1877a9001b79d0c9e0">PIN_PA19O_ADC0_DRV13</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(19)</td></tr>
<tr class="memdesc:a75580c9e71023e1877a9001b79d0c9e0"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: DRV13 on PA19 mux O. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA19O_ADC0_DRV13</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA19O_ADC0_DRV13</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a75580c9e71023e1877a9001b79d0c9e0">PIN_PA19O_ADC0_DRV13</a> &lt;&lt; 16) | MUX_PA19O_ADC0_DRV13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA19O_ADC0_DRV13</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 19)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7811ba2c988651c2c61e02459573e823">PIN_PA20O_ADC0_DRV14</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(20)</td></tr>
<tr class="memdesc:a7811ba2c988651c2c61e02459573e823"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: DRV14 on PA20 mux O. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA20O_ADC0_DRV14</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA20O_ADC0_DRV14</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a7811ba2c988651c2c61e02459573e823">PIN_PA20O_ADC0_DRV14</a> &lt;&lt; 16) | MUX_PA20O_ADC0_DRV14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA20O_ADC0_DRV14</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 20)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a604d2edd25dc85915500a377d47d333d">PIN_PA21O_ADC0_DRV15</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(21)</td></tr>
<tr class="memdesc:a604d2edd25dc85915500a377d47d333d"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: DRV15 on PA21 mux O. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA21O_ADC0_DRV15</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA21O_ADC0_DRV15</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a604d2edd25dc85915500a377d47d333d">PIN_PA21O_ADC0_DRV15</a> &lt;&lt; 16) | MUX_PA21O_ADC0_DRV15)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a454401ca6ea915995237970ce8b5bf4e">PIN_PA22O_ADC0_DRV16</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(22)</td></tr>
<tr class="memdesc:a454401ca6ea915995237970ce8b5bf4e"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: DRV16 on PA22 mux O. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA22O_ADC0_DRV16</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA22O_ADC0_DRV16</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a454401ca6ea915995237970ce8b5bf4e">PIN_PA22O_ADC0_DRV16</a> &lt;&lt; 16) | MUX_PA22O_ADC0_DRV16)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA22O_ADC0_DRV16</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 22)</td></tr>
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<tr class="memdesc:ab3f18155f6cac61bb44e45c1a766761f"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: DRV17 on PA23 mux O. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA23O_ADC0_DRV17</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ab3f18155f6cac61bb44e45c1a766761f">PIN_PA23O_ADC0_DRV17</a> &lt;&lt; 16) | MUX_PA23O_ADC0_DRV17)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA23O_ADC0_DRV17</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 23)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af73bd9f6eb5a0b8539fcd6e2c047bfa1">PIN_PA27O_ADC0_DRV18</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(27)</td></tr>
<tr class="memdesc:af73bd9f6eb5a0b8539fcd6e2c047bfa1"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: DRV18 on PA27 mux O. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA27O_ADC0_DRV18</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA27O_ADC0_DRV18</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#af73bd9f6eb5a0b8539fcd6e2c047bfa1">PIN_PA27O_ADC0_DRV18</a> &lt;&lt; 16) | MUX_PA27O_ADC0_DRV18)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA27O_ADC0_DRV18</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 27)</td></tr>
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<tr class="memdesc:a5b13862d74d69776c6422082dce6ce9c"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: DRV19 on PA30 mux O. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA30O_ADC0_DRV19</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA30O_ADC0_DRV19</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a5b13862d74d69776c6422082dce6ce9c">PIN_PA30O_ADC0_DRV19</a> &lt;&lt; 16) | MUX_PA30O_ADC0_DRV19)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA30O_ADC0_DRV19</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 30)</td></tr>
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<tr class="memdesc:a003cc1eff4fd259c0decd329a64b99ad"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: DRV20 on PB02 mux O. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB02O_ADC0_DRV20</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB02O_ADC0_DRV20</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a003cc1eff4fd259c0decd329a64b99ad">PIN_PB02O_ADC0_DRV20</a> &lt;&lt; 16) | MUX_PB02O_ADC0_DRV20)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB02O_ADC0_DRV20</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#afe7c72552e6d62e43b4a343e71631a33">PIN_PB03O_ADC0_DRV21</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(35)</td></tr>
<tr class="memdesc:afe7c72552e6d62e43b4a343e71631a33"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: DRV21 on PB03 mux O. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB03O_ADC0_DRV21</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB03O_ADC0_DRV21</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#afe7c72552e6d62e43b4a343e71631a33">PIN_PB03O_ADC0_DRV21</a> &lt;&lt; 16) | MUX_PB03O_ADC0_DRV21)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB03O_ADC0_DRV21</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ace86b0a3ba39a57a320132cb794dbcd8">PIN_PB04O_ADC0_DRV22</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(36)</td></tr>
<tr class="memdesc:ace86b0a3ba39a57a320132cb794dbcd8"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: DRV22 on PB04 mux O. <br /></td></tr>
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<tr class="memdesc:abb812dd33cb215819b02fde8dc83e2b3"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: DRV23 on PB05 mux O. <br /></td></tr>
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<tr class="memdesc:aee8e93606402ce8538ff388f59a4d8a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: DRV24 on PB06 mux O. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB06O_ADC0_DRV24</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aee8e93606402ce8538ff388f59a4d8a1">PIN_PB06O_ADC0_DRV24</a> &lt;&lt; 16) | MUX_PB06O_ADC0_DRV24)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB06O_ADC0_DRV24</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 6)</td></tr>
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<tr class="memdesc:aa04c82374f3c204429c9bdd25727ffd3"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: DRV25 on PB07 mux O. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB07O_ADC0_DRV25</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aa04c82374f3c204429c9bdd25727ffd3">PIN_PB07O_ADC0_DRV25</a> &lt;&lt; 16) | MUX_PB07O_ADC0_DRV25)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB07O_ADC0_DRV25</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 7)</td></tr>
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<tr class="memdesc:ac13236776ef13bbb246a38db5fcedcbe"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: DRV26 on PB12 mux O. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB12O_ADC0_DRV26</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ac13236776ef13bbb246a38db5fcedcbe">PIN_PB12O_ADC0_DRV26</a> &lt;&lt; 16) | MUX_PB12O_ADC0_DRV26)</td></tr>
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<tr class="memdesc:a538d061641af63c05beca44057cb89d4"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: DRV27 on PB13 mux O. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB13O_ADC0_DRV27</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a538d061641af63c05beca44057cb89d4">PIN_PB13O_ADC0_DRV27</a> &lt;&lt; 16) | MUX_PB13O_ADC0_DRV27)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB13O_ADC0_DRV27</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 13)</td></tr>
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<tr class="memdesc:ac16647a2f03a27eaaf9c342ea72a12eb"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: DRV28 on PB14 mux O. <br /></td></tr>
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<tr class="memdesc:aec373d14aee3d7a0ee120db4062b96fd"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: DRV29 on PB15 mux O. <br /></td></tr>
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<tr class="memdesc:a5e747c2a7f8e247f3240ac56ed01b801"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: DRV30 on PB00 mux O. <br /></td></tr>
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<tr class="memdesc:ae6cedeb179e669ab479adef553134390"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: DRV31 on PB01 mux O. <br /></td></tr>
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<tr class="memdesc:a784c2f54be152ea6835656c403756a47"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: PTCXY0 on PA03 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA03B_ADC0_PTCXY0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a784c2f54be152ea6835656c403756a47">PIN_PA03B_ADC0_PTCXY0</a> &lt;&lt; 16) | MUX_PA03B_ADC0_PTCXY0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA03B_ADC0_PTCXY0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a67e29c1596d2fd8c9eecefaf9c786496">PIN_PB08B_ADC0_PTCXY1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(40)</td></tr>
<tr class="memdesc:a67e29c1596d2fd8c9eecefaf9c786496"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: PTCXY1 on PB08 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB08B_ADC0_PTCXY1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB08B_ADC0_PTCXY1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a67e29c1596d2fd8c9eecefaf9c786496">PIN_PB08B_ADC0_PTCXY1</a> &lt;&lt; 16) | MUX_PB08B_ADC0_PTCXY1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB08B_ADC0_PTCXY1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a25fdcc3c5288cdf0bc5d486851570c77">PIN_PB09B_ADC0_PTCXY2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(41)</td></tr>
<tr class="memdesc:a25fdcc3c5288cdf0bc5d486851570c77"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: PTCXY2 on PB09 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB09B_ADC0_PTCXY2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB09B_ADC0_PTCXY2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a25fdcc3c5288cdf0bc5d486851570c77">PIN_PB09B_ADC0_PTCXY2</a> &lt;&lt; 16) | MUX_PB09B_ADC0_PTCXY2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB09B_ADC0_PTCXY2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac1a6b19dbcb239d4355bf74722462899">PIN_PA04B_ADC0_PTCXY3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
<tr class="memdesc:ac1a6b19dbcb239d4355bf74722462899"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: PTCXY3 on PA04 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA04B_ADC0_PTCXY3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA04B_ADC0_PTCXY3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ac1a6b19dbcb239d4355bf74722462899">PIN_PA04B_ADC0_PTCXY3</a> &lt;&lt; 16) | MUX_PA04B_ADC0_PTCXY3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA04B_ADC0_PTCXY3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#abb0ae97ab16dc80fc57a8a4d33108244">PIN_PA06B_ADC0_PTCXY4</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
<tr class="memdesc:abb0ae97ab16dc80fc57a8a4d33108244"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: PTCXY4 on PA06 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA06B_ADC0_PTCXY4</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA06B_ADC0_PTCXY4</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#abb0ae97ab16dc80fc57a8a4d33108244">PIN_PA06B_ADC0_PTCXY4</a> &lt;&lt; 16) | MUX_PA06B_ADC0_PTCXY4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA06B_ADC0_PTCXY4</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 6)</td></tr>
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<tr class="memdesc:a574c51a79a4c98847c325639af7b6547"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: PTCXY5 on PA07 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA07B_ADC0_PTCXY5</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="memdesc:a7dea306e5d584db7e6b7c442268579e5"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: PTCXY6 on PA08 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA08B_ADC0_PTCXY6</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a7dea306e5d584db7e6b7c442268579e5">PIN_PA08B_ADC0_PTCXY6</a> &lt;&lt; 16) | MUX_PA08B_ADC0_PTCXY6)</td></tr>
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<tr class="memdesc:a7c252bf52c87d70ef10d33cec58cedb1"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: PTCXY7 on PA09 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA09B_ADC0_PTCXY7</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a7c252bf52c87d70ef10d33cec58cedb1">PIN_PA09B_ADC0_PTCXY7</a> &lt;&lt; 16) | MUX_PA09B_ADC0_PTCXY7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa05ebecf74dc0f686d5785e096fb01cf">PIN_PA10B_ADC0_PTCXY8</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
<tr class="memdesc:aa05ebecf74dc0f686d5785e096fb01cf"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: PTCXY8 on PA10 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA10B_ADC0_PTCXY8</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA10B_ADC0_PTCXY8</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aa05ebecf74dc0f686d5785e096fb01cf">PIN_PA10B_ADC0_PTCXY8</a> &lt;&lt; 16) | MUX_PA10B_ADC0_PTCXY8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA10B_ADC0_PTCXY8</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a29e2445c680dd2b0983e8fb37db913a3">PIN_PA11B_ADC0_PTCXY9</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
<tr class="memdesc:a29e2445c680dd2b0983e8fb37db913a3"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: PTCXY9 on PA11 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA11B_ADC0_PTCXY9</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA11B_ADC0_PTCXY9</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a29e2445c680dd2b0983e8fb37db913a3">PIN_PA11B_ADC0_PTCXY9</a> &lt;&lt; 16) | MUX_PA11B_ADC0_PTCXY9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA11B_ADC0_PTCXY9</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae46ab53aa73b234bb352838bc2001053">PIN_PA16B_ADC0_PTCXY10</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(16)</td></tr>
<tr class="memdesc:ae46ab53aa73b234bb352838bc2001053"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: PTCXY10 on PA16 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA16B_ADC0_PTCXY10</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA16B_ADC0_PTCXY10</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ae46ab53aa73b234bb352838bc2001053">PIN_PA16B_ADC0_PTCXY10</a> &lt;&lt; 16) | MUX_PA16B_ADC0_PTCXY10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA16B_ADC0_PTCXY10</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 16)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a85397e94bd7137771f4cd4f97e174139">PIN_PA17B_ADC0_PTCXY11</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(17)</td></tr>
<tr class="memdesc:a85397e94bd7137771f4cd4f97e174139"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: PTCXY11 on PA17 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA17B_ADC0_PTCXY11</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA17B_ADC0_PTCXY11</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a85397e94bd7137771f4cd4f97e174139">PIN_PA17B_ADC0_PTCXY11</a> &lt;&lt; 16) | MUX_PA17B_ADC0_PTCXY11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA17B_ADC0_PTCXY11</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 17)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0b8a683d2b87230fe559ad1e302ed97e">PIN_PA18B_ADC0_PTCXY12</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(18)</td></tr>
<tr class="memdesc:a0b8a683d2b87230fe559ad1e302ed97e"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: PTCXY12 on PA18 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA18B_ADC0_PTCXY12</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA18B_ADC0_PTCXY12</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a0b8a683d2b87230fe559ad1e302ed97e">PIN_PA18B_ADC0_PTCXY12</a> &lt;&lt; 16) | MUX_PA18B_ADC0_PTCXY12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a480711f3291436de332bb57cc164620a">PIN_PA19B_ADC0_PTCXY13</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(19)</td></tr>
<tr class="memdesc:a480711f3291436de332bb57cc164620a"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: PTCXY13 on PA19 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA19B_ADC0_PTCXY13</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a480711f3291436de332bb57cc164620a">PIN_PA19B_ADC0_PTCXY13</a> &lt;&lt; 16) | MUX_PA19B_ADC0_PTCXY13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA19B_ADC0_PTCXY13</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 19)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a31706dfe73b7a197d56c975ea9bd11f1">PIN_PA20B_ADC0_PTCXY14</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(20)</td></tr>
<tr class="memdesc:a31706dfe73b7a197d56c975ea9bd11f1"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: PTCXY14 on PA20 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA20B_ADC0_PTCXY14</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a31706dfe73b7a197d56c975ea9bd11f1">PIN_PA20B_ADC0_PTCXY14</a> &lt;&lt; 16) | MUX_PA20B_ADC0_PTCXY14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad8ae9144243e006000d0d4f0fbf804ba">PIN_PA21B_ADC0_PTCXY15</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(21)</td></tr>
<tr class="memdesc:ad8ae9144243e006000d0d4f0fbf804ba"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: PTCXY15 on PA21 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA21B_ADC0_PTCXY15</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ad8ae9144243e006000d0d4f0fbf804ba">PIN_PA21B_ADC0_PTCXY15</a> &lt;&lt; 16) | MUX_PA21B_ADC0_PTCXY15)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af46d4c957b46480fde3e582606cd3d8c">PIN_PA22B_ADC0_PTCXY16</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(22)</td></tr>
<tr class="memdesc:af46d4c957b46480fde3e582606cd3d8c"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: PTCXY16 on PA22 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA22B_ADC0_PTCXY16</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#af46d4c957b46480fde3e582606cd3d8c">PIN_PA22B_ADC0_PTCXY16</a> &lt;&lt; 16) | MUX_PA22B_ADC0_PTCXY16)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA22B_ADC0_PTCXY16</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 22)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aaca514230fcf8e3d142ba3839243035a">PIN_PA23B_ADC0_PTCXY17</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(23)</td></tr>
<tr class="memdesc:aaca514230fcf8e3d142ba3839243035a"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: PTCXY17 on PA23 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA23B_ADC0_PTCXY17</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aaca514230fcf8e3d142ba3839243035a">PIN_PA23B_ADC0_PTCXY17</a> &lt;&lt; 16) | MUX_PA23B_ADC0_PTCXY17)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA23B_ADC0_PTCXY17</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 23)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1f6699fd0d3a7877e4609a81c3c47b9a">PIN_PA27B_ADC0_PTCXY18</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(27)</td></tr>
<tr class="memdesc:a1f6699fd0d3a7877e4609a81c3c47b9a"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: PTCXY18 on PA27 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA27B_ADC0_PTCXY18</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA27B_ADC0_PTCXY18</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a1f6699fd0d3a7877e4609a81c3c47b9a">PIN_PA27B_ADC0_PTCXY18</a> &lt;&lt; 16) | MUX_PA27B_ADC0_PTCXY18)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA27B_ADC0_PTCXY18</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 27)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6df4f427fa92417aae87a181a8c3db30">PIN_PA30B_ADC0_PTCXY19</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(30)</td></tr>
<tr class="memdesc:a6df4f427fa92417aae87a181a8c3db30"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: PTCXY19 on PA30 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA30B_ADC0_PTCXY19</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA30B_ADC0_PTCXY19</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a6df4f427fa92417aae87a181a8c3db30">PIN_PA30B_ADC0_PTCXY19</a> &lt;&lt; 16) | MUX_PA30B_ADC0_PTCXY19)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA30B_ADC0_PTCXY19</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 30)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a04c6898ae2c640f37b602d6ac3fec204">PIN_PB02B_ADC0_PTCXY20</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(34)</td></tr>
<tr class="memdesc:a04c6898ae2c640f37b602d6ac3fec204"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: PTCXY20 on PB02 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB02B_ADC0_PTCXY20</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB02B_ADC0_PTCXY20</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a04c6898ae2c640f37b602d6ac3fec204">PIN_PB02B_ADC0_PTCXY20</a> &lt;&lt; 16) | MUX_PB02B_ADC0_PTCXY20)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB02B_ADC0_PTCXY20</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5f42c846bd1c11dd378d68faa5ffea98">PIN_PB03B_ADC0_PTCXY21</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(35)</td></tr>
<tr class="memdesc:a5f42c846bd1c11dd378d68faa5ffea98"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: PTCXY21 on PB03 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB03B_ADC0_PTCXY21</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a5f42c846bd1c11dd378d68faa5ffea98">PIN_PB03B_ADC0_PTCXY21</a> &lt;&lt; 16) | MUX_PB03B_ADC0_PTCXY21)</td></tr>
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<tr class="memdesc:ab8dd8d6d0715a21d207405416a343d91"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: PTCXY22 on PB04 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB04B_ADC0_PTCXY22</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ab8dd8d6d0715a21d207405416a343d91">PIN_PB04B_ADC0_PTCXY22</a> &lt;&lt; 16) | MUX_PB04B_ADC0_PTCXY22)</td></tr>
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<tr class="memdesc:a6b2aff4fdf703d401fcff33c1ec239b5"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: PTCXY23 on PB05 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB05B_ADC0_PTCXY23</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a6b2aff4fdf703d401fcff33c1ec239b5">PIN_PB05B_ADC0_PTCXY23</a> &lt;&lt; 16) | MUX_PB05B_ADC0_PTCXY23)</td></tr>
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<tr class="memdesc:a61f6309b1993c6351c1306aeaeb4ee04"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: PTCXY24 on PB06 mux B. <br /></td></tr>
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<tr class="memdesc:ab6efc8ac261269eaae59e9ecbd2d23d2"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: PTCXY25 on PB07 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB07B_ADC0_PTCXY25</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ab6efc8ac261269eaae59e9ecbd2d23d2">PIN_PB07B_ADC0_PTCXY25</a> &lt;&lt; 16) | MUX_PB07B_ADC0_PTCXY25)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3cd5e2958db2decefe237ea16f7ef880">PIN_PB12B_ADC0_PTCXY26</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(44)</td></tr>
<tr class="memdesc:a3cd5e2958db2decefe237ea16f7ef880"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: PTCXY26 on PB12 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a9f2d7f3bda7f2ef4d6eb7be44c9f9216">PIN_PB13B_ADC0_PTCXY27</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(45)</td></tr>
<tr class="memdesc:a9f2d7f3bda7f2ef4d6eb7be44c9f9216"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: PTCXY27 on PB13 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB13B_ADC0_PTCXY27</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a9f2d7f3bda7f2ef4d6eb7be44c9f9216">PIN_PB13B_ADC0_PTCXY27</a> &lt;&lt; 16) | MUX_PB13B_ADC0_PTCXY27)</td></tr>
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<tr class="memdesc:a0bf30bc3602ed48035eaab5e8134992b"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: PTCXY28 on PB14 mux B. <br /></td></tr>
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<tr class="memdesc:af7fb8c70fc1c62e36b00829de2dd4b10"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: PTCXY29 on PB15 mux B. <br /></td></tr>
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<tr class="memdesc:a07ee9e0fae09a010e759e04175036b14"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: PTCXY30 on PB00 mux B. <br /></td></tr>
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<tr class="memdesc:a4b8994039f5b7fb8144c30db8671ee6e"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC0 signal: PTCXY31 on PB01 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB01B_ADC0_PTCXY31</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab4aea2d25f14f53d40dc26ccd47d18d1">PIN_PB08B_ADC1_AIN0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(40)</td></tr>
<tr class="memdesc:ab4aea2d25f14f53d40dc26ccd47d18d1"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC1 signal: AIN0 on PB08 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB08B_ADC1_AIN0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB08B_ADC1_AIN0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ab4aea2d25f14f53d40dc26ccd47d18d1">PIN_PB08B_ADC1_AIN0</a> &lt;&lt; 16) | MUX_PB08B_ADC1_AIN0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB08B_ADC1_AIN0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5a03b2710c270e14264403dad4e6d861">PIN_PB09B_ADC1_AIN1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(41)</td></tr>
<tr class="memdesc:a5a03b2710c270e14264403dad4e6d861"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC1 signal: AIN1 on PB09 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB09B_ADC1_AIN1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB09B_ADC1_AIN1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a5a03b2710c270e14264403dad4e6d861">PIN_PB09B_ADC1_AIN1</a> &lt;&lt; 16) | MUX_PB09B_ADC1_AIN1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB09B_ADC1_AIN1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af9e6229b9dbee3c7bacdad90f30cc5cf">PIN_PA08B_ADC1_AIN2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
<tr class="memdesc:af9e6229b9dbee3c7bacdad90f30cc5cf"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC1 signal: AIN2 on PA08 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA08B_ADC1_AIN2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA08B_ADC1_AIN2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#af9e6229b9dbee3c7bacdad90f30cc5cf">PIN_PA08B_ADC1_AIN2</a> &lt;&lt; 16) | MUX_PA08B_ADC1_AIN2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA08B_ADC1_AIN2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa345bdaaa58db83ba6928685882ff7e9">PIN_PA09B_ADC1_AIN3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
<tr class="memdesc:aa345bdaaa58db83ba6928685882ff7e9"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC1 signal: AIN3 on PA09 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA09B_ADC1_AIN3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA09B_ADC1_AIN3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aa345bdaaa58db83ba6928685882ff7e9">PIN_PA09B_ADC1_AIN3</a> &lt;&lt; 16) | MUX_PA09B_ADC1_AIN3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA09B_ADC1_AIN3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0a2f519ba1691dec19faaf4b2b47ecfd">PIN_PC02B_ADC1_AIN4</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(66)</td></tr>
<tr class="memdesc:a0a2f519ba1691dec19faaf4b2b47ecfd"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC1 signal: AIN4 on PC02 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC02B_ADC1_AIN4</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC02B_ADC1_AIN4</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a0a2f519ba1691dec19faaf4b2b47ecfd">PIN_PC02B_ADC1_AIN4</a> &lt;&lt; 16) | MUX_PC02B_ADC1_AIN4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC02B_ADC1_AIN4</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae1e1bbe3dd622f37e981e9abd52fcb5d">PIN_PC03B_ADC1_AIN5</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(67)</td></tr>
<tr class="memdesc:ae1e1bbe3dd622f37e981e9abd52fcb5d"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC1 signal: AIN5 on PC03 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC03B_ADC1_AIN5</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ae1e1bbe3dd622f37e981e9abd52fcb5d">PIN_PC03B_ADC1_AIN5</a> &lt;&lt; 16) | MUX_PC03B_ADC1_AIN5)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC03B_ADC1_AIN5</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 3)</td></tr>
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<tr class="memdesc:a2e48c0a61d69ac34ed9b34f2bdf7c2a5"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC1 signal: AIN6 on PB04 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB04B_ADC1_AIN6</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB04B_ADC1_AIN6</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a2e48c0a61d69ac34ed9b34f2bdf7c2a5">PIN_PB04B_ADC1_AIN6</a> &lt;&lt; 16) | MUX_PB04B_ADC1_AIN6)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB04B_ADC1_AIN6</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4d03ecccf6afc8a55f4ded17218adc9a">PIN_PB05B_ADC1_AIN7</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(37)</td></tr>
<tr class="memdesc:a4d03ecccf6afc8a55f4ded17218adc9a"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC1 signal: AIN7 on PB05 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB05B_ADC1_AIN7</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB05B_ADC1_AIN7</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a4d03ecccf6afc8a55f4ded17218adc9a">PIN_PB05B_ADC1_AIN7</a> &lt;&lt; 16) | MUX_PB05B_ADC1_AIN7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB05B_ADC1_AIN7</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 5)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a870dd9e9de79013b71c884f30062abba">PIN_PB06B_ADC1_AIN8</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(38)</td></tr>
<tr class="memdesc:a870dd9e9de79013b71c884f30062abba"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC1 signal: AIN8 on PB06 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB06B_ADC1_AIN8</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB06B_ADC1_AIN8</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a870dd9e9de79013b71c884f30062abba">PIN_PB06B_ADC1_AIN8</a> &lt;&lt; 16) | MUX_PB06B_ADC1_AIN8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB06B_ADC1_AIN8</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 6)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3b4e96995c22871c4335e70c008b11b3">PIN_PB07B_ADC1_AIN9</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(39)</td></tr>
<tr class="memdesc:a3b4e96995c22871c4335e70c008b11b3"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC1 signal: AIN9 on PB07 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB07B_ADC1_AIN9</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB07B_ADC1_AIN9</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a3b4e96995c22871c4335e70c008b11b3">PIN_PB07B_ADC1_AIN9</a> &lt;&lt; 16) | MUX_PB07B_ADC1_AIN9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB07B_ADC1_AIN9</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac287c4b9c3d4a192e62adb7f7d61308a">PIN_PC00B_ADC1_AIN10</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(64)</td></tr>
<tr class="memdesc:ac287c4b9c3d4a192e62adb7f7d61308a"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC1 signal: AIN10 on PC00 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC00B_ADC1_AIN10</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC00B_ADC1_AIN10</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ac287c4b9c3d4a192e62adb7f7d61308a">PIN_PC00B_ADC1_AIN10</a> &lt;&lt; 16) | MUX_PC00B_ADC1_AIN10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC00B_ADC1_AIN10</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7e06599af49b239b423962d006539735">PIN_PC01B_ADC1_AIN11</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(65)</td></tr>
<tr class="memdesc:a7e06599af49b239b423962d006539735"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC1 signal: AIN11 on PC01 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC01B_ADC1_AIN11</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC01B_ADC1_AIN11</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a7e06599af49b239b423962d006539735">PIN_PC01B_ADC1_AIN11</a> &lt;&lt; 16) | MUX_PC01B_ADC1_AIN11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC01B_ADC1_AIN11</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab5911f08cdb90b1f7879415264025446">PIN_PA02B_DAC_VOUT0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
<tr class="memdesc:ab5911f08cdb90b1f7879415264025446"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC signal: VOUT0 on PA02 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA02B_DAC_VOUT0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA02B_DAC_VOUT0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ab5911f08cdb90b1f7879415264025446">PIN_PA02B_DAC_VOUT0</a> &lt;&lt; 16) | MUX_PA02B_DAC_VOUT0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA02B_DAC_VOUT0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a01411a15324989201b2c5de18969e07b">PIN_PA05B_DAC_VOUT1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
<tr class="memdesc:a01411a15324989201b2c5de18969e07b"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC signal: VOUT1 on PA05 mux B. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA05B_DAC_VOUT1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA05B_DAC_VOUT1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a01411a15324989201b2c5de18969e07b">PIN_PA05B_DAC_VOUT1</a> &lt;&lt; 16) | MUX_PA05B_DAC_VOUT1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA05B_DAC_VOUT1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 5)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad57f1dfcecdd92fdc301a0b7c076313a">PIN_PA09J_I2S_FS0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
<tr class="memdesc:ad57f1dfcecdd92fdc301a0b7c076313a"><td class="mdescLeft">&#160;</td><td class="mdescRight">I2S signal: FS0 on PA09 mux J. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA09J_I2S_FS0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA09J_I2S_FS0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ad57f1dfcecdd92fdc301a0b7c076313a">PIN_PA09J_I2S_FS0</a> &lt;&lt; 16) | MUX_PA09J_I2S_FS0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA09J_I2S_FS0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2e59889980df747b588d166ff0901abe">PIN_PA20J_I2S_FS0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(20)</td></tr>
<tr class="memdesc:a2e59889980df747b588d166ff0901abe"><td class="mdescLeft">&#160;</td><td class="mdescRight">I2S signal: FS0 on PA20 mux J. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA20J_I2S_FS0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA20J_I2S_FS0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a2e59889980df747b588d166ff0901abe">PIN_PA20J_I2S_FS0</a> &lt;&lt; 16) | MUX_PA20J_I2S_FS0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA20J_I2S_FS0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 20)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a70dece10118a43cc55302df35b37ad63">PIN_PA23J_I2S_FS1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(23)</td></tr>
<tr class="memdesc:a70dece10118a43cc55302df35b37ad63"><td class="mdescLeft">&#160;</td><td class="mdescRight">I2S signal: FS1 on PA23 mux J. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA23J_I2S_FS1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA23J_I2S_FS1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a70dece10118a43cc55302df35b37ad63">PIN_PA23J_I2S_FS1</a> &lt;&lt; 16) | MUX_PA23J_I2S_FS1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA23J_I2S_FS1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 23)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a68d2992f731b20c19f0ae740157d5213">PIN_PB11J_I2S_FS1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(43)</td></tr>
<tr class="memdesc:a68d2992f731b20c19f0ae740157d5213"><td class="mdescLeft">&#160;</td><td class="mdescRight">I2S signal: FS1 on PB11 mux J. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB11J_I2S_FS1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB11J_I2S_FS1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a68d2992f731b20c19f0ae740157d5213">PIN_PB11J_I2S_FS1</a> &lt;&lt; 16) | MUX_PB11J_I2S_FS1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB11J_I2S_FS1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#abdb786683728918a543efeb2c12023cc">PIN_PA08J_I2S_MCK0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
<tr class="memdesc:abdb786683728918a543efeb2c12023cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">I2S signal: MCK0 on PA08 mux J. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA08J_I2S_MCK0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA08J_I2S_MCK0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#abdb786683728918a543efeb2c12023cc">PIN_PA08J_I2S_MCK0</a> &lt;&lt; 16) | MUX_PA08J_I2S_MCK0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA08J_I2S_MCK0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a375c1c34361038e192c89561d6541957">PIN_PB17J_I2S_MCK0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(49)</td></tr>
<tr class="memdesc:a375c1c34361038e192c89561d6541957"><td class="mdescLeft">&#160;</td><td class="mdescRight">I2S signal: MCK0 on PB17 mux J. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB17J_I2S_MCK0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB17J_I2S_MCK0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a375c1c34361038e192c89561d6541957">PIN_PB17J_I2S_MCK0</a> &lt;&lt; 16) | MUX_PB17J_I2S_MCK0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB17J_I2S_MCK0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 17)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4d12818153babaa8ee70733398df2b4d">PIN_PB13J_I2S_MCK1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(45)</td></tr>
<tr class="memdesc:a4d12818153babaa8ee70733398df2b4d"><td class="mdescLeft">&#160;</td><td class="mdescRight">I2S signal: MCK1 on PB13 mux J. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB13J_I2S_MCK1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB13J_I2S_MCK1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a4d12818153babaa8ee70733398df2b4d">PIN_PB13J_I2S_MCK1</a> &lt;&lt; 16) | MUX_PB13J_I2S_MCK1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB13J_I2S_MCK1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a9cdbd4d3cfc40b7d10d7e6c584bc8ca1">PIN_PA10J_I2S_SCK0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
<tr class="memdesc:a9cdbd4d3cfc40b7d10d7e6c584bc8ca1"><td class="mdescLeft">&#160;</td><td class="mdescRight">I2S signal: SCK0 on PA10 mux J. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA10J_I2S_SCK0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA10J_I2S_SCK0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a9cdbd4d3cfc40b7d10d7e6c584bc8ca1">PIN_PA10J_I2S_SCK0</a> &lt;&lt; 16) | MUX_PA10J_I2S_SCK0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA10J_I2S_SCK0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aace264fd0a10582361b0388268bad25f">PIN_PB16J_I2S_SCK0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(48)</td></tr>
<tr class="memdesc:aace264fd0a10582361b0388268bad25f"><td class="mdescLeft">&#160;</td><td class="mdescRight">I2S signal: SCK0 on PB16 mux J. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB16J_I2S_SCK0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB16J_I2S_SCK0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aace264fd0a10582361b0388268bad25f">PIN_PB16J_I2S_SCK0</a> &lt;&lt; 16) | MUX_PB16J_I2S_SCK0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB16J_I2S_SCK0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 16)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aab56848fdaf7f85c3eebb0b045610486">PIN_PB12J_I2S_SCK1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(44)</td></tr>
<tr class="memdesc:aab56848fdaf7f85c3eebb0b045610486"><td class="mdescLeft">&#160;</td><td class="mdescRight">I2S signal: SCK1 on PB12 mux J. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB12J_I2S_SCK1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB12J_I2S_SCK1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aab56848fdaf7f85c3eebb0b045610486">PIN_PB12J_I2S_SCK1</a> &lt;&lt; 16) | MUX_PB12J_I2S_SCK1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB12J_I2S_SCK1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2c545bc1954b16d4aeb60999133d9b99">PIN_PA22J_I2S_SDI</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(22)</td></tr>
<tr class="memdesc:a2c545bc1954b16d4aeb60999133d9b99"><td class="mdescLeft">&#160;</td><td class="mdescRight">I2S signal: SDI on PA22 mux J. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA22J_I2S_SDI</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA22J_I2S_SDI</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a2c545bc1954b16d4aeb60999133d9b99">PIN_PA22J_I2S_SDI</a> &lt;&lt; 16) | MUX_PA22J_I2S_SDI)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA22J_I2S_SDI</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 22)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a69b0fa5e8f8cc71567a13d2d6311fc16">PIN_PB10J_I2S_SDI</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(42)</td></tr>
<tr class="memdesc:a69b0fa5e8f8cc71567a13d2d6311fc16"><td class="mdescLeft">&#160;</td><td class="mdescRight">I2S signal: SDI on PB10 mux J. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB10J_I2S_SDI</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB10J_I2S_SDI</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a69b0fa5e8f8cc71567a13d2d6311fc16">PIN_PB10J_I2S_SDI</a> &lt;&lt; 16) | MUX_PB10J_I2S_SDI)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB10J_I2S_SDI</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7f7b2b73be9dad6b4dad521f9c315523">PIN_PA11J_I2S_SDO</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
<tr class="memdesc:a7f7b2b73be9dad6b4dad521f9c315523"><td class="mdescLeft">&#160;</td><td class="mdescRight">I2S signal: SDO on PA11 mux J. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA11J_I2S_SDO</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA11J_I2S_SDO</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a7f7b2b73be9dad6b4dad521f9c315523">PIN_PA11J_I2S_SDO</a> &lt;&lt; 16) | MUX_PA11J_I2S_SDO)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA11J_I2S_SDO</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#abbec72d29abc239aa2239b373bd15572">PIN_PA21J_I2S_SDO</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(21)</td></tr>
<tr class="memdesc:abbec72d29abc239aa2239b373bd15572"><td class="mdescLeft">&#160;</td><td class="mdescRight">I2S signal: SDO on PA21 mux J. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA21J_I2S_SDO</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA21J_I2S_SDO</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#abbec72d29abc239aa2239b373bd15572">PIN_PA21J_I2S_SDO</a> &lt;&lt; 16) | MUX_PA21J_I2S_SDO)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA21J_I2S_SDO</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 21)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a411bd3e7690b568fa356436eca829b79">PIN_PA14K_PCC_CLK</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
<tr class="memdesc:a411bd3e7690b568fa356436eca829b79"><td class="mdescLeft">&#160;</td><td class="mdescRight">PCC signal: CLK on PA14 mux K. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA14K_PCC_CLK</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA14K_PCC_CLK</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a411bd3e7690b568fa356436eca829b79">PIN_PA14K_PCC_CLK</a> &lt;&lt; 16) | MUX_PA14K_PCC_CLK)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA14K_PCC_CLK</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6b3fb5e2876d9e9ec3655e3d55ae23a8">PIN_PA16K_PCC_DATA0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(16)</td></tr>
<tr class="memdesc:a6b3fb5e2876d9e9ec3655e3d55ae23a8"><td class="mdescLeft">&#160;</td><td class="mdescRight">PCC signal: DATA0 on PA16 mux K. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA16K_PCC_DATA0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA16K_PCC_DATA0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a6b3fb5e2876d9e9ec3655e3d55ae23a8">PIN_PA16K_PCC_DATA0</a> &lt;&lt; 16) | MUX_PA16K_PCC_DATA0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA16K_PCC_DATA0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 16)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1aad4374898a1652ca028abdabff42d1">PIN_PA17K_PCC_DATA1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(17)</td></tr>
<tr class="memdesc:a1aad4374898a1652ca028abdabff42d1"><td class="mdescLeft">&#160;</td><td class="mdescRight">PCC signal: DATA1 on PA17 mux K. <br /></td></tr>
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<tr class="memitem:a858fb6a37b4922cd0938284d10f87e2a"><td class="memItemLeft" align="right" valign="top"><a id="a858fb6a37b4922cd0938284d10f87e2a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA17K_PCC_DATA1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA17K_PCC_DATA1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a1aad4374898a1652ca028abdabff42d1">PIN_PA17K_PCC_DATA1</a> &lt;&lt; 16) | MUX_PA17K_PCC_DATA1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA17K_PCC_DATA1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 17)</td></tr>
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<tr class="memitem:a579c6c8bc97df0de75f0ca3bd31af7fd"><td class="memItemLeft" align="right" valign="top"><a id="a579c6c8bc97df0de75f0ca3bd31af7fd"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a579c6c8bc97df0de75f0ca3bd31af7fd">PIN_PA18K_PCC_DATA2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(18)</td></tr>
<tr class="memdesc:a579c6c8bc97df0de75f0ca3bd31af7fd"><td class="mdescLeft">&#160;</td><td class="mdescRight">PCC signal: DATA2 on PA18 mux K. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA18K_PCC_DATA2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA18K_PCC_DATA2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a579c6c8bc97df0de75f0ca3bd31af7fd">PIN_PA18K_PCC_DATA2</a> &lt;&lt; 16) | MUX_PA18K_PCC_DATA2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA18K_PCC_DATA2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 18)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a159ef1fbea04782bcb324845399db83a">PIN_PA19K_PCC_DATA3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(19)</td></tr>
<tr class="memdesc:a159ef1fbea04782bcb324845399db83a"><td class="mdescLeft">&#160;</td><td class="mdescRight">PCC signal: DATA3 on PA19 mux K. <br /></td></tr>
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<tr class="memitem:a3a23bfa1a8314b957e4f7dc34300ecfe"><td class="memItemLeft" align="right" valign="top"><a id="a3a23bfa1a8314b957e4f7dc34300ecfe"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA19K_PCC_DATA3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA19K_PCC_DATA3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a159ef1fbea04782bcb324845399db83a">PIN_PA19K_PCC_DATA3</a> &lt;&lt; 16) | MUX_PA19K_PCC_DATA3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA19K_PCC_DATA3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 19)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac928db310ac25bb5b4db52e595ba49a4">PIN_PA20K_PCC_DATA4</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(20)</td></tr>
<tr class="memdesc:ac928db310ac25bb5b4db52e595ba49a4"><td class="mdescLeft">&#160;</td><td class="mdescRight">PCC signal: DATA4 on PA20 mux K. <br /></td></tr>
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<tr class="memitem:aef5b522747ccec1a1b95858042247d61"><td class="memItemLeft" align="right" valign="top"><a id="aef5b522747ccec1a1b95858042247d61"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA20K_PCC_DATA4</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA20K_PCC_DATA4</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ac928db310ac25bb5b4db52e595ba49a4">PIN_PA20K_PCC_DATA4</a> &lt;&lt; 16) | MUX_PA20K_PCC_DATA4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA20K_PCC_DATA4</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 20)</td></tr>
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<tr class="memitem:a0c422e9182101dd4c2cb6a1cefd89b59"><td class="memItemLeft" align="right" valign="top"><a id="a0c422e9182101dd4c2cb6a1cefd89b59"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0c422e9182101dd4c2cb6a1cefd89b59">PIN_PA21K_PCC_DATA5</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(21)</td></tr>
<tr class="memdesc:a0c422e9182101dd4c2cb6a1cefd89b59"><td class="mdescLeft">&#160;</td><td class="mdescRight">PCC signal: DATA5 on PA21 mux K. <br /></td></tr>
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<tr class="memitem:ae5ec056d119545cb50e692261e981b9a"><td class="memItemLeft" align="right" valign="top"><a id="ae5ec056d119545cb50e692261e981b9a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA21K_PCC_DATA5</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA21K_PCC_DATA5</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a0c422e9182101dd4c2cb6a1cefd89b59">PIN_PA21K_PCC_DATA5</a> &lt;&lt; 16) | MUX_PA21K_PCC_DATA5)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA21K_PCC_DATA5</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 21)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab259822602b60999587ffd97ce517ef3">PIN_PA22K_PCC_DATA6</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(22)</td></tr>
<tr class="memdesc:ab259822602b60999587ffd97ce517ef3"><td class="mdescLeft">&#160;</td><td class="mdescRight">PCC signal: DATA6 on PA22 mux K. <br /></td></tr>
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<tr class="memitem:a5b987af0771f5f01c46d7dbced40c2bd"><td class="memItemLeft" align="right" valign="top"><a id="a5b987af0771f5f01c46d7dbced40c2bd"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA22K_PCC_DATA6</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA22K_PCC_DATA6</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ab259822602b60999587ffd97ce517ef3">PIN_PA22K_PCC_DATA6</a> &lt;&lt; 16) | MUX_PA22K_PCC_DATA6)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA22K_PCC_DATA6</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 22)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#acc6782550f27bce322f863060115b087">PIN_PA23K_PCC_DATA7</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(23)</td></tr>
<tr class="memdesc:acc6782550f27bce322f863060115b087"><td class="mdescLeft">&#160;</td><td class="mdescRight">PCC signal: DATA7 on PA23 mux K. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA23K_PCC_DATA7</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA23K_PCC_DATA7</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#acc6782550f27bce322f863060115b087">PIN_PA23K_PCC_DATA7</a> &lt;&lt; 16) | MUX_PA23K_PCC_DATA7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA23K_PCC_DATA7</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 23)</td></tr>
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<tr class="memitem:ad5c99a74d773dc0d73987345fa1c8282"><td class="memItemLeft" align="right" valign="top"><a id="ad5c99a74d773dc0d73987345fa1c8282"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad5c99a74d773dc0d73987345fa1c8282">PIN_PB14K_PCC_DATA8</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(46)</td></tr>
<tr class="memdesc:ad5c99a74d773dc0d73987345fa1c8282"><td class="mdescLeft">&#160;</td><td class="mdescRight">PCC signal: DATA8 on PB14 mux K. <br /></td></tr>
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<tr class="memitem:ab23d9050756d7e56c6eca2bc91936e90"><td class="memItemLeft" align="right" valign="top"><a id="ab23d9050756d7e56c6eca2bc91936e90"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB14K_PCC_DATA8</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB14K_PCC_DATA8</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ad5c99a74d773dc0d73987345fa1c8282">PIN_PB14K_PCC_DATA8</a> &lt;&lt; 16) | MUX_PB14K_PCC_DATA8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB14K_PCC_DATA8</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 14)</td></tr>
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<tr class="memitem:a4d7e10c6674b55cdd8411414052b25ea"><td class="memItemLeft" align="right" valign="top"><a id="a4d7e10c6674b55cdd8411414052b25ea"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4d7e10c6674b55cdd8411414052b25ea">PIN_PB15K_PCC_DATA9</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(47)</td></tr>
<tr class="memdesc:a4d7e10c6674b55cdd8411414052b25ea"><td class="mdescLeft">&#160;</td><td class="mdescRight">PCC signal: DATA9 on PB15 mux K. <br /></td></tr>
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<tr class="memitem:a95b2baf04d0617acedf6372a9cf221f3"><td class="memItemLeft" align="right" valign="top"><a id="a95b2baf04d0617acedf6372a9cf221f3"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB15K_PCC_DATA9</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB15K_PCC_DATA9</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a4d7e10c6674b55cdd8411414052b25ea">PIN_PB15K_PCC_DATA9</a> &lt;&lt; 16) | MUX_PB15K_PCC_DATA9)</td></tr>
<tr class="separator:a4147505707f3d369b7c4a107e26fb512"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a57ff2f5276ddf91f90e154245361b0aa"><td class="memItemLeft" align="right" valign="top"><a id="a57ff2f5276ddf91f90e154245361b0aa"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB15K_PCC_DATA9</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 15)</td></tr>
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<tr class="memitem:aec4f0401174d813adcab3dda8ef685c1"><td class="memItemLeft" align="right" valign="top"><a id="aec4f0401174d813adcab3dda8ef685c1"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aec4f0401174d813adcab3dda8ef685c1">PIN_PC12K_PCC_DATA10</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(76)</td></tr>
<tr class="memdesc:aec4f0401174d813adcab3dda8ef685c1"><td class="mdescLeft">&#160;</td><td class="mdescRight">PCC signal: DATA10 on PC12 mux K. <br /></td></tr>
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<tr class="memitem:acb400aca398c2afb05ef368ca8d653e2"><td class="memItemLeft" align="right" valign="top"><a id="acb400aca398c2afb05ef368ca8d653e2"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC12K_PCC_DATA10</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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<tr class="memitem:af3f6727ee621c808edad5c650f13ceae"><td class="memItemLeft" align="right" valign="top"><a id="af3f6727ee621c808edad5c650f13ceae"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC12K_PCC_DATA10</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aec4f0401174d813adcab3dda8ef685c1">PIN_PC12K_PCC_DATA10</a> &lt;&lt; 16) | MUX_PC12K_PCC_DATA10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC12K_PCC_DATA10</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2f6caf0b091dbd3fd30382de37a358db">PIN_PC13K_PCC_DATA11</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(77)</td></tr>
<tr class="memdesc:a2f6caf0b091dbd3fd30382de37a358db"><td class="mdescLeft">&#160;</td><td class="mdescRight">PCC signal: DATA11 on PC13 mux K. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC13K_PCC_DATA11</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC13K_PCC_DATA11</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a2f6caf0b091dbd3fd30382de37a358db">PIN_PC13K_PCC_DATA11</a> &lt;&lt; 16) | MUX_PC13K_PCC_DATA11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC13K_PCC_DATA11</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af1a1cbcbc27cf4cc19ab9270be0166b6">PIN_PC14K_PCC_DATA12</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(78)</td></tr>
<tr class="memdesc:af1a1cbcbc27cf4cc19ab9270be0166b6"><td class="mdescLeft">&#160;</td><td class="mdescRight">PCC signal: DATA12 on PC14 mux K. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC14K_PCC_DATA12</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC14K_PCC_DATA12</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#af1a1cbcbc27cf4cc19ab9270be0166b6">PIN_PC14K_PCC_DATA12</a> &lt;&lt; 16) | MUX_PC14K_PCC_DATA12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC14K_PCC_DATA12</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a82788e2bb85284b088010dc69d7974fd">PIN_PC15K_PCC_DATA13</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(79)</td></tr>
<tr class="memdesc:a82788e2bb85284b088010dc69d7974fd"><td class="mdescLeft">&#160;</td><td class="mdescRight">PCC signal: DATA13 on PC15 mux K. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC15K_PCC_DATA13</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC15K_PCC_DATA13</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a82788e2bb85284b088010dc69d7974fd">PIN_PC15K_PCC_DATA13</a> &lt;&lt; 16) | MUX_PC15K_PCC_DATA13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC15K_PCC_DATA13</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 15)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a95f4299c5d7e1752b1d3f64a2ddd8431">PIN_PA12K_PCC_DEN1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
<tr class="memdesc:a95f4299c5d7e1752b1d3f64a2ddd8431"><td class="mdescLeft">&#160;</td><td class="mdescRight">PCC signal: DEN1 on PA12 mux K. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA12K_PCC_DEN1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA12K_PCC_DEN1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a95f4299c5d7e1752b1d3f64a2ddd8431">PIN_PA12K_PCC_DEN1</a> &lt;&lt; 16) | MUX_PA12K_PCC_DEN1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA12K_PCC_DEN1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad65fb1b287ea3b11963e946d4e014984">PIN_PA13K_PCC_DEN2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
<tr class="memdesc:ad65fb1b287ea3b11963e946d4e014984"><td class="mdescLeft">&#160;</td><td class="mdescRight">PCC signal: DEN2 on PA13 mux K. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA13K_PCC_DEN2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA13K_PCC_DEN2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ad65fb1b287ea3b11963e946d4e014984">PIN_PA13K_PCC_DEN2</a> &lt;&lt; 16) | MUX_PA13K_PCC_DEN2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA13K_PCC_DEN2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7eba67b3fa722743acdea76e2ef27d7a">PIN_PA06I_SDHC0_SDCD</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
<tr class="memdesc:a7eba67b3fa722743acdea76e2ef27d7a"><td class="mdescLeft">&#160;</td><td class="mdescRight">SDHC0 signal: SDCD on PA06 mux I. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA06I_SDHC0_SDCD</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA06I_SDHC0_SDCD</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a7eba67b3fa722743acdea76e2ef27d7a">PIN_PA06I_SDHC0_SDCD</a> &lt;&lt; 16) | MUX_PA06I_SDHC0_SDCD)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA06I_SDHC0_SDCD</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 6)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1652b1b085a562bc8917a81143f0c524">PIN_PA12I_SDHC0_SDCD</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
<tr class="memdesc:a1652b1b085a562bc8917a81143f0c524"><td class="mdescLeft">&#160;</td><td class="mdescRight">SDHC0 signal: SDCD on PA12 mux I. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA12I_SDHC0_SDCD</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA12I_SDHC0_SDCD</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a1652b1b085a562bc8917a81143f0c524">PIN_PA12I_SDHC0_SDCD</a> &lt;&lt; 16) | MUX_PA12I_SDHC0_SDCD)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA12I_SDHC0_SDCD</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6334c9da7c0ecbe7010cd8ed67000f0a">PIN_PB12I_SDHC0_SDCD</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(44)</td></tr>
<tr class="memdesc:a6334c9da7c0ecbe7010cd8ed67000f0a"><td class="mdescLeft">&#160;</td><td class="mdescRight">SDHC0 signal: SDCD on PB12 mux I. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB12I_SDHC0_SDCD</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB12I_SDHC0_SDCD</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a6334c9da7c0ecbe7010cd8ed67000f0a">PIN_PB12I_SDHC0_SDCD</a> &lt;&lt; 16) | MUX_PB12I_SDHC0_SDCD)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB12I_SDHC0_SDCD</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#accbfc26f95777ee4c8ea1dc6d97ef61a">PIN_PC06I_SDHC0_SDCD</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(70)</td></tr>
<tr class="memdesc:accbfc26f95777ee4c8ea1dc6d97ef61a"><td class="mdescLeft">&#160;</td><td class="mdescRight">SDHC0 signal: SDCD on PC06 mux I. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC06I_SDHC0_SDCD</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC06I_SDHC0_SDCD</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#accbfc26f95777ee4c8ea1dc6d97ef61a">PIN_PC06I_SDHC0_SDCD</a> &lt;&lt; 16) | MUX_PC06I_SDHC0_SDCD)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC06I_SDHC0_SDCD</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 6)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2e1cf132f6526c8da6bf172b8c04accb">PIN_PB11I_SDHC0_SDCK</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(43)</td></tr>
<tr class="memdesc:a2e1cf132f6526c8da6bf172b8c04accb"><td class="mdescLeft">&#160;</td><td class="mdescRight">SDHC0 signal: SDCK on PB11 mux I. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB11I_SDHC0_SDCK</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB11I_SDHC0_SDCK</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a2e1cf132f6526c8da6bf172b8c04accb">PIN_PB11I_SDHC0_SDCK</a> &lt;&lt; 16) | MUX_PB11I_SDHC0_SDCK)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB11I_SDHC0_SDCK</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5ce89ff16c8a387ed61286c08b560d2a">PIN_PA08I_SDHC0_SDCMD</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
<tr class="memdesc:a5ce89ff16c8a387ed61286c08b560d2a"><td class="mdescLeft">&#160;</td><td class="mdescRight">SDHC0 signal: SDCMD on PA08 mux I. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA08I_SDHC0_SDCMD</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA08I_SDHC0_SDCMD</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a5ce89ff16c8a387ed61286c08b560d2a">PIN_PA08I_SDHC0_SDCMD</a> &lt;&lt; 16) | MUX_PA08I_SDHC0_SDCMD)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA08I_SDHC0_SDCMD</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a94b8bf2870b540c7230c5cbb19d57802">PIN_PA09I_SDHC0_SDDAT0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
<tr class="memdesc:a94b8bf2870b540c7230c5cbb19d57802"><td class="mdescLeft">&#160;</td><td class="mdescRight">SDHC0 signal: SDDAT0 on PA09 mux I. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA09I_SDHC0_SDDAT0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA09I_SDHC0_SDDAT0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a94b8bf2870b540c7230c5cbb19d57802">PIN_PA09I_SDHC0_SDDAT0</a> &lt;&lt; 16) | MUX_PA09I_SDHC0_SDDAT0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA09I_SDHC0_SDDAT0</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae8ab21367573b32ffbb51adc89e5214c">PIN_PA10I_SDHC0_SDDAT1</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
<tr class="memdesc:ae8ab21367573b32ffbb51adc89e5214c"><td class="mdescLeft">&#160;</td><td class="mdescRight">SDHC0 signal: SDDAT1 on PA10 mux I. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA10I_SDHC0_SDDAT1</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA10I_SDHC0_SDDAT1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ae8ab21367573b32ffbb51adc89e5214c">PIN_PA10I_SDHC0_SDDAT1</a> &lt;&lt; 16) | MUX_PA10I_SDHC0_SDDAT1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA10I_SDHC0_SDDAT1</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac33e3a21859731b4f762debccf27eb3b">PIN_PA11I_SDHC0_SDDAT2</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
<tr class="memdesc:ac33e3a21859731b4f762debccf27eb3b"><td class="mdescLeft">&#160;</td><td class="mdescRight">SDHC0 signal: SDDAT2 on PA11 mux I. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA11I_SDHC0_SDDAT2</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA11I_SDHC0_SDDAT2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ac33e3a21859731b4f762debccf27eb3b">PIN_PA11I_SDHC0_SDDAT2</a> &lt;&lt; 16) | MUX_PA11I_SDHC0_SDDAT2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA11I_SDHC0_SDDAT2</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 11)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8b7b4025892d03890865b8f66bfc1ed6">PIN_PB10I_SDHC0_SDDAT3</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(42)</td></tr>
<tr class="memdesc:a8b7b4025892d03890865b8f66bfc1ed6"><td class="mdescLeft">&#160;</td><td class="mdescRight">SDHC0 signal: SDDAT3 on PB10 mux I. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB10I_SDHC0_SDDAT3</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB10I_SDHC0_SDDAT3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a8b7b4025892d03890865b8f66bfc1ed6">PIN_PB10I_SDHC0_SDDAT3</a> &lt;&lt; 16) | MUX_PB10I_SDHC0_SDDAT3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB10I_SDHC0_SDDAT3</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4c18ee0a78cc6c00542cd0bcb85c55c0">PIN_PA07I_SDHC0_SDWP</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
<tr class="memdesc:a4c18ee0a78cc6c00542cd0bcb85c55c0"><td class="mdescLeft">&#160;</td><td class="mdescRight">SDHC0 signal: SDWP on PA07 mux I. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA07I_SDHC0_SDWP</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA07I_SDHC0_SDWP</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a4c18ee0a78cc6c00542cd0bcb85c55c0">PIN_PA07I_SDHC0_SDWP</a> &lt;&lt; 16) | MUX_PA07I_SDHC0_SDWP)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA07I_SDHC0_SDWP</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aeb8b6ff5f0910a82ee11942744761bb1">PIN_PA13I_SDHC0_SDWP</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
<tr class="memdesc:aeb8b6ff5f0910a82ee11942744761bb1"><td class="mdescLeft">&#160;</td><td class="mdescRight">SDHC0 signal: SDWP on PA13 mux I. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA13I_SDHC0_SDWP</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA13I_SDHC0_SDWP</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aeb8b6ff5f0910a82ee11942744761bb1">PIN_PA13I_SDHC0_SDWP</a> &lt;&lt; 16) | MUX_PA13I_SDHC0_SDWP)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA13I_SDHC0_SDWP</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae23c3fa2b7ace661c286468f5be6a168">PIN_PB13I_SDHC0_SDWP</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(45)</td></tr>
<tr class="memdesc:ae23c3fa2b7ace661c286468f5be6a168"><td class="mdescLeft">&#160;</td><td class="mdescRight">SDHC0 signal: SDWP on PB13 mux I. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB13I_SDHC0_SDWP</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB13I_SDHC0_SDWP</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ae23c3fa2b7ace661c286468f5be6a168">PIN_PB13I_SDHC0_SDWP</a> &lt;&lt; 16) | MUX_PB13I_SDHC0_SDWP)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB13I_SDHC0_SDWP</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a25ca4efebdef34b3f4b89f9856d7fcdf">PIN_PC07I_SDHC0_SDWP</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(71)</td></tr>
<tr class="memdesc:a25ca4efebdef34b3f4b89f9856d7fcdf"><td class="mdescLeft">&#160;</td><td class="mdescRight">SDHC0 signal: SDWP on PC07 mux I. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC07I_SDHC0_SDWP</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC07I_SDHC0_SDWP</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a25ca4efebdef34b3f4b89f9856d7fcdf">PIN_PC07I_SDHC0_SDWP</a> &lt;&lt; 16) | MUX_PC07I_SDHC0_SDWP)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC07I_SDHC0_SDWP</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af7f8904dab20bffa1f795c139f278090">PIN_PB16I_SDHC1_SDCD</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(48)</td></tr>
<tr class="memdesc:af7f8904dab20bffa1f795c139f278090"><td class="mdescLeft">&#160;</td><td class="mdescRight">SDHC1 signal: SDCD on PB16 mux I. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB16I_SDHC1_SDCD</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB16I_SDHC1_SDCD</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#af7f8904dab20bffa1f795c139f278090">PIN_PB16I_SDHC1_SDCD</a> &lt;&lt; 16) | MUX_PB16I_SDHC1_SDCD)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PB16I_SDHC1_SDCD</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 16)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8460a60ab02c33b04a2860ac8c23c8eb">PIN_PC20I_SDHC1_SDCD</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(84)</td></tr>
<tr class="memdesc:a8460a60ab02c33b04a2860ac8c23c8eb"><td class="mdescLeft">&#160;</td><td class="mdescRight">SDHC1 signal: SDCD on PC20 mux I. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PC20I_SDHC1_SDCD</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PC20I_SDHC1_SDCD</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a8460a60ab02c33b04a2860ac8c23c8eb">PIN_PC20I_SDHC1_SDCD</a> &lt;&lt; 16) | MUX_PC20I_SDHC1_SDCD)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PC20I_SDHC1_SDCD</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 20)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a70332e65e672013ce468ce28f4630f13">PIN_PA21I_SDHC1_SDCK</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(21)</td></tr>
<tr class="memdesc:a70332e65e672013ce468ce28f4630f13"><td class="mdescLeft">&#160;</td><td class="mdescRight">SDHC1 signal: SDCK on PA21 mux I. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA21I_SDHC1_SDCK</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA21I_SDHC1_SDCK</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a70332e65e672013ce468ce28f4630f13">PIN_PA21I_SDHC1_SDCK</a> &lt;&lt; 16) | MUX_PA21I_SDHC1_SDCK)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA21I_SDHC1_SDCK</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 21)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6a1fd480bd8adde686c3725e1123a0f4">PIN_PA20I_SDHC1_SDCMD</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(20)</td></tr>
<tr class="memdesc:a6a1fd480bd8adde686c3725e1123a0f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">SDHC1 signal: SDCMD on PA20 mux I. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PA20I_SDHC1_SDCMD</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PA20I_SDHC1_SDCMD</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a6a1fd480bd8adde686c3725e1123a0f4">PIN_PA20I_SDHC1_SDCMD</a> &lt;&lt; 16) | MUX_PA20I_SDHC1_SDCMD)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PORT_PA20I_SDHC1_SDCMD</b>&#160;&#160;&#160;(<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) &lt;&lt; 20)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2902ffa452bb5c02771369f1d2730828">PIN_PB18I_SDHC1_SDDAT0</a>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(50)</td></tr>
<tr class="memdesc:a2902ffa452bb5c02771369f1d2730828"><td class="mdescLeft">&#160;</td><td class="mdescRight">SDHC1 signal: SDDAT0 on PB18 mux I. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>MUX_PB18I_SDHC1_SDDAT0</b>&#160;&#160;&#160;<a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB18I_SDHC1_SDDAT0</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#a2902ffa452bb5c02771369f1d2730828">PIN_PB18I_SDHC1_SDDAT0</a> &lt;&lt; 16) | MUX_PB18I_SDHC1_SDDAT0)</td></tr>
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<tr class="memdesc:aa096f5ec84f5c11fa5d23a9499c7d7cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">SDHC1 signal: SDDAT1 on PB19 mux I. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB19I_SDHC1_SDDAT1</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#aa096f5ec84f5c11fa5d23a9499c7d7cc">PIN_PB19I_SDHC1_SDDAT1</a> &lt;&lt; 16) | MUX_PB19I_SDHC1_SDDAT1)</td></tr>
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<tr class="memdesc:ad3017802d2f20dd1450cc1f59516b09a"><td class="mdescLeft">&#160;</td><td class="mdescRight">SDHC1 signal: SDDAT2 on PB20 mux I. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB20I_SDHC1_SDDAT2</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#ad3017802d2f20dd1450cc1f59516b09a">PIN_PB20I_SDHC1_SDDAT2</a> &lt;&lt; 16) | MUX_PB20I_SDHC1_SDDAT2)</td></tr>
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<tr class="memdesc:afa203efc0446dfae5ae9f1f6317e7cbf"><td class="mdescLeft">&#160;</td><td class="mdescRight">SDHC1 signal: SDDAT3 on PB21 mux I. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PINMUX_PB21I_SDHC1_SDDAT3</b>&#160;&#160;&#160;((<a class="el" href="pio_2same54p20a_8h.html#afa203efc0446dfae5ae9f1f6317e7cbf">PIN_PB21I_SDHC1_SDDAT3</a> &lt;&lt; 16) | MUX_PB21I_SDHC1_SDDAT3)</td></tr>
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<tr class="memdesc:a1ca123636104f6a92cacf8cde3bd768d"><td class="mdescLeft">&#160;</td><td class="mdescRight">SDHC1 signal: SDWP on PB17 mux I. <br /></td></tr>
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<tr class="memdesc:a077cc951218cd28cf6b68a7877a8b111"><td class="mdescLeft">&#160;</td><td class="mdescRight">SDHC1 signal: SDWP on PC21 mux I. <br /></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>Peripheral I/O description for SAME54N20A. </p>
<p>Copyright (c) 2019 Microchip Technology Inc.</p>
<p>\asf_license_start </p>
<p class="definition">Definition in file <a class="el" href="pio_2same54n20a_8h_source.html">same54n20a.h</a>.</p>
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