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334 lines
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334 lines
16 KiB
HTML
4 years ago
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<html lang="en">
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<head>
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<title>MIPS DSP Built-in Functions - Using the GNU Compiler Collection (GCC)</title>
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<meta http-equiv="Content-Type" content="text/html">
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<meta name="description" content="Using the GNU Compiler Collection (GCC)">
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<meta name="generator" content="makeinfo 4.13">
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<link title="Top" rel="start" href="index.html#Top">
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<link rel="up" href="Target-Builtins.html#Target-Builtins" title="Target Builtins">
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<link rel="prev" href="FR_002dV-Built_002din-Functions.html#FR_002dV-Built_002din-Functions" title="FR-V Built-in Functions">
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<link rel="next" href="MIPS-Paired_002dSingle-Support.html#MIPS-Paired_002dSingle-Support" title="MIPS Paired-Single Support">
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<link href="http://www.gnu.org/software/texinfo/" rel="generator-home" title="Texinfo Homepage">
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Copyright (C) 1988-2015 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.3 or
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any later version published by the Free Software Foundation; with the
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Invariant Sections being ``Funding Free Software'', the Front-Cover
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(see below). A copy of the license is included in the section entitled
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``GNU Free Documentation License''.
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(a) The FSF's Front-Cover Text is:
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A GNU Manual
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(b) The FSF's Back-Cover Text is:
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You have freedom to copy and modify this GNU Manual, like GNU
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</head>
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<body>
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<div class="node">
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<a name="MIPS-DSP-Built-in-Functions"></a>
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<a name="MIPS-DSP-Built_002din-Functions"></a>
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<p>
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Next: <a rel="next" accesskey="n" href="MIPS-Paired_002dSingle-Support.html#MIPS-Paired_002dSingle-Support">MIPS Paired-Single Support</a>,
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Previous: <a rel="previous" accesskey="p" href="FR_002dV-Built_002din-Functions.html#FR_002dV-Built_002din-Functions">FR-V Built-in Functions</a>,
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Up: <a rel="up" accesskey="u" href="Target-Builtins.html#Target-Builtins">Target Builtins</a>
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<hr>
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</div>
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<h4 class="subsection">6.58.12 MIPS DSP Built-in Functions</h4>
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<p>The MIPS DSP Application-Specific Extension (ASE) includes new
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instructions that are designed to improve the performance of DSP and
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media applications. It provides instructions that operate on packed
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8-bit/16-bit integer data, Q7, Q15 and Q31 fractional data.
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<p>GCC supports MIPS DSP operations using both the generic
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vector extensions (see <a href="Vector-Extensions.html#Vector-Extensions">Vector Extensions</a>) and a collection of
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MIPS-specific built-in functions. Both kinds of support are
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enabled by the <samp><span class="option">-mdsp</span></samp> command-line option.
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<p>Revision 2 of the ASE was introduced in the second half of 2006.
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This revision adds extra instructions to the original ASE, but is
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otherwise backwards-compatible with it. You can select revision 2
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using the command-line option <samp><span class="option">-mdspr2</span></samp>; this option implies
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<samp><span class="option">-mdsp</span></samp>.
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<p>The SCOUNT and POS bits of the DSP control register are global. The
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WRDSP, EXTPDP, EXTPDPV and MTHLIP instructions modify the SCOUNT and
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POS bits. During optimization, the compiler does not delete these
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instructions and it does not delete calls to functions containing
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these instructions.
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<p>At present, GCC only provides support for operations on 32-bit
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vectors. The vector type associated with 8-bit integer data is
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usually called <code>v4i8</code>, the vector type associated with Q7
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is usually called <code>v4q7</code>, the vector type associated with 16-bit
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integer data is usually called <code>v2i16</code>, and the vector type
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associated with Q15 is usually called <code>v2q15</code>. They can be
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defined in C as follows:
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<pre class="smallexample"> typedef signed char v4i8 __attribute__ ((vector_size(4)));
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typedef signed char v4q7 __attribute__ ((vector_size(4)));
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typedef short v2i16 __attribute__ ((vector_size(4)));
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typedef short v2q15 __attribute__ ((vector_size(4)));
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</pre>
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<p><code>v4i8</code>, <code>v4q7</code>, <code>v2i16</code> and <code>v2q15</code> values are
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initialized in the same way as aggregates. For example:
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<pre class="smallexample"> v4i8 a = {1, 2, 3, 4};
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v4i8 b;
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b = (v4i8) {5, 6, 7, 8};
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v2q15 c = {0x0fcb, 0x3a75};
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v2q15 d;
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d = (v2q15) {0.1234 * 0x1.0p15, 0.4567 * 0x1.0p15};
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</pre>
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<p><em>Note:</em> The CPU's endianness determines the order in which values
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are packed. On little-endian targets, the first value is the least
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significant and the last value is the most significant. The opposite
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order applies to big-endian targets. For example, the code above
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sets the lowest byte of <code>a</code> to <code>1</code> on little-endian targets
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and <code>4</code> on big-endian targets.
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<p><em>Note:</em> Q7, Q15 and Q31 values must be initialized with their integer
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representation. As shown in this example, the integer representation
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of a Q7 value can be obtained by multiplying the fractional value by
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<code>0x1.0p7</code>. The equivalent for Q15 values is to multiply by
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<code>0x1.0p15</code>. The equivalent for Q31 values is to multiply by
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<code>0x1.0p31</code>.
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<p>The table below lists the <code>v4i8</code> and <code>v2q15</code> operations for which
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hardware support exists. <code>a</code> and <code>b</code> are <code>v4i8</code> values,
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and <code>c</code> and <code>d</code> are <code>v2q15</code> values.
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<p><table summary=""><tr align="left"><td valign="top" width="50%">C code </td><td valign="top" width="50%">MIPS instruction
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<br></td></tr><tr align="left"><td valign="top" width="50%"><code>a + b</code> </td><td valign="top" width="50%"><code>addu.qb</code>
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<br></td></tr><tr align="left"><td valign="top" width="50%"><code>c + d</code> </td><td valign="top" width="50%"><code>addq.ph</code>
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<br></td></tr><tr align="left"><td valign="top" width="50%"><code>a - b</code> </td><td valign="top" width="50%"><code>subu.qb</code>
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<br></td></tr><tr align="left"><td valign="top" width="50%"><code>c - d</code> </td><td valign="top" width="50%"><code>subq.ph</code>
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<br></td></tr></table>
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<p>The table below lists the <code>v2i16</code> operation for which
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hardware support exists for the DSP ASE REV 2. <code>e</code> and <code>f</code> are
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<code>v2i16</code> values.
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<p><table summary=""><tr align="left"><td valign="top" width="50%">C code </td><td valign="top" width="50%">MIPS instruction
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<br></td></tr><tr align="left"><td valign="top" width="50%"><code>e * f</code> </td><td valign="top" width="50%"><code>mul.ph</code>
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<br></td></tr></table>
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<p>It is easier to describe the DSP built-in functions if we first define
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the following types:
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<pre class="smallexample"> typedef int q31;
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typedef int i32;
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typedef unsigned int ui32;
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typedef long long a64;
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</pre>
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<p><code>q31</code> and <code>i32</code> are actually the same as <code>int</code>, but we
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use <code>q31</code> to indicate a Q31 fractional value and <code>i32</code> to
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indicate a 32-bit integer value. Similarly, <code>a64</code> is the same as
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<code>long long</code>, but we use <code>a64</code> to indicate values that are
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placed in one of the four DSP accumulators (<code>$ac0</code>,
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<code>$ac1</code>, <code>$ac2</code> or <code>$ac3</code>).
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<p>Also, some built-in functions prefer or require immediate numbers as
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parameters, because the corresponding DSP instructions accept both immediate
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numbers and register operands, or accept immediate numbers only. The
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immediate parameters are listed as follows.
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<pre class="smallexample"> imm0_3: 0 to 3.
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imm0_7: 0 to 7.
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imm0_15: 0 to 15.
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imm0_31: 0 to 31.
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imm0_63: 0 to 63.
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imm0_255: 0 to 255.
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imm_n32_31: -32 to 31.
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imm_n512_511: -512 to 511.
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</pre>
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<p>The following built-in functions map directly to a particular MIPS DSP
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instruction. Please refer to the architecture specification
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for details on what each instruction does.
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<pre class="smallexample"> v2q15 __builtin_mips_addq_ph (v2q15, v2q15)
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v2q15 __builtin_mips_addq_s_ph (v2q15, v2q15)
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q31 __builtin_mips_addq_s_w (q31, q31)
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v4i8 __builtin_mips_addu_qb (v4i8, v4i8)
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v4i8 __builtin_mips_addu_s_qb (v4i8, v4i8)
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v2q15 __builtin_mips_subq_ph (v2q15, v2q15)
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v2q15 __builtin_mips_subq_s_ph (v2q15, v2q15)
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q31 __builtin_mips_subq_s_w (q31, q31)
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v4i8 __builtin_mips_subu_qb (v4i8, v4i8)
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v4i8 __builtin_mips_subu_s_qb (v4i8, v4i8)
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i32 __builtin_mips_addsc (i32, i32)
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i32 __builtin_mips_addwc (i32, i32)
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i32 __builtin_mips_modsub (i32, i32)
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i32 __builtin_mips_raddu_w_qb (v4i8)
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v2q15 __builtin_mips_absq_s_ph (v2q15)
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q31 __builtin_mips_absq_s_w (q31)
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v4i8 __builtin_mips_precrq_qb_ph (v2q15, v2q15)
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v2q15 __builtin_mips_precrq_ph_w (q31, q31)
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v2q15 __builtin_mips_precrq_rs_ph_w (q31, q31)
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v4i8 __builtin_mips_precrqu_s_qb_ph (v2q15, v2q15)
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q31 __builtin_mips_preceq_w_phl (v2q15)
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q31 __builtin_mips_preceq_w_phr (v2q15)
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v2q15 __builtin_mips_precequ_ph_qbl (v4i8)
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v2q15 __builtin_mips_precequ_ph_qbr (v4i8)
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v2q15 __builtin_mips_precequ_ph_qbla (v4i8)
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v2q15 __builtin_mips_precequ_ph_qbra (v4i8)
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v2q15 __builtin_mips_preceu_ph_qbl (v4i8)
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v2q15 __builtin_mips_preceu_ph_qbr (v4i8)
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v2q15 __builtin_mips_preceu_ph_qbla (v4i8)
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v2q15 __builtin_mips_preceu_ph_qbra (v4i8)
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v4i8 __builtin_mips_shll_qb (v4i8, imm0_7)
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v4i8 __builtin_mips_shll_qb (v4i8, i32)
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v2q15 __builtin_mips_shll_ph (v2q15, imm0_15)
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v2q15 __builtin_mips_shll_ph (v2q15, i32)
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v2q15 __builtin_mips_shll_s_ph (v2q15, imm0_15)
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v2q15 __builtin_mips_shll_s_ph (v2q15, i32)
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q31 __builtin_mips_shll_s_w (q31, imm0_31)
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q31 __builtin_mips_shll_s_w (q31, i32)
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v4i8 __builtin_mips_shrl_qb (v4i8, imm0_7)
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v4i8 __builtin_mips_shrl_qb (v4i8, i32)
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v2q15 __builtin_mips_shra_ph (v2q15, imm0_15)
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v2q15 __builtin_mips_shra_ph (v2q15, i32)
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v2q15 __builtin_mips_shra_r_ph (v2q15, imm0_15)
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v2q15 __builtin_mips_shra_r_ph (v2q15, i32)
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q31 __builtin_mips_shra_r_w (q31, imm0_31)
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q31 __builtin_mips_shra_r_w (q31, i32)
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v2q15 __builtin_mips_muleu_s_ph_qbl (v4i8, v2q15)
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v2q15 __builtin_mips_muleu_s_ph_qbr (v4i8, v2q15)
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v2q15 __builtin_mips_mulq_rs_ph (v2q15, v2q15)
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q31 __builtin_mips_muleq_s_w_phl (v2q15, v2q15)
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q31 __builtin_mips_muleq_s_w_phr (v2q15, v2q15)
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a64 __builtin_mips_dpau_h_qbl (a64, v4i8, v4i8)
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a64 __builtin_mips_dpau_h_qbr (a64, v4i8, v4i8)
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a64 __builtin_mips_dpsu_h_qbl (a64, v4i8, v4i8)
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a64 __builtin_mips_dpsu_h_qbr (a64, v4i8, v4i8)
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a64 __builtin_mips_dpaq_s_w_ph (a64, v2q15, v2q15)
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a64 __builtin_mips_dpaq_sa_l_w (a64, q31, q31)
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a64 __builtin_mips_dpsq_s_w_ph (a64, v2q15, v2q15)
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a64 __builtin_mips_dpsq_sa_l_w (a64, q31, q31)
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a64 __builtin_mips_mulsaq_s_w_ph (a64, v2q15, v2q15)
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a64 __builtin_mips_maq_s_w_phl (a64, v2q15, v2q15)
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a64 __builtin_mips_maq_s_w_phr (a64, v2q15, v2q15)
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a64 __builtin_mips_maq_sa_w_phl (a64, v2q15, v2q15)
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a64 __builtin_mips_maq_sa_w_phr (a64, v2q15, v2q15)
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i32 __builtin_mips_bitrev (i32)
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i32 __builtin_mips_insv (i32, i32)
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v4i8 __builtin_mips_repl_qb (imm0_255)
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v4i8 __builtin_mips_repl_qb (i32)
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v2q15 __builtin_mips_repl_ph (imm_n512_511)
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v2q15 __builtin_mips_repl_ph (i32)
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void __builtin_mips_cmpu_eq_qb (v4i8, v4i8)
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void __builtin_mips_cmpu_lt_qb (v4i8, v4i8)
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void __builtin_mips_cmpu_le_qb (v4i8, v4i8)
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i32 __builtin_mips_cmpgu_eq_qb (v4i8, v4i8)
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i32 __builtin_mips_cmpgu_lt_qb (v4i8, v4i8)
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i32 __builtin_mips_cmpgu_le_qb (v4i8, v4i8)
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void __builtin_mips_cmp_eq_ph (v2q15, v2q15)
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void __builtin_mips_cmp_lt_ph (v2q15, v2q15)
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void __builtin_mips_cmp_le_ph (v2q15, v2q15)
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v4i8 __builtin_mips_pick_qb (v4i8, v4i8)
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v2q15 __builtin_mips_pick_ph (v2q15, v2q15)
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|
|
v2q15 __builtin_mips_packrl_ph (v2q15, v2q15)
|
||
|
|
i32 __builtin_mips_extr_w (a64, imm0_31)
|
||
|
|
i32 __builtin_mips_extr_w (a64, i32)
|
||
|
|
i32 __builtin_mips_extr_r_w (a64, imm0_31)
|
||
|
|
i32 __builtin_mips_extr_s_h (a64, i32)
|
||
|
|
i32 __builtin_mips_extr_rs_w (a64, imm0_31)
|
||
|
|
i32 __builtin_mips_extr_rs_w (a64, i32)
|
||
|
|
i32 __builtin_mips_extr_s_h (a64, imm0_31)
|
||
|
|
i32 __builtin_mips_extr_r_w (a64, i32)
|
||
|
|
i32 __builtin_mips_extp (a64, imm0_31)
|
||
|
|
i32 __builtin_mips_extp (a64, i32)
|
||
|
|
i32 __builtin_mips_extpdp (a64, imm0_31)
|
||
|
|
i32 __builtin_mips_extpdp (a64, i32)
|
||
|
|
a64 __builtin_mips_shilo (a64, imm_n32_31)
|
||
|
|
a64 __builtin_mips_shilo (a64, i32)
|
||
|
|
a64 __builtin_mips_mthlip (a64, i32)
|
||
|
|
void __builtin_mips_wrdsp (i32, imm0_63)
|
||
|
|
i32 __builtin_mips_rddsp (imm0_63)
|
||
|
|
i32 __builtin_mips_lbux (void *, i32)
|
||
|
|
i32 __builtin_mips_lhx (void *, i32)
|
||
|
|
i32 __builtin_mips_lwx (void *, i32)
|
||
|
|
a64 __builtin_mips_ldx (void *, i32) [MIPS64 only]
|
||
|
|
i32 __builtin_mips_bposge32 (void)
|
||
|
|
a64 __builtin_mips_madd (a64, i32, i32);
|
||
|
|
a64 __builtin_mips_maddu (a64, ui32, ui32);
|
||
|
|
a64 __builtin_mips_msub (a64, i32, i32);
|
||
|
|
a64 __builtin_mips_msubu (a64, ui32, ui32);
|
||
|
|
a64 __builtin_mips_mult (i32, i32);
|
||
|
|
a64 __builtin_mips_multu (ui32, ui32);
|
||
|
|
</pre>
|
||
|
|
<p>The following built-in functions map directly to a particular MIPS DSP REV 2
|
||
|
|
instruction. Please refer to the architecture specification
|
||
|
|
for details on what each instruction does.
|
||
|
|
|
||
|
|
<pre class="smallexample"> v4q7 __builtin_mips_absq_s_qb (v4q7);
|
||
|
|
v2i16 __builtin_mips_addu_ph (v2i16, v2i16);
|
||
|
|
v2i16 __builtin_mips_addu_s_ph (v2i16, v2i16);
|
||
|
|
v4i8 __builtin_mips_adduh_qb (v4i8, v4i8);
|
||
|
|
v4i8 __builtin_mips_adduh_r_qb (v4i8, v4i8);
|
||
|
|
i32 __builtin_mips_append (i32, i32, imm0_31);
|
||
|
|
i32 __builtin_mips_balign (i32, i32, imm0_3);
|
||
|
|
i32 __builtin_mips_cmpgdu_eq_qb (v4i8, v4i8);
|
||
|
|
i32 __builtin_mips_cmpgdu_lt_qb (v4i8, v4i8);
|
||
|
|
i32 __builtin_mips_cmpgdu_le_qb (v4i8, v4i8);
|
||
|
|
a64 __builtin_mips_dpa_w_ph (a64, v2i16, v2i16);
|
||
|
|
a64 __builtin_mips_dps_w_ph (a64, v2i16, v2i16);
|
||
|
|
v2i16 __builtin_mips_mul_ph (v2i16, v2i16);
|
||
|
|
v2i16 __builtin_mips_mul_s_ph (v2i16, v2i16);
|
||
|
|
q31 __builtin_mips_mulq_rs_w (q31, q31);
|
||
|
|
v2q15 __builtin_mips_mulq_s_ph (v2q15, v2q15);
|
||
|
|
q31 __builtin_mips_mulq_s_w (q31, q31);
|
||
|
|
a64 __builtin_mips_mulsa_w_ph (a64, v2i16, v2i16);
|
||
|
|
v4i8 __builtin_mips_precr_qb_ph (v2i16, v2i16);
|
||
|
|
v2i16 __builtin_mips_precr_sra_ph_w (i32, i32, imm0_31);
|
||
|
|
v2i16 __builtin_mips_precr_sra_r_ph_w (i32, i32, imm0_31);
|
||
|
|
i32 __builtin_mips_prepend (i32, i32, imm0_31);
|
||
|
|
v4i8 __builtin_mips_shra_qb (v4i8, imm0_7);
|
||
|
|
v4i8 __builtin_mips_shra_r_qb (v4i8, imm0_7);
|
||
|
|
v4i8 __builtin_mips_shra_qb (v4i8, i32);
|
||
|
|
v4i8 __builtin_mips_shra_r_qb (v4i8, i32);
|
||
|
|
v2i16 __builtin_mips_shrl_ph (v2i16, imm0_15);
|
||
|
|
v2i16 __builtin_mips_shrl_ph (v2i16, i32);
|
||
|
|
v2i16 __builtin_mips_subu_ph (v2i16, v2i16);
|
||
|
|
v2i16 __builtin_mips_subu_s_ph (v2i16, v2i16);
|
||
|
|
v4i8 __builtin_mips_subuh_qb (v4i8, v4i8);
|
||
|
|
v4i8 __builtin_mips_subuh_r_qb (v4i8, v4i8);
|
||
|
|
v2q15 __builtin_mips_addqh_ph (v2q15, v2q15);
|
||
|
|
v2q15 __builtin_mips_addqh_r_ph (v2q15, v2q15);
|
||
|
|
q31 __builtin_mips_addqh_w (q31, q31);
|
||
|
|
q31 __builtin_mips_addqh_r_w (q31, q31);
|
||
|
|
v2q15 __builtin_mips_subqh_ph (v2q15, v2q15);
|
||
|
|
v2q15 __builtin_mips_subqh_r_ph (v2q15, v2q15);
|
||
|
|
q31 __builtin_mips_subqh_w (q31, q31);
|
||
|
|
q31 __builtin_mips_subqh_r_w (q31, q31);
|
||
|
|
a64 __builtin_mips_dpax_w_ph (a64, v2i16, v2i16);
|
||
|
|
a64 __builtin_mips_dpsx_w_ph (a64, v2i16, v2i16);
|
||
|
|
a64 __builtin_mips_dpaqx_s_w_ph (a64, v2q15, v2q15);
|
||
|
|
a64 __builtin_mips_dpaqx_sa_w_ph (a64, v2q15, v2q15);
|
||
|
|
a64 __builtin_mips_dpsqx_s_w_ph (a64, v2q15, v2q15);
|
||
|
|
a64 __builtin_mips_dpsqx_sa_w_ph (a64, v2q15, v2q15);
|
||
|
|
</pre>
|
||
|
|
</body></html>
|
||
|
|
|