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220 lines
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HTML
4 years ago
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<title>IA-64 Options - Using the GNU Compiler Collection (GCC)</title>
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<meta name="description" content="Using the GNU Compiler Collection (GCC)">
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<link title="Top" rel="start" href="index.html#Top">
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<link rel="up" href="Submodel-Options.html#Submodel-Options" title="Submodel Options">
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<link rel="prev" href="HPPA-Options.html#HPPA-Options" title="HPPA Options">
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<link rel="next" href="LM32-Options.html#LM32-Options" title="LM32 Options">
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.3 or
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any later version published by the Free Software Foundation; with the
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Invariant Sections being ``Funding Free Software'', the Front-Cover
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(see below). A copy of the license is included in the section entitled
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``GNU Free Documentation License''.
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(a) The FSF's Front-Cover Text is:
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A GNU Manual
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(b) The FSF's Back-Cover Text is:
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<body>
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<div class="node">
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<a name="IA-64-Options"></a>
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<a name="IA_002d64-Options"></a>
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<p>
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Next: <a rel="next" accesskey="n" href="LM32-Options.html#LM32-Options">LM32 Options</a>,
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Previous: <a rel="previous" accesskey="p" href="HPPA-Options.html#HPPA-Options">HPPA Options</a>,
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Up: <a rel="up" accesskey="u" href="Submodel-Options.html#Submodel-Options">Submodel Options</a>
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<hr>
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</div>
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<h4 class="subsection">3.17.17 IA-64 Options</h4>
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<p><a name="index-IA_002d64-Options-1724"></a>
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These are the ‘<samp><span class="samp">-m</span></samp>’ options defined for the Intel IA-64 architecture.
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<dl>
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<dt><code>-mbig-endian</code><dd><a name="index-mbig_002dendian-1725"></a>Generate code for a big-endian target. This is the default for HP-UX.
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<br><dt><code>-mlittle-endian</code><dd><a name="index-mlittle_002dendian-1726"></a>Generate code for a little-endian target. This is the default for AIX5
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and GNU/Linux.
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<br><dt><code>-mgnu-as</code><dt><code>-mno-gnu-as</code><dd><a name="index-mgnu_002das-1727"></a><a name="index-mno_002dgnu_002das-1728"></a>Generate (or don't) code for the GNU assembler. This is the default.
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<!-- Also, this is the default if the configure option @option{-with-gnu-as} -->
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<!-- is used. -->
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<br><dt><code>-mgnu-ld</code><dt><code>-mno-gnu-ld</code><dd><a name="index-mgnu_002dld-1729"></a><a name="index-mno_002dgnu_002dld-1730"></a>Generate (or don't) code for the GNU linker. This is the default.
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<!-- Also, this is the default if the configure option @option{-with-gnu-ld} -->
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<!-- is used. -->
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<br><dt><code>-mno-pic</code><dd><a name="index-mno_002dpic-1731"></a>Generate code that does not use a global pointer register. The result
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is not position independent code, and violates the IA-64 ABI.
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<br><dt><code>-mvolatile-asm-stop</code><dt><code>-mno-volatile-asm-stop</code><dd><a name="index-mvolatile_002dasm_002dstop-1732"></a><a name="index-mno_002dvolatile_002dasm_002dstop-1733"></a>Generate (or don't) a stop bit immediately before and after volatile asm
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statements.
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<br><dt><code>-mregister-names</code><dt><code>-mno-register-names</code><dd><a name="index-mregister_002dnames-1734"></a><a name="index-mno_002dregister_002dnames-1735"></a>Generate (or don't) ‘<samp><span class="samp">in</span></samp>’, ‘<samp><span class="samp">loc</span></samp>’, and ‘<samp><span class="samp">out</span></samp>’ register names for
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the stacked registers. This may make assembler output more readable.
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<br><dt><code>-mno-sdata</code><dt><code>-msdata</code><dd><a name="index-mno_002dsdata-1736"></a><a name="index-msdata-1737"></a>Disable (or enable) optimizations that use the small data section. This may
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be useful for working around optimizer bugs.
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<br><dt><code>-mconstant-gp</code><dd><a name="index-mconstant_002dgp-1738"></a>Generate code that uses a single constant global pointer value. This is
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useful when compiling kernel code.
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<br><dt><code>-mauto-pic</code><dd><a name="index-mauto_002dpic-1739"></a>Generate code that is self-relocatable. This implies <samp><span class="option">-mconstant-gp</span></samp>.
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This is useful when compiling firmware code.
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<br><dt><code>-minline-float-divide-min-latency</code><dd><a name="index-minline_002dfloat_002ddivide_002dmin_002dlatency-1740"></a>Generate code for inline divides of floating-point values
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using the minimum latency algorithm.
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<br><dt><code>-minline-float-divide-max-throughput</code><dd><a name="index-minline_002dfloat_002ddivide_002dmax_002dthroughput-1741"></a>Generate code for inline divides of floating-point values
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using the maximum throughput algorithm.
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<br><dt><code>-mno-inline-float-divide</code><dd><a name="index-mno_002dinline_002dfloat_002ddivide-1742"></a>Do not generate inline code for divides of floating-point values.
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<br><dt><code>-minline-int-divide-min-latency</code><dd><a name="index-minline_002dint_002ddivide_002dmin_002dlatency-1743"></a>Generate code for inline divides of integer values
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using the minimum latency algorithm.
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<br><dt><code>-minline-int-divide-max-throughput</code><dd><a name="index-minline_002dint_002ddivide_002dmax_002dthroughput-1744"></a>Generate code for inline divides of integer values
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using the maximum throughput algorithm.
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<br><dt><code>-mno-inline-int-divide</code><dd><a name="index-mno_002dinline_002dint_002ddivide-1745"></a>Do not generate inline code for divides of integer values.
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<br><dt><code>-minline-sqrt-min-latency</code><dd><a name="index-minline_002dsqrt_002dmin_002dlatency-1746"></a>Generate code for inline square roots
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using the minimum latency algorithm.
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<br><dt><code>-minline-sqrt-max-throughput</code><dd><a name="index-minline_002dsqrt_002dmax_002dthroughput-1747"></a>Generate code for inline square roots
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using the maximum throughput algorithm.
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<br><dt><code>-mno-inline-sqrt</code><dd><a name="index-mno_002dinline_002dsqrt-1748"></a>Do not generate inline code for <code>sqrt</code>.
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<br><dt><code>-mfused-madd</code><dt><code>-mno-fused-madd</code><dd><a name="index-mfused_002dmadd-1749"></a><a name="index-mno_002dfused_002dmadd-1750"></a>Do (don't) generate code that uses the fused multiply/add or multiply/subtract
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instructions. The default is to use these instructions.
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<br><dt><code>-mno-dwarf2-asm</code><dt><code>-mdwarf2-asm</code><dd><a name="index-mno_002ddwarf2_002dasm-1751"></a><a name="index-mdwarf2_002dasm-1752"></a>Don't (or do) generate assembler code for the DWARF 2 line number debugging
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info. This may be useful when not using the GNU assembler.
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<br><dt><code>-mearly-stop-bits</code><dt><code>-mno-early-stop-bits</code><dd><a name="index-mearly_002dstop_002dbits-1753"></a><a name="index-mno_002dearly_002dstop_002dbits-1754"></a>Allow stop bits to be placed earlier than immediately preceding the
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instruction that triggered the stop bit. This can improve instruction
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scheduling, but does not always do so.
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<br><dt><code>-mfixed-range=</code><var>register-range</var><dd><a name="index-mfixed_002drange-1755"></a>Generate code treating the given register range as fixed registers.
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A fixed register is one that the register allocator cannot use. This is
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useful when compiling kernel code. A register range is specified as
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two registers separated by a dash. Multiple register ranges can be
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specified separated by a comma.
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<br><dt><code>-mtls-size=</code><var>tls-size</var><dd><a name="index-mtls_002dsize-1756"></a>Specify bit size of immediate TLS offsets. Valid values are 14, 22, and
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64.
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<br><dt><code>-mtune=</code><var>cpu-type</var><dd><a name="index-mtune-1757"></a>Tune the instruction scheduling for a particular CPU, Valid values are
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‘<samp><span class="samp">itanium</span></samp>’, ‘<samp><span class="samp">itanium1</span></samp>’, ‘<samp><span class="samp">merced</span></samp>’, ‘<samp><span class="samp">itanium2</span></samp>’,
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and ‘<samp><span class="samp">mckinley</span></samp>’.
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<br><dt><code>-milp32</code><dt><code>-mlp64</code><dd><a name="index-milp32-1758"></a><a name="index-mlp64-1759"></a>Generate code for a 32-bit or 64-bit environment.
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The 32-bit environment sets int, long and pointer to 32 bits.
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The 64-bit environment sets int to 32 bits and long and pointer
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to 64 bits. These are HP-UX specific flags.
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<br><dt><code>-mno-sched-br-data-spec</code><dt><code>-msched-br-data-spec</code><dd><a name="index-mno_002dsched_002dbr_002ddata_002dspec-1760"></a><a name="index-msched_002dbr_002ddata_002dspec-1761"></a>(Dis/En)able data speculative scheduling before reload.
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This results in generation of <code>ld.a</code> instructions and
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the corresponding check instructions (<code>ld.c</code> / <code>chk.a</code>).
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The default is 'disable'.
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<br><dt><code>-msched-ar-data-spec</code><dt><code>-mno-sched-ar-data-spec</code><dd><a name="index-msched_002dar_002ddata_002dspec-1762"></a><a name="index-mno_002dsched_002dar_002ddata_002dspec-1763"></a>(En/Dis)able data speculative scheduling after reload.
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This results in generation of <code>ld.a</code> instructions and
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the corresponding check instructions (<code>ld.c</code> / <code>chk.a</code>).
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The default is 'enable'.
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<br><dt><code>-mno-sched-control-spec</code><dt><code>-msched-control-spec</code><dd><a name="index-mno_002dsched_002dcontrol_002dspec-1764"></a><a name="index-msched_002dcontrol_002dspec-1765"></a>(Dis/En)able control speculative scheduling. This feature is
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available only during region scheduling (i.e. before reload).
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This results in generation of the <code>ld.s</code> instructions and
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the corresponding check instructions <code>chk.s</code>.
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The default is 'disable'.
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<br><dt><code>-msched-br-in-data-spec</code><dt><code>-mno-sched-br-in-data-spec</code><dd><a name="index-msched_002dbr_002din_002ddata_002dspec-1766"></a><a name="index-mno_002dsched_002dbr_002din_002ddata_002dspec-1767"></a>(En/Dis)able speculative scheduling of the instructions that
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are dependent on the data speculative loads before reload.
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This is effective only with <samp><span class="option">-msched-br-data-spec</span></samp> enabled.
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The default is 'enable'.
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<br><dt><code>-msched-ar-in-data-spec</code><dt><code>-mno-sched-ar-in-data-spec</code><dd><a name="index-msched_002dar_002din_002ddata_002dspec-1768"></a><a name="index-mno_002dsched_002dar_002din_002ddata_002dspec-1769"></a>(En/Dis)able speculative scheduling of the instructions that
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are dependent on the data speculative loads after reload.
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This is effective only with <samp><span class="option">-msched-ar-data-spec</span></samp> enabled.
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The default is 'enable'.
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<br><dt><code>-msched-in-control-spec</code><dt><code>-mno-sched-in-control-spec</code><dd><a name="index-msched_002din_002dcontrol_002dspec-1770"></a><a name="index-mno_002dsched_002din_002dcontrol_002dspec-1771"></a>(En/Dis)able speculative scheduling of the instructions that
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are dependent on the control speculative loads.
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This is effective only with <samp><span class="option">-msched-control-spec</span></samp> enabled.
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The default is 'enable'.
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<br><dt><code>-mno-sched-prefer-non-data-spec-insns</code><dt><code>-msched-prefer-non-data-spec-insns</code><dd><a name="index-mno_002dsched_002dprefer_002dnon_002ddata_002dspec_002dinsns-1772"></a><a name="index-msched_002dprefer_002dnon_002ddata_002dspec_002dinsns-1773"></a>If enabled, data-speculative instructions are chosen for schedule
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only if there are no other choices at the moment. This makes
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the use of the data speculation much more conservative.
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The default is 'disable'.
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<br><dt><code>-mno-sched-prefer-non-control-spec-insns</code><dt><code>-msched-prefer-non-control-spec-insns</code><dd><a name="index-mno_002dsched_002dprefer_002dnon_002dcontrol_002dspec_002dinsns-1774"></a><a name="index-msched_002dprefer_002dnon_002dcontrol_002dspec_002dinsns-1775"></a>If enabled, control-speculative instructions are chosen for schedule
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only if there are no other choices at the moment. This makes
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the use of the control speculation much more conservative.
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The default is 'disable'.
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<br><dt><code>-mno-sched-count-spec-in-critical-path</code><dt><code>-msched-count-spec-in-critical-path</code><dd><a name="index-mno_002dsched_002dcount_002dspec_002din_002dcritical_002dpath-1776"></a><a name="index-msched_002dcount_002dspec_002din_002dcritical_002dpath-1777"></a>If enabled, speculative dependencies are considered during
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computation of the instructions priorities. This makes the use of the
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speculation a bit more conservative.
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The default is 'disable'.
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<br><dt><code>-msched-spec-ldc</code><dd><a name="index-msched_002dspec_002dldc-1778"></a>Use a simple data speculation check. This option is on by default.
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<br><dt><code>-msched-control-spec-ldc</code><dd><a name="index-msched_002dspec_002dldc-1779"></a>Use a simple check for control speculation. This option is on by default.
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<br><dt><code>-msched-stop-bits-after-every-cycle</code><dd><a name="index-msched_002dstop_002dbits_002dafter_002devery_002dcycle-1780"></a>Place a stop bit after every cycle when scheduling. This option is on
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by default.
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<br><dt><code>-msched-fp-mem-deps-zero-cost</code><dd><a name="index-msched_002dfp_002dmem_002ddeps_002dzero_002dcost-1781"></a>Assume that floating-point stores and loads are not likely to cause a conflict
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when placed into the same instruction group. This option is disabled by
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default.
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<br><dt><code>-msel-sched-dont-check-control-spec</code><dd><a name="index-msel_002dsched_002ddont_002dcheck_002dcontrol_002dspec-1782"></a>Generate checks for control speculation in selective scheduling.
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This flag is disabled by default.
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<br><dt><code>-msched-max-memory-insns=</code><var>max-insns</var><dd><a name="index-msched_002dmax_002dmemory_002dinsns-1783"></a>Limit on the number of memory insns per instruction group, giving lower
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priority to subsequent memory insns attempting to schedule in the same
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instruction group. Frequently useful to prevent cache bank conflicts.
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The default value is 1.
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<br><dt><code>-msched-max-memory-insns-hard-limit</code><dd><a name="index-msched_002dmax_002dmemory_002dinsns_002dhard_002dlimit-1784"></a>Makes the limit specified by <samp><span class="option">msched-max-memory-insns</span></samp> a hard limit,
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disallowing more than that number in an instruction group.
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Otherwise, the limit is “soft”, meaning that non-memory operations
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are preferred when the limit is reached, but memory operations may still
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be scheduled.
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</dl>
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</body></html>
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