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ePenguin-Software-Framework/arch/arm/SAMD21/SAMD21L/samd21l/atdf/ATSAMD21G16L.atdf

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the monkey dances and laughs and sings and dances
4 years ago
<?xml version="1.0" encoding="UTF-8"?>
<!--
Copyright (c) 2018 Microchip Technology Inc.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
-->
<avr-tools-device-file xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" schema-version="4.3.1" xsi:noNamespaceSchemaLocation="../../schema/avr_tools_device_file.xsd">
<file timestamp="2019-11-25T06:55:57Z"/>
<variants xmlns:mhc="http://www.atmel.com/schemas/avr-tools-device-file/mhc">
<variant ordercode="SAMD21G16L-MU" mhc:ordercode="ATSAMD21G16L-MU" package="QFN48" pinout="SAMD21G1xL" speedmax="48000000" tempmin="-40" tempmax="85" vccmin="1.62" vccmax="3.63"/>
<variant ordercode="SAMD21G16L-MN" mhc:ordercode="ATSAMD21G16L-MN" package="QFN48" pinout="SAMD21G1xL" speedmax="48000000" tempmin="-40" tempmax="105" vccmin="1.62" vccmax="3.63"/>
</variants>
<devices>
<device name="ATSAMD21G16L" architecture="CORTEX-M0PLUS" family="SAMD" series="SAMD21">
<address-spaces>
<address-space id="base" name="base" start="0" size="0x100000000" endianness="little">
<memory-segment name="FLASH" start="0x00000000" size="0x10000" type="flash" pagesize="64" rw="RW" exec="true"/>
<memory-segment name="AUX0" start="0x00804000" size="0x100" type="fuses" pagesize="64" rw="RW"/>
<memory-segment name="AUX1" start="0x00806000" size="0x100" type="fuses" pagesize="64" rw="RW"/>
<memory-segment name="AUX3" start="0x0080A000" size="0x100" type="fuses" pagesize="64" rw="RW"/>
<memory-segment name="OTP1" start="0x00806000" size="0x8" type="fuses" rw="R"/>
<memory-segment name="OTP2" start="0x00806008" size="0x8" type="fuses" rw="R"/>
<memory-segment name="OTP4" start="0x00806020" size="0xE0" type="fuses" pagesize="64" rw="RW"/>
<memory-segment name="TEMP_LOG" start="0x00806030" size="0x8" type="fuses" rw="R"/>
<memory-segment name="USER_PAGE" start="0x00804000" size="0x100" type="user_page" pagesize="64" rw="RW"/>
<memory-segment name="RWW" start="0x00400000" size="0x800" type="flash" pagesize="64" rw="RW" exec="true"/>
<memory-segment name="HMCRAMC0" start="0x20000000" size="0x2000" type="ram" rw="RW" exec="true"/>
<memory-segment name="HPB0" start="0x40000000" size="0x10000" type="io" rw="RW"/>
<memory-segment name="HPB1" start="0x41000000" size="0x10000" type="io" rw="RW"/>
<memory-segment name="HPB2" start="0x42000000" size="0x10000" type="io" rw="RW"/>
<memory-segment name="PPB" start="0xE0000000" size="0x100000" type="io" rw="RW"/>
<memory-segment name="SCS" start="0xE000E000" size="0x00001000" type="io" rw="RW"/>
<memory-segment name="PERIPHERALS" start="0x40000000" size="0x20000000" type="io" rw="RW"/>
</address-space>
<address-space id="fuses" name="fuses" start="0x00000000" size="0x20000000" endianness="little"/>
</address-spaces>
<parameters>
<param name="NUM_IRQ" value="29" caption="Number of Interrupt Requests"/>
<param name="__CM0PLUS_REV" value="0x0001" caption="Cortex-M0+ Core Revision"/>
<param name="__MPU_PRESENT" value="0" caption="MPU present or not"/>
<param name="__NVIC_PRIO_BITS" value="2" caption="Number of Bits used for Priority Levels"/>
<param name="__VTOR_PRESENT" value="1" caption="Vector Table Offset Register present or not"/>
<param name="__Vendor_SysTickConfig" value="0" caption="Set to 1 if different SysTick Config is used"/>
<param name="__ARCH_ARM" value="1"/>
<param name="__ARCH_ARM_CORTEX_M" value="1"/>
<param name="__DEVICE_IS_SAM" value="1"/>
</parameters>
<peripherals>
<module name="AC" id="U2205" version="1.1.2">
<instance name="AC">
<register-group name="AC" name-in-module="AC" address-space="base" offset="0x42004400"/>
<signals>
<signal group="AIN" index="0" function="B" pad="PA04"/>
<signal group="AIN" index="1" function="B" pad="PA05"/>
<signal group="AIN" index="2" function="B" pad="PA06"/>
<signal group="AIN" index="3" function="B" pad="PA07"/>
<signal group="CMP" index="0" function="H" pad="PA12"/>
<signal group="CMP" index="0" function="H" pad="PA18"/>
<signal group="CMP" index="1" function="H" pad="PA13"/>
<signal group="CMP" index="1" function="H" pad="PA19"/>
</signals>
<parameters>
<param name="CMP_NUM" value="2" caption="Number of comparators"/>
<param name="GCLK_ID_ANA" value="32" caption="Index of Generic Clock for analog"/>
<param name="GCLK_ID_DIG" value="31" caption="Index of Generic Clock for digital"/>
<param name="NUM_CMP" value="2"/>
<param name="PAIRS" value="1" caption="Number of pairs of comparators"/>
<param name="INSTANCE_ID" value="81"/>
</parameters>
</instance>
<instance name="AC1">
<register-group name="AC1" name-in-module="AC" address-space="base" offset="0x42005400"/>
<signals>
<signal group="AIN" index="0" function="B" pad="PB04"/>
<signal group="AIN" index="1" function="B" pad="PB05"/>
<signal group="AIN" index="2" function="B" pad="PB02"/>
<signal group="AIN" index="3" function="B" pad="PB03"/>
<signal group="CMP" index="0" function="H" pad="PA24"/>
<signal group="CMP" index="1" function="H" pad="PA25"/>
</signals>
<parameters>
<param name="CMP_NUM" value="2" caption="Number of comparators"/>
<param name="GCLK_ID_ANA" value="32" caption="Index of Generic Clock for analog"/>
<param name="GCLK_ID_DIG" value="31" caption="Index of Generic Clock for digital"/>
<param name="NUM_CMP" value="2"/>
<param name="PAIRS" value="1" caption="Number of pairs of comparators"/>
<param name="INSTANCE_ID" value="85"/>
</parameters>
</instance>
</module>
<module name="ADC" id="U2204" version="1.2.0">
<instance name="ADC">
<register-group name="ADC" name-in-module="ADC" address-space="base" offset="0x42004000"/>
<signals>
<signal group="AIN" index="0" function="B" pad="PA02"/>
<signal group="AIN" index="1" function="B" pad="PA03"/>
<signal group="AIN" index="2" function="B" pad="PB08"/>
<signal group="AIN" index="3" function="B" pad="PB09"/>
<signal group="AIN" index="4" function="B" pad="PA04"/>
<signal group="AIN" index="5" function="B" pad="PA05"/>
<signal group="AIN" index="6" function="B" pad="PA06"/>
<signal group="AIN" index="7" function="B" pad="PA07"/>
<signal group="AIN" index="8" function="B" pad="PB00"/>
<signal group="AIN" index="9" function="B" pad="PB01"/>
<signal group="AIN" index="10" function="B" pad="PB02"/>
<signal group="AIN" index="11" function="B" pad="PB03"/>
<signal group="AIN" index="12" function="B" pad="PB04"/>
<signal group="AIN" index="13" function="B" pad="PB05"/>
<signal group="AIN" index="16" function="B" pad="PA08"/>
<signal group="AIN" index="17" function="B" pad="PA09"/>
<signal group="AIN" index="18" function="B" pad="PA10"/>
<signal group="AIN" index="19" function="B" pad="PA11"/>
<signal group="VREFP" function="B" pad="PA04"/>
</signals>
<parameters>
<param name="DMAC_ID_RESRDY" value="39" caption="Index of DMA RESRDY trigger"/>
<param name="EXTCHANNEL_MSB" value="19" caption="Number of external channels"/>
<param name="GCLK_ID" value="30" caption="Index of Generic Clock"/>
<param name="RESULT_BITS" value="16" caption="Size of RESULT.RESULT bitfield"/>
<param name="RESULT_MSB" value="15" caption="Size of Result"/>
<param name="INSTANCE_ID" value="80"/>
</parameters>
</instance>
</module>
<module name="DAC" id="U2214" version="1.1.0">
<instance name="DAC">
<register-group name="DAC" name-in-module="DAC" address-space="base" offset="0x42004800"/>
<signals>
<signal group="VOUT" function="B" pad="PA02"/>
<signal group="VREFP" function="B" pad="PA03"/>
</signals>
<parameters>
<param name="DMAC_ID_EMPTY" value="40" caption="Index of DMAC EMPTY trigger"/>
<param name="GCLK_ID" value="33" caption="Index of Generic Clock"/>
<param name="INSTANCE_ID" value="82"/>
</parameters>
</instance>
</module>
<module name="DMAC" id="U2223" version="1.1.0">
<instance name="DMAC">
<register-group name="DMAC" name-in-module="DMAC" address-space="base" offset="0x41004800"/>
<parameters>
<param name="CH_BITS" value="4" caption="Number of bits to select channel"/>
<param name="CH_NUM" value="12" caption="Number of channels"/>
<param name="EVIN_NUM" value="4" caption="Number of input events"/>
<param name="EVOUT_NUM" value="4" caption="Number of output events"/>
<param name="LVL_BITS" value="2" caption="Number of bit to select level priority"/>
<param name="LVL_NUM" value="4" caption="Enable priority level number"/>
<param name="TRIG_BITS" value="6" caption="Number of bits to select trigger source"/>
<param name="TRIG_NUM" value="45" caption="Number of peripheral triggers"/>
<param name="INSTANCE_ID" value="36"/>
</parameters>
</instance>
</module>
<module name="DSU" id="U2209" version="2.0.3">
<instance name="DSU">
<register-group name="DSU" name-in-module="DSU" address-space="base" offset="0x41002000"/>
<parameters>
<param name="INSTANCE_ID" value="33"/>
</parameters>
</instance>
</module>
<module name="EIC" id="U2217" version="1.0.1">
<instance name="EIC">
<register-group name="EIC" name-in-module="EIC" address-space="base" offset="0x40001800"/>
<signals>
<signal group="EXTINT" index="0" function="A" pad="PA16"/>
<signal group="EXTINT" index="0" function="A" pad="PB00"/>
<signal group="EXTINT" index="1" function="A" pad="PA17"/>
<signal group="EXTINT" index="1" function="A" pad="PB01"/>
<signal group="EXTINT" index="2" function="A" pad="PA02"/>
<signal group="EXTINT" index="2" function="A" pad="PA18"/>
<signal group="EXTINT" index="2" function="A" pad="PB02"/>
<signal group="EXTINT" index="3" function="A" pad="PA03"/>
<signal group="EXTINT" index="3" function="A" pad="PA19"/>
<signal group="EXTINT" index="3" function="A" pad="PB03"/>
<signal group="EXTINT" index="4" function="A" pad="PA04"/>
<signal group="EXTINT" index="4" function="A" pad="PA20"/>
<signal group="EXTINT" index="4" function="A" pad="PB04"/>
<signal group="EXTINT" index="5" function="A" pad="PA05"/>
<signal group="EXTINT" index="5" function="A" pad="PA21"/>
<signal group="EXTINT" index="5" function="A" pad="PB05"/>
<signal group="EXTINT" index="6" function="A" pad="PA06"/>
<signal group="EXTINT" index="6" function="A" pad="PA22"/>
<signal group="EXTINT" index="7" function="A" pad="PA07"/>
<signal group="EXTINT" index="7" function="A" pad="PA23"/>
<signal group="EXTINT" index="8" function="A" pad="PA28"/>
<signal group="EXTINT" index="8" function="A" pad="PB08"/>
<signal group="EXTINT" index="9" function="A" pad="PA09"/>
<signal group="EXTINT" index="9" function="A" pad="PB09"/>
<signal group="EXTINT" index="10" function="A" pad="PA10"/>
<signal group="EXTINT" index="10" function="A" pad="PA30"/>
<signal group="EXTINT" index="10" function="A" pad="PB10"/>
<signal group="EXTINT" index="11" function="A" pad="PA11"/>
<signal group="EXTINT" index="11" function="A" pad="PA31"/>
<signal group="EXTINT" index="11" function="A" pad="PB11"/>
<signal group="EXTINT" index="12" function="A" pad="PA12"/>
<signal group="EXTINT" index="12" function="A" pad="PA24"/>
<signal group="EXTINT" index="13" function="A" pad="PA13"/>
<signal group="EXTINT" index="13" function="A" pad="PA25"/>
<signal group="EXTINT" index="14" function="A" pad="PA14"/>
<signal group="EXTINT" index="15" function="A" pad="PA27"/>
<signal group="EXTINT" index="15" function="A" pad="PA15"/>
<signal group="NMI" function="A" pad="PA08"/>
</signals>
<parameters>
<param name="CONFIG_NUM" value="2" caption="Number of CONFIG registers"/>
<param name="EXTINT_NUM" value="16" caption="Number of External Interrupts"/>
<param name="GCLK_ID" value="5" caption="Index of Generic Clock"/>
<param name="INSTANCE_ID" value="6"/>
</parameters>
</instance>
</module>
<module name="EVSYS" id="U2208" version="1.0.1">
<instance name="EVSYS">
<register-group name="EVSYS" name-in-module="EVSYS" address-space="base" offset="0x42000400"/>
<parameters>
<param name="CHANNELS" value="12" caption="Number of Channels"/>
<param name="CHANNELS_BITS" value="4" caption="Number of bits to select Channel"/>
<param name="CHANNELS_MSB" value="11" caption="Number of Channels - 1"/>
<param name="EXTEVT_NUM" value="0" caption="Number of External Event Generators"/>
<param name="GCLK_ID_0" value="7" caption="Index of Generic Clock 0"/>
<param name="GCLK_ID_1" value="8" caption="Index of Generic Clock 1"/>
<param name="GCLK_ID_2" value="9" caption="Index of Generic Clock 2"/>
<param name="GCLK_ID_3" value="10" caption="Index of Generic Clock 3"/>
<param name="GCLK_ID_4" value="11" caption="Index of Generic Clock 4"/>
<param name="GCLK_ID_5" value="12" caption="Index of Generic Clock 5"/>
<param name="GCLK_ID_6" value="13" caption="Index of Generic Clock 6"/>
<param name="GCLK_ID_7" value="14" caption="Index of Generic Clock 7"/>
<param name="GCLK_ID_8" value="15" caption="Index of Generic Clock 8"/>
<param name="GCLK_ID_9" value="16" caption="Index of Generic Clock 9"/>
<param name="GCLK_ID_10" value="17" caption="Index of Generic Clock 10"/>
<param name="GCLK_ID_11" value="18" caption="Index of Generic Clock 11"/>
<param name="GENERATORS" value="76" caption="Total Number of Event Generators"/>
<param name="GENERATORS_BITS" value="7" caption="Number of bits to select Event Generator"/>
<param name="USERS" value="31" caption="Total Number of Event Users"/>
<param name="USERS_BITS" value="5" caption="Number of bits to select Event User"/>
<param name="INSTANCE_ID" value="65"/>
</parameters>
</instance>
</module>
<module name="GCLK" id="U2102" version="2.1.0">
<instance name="GCLK">
<register-group name="GCLK" name-in-module="GCLK" address-space="base" offset="0x40000C00"/>
<signals>
<signal group="IO" index="0" function="H" pad="PA14"/>
<signal group="IO" index="0" function="H" pad="PA27"/>
<signal group="IO" index="0" function="H" pad="PA28"/>
<signal group="IO" index="0" function="H" pad="PA30"/>
<signal group="IO" index="1" function="H" pad="PA15"/>
<signal group="IO" index="2" function="H" pad="PA16"/>
<signal group="IO" index="3" function="H" pad="PA17"/>
<signal group="IO" index="4" function="H" pad="PA10"/>
<signal group="IO" index="4" function="H" pad="PA20"/>
<signal group="IO" index="4" function="H" pad="PB10"/>
<signal group="IO" index="5" function="H" pad="PA11"/>
<signal group="IO" index="5" function="H" pad="PA21"/>
<signal group="IO" index="5" function="H" pad="PB11"/>
<signal group="IO" index="6" function="H" pad="PA22"/>
<signal group="IO" index="7" function="H" pad="PA23"/>
</signals>
<parameters>
<param name="GENDIV_BITS" value="16"/>
<param name="GEN_NUM" value="9" caption="Number of Generic Clock Generators"/>
<param name="GEN_NUM_MSB" value="8" caption="Number of Generic Clock Generators - 1"/>
<param name="GEN_SOURCE_NUM_MSB" value="8" caption="Number of Generic Clock Sources - 1"/>
<param name="NUM" value="37" caption="Number of Generic Clock Users"/>
<param name="SOURCE_DFLL48M" value="7" caption="DFLL48M output"/>
<param name="SOURCE_DPLL96M" value="8" caption="DPLL96M output"/>
<param name="SOURCE_GCLKGEN1" value="2" caption="Generic clock generator 1 output"/>
<param name="SOURCE_GCLKIN" value="1" caption="Generator input pad"/>
<param name="SOURCE_NUM" value="9" caption="Number of Generic Clock Sources"/>
<param name="SOURCE_OSCULP32K" value="3" caption="OSCULP32K oscillator output"/>
<param name="SOURCE_OSC8M" value="6" caption="OSC8M oscillator output"/>
<param name="SOURCE_OSC32K" value="4" caption="OSC32K oscillator outpur"/>
<param name="SOURCE_XOSC" value="0" caption="XOSC oscillator output"/>
<param name="SOURCE_XOSC32K" value="5" caption="XOSC32K oscillator output"/>
<param name="INSTANCE_ID" value="3"/>
</parameters>
</instance>
</module>
<module name="HMATRIXB" id="I7638" version="2.1.2">
<instance name="SBMATRIX">
<register-group name="SBMATRIX" name-in-module="HMATRIXB" address-space="base" offset="0x41007000"/>
<parameters>
<param name="MASTER_NUM" value="3"/>
<param name="MASTER_CM0PLUS" value="0"/>
<param name="MASTER_DSU" value="1"/>
<param name="MASTER_DMAC" value="2"/>
<param name="SLAVE_NUM" value="7"/>
<param name="SLAVE_FLASH" value="0"/>
<param name="SLAVE_HPB0" value="1"/>
<param name="SLAVE_HPB1" value="2"/>
<param name="SLAVE_HPB2" value="3"/>
<param name="SLAVE_HMCRAMC0" value="4"/>
<param name="SLAVE_HMCRAMC0_ALT0" value="5"/>
<param name="SLAVE_HMCRAMC0_ALT1" value="6"/>
<param name="INSTANCE_ID" value="39"/>
</parameters>
</instance>
</module>
<module name="MTB" id="U2002" version="1.0.0">
<instance name="MTB">
<register-group name="MTB" name-in-module="MTB" address-space="base" offset="0x41006000"/>
<parameters>
<param name="INSTANCE_ID" value="38"/>
</parameters>
</instance>
</module>
<module name="NVMCTRL" id="U2207" version="2.0.2">
<instance name="NVMCTRL">
<register-group name="NVMCTRL" name-in-module="NVMCTRL" address-space="base" offset="0x41004000"/>
<signals>
<signal group="MARGIN" function="default" pad="VMARGIN"/>
</signals>
<parameters>
<param name="FACTORY_WORD_IMPLEMENTED_MASK" value="0xC0000007FFFFFFFF"/>
<param name="PMSB" value="3"/>
<param name="PSZ_BITS" value="6"/>
<param name="ROW_PAGES" value="4"/>
<param name="USER_PAGE_OFFSET" value="0x00800000"/>
<param name="USER_WORD_IMPLEMENTED_MASK" value="0xC01FFFFFFFFFFFFF"/>
<param name="RWWEE_PAGES" value="32" caption="Number of pages in the WWR EEPROM area"/>
<param name="RWWEE_ROW_SIZE" value="256"/>
<param name="RWW_EEPROM_ADDR" value="0x00400000" caption="Start address of the WWR EEPROM area"/>
<param name="RWW_EEPROM_SIZE" value="2048" caption="Byte size of the WWR EEPROM area"/>
<param name="FLASH_SIZE" value="65536"/>
<param name="PAGE_SIZE" value="64"/>
<param name="PAGES" value="1024"/>
<param name="PAGES_PR_REGION" value="64"/>
<param name="ROW_SIZE" value="256"/>
<!-- From Datasheet section "Electrical Characteristics","Flash Characteristics" table "Maximum operating Frequency" -->
<param name="PSM_0_FRMFW_FWS_1_MAX_FREQ" value="12000000"/>
<param name="PSM_0_FRMLP_FWS_0_MAX_FREQ" value="18000000"/>
<param name="PSM_0_FRMLP_FWS_1_MAX_FREQ" value="36000000"/>
<param name="PSM_0_FRMHS_FWS_0_MAX_FREQ" value="25000000"/>
<param name="PSM_0_FRMHS_FWS_1_MAX_FREQ" value="50000000"/>
<param name="PSM_1_FRMFW_FWS_1_MAX_FREQ" value="12000000"/>
<param name="PSM_1_FRMLP_FWS_0_MAX_FREQ" value="8000000"/>
<param name="PSM_1_FRMLP_FWS_1_MAX_FREQ" value="12000000"/>
<param name="INSTANCE_ID" value="34"/>
</parameters>
</instance>
</module>
<module name="FUSES" id="U2207" version="2.0.2">
<instance name="FUSES">
<register-group name="AUX3_FUSES" name-in-module="AUX3_FUSES" address-space="fuses" offset="0x0080A000"/>
<register-group name="OTP4_FUSES" name-in-module="OTP4_FUSES" address-space="fuses" offset="0x00806020"/>
<register-group name="TEMP_LOG_FUSES" name-in-module="TEMP_LOG_FUSES" address-space="fuses" offset="0x00806030"/>
<register-group name="USER_FUSES" name-in-module="USER_FUSES" address-space="fuses" offset="0x00804000"/>
</instance>
</module>
<module name="PAC" id="U2211" version="1.0.1">
<instance name="PAC0">
<register-group name="PAC0" name-in-module="PAC" address-space="base" offset="0x40000000"/>
<parameters>
<param name="WPROT_DEFAULT_VAL" value="0x00000000" caption="PAC protection mask at reset"/>
<param name="INSTANCE_ID" value="0"/>
</parameters>
</instance>
<instance name="PAC1">
<register-group name="PAC1" name-in-module="PAC" address-space="base" offset="0x41000000"/>
<parameters>
<param name="WPROT_DEFAULT_VAL" value="0x00000002" caption="PAC protection mask at reset"/>
<param name="INSTANCE_ID" value="32"/>
</parameters>
</instance>
<instance name="PAC2">
<register-group name="PAC2" name-in-module="PAC" address-space="base" offset="0x42000000"/>
<parameters>
<param name="WPROT_DEFAULT_VAL" value="0x00800000" caption="PAC protection mask at reset"/>
<param name="INSTANCE_ID" value="64"/>
</parameters>
</instance>
</module>
<module name="PM" id="U2206" version="2.1.2">
<instance name="PM">
<register-group name="PM" name-in-module="PM" address-space="base" offset="0x40000400"/>
<signals>
<signal group="RESET_N" function="default" pad="RESET_N"/>
</signals>
<parameters>
<param name="CTRL_MCSEL_DFLL48M" value="3"/>
<param name="CTRL_MCSEL_GCLK" value="0"/>
<param name="CTRL_MCSEL_OSC8M" value="1"/>
<param name="CTRL_MCSEL_XOSC" value="2"/>
<param name="PM_CLK_APB_NUM" value="2"/>
<param name="INSTANCE_ID" value="1"/>
</parameters>
<clock-groups>
<clock-group name="AHB" grouporder="0">
<clock name="HPB0" bit="0"/>
<clock name="HPB1" bit="1"/>
<clock name="HPB2" bit="2"/>
<clock name="DSU" bit="3"/>
<clock name="NVMCTRL" bit="4"/>
<clock name="DMAC" bit="5"/>
</clock-group>
</clock-groups>
</instance>
</module>
<module name="PORT" id="U2210" version="1.0.0">
<instance name="PORT">
<register-group name="PORT" name-in-module="PORT" address-space="base" offset="0x41004400"/>
<register-group name="PORT_IOBUS" name-in-module="PORT" address-space="base" offset="0x60000000"/>
<signals>
<signal group="P" index="2" function="default" pad="PA02"/>
<signal group="P" index="3" function="default" pad="PA03"/>
<signal group="P" index="4" function="default" pad="PA04"/>
<signal group="P" index="5" function="default" pad="PA05"/>
<signal group="P" index="6" function="default" pad="PA06"/>
<signal group="P" index="7" function="default" pad="PA07"/>
<signal group="P" index="8" function="default" pad="PA08"/>
<signal group="P" index="9" function="default" pad="PA09"/>
<signal group="P" index="10" function="default" pad="PA10"/>
<signal group="P" index="11" function="default" pad="PA11"/>
<signal group="P" index="12" function="default" pad="PA12"/>
<signal group="P" index="13" function="default" pad="PA13"/>
<signal group="P" index="14" function="default" pad="PA14"/>
<signal group="P" index="15" function="default" pad="PA15"/>
<signal group="P" index="16" function="default" pad="PA16"/>
<signal group="P" index="17" function="default" pad="PA17"/>
<signal group="P" index="18" function="default" pad="PA18"/>
<signal group="P" index="19" function="default" pad="PA19"/>
<signal group="P" index="20" function="default" pad="PA20"/>
<signal group="P" index="21" function="default" pad="PA21"/>
<signal group="P" index="22" function="default" pad="PA22"/>
<signal group="P" index="23" function="default" pad="PA23"/>
<signal group="P" index="24" function="default" pad="PA24"/>
<signal group="P" index="25" function="default" pad="PA25"/>
<signal group="P" index="27" function="default" pad="PA27"/>
<signal group="P" index="28" function="default" pad="PA28"/>
<signal group="P" index="30" function="default" pad="PA30"/>
<signal group="P" index="31" function="default" pad="PA31"/>
<signal group="P" index="32" function="default" pad="PB00"/>
<signal group="P" index="33" function="default" pad="PB01"/>
<signal group="P" index="34" function="default" pad="PB02"/>
<signal group="P" index="35" function="default" pad="PB03"/>
<signal group="P" index="36" function="default" pad="PB04"/>
<signal group="P" index="37" function="default" pad="PB05"/>
<signal group="P" index="40" function="default" pad="PB08"/>
<signal group="P" index="41" function="default" pad="PB09"/>
<signal group="P" index="42" function="default" pad="PB10"/>
<signal group="P" index="43" function="default" pad="PB11"/>
</signals>
<parameters>
<param name="BITS" value="64" caption="Number of PORT pins"/>
<param name="DRVSTR" value="1" caption="DRVSTR supported"/>
<param name="GROUPS" value="2" caption="Number of 32-bit PORT groups"/>
<param name="ODRAIN" value="0" caption="ODRAIN supported"/>
<param name="SLEWLIM" value="0" caption="SLEWLIM supported"/>
<param name="INSTANCE_ID" value="35"/>
</parameters>
</instance>
</module>
<module name="RTC" id="U2202" version="1.0.1">
<instance name="RTC">
<register-group name="RTC" name-in-module="RTC" address-space="base" offset="0x40001400"/>
<parameters>
<param name="ALARM_NUM" value="1" caption="Number of Alarms"/>
<param name="COMP16_NUM" value="2" caption="Number of 16-bit Comparators"/>
<param name="COMP32_NUM" value="1" caption="Number of 32-bit Comparators"/>
<param name="GCLK_ID" value="4" caption="Index of Generic Clock"/>
<param name="NUM_OF_ALARMS" value="1" caption="Number of Alarms (obsolete)"/>
<param name="NUM_OF_COMP16" value="2" caption="Number of 16-bit Comparators (obsolete)"/>
<param name="NUM_OF_COMP32" value="1" caption="Number of 32-bit Comparators (obsolete)"/>
<param name="INSTANCE_ID" value="5"/>
</parameters>
</instance>
</module>
<module name="SERCOM" id="U2201" version="2.2.0">
<instance name="SERCOM0">
<register-group name="SERCOM0" name-in-module="SERCOM" address-space="base" offset="0x42000800"/>
<signals>
<signal group="PAD" index="0" function="D" pad="PA04"/>
<signal group="PAD" index="0" function="C" pad="PA08"/>
<signal group="PAD" index="1" function="D" pad="PA05"/>
<signal group="PAD" index="1" function="C" pad="PA09"/>
<signal group="PAD" index="2" function="D" pad="PA06"/>
<signal group="PAD" index="2" function="C" pad="PA10"/>
<signal group="PAD" index="3" function="D" pad="PA07"/>
<signal group="PAD" index="3" function="C" pad="PA11"/>
</signals>
<parameters>
<param name="DMAC_ID_RX" value="1" caption="Index of DMA RX trigger"/>
<param name="DMAC_ID_TX" value="2" caption="Index of DMA TX trigger"/>
<param name="GCLK_ID_CORE" value="20" caption="Index of Generic Clock for Core"/>
<param name="GCLK_ID_SLOW" value="19" caption="Index of Generic Clock for SMbus timeout"/>
<param name="INT_MSB" value="6"/>
<param name="INSTANCE_ID" value="66"/>
</parameters>
</instance>
<instance name="SERCOM1">
<register-group name="SERCOM1" name-in-module="SERCOM" address-space="base" offset="0x42000C00"/>
<signals>
<signal group="PAD" index="0" function="C" pad="PA16"/>
<signal group="PAD" index="1" function="C" pad="PA17"/>
<signal group="PAD" index="2" function="D" pad="PA30"/>
<signal group="PAD" index="2" function="C" pad="PA18"/>
<signal group="PAD" index="3" function="D" pad="PA31"/>
<signal group="PAD" index="3" function="C" pad="PA19"/>
</signals>
<parameters>
<param name="DMAC_ID_RX" value="3" caption="Index of DMA RX trigger"/>
<param name="DMAC_ID_TX" value="4" caption="Index of DMA TX trigger"/>
<param name="GCLK_ID_CORE" value="21" caption="Index of Generic Clock for Core"/>
<param name="GCLK_ID_SLOW" value="19" caption="Index of Generic Clock for SMbus timeout"/>
<param name="INT_MSB" value="6"/>
<param name="INSTANCE_ID" value="67"/>
</parameters>
</instance>
<instance name="SERCOM2">
<register-group name="SERCOM2" name-in-module="SERCOM" address-space="base" offset="0x42001000"/>
<signals>
<signal group="PAD" index="0" function="D" pad="PA08"/>
<signal group="PAD" index="0" function="C" pad="PA12"/>
<signal group="PAD" index="1" function="D" pad="PA09"/>
<signal group="PAD" index="1" function="C" pad="PA13"/>
<signal group="PAD" index="2" function="D" pad="PA10"/>
<signal group="PAD" index="2" function="C" pad="PA14"/>
<signal group="PAD" index="3" function="D" pad="PA11"/>
<signal group="PAD" index="3" function="C" pad="PA15"/>
</signals>
<parameters>
<param name="DMAC_ID_RX" value="5" caption="Index of DMA RX trigger"/>
<param name="DMAC_ID_TX" value="6" caption="Index of DMA TX trigger"/>
<param name="GCLK_ID_CORE" value="22" caption="Index of Generic Clock for Core"/>
<param name="GCLK_ID_SLOW" value="19" caption="Index of Generic Clock for SMbus timeout"/>
<param name="INT_MSB" value="6"/>
<param name="INSTANCE_ID" value="68"/>
</parameters>
</instance>
<instance name="SERCOM3">
<register-group name="SERCOM3" name-in-module="SERCOM" address-space="base" offset="0x42001400"/>
<signals>
<signal group="PAD" index="0" function="D" pad="PA16"/>
<signal group="PAD" index="0" function="C" pad="PA22"/>
<signal group="PAD" index="1" function="D" pad="PA17"/>
<signal group="PAD" index="1" function="C" pad="PA23"/>
<signal group="PAD" index="2" function="D" pad="PA18"/>
<signal group="PAD" index="2" function="D" pad="PA20"/>
<signal group="PAD" index="2" function="C" pad="PA24"/>
<signal group="PAD" index="3" function="D" pad="PA19"/>
<signal group="PAD" index="3" function="D" pad="PA21"/>
<signal group="PAD" index="3" function="C" pad="PA25"/>
</signals>
<parameters>
<param name="DMAC_ID_RX" value="7" caption="Index of DMA RX trigger"/>
<param name="DMAC_ID_TX" value="8" caption="Index of DMA TX trigger"/>
<param name="GCLK_ID_CORE" value="23" caption="Index of Generic Clock for Core"/>
<param name="GCLK_ID_SLOW" value="19" caption="Index of Generic Clock for SMbus timeout"/>
<param name="INT_MSB" value="6"/>
<param name="INSTANCE_ID" value="69"/>
</parameters>
</instance>
<instance name="SERCOM4">
<register-group name="SERCOM4" name-in-module="SERCOM" address-space="base" offset="0x42001800"/>
<signals>
<signal group="PAD" index="0" function="D" pad="PA12"/>
<signal group="PAD" index="0" function="D" pad="PB08"/>
<signal group="PAD" index="1" function="D" pad="PA13"/>
<signal group="PAD" index="1" function="D" pad="PB09"/>
<signal group="PAD" index="2" function="D" pad="PA14"/>
<signal group="PAD" index="2" function="D" pad="PB10"/>
<signal group="PAD" index="3" function="D" pad="PA15"/>
<signal group="PAD" index="3" function="D" pad="PB11"/>
</signals>
<parameters>
<param name="DMAC_ID_RX" value="9" caption="Index of DMA RX trigger"/>
<param name="DMAC_ID_TX" value="10" caption="Index of DMA TX trigger"/>
<param name="GCLK_ID_CORE" value="24" caption="Index of Generic Clock for Core"/>
<param name="GCLK_ID_SLOW" value="19" caption="Index of Generic Clock for SMbus timeout"/>
<param name="INT_MSB" value="6"/>
<param name="INSTANCE_ID" value="70"/>
</parameters>
</instance>
<instance name="SERCOM5">
<register-group name="SERCOM5" name-in-module="SERCOM" address-space="base" offset="0x42001C00"/>
<signals>
<signal group="PAD" index="0" function="D" pad="PA22"/>
<signal group="PAD" index="0" function="D" pad="PB02"/>
<signal group="PAD" index="1" function="D" pad="PA23"/>
<signal group="PAD" index="1" function="D" pad="PB03"/>
<signal group="PAD" index="2" function="D" pad="PA24"/>
<signal group="PAD" index="2" function="D" pad="PB00"/>
<signal group="PAD" index="2" function="C" pad="PA20"/>
<signal group="PAD" index="3" function="D" pad="PA25"/>
<signal group="PAD" index="3" function="D" pad="PB01"/>
<signal group="PAD" index="3" function="C" pad="PA21"/>
</signals>
<parameters>
<param name="DMAC_ID_RX" value="11" caption="Index of DMA RX trigger"/>
<param name="DMAC_ID_TX" value="12" caption="Index of DMA TX trigger"/>
<param name="GCLK_ID_CORE" value="25" caption="Index of Generic Clock for Core"/>
<param name="GCLK_ID_SLOW" value="19" caption="Index of Generic Clock for SMbus timeout"/>
<param name="INT_MSB" value="6"/>
<param name="INSTANCE_ID" value="71"/>
</parameters>
</instance>
</module>
<module name="SYSCTRL" id="U2100" version="2.0.1">
<instance name="SYSCTRL">
<register-group name="SYSCTRL" name-in-module="SYSCTRL" address-space="base" offset="0x40000800"/>
<signals>
<signal group="XIN" function="XIN" pad="PA14"/>
<signal group="XOUT" function="XOUT" pad="PA15"/>
</signals>
<parameters>
<param name="BGAP_CALIB_MSB" value="11"/>
<param name="BOD33_CALIB_MSB" value="5"/>
<param name="DFLL48M_COARSE_MSB" value="5"/>
<param name="DFLL48M_FINE_MSB" value="9"/>
<param name="GCLK_ID_DFLL48" value="0" caption="Index of Generic Clock for DFLL48"/>
<param name="GCLK_ID_FDPLL" value="1" caption="Index of Generic Clock for DPLL"/>
<param name="GCLK_ID_FDPLL32K" value="2" caption="Index of Generic Clock for DPLL 32K"/>
<param name="OSC32K_COARSE_CALIB_MSB" value="6"/>
<param name="POR33_ENTEST_MSB" value="1"/>
<param name="SYSTEM_CLOCK" value="1000000" caption="Initial system clock frequency"/>
<param name="ULPVREF_DIVLEV_MSB" value="3"/>
<param name="ULPVREG_FORCEGAIN_MSB" value="1"/>
<param name="ULPVREG_RAMREFSEL_MSB" value="2"/>
<param name="VREF_CONTROL_MSB" value="48"/>
<param name="VREF_STATUS_MSB" value="7"/>
<param name="VREG_LEVEL_MSB" value="2"/>
<param name="BOD12_VERSION" value="0x112"/>
<param name="BOD33_VERSION" value="0x112"/>
<param name="DFLL48M_VERSION" value="0x301"/>
<param name="FDPLL_VERSION" value="0x111"/>
<param name="OSCULP32K_VERSION" value="0x111"/>
<param name="OSC8M_VERSION" value="0x120"/>
<param name="OSC32K_VERSION" value="0x112"/>
<param name="VREF_VERSION" value="0x201"/>
<param name="VREG_VERSION" value="0x201"/>
<param name="XOSC_VERSION" value="0x114"/>
<param name="XOSC32K_VERSION" value="0x113"/>
<param name="INSTANCE_ID" value="2"/>
</parameters>
</instance>
</module>
<module name="TC" id="U2212" version="1.3.1">
<instance name="TC3">
<register-group name="TC3" name-in-module="TC" address-space="base" offset="0x42002C00"/>
<signals>
<signal group="WO" index="0" function="E" pad="PA18"/>
<signal group="WO" index="0" function="E" pad="PA14"/>
<signal group="WO" index="1" function="E" pad="PA19"/>
<signal group="WO" index="1" function="E" pad="PA15"/>
</signals>
<parameters>
<param name="CC8_NUM" value="2" caption="Number of 8-bit Counters"/>
<param name="CC16_NUM" value="2" caption="Number of 16-bit Counters"/>
<param name="CC32_NUM" value="2" caption="Number of 32-bit Counters"/>
<param name="DITHERING_EXT" value="0" caption="Dithering feature implemented"/>
<param name="DMAC_ID_OVF" value="24" caption="Indexes of DMA Overflow trigger"/>
<param name="DMAC_ID_MC0" value="25" caption="Indexes of DMA Match/Compare 0 trigger"/>
<param name="DMAC_ID_MC1" value="26" caption="Indexes of DMA Match/Compare 1 trigger"/>
<param name="GCLK_ID" value="27" caption="Index of Generic Clock"/>
<param name="MASTER" value="0"/>
<param name="OW_NUM" value="2" caption="Number of Output Waveforms"/>
<param name="PERIOD_EXT" value="0" caption="Period feature implemented"/>
<param name="SHADOW_EXT" value="0" caption="Shadow feature implemented"/>
<param name="INSTANCE_ID" value="75"/>
</parameters>
</instance>
<instance name="TC4">
<register-group name="TC4" name-in-module="TC" address-space="base" offset="0x42003000"/>
<signals>
<signal group="WO" index="0" function="E" pad="PA22"/>
<signal group="WO" index="0" function="E" pad="PB08"/>
<signal group="WO" index="1" function="E" pad="PA23"/>
<signal group="WO" index="1" function="E" pad="PB09"/>
</signals>
<parameters>
<param name="CC8_NUM" value="2" caption="Number of 8-bit Counters"/>
<param name="CC16_NUM" value="2" caption="Number of 16-bit Counters"/>
<param name="CC32_NUM" value="2" caption="Number of 32-bit Counters"/>
<param name="DITHERING_EXT" value="0" caption="Dithering feature implemented"/>
<param name="DMAC_ID_OVF" value="27" caption="Indexes of DMA Overflow trigger"/>
<param name="DMAC_ID_MC0" value="28" caption="Indexes of DMA Match/Compare 0 trigger"/>
<param name="DMAC_ID_MC1" value="29" caption="Indexes of DMA Match/Compare 1 trigger"/>
<param name="GCLK_ID" value="28" caption="Index of Generic Clock"/>
<param name="MASTER" value="1"/>
<param name="OW_NUM" value="2" caption="Number of Output Waveforms"/>
<param name="PERIOD_EXT" value="0" caption="Period feature implemented"/>
<param name="SHADOW_EXT" value="0" caption="Shadow feature implemented"/>
<param name="INSTANCE_ID" value="76"/>
</parameters>
</instance>
<instance name="TC5">
<register-group name="TC5" name-in-module="TC" address-space="base" offset="0x42003400"/>
<signals>
<signal group="WO" index="0" function="E" pad="PA24"/>
<signal group="WO" index="0" function="E" pad="PB10"/>
<signal group="WO" index="1" function="E" pad="PA25"/>
<signal group="WO" index="1" function="E" pad="PB11"/>
</signals>
<parameters>
<param name="CC8_NUM" value="2" caption="Number of 8-bit Counters"/>
<param name="CC16_NUM" value="2" caption="Number of 16-bit Counters"/>
<param name="CC32_NUM" value="2" caption="Number of 32-bit Counters"/>
<param name="DITHERING_EXT" value="0" caption="Dithering feature implemented"/>
<param name="DMAC_ID_OVF" value="30" caption="Indexes of DMA Overflow trigger"/>
<param name="DMAC_ID_MC0" value="21" caption="Indexes of DMA Match/Compare 0 trigger"/>
<param name="DMAC_ID_MC1" value="32" caption="Indexes of DMA Match/Compare 1 trigger"/>
<param name="GCLK_ID" value="28" caption="Index of Generic Clock"/>
<param name="MASTER" value="0"/>
<param name="OW_NUM" value="2" caption="Number of Output Waveforms"/>
<param name="PERIOD_EXT" value="0" caption="Period feature implemented"/>
<param name="SHADOW_EXT" value="0" caption="Shadow feature implemented"/>
<param name="INSTANCE_ID" value="77"/>
</parameters>
</instance>
<instance name="TC6">
<register-group name="TC6" name-in-module="TC" address-space="base" offset="0x42003800"/>
<signals>
<signal group="WO" index="0" function="E" pad="PB02"/>
<signal group="WO" index="1" function="E" pad="PB03"/>
</signals>
<parameters>
<param name="CC8_NUM" value="2" caption="Number of 8-bit Counters"/>
<param name="CC16_NUM" value="2" caption="Number of 16-bit Counters"/>
<param name="CC32_NUM" value="2" caption="Number of 32-bit Counters"/>
<param name="DITHERING_EXT" value="0" caption="Dithering feature implemented"/>
<param name="DMAC_ID_OVF" value="33" caption="Indexes of DMA Overflow trigger"/>
<param name="DMAC_ID_MC0" value="34" caption="Indexes of DMA Match/Compare 0 trigger"/>
<param name="DMAC_ID_MC1" value="35" caption="Indexes of DMA Match/Compare 1 trigger"/>
<param name="GCLK_ID" value="29" caption="Index of Generic Clock"/>
<param name="MASTER" value="1"/>
<param name="OW_NUM" value="2" caption="Number of Output Waveforms"/>
<param name="PERIOD_EXT" value="0" caption="Period feature implemented"/>
<param name="SHADOW_EXT" value="0" caption="Shadow feature implemented"/>
<param name="INSTANCE_ID" value="78"/>
</parameters>
</instance>
<instance name="TC7">
<register-group name="TC7" name-in-module="TC" address-space="base" offset="0x42003C00"/>
<signals>
<signal group="WO" index="0" function="E" pad="PA20"/>
<signal group="WO" index="0" function="E" pad="PB00"/>
<signal group="WO" index="1" function="E" pad="PA21"/>
<signal group="WO" index="1" function="E" pad="PB01"/>
</signals>
<parameters>
<param name="CC8_NUM" value="2" caption="Number of 8-bit Counters"/>
<param name="CC16_NUM" value="2" caption="Number of 16-bit Counters"/>
<param name="CC32_NUM" value="2" caption="Number of 32-bit Counters"/>
<param name="DITHERING_EXT" value="0" caption="Dithering feature implemented"/>
<param name="DMAC_ID_OVF" value="36" caption="Indexes of DMA Overflow trigger"/>
<param name="DMAC_ID_MC0" value="37" caption="Indexes of DMA Match/Compare 0 trigger"/>
<param name="DMAC_ID_MC1" value="38" caption="Indexes of DMA Match/Compare 1 trigger"/>
<param name="GCLK_ID" value="29" caption="Index of Generic Clock"/>
<param name="MASTER" value="0"/>
<param name="OW_NUM" value="2" caption="Number of Output Waveforms"/>
<param name="PERIOD_EXT" value="0" caption="Period feature implemented"/>
<param name="SHADOW_EXT" value="0" caption="Shadow feature implemented"/>
<param name="INSTANCE_ID" value="79"/>
</parameters>
</instance>
</module>
<module name="TCC" id="U2213" version="1.2.2">
<instance name="TCC0">
<register-group name="TCC0" name-in-module="TCC" address-space="base" offset="0x42002000"/>
<signals>
<signal group="WO" index="0" function="E" pad="PA04"/>
<signal group="WO" index="0" function="E" pad="PA08"/>
<signal group="WO" index="1" function="E" pad="PA05"/>
<signal group="WO" index="1" function="E" pad="PA09"/>
<signal group="WO" index="2" function="F" pad="PA10"/>
<signal group="WO" index="2" function="F" pad="PA18"/>
<signal group="WO" index="3" function="F" pad="PA11"/>
<signal group="WO" index="3" function="F" pad="PA19"/>
<signal group="WO" index="4" function="F" pad="PA22"/>
<signal group="WO" index="4" function="F" pad="PB10"/>
<signal group="WO" index="4" function="F" pad="PA14"/>
<signal group="WO" index="5" function="F" pad="PA23"/>
<signal group="WO" index="5" function="F" pad="PB11"/>
<signal group="WO" index="5" function="F" pad="PA15"/>
<signal group="WO" index="6" function="F" pad="PA12"/>
<signal group="WO" index="6" function="F" pad="PA20"/>
<signal group="WO" index="6" function="F" pad="PA16"/>
<signal group="WO" index="7" function="F" pad="PA13"/>
<signal group="WO" index="7" function="F" pad="PA21"/>
<signal group="WO" index="7" function="F" pad="PA17"/>
</signals>
<parameters>
<param name="CC_NUM" value="4" caption="Number of Compare/Capture units"/>
<param name="DITHERING" value="1" caption="Dithering feature implemented"/>
<param name="DMAC_ID_OVF" value="13" caption="DMA overflow/underflow/retrigger trigger"/>
<param name="DMAC_ID_MC0" value="14" caption="DMA Match/Compare 0 trigger"/>
<param name="DMAC_ID_MC1" value="15" caption="DMA Match/Compare 1 trigger"/>
<param name="DMAC_ID_MC2" value="16" caption="DMA Match/Compare 2 trigger"/>
<param name="DMAC_ID_MC3" value="17" caption="DMA Match/Compare 3 trigger"/>
<param name="DTI" value="1" caption="Dead-Time-Insertion feature implemented"/>
<param name="EXT" value="31" caption="(@_DITHERING*16+@_PG*8+@_SWAP*4+@_DTI*2+@_OTMX*1)"/>
<param name="GCLK_ID" value="26" caption="Index of Generic Clock"/>
<param name="MASTER" value="0"/>
<param name="OTMX" value="1" caption="Output Matrix feature implemented"/>
<param name="OW_NUM" value="8" caption="Number of Output Waveforms"/>
<param name="PG" value="1" caption="Pattern Generation feature implemented"/>
<param name="SIZE" value="24"/>
<param name="SWAP" value="1" caption="DTI outputs swap feature implemented"/>
<param name="TYPE" value="1" caption="TCC type 0 : NA, 1 : Master, 2 : Slave"/>
<param name="INSTANCE_ID" value="72"/>
</parameters>
</instance>
<instance name="TCC1">
<register-group name="TCC1" name-in-module="TCC" address-space="base" offset="0x42002400"/>
<signals>
<signal group="WO" index="0" function="E" pad="PA06"/>
<signal group="WO" index="0" function="E" pad="PA10"/>
<signal group="WO" index="0" function="E" pad="PA30"/>
<signal group="WO" index="1" function="E" pad="PA07"/>
<signal group="WO" index="1" function="E" pad="PA11"/>
<signal group="WO" index="1" function="E" pad="PA31"/>
<signal group="WO" index="2" function="F" pad="PA08"/>
<signal group="WO" index="2" function="F" pad="PA24"/>
<signal group="WO" index="3" function="F" pad="PA09"/>
<signal group="WO" index="3" function="F" pad="PA25"/>
</signals>
<parameters>
<param name="CC_NUM" value="2" caption="Number of Compare/Capture units"/>
<param name="DITHERING" value="1" caption="Dithering feature implemented"/>
<param name="DMAC_ID_OVF" value="18" caption="DMA overflow/underflow/retrigger trigger"/>
<param name="DMAC_ID_MC0" value="19" caption="DMA Match/Compare 0 trigger"/>
<param name="DMAC_ID_MC1" value="20" caption="DMA Match/Compare 1 trigger"/>
<param name="DTI" value="0" caption="Dead-Time-Insertion feature implemented"/>
<param name="EXT" value="24" caption="Coding of implemented extended features"/>
<param name="GCLK_ID" value="26" caption="Index of Generic Clock"/>
<param name="MASTER" value="1"/>
<param name="OTMX" value="0" caption="Output Matrix feature implemented"/>
<param name="OW_NUM" value="4" caption="Number of Output Waveforms"/>
<param name="PG" value="1" caption="Pattern Generation feature implemented"/>
<param name="SIZE" value="24"/>
<param name="SWAP" value="0" caption="DTI outputs swap feature implemented"/>
<param name="TYPE" value="2" caption="TCC type 0 : NA, 1 : Master, 2 : Slave"/>
<param name="INSTANCE_ID" value="73"/>
</parameters>
</instance>
<instance name="TCC2">
<register-group name="TCC2" name-in-module="TCC" address-space="base" offset="0x42002800"/>
<signals>
<signal group="WO" index="0" function="E" pad="PA12"/>
<signal group="WO" index="0" function="E" pad="PA16"/>
<signal group="WO" index="1" function="E" pad="PA13"/>
<signal group="WO" index="1" function="E" pad="PA17"/>
</signals>
<parameters>
<param name="CC_NUM" value="2" caption="Number of Compare/Capture units"/>
<param name="DITHERING" value="0" caption="Dithering feature implemented"/>
<param name="DMAC_ID_OVF" value="21" caption="DMA overflow/underflow/retrigger trigger"/>
<param name="DMAC_ID_MC0" value="22" caption="DMA Match/Compare 0 trigger"/>
<param name="DMAC_ID_MC1" value="23" caption="DMA Match/Compare 1 trigger"/>
<param name="DTI" value="0" caption="Dead-Time-Insertion feature implemented"/>
<param name="EXT" value="0" caption="Coding of implemented extended features"/>
<param name="GCLK_ID" value="27" caption="Index of Generic Clock"/>
<param name="MASTER" value="0"/>
<param name="OTMX" value="0" caption="Output Matrix feature implemented"/>
<param name="OW_NUM" value="2" caption="Number of Output Waveforms"/>
<param name="PG" value="0" caption="Pattern Generation feature implemented"/>
<param name="SIZE" value="16"/>
<param name="SWAP" value="0" caption="DTI outputs swap feature implemented"/>
<param name="TYPE" value="0" caption="TCC type 0 : NA, 1 : Master, 2 : Slave"/>
<param name="INSTANCE_ID" value="74"/>
</parameters>
</instance>
</module>
<module name="WDT" id="U2203" version="2.0.0">
<instance name="WDT">
<register-group name="WDT" name-in-module="WDT" address-space="base" offset="0x40001000"/>
<parameters>
<param name="GCLK_ID" value="3" caption="Index of Generic Clock"/>
<param name="INSTANCE_ID" value="4"/>
</parameters>
</instance>
</module>
<module name="NVIC" version="1.0.0">
<instance name="NVIC">
<register-group name="NVIC" name-in-module="NVIC" address-space="base" offset="0xE000E100"/>
<parameters>
<param name="NUM_IRQ" value="29" caption="Number of interrupt requests"/>
<param name="__NVIC_PRIO_BITS" value="2" caption="Number of NVIC interrupt priority bits"/>
</parameters>
</instance>
</module>
<module name="SysTick" version="1.0.0">
<instance name="SysTick">
<register-group name="SysTick" name-in-module="SysTick" address-space="base" offset="0xE000E010"/>
</instance>
</module>
<module name="SystemControl" version="1.0.0">
<instance name="SystemControl">
<register-group name="SystemControl" name-in-module="SystemControl" address-space="base" offset="0xE000E000"/>
<parameters>
<param name="__VTOR_PRESENT" value="1" caption="Vector Table Offset Register present"/>
</parameters>
</instance>
</module>
</peripherals>
<interrupts xmlns:header="http://www.atmel.com/schemas/avr-tools-device-file/header">
<interrupt name="Reset" index="-15" caption="Reset Vector, invoked on Power up and warm reset" header:alternate-caption="Reset Vector"/>
<interrupt name="NonMaskableInt" index="-14" caption="Non maskable Interrupt, cannot be stopped or preempted" header:alternate-caption="Non-maskable Interrupt"/>
<interrupt name="HardFault" index="-13" caption="Hard Fault, all classes of Fault" header:alternate-caption="Hard Fault"/>
<interrupt name="SVCall" index="-5" caption="System Service Call via SVC instruction" header:alternate-caption="SuperVisor Call"/>
<interrupt name="PendSV" index="-2" caption="Pendable request for system service" header:alternate-caption="Pendable SerVice"/>
<interrupt name="SysTick" index="-1" caption="System Tick Timer"/>
<interrupt name="PM" index="0" module-instance="PM" caption="Power Manager"/>
<interrupt name="SYSCTRL" index="1" module-instance="SYSCTRL" caption="System Controller"/>
<interrupt name="WDT" index="2" module-instance="WDT" caption="Watchdog Timer"/>
<interrupt name="RTC" index="3" module-instance="RTC" caption="Real Time Counter"/>
<interrupt name="EIC" index="4" module-instance="EIC" caption="External Interrupt Controller"/>
<interrupt name="NVMCTRL" index="5" module-instance="NVMCTRL" caption="Non-Volatile Memory Controller"/>
<interrupt name="DMAC" index="6" module-instance="DMAC" caption="Direct Memory Controller"/>
<interrupt name="EVSYS" index="8" module-instance="EVSYS" caption="Event Systems"/>
<interrupt name="SERCOM0" index="9" module-instance="SERCOM0" caption="Serial Communication Interface 0"/>
<interrupt name="SERCOM1" index="10" module-instance="SERCOM1" caption="Serial Communication Interface 1"/>
<interrupt name="SERCOM2" index="11" module-instance="SERCOM2" caption="Serial Communication Interface 2"/>
<interrupt name="SERCOM3" index="12" module-instance="SERCOM3" caption="Serial Communication Interface 3"/>
<interrupt name="SERCOM4" index="13" module-instance="SERCOM4" caption="Serial Communication Interface 4"/>
<interrupt name="SERCOM5" index="14" module-instance="SERCOM5" caption="Serial Communication Interface 5"/>
<interrupt name="TCC0" index="15" module-instance="TCC0" caption="Timer/Counter for Control Applications 0"/>
<interrupt name="TCC1" index="16" module-instance="TCC1" caption="Timer/Counter for Control Applications 1"/>
<interrupt name="TCC2" index="17" module-instance="TCC2" caption="Timer/Counter for Control Applications 2"/>
<interrupt name="TC3" index="18" module-instance="TC3" caption="Timer/Counter 3"/>
<interrupt name="TC4" index="19" module-instance="TC4" caption="Timer/Counter 4"/>
<interrupt name="TC5" index="20" module-instance="TC5" caption="Timer/Counter 5"/>
<interrupt name="TC6" index="21" module-instance="TC6" caption="Timer/Counter 6"/>
<interrupt name="TC7" index="22" module-instance="TC7" caption="Timer/Counter 7"/>
<interrupt name="ADC" index="23" module-instance="ADC" caption="Analog-to-Digital Converter"/>
<interrupt name="AC" index="24" module-instance="AC" caption="Analog Comparators"/>
<interrupt name="DAC" index="25" module-instance="DAC" caption="Digital-to-Analog Converter"/>
<interrupt name="AC1" index="28" module-instance="AC1" caption="Analog Comparators 1"/>
</interrupts>
<events>
<generators>
<generator name="RTC_CMP_0" index="1" module-instance="RTC"/>
<generator name="RTC_CMP_1" index="2" module-instance="RTC"/>
<generator name="RTC_OVF" index="3" module-instance="RTC"/>
<generator name="RTC_PER_0" index="4" module-instance="RTC"/>
<generator name="RTC_PER_1" index="5" module-instance="RTC"/>
<generator name="RTC_PER_2" index="6" module-instance="RTC"/>
<generator name="RTC_PER_3" index="7" module-instance="RTC"/>
<generator name="RTC_PER_4" index="8" module-instance="RTC"/>
<generator name="RTC_PER_5" index="9" module-instance="RTC"/>
<generator name="RTC_PER_6" index="10" module-instance="RTC"/>
<generator name="RTC_PER_7" index="11" module-instance="RTC"/>
<generator name="EIC_EXTINT_0" index="12" module-instance="EIC"/>
<generator name="EIC_EXTINT_1" index="13" module-instance="EIC"/>
<generator name="EIC_EXTINT_2" index="14" module-instance="EIC"/>
<generator name="EIC_EXTINT_3" index="15" module-instance="EIC"/>
<generator name="EIC_EXTINT_4" index="16" module-instance="EIC"/>
<generator name="EIC_EXTINT_5" index="17" module-instance="EIC"/>
<generator name="EIC_EXTINT_6" index="18" module-instance="EIC"/>
<generator name="EIC_EXTINT_7" index="19" module-instance="EIC"/>
<generator name="EIC_EXTINT_8" index="20" module-instance="EIC"/>
<generator name="EIC_EXTINT_9" index="21" module-instance="EIC"/>
<generator name="EIC_EXTINT_10" index="22" module-instance="EIC"/>
<generator name="EIC_EXTINT_11" index="23" module-instance="EIC"/>
<generator name="EIC_EXTINT_12" index="24" module-instance="EIC"/>
<generator name="EIC_EXTINT_13" index="25" module-instance="EIC"/>
<generator name="EIC_EXTINT_14" index="26" module-instance="EIC"/>
<generator name="EIC_EXTINT_15" index="27" module-instance="EIC"/>
<generator name="EIC_EXTINT_16" index="28" module-instance="EIC"/>
<generator name="EIC_EXTINT_17" index="29" module-instance="EIC"/>
<generator name="DMAC_CH_0" index="30" module-instance="DMAC"/>
<generator name="DMAC_CH_1" index="31" module-instance="DMAC"/>
<generator name="DMAC_CH_2" index="32" module-instance="DMAC"/>
<generator name="DMAC_CH_3" index="33" module-instance="DMAC"/>
<generator name="TCC0_OVF" index="34" module-instance="TCC0"/>
<generator name="TCC0_TRG" index="35" module-instance="TCC0"/>
<generator name="TCC0_CNT" index="36" module-instance="TCC0"/>
<generator name="TCC0_MC_0" index="37" module-instance="TCC0"/>
<generator name="TCC0_MC_1" index="38" module-instance="TCC0"/>
<generator name="TCC0_MC_2" index="39" module-instance="TCC0"/>
<generator name="TCC0_MC_3" index="40" module-instance="TCC0"/>
<generator name="TCC1_OVF" index="41" module-instance="TCC1"/>
<generator name="TCC1_TRG" index="42" module-instance="TCC1"/>
<generator name="TCC1_CNT" index="43" module-instance="TCC1"/>
<generator name="TCC1_MC_0" index="44" module-instance="TCC1"/>
<generator name="TCC1_MC_1" index="45" module-instance="TCC1"/>
<generator name="TCC2_OVF" index="46" module-instance="TCC2"/>
<generator name="TCC2_TRG" index="47" module-instance="TCC2"/>
<generator name="TCC2_CNT" index="48" module-instance="TCC2"/>
<generator name="TCC2_MC_0" index="49" module-instance="TCC2"/>
<generator name="TCC2_MC_1" index="50" module-instance="TCC2"/>
<generator name="TC3_OVF" index="51" module-instance="TC3"/>
<generator name="TC3_MC_0" index="52" module-instance="TC3"/>
<generator name="TC3_MC_1" index="53" module-instance="TC3"/>
<generator name="TC4_OVF" index="54" module-instance="TC4"/>
<generator name="TC4_MC_0" index="55" module-instance="TC4"/>
<generator name="TC4_MC_1" index="56" module-instance="TC4"/>
<generator name="TC5_OVF" index="57" module-instance="TC5"/>
<generator name="TC5_MC_0" index="58" module-instance="TC5"/>
<generator name="TC5_MC_1" index="59" module-instance="TC5"/>
<generator name="TC6_OVF" index="60" module-instance="TC6"/>
<generator name="TC6_MC_0" index="61" module-instance="TC6"/>
<generator name="TC6_MC_1" index="62" module-instance="TC6"/>
<generator name="TC7_OVF" index="63" module-instance="TC7"/>
<generator name="TC7_MC_0" index="64" module-instance="TC7"/>
<generator name="TC7_MC_1" index="65" module-instance="TC7"/>
<generator name="ADC_RESRDY" index="66" module-instance="ADC"/>
<generator name="ADC_WINMON" index="67" module-instance="ADC"/>
<generator name="AC_COMP_0" index="68" module-instance="AC"/>
<generator name="AC_COMP_1" index="69" module-instance="AC"/>
<generator name="AC_WIN_0" index="70" module-instance="AC"/>
<generator name="DAC_EMPTY" index="71" module-instance="DAC"/>
<generator name="AC1_COMP_0" index="74" module-instance="AC1"/>
<generator name="AC1_COMP_1" index="75" module-instance="AC1"/>
<generator name="AC1_WIN_0" index="76" module-instance="AC1"/>
</generators>
<users>
<user name="DMAC_CH_0" index="0" module-instance="DMAC"/>
<user name="DMAC_CH_1" index="1" module-instance="DMAC"/>
<user name="DMAC_CH_2" index="2" module-instance="DMAC"/>
<user name="DMAC_CH_3" index="3" module-instance="DMAC"/>
<user name="TCC0_EV_0" index="4" module-instance="TCC0"/>
<user name="TCC0_EV_1" index="5" module-instance="TCC0"/>
<user name="TCC0_MC_0" index="6" module-instance="TCC0"/>
<user name="TCC0_MC_1" index="7" module-instance="TCC0"/>
<user name="TCC0_MC_2" index="8" module-instance="TCC0"/>
<user name="TCC0_MC_3" index="9" module-instance="TCC0"/>
<user name="TCC1_EV_0" index="10" module-instance="TCC1"/>
<user name="TCC1_EV_1" index="11" module-instance="TCC1"/>
<user name="TCC1_MC_0" index="12" module-instance="TCC1"/>
<user name="TCC1_MC_1" index="13" module-instance="TCC1"/>
<user name="TCC2_EV_0" index="14" module-instance="TCC2"/>
<user name="TCC2_EV_1" index="15" module-instance="TCC2"/>
<user name="TCC2_MC_0" index="16" module-instance="TCC2"/>
<user name="TCC2_MC_1" index="17" module-instance="TCC2"/>
<user name="TC3_EVU" index="18" module-instance="TC3"/>
<user name="TC4_EVU" index="19" module-instance="TC4"/>
<user name="TC5_EVU" index="20" module-instance="TC5"/>
<user name="TC6_EVU" index="21" module-instance="TC6"/>
<user name="TC7_EVU" index="22" module-instance="TC7"/>
<user name="ADC_START" index="23" module-instance="ADC"/>
<user name="ADC_SYNC" index="24" module-instance="ADC"/>
<user name="AC_SOC_0" index="25" module-instance="AC"/>
<user name="AC_SOC_1" index="26" module-instance="AC"/>
<user name="DAC_START" index="27" module-instance="DAC"/>
<user name="AC1_SOC_0" index="29" module-instance="AC1"/>
<user name="AC1_SOC_1" index="30" module-instance="AC1"/>
</users>
</events>
<interfaces>
<interface name="SWD" type="swd"/>
</interfaces>
<property-groups>
<property-group name="SIGNATURES">
<property name="DSU_DID" value="0x10011557"/>
</property-group>
</property-groups>
</device>
</devices>
<modules>
<module name="AC" id="U2205" version="1.1.2" caption="Analog Comparators">
<register-group name="AC" caption="Analog Comparators">
<register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control A">
<bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
<bitfield name="ENABLE" caption="Enable" mask="0x2"/>
<bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
<bitfield name="LPMUX" caption="Low-Power Mux" mask="0x80"/>
</register>
<register name="CTRLB" offset="0x1" rw="W" size="1" initval="0x00" caption="Control B">
<bitfield name="START0" caption="Comparator 0 Start Comparison" mask="0x1"/>
<bitfield name="START1" caption="Comparator 1 Start Comparison" mask="0x2"/>
</register>
<register name="EVCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Event Control">
<bitfield name="COMPEO0" caption="Comparator 0 Event Output Enable" mask="0x1"/>
<bitfield name="COMPEO1" caption="Comparator 1 Event Output Enable" mask="0x2"/>
<bitfield name="WINEO0" caption="Window 0 Event Output Enable" mask="0x10"/>
<bitfield name="COMPEI0" caption="Comparator 0 Event Input" mask="0x100"/>
<bitfield name="COMPEI1" caption="Comparator 1 Event Input" mask="0x200"/>
</register>
<register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
<bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
<bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
<bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x10"/>
</register>
<register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
<bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
<bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
<bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x10"/>
</register>
<register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
<bitfield name="COMP0" caption="Comparator 0" mask="0x1"/>
<bitfield name="COMP1" caption="Comparator 1" mask="0x2"/>
<bitfield name="WIN0" caption="Window 0" mask="0x10"/>
</register>
<register name="STATUSA" offset="0x8" rw="R" size="1" initval="0x00" caption="Status A">
<bitfield name="STATE0" caption="Comparator 0 Current State" mask="0x1"/>
<bitfield name="STATE1" caption="Comparator 1 Current State" mask="0x2"/>
<bitfield name="WSTATE0" caption="Window 0 Current State" mask="0x30" values="AC_STATUSA__WSTATE0"/>
</register>
<register name="STATUSB" offset="0x9" rw="R" size="1" initval="0x00" caption="Status B">
<bitfield name="READY0" caption="Comparator 0 Ready" mask="0x1"/>
<bitfield name="READY1" caption="Comparator 1 Ready" mask="0x2"/>
<bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
</register>
<register name="STATUSC" offset="0xA" rw="R" size="1" initval="0x00" caption="Status C">
<bitfield name="STATE0" caption="Comparator 0 Current State" mask="0x1"/>
<bitfield name="STATE1" caption="Comparator 1 Current State" mask="0x2"/>
<bitfield name="WSTATE0" caption="Window 0 Current State" mask="0x30" values="AC_STATUSC__WSTATE0"/>
</register>
<register name="WINCTRL" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Window Control">
<bitfield name="WEN0" caption="Window 0 Mode Enable" mask="0x1"/>
<bitfield name="WINTSEL0" caption="Window 0 Interrupt Selection" mask="0x6" values="AC_WINCTRL__WINTSEL0"/>
</register>
<register name="COMPCTRL" offset="0x10" rw="RW" access="WSYNC" size="4" count="2" initval="0x00000000" caption="Comparator Control n">
<bitfield name="ENABLE" caption="Enable" mask="0x1"/>
<bitfield name="SINGLE" caption="Single-Shot Mode" mask="0x2"/>
<bitfield name="SPEED" caption="Speed Selection" mask="0xC" values="AC_COMPCTRL__SPEED"/>
<bitfield name="INTSEL" caption="Interrupt Selection" mask="0x60" values="AC_COMPCTRL__INTSEL"/>
<bitfield name="MUXNEG" caption="Negative Input Mux Selection" mask="0x700" values="AC_COMPCTRL__MUXNEG"/>
<bitfield name="MUXPOS" caption="Positive Input Mux Selection" mask="0x3000" values="AC_COMPCTRL__MUXPOS"/>
<bitfield name="SWAP" caption="Swap Inputs and Invert" mask="0x8000"/>
<bitfield name="OUT" caption="Output" mask="0x30000" values="AC_COMPCTRL__OUT"/>
<bitfield name="HYST" caption="Hysteresis Enable" mask="0x80000"/>
<bitfield name="FLEN" caption="Filter Length" mask="0x7000000" values="AC_COMPCTRL__FLEN"/>
</register>
<register name="SCALER" offset="0x20" rw="RW" size="1" count="2" initval="0x00" caption="Scaler n">
<bitfield name="VALUE" caption="Scaler Value" mask="0x3F"/>
</register>
</register-group>
<value-group name="AC_STATUSA__WSTATE0">
<value name="ABOVE" caption="Signal is above window" value="0"/>
<value name="INSIDE" caption="Signal is inside window" value="1"/>
<value name="BELOW" caption="Signal is below window" value="2"/>
</value-group>
<value-group name="AC_STATUSA__WSTATE1">
<value name="ABOVE" caption="Signal is above window" value="0"/>
<value name="INSIDE" caption="Signal is inside window" value="1"/>
<value name="BELOW" caption="Signal is below window" value="2"/>
</value-group>
<value-group name="AC_STATUSC__WSTATE0">
<value name="ABOVE" caption="Signal is above window" value="0"/>
<value name="INSIDE" caption="Signal is inside window" value="1"/>
<value name="BELOW" caption="Signal is below window" value="2"/>
</value-group>
<value-group name="AC_STATUSC__WSTATE1">
<value name="ABOVE" caption="Signal is above window" value="0"/>
<value name="INSIDE" caption="Signal is inside window" value="1"/>
<value name="BELOW" caption="Signal is below window" value="2"/>
</value-group>
<value-group name="AC_WINCTRL__WINTSEL0">
<value name="ABOVE" caption="Interrupt on signal above window" value="0"/>
<value name="INSIDE" caption="Interrupt on signal inside window" value="1"/>
<value name="BELOW" caption="Interrupt on signal below window" value="2"/>
<value name="OUTSIDE" caption="Interrupt on signal outside window" value="3"/>
</value-group>
<value-group name="AC_WINCTRL__WINTSEL1">
<value name="ABOVE" caption="Interrupt on signal above window" value="0"/>
<value name="INSIDE" caption="Interrupt on signal inside window" value="1"/>
<value name="BELOW" caption="Interrupt on signal below window" value="2"/>
<value name="OUTSIDE" caption="Interrupt on signal outside window" value="3"/>
</value-group>
<value-group name="AC_COMPCTRL__FLEN">
<value name="OFF" caption="No filtering" value="0"/>
<value name="MAJ3" caption="3-bit majority function (2 of 3)" value="1"/>
<value name="MAJ5" caption="5-bit majority function (3 of 5)" value="2"/>
</value-group>
<value-group name="AC_COMPCTRL__INTSEL">
<value name="TOGGLE" caption="Interrupt on comparator output toggle" value="0"/>
<value name="RISING" caption="Interrupt on comparator output rising" value="1"/>
<value name="FALLING" caption="Interrupt on comparator output falling" value="2"/>
<value name="EOC" caption="Interrupt on end of comparison (single-shot mode only)" value="3"/>
</value-group>
<value-group name="AC_COMPCTRL__MUXNEG">
<value name="PIN0" caption="I/O pin 0" value="0"/>
<value name="PIN1" caption="I/O pin 1" value="1"/>
<value name="PIN2" caption="I/O pin 2" value="2"/>
<value name="PIN3" caption="I/O pin 3" value="3"/>
<value name="GND" caption="Ground" value="4"/>
<value name="VSCALE" caption="VDD scaler" value="5"/>
<value name="BANDGAP" caption="Internal bandgap voltage" value="6"/>
<value name="DAC" caption="DAC output" value="7"/>
</value-group>
<value-group name="AC_COMPCTRL__MUXPOS">
<value name="PIN0" caption="I/O pin 0" value="0"/>
<value name="PIN1" caption="I/O pin 1" value="1"/>
<value name="PIN2" caption="I/O pin 2" value="2"/>
<value name="PIN3" caption="I/O pin 3" value="3"/>
</value-group>
<value-group name="AC_COMPCTRL__OUT">
<value name="OFF" caption="The output of COMPn is not routed to the COMPn I/O port" value="0"/>
<value name="ASYNC" caption="The asynchronous output of COMPn is routed to the COMPn I/O port" value="1"/>
<value name="SYNC" caption="The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port" value="2"/>
</value-group>
<value-group name="AC_COMPCTRL__SPEED">
<value name="LOW" caption="Low speed" value="0"/>
<value name="HIGH" caption="High speed" value="1"/>
</value-group>
</module>
<module name="ADC" id="U2204" version="1.2.0" caption="Analog Digital Converter">
<register-group name="ADC" caption="Analog Digital Converter">
<register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
<bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
<bitfield name="ENABLE" caption="Enable" mask="0x2"/>
<bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
</register>
<register name="REFCTRL" offset="0x1" rw="RW" size="1" initval="0x00" caption="Reference Control">
<bitfield name="REFSEL" caption="Reference Selection" mask="0xF" values="ADC_REFCTRL__REFSEL"/>
<bitfield name="REFCOMP" caption="Reference Buffer Offset Compensation Enable" mask="0x80"/>
</register>
<register name="AVGCTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Average Control">
<bitfield name="SAMPLENUM" caption="Number of Samples to be Collected" mask="0xF" values="ADC_AVGCTRL__SAMPLENUM"/>
<bitfield name="ADJRES" caption="Adjusting Result / Division Coefficient" mask="0x70"/>
</register>
<register name="SAMPCTRL" offset="0x3" rw="RW" size="1" initval="0x00" caption="Sampling Time Control">
<bitfield name="SAMPLEN" caption="Sampling Time Length" mask="0x3F"/>
</register>
<register name="CTRLB" offset="0x4" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Control B">
<bitfield name="DIFFMODE" caption="Differential Mode" mask="0x1"/>
<bitfield name="LEFTADJ" caption="Left-Adjusted Result" mask="0x2"/>
<bitfield name="FREERUN" caption="Free Running Mode" mask="0x4"/>
<bitfield name="CORREN" caption="Digital Correction Logic Enabled" mask="0x8"/>
<bitfield name="RESSEL" caption="Conversion Result Resolution" mask="0x30" values="ADC_CTRLB__RESSEL"/>
<bitfield name="PRESCALER" caption="Prescaler Configuration" mask="0x700" values="ADC_CTRLB__PRESCALER"/>
</register>
<register name="WINCTRL" offset="0x8" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Window Monitor Control">
<bitfield name="WINMODE" caption="Window Monitor Mode" mask="0x7" values="ADC_WINCTRL__WINMODE"/>
</register>
<register name="SWTRIG" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Software Trigger">
<bitfield name="FLUSH" caption="ADC Conversion Flush" mask="0x1"/>
<bitfield name="START" caption="ADC Start Conversion" mask="0x2"/>
</register>
<register name="INPUTCTRL" offset="0x10" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Input Control">
<bitfield name="MUXPOS" caption="Positive Mux Input Selection" mask="0x1F" values="ADC_INPUTCTRL__MUXPOS"/>
<bitfield name="MUXNEG" caption="Negative Mux Input Selection" mask="0x1F00" values="ADC_INPUTCTRL__MUXNEG"/>
<bitfield name="INPUTSCAN" caption="Number of Input Channels Included in Scan" mask="0xF0000"/>
<bitfield name="INPUTOFFSET" caption="Positive Mux Setting Offset" mask="0xF00000"/>
<bitfield name="GAIN" caption="Gain Factor Selection" mask="0xF000000" values="ADC_INPUTCTRL__GAIN"/>
</register>
<register name="EVCTRL" offset="0x14" rw="RW" size="1" initval="0x00" caption="Event Control">
<bitfield name="STARTEI" caption="Start Conversion Event In" mask="0x1"/>
<bitfield name="SYNCEI" caption="Synchronization Event In" mask="0x2"/>
<bitfield name="RESRDYEO" caption="Result Ready Event Out" mask="0x10"/>
<bitfield name="WINMONEO" caption="Window Monitor Event Out" mask="0x20"/>
</register>
<register name="INTENCLR" offset="0x16" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
<bitfield name="RESRDY" caption="Result Ready Interrupt Enable" mask="0x1"/>
<bitfield name="OVERRUN" caption="Overrun Interrupt Enable" mask="0x2"/>
<bitfield name="WINMON" caption="Window Monitor Interrupt Enable" mask="0x4"/>
<bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
</register>
<register name="INTENSET" offset="0x17" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
<bitfield name="RESRDY" caption="Result Ready Interrupt Enable" mask="0x1"/>
<bitfield name="OVERRUN" caption="Overrun Interrupt Enable" mask="0x2"/>
<bitfield name="WINMON" caption="Window Monitor Interrupt Enable" mask="0x4"/>
<bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
</register>
<register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
<bitfield name="RESRDY" caption="Result Ready" mask="0x1"/>
<bitfield name="OVERRUN" caption="Overrun" mask="0x2"/>
<bitfield name="WINMON" caption="Window Monitor" mask="0x4"/>
<bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
</register>
<register name="STATUS" offset="0x19" rw="R" size="1" initval="0x00" caption="Status">
<bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
</register>
<register name="RESULT" offset="0x1A" rw="R" access="RSYNC" size="2" initval="0x0000" caption="Result">
<bitfield name="RESULT" caption="Result Conversion Value" mask="0xFFFF"/>
</register>
<register name="WINLT" offset="0x1C" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Window Monitor Lower Threshold">
<bitfield name="WINLT" caption="Window Lower Threshold" mask="0xFFFF"/>
</register>
<register name="WINUT" offset="0x20" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Window Monitor Upper Threshold">
<bitfield name="WINUT" caption="Window Upper Threshold" mask="0xFFFF"/>
</register>
<register name="GAINCORR" offset="0x24" rw="RW" size="2" initval="0x0000" caption="Gain Correction">
<bitfield name="GAINCORR" caption="Gain Correction Value" mask="0xFFF"/>
</register>
<register name="OFFSETCORR" offset="0x26" rw="RW" size="2" initval="0x0000" caption="Offset Correction">
<bitfield name="OFFSETCORR" caption="Offset Correction Value" mask="0xFFF"/>
</register>
<register name="CALIB" offset="0x28" rw="RW" size="2" initval="0x0000" caption="Calibration">
<bitfield name="LINEARITY_CAL" caption="Linearity Calibration Value" mask="0xFF"/>
<bitfield name="BIAS_CAL" caption="Bias Calibration Value" mask="0x700"/>
</register>
<register name="DBGCTRL" offset="0x2A" rw="RW" size="1" initval="0x00" caption="Debug Control">
<bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
</register>
</register-group>
<value-group name="ADC_REFCTRL__REFSEL">
<value name="INT1V" caption="1.0V voltage reference" value="0x0"/>
<value name="INTVCC0" caption="1/1.48 VDDANA" value="0x1"/>
<value name="INTVCC1" caption="1/2 VDDANA (only for VDDANA &gt; 2.0V)" value="0x2"/>
<value name="AREFA" caption="External reference A" value="0x3"/>
<value name="AREFB" caption="External reference B" value="0x4"/>
</value-group>
<value-group name="ADC_AVGCTRL__SAMPLENUM">
<value name="1" caption="1 sample" value="0x0"/>
<value name="2" caption="2 samples" value="0x1"/>
<value name="4" caption="4 samples" value="0x2"/>
<value name="8" caption="8 samples" value="0x3"/>
<value name="16" caption="16 samples" value="0x4"/>
<value name="32" caption="32 samples" value="0x5"/>
<value name="64" caption="64 samples" value="0x6"/>
<value name="128" caption="128 samples" value="0x7"/>
<value name="256" caption="256 samples" value="0x8"/>
<value name="512" caption="512 samples" value="0x9"/>
<value name="1024" caption="1024 samples" value="0xA"/>
</value-group>
<value-group name="ADC_CTRLB__PRESCALER">
<value name="DIV4" caption="Peripheral clock divided by 4" value="0x0"/>
<value name="DIV8" caption="Peripheral clock divided by 8" value="0x1"/>
<value name="DIV16" caption="Peripheral clock divided by 16" value="0x2"/>
<value name="DIV32" caption="Peripheral clock divided by 32" value="0x3"/>
<value name="DIV64" caption="Peripheral clock divided by 64" value="0x4"/>
<value name="DIV128" caption="Peripheral clock divided by 128" value="0x5"/>
<value name="DIV256" caption="Peripheral clock divided by 256" value="0x6"/>
<value name="DIV512" caption="Peripheral clock divided by 512" value="0x7"/>
</value-group>
<value-group name="ADC_CTRLB__RESSEL">
<value name="12BIT" caption="12-bit result" value="0x0"/>
<value name="16BIT" caption="16-bit averaging mode" value="0x1"/>
<value name="10BIT" caption="10-bit result" value="0x2"/>
<value name="8BIT" caption="8-bit result" value="0x3"/>
</value-group>
<value-group name="ADC_WINCTRL__WINMODE">
<value name="DISABLE" caption="No window mode (default)" value="0x0"/>
<value name="MODE1" caption="Mode 1: RESULT &gt; WINLT" value="0x1"/>
<value name="MODE2" caption="Mode 2: RESULT &lt; WINUT" value="0x2"/>
<value name="MODE3" caption="Mode 3: WINLT &lt; RESULT &lt; WINUT" value="0x3"/>
<value name="MODE4" caption="Mode 4: !(WINLT &lt; RESULT &lt; WINUT)" value="0x4"/>
</value-group>
<value-group name="ADC_INPUTCTRL__GAIN">
<value name="1X" caption="1x" value="0x0"/>
<value name="2X" caption="2x" value="0x1"/>
<value name="4X" caption="4x" value="0x2"/>
<value name="8X" caption="8x" value="0x3"/>
<value name="16X" caption="16x" value="0x4"/>
<value name="DIV2" caption="1/2x" value="0xF"/>
</value-group>
<value-group name="ADC_INPUTCTRL__MUXNEG">
<value name="PIN0" caption="ADC AIN0 Pin" value="0x0"/>
<value name="PIN1" caption="ADC AIN1 Pin" value="0x1"/>
<value name="PIN2" caption="ADC AIN2 Pin" value="0x2"/>
<value name="PIN3" caption="ADC AIN3 Pin" value="0x3"/>
<value name="PIN4" caption="ADC AIN4 Pin" value="0x4"/>
<value name="PIN5" caption="ADC AIN5 Pin" value="0x5"/>
<value name="PIN6" caption="ADC AIN6 Pin" value="0x6"/>
<value name="PIN7" caption="ADC AIN7 Pin" value="0x7"/>
<value name="GND" caption="Internal Ground" value="0x18"/>
<value name="IOGND" caption="I/O Ground" value="0x19"/>
</value-group>
<value-group name="ADC_INPUTCTRL__MUXPOS">
<value name="PIN0" caption="ADC AIN0 Pin" value="0x0"/>
<value name="PIN1" caption="ADC AIN1 Pin" value="0x1"/>
<value name="PIN2" caption="ADC AIN2 Pin" value="0x2"/>
<value name="PIN3" caption="ADC AIN3 Pin" value="0x3"/>
<value name="PIN4" caption="ADC AIN4 Pin" value="0x4"/>
<value name="PIN5" caption="ADC AIN5 Pin" value="0x5"/>
<value name="PIN6" caption="ADC AIN6 Pin" value="0x6"/>
<value name="PIN7" caption="ADC AIN7 Pin" value="0x7"/>
<value name="PIN8" caption="ADC AIN8 Pin" value="0x8"/>
<value name="PIN9" caption="ADC AIN9 Pin" value="0x9"/>
<value name="PIN10" caption="ADC AIN10 Pin" value="0xA"/>
<value name="PIN11" caption="ADC AIN11 Pin" value="0xB"/>
<value name="PIN12" caption="ADC AIN12 Pin" value="0xC"/>
<value name="PIN13" caption="ADC AIN13 Pin" value="0xD"/>
<value name="PIN14" caption="ADC AIN14 Pin" value="0xE"/>
<value name="PIN15" caption="ADC AIN15 Pin" value="0xF"/>
<value name="PIN16" caption="ADC AIN16 Pin" value="0x10"/>
<value name="PIN17" caption="ADC AIN17 Pin" value="0x11"/>
<value name="PIN18" caption="ADC AIN18 Pin" value="0x12"/>
<value name="PIN19" caption="ADC AIN19 Pin" value="0x13"/>
<value name="TEMP" caption="Temperature Reference" value="0x18"/>
<value name="BANDGAP" caption="Bandgap Voltage" value="0x19"/>
<value name="SCALEDCOREVCC" caption="1/4 Scaled Core Supply" value="0x1A"/>
<value name="SCALEDIOVCC" caption="1/4 Scaled I/O Supply" value="0x1B"/>
<value name="DAC" caption="DAC Output" value="0x1C"/>
</value-group>
</module>
<module name="DAC" id="U2214" version="1.1.0" caption="Digital Analog Converter">
<register-group name="DAC" caption="Digital Analog Converter">
<register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control A">
<bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
<bitfield name="ENABLE" caption="Enable" mask="0x2"/>
<bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
</register>
<register name="CTRLB" offset="0x1" rw="RW" size="1" initval="0x00" caption="Control B">
<bitfield name="EOEN" caption="External Output Enable" mask="0x1"/>
<bitfield name="IOEN" caption="Internal Output Enable" mask="0x2"/>
<bitfield name="LEFTADJ" caption="Left Adjusted Data" mask="0x4"/>
<bitfield name="VPD" caption="Voltage Pump Disable" mask="0x8"/>
<bitfield name="BDWP" caption="Bypass DATABUF Write Protection" mask="0x10"/>
<bitfield name="REFSEL" caption="Reference Selection" mask="0xC0" values="DAC_CTRLB__REFSEL"/>
</register>
<register name="EVCTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Event Control">
<bitfield name="STARTEI" caption="Start Conversion Event Input" mask="0x1"/>
<bitfield name="EMPTYEO" caption="Data Buffer Empty Event Output" mask="0x2"/>
</register>
<register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
<bitfield name="UNDERRUN" caption="Underrun Interrupt Enable" mask="0x1"/>
<bitfield name="EMPTY" caption="Data Buffer Empty Interrupt Enable" mask="0x2"/>
<bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x4"/>
</register>
<register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
<bitfield name="UNDERRUN" caption="Underrun Interrupt Enable" mask="0x1"/>
<bitfield name="EMPTY" caption="Data Buffer Empty Interrupt Enable" mask="0x2"/>
<bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x4"/>
</register>
<register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
<bitfield name="UNDERRUN" caption="Underrun" mask="0x1"/>
<bitfield name="EMPTY" caption="Data Buffer Empty" mask="0x2"/>
<bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x4"/>
</register>
<register name="STATUS" offset="0x7" rw="R" access="RSYNC" size="1" initval="0x00" caption="Status">
<bitfield name="SYNCBUSY" caption="Synchronization Busy Status" mask="0x80"/>
</register>
<register name="DATA" offset="0x8" rw="RW" access="RWSYNC" size="2" initval="0x0000" caption="Data">
<bitfield name="DATA" caption="Data value to be converted" mask="0xFFFF"/>
</register>
<register name="DATABUF" offset="0xC" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Data Buffer">
<bitfield name="DATABUF" caption="Data Buffer" mask="0xFFFF"/>
</register>
</register-group>
<value-group name="DAC_CTRLB__REFSEL">
<value name="INT1V" caption="Internal 1.0V reference" value="0"/>
<value name="AVCC" caption="AVCC" value="1"/>
<value name="VREFP" caption="External reference" value="2"/>
</value-group>
</module>
<module name="DMAC" id="U2223" version="1.1.0" caption="Direct Memory Access Controller">
<register-group name="DMAC" caption="Direct Memory Access Controller">
<register name="CTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control">
<bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
<bitfield name="DMAENABLE" caption="DMA Enable" mask="0x2"/>
<bitfield name="CRCENABLE" caption="CRC Enable" mask="0x4"/>
<bitfield name="LVLEN0" caption="Priority Level 0 Enable" mask="0x100"/>
<bitfield name="LVLEN1" caption="Priority Level 1 Enable" mask="0x200"/>
<bitfield name="LVLEN2" caption="Priority Level 2 Enable" mask="0x400"/>
<bitfield name="LVLEN3" caption="Priority Level 3 Enable" mask="0x800"/>
</register>
<register name="CRCCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="CRC Control">
<bitfield name="CRCBEATSIZE" caption="CRC Beat Size" mask="0x3" values="DMAC_CRCCTRL__CRCBEATSIZE"/>
<bitfield name="CRCPOLY" caption="CRC Polynomial Type" mask="0xC" values="DMAC_CRCCTRL__CRCPOLY"/>
<bitfield name="CRCSRC" caption="CRC Input Source" mask="0x3F00" values="DMAC_CRCCTRL__CRCSRC"/>
</register>
<register name="CRCDATAIN" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="CRC Data Input">
<bitfield name="CRCDATAIN" caption="CRC Data Input" mask="0xFFFFFFFF"/>
</register>
<register name="CRCCHKSUM" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="CRC Checksum">
<bitfield name="CRCCHKSUM" caption="CRC Checksum" mask="0xFFFFFFFF"/>
</register>
<register name="CRCSTATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="CRC Status">
<bitfield name="CRCBUSY" caption="CRC Module Busy" mask="0x1"/>
<bitfield name="CRCZERO" caption="CRC Zero" mask="0x2"/>
</register>
<register name="DBGCTRL" offset="0xD" rw="RW" size="1" initval="0x00" caption="Debug Control">
<bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
</register>
<register name="QOSCTRL" offset="0xE" rw="RW" size="1" initval="0x15" caption="QOS Control">
<bitfield name="WRBQOS" caption="Write-Back Quality of Service" mask="0x3" values="DMAC_QOSCTRL__WRBQOS"/>
<bitfield name="FQOS" caption="Fetch Quality of Service" mask="0xC" values="DMAC_QOSCTRL__FQOS"/>
<bitfield name="DQOS" caption="Data Transfer Quality of Service" mask="0x30" values="DMAC_QOSCTRL__DQOS"/>
</register>
<register name="SWTRIGCTRL" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Software Trigger Control">
<bitfield name="SWTRIG0" caption="Channel 0 Software Trigger" mask="0x1"/>
<bitfield name="SWTRIG1" caption="Channel 1 Software Trigger" mask="0x2"/>
<bitfield name="SWTRIG2" caption="Channel 2 Software Trigger" mask="0x4"/>
<bitfield name="SWTRIG3" caption="Channel 3 Software Trigger" mask="0x8"/>
<bitfield name="SWTRIG4" caption="Channel 4 Software Trigger" mask="0x10"/>
<bitfield name="SWTRIG5" caption="Channel 5 Software Trigger" mask="0x20"/>
<bitfield name="SWTRIG6" caption="Channel 6 Software Trigger" mask="0x40"/>
<bitfield name="SWTRIG7" caption="Channel 7 Software Trigger" mask="0x80"/>
<bitfield name="SWTRIG8" caption="Channel 8 Software Trigger" mask="0x100"/>
<bitfield name="SWTRIG9" caption="Channel 9 Software Trigger" mask="0x200"/>
<bitfield name="SWTRIG10" caption="Channel 10 Software Trigger" mask="0x400"/>
<bitfield name="SWTRIG11" caption="Channel 11 Software Trigger" mask="0x800"/>
</register>
<register name="PRICTRL0" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Priority Control 0">
<bitfield name="LVLPRI0" caption="Level 0 Channel Priority Number" mask="0xF"/>
<bitfield name="RRLVLEN0" caption="Level 0 Round-Robin Scheduling Enable" mask="0x80"/>
<bitfield name="LVLPRI1" caption="Level 1 Channel Priority Number" mask="0xF00"/>
<bitfield name="RRLVLEN1" caption="Level 1 Round-Robin Scheduling Enable" mask="0x8000"/>
<bitfield name="LVLPRI2" caption="Level 2 Channel Priority Number" mask="0xF0000"/>
<bitfield name="RRLVLEN2" caption="Level 2 Round-Robin Scheduling Enable" mask="0x800000"/>
<bitfield name="LVLPRI3" caption="Level 3 Channel Priority Number" mask="0xF000000"/>
<bitfield name="RRLVLEN3" caption="Level 3 Round-Robin Scheduling Enable" mask="0x80000000"/>
</register>
<register name="INTPEND" offset="0x20" rw="RW" size="2" initval="0x0000" caption="Interrupt Pending">
<bitfield name="ID" caption="Channel ID" mask="0xF"/>
<bitfield name="TERR" caption="Transfer Error" mask="0x100"/>
<bitfield name="TCMPL" caption="Transfer Complete" mask="0x200"/>
<bitfield name="SUSP" caption="Channel Suspend" mask="0x400"/>
<bitfield name="FERR" caption="Fetch Error" mask="0x2000"/>
<bitfield name="BUSY" caption="Busy" mask="0x4000"/>
<bitfield name="PEND" caption="Pending" mask="0x8000"/>
</register>
<register name="INTSTATUS" offset="0x24" rw="R" size="4" initval="0x00000000" caption="Interrupt Status">
<bitfield name="CHINT0" caption="Channel 0 Pending Interrupt" mask="0x1"/>
<bitfield name="CHINT1" caption="Channel 1 Pending Interrupt" mask="0x2"/>
<bitfield name="CHINT2" caption="Channel 2 Pending Interrupt" mask="0x4"/>
<bitfield name="CHINT3" caption="Channel 3 Pending Interrupt" mask="0x8"/>
<bitfield name="CHINT4" caption="Channel 4 Pending Interrupt" mask="0x10"/>
<bitfield name="CHINT5" caption="Channel 5 Pending Interrupt" mask="0x20"/>
<bitfield name="CHINT6" caption="Channel 6 Pending Interrupt" mask="0x40"/>
<bitfield name="CHINT7" caption="Channel 7 Pending Interrupt" mask="0x80"/>
<bitfield name="CHINT8" caption="Channel 8 Pending Interrupt" mask="0x100"/>
<bitfield name="CHINT9" caption="Channel 9 Pending Interrupt" mask="0x200"/>
<bitfield name="CHINT10" caption="Channel 10 Pending Interrupt" mask="0x400"/>
<bitfield name="CHINT11" caption="Channel 11 Pending Interrupt" mask="0x800"/>
</register>
<register name="BUSYCH" offset="0x28" rw="R" size="4" initval="0x00000000" caption="Busy Channels">
<bitfield name="BUSYCH0" caption="Busy Channel 0" mask="0x1"/>
<bitfield name="BUSYCH1" caption="Busy Channel 1" mask="0x2"/>
<bitfield name="BUSYCH2" caption="Busy Channel 2" mask="0x4"/>
<bitfield name="BUSYCH3" caption="Busy Channel 3" mask="0x8"/>
<bitfield name="BUSYCH4" caption="Busy Channel 4" mask="0x10"/>
<bitfield name="BUSYCH5" caption="Busy Channel 5" mask="0x20"/>
<bitfield name="BUSYCH6" caption="Busy Channel 6" mask="0x40"/>
<bitfield name="BUSYCH7" caption="Busy Channel 7" mask="0x80"/>
<bitfield name="BUSYCH8" caption="Busy Channel 8" mask="0x100"/>
<bitfield name="BUSYCH9" caption="Busy Channel 9" mask="0x200"/>
<bitfield name="BUSYCH10" caption="Busy Channel 10" mask="0x400"/>
<bitfield name="BUSYCH11" caption="Busy Channel 11" mask="0x800"/>
</register>
<register name="PENDCH" offset="0x2C" rw="R" size="4" initval="0x00000000" caption="Pending Channels">
<bitfield name="PENDCH0" caption="Pending Channel 0" mask="0x1"/>
<bitfield name="PENDCH1" caption="Pending Channel 1" mask="0x2"/>
<bitfield name="PENDCH2" caption="Pending Channel 2" mask="0x4"/>
<bitfield name="PENDCH3" caption="Pending Channel 3" mask="0x8"/>
<bitfield name="PENDCH4" caption="Pending Channel 4" mask="0x10"/>
<bitfield name="PENDCH5" caption="Pending Channel 5" mask="0x20"/>
<bitfield name="PENDCH6" caption="Pending Channel 6" mask="0x40"/>
<bitfield name="PENDCH7" caption="Pending Channel 7" mask="0x80"/>
<bitfield name="PENDCH8" caption="Pending Channel 8" mask="0x100"/>
<bitfield name="PENDCH9" caption="Pending Channel 9" mask="0x200"/>
<bitfield name="PENDCH10" caption="Pending Channel 10" mask="0x400"/>
<bitfield name="PENDCH11" caption="Pending Channel 11" mask="0x800"/>
</register>
<register name="ACTIVE" offset="0x30" rw="R" size="4" initval="0x00000000" caption="Active Channel and Levels">
<bitfield name="LVLEX0" caption="Level 0 Channel Trigger Request Executing" mask="0x1"/>
<bitfield name="LVLEX1" caption="Level 1 Channel Trigger Request Executing" mask="0x2"/>
<bitfield name="LVLEX2" caption="Level 2 Channel Trigger Request Executing" mask="0x4"/>
<bitfield name="LVLEX3" caption="Level 3 Channel Trigger Request Executing" mask="0x8"/>
<bitfield name="ID" caption="Active Channel ID" mask="0x1F00"/>
<bitfield name="ABUSY" caption="Active Channel Busy" mask="0x8000"/>
<bitfield name="BTCNT" caption="Active Channel Block Transfer Count" mask="0xFFFF0000"/>
</register>
<register name="BASEADDR" offset="0x34" rw="RW" size="4" initval="0x00000000" caption="Descriptor Memory Section Base Address">
<bitfield name="BASEADDR" caption="Descriptor Memory Base Address" mask="0xFFFFFFFF"/>
</register>
<register name="WRBADDR" offset="0x38" rw="RW" size="4" initval="0x00000000" caption="Write-Back Memory Section Base Address">
<bitfield name="WRBADDR" caption="Write-Back Memory Base Address" mask="0xFFFFFFFF"/>
</register>
<register name="CHID" offset="0x3F" rw="RW" size="1" initval="0x00" caption="Channel ID">
<bitfield name="ID" caption="Channel ID" mask="0xF"/>
</register>
<register name="CHCTRLA" offset="0x40" rw="RW" size="1" initval="0x00" caption="Channel Control A">
<bitfield name="SWRST" caption="Channel Software Reset" mask="0x1"/>
<bitfield name="ENABLE" caption="Channel Enable" mask="0x2"/>
</register>
<register name="CHCTRLB" offset="0x44" rw="RW" size="4" initval="0x00000000" caption="Channel Control B">
<bitfield name="EVACT" caption="Event Input Action" mask="0x7" values="DMAC_CHCTRLB__EVACT"/>
<bitfield name="EVIE" caption="Channel Event Input Enable" mask="0x8"/>
<bitfield name="EVOE" caption="Channel Event Output Enable" mask="0x10"/>
<bitfield name="LVL" caption="Channel Arbitration Level" mask="0x60" values="DMAC_CHCTRLB__LVL"/>
<bitfield name="TRIGSRC" caption="Peripheral Trigger Source" mask="0x3F00" values="DMAC_CHCTRLB__TRIGSRC"/>
<bitfield name="TRIGACT" caption="Trigger Action" mask="0xC00000" values="DMAC_CHCTRLB__TRIGACT"/>
<bitfield name="CMD" caption="Software Command" mask="0x3000000" values="DMAC_CHCTRLB__CMD"/>
</register>
<register name="CHINTENCLR" offset="0x4C" rw="RW" size="1" atomic-op="clear:CHINTENCLR" initval="0x00" caption="Channel Interrupt Enable Clear">
<bitfield name="TERR" caption="Transfer Error Interrupt Enable" mask="0x1"/>
<bitfield name="TCMPL" caption="Transfer Complete Interrupt Enable" mask="0x2"/>
<bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
</register>
<register name="CHINTENSET" offset="0x4D" rw="RW" size="1" atomic-op="set:CHINTENSET" initval="0x00" caption="Channel Interrupt Enable Set">
<bitfield name="TERR" caption="Transfer Error Interrupt Enable" mask="0x1"/>
<bitfield name="TCMPL" caption="Transfer Complete Interrupt Enable" mask="0x2"/>
<bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
</register>
<register name="CHINTFLAG" offset="0x4E" rw="RW" size="1" atomic-op="clear:CHINTFLAG" initval="0x00" caption="Channel Interrupt Flag Status and Clear">
<bitfield name="TERR" caption="Transfer Error" mask="0x1"/>
<bitfield name="TCMPL" caption="Transfer Complete" mask="0x2"/>
<bitfield name="SUSP" caption="Channel Suspend" mask="0x4"/>
</register>
<register name="CHSTATUS" offset="0x4F" rw="R" size="1" initval="0x00" caption="Channel Status">
<bitfield name="PEND" caption="Channel Pending" mask="0x1"/>
<bitfield name="BUSY" caption="Channel Busy" mask="0x2"/>
<bitfield name="FERR" caption="Fetch Error" mask="0x4"/>
</register>
</register-group>
<register-group name="DMAC_DESCRIPTOR" caption="Direct Memory Access Controller" aligned="8">
<register name="BTCTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Block Transfer Control">
<bitfield name="VALID" caption="Descriptor Valid" mask="0x1"/>
<bitfield name="EVOSEL" caption="Event Output Selection" mask="0x6" values="DMAC_BTCTRL__EVOSEL"/>
<bitfield name="BLOCKACT" caption="Block Action" mask="0x18" values="DMAC_BTCTRL__BLOCKACT"/>
<bitfield name="BEATSIZE" caption="Beat Size" mask="0x300" values="DMAC_BTCTRL__BEATSIZE"/>
<bitfield name="SRCINC" caption="Source Address Increment Enable" mask="0x400"/>
<bitfield name="DSTINC" caption="Destination Address Increment Enable" mask="0x800"/>
<bitfield name="STEPSEL" caption="Step Selection" mask="0x1000" values="DMAC_BTCTRL__STEPSEL"/>
<bitfield name="STEPSIZE" caption="Address Increment Step Size" mask="0xE000" values="DMAC_BTCTRL__STEPSIZE"/>
</register>
<register name="BTCNT" offset="0x2" rw="RW" size="2" caption="Block Transfer Count">
<bitfield name="BTCNT" caption="Block Transfer Count" mask="0xFFFF"/>
</register>
<register name="SRCADDR" offset="0x4" rw="RW" size="4" caption="Transfer Source Address">
<bitfield name="SRCADDR" caption="Transfer Source Address" mask="0xFFFFFFFF"/>
</register>
<register name="DSTADDR" offset="0x8" rw="RW" size="4" caption="Transfer Destination Address">
<bitfield name="DSTADDR" caption="Transfer Destination Address" mask="0xFFFFFFFF"/>
</register>
<register name="DESCADDR" offset="0xC" rw="RW" size="4" caption="Next Descriptor Address">
<bitfield name="DESCADDR" caption="Next Descriptor Address" mask="0xFFFFFFFF"/>
</register>
</register-group>
<value-group name="DMAC_BTCTRL__BEATSIZE">
<value name="BYTE" caption="8-bit access" value="0x0"/>
<value name="HWORD" caption="16-bit access" value="0x1"/>
<value name="WORD" caption="32-bit access" value="0x2"/>
</value-group>
<value-group name="DMAC_BTCTRL__BLOCKACT">
<value name="NOACT" caption="No action" value="0x0"/>
<value name="INT" caption="Channel in normal operation and block interrupt" value="0x1"/>
<value name="SUSPEND" caption="Channel suspend operation is completed" value="0x2"/>
<value name="BOTH" caption="Both channel suspend operation and block interrupt" value="0x3"/>
</value-group>
<value-group name="DMAC_BTCTRL__EVOSEL">
<value name="DISABLE" caption="Event generation disabled" value="0x0"/>
<value name="BLOCK" caption="Event strobe when block transfer complete" value="0x1"/>
<value name="BEAT" caption="Event strobe when beat transfer complete" value="0x3"/>
</value-group>
<value-group name="DMAC_BTCTRL__STEPSEL">
<value name="DST" caption="Step size settings apply to the destination address" value="0x0"/>
<value name="SRC" caption="Step size settings apply to the source address" value="0x1"/>
</value-group>
<value-group name="DMAC_BTCTRL__STEPSIZE">
<value name="X1" caption="Next ADDR &lt;- ADDR + (1&lt;&lt;BEATSIZE) * 1" value="0x0"/>
<value name="X2" caption="Next ADDR &lt;- ADDR + (1&lt;&lt;BEATSIZE) * 2" value="0x1"/>
<value name="X4" caption="Next ADDR &lt;- ADDR + (1&lt;&lt;BEATSIZE) * 4" value="0x2"/>
<value name="X8" caption="Next ADDR &lt;- ADDR + (1&lt;&lt;BEATSIZE) * 8" value="0x3"/>
<value name="X16" caption="Next ADDR &lt;- ADDR + (1&lt;&lt;BEATSIZE) * 16" value="0x4"/>
<value name="X32" caption="Next ADDR &lt;- ADDR + (1&lt;&lt;BEATSIZE) * 32" value="0x5"/>
<value name="X64" caption="Next ADDR &lt;- ADDR + (1&lt;&lt;BEATSIZE) * 64" value="0x6"/>
<value name="X128" caption="Next ADDR &lt;- ADDR + (1&lt;&lt;BEATSIZE) * 128" value="0x7"/>
</value-group>
<value-group name="DMAC_CRCCTRL__CRCBEATSIZE">
<value name="BYTE" caption="Byte bus access" value="0x0"/>
<value name="HWORD" caption="Half-word bus access" value="0x1"/>
<value name="WORD" caption="Word bus access" value="0x2"/>
</value-group>
<value-group name="DMAC_CRCCTRL__CRCPOLY">
<value name="CRC16" caption="CRC-16 (CRC-CCITT)" value="0x0"/>
<value name="CRC32" caption="CRC32 (IEEE 802.3)" value="0x1"/>
</value-group>
<value-group name="DMAC_CRCCTRL__CRCSRC">
<value name="NOACT" caption="No action" value="0x00"/>
<value name="IO" caption="I/O interface" value="0x01"/>
</value-group>
<value-group name="DMAC_QOSCTRL__DQOS">
<value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
<value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
<value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
<value name="HIGH" caption="Critical Latency" value="0x3"/>
</value-group>
<value-group name="DMAC_QOSCTRL__FQOS">
<value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
<value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
<value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
<value name="HIGH" caption="Critical Latency" value="0x3"/>
</value-group>
<value-group name="DMAC_QOSCTRL__WRBQOS">
<value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
<value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
<value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
<value name="HIGH" caption="Critical Latency" value="0x3"/>
</value-group>
<value-group name="DMAC_CHCTRLB__CMD">
<value name="NOACT" caption="No action" value="0x0"/>
<value name="SUSPEND" caption="Channel suspend operation" value="0x1"/>
<value name="RESUME" caption="Channel resume operation" value="0x2"/>
</value-group>
<value-group name="DMAC_CHCTRLB__EVACT">
<value name="NOACT" caption="No action" value="0x0"/>
<value name="TRIG" caption="Transfer and periodic transfer trigger" value="0x1"/>
<value name="CTRIG" caption="Conditional transfer trigger" value="0x2"/>
<value name="CBLOCK" caption="Conditional block transfer" value="0x3"/>
<value name="SUSPEND" caption="Channel suspend operation" value="0x4"/>
<value name="RESUME" caption="Channel resume operation" value="0x5"/>
<value name="SSKIP" caption="Skip next block suspend action" value="0x6"/>
</value-group>
<value-group name="DMAC_CHCTRLB__LVL">
<value name="LVL0" caption="Channel Priority Level 0" value="0x00"/>
<value name="LVL1" caption="Channel Priority Level 1" value="0x01"/>
<value name="LVL2" caption="Channel Priority Level 2" value="0x02"/>
<value name="LVL3" caption="Channel Priority Level 3" value="0x03"/>
</value-group>
<value-group name="DMAC_CHCTRLB__TRIGACT">
<value name="BLOCK" caption="One trigger required for each block transfer" value="0x0"/>
<value name="BEAT" caption="One trigger required for each beat transfer" value="0x2"/>
<value name="TRANSACTION" caption="One trigger required for each transaction" value="0x3"/>
</value-group>
<value-group name="DMAC_CHCTRLB__TRIGSRC">
<value name="DISABLE" caption="Only software/event triggers" value="0x00"/>
</value-group>
</module>
<module name="DSU" id="U2209" version="2.0.3" caption="Device Service Unit">
<register-group name="DSU" caption="Device Service Unit">
<register name="CTRL" offset="0x0" rw="W" size="1" initval="0x00" caption="Control">
<bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
<bitfield name="CRC" caption="32-bit Cyclic Redundancy Check" mask="0x4"/>
<bitfield name="MBIST" caption="Memory Built-In Self-Test" mask="0x8"/>
<bitfield name="CE" caption="Chip Erase" mask="0x10"/>
</register>
<register name="STATUSA" offset="0x1" rw="RW" size="1" initval="0x00" caption="Status A">
<bitfield name="DONE" caption="Done" mask="0x1"/>
<bitfield name="CRSTEXT" caption="CPU Reset Phase Extension" mask="0x2"/>
<bitfield name="BERR" caption="Bus Error" mask="0x4"/>
<bitfield name="FAIL" caption="Failure" mask="0x8"/>
<bitfield name="PERR" caption="Protection Error" mask="0x10"/>
</register>
<register name="STATUSB" offset="0x2" rw="R" size="1" initval="0x10" caption="Status B">
<bitfield name="PROT" caption="Protected" mask="0x1"/>
<bitfield name="DBGPRES" caption="Debugger Present" mask="0x2"/>
<bitfield name="DCCD0" caption="Debug Communication Channel 0 Dirty" mask="0x4"/>
<bitfield name="DCCD1" caption="Debug Communication Channel 1 Dirty" mask="0x8"/>
<bitfield name="HPE" caption="Hot-Plugging Enable" mask="0x10"/>
</register>
<register name="ADDR" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Address">
<bitfield name="ADDR" caption="Address" mask="0xFFFFFFFC"/>
</register>
<register name="LENGTH" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Length">
<bitfield name="LENGTH" caption="Length" mask="0xFFFFFFFC"/>
</register>
<register name="DATA" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Data">
<bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
</register>
<register name="DCC" offset="0x10" rw="RW" size="4" count="2" initval="0x00000000" caption="Debug Communication Channel n">
<bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
</register>
<register name="DID" offset="0x18" rw="R" size="4" initval="0x10011557" caption="Device Identification">
<bitfield name="DEVSEL" caption="Device Select" mask="0xFF"/>
<bitfield name="REVISION" caption="Revision" mask="0xF00"/>
<bitfield name="DIE" caption="Die Identification" mask="0xF000"/>
<bitfield name="SERIES" caption="Product Series" mask="0x3F0000"/>
<bitfield name="FAMILY" caption="Product Family" mask="0xF800000"/>
<bitfield name="PROCESSOR" caption="Processor" mask="0xF0000000"/>
</register>
<register name="ENTRY0" offset="0x1000" rw="R" size="4" initval="0x9F0FC002" caption="CoreSight ROM Table Entry 0">
<bitfield name="EPRES" caption="Entry Present" mask="0x1"/>
<bitfield name="FMT" caption="Format" mask="0x2"/>
<bitfield name="ADDOFF" caption="Address Offset" mask="0xFFFFF000"/>
</register>
<register name="ENTRY1" offset="0x1004" rw="R" size="4" initval="0x00003002" caption="CoreSight ROM Table Entry 1">
</register>
<register name="END" offset="0x1008" rw="R" size="4" initval="0x00000000" caption="CoreSight ROM Table End">
<bitfield name="END" caption="End Marker" mask="0xFFFFFFFF"/>
</register>
<register name="MEMTYPE" offset="0x1FCC" rw="R" size="4" initval="0x00000000" caption="CoreSight ROM Table Memory Type">
<bitfield name="SMEMP" caption="System Memory Present" mask="0x1"/>
</register>
<register name="PID4" offset="0x1FD0" rw="R" size="4" initval="0x00000000" caption="Peripheral Identification 4">
<bitfield name="JEPCC" caption="JEP-106 Continuation Code" mask="0xF"/>
<bitfield name="FKBC" caption="4KB Count" mask="0xF0"/>
</register>
<register name="PID0" offset="0x1FE0" rw="R" size="4" initval="0x000000D0" caption="Peripheral Identification 0">
<bitfield name="PARTNBL" caption="Part Number Low" mask="0xFF"/>
</register>
<register name="PID1" offset="0x1FE4" rw="R" size="4" initval="0x000000FC" caption="Peripheral Identification 1">
<bitfield name="PARTNBH" caption="Part Number High" mask="0xF"/>
<bitfield name="JEPIDCL" caption="Low part of the JEP-106 Identity Code" mask="0xF0"/>
</register>
<register name="PID2" offset="0x1FE8" rw="R" size="4" initval="0x00000009" caption="Peripheral Identification 2">
<bitfield name="JEPIDCH" caption="JEP-106 Identity Code High" mask="0x7"/>
<bitfield name="JEPU" caption="JEP-106 Identity Code is used" mask="0x8"/>
<bitfield name="REVISION" caption="Revision Number" mask="0xF0"/>
</register>
<register name="PID3" offset="0x1FEC" rw="R" size="4" initval="0x00000000" caption="Peripheral Identification 3">
<bitfield name="CUSMOD" caption="ARM CUSMOD" mask="0xF"/>
<bitfield name="REVAND" caption="Revision Number" mask="0xF0"/>
</register>
<register name="CID0" offset="0x1FF0" rw="R" size="4" initval="0x0000000D" caption="Component Identification 0">
<bitfield name="PREAMBLEB0" caption="Preamble Byte 0" mask="0xFF"/>
</register>
<register name="CID1" offset="0x1FF4" rw="R" size="4" initval="0x00000010" caption="Component Identification 1">
<bitfield name="PREAMBLE" caption="Preamble" mask="0xF"/>
<bitfield name="CCLASS" caption="Component Class" mask="0xF0"/>
</register>
<register name="CID2" offset="0x1FF8" rw="R" size="4" initval="0x00000005" caption="Component Identification 2">
<bitfield name="PREAMBLEB2" caption="Preamble Byte 2" mask="0xFF"/>
</register>
<register name="CID3" offset="0x1FFC" rw="R" size="4" initval="0x000000B1" caption="Component Identification 3">
<bitfield name="PREAMBLEB3" caption="Preamble Byte 3" mask="0xFF"/>
</register>
</register-group>
</module>
<module name="EIC" id="U2217" version="1.0.1" caption="External Interrupt Controller">
<register-group name="EIC" caption="External Interrupt Controller">
<register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
<bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
<bitfield name="ENABLE" caption="Enable" mask="0x2"/>
</register>
<register name="STATUS" offset="0x1" rw="R" size="1" initval="0x00" caption="Status">
<bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
</register>
<register name="NMICTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Non-Maskable Interrupt Control">
<bitfield name="NMISENSE" caption="Non-Maskable Interrupt Sense" mask="0x7" values="EIC_NMICTRL__NMISENSE"/>
<bitfield name="NMIFILTEN" caption="Non-Maskable Interrupt Filter Enable" mask="0x8"/>
</register>
<register name="NMIFLAG" offset="0x3" rw="RW" size="1" atomic-op="clear:NMIFLAG" initval="0x00" caption="Non-Maskable Interrupt Flag Status and Clear">
<bitfield name="NMI" caption="Non-Maskable Interrupt" mask="0x1"/>
</register>
<register name="EVCTRL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Event Control">
<bitfield name="EXTINTEO0" caption="External Interrupt 0 Event Output Enable" mask="0x1"/>
<bitfield name="EXTINTEO1" caption="External Interrupt 1 Event Output Enable" mask="0x2"/>
<bitfield name="EXTINTEO2" caption="External Interrupt 2 Event Output Enable" mask="0x4"/>
<bitfield name="EXTINTEO3" caption="External Interrupt 3 Event Output Enable" mask="0x8"/>
<bitfield name="EXTINTEO4" caption="External Interrupt 4 Event Output Enable" mask="0x10"/>
<bitfield name="EXTINTEO5" caption="External Interrupt 5 Event Output Enable" mask="0x20"/>
<bitfield name="EXTINTEO6" caption="External Interrupt 6 Event Output Enable" mask="0x40"/>
<bitfield name="EXTINTEO7" caption="External Interrupt 7 Event Output Enable" mask="0x80"/>
<bitfield name="EXTINTEO8" caption="External Interrupt 8 Event Output Enable" mask="0x100"/>
<bitfield name="EXTINTEO9" caption="External Interrupt 9 Event Output Enable" mask="0x200"/>
<bitfield name="EXTINTEO10" caption="External Interrupt 10 Event Output Enable" mask="0x400"/>
<bitfield name="EXTINTEO11" caption="External Interrupt 11 Event Output Enable" mask="0x800"/>
<bitfield name="EXTINTEO12" caption="External Interrupt 12 Event Output Enable" mask="0x1000"/>
<bitfield name="EXTINTEO13" caption="External Interrupt 13 Event Output Enable" mask="0x2000"/>
<bitfield name="EXTINTEO14" caption="External Interrupt 14 Event Output Enable" mask="0x4000"/>
<bitfield name="EXTINTEO15" caption="External Interrupt 15 Event Output Enable" mask="0x8000"/>
</register>
<register name="INTENCLR" offset="0x8" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
<bitfield name="EXTINT0" caption="External Interrupt 0 Enable" mask="0x1"/>
<bitfield name="EXTINT1" caption="External Interrupt 1 Enable" mask="0x2"/>
<bitfield name="EXTINT2" caption="External Interrupt 2 Enable" mask="0x4"/>
<bitfield name="EXTINT3" caption="External Interrupt 3 Enable" mask="0x8"/>
<bitfield name="EXTINT4" caption="External Interrupt 4 Enable" mask="0x10"/>
<bitfield name="EXTINT5" caption="External Interrupt 5 Enable" mask="0x20"/>
<bitfield name="EXTINT6" caption="External Interrupt 6 Enable" mask="0x40"/>
<bitfield name="EXTINT7" caption="External Interrupt 7 Enable" mask="0x80"/>
<bitfield name="EXTINT8" caption="External Interrupt 8 Enable" mask="0x100"/>
<bitfield name="EXTINT9" caption="External Interrupt 9 Enable" mask="0x200"/>
<bitfield name="EXTINT10" caption="External Interrupt 10 Enable" mask="0x400"/>
<bitfield name="EXTINT11" caption="External Interrupt 11 Enable" mask="0x800"/>
<bitfield name="EXTINT12" caption="External Interrupt 12 Enable" mask="0x1000"/>
<bitfield name="EXTINT13" caption="External Interrupt 13 Enable" mask="0x2000"/>
<bitfield name="EXTINT14" caption="External Interrupt 14 Enable" mask="0x4000"/>
<bitfield name="EXTINT15" caption="External Interrupt 15 Enable" mask="0x8000"/>
</register>
<register name="INTENSET" offset="0xC" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
<bitfield name="EXTINT0" caption="External Interrupt 0 Enable" mask="0x1"/>
<bitfield name="EXTINT1" caption="External Interrupt 1 Enable" mask="0x2"/>
<bitfield name="EXTINT2" caption="External Interrupt 2 Enable" mask="0x4"/>
<bitfield name="EXTINT3" caption="External Interrupt 3 Enable" mask="0x8"/>
<bitfield name="EXTINT4" caption="External Interrupt 4 Enable" mask="0x10"/>
<bitfield name="EXTINT5" caption="External Interrupt 5 Enable" mask="0x20"/>
<bitfield name="EXTINT6" caption="External Interrupt 6 Enable" mask="0x40"/>
<bitfield name="EXTINT7" caption="External Interrupt 7 Enable" mask="0x80"/>
<bitfield name="EXTINT8" caption="External Interrupt 8 Enable" mask="0x100"/>
<bitfield name="EXTINT9" caption="External Interrupt 9 Enable" mask="0x200"/>
<bitfield name="EXTINT10" caption="External Interrupt 10 Enable" mask="0x400"/>
<bitfield name="EXTINT11" caption="External Interrupt 11 Enable" mask="0x800"/>
<bitfield name="EXTINT12" caption="External Interrupt 12 Enable" mask="0x1000"/>
<bitfield name="EXTINT13" caption="External Interrupt 13 Enable" mask="0x2000"/>
<bitfield name="EXTINT14" caption="External Interrupt 14 Enable" mask="0x4000"/>
<bitfield name="EXTINT15" caption="External Interrupt 15 Enable" mask="0x8000"/>
</register>
<register name="INTFLAG" offset="0x10" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
<bitfield name="EXTINT0" caption="External Interrupt 0" mask="0x1"/>
<bitfield name="EXTINT1" caption="External Interrupt 1" mask="0x2"/>
<bitfield name="EXTINT2" caption="External Interrupt 2" mask="0x4"/>
<bitfield name="EXTINT3" caption="External Interrupt 3" mask="0x8"/>
<bitfield name="EXTINT4" caption="External Interrupt 4" mask="0x10"/>
<bitfield name="EXTINT5" caption="External Interrupt 5" mask="0x20"/>
<bitfield name="EXTINT6" caption="External Interrupt 6" mask="0x40"/>
<bitfield name="EXTINT7" caption="External Interrupt 7" mask="0x80"/>
<bitfield name="EXTINT8" caption="External Interrupt 8" mask="0x100"/>
<bitfield name="EXTINT9" caption="External Interrupt 9" mask="0x200"/>
<bitfield name="EXTINT10" caption="External Interrupt 10" mask="0x400"/>
<bitfield name="EXTINT11" caption="External Interrupt 11" mask="0x800"/>
<bitfield name="EXTINT12" caption="External Interrupt 12" mask="0x1000"/>
<bitfield name="EXTINT13" caption="External Interrupt 13" mask="0x2000"/>
<bitfield name="EXTINT14" caption="External Interrupt 14" mask="0x4000"/>
<bitfield name="EXTINT15" caption="External Interrupt 15" mask="0x8000"/>
</register>
<register name="WAKEUP" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Wake-Up Enable">
<bitfield name="WAKEUPEN0" caption="External Interrupt 0 Wake-up Enable" mask="0x1"/>
<bitfield name="WAKEUPEN1" caption="External Interrupt 1 Wake-up Enable" mask="0x2"/>
<bitfield name="WAKEUPEN2" caption="External Interrupt 2 Wake-up Enable" mask="0x4"/>
<bitfield name="WAKEUPEN3" caption="External Interrupt 3 Wake-up Enable" mask="0x8"/>
<bitfield name="WAKEUPEN4" caption="External Interrupt 4 Wake-up Enable" mask="0x10"/>
<bitfield name="WAKEUPEN5" caption="External Interrupt 5 Wake-up Enable" mask="0x20"/>
<bitfield name="WAKEUPEN6" caption="External Interrupt 6 Wake-up Enable" mask="0x40"/>
<bitfield name="WAKEUPEN7" caption="External Interrupt 7 Wake-up Enable" mask="0x80"/>
<bitfield name="WAKEUPEN8" caption="External Interrupt 8 Wake-up Enable" mask="0x100"/>
<bitfield name="WAKEUPEN9" caption="External Interrupt 9 Wake-up Enable" mask="0x200"/>
<bitfield name="WAKEUPEN10" caption="External Interrupt 10 Wake-up Enable" mask="0x400"/>
<bitfield name="WAKEUPEN11" caption="External Interrupt 11 Wake-up Enable" mask="0x800"/>
<bitfield name="WAKEUPEN12" caption="External Interrupt 12 Wake-up Enable" mask="0x1000"/>
<bitfield name="WAKEUPEN13" caption="External Interrupt 13 Wake-up Enable" mask="0x2000"/>
<bitfield name="WAKEUPEN14" caption="External Interrupt 14 Wake-up Enable" mask="0x4000"/>
<bitfield name="WAKEUPEN15" caption="External Interrupt 15 Wake-up Enable" mask="0x8000"/>
</register>
<register name="CONFIG" offset="0x18" rw="RW" size="4" count="2" initval="0x00000000" caption="Configuration n">
<bitfield name="SENSE0" caption="Input Sense 0 Configuration" mask="0x7" values="EIC_CONFIG__SENSE0"/>
<bitfield name="FILTEN0" caption="Filter 0 Enable" mask="0x8"/>
<bitfield name="SENSE1" caption="Input Sense 1 Configuration" mask="0x70" values="EIC_CONFIG__SENSE1"/>
<bitfield name="FILTEN1" caption="Filter 1 Enable" mask="0x80"/>
<bitfield name="SENSE2" caption="Input Sense 2 Configuration" mask="0x700" values="EIC_CONFIG__SENSE2"/>
<bitfield name="FILTEN2" caption="Filter 2 Enable" mask="0x800"/>
<bitfield name="SENSE3" caption="Input Sense 3 Configuration" mask="0x7000" values="EIC_CONFIG__SENSE3"/>
<bitfield name="FILTEN3" caption="Filter 3 Enable" mask="0x8000"/>
<bitfield name="SENSE4" caption="Input Sense 4 Configuration" mask="0x70000" values="EIC_CONFIG__SENSE4"/>
<bitfield name="FILTEN4" caption="Filter 4 Enable" mask="0x80000"/>
<bitfield name="SENSE5" caption="Input Sense 5 Configuration" mask="0x700000" values="EIC_CONFIG__SENSE5"/>
<bitfield name="FILTEN5" caption="Filter 5 Enable" mask="0x800000"/>
<bitfield name="SENSE6" caption="Input Sense 6 Configuration" mask="0x7000000" values="EIC_CONFIG__SENSE6"/>
<bitfield name="FILTEN6" caption="Filter 6 Enable" mask="0x8000000"/>
<bitfield name="SENSE7" caption="Input Sense 7 Configuration" mask="0x70000000" values="EIC_CONFIG__SENSE7"/>
<bitfield name="FILTEN7" caption="Filter 7 Enable" mask="0x80000000"/>
</register>
</register-group>
<value-group name="EIC_NMICTRL__NMISENSE">
<value name="NONE" caption="No detection" value="0"/>
<value name="RISE" caption="Rising-edge detection" value="1"/>
<value name="FALL" caption="Falling-edge detection" value="2"/>
<value name="BOTH" caption="Both-edges detection" value="3"/>
<value name="HIGH" caption="High-level detection" value="4"/>
<value name="LOW" caption="Low-level detection" value="5"/>
</value-group>
<value-group name="EIC_CONFIG__SENSE0">
<value name="NONE" caption="No detection" value="0"/>
<value name="RISE" caption="Rising-edge detection" value="1"/>
<value name="FALL" caption="Falling-edge detection" value="2"/>
<value name="BOTH" caption="Both-edges detection" value="3"/>
<value name="HIGH" caption="High-level detection" value="4"/>
<value name="LOW" caption="Low-level detection" value="5"/>
</value-group>
<value-group name="EIC_CONFIG__SENSE1">
<value name="NONE" caption="No detection" value="0"/>
<value name="RISE" caption="Rising edge detection" value="1"/>
<value name="FALL" caption="Falling edge detection" value="2"/>
<value name="BOTH" caption="Both edges detection" value="3"/>
<value name="HIGH" caption="High level detection" value="4"/>
<value name="LOW" caption="Low level detection" value="5"/>
</value-group>
<value-group name="EIC_CONFIG__SENSE2">
<value name="NONE" caption="No detection" value="0"/>
<value name="RISE" caption="Rising edge detection" value="1"/>
<value name="FALL" caption="Falling edge detection" value="2"/>
<value name="BOTH" caption="Both edges detection" value="3"/>
<value name="HIGH" caption="High level detection" value="4"/>
<value name="LOW" caption="Low level detection" value="5"/>
</value-group>
<value-group name="EIC_CONFIG__SENSE3">
<value name="NONE" caption="No detection" value="0"/>
<value name="RISE" caption="Rising edge detection" value="1"/>
<value name="FALL" caption="Falling edge detection" value="2"/>
<value name="BOTH" caption="Both edges detection" value="3"/>
<value name="HIGH" caption="High level detection" value="4"/>
<value name="LOW" caption="Low level detection" value="5"/>
</value-group>
<value-group name="EIC_CONFIG__SENSE4">
<value name="NONE" caption="No detection" value="0"/>
<value name="RISE" caption="Rising edge detection" value="1"/>
<value name="FALL" caption="Falling edge detection" value="2"/>
<value name="BOTH" caption="Both edges detection" value="3"/>
<value name="HIGH" caption="High level detection" value="4"/>
<value name="LOW" caption="Low level detection" value="5"/>
</value-group>
<value-group name="EIC_CONFIG__SENSE5">
<value name="NONE" caption="No detection" value="0"/>
<value name="RISE" caption="Rising edge detection" value="1"/>
<value name="FALL" caption="Falling edge detection" value="2"/>
<value name="BOTH" caption="Both edges detection" value="3"/>
<value name="HIGH" caption="High level detection" value="4"/>
<value name="LOW" caption="Low level detection" value="5"/>
</value-group>
<value-group name="EIC_CONFIG__SENSE6">
<value name="NONE" caption="No detection" value="0"/>
<value name="RISE" caption="Rising edge detection" value="1"/>
<value name="FALL" caption="Falling edge detection" value="2"/>
<value name="BOTH" caption="Both edges detection" value="3"/>
<value name="HIGH" caption="High level detection" value="4"/>
<value name="LOW" caption="Low level detection" value="5"/>
</value-group>
<value-group name="EIC_CONFIG__SENSE7">
<value name="NONE" caption="No detection" value="0"/>
<value name="RISE" caption="Rising edge detection" value="1"/>
<value name="FALL" caption="Falling edge detection" value="2"/>
<value name="BOTH" caption="Both edges detection" value="3"/>
<value name="HIGH" caption="High level detection" value="4"/>
<value name="LOW" caption="Low level detection" value="5"/>
</value-group>
</module>
<module name="EVSYS" id="U2208" version="1.0.1" caption="Event System Interface">
<register-group name="EVSYS" caption="Event System Interface">
<register name="CTRL" offset="0x0" rw="W" size="1" initval="0x00" caption="Control">
<bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
<bitfield name="GCLKREQ" caption="Generic Clock Requests" mask="0x10"/>
</register>
<register name="CHANNEL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Channel">
<bitfield name="CHANNEL" caption="Channel Selection" mask="0xF"/>
<bitfield name="SWEVT" caption="Software Event" mask="0x100"/>
<bitfield name="EVGEN" caption="Event Generator Selection" mask="0x7F0000"/>
<bitfield name="PATH" caption="Path Selection" mask="0x3000000" values="EVSYS_CHANNEL__PATH"/>
<bitfield name="EDGSEL" caption="Edge Detection Selection" mask="0xC000000" values="EVSYS_CHANNEL__EDGSEL"/>
</register>
<register name="USER" offset="0x8" rw="RW" size="2" initval="0x0000" caption="User Multiplexer">
<bitfield name="USER" caption="User Multiplexer Selection" mask="0x1F"/>
<bitfield name="CHANNEL" caption="Channel Event Selection" mask="0x1F00" values="EVSYS_USER__CHANNEL"/>
</register>
<register name="CHSTATUS" offset="0xC" rw="R" size="4" initval="0x000F00FF" caption="Channel Status">
<bitfield name="USRRDY0" caption="Channel 0 User Ready" mask="0x1"/>
<bitfield name="USRRDY1" caption="Channel 1 User Ready" mask="0x2"/>
<bitfield name="USRRDY2" caption="Channel 2 User Ready" mask="0x4"/>
<bitfield name="USRRDY3" caption="Channel 3 User Ready" mask="0x8"/>
<bitfield name="USRRDY4" caption="Channel 4 User Ready" mask="0x10"/>
<bitfield name="USRRDY5" caption="Channel 5 User Ready" mask="0x20"/>
<bitfield name="USRRDY6" caption="Channel 6 User Ready" mask="0x40"/>
<bitfield name="USRRDY7" caption="Channel 7 User Ready" mask="0x80"/>
<bitfield name="CHBUSY0" caption="Channel 0 Busy" mask="0x100"/>
<bitfield name="CHBUSY1" caption="Channel 1 Busy" mask="0x200"/>
<bitfield name="CHBUSY2" caption="Channel 2 Busy" mask="0x400"/>
<bitfield name="CHBUSY3" caption="Channel 3 Busy" mask="0x800"/>
<bitfield name="CHBUSY4" caption="Channel 4 Busy" mask="0x1000"/>
<bitfield name="CHBUSY5" caption="Channel 5 Busy" mask="0x2000"/>
<bitfield name="CHBUSY6" caption="Channel 6 Busy" mask="0x4000"/>
<bitfield name="CHBUSY7" caption="Channel 7 Busy" mask="0x8000"/>
<bitfield name="USRRDY8" caption="Channel 8 User Ready" mask="0x10000"/>
<bitfield name="USRRDY9" caption="Channel 9 User Ready" mask="0x20000"/>
<bitfield name="USRRDY10" caption="Channel 10 User Ready" mask="0x40000"/>
<bitfield name="USRRDY11" caption="Channel 11 User Ready" mask="0x80000"/>
<bitfield name="CHBUSY8" caption="Channel 8 Busy" mask="0x1000000"/>
<bitfield name="CHBUSY9" caption="Channel 9 Busy" mask="0x2000000"/>
<bitfield name="CHBUSY10" caption="Channel 10 Busy" mask="0x4000000"/>
<bitfield name="CHBUSY11" caption="Channel 11 Busy" mask="0x8000000"/>
</register>
<register name="INTENCLR" offset="0x10" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
<bitfield name="OVR0" caption="Channel 0 Overrun Interrupt Enable" mask="0x1"/>
<bitfield name="OVR1" caption="Channel 1 Overrun Interrupt Enable" mask="0x2"/>
<bitfield name="OVR2" caption="Channel 2 Overrun Interrupt Enable" mask="0x4"/>
<bitfield name="OVR3" caption="Channel 3 Overrun Interrupt Enable" mask="0x8"/>
<bitfield name="OVR4" caption="Channel 4 Overrun Interrupt Enable" mask="0x10"/>
<bitfield name="OVR5" caption="Channel 5 Overrun Interrupt Enable" mask="0x20"/>
<bitfield name="OVR6" caption="Channel 6 Overrun Interrupt Enable" mask="0x40"/>
<bitfield name="OVR7" caption="Channel 7 Overrun Interrupt Enable" mask="0x80"/>
<bitfield name="EVD0" caption="Channel 0 Event Detection Interrupt Enable" mask="0x100"/>
<bitfield name="EVD1" caption="Channel 1 Event Detection Interrupt Enable" mask="0x200"/>
<bitfield name="EVD2" caption="Channel 2 Event Detection Interrupt Enable" mask="0x400"/>
<bitfield name="EVD3" caption="Channel 3 Event Detection Interrupt Enable" mask="0x800"/>
<bitfield name="EVD4" caption="Channel 4 Event Detection Interrupt Enable" mask="0x1000"/>
<bitfield name="EVD5" caption="Channel 5 Event Detection Interrupt Enable" mask="0x2000"/>
<bitfield name="EVD6" caption="Channel 6 Event Detection Interrupt Enable" mask="0x4000"/>
<bitfield name="EVD7" caption="Channel 7 Event Detection Interrupt Enable" mask="0x8000"/>
<bitfield name="OVR8" caption="Channel 8 Overrun Interrupt Enable" mask="0x10000"/>
<bitfield name="OVR9" caption="Channel 9 Overrun Interrupt Enable" mask="0x20000"/>
<bitfield name="OVR10" caption="Channel 10 Overrun Interrupt Enable" mask="0x40000"/>
<bitfield name="OVR11" caption="Channel 11 Overrun Interrupt Enable" mask="0x80000"/>
<bitfield name="EVD8" caption="Channel 8 Event Detection Interrupt Enable" mask="0x1000000"/>
<bitfield name="EVD9" caption="Channel 9 Event Detection Interrupt Enable" mask="0x2000000"/>
<bitfield name="EVD10" caption="Channel 10 Event Detection Interrupt Enable" mask="0x4000000"/>
<bitfield name="EVD11" caption="Channel 11 Event Detection Interrupt Enable" mask="0x8000000"/>
</register>
<register name="INTENSET" offset="0x14" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
<bitfield name="OVR0" caption="Channel 0 Overrun Interrupt Enable" mask="0x1"/>
<bitfield name="OVR1" caption="Channel 1 Overrun Interrupt Enable" mask="0x2"/>
<bitfield name="OVR2" caption="Channel 2 Overrun Interrupt Enable" mask="0x4"/>
<bitfield name="OVR3" caption="Channel 3 Overrun Interrupt Enable" mask="0x8"/>
<bitfield name="OVR4" caption="Channel 4 Overrun Interrupt Enable" mask="0x10"/>
<bitfield name="OVR5" caption="Channel 5 Overrun Interrupt Enable" mask="0x20"/>
<bitfield name="OVR6" caption="Channel 6 Overrun Interrupt Enable" mask="0x40"/>
<bitfield name="OVR7" caption="Channel 7 Overrun Interrupt Enable" mask="0x80"/>
<bitfield name="EVD0" caption="Channel 0 Event Detection Interrupt Enable" mask="0x100"/>
<bitfield name="EVD1" caption="Channel 1 Event Detection Interrupt Enable" mask="0x200"/>
<bitfield name="EVD2" caption="Channel 2 Event Detection Interrupt Enable" mask="0x400"/>
<bitfield name="EVD3" caption="Channel 3 Event Detection Interrupt Enable" mask="0x800"/>
<bitfield name="EVD4" caption="Channel 4 Event Detection Interrupt Enable" mask="0x1000"/>
<bitfield name="EVD5" caption="Channel 5 Event Detection Interrupt Enable" mask="0x2000"/>
<bitfield name="EVD6" caption="Channel 6 Event Detection Interrupt Enable" mask="0x4000"/>
<bitfield name="EVD7" caption="Channel 7 Event Detection Interrupt Enable" mask="0x8000"/>
<bitfield name="OVR8" caption="Channel 8 Overrun Interrupt Enable" mask="0x10000"/>
<bitfield name="OVR9" caption="Channel 9 Overrun Interrupt Enable" mask="0x20000"/>
<bitfield name="OVR10" caption="Channel 10 Overrun Interrupt Enable" mask="0x40000"/>
<bitfield name="OVR11" caption="Channel 11 Overrun Interrupt Enable" mask="0x80000"/>
<bitfield name="EVD8" caption="Channel 8 Event Detection Interrupt Enable" mask="0x1000000"/>
<bitfield name="EVD9" caption="Channel 9 Event Detection Interrupt Enable" mask="0x2000000"/>
<bitfield name="EVD10" caption="Channel 10 Event Detection Interrupt Enable" mask="0x4000000"/>
<bitfield name="EVD11" caption="Channel 11 Event Detection Interrupt Enable" mask="0x8000000"/>
</register>
<register name="INTFLAG" offset="0x18" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
<bitfield name="OVR0" caption="Channel 0 Overrun" mask="0x1"/>
<bitfield name="OVR1" caption="Channel 1 Overrun" mask="0x2"/>
<bitfield name="OVR2" caption="Channel 2 Overrun" mask="0x4"/>
<bitfield name="OVR3" caption="Channel 3 Overrun" mask="0x8"/>
<bitfield name="OVR4" caption="Channel 4 Overrun" mask="0x10"/>
<bitfield name="OVR5" caption="Channel 5 Overrun" mask="0x20"/>
<bitfield name="OVR6" caption="Channel 6 Overrun" mask="0x40"/>
<bitfield name="OVR7" caption="Channel 7 Overrun" mask="0x80"/>
<bitfield name="EVD0" caption="Channel 0 Event Detection" mask="0x100"/>
<bitfield name="EVD1" caption="Channel 1 Event Detection" mask="0x200"/>
<bitfield name="EVD2" caption="Channel 2 Event Detection" mask="0x400"/>
<bitfield name="EVD3" caption="Channel 3 Event Detection" mask="0x800"/>
<bitfield name="EVD4" caption="Channel 4 Event Detection" mask="0x1000"/>
<bitfield name="EVD5" caption="Channel 5 Event Detection" mask="0x2000"/>
<bitfield name="EVD6" caption="Channel 6 Event Detection" mask="0x4000"/>
<bitfield name="EVD7" caption="Channel 7 Event Detection" mask="0x8000"/>
<bitfield name="OVR8" caption="Channel 8 Overrun" mask="0x10000"/>
<bitfield name="OVR9" caption="Channel 9 Overrun" mask="0x20000"/>
<bitfield name="OVR10" caption="Channel 10 Overrun" mask="0x40000"/>
<bitfield name="OVR11" caption="Channel 11 Overrun" mask="0x80000"/>
<bitfield name="EVD8" caption="Channel 8 Event Detection" mask="0x1000000"/>
<bitfield name="EVD9" caption="Channel 9 Event Detection" mask="0x2000000"/>
<bitfield name="EVD10" caption="Channel 10 Event Detection" mask="0x4000000"/>
<bitfield name="EVD11" caption="Channel 11 Event Detection" mask="0x8000000"/>
</register>
</register-group>
<value-group name="EVSYS_CHANNEL__EDGSEL">
<value name="NO_EVT_OUTPUT" caption="No event output when using the resynchronized or synchronous path" value="0"/>
<value name="RISING_EDGE" caption="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" value="1"/>
<value name="FALLING_EDGE" caption="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" value="2"/>
<value name="BOTH_EDGES" caption="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" value="3"/>
</value-group>
<value-group name="EVSYS_CHANNEL__PATH">
<value name="SYNCHRONOUS" caption="Synchronous path" value="0"/>
<value name="RESYNCHRONIZED" caption="Resynchronized path" value="1"/>
<value name="ASYNCHRONOUS" caption="Asynchronous path" value="2"/>
</value-group>
<value-group name="EVSYS_USER__CHANNEL">
<value name="0" caption="No Channel Output Selected" value="0"/>
</value-group>
</module>
<module name="GCLK" id="U2102" version="2.1.0" caption="Generic Clock Generator">
<register-group name="GCLK" caption="Generic Clock Generator">
<register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
<bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
</register>
<register name="STATUS" offset="0x1" rw="R" size="1" initval="0x00" caption="Status">
<bitfield name="SYNCBUSY" caption="Synchronization Busy Status" mask="0x80"/>
</register>
<register name="CLKCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Generic Clock Control">
<bitfield name="ID" caption="Generic Clock Selection ID" mask="0x3F" values="GCLK_CLKCTRL__ID"/>
<bitfield name="GEN" caption="Generic Clock Generator" mask="0xF00" values="GCLK_CLKCTRL__GEN"/>
<bitfield name="CLKEN" caption="Clock Enable" mask="0x4000"/>
<bitfield name="WRTLOCK" caption="Write Lock" mask="0x8000"/>
</register>
<register name="GENCTRL" offset="0x4" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Generic Clock Generator Control">
<bitfield name="ID" caption="Generic Clock Generator Selection" mask="0xF"/>
<bitfield name="SRC" caption="Source Select" mask="0x1F00" values="GCLK_GENCTRL__SRC"/>
<bitfield name="GENEN" caption="Generic Clock Generator Enable" mask="0x10000"/>
<bitfield name="IDC" caption="Improve Duty Cycle" mask="0x20000"/>
<bitfield name="OOV" caption="Output Off Value" mask="0x40000"/>
<bitfield name="OE" caption="Output Enable" mask="0x80000"/>
<bitfield name="DIVSEL" caption="Divide Selection" mask="0x100000" values="GCLK_GENCTRL__DIVSEL"/>
<bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x200000"/>
</register>
<register name="GENDIV" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Generic Clock Generator Division">
<bitfield name="ID" caption="Generic Clock Generator Selection" mask="0xF"/>
<bitfield name="DIV" caption="Division Factor" mask="0xFFFF00"/>
</register>
</register-group>
<value-group name="GCLK_CLKCTRL__GEN">
<value name="GCLK0" caption="Generic clock generator 0" value="0x0"/>
<value name="GCLK1" caption="Generic clock generator 1" value="0x1"/>
<value name="GCLK2" caption="Generic clock generator 2" value="0x2"/>
<value name="GCLK3" caption="Generic clock generator 3" value="0x3"/>
<value name="GCLK4" caption="Generic clock generator 4" value="0x4"/>
<value name="GCLK5" caption="Generic clock generator 5" value="0x5"/>
<value name="GCLK6" caption="Generic clock generator 6" value="0x6"/>
<value name="GCLK7" caption="Generic clock generator 7" value="0x7"/>
<value name="GCLK8" caption="Generic clock generator 8" value="0x8"/>
</value-group>
<value-group name="GCLK_CLKCTRL__ID">
<value name="DFLL48" caption="DFLL48" value="0x0"/>
<value name="FDPLL" caption="FDPLL" value="0x1"/>
<value name="FDPLL32K" caption="FDPLL32K" value="0x2"/>
<value name="WDT" caption="WDT" value="0x3"/>
<value name="RTC" caption="RTC" value="0x4"/>
<value name="EIC" caption="EIC" value="0x5"/>
<value name="EVSYS_0" caption="EVSYS_0" value="0x7"/>
<value name="EVSYS_1" caption="EVSYS_1" value="0x8"/>
<value name="EVSYS_2" caption="EVSYS_2" value="0x9"/>
<value name="EVSYS_3" caption="EVSYS_3" value="0xA"/>
<value name="EVSYS_4" caption="EVSYS_4" value="0xB"/>
<value name="EVSYS_5" caption="EVSYS_5" value="0xC"/>
<value name="EVSYS_6" caption="EVSYS_6" value="0xD"/>
<value name="EVSYS_7" caption="EVSYS_7" value="0xE"/>
<value name="EVSYS_8" caption="EVSYS_8" value="0xF"/>
<value name="EVSYS_9" caption="EVSYS_9" value="0x10"/>
<value name="EVSYS_10" caption="EVSYS_10" value="0x11"/>
<value name="EVSYS_11" caption="EVSYS_11" value="0x12"/>
<value name="SERCOMX_SLOW" caption="SERCOMX_SLOW" value="0x13"/>
<value name="SERCOM0_CORE" caption="SERCOM0_CORE" value="0x14"/>
<value name="SERCOM1_CORE" caption="SERCOM1_CORE" value="0x15"/>
<value name="SERCOM2_CORE" caption="SERCOM2_CORE" value="0x16"/>
<value name="SERCOM3_CORE" caption="SERCOM3_CORE" value="0x17"/>
<value name="SERCOM4_CORE" caption="SERCOM4_CORE" value="0x18"/>
<value name="SERCOM5_CORE" caption="SERCOM5_CORE" value="0x19"/>
<value name="TCC0_TCC1" caption="TCC0_TCC1" value="0x1A"/>
<value name="TCC2_TC3" caption="TCC2_TC3" value="0x1B"/>
<value name="TC4_TC5" caption="TC4_TC5" value="0x1C"/>
<value name="TC6_TC7" caption="TC6_TC7" value="0x1D"/>
<value name="ADC" caption="ADC" value="0x1E"/>
<value name="AC_DIG" caption="AC_DIG" value="0x1F"/>
<value name="AC_ANA" caption="AC_ANA" value="0x20"/>
<value name="DAC" caption="DAC" value="0x21"/>
<value name="I2S_0" caption="I2S_0" value="0x23"/>
<value name="I2S_1" caption="I2S_1" value="0x24"/>
</value-group>
<value-group name="GCLK_GENCTRL__SRC">
<value name="XOSC" caption="XOSC oscillator output" value="0"/>
<value name="GCLKIN" caption="Generator input pad" value="1"/>
<value name="GCLKGEN1" caption="Generic clock generator 1 output" value="2"/>
<value name="OSCULP32K" caption="OSCULP32K oscillator output" value="3"/>
<value name="OSC32K" caption="OSC32K oscillator output" value="4"/>
<value name="XOSC32K" caption="XOSC32K oscillator output" value="5"/>
<value name="OSC8M" caption="OSC8M oscillator output" value="6"/>
<value name="DFLL48M" caption="DFLL48M output" value="7"/>
<value name="DPLL96M" caption="DPLL96M output" value="8"/>
</value-group>
<value-group name="GCLK_GENCTRL__DIVSEL">
<value name="DIV1" caption="Divide input directly by divider factor" value="0x0"/>
<value name="DIV2" caption="Divide input by 2^(divider factor+ 1)" value="0x1"/>
</value-group>
</module>
<module name="HMATRIXB" id="I7638" version="2.1.2" caption="HSB Matrix">
<register-group name="PRS" size="0x8">
<register name="PRAS" offset="0x0" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Priority A for Slave">
</register>
<register name="PRBS" offset="0x4" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Priority B for Slave">
</register>
</register-group>
<register-group name="HMATRIXB" caption="HSB Matrix">
<register-group name="PRS" name-in-module="PRS" offset="0x080" size="0x8" count="16"/>
<register name="SFR" offset="0x110" rw="RW" size="4" access-size="4" count="16" initval="0x00000000" caption="Special Function">
<bitfield name="SFR" caption="Special Function Register" mask="0xFFFFFFFF"/>
</register>
</register-group>
</module>
<module name="MTB" id="U2002" version="1.0.0" caption="Cortex-M0+ Micro-Trace Buffer">
<register-group name="MTB" caption="Cortex-M0+ Micro-Trace Buffer">
<register name="POSITION" offset="0x0" rw="RW" size="4" access-size="4" caption="MTB Position">
<bitfield name="WRAP" caption="Pointer Value Wraps" mask="0x4"/>
<bitfield name="POINTER" caption="Trace Packet Location Pointer" mask="0xFFFFFFF8"/>
</register>
<register name="MASTER" offset="0x4" rw="RW" size="4" access-size="4" initval="0x00000000" caption="MTB Master">
<bitfield name="MASK" caption="Maximum Value of the Trace Buffer in SRAM" mask="0x1F"/>
<bitfield name="TSTARTEN" caption="Trace Start Input Enable" mask="0x20"/>
<bitfield name="TSTOPEN" caption="Trace Stop Input Enable" mask="0x40"/>
<bitfield name="SFRWPRIV" caption="Special Function Register Write Privilege" mask="0x80"/>
<bitfield name="RAMPRIV" caption="SRAM Privilege" mask="0x100"/>
<bitfield name="HALTREQ" caption="Halt Request" mask="0x200"/>
<bitfield name="EN" caption="Main Trace Enable" mask="0x80000000"/>
</register>
<register name="FLOW" offset="0x8" rw="RW" size="4" access-size="4" initval="0x00000000" caption="MTB Flow">
<bitfield name="AUTOSTOP" caption="Auto Stop Tracing" mask="0x1"/>
<bitfield name="AUTOHALT" caption="Auto Halt Request" mask="0x2"/>
<bitfield name="WATERMARK" caption="Watermark value" mask="0xFFFFFFF8"/>
</register>
<register name="BASE" offset="0xC" rw="R" size="4" access-size="4" caption="MTB Base">
</register>
<register name="ITCTRL" offset="0xF00" rw="RW" size="4" access-size="4" caption="MTB Integration Mode Control">
</register>
<register name="CLAIMSET" offset="0xFA0" rw="RW" size="4" access-size="4" atomic-op="set:CLAIMSET" caption="MTB Claim Set">
</register>
<register name="CLAIMCLR" offset="0xFA4" rw="RW" size="4" access-size="4" atomic-op="clear:CLAIMCLR" caption="MTB Claim Clear">
</register>
<register name="LOCKACCESS" offset="0xFB0" rw="RW" size="4" access-size="4" caption="MTB Lock Access">
</register>
<register name="LOCKSTATUS" offset="0xFB4" rw="R" size="4" access-size="4" caption="MTB Lock Status">
</register>
<register name="AUTHSTATUS" offset="0xFB8" rw="R" size="4" access-size="4" caption="MTB Authentication Status">
</register>
<register name="DEVARCH" offset="0xFBC" rw="R" size="4" access-size="4" caption="MTB Device Architecture">
</register>
<register name="DEVID" offset="0xFC8" rw="R" size="4" access-size="4" caption="MTB Device Configuration">
</register>
<register name="DEVTYPE" offset="0xFCC" rw="R" size="4" access-size="4" caption="MTB Device Type">
</register>
<register name="PID4" offset="0xFD0" rw="R" size="4" access-size="4" caption="CoreSight">
</register>
<register name="PID5" offset="0xFD4" rw="R" size="4" access-size="4" caption="CoreSight">
</register>
<register name="PID6" offset="0xFD8" rw="R" size="4" access-size="4" caption="CoreSight">
</register>
<register name="PID7" offset="0xFDC" rw="R" size="4" access-size="4" caption="CoreSight">
</register>
<register name="PID0" offset="0xFE0" rw="R" size="4" access-size="4" caption="CoreSight">
</register>
<register name="PID1" offset="0xFE4" rw="R" size="4" access-size="4" caption="CoreSight">
</register>
<register name="PID2" offset="0xFE8" rw="R" size="4" access-size="4" caption="CoreSight">
</register>
<register name="PID3" offset="0xFEC" rw="R" size="4" access-size="4" caption="CoreSight">
</register>
<register name="CID0" offset="0xFF0" rw="R" size="4" access-size="4" caption="CoreSight">
</register>
<register name="CID1" offset="0xFF4" rw="R" size="4" access-size="4" caption="CoreSight">
</register>
<register name="CID2" offset="0xFF8" rw="R" size="4" access-size="4" caption="CoreSight">
</register>
<register name="CID3" offset="0xFFC" rw="R" size="4" access-size="4" caption="CoreSight">
</register>
</register-group>
</module>
<module name="NVMCTRL" id="U2207" version="2.0.2" caption="Non-Volatile Memory Controller">
<register-group name="NVMCTRL" caption="Non-Volatile Memory Controller">
<register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
<bitfield name="CMD" caption="Command" mask="0x7F" values="NVMCTRL_CTRLA__CMD"/>
<bitfield name="CMDEX" caption="Command Execution" mask="0xFF00" values="NVMCTRL_CTRLA__CMDEX"/>
</register>
<register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Control B">
<bitfield name="RWS" caption="NVM Read Wait States" mask="0x1E" values="NVMCTRL_CTRLB__RWS"/>
<bitfield name="MANW" caption="Manual Write" mask="0x80"/>
<bitfield name="SLEEPPRM" caption="Power Reduction Mode during Sleep" mask="0x300" values="NVMCTRL_CTRLB__SLEEPPRM"/>
<bitfield name="READMODE" caption="NVMCTRL Read Mode" mask="0x30000" values="NVMCTRL_CTRLB__READMODE"/>
<bitfield name="CACHEDIS" caption="Cache Disable" mask="0x40000"/>
</register>
<register name="PARAM" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="NVM Parameter">
<bitfield name="NVMP" caption="NVM Pages" mask="0xFFFF"/>
<bitfield name="PSZ" caption="Page Size" mask="0x70000" values="NVMCTRL_PARAM__PSZ"/>
<bitfield name="RWWEEP" caption="RWW EEPROM Pages" mask="0xFFF00000"/>
</register>
<register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
<bitfield name="READY" caption="NVM Ready Interrupt Enable" mask="0x1"/>
<bitfield name="ERROR" caption="Error Interrupt Enable" mask="0x2"/>
</register>
<register name="INTENSET" offset="0x10" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
<bitfield name="READY" caption="NVM Ready Interrupt Enable" mask="0x1"/>
<bitfield name="ERROR" caption="Error Interrupt Enable" mask="0x2"/>
</register>
<register name="INTFLAG" offset="0x14" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
<bitfield name="READY" caption="NVM Ready" mask="0x1"/>
<bitfield name="ERROR" caption="Error" mask="0x2"/>
</register>
<register name="STATUS" offset="0x18" rw="RW" size="2" initval="0x0000" caption="Status">
<bitfield name="PRM" caption="Power Reduction Mode" mask="0x1"/>
<bitfield name="LOAD" caption="NVM Page Buffer Active Loading" mask="0x2"/>
<bitfield name="PROGE" caption="Programming Error Status" mask="0x4"/>
<bitfield name="LOCKE" caption="Lock Error Status" mask="0x8"/>
<bitfield name="NVME" caption="NVM Error" mask="0x10"/>
<bitfield name="SB" caption="Security Bit Status" mask="0x100"/>
</register>
<register name="ADDR" offset="0x1C" rw="RW" size="4" initval="0x00000000" caption="Address">
<bitfield name="ADDR" caption="NVM Address" mask="0x3FFFFF"/>
</register>
<register name="LOCK" offset="0x20" rw="RW" size="2" caption="Lock Section">
<bitfield name="LOCK" caption="Region Lock Bits" mask="0xFFFF"/>
</register>
</register-group>
<value-group name="NVMCTRL_CTRLA__CMD">
<value name="ER" caption="Erase Row - Erases the row addressed by the ADDR register." value="0x02"/>
<value name="WP" caption="Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register." value="0x04"/>
<value name="EAR" caption="Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row." value="0x05"/>
<value name="WAP" caption="Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row." value="0x06"/>
<value name="SF" caption="Security Flow Command" value="0x0A"/>
<value name="WL" caption="Write lockbits" value="0x0F"/>
<value name="RWWEEER" caption="RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register." value="0x1A"/>
<value name="RWWEEWP" caption="RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register." value="0x1C"/>
<value name="LR" caption="Lock Region - Locks the region containing the address location in the ADDR register." value="0x40"/>
<value name="UR" caption="Unlock Region - Unlocks the region containing the address location in the ADDR register." value="0x41"/>
<value name="SPRM" caption="Sets the power reduction mode." value="0x42"/>
<value name="CPRM" caption="Clears the power reduction mode." value="0x43"/>
<value name="PBC" caption="Page Buffer Clear - Clears the page buffer." value="0x44"/>
<value name="SSB" caption="Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row." value="0x45"/>
<value name="INVALL" caption="Invalidate all cache lines." value="0x46"/>
</value-group>
<value-group name="NVMCTRL_CTRLA__CMDEX">
<value name="KEY" caption="Execution Key" value="0xA5"/>
</value-group>
<value-group name="NVMCTRL_CTRLB__READMODE">
<value name="NO_MISS_PENALTY" caption="The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance." value="0x0"/>
<value name="LOW_POWER" caption="Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time." value="0x1"/>
<value name="DETERMINISTIC" caption="The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings." value="0x2"/>
</value-group>
<value-group name="NVMCTRL_CTRLB__RWS">
<value name="SINGLE" caption="Single Auto Wait State" value="0"/>
<value name="HALF" caption="Half Auto Wait State" value="1"/>
<value name="DUAL" caption="Dual Auto Wait State" value="2"/>
</value-group>
<value-group name="NVMCTRL_CTRLB__SLEEPPRM">
<value name="WAKEONACCESS" caption="NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access." value="0"/>
<value name="WAKEUPINSTANT" caption="NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep." value="1"/>
<value name="DISABLED" caption="Auto power reduction disabled." value="3"/>
</value-group>
<value-group name="NVMCTRL_PARAM__PSZ">
<value name="8" caption="8 bytes" value="0x0"/>
<value name="16" caption="16 bytes" value="0x1"/>
<value name="32" caption="32 bytes" value="0x2"/>
<value name="64" caption="64 bytes" value="0x3"/>
<value name="128" caption="128 bytes" value="0x4"/>
<value name="256" caption="256 bytes" value="0x5"/>
<value name="512" caption="512 bytes" value="0x6"/>
<value name="1024" caption="1024 bytes" value="0x7"/>
</value-group>
</module>
<module name="FUSES" id="U2207" version="2.0.2" caption="Non-Volatile Fuses">
<register-group name="AUX3_FUSES">
<register name="AUX3_WORD_3" offset="0xC" size="4" rw="R" caption="AUX3 Page Word 3">
<bitfield name="SERIAL_NUMBER_3" caption="Serial Number word 3" mask="0xFFFFFFFF"/>
</register>
<register name="AUX3_WORD_16" offset="0x40" size="4" rw="R" caption="AUX3 Page Word 16">
<bitfield name="SERIAL_NUMBER_0" caption="Serial Number words 2-0 bits 31:0" mask="0xFFFFFFFF"/>
</register>
<register name="AUX3_WORD_17" offset="0x44" size="4" rw="R" caption="AUX3 Page Word 17">
<bitfield name="SERIAL_NUMBER_1" caption="Serial Number words 2-0 bits 63:32" mask="0xFFFFFFFF"/>
</register>
<register name="AUX3_WORD_18" offset="0x48" size="4" rw="R" caption="AUX3 Page Word 18">
<bitfield name="SERIAL_NUMBER_2" caption="Serial Number words 2-0 bits 95:64" mask="0xFFFFFFFF"/>
</register>
</register-group>
<register-group name="OTP4_FUSES">
<register name="OTP4_WORD_0" offset="0x0" size="4" rw="R" caption="OTP4 Page Word 0">
<bitfield name="ADC_LINEARITY_0" caption="ADC Linearity bits 4:0" mask="0xF8000000"/>
</register>
<register name="OTP4_WORD_1" offset="0x4" size="4" rw="R" caption="OTP4 Page Word 1">
<bitfield name="ADC_LINEARITY_1" caption="ADC Linearity bits 7:5" mask="0x7"/>
<bitfield name="ADC_BIASCAL" caption="ADC Bias Calibration" mask="0x38"/>
<bitfield name="OSC32K_CAL" caption="OSC32K Calibration" mask="0x1FC0"/>
<bitfield name="DFLL48M_COARSE_CAL" caption="DFLL48M Coarse Calibration" mask="0xFC000000"/>
</register>
<register name="OTP4_WORD_2" offset="0x8" size="4" rw="R" caption="OTP4 Page Word 2">
<bitfield name="DFLL48M_FINE_CAL" caption="DFLL48M Fine Calibration" mask="0x3FF"/>
</register>
</register-group>
<register-group name="TEMP_LOG_FUSES">
<register name="TEMP_LOG_WORD_0" offset="0x0" size="4" rw="R" caption="TEMP_LOG Page Word 0">
<bitfield name="ROOM_TEMP_VAL_INT" caption="Integer part of room temperature in oC" mask="0xFF"/>
<bitfield name="ROOM_TEMP_VAL_DEC" caption="Decimal part of room temperature" mask="0xF00"/>
<bitfield name="HOT_TEMP_VAL_INT" caption="Integer part of hot temperature in oC" mask="0xFF000"/>
<bitfield name="HOT_TEMP_VAL_DEC" caption="Decimal part of hot temperature" mask="0xF00000"/>
<bitfield name="ROOM_INT1V_VAL" caption="2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value)" mask="0xFF000000"/>
</register>
<register name="TEMP_LOG_WORD_1" offset="0x4" size="4" rw="R" caption="TEMP_LOG Page Word 1">
<bitfield name="HOT_INT1V_VAL" caption="2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value)" mask="0xFF"/>
<bitfield name="ROOM_ADC_VAL" caption="12-bit ADC conversion at room temperature" mask="0xFFF00"/>
<bitfield name="HOT_ADC_VAL" caption="12-bit ADC conversion at hot temperature" mask="0xFFF00000"/>
</register>
</register-group>
<register-group name="USER_FUSES">
<register name="USER_WORD_0" offset="0x0" size="4" rw="RW" caption="USER Page Word 0">
<bitfield name="NVMCTRL_BOOTPROT" caption="Bootloader Size" mask="0x7" values="USER_FUSES_NVMCTRL__BOOTPROT"/>
<bitfield name="NVMCTRL_EEPROM_SIZE" caption="EEPROM Size" mask="0x70" values="USER_FUSES_NVMCTRL__EEPROM_SIZE"/>
<bitfield name="BOD33USERLEVEL" caption="BOD33 User Level" mask="0x3F00"/>
<bitfield name="BOD33_EN" caption="BOD33 Enable" mask="0x4000" values="SYSCTRL_BOD33__ENABLE"/>
<bitfield name="BOD33_ACTION" caption="BOD33 Action" mask="0x18000" values="SYSCTRL_BOD33__ACTION"/>
<bitfield name="WDT_ENABLE" caption="WDT Enable" mask="0x2000000" values="WDT__ENABLE"/>
<bitfield name="WDT_ALWAYSON" caption="WDT Always On" mask="0x4000000" values="WDT__ALWAYSON"/>
<bitfield name="WDT_PER" caption="WDT Period" mask="0x78000000" values="WDT_CONFIG__PER"/>
<bitfield name="WDT_WINDOW_0" caption="WDT Window bit 0" mask="0x80000000"/>
</register>
<register name="USER_WORD_1" offset="0x4" size="4" rw="RW" caption="USER Page Word 1">
<bitfield name="WDT_WINDOW_1" caption="WDT Window bits 3:1" mask="0x7"/>
<bitfield name="WDT_EWOFFSET" caption="WDT Early Warning Offset" mask="0x78" values="WDT_EWCTRL__EWOFFSET"/>
<bitfield name="WDT_WEN" caption="WDT Window Mode Enable" mask="0x80" values="WDT__WEN"/>
<bitfield name="BOD33_HYST" caption="BOD33 Hysteresis" mask="0x100" values="SYSCTRL_BOD33__HYST"/>
<bitfield name="NVMCTRL_REGION_LOCKS" caption="NVM Region Locks" mask="0xFFFF0000"/>
</register>
</register-group>
<value-group name="USER_FUSES_NVMCTRL__BOOTPROT">
<value name="SIZE_0BYTES" caption="0 Bytes" value="0x7"/>
<value name="SIZE_512BYTES" caption="512 Bytes" value="0x6"/>
<value name="SIZE_1024BYTES" caption="1024 Bytes" value="0x5"/>
<value name="SIZE_2048BYTES" caption="2048 Bytes" value="0x4"/>
<value name="SIZE_4096BYTES" caption="4096 Bytes" value="0x3"/>
<value name="SIZE_8192BYTES" caption="8192 Bytes" value="0x2"/>
<value name="SIZE_16384BYTES" caption="16384 Bytes" value="0x1"/>
<value name="SIZE_32768BYTES" caption="32768 Bytes" value="0x0"/>
</value-group>
<value-group name="USER_FUSES_NVMCTRL__EEPROM_SIZE">
<value name="SIZE_0BYTES" caption="0 Bytes" value="0x7"/>
<value name="SIZE_256BYTES" caption="256 Bytes" value="0x6"/>
<value name="SIZE_512BYTES" caption="512 Bytes" value="0x5"/>
<value name="SIZE_1024BYTES" caption="1024 Bytes" value="0x4"/>
<value name="SIZE_2048BYTES" caption="2048 Bytes" value="0x3"/>
<value name="SIZE_4096BYTES" caption="4096 Bytes" value="0x2"/>
<value name="SIZE_8192BYTES" caption="8192 Bytes" value="0x1"/>
<value name="SIZE_16384BYTES" caption="16384 Bytes" value="0x0"/>
</value-group>
<value-group name="SYSCTRL_BOD33__ENABLE">
<value name="DISABLED" caption="BOD33 is disabled" value="0x0"/>
<value name="ENABLED" caption="BOD33 is enabled" value="0x1"/>
</value-group>
<value-group name="SYSCTRL_BOD33__ACTION">
<value name="NONE" caption="No action" value="0x0"/>
<value name="RESET" caption="The BOD33 generates a reset" value="0x1"/>
<value name="INTERRUPT" caption="The BOD33 generates an interrupt" value="0x2"/>
</value-group>
<value-group name="WDT__ENABLE">
<value name="DISABLED" caption="WDT is disabled" value="0x0"/>
<value name="ENABLED" caption="WDT is enabled" value="0x1"/>
</value-group>
<value-group name="WDT__ALWAYSON">
<value name="DISABLED" caption="WDT is enabled and disabled through ENABLE bit" value="0x0"/>
<value name="ENABLED" caption="WDT is enabled and can only be disabled by a power-on reset" value="0x1"/>
</value-group>
<value-group name="WDT_CONFIG__PER">
<value name="CYC8" caption="8 clock cycles" value="0x0"/>
<value name="CYC16" caption="16 clock cycles" value="0x1"/>
<value name="CYC32" caption="32 clock cycles" value="0x2"/>
<value name="CYC64" caption="64 clock cycles" value="0x3"/>
<value name="CYC128" caption="128 clock cycles" value="0x4"/>
<value name="CYC256" caption="256 clock cycles" value="0x5"/>
<value name="CYC512" caption="512 clock cycles" value="0x6"/>
<value name="CYC1024" caption="1024 clock cycles" value="0x7"/>
<value name="CYC2048" caption="2048 clock cycles" value="0x8"/>
<value name="CYC4096" caption="4096 clock cycles" value="0x9"/>
<value name="CYC8192" caption="8192 clock cycles" value="0xA"/>
<value name="CYC16384" caption="16384 clock cycles" value="0xB"/>
</value-group>
<value-group name="WDT_EWCTRL__EWOFFSET">
<value name="CYC8" caption="8 clock cycles" value="0x0"/>
<value name="CYC16" caption="16 clock cycles" value="0x1"/>
<value name="CYC32" caption="32 clock cycles" value="0x2"/>
<value name="CYC64" caption="64 clock cycles" value="0x3"/>
<value name="CYC128" caption="128 clock cycles" value="0x4"/>
<value name="CYC256" caption="256 clock cycles" value="0x5"/>
<value name="CYC512" caption="512 clock cycles" value="0x6"/>
<value name="CYC1024" caption="1024 clock cycles" value="0x7"/>
<value name="CYC2048" caption="2048 clock cycles" value="0x8"/>
<value name="CYC4096" caption="4096 clock cycles" value="0x9"/>
<value name="CYC8192" caption="8192 clock cycles" value="0xA"/>
<value name="CYC16384" caption="16384 clock cycles" value="0xB"/>
</value-group>
<value-group name="WDT__WEN">
<value name="DISABLED" caption="WDT is disabled" value="0x0"/>
<value name="ENABLED" caption="WDT is enabled" value="0x1"/>
</value-group>
<value-group name="SYSCTRL_BOD33__HYST">
<value name="DISABLED" caption="No Hysteresis" value="0x0"/>
<value name="ENABLED" caption="Hysteresis Enabled" value="0x1"/>
</value-group>
</module>
<module name="PAC" id="U2211" version="1.0.1" caption="Peripheral Access Controller">
<register-group name="PAC" caption="Peripheral Access Controller">
<register name="WPCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:WPCLR" initval="0x00000000" caption="Write Protection Clear">
<bitfield name="WP" caption="Write Protection Clear" mask="0xFFFFFFFE"/>
</register>
<register name="WPSET" offset="0x4" rw="RW" size="4" atomic-op="set:WPSET" initval="0x00000000" caption="Write Protection Set">
<bitfield name="WP" caption="Write Protection Set" mask="0xFFFFFFFE"/>
</register>
</register-group>
</module>
<module name="PM" id="U2206" version="2.1.2" caption="Power Manager">
<register-group name="PM" caption="Power Manager">
<register name="CTRL" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control">
</register>
<register name="SLEEP" offset="0x1" rw="RW" size="1" initval="0x00" caption="Sleep Mode">
<bitfield name="IDLE" caption="Idle Mode Configuration" mask="0x3" values="PM_SLEEP__IDLE"/>
</register>
<register name="EXTCTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="External Reset Controller">
<bitfield name="SETDIS" caption="External Reset Disable" mask="0x1"/>
</register>
<register name="CPUSEL" offset="0x8" rw="RW" size="1" initval="0x00" caption="CPU Clock Select">
<bitfield name="CPUDIV" caption="CPU Prescaler Selection" mask="0x7" values="PM_CPUSEL__CPUDIV"/>
</register>
<register name="APBASEL" offset="0x9" rw="RW" size="1" initval="0x00" caption="APBA Clock Select">
<bitfield name="APBADIV" caption="APBA Prescaler Selection" mask="0x7" values="PM_APBASEL__APBADIV"/>
</register>
<register name="APBBSEL" offset="0xA" rw="RW" size="1" initval="0x00" caption="APBB Clock Select">
<bitfield name="APBBDIV" caption="APBB Prescaler Selection" mask="0x7" values="PM_APBBSEL__APBBDIV"/>
</register>
<register name="APBCSEL" offset="0xB" rw="RW" size="1" initval="0x00" caption="APBC Clock Select">
<bitfield name="APBCDIV" caption="APBC Prescaler Selection" mask="0x7" values="PM_APBCSEL__APBCDIV"/>
</register>
<register name="AHBMASK" offset="0x14" rw="RW" size="4" initval="0x0000007F" caption="AHB Mask">
<bitfield name="HPB0_" caption="HPB0 AHB Clock Mask" mask="0x1"/>
<bitfield name="HPB1_" caption="HPB1 AHB Clock Mask" mask="0x2"/>
<bitfield name="HPB2_" caption="HPB2 AHB Clock Mask" mask="0x4"/>
<bitfield name="DSU_" caption="DSU AHB Clock Mask" mask="0x8"/>
<bitfield name="NVMCTRL_" caption="NVMCTRL AHB Clock Mask" mask="0x10"/>
<bitfield name="DMAC_" caption="DMAC AHB Clock Mask" mask="0x20"/>
</register>
<register name="APBAMASK" offset="0x18" rw="RW" size="4" initval="0x0000007F" caption="APBA Mask">
<bitfield name="PAC0_" caption="PAC0 APB Clock Enable" mask="0x1"/>
<bitfield name="PM_" caption="PM APB Clock Enable" mask="0x2"/>
<bitfield name="SYSCTRL_" caption="SYSCTRL APB Clock Enable" mask="0x4"/>
<bitfield name="GCLK_" caption="GCLK APB Clock Enable" mask="0x8"/>
<bitfield name="WDT_" caption="WDT APB Clock Enable" mask="0x10"/>
<bitfield name="RTC_" caption="RTC APB Clock Enable" mask="0x20"/>
<bitfield name="EIC_" caption="EIC APB Clock Enable" mask="0x40"/>
</register>
<register name="APBBMASK" offset="0x1C" rw="RW" size="4" initval="0x0000007F" caption="APBB Mask">
<bitfield name="PAC1_" caption="PAC1 APB Clock Enable" mask="0x1"/>
<bitfield name="DSU_" caption="DSU APB Clock Enable" mask="0x2"/>
<bitfield name="NVMCTRL_" caption="NVMCTRL APB Clock Enable" mask="0x4"/>
<bitfield name="PORT_" caption="PORT APB Clock Enable" mask="0x8"/>
<bitfield name="DMAC_" caption="DMAC APB Clock Enable" mask="0x10"/>
<bitfield name="HMATRIX_" caption="HMATRIX APB Clock Enable" mask="0x40"/>
</register>
<register name="APBCMASK" offset="0x20" rw="RW" size="4" initval="0x00010000" caption="APBC Mask">
<bitfield name="PAC2_" caption="PAC2 APB Clock Enable" mask="0x1"/>
<bitfield name="EVSYS_" caption="EVSYS APB Clock Enable" mask="0x2"/>
<bitfield name="SERCOM0_" caption="SERCOM0 APB Clock Enable" mask="0x4"/>
<bitfield name="SERCOM1_" caption="SERCOM1 APB Clock Enable" mask="0x8"/>
<bitfield name="SERCOM2_" caption="SERCOM2 APB Clock Enable" mask="0x10"/>
<bitfield name="SERCOM3_" caption="SERCOM3 APB Clock Enable" mask="0x20"/>
<bitfield name="SERCOM4_" caption="SERCOM4 APB Clock Enable" mask="0x40"/>
<bitfield name="SERCOM5_" caption="SERCOM5 APB Clock Enable" mask="0x80"/>
<bitfield name="TCC0_" caption="TCC0 APB Clock Enable" mask="0x100"/>
<bitfield name="TCC1_" caption="TCC1 APB Clock Enable" mask="0x200"/>
<bitfield name="TCC2_" caption="TCC2 APB Clock Enable" mask="0x400"/>
<bitfield name="TC3_" caption="TC3 APB Clock Enable" mask="0x800"/>
<bitfield name="TC4_" caption="TC4 APB Clock Enable" mask="0x1000"/>
<bitfield name="TC5_" caption="TC5 APB Clock Enable" mask="0x2000"/>
<bitfield name="TC6_" caption="TC6 APB Clock Enable" mask="0x4000"/>
<bitfield name="TC7_" caption="TC7 APB Clock Enable" mask="0x8000"/>
<bitfield name="ADC_" caption="ADC APB Clock Enable" mask="0x10000"/>
<bitfield name="AC_" caption="AC APB Clock Enable" mask="0x20000"/>
<bitfield name="DAC_" caption="DAC APB Clock Enable" mask="0x40000"/>
<bitfield name="AC1_" caption="AC1 APB Clock Enable" mask="0x200000"/>
</register>
<register name="INTENCLR" offset="0x34" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
<bitfield name="CKRDY" caption="Clock Ready Interrupt Enable" mask="0x1"/>
</register>
<register name="INTENSET" offset="0x35" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
<bitfield name="CKRDY" caption="Clock Ready Interrupt Enable" mask="0x1"/>
</register>
<register name="INTFLAG" offset="0x36" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
<bitfield name="CKRDY" caption="Clock Ready" mask="0x1"/>
</register>
<register name="RCAUSE" offset="0x38" rw="R" size="1" initval="0x01" caption="Reset Cause">
<bitfield name="POR" caption="Power On Reset" mask="0x1"/>
<bitfield name="BOD12" caption="Brown Out 12 Detector Reset" mask="0x2"/>
<bitfield name="BOD33" caption="Brown Out 33 Detector Reset" mask="0x4"/>
<bitfield name="EXT" caption="External Reset" mask="0x10"/>
<bitfield name="WDT" caption="Watchdog Reset" mask="0x20"/>
<bitfield name="SYST" caption="System Reset Request" mask="0x40"/>
</register>
</register-group>
<value-group name="PM_SLEEP__IDLE">
<value name="CPU" caption="The CPU clock domain is stopped" value="0"/>
<value name="AHB" caption="The CPU and AHB clock domains are stopped" value="1"/>
<value name="APB" caption="The CPU, AHB and APB clock domains are stopped" value="2"/>
</value-group>
<value-group name="PM_CPUSEL__CPUDIV">
<value name="DIV1" caption="Divide by 1" value="0"/>
<value name="DIV2" caption="Divide by 2" value="1"/>
<value name="DIV4" caption="Divide by 4" value="2"/>
<value name="DIV8" caption="Divide by 8" value="3"/>
<value name="DIV16" caption="Divide by 16" value="4"/>
<value name="DIV32" caption="Divide by 32" value="5"/>
<value name="DIV64" caption="Divide by 64" value="6"/>
<value name="DIV128" caption="Divide by 128" value="7"/>
</value-group>
<value-group name="PM_APBASEL__APBADIV">
<value name="DIV1" caption="Divide by 1" value="0"/>
<value name="DIV2" caption="Divide by 2" value="1"/>
<value name="DIV4" caption="Divide by 4" value="2"/>
<value name="DIV8" caption="Divide by 8" value="3"/>
<value name="DIV16" caption="Divide by 16" value="4"/>
<value name="DIV32" caption="Divide by 32" value="5"/>
<value name="DIV64" caption="Divide by 64" value="6"/>
<value name="DIV128" caption="Divide by 128" value="7"/>
</value-group>
<value-group name="PM_APBBSEL__APBBDIV">
<value name="DIV1" caption="Divide by 1" value="0"/>
<value name="DIV2" caption="Divide by 2" value="1"/>
<value name="DIV4" caption="Divide by 4" value="2"/>
<value name="DIV8" caption="Divide by 8" value="3"/>
<value name="DIV16" caption="Divide by 16" value="4"/>
<value name="DIV32" caption="Divide by 32" value="5"/>
<value name="DIV64" caption="Divide by 64" value="6"/>
<value name="DIV128" caption="Divide by 128" value="7"/>
</value-group>
<value-group name="PM_APBCSEL__APBCDIV">
<value name="DIV1" caption="Divide by 1" value="0"/>
<value name="DIV2" caption="Divide by 2" value="1"/>
<value name="DIV4" caption="Divide by 4" value="2"/>
<value name="DIV8" caption="Divide by 8" value="3"/>
<value name="DIV16" caption="Divide by 16" value="4"/>
<value name="DIV32" caption="Divide by 32" value="5"/>
<value name="DIV64" caption="Divide by 64" value="6"/>
<value name="DIV128" caption="Divide by 128" value="7"/>
</value-group>
</module>
<module name="PORT" id="U2210" version="1.0.0" caption="Port Module">
<register-group name="GROUP" size="0x80">
<register name="DIR" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Data Direction">
<bitfield name="DIR" caption="Port Data Direction" mask="0xFFFFFFFF"/>
</register>
<register name="DIRCLR" offset="0x4" rw="RW" size="4" atomic-op="clear:DIR" initval="0x00000000" caption="Data Direction Clear">
<bitfield name="DIRCLR" caption="Port Data Direction Clear" mask="0xFFFFFFFF"/>
</register>
<register name="DIRSET" offset="0x8" rw="RW" size="4" atomic-op="set:DIR" initval="0x00000000" caption="Data Direction Set">
<bitfield name="DIRSET" caption="Port Data Direction Set" mask="0xFFFFFFFF"/>
</register>
<register name="DIRTGL" offset="0xC" rw="RW" size="4" atomic-op="toggle:DIR" initval="0x00000000" caption="Data Direction Toggle">
<bitfield name="DIRTGL" caption="Port Data Direction Toggle" mask="0xFFFFFFFF"/>
</register>
<register name="OUT" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Data Output Value">
<bitfield name="OUT" caption="Port Data Output Value" mask="0xFFFFFFFF"/>
</register>
<register name="OUTCLR" offset="0x14" rw="RW" size="4" atomic-op="clear:OUT" initval="0x00000000" caption="Data Output Value Clear">
<bitfield name="OUTCLR" caption="Port Data Output Value Clear" mask="0xFFFFFFFF"/>
</register>
<register name="OUTSET" offset="0x18" rw="RW" size="4" atomic-op="set:OUT" initval="0x00000000" caption="Data Output Value Set">
<bitfield name="OUTSET" caption="Port Data Output Value Set" mask="0xFFFFFFFF"/>
</register>
<register name="OUTTGL" offset="0x1C" rw="RW" size="4" atomic-op="toggle:OUT" initval="0x00000000" caption="Data Output Value Toggle">
<bitfield name="OUTTGL" caption="Port Data Output Value Toggle" mask="0xFFFFFFFF"/>
</register>
<register name="IN" offset="0x20" rw="R" size="4" initval="0x00000000" caption="Data Input Value">
<bitfield name="IN" caption="Port Data Input Value" mask="0xFFFFFFFF"/>
</register>
<register name="CTRL" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Control">
<bitfield name="SAMPLING" caption="Input Sampling Mode" mask="0xFFFFFFFF"/>
</register>
<register name="WRCONFIG" offset="0x28" rw="W" size="4" access-size="4" initval="0x00000000" caption="Write Configuration">
<bitfield name="PINMASK" caption="Pin Mask for Multiple Pin Configuration" mask="0xFFFF"/>
<bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x10000"/>
<bitfield name="INEN" caption="Input Enable" mask="0x20000"/>
<bitfield name="PULLEN" caption="Pull Enable" mask="0x40000"/>
<bitfield name="DRVSTR" caption="Output Driver Strength Selection" mask="0x400000"/>
<bitfield name="PMUX" caption="Peripheral Multiplexing" mask="0xF000000"/>
<bitfield name="WRPMUX" caption="Write PMUX" mask="0x10000000"/>
<bitfield name="WRPINCFG" caption="Write PINCFG" mask="0x40000000"/>
<bitfield name="HWSEL" caption="Half-Word Select" mask="0x80000000"/>
</register>
<register name="PMUX" offset="0x30" rw="RW" size="1" count="16" initval="0x00" caption="Peripheral Multiplexing n">
<bitfield name="PMUXE" caption="Peripheral Multiplexing Even" mask="0xF" values="PORT_PMUX__PMUXE"/>
<bitfield name="PMUXO" caption="Peripheral Multiplexing Odd" mask="0xF0" values="PORT_PMUX__PMUXO"/>
</register>
<register name="PINCFG" offset="0x40" rw="RW" size="1" count="32" initval="0x00" caption="Pin Configuration n">
<bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x1"/>
<bitfield name="INEN" caption="Input Enable" mask="0x2"/>
<bitfield name="PULLEN" caption="Pull Enable" mask="0x4"/>
<bitfield name="DRVSTR" caption="Output Driver Strength Selection" mask="0x40"/>
</register>
</register-group>
<register-group name="PORT" caption="Port Module">
<register-group name="GROUP" name-in-module="GROUP" offset="0x00" size="0x80" count="2"/>
</register-group>
<value-group name="PORT_PMUX__PMUXE">
<value name="A" caption="Peripheral function A selected" value="0x0"/>
<value name="B" caption="Peripheral function B selected" value="0x1"/>
<value name="C" caption="Peripheral function C selected" value="0x2"/>
<value name="D" caption="Peripheral function D selected" value="0x3"/>
<value name="E" caption="Peripheral function E selected" value="0x4"/>
<value name="F" caption="Peripheral function F selected" value="0x5"/>
<value name="G" caption="Peripheral function G selected" value="0x6"/>
<value name="H" caption="Peripheral function H selected" value="0x7"/>
</value-group>
<value-group name="PORT_PMUX__PMUXO">
<value name="A" caption="Peripheral function A selected" value="0x0"/>
<value name="B" caption="Peripheral function B selected" value="0x1"/>
<value name="C" caption="Peripheral function C selected" value="0x2"/>
<value name="D" caption="Peripheral function D selected" value="0x3"/>
<value name="E" caption="Peripheral function E selected" value="0x4"/>
<value name="F" caption="Peripheral function F selected" value="0x5"/>
<value name="G" caption="Peripheral function G selected" value="0x6"/>
<value name="H" caption="Peripheral function H selected" value="0x7"/>
</value-group>
</module>
<module name="RTC" id="U2202" version="1.0.1" caption="Real-Time Counter">
<register-group name="RTC" caption="Real-Time Counter">
<mode name="MODE0" qualifier="RTC.MODE0.CTRL.MODE" value="0" caption="32-bit Counter with Single 32-bit Compare"/>
<mode name="MODE1" qualifier="RTC.MODE1.CTRL.MODE" value="1" caption="16-bit Counter with Two 16-bit Compares"/>
<mode name="MODE2" qualifier="RTC.MODE2.CTRL.MODE" value="2" caption="Clock/Calendar with Alarm"/>
<register modes="MODE0" name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE0 Control">
<bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
<bitfield name="ENABLE" caption="Enable" mask="0x2"/>
<bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE0_CTRL__MODE"/>
<bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
<bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE0_CTRL__PRESCALER"/>
</register>
<register modes="MODE1" name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Control">
<bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
<bitfield name="ENABLE" caption="Enable" mask="0x2"/>
<bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE1_CTRL__MODE"/>
<bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE1_CTRL__PRESCALER"/>
</register>
<register modes="MODE2" name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE2 Control">
<bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
<bitfield name="ENABLE" caption="Enable" mask="0x2"/>
<bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE2_CTRL__MODE"/>
<bitfield name="CLKREP" caption="Clock Representation" mask="0x40"/>
<bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
<bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE2_CTRL__PRESCALER"/>
</register>
<register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
<bitfield name="ADDR" caption="Address" mask="0x3F"/>
<bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
<bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
</register>
<register modes="MODE0" name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE0 Event Control">
<bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
<bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
<bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
<bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
<bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
<bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
<bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
<bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
<bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
<bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
</register>
<register modes="MODE1" name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE1 Event Control">
<bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
<bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
<bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
<bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
<bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
<bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
<bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
<bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
<bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
<bitfield name="CMPEO1" caption="Compare 1 Event Output Enable" mask="0x200"/>
<bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
</register>
<register modes="MODE2" name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE2 Event Control">
<bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
<bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
<bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
<bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
<bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
<bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
<bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
<bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
<bitfield name="ALARMEO0" caption="Alarm 0 Event Output Enable" mask="0x100"/>
<bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
</register>
<register modes="MODE0" name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE0 Interrupt Enable Clear">
<bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
<bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
<bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
</register>
<register modes="MODE1" name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE1 Interrupt Enable Clear">
<bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
<bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x2"/>
<bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
<bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
</register>
<register modes="MODE2" name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE2 Interrupt Enable Clear">
<bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x1"/>
<bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
<bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
</register>
<register modes="MODE0" name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE0 Interrupt Enable Set">
<bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
<bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
<bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
</register>
<register modes="MODE1" name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE1 Interrupt Enable Set">
<bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
<bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x2"/>
<bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
<bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
</register>
<register modes="MODE2" name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE2 Interrupt Enable Set">
<bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x1"/>
<bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
<bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
</register>
<register modes="MODE0" name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE0 Interrupt Flag Status and Clear">
<bitfield name="CMP0" caption="Compare 0" mask="0x1"/>
<bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
<bitfield name="OVF" caption="Overflow" mask="0x80"/>
</register>
<register modes="MODE1" name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE1 Interrupt Flag Status and Clear">
<bitfield name="CMP0" caption="Compare 0" mask="0x1"/>
<bitfield name="CMP1" caption="Compare 1" mask="0x2"/>
<bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
<bitfield name="OVF" caption="Overflow" mask="0x80"/>
</register>
<register modes="MODE2" name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE2 Interrupt Flag Status and Clear">
<bitfield name="ALARM0" caption="Alarm 0" mask="0x1"/>
<bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
<bitfield name="OVF" caption="Overflow" mask="0x80"/>
</register>
<register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
<bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
</register>
<register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
<bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
</register>
<register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
<bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
<bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
</register>
<register modes="MODE0" name="COUNT" offset="0x10" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="MODE0 Counter Value">
<bitfield name="COUNT" caption="Counter Value" mask="0xFFFFFFFF"/>
</register>
<register modes="MODE1" name="COUNT" offset="0x10" rw="RW" access="RWSYNC" size="2" initval="0x0000" caption="MODE1 Counter Value">
<bitfield name="COUNT" caption="Counter Value" mask="0xFFFF"/>
</register>
<register modes="MODE2" name="CLOCK" offset="0x10" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="MODE2 Clock Value">
<bitfield name="SECOND" caption="Second" mask="0x3F"/>
<bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
<bitfield name="HOUR" caption="Hour" mask="0x1F000" values="RTC_MODE2_CLOCK__HOUR"/>
<bitfield name="DAY" caption="Day" mask="0x3E0000"/>
<bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
<bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
</register>
<register modes="MODE1" name="PER" offset="0x14" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Counter Period">
<bitfield name="PER" caption="Counter Period" mask="0xFFFF"/>
</register>
<register modes="MODE0" name="COMP" offset="0x18" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="MODE0 Compare n Value">
<bitfield name="COMP" caption="Compare Value" mask="0xFFFFFFFF"/>
</register>
<register modes="MODE1" name="COMP" offset="0x18" rw="RW" access="WSYNC" size="2" count="2" initval="0x0000" caption="MODE1 Compare n Value">
<bitfield name="COMP" caption="Compare Value" mask="0xFFFF"/>
</register>
<register modes="MODE2" name="ALARM" offset="0x18" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="MODE2_ALARM Alarm n Value">
<bitfield name="SECOND" caption="Second" mask="0x3F"/>
<bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
<bitfield name="HOUR" caption="Hour" mask="0x1F000" values="RTC_MODE2_ALARM_ALARM__HOUR"/>
<bitfield name="DAY" caption="Day" mask="0x3E0000"/>
<bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
<bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
</register>
<register modes="MODE2" name="MASK" offset="0x1C" rw="RW" access="WSYNC" size="1" initval="0x00" caption="MODE2_ALARM Alarm n Mask">
<bitfield name="SEL" caption="Alarm Mask Selection" mask="0x7" values="RTC_MODE2_ALARM_MASK__SEL"/>
</register>
</register-group>
<value-group name="RTC_MODE0_CTRL__MODE">
<value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
<value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
<value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
</value-group>
<value-group name="RTC_MODE0_CTRL__PRESCALER">
<value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
<value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
<value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
<value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
<value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
<value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
<value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
<value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
<value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
<value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
<value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
</value-group>
<value-group name="RTC_MODE1_CTRL__MODE">
<value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
<value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
<value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
</value-group>
<value-group name="RTC_MODE1_CTRL__PRESCALER">
<value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
<value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
<value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
<value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
<value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
<value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
<value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
<value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
<value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
<value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
<value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
</value-group>
<value-group name="RTC_MODE2_CTRL__MODE">
<value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
<value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
<value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
</value-group>
<value-group name="RTC_MODE2_CTRL__PRESCALER">
<value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
<value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
<value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
<value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
<value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
<value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
<value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
<value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
<value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
<value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
<value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
</value-group>
<value-group name="RTC_MODE2_CLOCK__HOUR">
<value name="AM" caption="AM when CLKREP in 12-hour" value="0x00"/>
<value name="PM" caption="PM when CLKREP in 12-hour" value="0x10"/>
</value-group>
<value-group name="RTC_MODE2_ALARM_ALARM__HOUR">
<value name="AM" caption="Morning hour" value="0x00"/>
<value name="PM" caption="Afternoon hour" value="0x10"/>
</value-group>
<value-group name="RTC_MODE2_ALARM_MASK__SEL">
<value name="OFF" caption="Alarm Disabled" value="0x0"/>
<value name="SS" caption="Match seconds only" value="0x1"/>
<value name="MMSS" caption="Match seconds and minutes only" value="0x2"/>
<value name="HHMMSS" caption="Match seconds, minutes, and hours only" value="0x3"/>
<value name="DDHHMMSS" caption="Match seconds, minutes, hours, and days only" value="0x4"/>
<value name="MMDDHHMMSS" caption="Match seconds, minutes, hours, days, and months only" value="0x5"/>
<value name="YYMMDDHHMMSS" caption="Match seconds, minutes, hours, days, months, and years" value="0x6"/>
</value-group>
</module>
<module name="SERCOM" id="U2201" version="2.2.0" caption="Serial Communication Interface">
<register-group name="SERCOM" caption="Serial Communication Interface">
<mode name="I2CM" qualifier="SERCOM.I2CM_CTRLA.MODE" value="5" caption="I2C Master Mode"/>
<mode name="I2CS" qualifier="SERCOM.I2CS_CTRLA.MODE" value="4" caption="I2C Slave Mode"/>
<mode name="SPIS" qualifier="SERCOM.SPIS_CTRLA.MODE" mask="6" value="2" caption="SPI Slave Mode"/>
<mode name="SPIM" qualifier="SERCOM.SPIM_CTRLA.MODE" mask="6" value="3" caption="SPI Master Mode"/>
<mode name="USART_EXT" qualifier="SERCOM.USART_CTRLA.MODE" mask="6" value="0" caption="USART EXTERNAL CLOCK Mode"/>
<mode name="USART_INT" qualifier="SERCOM.USART_CTRLA.MODE" mask="6" value="1" caption="USART INTERNAL CLOCK Mode"/>
<register modes="I2CM" name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CM Control A">
<bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
<bitfield name="ENABLE" caption="Enable" mask="0x2"/>
<bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_I2CM_CTRLA__MODE"/>
<bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x80"/>
<bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
<bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000" values="SERCOM_I2CM_CTRLA__SDAHOLD"/>
<bitfield name="MEXTTOEN" caption="Master SCL Low Extend Timeout" mask="0x400000"/>
<bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
<bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000" values="SERCOM_I2CM_CTRLA__SPEED"/>
<bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
<bitfield name="INACTOUT" caption="Inactive Time-Out" mask="0x30000000" values="SERCOM_I2CM_CTRLA__INACTOUT"/>
<bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
</register>
<register modes="I2CS" name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CS Control A">
<bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
<bitfield name="ENABLE" caption="Enable" mask="0x2"/>
<bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_I2CM_CTRLA__MODE"/>
<bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
<bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
<bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000" values="SERCOM_I2CM_CTRLA__SDAHOLD"/>
<bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
<bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000" values="SERCOM_I2CM_CTRLA__SPEED"/>
<bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
<bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
</register>
<register modes="SPIM" name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="SPIM Control A">
<bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
<bitfield name="ENABLE" caption="Enable" mask="0x2"/>
<bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_SPIM_CTRLA__MODE"/>
<bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
<bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
<bitfield name="DOPO" caption="Data Out Pinout" mask="0x30000" values="SERCOM_SPIM_CTRLA__DOPO"/>
<bitfield name="DIPO" caption="Data In Pinout" mask="0x300000" values="SERCOM_SPIM_CTRLA__DIPO"/>
<bitfield name="FORM" caption="Frame Format" mask="0xF000000" values="SERCOM_SPIM_CTRLA__FORM"/>
<bitfield name="CPHA" caption="Clock Phase" mask="0x10000000" values="SERCOM_SPIM_CTRLA__CPHA"/>
<bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000" values="SERCOM_SPIM_CTRLA__CPOL"/>
<bitfield name="DORD" caption="Data Order" mask="0x40000000" values="SERCOM_SPIM_CTRLA__DORD"/>
</register>
<register modes="SPIS" name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="SPIS Control A">
<bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
<bitfield name="ENABLE" caption="Enable" mask="0x2"/>
<bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_SPIM_CTRLA__MODE"/>
<bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
<bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
<bitfield name="DOPO" caption="Data Out Pinout" mask="0x30000" values="SERCOM_SPIM_CTRLA__DOPO"/>
<bitfield name="DIPO" caption="Data In Pinout" mask="0x300000" values="SERCOM_SPIM_CTRLA__DIPO"/>
<bitfield name="FORM" caption="Frame Format" mask="0xF000000" values="SERCOM_SPIM_CTRLA__FORM"/>
<bitfield name="CPHA" caption="Clock Phase" mask="0x10000000" values="SERCOM_SPIM_CTRLA__CPHA"/>
<bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000" values="SERCOM_SPIM_CTRLA__CPOL"/>
<bitfield name="DORD" caption="Data Order" mask="0x40000000" values="SERCOM_SPIM_CTRLA__DORD"/>
</register>
<register modes="USART_EXT" name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="USART_EXT Control A">
<bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
<bitfield name="ENABLE" caption="Enable" mask="0x2"/>
<bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_USART_CTRLA__MODE"/>
<bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
<bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
<bitfield name="SAMPR" caption="Sample" mask="0xE000" values="SERCOM_USART_CTRLA__SAMPR"/>
<bitfield name="TXPO" caption="Transmit Data Pinout" mask="0x30000" values="SERCOM_USART_CTRLA__TXPO"/>
<bitfield name="RXPO" caption="Receive Data Pinout" mask="0x300000" values="SERCOM_USART_CTRLA__RXPO"/>
<bitfield name="SAMPA" caption="Sample Adjustment" mask="0xC00000" values="SERCOM_USART_CTRLA__SAMPA"/>
<bitfield name="FORM" caption="Frame Format" mask="0xF000000" values="SERCOM_USART_CTRLA__FORM"/>
<bitfield name="CMODE" caption="Communication Mode" mask="0x10000000" values="SERCOM_USART_CTRLA__CMODE"/>
<bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000" values="SERCOM_USART_CTRLA__CPOL"/>
<bitfield name="DORD" caption="Data Order" mask="0x40000000" values="SERCOM_USART_CTRLA__DORD"/>
</register>
<register modes="USART_INT" name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="USART_INT Control A">
<bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
<bitfield name="ENABLE" caption="Enable" mask="0x2"/>
<bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_USART_CTRLA__MODE"/>
<bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
<bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
<bitfield name="SAMPR" caption="Sample" mask="0xE000" values="SERCOM_USART_CTRLA__SAMPR"/>
<bitfield name="TXPO" caption="Transmit Data Pinout" mask="0x30000" values="SERCOM_USART_CTRLA__TXPO"/>
<bitfield name="RXPO" caption="Receive Data Pinout" mask="0x300000" values="SERCOM_USART_CTRLA__RXPO"/>
<bitfield name="SAMPA" caption="Sample Adjustment" mask="0xC00000" values="SERCOM_USART_CTRLA__SAMPA"/>
<bitfield name="FORM" caption="Frame Format" mask="0xF000000" values="SERCOM_USART_CTRLA__FORM"/>
<bitfield name="CMODE" caption="Communication Mode" mask="0x10000000" values="SERCOM_USART_CTRLA__CMODE"/>
<bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000" values="SERCOM_USART_CTRLA__CPOL"/>
<bitfield name="DORD" caption="Data Order" mask="0x40000000" values="SERCOM_USART_CTRLA__DORD"/>
</register>
<register modes="I2CM" name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="I2CM Control B">
<bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
<bitfield name="QCEN" caption="Quick Command Enable" mask="0x200"/>
<bitfield name="CMD" caption="Command" mask="0x30000"/>
<bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
</register>
<register modes="I2CS" name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="I2CS Control B">
<bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
<bitfield name="GCMD" caption="PMBus Group Command" mask="0x200"/>
<bitfield name="AACKEN" caption="Automatic Address Acknowledge" mask="0x400"/>
<bitfield name="AMODE" caption="Address Mode" mask="0xC000"/>
<bitfield name="CMD" caption="Command" mask="0x30000"/>
<bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
</register>
<register modes="SPIM" name="CTRLB" offset="0x4" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="SPIM Control B">
<bitfield name="CHSIZE" caption="Character Size" mask="0x7" values="SERCOM_SPIM_CTRLB__CHSIZE"/>
<bitfield name="PLOADEN" caption="Data Preload Enable" mask="0x40"/>
<bitfield name="SSDE" caption="Slave Select Low Detect Enable" mask="0x200"/>
<bitfield name="MSSEN" caption="Master Slave Select Enable" mask="0x2000"/>
<bitfield name="AMODE" caption="Address Mode" mask="0xC000" values="SERCOM_SPIM_CTRLB__AMODE"/>
<bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
</register>
<register modes="SPIS" name="CTRLB" offset="0x4" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="SPIS Control B">
<bitfield name="CHSIZE" caption="Character Size" mask="0x7" values="SERCOM_SPIM_CTRLB__CHSIZE"/>
<bitfield name="PLOADEN" caption="Data Preload Enable" mask="0x40"/>
<bitfield name="SSDE" caption="Slave Select Low Detect Enable" mask="0x200"/>
<bitfield name="MSSEN" caption="Master Slave Select Enable" mask="0x2000"/>
<bitfield name="AMODE" caption="Address Mode" mask="0xC000" values="SERCOM_SPIM_CTRLB__AMODE"/>
<bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
</register>
<register modes="USART_EXT" name="CTRLB" offset="0x4" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="USART_EXT Control B">
<bitfield name="CHSIZE" caption="Character Size" mask="0x7" values="SERCOM_USART_CTRLB__CHSIZE"/>
<bitfield name="SBMODE" caption="Stop Bit Mode" mask="0x40" values="SERCOM_USART_CTRLB__SBMODE"/>
<bitfield name="COLDEN" caption="Collision Detection Enable" mask="0x100"/>
<bitfield name="SFDE" caption="Start of Frame Detection Enable" mask="0x200"/>
<bitfield name="ENC" caption="Encoding Format" mask="0x400"/>
<bitfield name="PMODE" caption="Parity Mode" mask="0x2000" values="SERCOM_USART_CTRLB__PMODE"/>
<bitfield name="TXEN" caption="Transmitter Enable" mask="0x10000"/>
<bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
</register>
<register modes="USART_INT" name="CTRLB" offset="0x4" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="USART_INT Control B">
<bitfield name="CHSIZE" caption="Character Size" mask="0x7" values="SERCOM_USART_CTRLB__CHSIZE"/>
<bitfield name="SBMODE" caption="Stop Bit Mode" mask="0x40" values="SERCOM_USART_CTRLB__SBMODE"/>
<bitfield name="COLDEN" caption="Collision Detection Enable" mask="0x100"/>
<bitfield name="SFDE" caption="Start of Frame Detection Enable" mask="0x200"/>
<bitfield name="ENC" caption="Encoding Format" mask="0x400"/>
<bitfield name="PMODE" caption="Parity Mode" mask="0x2000" values="SERCOM_USART_CTRLB__PMODE"/>
<bitfield name="TXEN" caption="Transmitter Enable" mask="0x10000"/>
<bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
</register>
<register modes="I2CM" name="BAUD" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="I2CM Baud Rate">
<bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
<bitfield name="BAUDLOW" caption="Baud Rate Value Low" mask="0xFF00"/>
<bitfield name="HSBAUD" caption="High Speed Baud Rate Value" mask="0xFF0000"/>
<bitfield name="HSBAUDLOW" caption="High Speed Baud Rate Value Low" mask="0xFF000000"/>
</register>
<register modes="SPIM" name="BAUD" offset="0xC" rw="RW" size="1" initval="0x00" caption="SPIM Baud Rate">
<bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
</register>
<register modes="SPIS" name="BAUD" offset="0xC" rw="RW" size="1" initval="0x00" caption="SPIS Baud Rate">
<bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
</register>
<register modes="USART_EXT" name="BAUD" offset="0xC" rw="RW" size="2" initval="0x0000" caption="USART_EXT Baud Rate">
<mode name="DEFAULT"/>
<mode name="FRAC"/>
<mode name="FRACFP"/>
<mode name="USARTFP"/>
<bitfield modes="FRAC FRACFP" name="BAUD" caption="Baud Rate Value" mask="0x1FFF"/>
<bitfield modes="FRAC FRACFP" name="FP" caption="Fractional Part" mask="0xE000"/>
<bitfield modes="DEFAULT USARTFP" name="BAUD" caption="Baud Rate Value" mask="0xFFFF"/>
</register>
<register modes="USART_INT" name="BAUD" offset="0xC" rw="RW" size="2" initval="0x0000" caption="USART_INT Baud Rate">
<mode name="DEFAULT"/>
<mode name="FRAC"/>
<mode name="FRACFP"/>
<mode name="USARTFP"/>
<bitfield modes="FRAC FRACFP" name="BAUD" caption="Baud Rate Value" mask="0x1FFF"/>
<bitfield modes="FRAC FRACFP" name="FP" caption="Fractional Part" mask="0xE000"/>
<bitfield modes="DEFAULT USARTFP" name="BAUD" caption="Baud Rate Value" mask="0xFFFF"/>
</register>
<register modes="USART_EXT" name="RXPL" offset="0xE" rw="RW" size="1" initval="0x00" caption="USART_EXT Receive Pulse Length">
<bitfield name="RXPL" caption="Receive Pulse Length" mask="0xFF"/>
</register>
<register modes="USART_INT" name="RXPL" offset="0xE" rw="RW" size="1" initval="0x00" caption="USART_INT Receive Pulse Length">
<bitfield name="RXPL" caption="Receive Pulse Length" mask="0xFF"/>
</register>
<register modes="I2CM" name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CM Interrupt Enable Clear">
<bitfield name="MB" caption="Master On Bus Interrupt Disable" mask="0x1"/>
<bitfield name="SB" caption="Slave On Bus Interrupt Disable" mask="0x2"/>
<bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
</register>
<register modes="I2CS" name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CS Interrupt Enable Clear">
<bitfield name="PREC" caption="Stop Received Interrupt Disable" mask="0x1"/>
<bitfield name="AMATCH" caption="Address Match Interrupt Disable" mask="0x2"/>
<bitfield name="DRDY" caption="Data Interrupt Disable" mask="0x4"/>
<bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
</register>
<register modes="SPIM" name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="SPIM Interrupt Enable Clear">
<bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
<bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
<bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
<bitfield name="SSL" caption="Slave Select Low Interrupt Disable" mask="0x8"/>
<bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
</register>
<register modes="SPIS" name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="SPIS Interrupt Enable Clear">
<bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
<bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
<bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
<bitfield name="SSL" caption="Slave Select Low Interrupt Disable" mask="0x8"/>
<bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
</register>
<register modes="USART_EXT" name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="USART_EXT Interrupt Enable Clear">
<bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
<bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
<bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
<bitfield name="RXS" caption="Receive Start Interrupt Disable" mask="0x8"/>
<bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Disable" mask="0x10"/>
<bitfield name="RXBRK" caption="Break Received Interrupt Disable" mask="0x20"/>
<bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
</register>
<register modes="USART_INT" name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="USART_INT Interrupt Enable Clear">
<bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
<bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
<bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
<bitfield name="RXS" caption="Receive Start Interrupt Disable" mask="0x8"/>
<bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Disable" mask="0x10"/>
<bitfield name="RXBRK" caption="Break Received Interrupt Disable" mask="0x20"/>
<bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
</register>
<register modes="I2CM" name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CM Interrupt Enable Set">
<bitfield name="MB" caption="Master On Bus Interrupt Enable" mask="0x1"/>
<bitfield name="SB" caption="Slave On Bus Interrupt Enable" mask="0x2"/>
<bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
</register>
<register modes="I2CS" name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CS Interrupt Enable Set">
<bitfield name="PREC" caption="Stop Received Interrupt Enable" mask="0x1"/>
<bitfield name="AMATCH" caption="Address Match Interrupt Enable" mask="0x2"/>
<bitfield name="DRDY" caption="Data Interrupt Enable" mask="0x4"/>
<bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
</register>
<register modes="SPIM" name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="SPIM Interrupt Enable Set">
<bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
<bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
<bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
<bitfield name="SSL" caption="Slave Select Low Interrupt Enable" mask="0x8"/>
<bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
</register>
<register modes="SPIS" name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="SPIS Interrupt Enable Set">
<bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
<bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
<bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
<bitfield name="SSL" caption="Slave Select Low Interrupt Enable" mask="0x8"/>
<bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
</register>
<register modes="USART_EXT" name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="USART_EXT Interrupt Enable Set">
<bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
<bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
<bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
<bitfield name="RXS" caption="Receive Start Interrupt Enable" mask="0x8"/>
<bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Enable" mask="0x10"/>
<bitfield name="RXBRK" caption="Break Received Interrupt Enable" mask="0x20"/>
<bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
</register>
<register modes="USART_INT" name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="USART_INT Interrupt Enable Set">
<bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
<bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
<bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
<bitfield name="RXS" caption="Receive Start Interrupt Enable" mask="0x8"/>
<bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Enable" mask="0x10"/>
<bitfield name="RXBRK" caption="Break Received Interrupt Enable" mask="0x20"/>
<bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
</register>
<register modes="I2CM" name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CM Interrupt Flag Status and Clear">
<bitfield name="MB" caption="Master On Bus Interrupt" mask="0x1"/>
<bitfield name="SB" caption="Slave On Bus Interrupt" mask="0x2"/>
<bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
</register>
<register modes="I2CS" name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CS Interrupt Flag Status and Clear">
<bitfield name="PREC" caption="Stop Received Interrupt" mask="0x1"/>
<bitfield name="AMATCH" caption="Address Match Interrupt" mask="0x2"/>
<bitfield name="DRDY" caption="Data Interrupt" mask="0x4"/>
<bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
</register>
<register modes="SPIM" name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="SPIM Interrupt Flag Status and Clear">
<bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
<bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
<bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
<bitfield name="SSL" caption="Slave Select Low Interrupt Flag" mask="0x8"/>
<bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
</register>
<register modes="SPIS" name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="SPIS Interrupt Flag Status and Clear">
<bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
<bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
<bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
<bitfield name="SSL" caption="Slave Select Low Interrupt Flag" mask="0x8"/>
<bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
</register>
<register modes="USART_EXT" name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="USART_EXT Interrupt Flag Status and Clear">
<bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
<bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
<bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
<bitfield name="RXS" caption="Receive Start Interrupt" mask="0x8"/>
<bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt" mask="0x10"/>
<bitfield name="RXBRK" caption="Break Received Interrupt" mask="0x20"/>
<bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
</register>
<register modes="USART_INT" name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="USART_INT Interrupt Flag Status and Clear">
<bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
<bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
<bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
<bitfield name="RXS" caption="Receive Start Interrupt" mask="0x8"/>
<bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt" mask="0x10"/>
<bitfield name="RXBRK" caption="Break Received Interrupt" mask="0x20"/>
<bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
</register>
<register modes="I2CM" name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="I2CM Status">
<bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
<bitfield name="ARBLOST" caption="Arbitration Lost" mask="0x2"/>
<bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
<bitfield name="BUSSTATE" caption="Bus State" mask="0x30"/>
<bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
<bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
<bitfield name="MEXTTOUT" caption="Master SCL Low Extend Timeout" mask="0x100"/>
<bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
<bitfield name="LENERR" caption="Length Error" mask="0x400"/>
</register>
<register modes="I2CS" name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="I2CS Status">
<bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
<bitfield name="COLL" caption="Transmit Collision" mask="0x2"/>
<bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
<bitfield name="DIR" caption="Read/Write Direction" mask="0x8"/>
<bitfield name="SR" caption="Repeated Start" mask="0x10"/>
<bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
<bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
<bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
<bitfield name="HS" caption="High Speed" mask="0x400"/>
</register>
<register modes="SPIM" name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="SPIM Status">
<bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
</register>
<register modes="SPIS" name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="SPIS Status">
<bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
</register>
<register modes="USART_EXT" name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="USART_EXT Status">
<bitfield name="PERR" caption="Parity Error" mask="0x1"/>
<bitfield name="FERR" caption="Frame Error" mask="0x2"/>
<bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
<bitfield name="CTS" caption="Clear To Send" mask="0x8"/>
<bitfield name="ISF" caption="Inconsistent Sync Field" mask="0x10"/>
<bitfield name="COLL" caption="Collision Detected" mask="0x20"/>
<bitfield name="TXE" caption="Transmitter Empty" mask="0x40"/>
</register>
<register modes="USART_INT" name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="USART_INT Status">
<bitfield name="PERR" caption="Parity Error" mask="0x1"/>
<bitfield name="FERR" caption="Frame Error" mask="0x2"/>
<bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
<bitfield name="CTS" caption="Clear To Send" mask="0x8"/>
<bitfield name="ISF" caption="Inconsistent Sync Field" mask="0x10"/>
<bitfield name="COLL" caption="Collision Detected" mask="0x20"/>
<bitfield name="TXE" caption="Transmitter Empty" mask="0x40"/>
</register>
<register modes="I2CM" name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CM Synchronization Busy">
<bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
<bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
<bitfield name="SYSOP" caption="System Operation Synchronization Busy" mask="0x4"/>
</register>
<register modes="I2CS" name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CS Synchronization Busy">
<bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
<bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
</register>
<register modes="SPIM" name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="SPIM Synchronization Busy">
<bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
<bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
<bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
</register>
<register modes="SPIS" name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="SPIS Synchronization Busy">
<bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
<bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
<bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
</register>
<register modes="USART_EXT" name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="USART_EXT Synchronization Busy">
<bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
<bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
<bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
</register>
<register modes="USART_INT" name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="USART_INT Synchronization Busy">
<bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
<bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
<bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
</register>
<register modes="I2CM" name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="I2CM Address">
<bitfield name="ADDR" caption="Address Value" mask="0x7FF"/>
<bitfield name="LENEN" caption="Length Enable" mask="0x2000"/>
<bitfield name="HS" caption="High Speed Mode" mask="0x4000"/>
<bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
<bitfield name="LEN" caption="Length" mask="0xFF0000"/>
</register>
<register modes="I2CS" name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="I2CS Address">
<bitfield name="GENCEN" caption="General Call Address Enable" mask="0x1"/>
<bitfield name="ADDR" caption="Address Value" mask="0x7FE"/>
<bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
<bitfield name="ADDRMASK" caption="Address Mask" mask="0x7FE0000"/>
</register>
<register modes="SPIM" name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="SPIM Address">
<bitfield name="ADDR" caption="Address Value" mask="0xFF"/>
<bitfield name="ADDRMASK" caption="Address Mask" mask="0xFF0000"/>
</register>
<register modes="SPIS" name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="SPIS Address">
<bitfield name="ADDR" caption="Address Value" mask="0xFF"/>
<bitfield name="ADDRMASK" caption="Address Mask" mask="0xFF0000"/>
</register>
<register modes="I2CM" name="DATA" offset="0x28" rw="RW" size="1" initval="0x00" caption="I2CM Data">
<bitfield name="DATA" caption="Data Value" mask="0xFF"/>
</register>
<register modes="I2CS" name="DATA" offset="0x28" rw="RW" size="1" initval="0x00" caption="I2CS Data">
<bitfield name="DATA" caption="Data Value" mask="0xFF"/>
</register>
<register modes="SPIM" name="DATA" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="SPIM Data">
<bitfield name="DATA" caption="Data Value" mask="0x1FF"/>
</register>
<register modes="SPIS" name="DATA" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="SPIS Data">
<bitfield name="DATA" caption="Data Value" mask="0x1FF"/>
</register>
<register modes="USART_EXT" name="DATA" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USART_EXT Data">
<bitfield name="DATA" caption="Data Value" mask="0x1FF"/>
</register>
<register modes="USART_INT" name="DATA" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USART_INT Data">
<bitfield name="DATA" caption="Data Value" mask="0x1FF"/>
</register>
<register modes="I2CM" name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="I2CM Debug Control">
<bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
</register>
<register modes="SPIM" name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="SPIM Debug Control">
<bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
</register>
<register modes="SPIS" name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="SPIS Debug Control">
<bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
</register>
<register modes="USART_EXT" name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="USART_EXT Debug Control">
<bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
</register>
<register modes="USART_INT" name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="USART_INT Debug Control">
<bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
</register>
</register-group>
<value-group name="SERCOM_I2CM_CTRLA__MODE">
<value name="USART_EXT_CLK" caption="USART with external clock" value="0x0"/>
<value name="USART_INT_CLK" caption="USART with internal clock" value="0x1"/>
<value name="SPI_SLAVE" caption="SPI in slave operation" value="0x2"/>
<value name="SPI_MASTER" caption="SPI in master operation" value="0x3"/>
<value name="I2C_SLAVE" caption="I2C slave operation" value="0x4"/>
<value name="I2C_MASTER" caption="I2C master operation" value="0x5"/>
</value-group>
<value-group name="SERCOM_I2CM_CTRLA__SDAHOLD">
<value name="DISABLE" caption="Disabled" value="0x0"/>
<value name="75NS" caption="50-100ns hold time" value="0x1"/>
<value name="450NS" caption="300-600ns hold time" value="0x2"/>
<value name="600NS" caption="400-800ns hold time" value="0x3"/>
</value-group>
<value-group name="SERCOM_I2CM_CTRLA__SPEED">
<value name="STANDARD_AND_FAST_MODE" caption="Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz " value="0x0"/>
<value name="FASTPLUS_MODE" caption="Fast-mode Plus Upto 1MHz" value="0x1"/>
<value name="HIGH_SPEED_MODE" caption="High-speed mode Upto 3.4MHz" value="0x2"/>
</value-group>
<value-group name="SERCOM_I2CM_CTRLA__INACTOUT">
<value name="DISABLE" caption="Disabled" value="0x0"/>
<value name="55US" caption="5-6 SCL Time-Out(50-60us)" value="0x1"/>
<value name="105US" caption="10-11 SCL Time-Out(100-110us)" value="0x2"/>
<value name="205US" caption="20-21 SCL Time-Out(200-210us)" value="0x3"/>
</value-group>
<value-group name="SERCOM_SPIM_CTRLA__MODE">
<value name="USART_EXT_CLK" caption="USART with external clock" value="0x0"/>
<value name="USART_INT_CLK" caption="USART with internal clock" value="0x1"/>
<value name="SPI_SLAVE" caption="SPI in slave operation" value="0x2"/>
<value name="SPI_MASTER" caption="SPI in master operation" value="0x3"/>
<value name="I2C_SLAVE" caption="I2C slave operation" value="0x4"/>
<value name="I2C_MASTER" caption="I2C master operation" value="0x5"/>
</value-group>
<value-group name="SERCOM_SPIM_CTRLA__CPHA">
<value name="LEADING_EDGE" caption="The data is sampled on a leading SCK edge and changed on a trailing SCK edge" value="0x0"/>
<value name="TRAILING_EDGE" caption="The data is sampled on a trailing SCK edge and changed on a leading SCK edge" value="0x1"/>
</value-group>
<value-group name="SERCOM_SPIM_CTRLA__CPOL">
<value name="IDLE_LOW" caption="SCK is low when idle" value="0x0"/>
<value name="IDLE_HIGH" caption="SCK is high when idle" value="0x1"/>
</value-group>
<value-group name="SERCOM_SPIM_CTRLA__DORD">
<value name="MSB" caption="MSB is transferred first" value="0x0"/>
<value name="LSB" caption="LSB is transferred first" value="0x1"/>
</value-group>
<value-group name="SERCOM_SPIM_CTRLA__DOPO">
<value name="PAD0" caption="DO on PAD[0], SCK on PAD[1] and SS on PAD[2]" value="0x0"/>
<value name="PAD1" caption="DO on PAD[2], SCK on PAD[3] and SS on PAD[1]" value="0x1"/>
<value name="PAD2" caption="DO on PAD[3], SCK on PAD[1] and SS on PAD[2]" value="0x2"/>
<value name="PAD3" caption="DO on PAD[0], SCK on PAD[3] and SS on PAD[1]" value="0x3"/>
</value-group>
<value-group name="SERCOM_SPIM_CTRLA__DIPO">
<value name="PAD0" caption="SERCOM PAD[0]" value="0x0"/>
<value name="PAD1" caption="SERCOM PAD[1]" value="0x1"/>
<value name="PAD2" caption="SERCOM PAD[2]" value="0x2"/>
<value name="PAD3" caption="SERCOM PAD[3]" value="0x3"/>
</value-group>
<value-group name="SERCOM_SPIM_CTRLA__FORM">
<value name="SPI_FRAME" caption="SPI Frame" value="0x0"/>
<value name="SPI_FRAME_WITH_ADDR" caption="SPI Frame with Addr" value="0x2"/>
</value-group>
<value-group name="SERCOM_SPIM_CTRLB__CHSIZE">
<value name="8_BIT" caption="8 bits" value="0x0"/>
<value name="9_BIT" caption="9 bits" value="0x1"/>
</value-group>
<value-group name="SERCOM_SPIM_CTRLB__AMODE">
<value name="MASK" caption="SPI Address mask " value="0x0"/>
<value name="2_ADDRESSES" caption="Two unique Addressess" value="0x1"/>
<value name="RANGE" caption="Address Range" value="0x2"/>
</value-group>
<value-group name="SERCOM_USART_CTRLA__MODE">
<value name="USART_EXT_CLK" caption="USART with external clock" value="0x0"/>
<value name="USART_INT_CLK" caption="USART with internal clock" value="0x1"/>
<value name="SPI_SLAVE" caption="SPI in slave operation" value="0x2"/>
<value name="SPI_MASTER" caption="SPI in master operation" value="0x3"/>
<value name="I2C_SLAVE" caption="I2C slave operation" value="0x4"/>
<value name="I2C_MASTER" caption="I2C master operation" value="0x5"/>
</value-group>
<value-group name="SERCOM_USART_CTRLA__CMODE">
<value name="ASYNC" caption="Asynchronous Communication" value="0x0"/>
<value name="SYNC" caption="Synchronous Communication" value="0x1"/>
</value-group>
<value-group name="SERCOM_USART_CTRLA__CPOL">
<value name="IDLE_LOW" caption="TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge" value="0x0"/>
<value name="IDLE_HIGH" caption="TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge" value="0x1"/>
</value-group>
<value-group name="SERCOM_USART_CTRLA__DORD">
<value name="MSB" caption="MSB is transmitted first" value="0x0"/>
<value name="LSB" caption="LSB is transmitted first" value="0x1"/>
</value-group>
<value-group name="SERCOM_USART_CTRLA__FORM">
<value name="USART_FRAME_NO_PARITY" caption="USART frame" value="0x0"/>
<value name="USART_FRAME_WITH_PARITY" caption="USART frame with parity" value="0x1"/>
<value name="USART_FRAME_AUTO_BAUD_NO_PARITY" caption="Auto-baud - break detection and auto-baud" value="0x4"/>
<value name="USART_FRAME_AUTO_BAUD_WITH_PARITY" caption="Auto-baud - break detection and auto-baud with parity" value="0x5"/>
</value-group>
<value-group name="SERCOM_USART_CTRLA__RXPO">
<value name="PAD0" caption="SERCOM PAD[0] is used for data reception" value="0x0"/>
<value name="PAD1" caption="SERCOM PAD[1] is used for data reception" value="0x1"/>
<value name="PAD2" caption="SERCOM PAD[2] is used for data reception" value="0x2"/>
<value name="PAD3" caption="SERCOM PAD[3] is used for data reception" value="0x3"/>
</value-group>
<value-group name="SERCOM_USART_CTRLA__TXPO">
<value name="PAD0" caption="PAD[0] = TxD; PAD[1] = XCK" value="0x0"/>
<value name="PAD1" caption="PAD[2] = TxD; PAD[3] = XCK" value="0x1"/>
<value name="PAD2" caption="PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS" value="0x2"/>
</value-group>
<value-group name="SERCOM_USART_CTRLA__SAMPR">
<value name="16X_ARITHMETIC" caption="16x over-sampling using arithmetic baudrate generation" value="0x0"/>
<value name="16X_FRACTIONAL" caption="16x over-sampling using fractional baudrate generation" value="0x1"/>
<value name="8X_ARITHMETIC" caption="8x over-sampling using arithmetic baudrate generation" value="0x2"/>
<value name="8X_FRACTIONAL" caption="8x over-sampling using fractional baudrate generation" value="0x3"/>
<value name="3X_ARITHMETIC" caption="3x over-sampling using arithmetic baudrate generation" value="0x4"/>
</value-group>
<value-group name="SERCOM_USART_CTRLA__SAMPA">
<value name="ADJ0" caption="16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5" value="0x0"/>
<value name="ADJ1" caption="16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6" value="0x1"/>
<value name="ADJ2" caption="16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7" value="0x2"/>
<value name="ADJ3" caption="16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8" value="0x3"/>
</value-group>
<value-group name="SERCOM_USART_CTRLB__CHSIZE">
<value name="8_BIT" caption="8 Bits" value="0x0"/>
<value name="9_BIT" caption="9 Bits" value="0x1"/>
<value name="5_BIT" caption="5 Bits" value="0x5"/>
<value name="6_BIT" caption="6 Bits" value="0x6"/>
<value name="7_BIT" caption="7 Bits" value="0x7"/>
</value-group>
<value-group name="SERCOM_USART_CTRLB__PMODE">
<value name="EVEN" caption="Even Parity" value="0x0"/>
<value name="ODD" caption="Odd Parity" value="0x1"/>
</value-group>
<value-group name="SERCOM_USART_CTRLB__SBMODE">
<value name="1_BIT" caption="One Stop Bit" value="0x0"/>
<value name="2_BIT" caption="Two Stop Bits" value="0x1"/>
</value-group>
</module>
<module name="SYSCTRL" id="U2100" version="2.0.1" caption="System Control">
<register-group name="SYSCTRL" caption="System Control">
<register name="INTENCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
<bitfield name="XOSCRDY" caption="XOSC Ready Interrupt Enable" mask="0x1"/>
<bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x2"/>
<bitfield name="OSC32KRDY" caption="OSC32K Ready Interrupt Enable" mask="0x4"/>
<bitfield name="OSC8MRDY" caption="OSC8M Ready Interrupt Enable" mask="0x8"/>
<bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x10"/>
<bitfield name="DFLLOOB" caption="DFLL Out Of Bounds Interrupt Enable" mask="0x20"/>
<bitfield name="DFLLLCKF" caption="DFLL Lock Fine Interrupt Enable" mask="0x40"/>
<bitfield name="DFLLLCKC" caption="DFLL Lock Coarse Interrupt Enable" mask="0x80"/>
<bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x100"/>
<bitfield name="BOD33RDY" caption="BOD33 Ready Interrupt Enable" mask="0x200"/>
<bitfield name="BOD33DET" caption="BOD33 Detection Interrupt Enable" mask="0x400"/>
<bitfield name="B33SRDY" caption="BOD33 Synchronization Ready Interrupt Enable" mask="0x800"/>
<bitfield name="DPLLLCKR" caption="DPLL Lock Rise Interrupt Enable" mask="0x8000"/>
<bitfield name="DPLLLCKF" caption="DPLL Lock Fall Interrupt Enable" mask="0x10000"/>
<bitfield name="DPLLLTO" caption="DPLL Lock Timeout Interrupt Enable" mask="0x20000"/>
</register>
<register name="INTENSET" offset="0x4" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
<bitfield name="XOSCRDY" caption="XOSC Ready Interrupt Enable" mask="0x1"/>
<bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x2"/>
<bitfield name="OSC32KRDY" caption="OSC32K Ready Interrupt Enable" mask="0x4"/>
<bitfield name="OSC8MRDY" caption="OSC8M Ready Interrupt Enable" mask="0x8"/>
<bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x10"/>
<bitfield name="DFLLOOB" caption="DFLL Out Of Bounds Interrupt Enable" mask="0x20"/>
<bitfield name="DFLLLCKF" caption="DFLL Lock Fine Interrupt Enable" mask="0x40"/>
<bitfield name="DFLLLCKC" caption="DFLL Lock Coarse Interrupt Enable" mask="0x80"/>
<bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x100"/>
<bitfield name="BOD33RDY" caption="BOD33 Ready Interrupt Enable" mask="0x200"/>
<bitfield name="BOD33DET" caption="BOD33 Detection Interrupt Enable" mask="0x400"/>
<bitfield name="B33SRDY" caption="BOD33 Synchronization Ready Interrupt Enable" mask="0x800"/>
<bitfield name="DPLLLCKR" caption="DPLL Lock Rise Interrupt Enable" mask="0x8000"/>
<bitfield name="DPLLLCKF" caption="DPLL Lock Fall Interrupt Enable" mask="0x10000"/>
<bitfield name="DPLLLTO" caption="DPLL Lock Timeout Interrupt Enable" mask="0x20000"/>
</register>
<register name="INTFLAG" offset="0x8" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
<bitfield name="XOSCRDY" caption="XOSC Ready" mask="0x1"/>
<bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x2"/>
<bitfield name="OSC32KRDY" caption="OSC32K Ready" mask="0x4"/>
<bitfield name="OSC8MRDY" caption="OSC8M Ready" mask="0x8"/>
<bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x10"/>
<bitfield name="DFLLOOB" caption="DFLL Out Of Bounds" mask="0x20"/>
<bitfield name="DFLLLCKF" caption="DFLL Lock Fine" mask="0x40"/>
<bitfield name="DFLLLCKC" caption="DFLL Lock Coarse" mask="0x80"/>
<bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x100"/>
<bitfield name="BOD33RDY" caption="BOD33 Ready" mask="0x200"/>
<bitfield name="BOD33DET" caption="BOD33 Detection" mask="0x400"/>
<bitfield name="B33SRDY" caption="BOD33 Synchronization Ready" mask="0x800"/>
<bitfield name="DPLLLCKR" caption="DPLL Lock Rise" mask="0x8000"/>
<bitfield name="DPLLLCKF" caption="DPLL Lock Fall" mask="0x10000"/>
<bitfield name="DPLLLTO" caption="DPLL Lock Timeout" mask="0x20000"/>
</register>
<register name="PCLKSR" offset="0xC" rw="R" size="4" initval="0x00000000" caption="Power and Clocks Status">
<bitfield name="XOSCRDY" caption="XOSC Ready" mask="0x1"/>
<bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x2"/>
<bitfield name="OSC32KRDY" caption="OSC32K Ready" mask="0x4"/>
<bitfield name="OSC8MRDY" caption="OSC8M Ready" mask="0x8"/>
<bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x10"/>
<bitfield name="DFLLOOB" caption="DFLL Out Of Bounds" mask="0x20"/>
<bitfield name="DFLLLCKF" caption="DFLL Lock Fine" mask="0x40"/>
<bitfield name="DFLLLCKC" caption="DFLL Lock Coarse" mask="0x80"/>
<bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x100"/>
<bitfield name="BOD33RDY" caption="BOD33 Ready" mask="0x200"/>
<bitfield name="BOD33DET" caption="BOD33 Detection" mask="0x400"/>
<bitfield name="B33SRDY" caption="BOD33 Synchronization Ready" mask="0x800"/>
<bitfield name="DPLLLCKR" caption="DPLL Lock Rise" mask="0x8000"/>
<bitfield name="DPLLLCKF" caption="DPLL Lock Fall" mask="0x10000"/>
<bitfield name="DPLLLTO" caption="DPLL Lock Timeout" mask="0x20000"/>
</register>
<register name="XOSC" offset="0x10" rw="RW" size="2" initval="0x0080" caption="External Multipurpose Crystal Oscillator (XOSC) Control">
<bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
<bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x4"/>
<bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
<bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
<bitfield name="GAIN" caption="Oscillator Gain" mask="0x700" values="SYSCTRL_XOSC__GAIN"/>
<bitfield name="AMPGC" caption="Automatic Amplitude Gain Control" mask="0x800"/>
<bitfield name="STARTUP" caption="Start-Up Time" mask="0xF000" values="SYSCTRL_XOSC__STARTUP"/>
</register>
<register name="XOSC32K" offset="0x14" rw="RW" size="2" initval="0x0080" caption="32kHz External Crystal Oscillator (XOSC32K) Control">
<bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
<bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x4"/>
<bitfield name="EN32K" caption="32kHz Output Enable" mask="0x8"/>
<bitfield name="EN1K" caption="1kHz Output Enable" mask="0x10"/>
<bitfield name="AAMPEN" caption="Automatic Amplitude Control Enable" mask="0x20"/>
<bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
<bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
<bitfield name="STARTUP" caption="Oscillator Start-Up Time" mask="0x700" values="SYSCTRL_XOSC32K__STARTUP"/>
<bitfield name="WRTLOCK" caption="Write Lock" mask="0x1000"/>
</register>
<register name="OSC32K" offset="0x18" rw="RW" size="4" initval="0x003F0080" caption="32kHz Internal Oscillator (OSC32K) Control">
<bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
<bitfield name="EN32K" caption="32kHz Output Enable" mask="0x4"/>
<bitfield name="EN1K" caption="1kHz Output Enable" mask="0x8"/>
<bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
<bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
<bitfield name="STARTUP" caption="Oscillator Start-Up Time" mask="0x700" values="SYSCTRL_OSC32K__STARTUP"/>
<bitfield name="WRTLOCK" caption="Write Lock" mask="0x1000"/>
<bitfield name="CALIB" caption="Oscillator Calibration" mask="0x7F0000"/>
</register>
<register name="OSCULP32K" offset="0x1C" rw="RW" size="1" initval="0x1F" caption="32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control">
<bitfield name="CALIB" caption="Oscillator Calibration" mask="0x1F"/>
<bitfield name="WRTLOCK" caption="Write Lock" mask="0x80"/>
</register>
<register name="OSC8M" offset="0x20" rw="RW" size="4" initval="0x87070382" caption="8MHz Internal Oscillator (OSC8M) Control">
<bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
<bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
<bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
<bitfield name="PRESC" caption="Oscillator Prescaler" mask="0x300" values="SYSCTRL_OSC8M__PRESC"/>
<bitfield name="CALIB" caption="Oscillator Calibration" mask="0xFFF0000"/>
<bitfield name="FRANGE" caption="Oscillator Frequency Range" mask="0xC0000000" values="SYSCTRL_OSC8M__FRANGE"/>
</register>
<register name="DFLLCTRL" offset="0x24" rw="RW" access="WSYNC" size="2" initval="0x0080" caption="DFLL48M Control">
<bitfield name="ENABLE" caption="DFLL Enable" mask="0x2"/>
<bitfield name="MODE" caption="Operating Mode Selection" mask="0x4"/>
<bitfield name="STABLE" caption="Stable DFLL Frequency" mask="0x8"/>
<bitfield name="LLAW" caption="Lose Lock After Wake" mask="0x10"/>
<bitfield name="USBCRM" caption="USB Clock Recovery Mode" mask="0x20"/>
<bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
<bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
<bitfield name="CCDIS" caption="Chill Cycle Disable" mask="0x100"/>
<bitfield name="QLDIS" caption="Quick Lock Disable" mask="0x200"/>
<bitfield name="BPLCKC" caption="Bypass Coarse Lock" mask="0x400"/>
<bitfield name="WAITLOCK" caption="Wait Lock" mask="0x800"/>
</register>
<register name="DFLLVAL" offset="0x28" rw="RW" access="RSYNC" size="4" initval="0x00000000" caption="DFLL48M Value">
<bitfield name="FINE" caption="Fine Value" mask="0x3FF"/>
<bitfield name="COARSE" caption="Coarse Value" mask="0xFC00"/>
<bitfield name="DIFF" caption="Multiplication Ratio Difference" mask="0xFFFF0000"/>
</register>
<register name="DFLLMUL" offset="0x2C" rw="RW" size="4" initval="0x00000000" caption="DFLL48M Multiplier">
<bitfield name="MUL" caption="DFLL Multiply Factor" mask="0xFFFF"/>
<bitfield name="FSTEP" caption="Fine Maximum Step" mask="0x3FF0000"/>
<bitfield name="CSTEP" caption="Coarse Maximum Step" mask="0xFC000000"/>
</register>
<register name="DFLLSYNC" offset="0x30" rw="RW" size="1" initval="0x00" caption="DFLL48M Synchronization">
<bitfield name="READREQ" caption="Read Request" mask="0x80"/>
</register>
<register name="BOD33" offset="0x34" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="3.3V Brown-Out Detector (BOD33) Control">
<bitfield name="ENABLE" caption="Enable" mask="0x2"/>
<bitfield name="HYST" caption="Hysteresis" mask="0x4"/>
<bitfield name="ACTION" caption="BOD33 Action" mask="0x18" values="SYSCTRL_BOD33__ACTION"/>
<bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
<bitfield name="MODE" caption="Operation Mode" mask="0x100"/>
<bitfield name="CEN" caption="Clock Enable" mask="0x200"/>
<bitfield name="PSEL" caption="Prescaler Select" mask="0xF000" values="SYSCTRL_BOD33__PSEL"/>
<bitfield name="LEVEL" caption="BOD33 Threshold Level" mask="0x3F0000"/>
</register>
<register name="VREG" offset="0x3C" rw="RW" size="2" initval="0x0000" caption="Voltage Regulator System (VREG) Control">
<bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
<bitfield name="FORCELDO" caption="Force LDO Voltage Regulator" mask="0x2000"/>
</register>
<register name="VREF" offset="0x40" rw="RW" size="4" initval="0x00000000" caption="Voltage References System (VREF) Control">
<bitfield name="TSEN" caption="Temperature Sensor Enable" mask="0x2"/>
<bitfield name="BGOUTEN" caption="Bandgap Output Enable" mask="0x4"/>
<bitfield name="CALIB" caption="Bandgap Voltage Generator Calibration" mask="0x7FF0000"/>
</register>
<register name="DPLLCTRLA" offset="0x44" rw="RW" size="1" initval="0x80" caption="DPLL Control A">
<bitfield name="ENABLE" caption="DPLL Enable" mask="0x2"/>
<bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
<bitfield name="ONDEMAND" caption="On Demand Clock Activation" mask="0x80"/>
</register>
<register name="DPLLRATIO" offset="0x48" rw="RW" size="4" initval="0x00000000" caption="DPLL Ratio Control">
<bitfield name="LDR" caption="Loop Divider Ratio" mask="0xFFF"/>
<bitfield name="LDRFRAC" caption="Loop Divider Ratio Fractional Part" mask="0xF0000"/>
</register>
<register name="DPLLCTRLB" offset="0x4C" rw="RW" size="4" initval="0x00000000" caption="DPLL Control B">
<bitfield name="FILTER" caption="Proportional Integral Filter Selection" mask="0x3" values="SYSCTRL_DPLLCTRLB__FILTER"/>
<bitfield name="LPEN" caption="Low-Power Enable" mask="0x4"/>
<bitfield name="WUF" caption="Wake Up Fast" mask="0x8"/>
<bitfield name="REFCLK" caption="Reference Clock Selection" mask="0x30" values="SYSCTRL_DPLLCTRLB__REFCLK"/>
<bitfield name="LTIME" caption="Lock Time" mask="0x700" values="SYSCTRL_DPLLCTRLB__LTIME"/>
<bitfield name="LBYPASS" caption="Lock Bypass" mask="0x1000"/>
<bitfield name="DIV" caption="Clock Divider" mask="0x7FF0000"/>
</register>
<register name="DPLLSTATUS" offset="0x50" rw="R" size="1" initval="0x00" caption="DPLL Status">
<bitfield name="LOCK" caption="DPLL Lock Status" mask="0x1"/>
<bitfield name="CLKRDY" caption="Output Clock Ready" mask="0x2"/>
<bitfield name="ENABLE" caption="DPLL Enable" mask="0x4"/>
<bitfield name="DIV" caption="Divider Enable" mask="0x8"/>
</register>
</register-group>
<value-group name="SYSCTRL_XOSC__GAIN">
<value name="0" caption="2MHz" value="0x0"/>
<value name="1" caption="4MHz" value="0x1"/>
<value name="2" caption="8MHz" value="0x2"/>
<value name="3" caption="16MHz" value="0x3"/>
<value name="4" caption="30MHz" value="0x4"/>
</value-group>
<value-group name="SYSCTRL_OSC8M__FRANGE">
<value name="0" caption="4 to 6MHz" value="0x0"/>
<value name="1" caption="6 to 8MHz" value="0x1"/>
<value name="2" caption="8 to 11MHz" value="0x2"/>
<value name="3" caption="11 to 15MHz" value="0x3"/>
</value-group>
<value-group name="SYSCTRL_OSC8M__PRESC">
<value name="0" caption="1" value="0x0"/>
<value name="1" caption="2" value="0x1"/>
<value name="2" caption="4" value="0x2"/>
<value name="3" caption="8" value="0x3"/>
</value-group>
<value-group name="SYSCTRL_BOD33__ACTION">
<value name="NONE" caption="No action" value="0x0"/>
<value name="RESET" caption="The BOD33 generates a reset" value="0x1"/>
<value name="INTERRUPT" caption="The BOD33 generates an interrupt" value="0x2"/>
</value-group>
<value-group name="SYSCTRL_BOD33__PSEL">
<value name="DIV2" caption="Divide clock by 2" value="0x0"/>
<value name="DIV4" caption="Divide clock by 4" value="0x1"/>
<value name="DIV8" caption="Divide clock by 8" value="0x2"/>
<value name="DIV16" caption="Divide clock by 16" value="0x3"/>
<value name="DIV32" caption="Divide clock by 32" value="0x4"/>
<value name="DIV64" caption="Divide clock by 64" value="0x5"/>
<value name="DIV128" caption="Divide clock by 128" value="0x6"/>
<value name="DIV256" caption="Divide clock by 256" value="0x7"/>
<value name="DIV512" caption="Divide clock by 512" value="0x8"/>
<value name="DIV1K" caption="Divide clock by 1024" value="0x9"/>
<value name="DIV2K" caption="Divide clock by 2048" value="0xA"/>
<value name="DIV4K" caption="Divide clock by 4096" value="0xB"/>
<value name="DIV8K" caption="Divide clock by 8192" value="0xC"/>
<value name="DIV16K" caption="Divide clock by 16384" value="0xD"/>
<value name="DIV32K" caption="Divide clock by 32768" value="0xE"/>
<value name="DIV64K" caption="Divide clock by 65536" value="0xF"/>
</value-group>
<value-group name="SYSCTRL_XOSC__STARTUP">
<value name="CYCLE1" caption="31 us" value="0"/>
<value name="CYCLE2" caption="61 us" value="1"/>
<value name="CYCLE4" caption="122 us" value="2"/>
<value name="CYCLE8" caption="244 us" value="3"/>
<value name="CYCLE16" caption="488 us" value="4"/>
<value name="CYCLE32" caption="977 us" value="5"/>
<value name="CYCLE64" caption="1953 us" value="6"/>
<value name="CYCLE128" caption="3906 us" value="7"/>
<value name="CYCLE256" caption="7813 us" value="8"/>
<value name="CYCLE512" caption="15625 us" value="9"/>
<value name="CYCLE1024" caption="31250 us" value="10"/>
<value name="CYCLE2048" caption="62500 us" value="11"/>
<value name="CYCLE4096" caption="125000 us" value="12"/>
<value name="CYCLE8192" caption="250000 us" value="13"/>
<value name="CYCLE16384" caption="500000 us" value="14"/>
<value name="CYCLE32768" caption="1000000 us" value="15"/>
</value-group>
<value-group name="SYSCTRL_OSC32K__STARTUP">
<value name="CYCLE3" caption="0.092 ms" value="0"/>
<value name="CYCLE4" caption="0.122 ms" value="1"/>
<value name="CYCLE6" caption="0.183 ms" value="2"/>
<value name="CYCLE10" caption="0.305 ms" value="3"/>
<value name="CYCLE18" caption="0.549 ms" value="4"/>
<value name="CYCLE34" caption="1.038 ms" value="5"/>
<value name="CYCLE66" caption="2.014 ms" value="6"/>
<value name="CYCLE130" caption="3.967 ms" value="7"/>
</value-group>
<value-group name="SYSCTRL_XOSC32K__STARTUP">
<value name="CYCLE1" caption="0.122 ms" value="0"/>
<value name="CYCLE32" caption="1.068 ms" value="1"/>
<value name="CYCLE2048" caption="62.592 ms" value="2"/>
<value name="CYCLE4096" caption="125.092 ms" value="3"/>
<value name="CYCLE16384" caption="500.092 ms" value="4"/>
<value name="CYCLE32768" caption="1000.092 ms" value="5"/>
<value name="CYCLE65536" caption="2000.092 ms" value="6"/>
<value name="CYCLE131072" caption="4000.092 ms" value="7"/>
</value-group>
<value-group name="SYSCTRL_DPLLCTRLB__FILTER">
<value name="DEFAULT" caption="Default filter mode" value="0x0"/>
<value name="LBFILT" caption="Low bandwidth filter" value="0x1"/>
<value name="HBFILT" caption="High bandwidth filter" value="0x2"/>
<value name="HDFILT" caption="High damping filter" value="0x3"/>
</value-group>
<value-group name="SYSCTRL_DPLLCTRLB__LTIME">
<value name="DEFAULT" caption="No time-out" value="0x0"/>
<value name="8MS" caption="Time-out if no lock within 8 ms" value="0x4"/>
<value name="9MS" caption="Time-out if no lock within 9 ms" value="0x5"/>
<value name="10MS" caption="Time-out if no lock within 10 ms" value="0x6"/>
<value name="11MS" caption="Time-out if no lock within 11 ms" value="0x7"/>
</value-group>
<value-group name="SYSCTRL_DPLLCTRLB__REFCLK">
<value name="REF0" caption="CLK_DPLL_REF0 clock reference" value="0x0"/>
<value name="REF1" caption="CLK_DPLL_REF1 clock reference" value="0x1"/>
<value name="GCLK" caption="GCLK_DPLL clock reference" value="0x2"/>
</value-group>
</module>
<module name="TC" id="U2212" version="1.3.1" caption="Basic Timer Counter">
<register-group name="TC" caption="Basic Timer Counter">
<mode name="COUNT8" qualifier="TC.CTRLA.MODE" value="1" caption="8-bit Counter Mode"/>
<mode name="COUNT16" qualifier="TC.CTRLA.MODE" value="0" caption="16-bit Counter Mode"/>
<mode name="COUNT32" qualifier="TC.CTRLA.MODE" value="2" caption="32-bit Counter Mode"/>
<register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
<bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
<bitfield name="ENABLE" caption="Enable" mask="0x2"/>
<bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
<bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
<bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
<bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
<bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
</register>
<register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
<bitfield name="ADDR" caption="Address" mask="0x1F"/>
<bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
<bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
</register>
<register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
<bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
<bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
<bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
</register>
<register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
<bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
<bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
<bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
</register>
<register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
<bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
<bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
<bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
<bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
</register>
<register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
<bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
</register>
<register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
<bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
<bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
<bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
<bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
<bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
<bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
</register>
<register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
<bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
<bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
<bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
<bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
<bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
</register>
<register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
<bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
<bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
<bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
<bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
<bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
</register>
<register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
<bitfield name="OVF" caption="Overflow" mask="0x1"/>
<bitfield name="ERR" caption="Error" mask="0x2"/>
<bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
<bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
<bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
</register>
<register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
<bitfield name="STOP" caption="Stop" mask="0x8"/>
<bitfield name="SLAVE" caption="Slave" mask="0x10"/>
<bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
</register>
<register modes="COUNT8" name="COUNT" offset="0x10" rw="RW" size="1" initval="0x00" caption="COUNT8 Counter Value">
<bitfield name="COUNT" caption="Counter Value" mask="0xFF"/>
</register>
<register modes="COUNT16" name="COUNT" offset="0x10" rw="RW" size="2" initval="0x0000" caption="COUNT16 Counter Value">
<bitfield name="COUNT" caption="Count Value" mask="0xFFFF"/>
</register>
<register modes="COUNT32" name="COUNT" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="COUNT32 Counter Value">
<bitfield name="COUNT" caption="Count Value" mask="0xFFFFFFFF"/>
</register>
<register modes="COUNT8" name="PER" offset="0x14" rw="RW" size="1" initval="0xFF" caption="COUNT8 Period Value">
<bitfield name="PER" caption="Period Value" mask="0xFF"/>
</register>
<register modes="COUNT8" name="CC" offset="0x18" rw="RW" size="1" count="2" initval="0x00" caption="COUNT8 Compare/Capture">
<bitfield name="CC" caption="Compare/Capture Value" mask="0xFF"/>
</register>
<register modes="COUNT16" name="CC" offset="0x18" rw="RW" size="2" count="2" initval="0x0000" caption="COUNT16 Compare/Capture">
<bitfield name="CC" caption="Compare/Capture Value" mask="0xFFFF"/>
</register>
<register modes="COUNT32" name="CC" offset="0x18" rw="RW" size="4" count="2" initval="0x00000000" caption="COUNT32 Compare/Capture">
<bitfield name="CC" caption="Compare/Capture Value" mask="0xFFFFFFFF"/>
</register>
</register-group>
<value-group name="TC_CTRLA__MODE">
<value name="COUNT16" caption="Counter in 16-bit mode" value="0"/>
<value name="COUNT8" caption="Counter in 8-bit mode" value="1"/>
<value name="COUNT32" caption="Counter in 32-bit mode" value="2"/>
</value-group>
<value-group name="TC_CTRLA__PRESCALER">
<value name="DIV1" caption="Prescaler: GCLK_TC" value="0x0"/>
<value name="DIV2" caption="Prescaler: GCLK_TC/2" value="0x1"/>
<value name="DIV4" caption="Prescaler: GCLK_TC/4" value="0x2"/>
<value name="DIV8" caption="Prescaler: GCLK_TC/8" value="0x3"/>
<value name="DIV16" caption="Prescaler: GCLK_TC/16" value="0x4"/>
<value name="DIV64" caption="Prescaler: GCLK_TC/64" value="0x5"/>
<value name="DIV256" caption="Prescaler: GCLK_TC/256" value="0x6"/>
<value name="DIV1024" caption="Prescaler: GCLK_TC/1024" value="0x7"/>
</value-group>
<value-group name="TC_CTRLA__PRESCSYNC">
<value name="GCLK" caption="Reload or reset the counter on next generic clock" value="0"/>
<value name="PRESC" caption="Reload or reset the counter on next prescaler clock" value="1"/>
<value name="RESYNC" caption="Reload or reset the counter on next generic clock. Reset the prescaler counter" value="2"/>
</value-group>
<value-group name="TC_CTRLA__WAVEGEN">
<value name="NFRQ" value="0"/>
<value name="MFRQ" value="1"/>
<value name="NPWM" value="2"/>
<value name="MPWM" value="3"/>
</value-group>
<value-group name="TC_CTRLBCLR__CMD">
<value name="NONE" caption="No action" value="0"/>
<value name="RETRIGGER" caption="Force a start, restart or retrigger" value="1"/>
<value name="STOP" caption="Force a stop" value="2"/>
</value-group>
<value-group name="TC_CTRLBSET__CMD">
<value name="NONE" caption="No action" value="0x0"/>
<value name="RETRIGGER" caption="Force a start, restart or retrigger" value="0x1"/>
<value name="STOP" caption="Force a stop" value="0x2"/>
</value-group>
<value-group name="TC_EVCTRL__EVACT">
<value name="OFF" caption="Event action disabled" value="0"/>
<value name="RETRIGGER" caption="Start, restart or retrigger TC on event" value="1"/>
<value name="COUNT" caption="Count on event" value="2"/>
<value name="START" caption="Start TC on event" value="3"/>
<value name="PPW" caption="Period captured in CC0, pulse width in CC1" value="5"/>
<value name="PWP" caption="Period captured in CC1, pulse width in CC0" value="6"/>
</value-group>
</module>
<module name="TCC" id="U2213" version="1.2.2" caption="Timer Counter Control">
<register-group name="TCC" caption="Timer Counter Control">
<register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Control A">
<bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
<bitfield name="ENABLE" caption="Enable" mask="0x2"/>
<bitfield name="RESOLUTION" caption="Enhanced Resolution" mask="0x60" values="TCC_CTRLA__RESOLUTION"/>
<bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TCC_CTRLA__PRESCALER"/>
<bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
<bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization Selection" mask="0x3000" values="TCC_CTRLA__PRESCSYNC"/>
<bitfield name="ALOCK" caption="Auto Lock" mask="0x4000"/>
<bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x1000000"/>
<bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x2000000"/>
<bitfield name="CPTEN2" caption="Capture Channel 2 Enable" mask="0x4000000"/>
<bitfield name="CPTEN3" caption="Capture Channel 3 Enable" mask="0x8000000"/>
</register>
<register name="CTRLBCLR" offset="0x4" rw="RW" access="RWSYNC" size="1" atomic-op="clear:CTRLBCLR" initval="0x00" caption="Control B Clear">
<bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
<bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
<bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
<bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="TCC_CTRLBCLR__IDXCMD"/>
<bitfield name="CMD" caption="TCC Command" mask="0xE0" values="TCC_CTRLBCLR__CMD"/>
</register>
<register name="CTRLBSET" offset="0x5" rw="RW" access="RWSYNC" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
<bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
<bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
<bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
<bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="TCC_CTRLBSET__IDXCMD"/>
<bitfield name="CMD" caption="TCC Command" mask="0xE0" values="TCC_CTRLBSET__CMD"/>
</register>
<register name="SYNCBUSY" offset="0x8" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
<bitfield name="SWRST" caption="Swrst Busy" mask="0x1"/>
<bitfield name="ENABLE" caption="Enable Busy" mask="0x2"/>
<bitfield name="CTRLB" caption="Ctrlb Busy" mask="0x4"/>
<bitfield name="STATUS" caption="Status Busy" mask="0x8"/>
<bitfield name="COUNT" caption="Count Busy" mask="0x10"/>
<bitfield name="PATT" caption="Pattern Busy" mask="0x20"/>
<bitfield name="WAVE" caption="Wave Busy" mask="0x40"/>
<bitfield name="PER" caption="Period busy" mask="0x80"/>
<bitfield name="CC0" caption="Compare Channel 0 Busy" mask="0x100"/>
<bitfield name="CC1" caption="Compare Channel 1 Busy" mask="0x200"/>
<bitfield name="CC2" caption="Compare Channel 2 Busy" mask="0x400"/>
<bitfield name="CC3" caption="Compare Channel 3 Busy" mask="0x800"/>
<bitfield name="PATTB" caption="Pattern Buffer Busy" mask="0x10000"/>
<bitfield name="WAVEB" caption="Wave Buffer Busy" mask="0x20000"/>
<bitfield name="PERB" caption="Period Buffer Busy" mask="0x40000"/>
<bitfield name="CCB0" caption="Compare Channel Buffer 0 Busy" mask="0x80000"/>
<bitfield name="CCB1" caption="Compare Channel Buffer 1 Busy" mask="0x100000"/>
<bitfield name="CCB2" caption="Compare Channel Buffer 2 Busy" mask="0x200000"/>
<bitfield name="CCB3" caption="Compare Channel Buffer 3 Busy" mask="0x400000"/>
</register>
<register name="FCTRLA" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault A Configuration">
<bitfield name="SRC" caption="Fault A Source" mask="0x3" values="TCC_FCTRLA__SRC"/>
<bitfield name="KEEP" caption="Fault A Keeper" mask="0x8"/>
<bitfield name="QUAL" caption="Fault A Qualification" mask="0x10"/>
<bitfield name="BLANK" caption="Fault A Blanking Mode" mask="0x60" values="TCC_FCTRLA__BLANK"/>
<bitfield name="RESTART" caption="Fault A Restart" mask="0x80"/>
<bitfield name="HALT" caption="Fault A Halt Mode" mask="0x300" values="TCC_FCTRLA__HALT"/>
<bitfield name="CHSEL" caption="Fault A Capture Channel" mask="0xC00" values="TCC_FCTRLA__CHSEL"/>
<bitfield name="CAPTURE" caption="Fault A Capture Action" mask="0x7000" values="TCC_FCTRLA__CAPTURE"/>
<bitfield name="BLANKPRESC" caption="Fault A Blanking Prescaler" mask="0x8000"/>
<bitfield name="BLANKVAL" caption="Fault A Blanking Time" mask="0xFF0000"/>
<bitfield name="FILTERVAL" caption="Fault A Filter Value" mask="0xF000000"/>
</register>
<register name="FCTRLB" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault B Configuration">
<bitfield name="SRC" caption="Fault B Source" mask="0x3" values="TCC_FCTRLB__SRC"/>
<bitfield name="KEEP" caption="Fault B Keeper" mask="0x8"/>
<bitfield name="QUAL" caption="Fault B Qualification" mask="0x10"/>
<bitfield name="BLANK" caption="Fault B Blanking Mode" mask="0x60" values="TCC_FCTRLB__BLANK"/>
<bitfield name="RESTART" caption="Fault B Restart" mask="0x80"/>
<bitfield name="HALT" caption="Fault B Halt Mode" mask="0x300" values="TCC_FCTRLB__HALT"/>
<bitfield name="CHSEL" caption="Fault B Capture Channel" mask="0xC00" values="TCC_FCTRLB__CHSEL"/>
<bitfield name="CAPTURE" caption="Fault B Capture Action" mask="0x7000" values="TCC_FCTRLB__CAPTURE"/>
<bitfield name="BLANKPRESC" caption="Fault B Blanking Prescaler" mask="0x8000"/>
<bitfield name="BLANKVAL" caption="Fault B Blanking Time" mask="0xFF0000"/>
<bitfield name="FILTERVAL" caption="Fault B Filter Value" mask="0xF000000"/>
</register>
<register name="WEXCTRL" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Waveform Extension Configuration">
<bitfield name="OTMX" caption="Output Matrix" mask="0x3"/>
<bitfield name="DTIEN0" caption="Dead-time Insertion Generator 0 Enable" mask="0x100"/>
<bitfield name="DTIEN1" caption="Dead-time Insertion Generator 1 Enable" mask="0x200"/>
<bitfield name="DTIEN2" caption="Dead-time Insertion Generator 2 Enable" mask="0x400"/>
<bitfield name="DTIEN3" caption="Dead-time Insertion Generator 3 Enable" mask="0x800"/>
<bitfield name="DTLS" caption="Dead-time Low Side Outputs Value" mask="0xFF0000"/>
<bitfield name="DTHS" caption="Dead-time High Side Outputs Value" mask="0xFF000000"/>
</register>
<register name="DRVCTRL" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="Driver Control">
<bitfield name="NRE0" caption="Non-Recoverable State 0 Output Enable" mask="0x1"/>
<bitfield name="NRE1" caption="Non-Recoverable State 1 Output Enable" mask="0x2"/>
<bitfield name="NRE2" caption="Non-Recoverable State 2 Output Enable" mask="0x4"/>
<bitfield name="NRE3" caption="Non-Recoverable State 3 Output Enable" mask="0x8"/>
<bitfield name="NRE4" caption="Non-Recoverable State 4 Output Enable" mask="0x10"/>
<bitfield name="NRE5" caption="Non-Recoverable State 5 Output Enable" mask="0x20"/>
<bitfield name="NRE6" caption="Non-Recoverable State 6 Output Enable" mask="0x40"/>
<bitfield name="NRE7" caption="Non-Recoverable State 7 Output Enable" mask="0x80"/>
<bitfield name="NRV0" caption="Non-Recoverable State 0 Output Value" mask="0x100"/>
<bitfield name="NRV1" caption="Non-Recoverable State 1 Output Value" mask="0x200"/>
<bitfield name="NRV2" caption="Non-Recoverable State 2 Output Value" mask="0x400"/>
<bitfield name="NRV3" caption="Non-Recoverable State 3 Output Value" mask="0x800"/>
<bitfield name="NRV4" caption="Non-Recoverable State 4 Output Value" mask="0x1000"/>
<bitfield name="NRV5" caption="Non-Recoverable State 5 Output Value" mask="0x2000"/>
<bitfield name="NRV6" caption="Non-Recoverable State 6 Output Value" mask="0x4000"/>
<bitfield name="NRV7" caption="Non-Recoverable State 7 Output Value" mask="0x8000"/>
<bitfield name="INVEN0" caption="Output Waveform 0 Inversion" mask="0x10000"/>
<bitfield name="INVEN1" caption="Output Waveform 1 Inversion" mask="0x20000"/>
<bitfield name="INVEN2" caption="Output Waveform 2 Inversion" mask="0x40000"/>
<bitfield name="INVEN3" caption="Output Waveform 3 Inversion" mask="0x80000"/>
<bitfield name="INVEN4" caption="Output Waveform 4 Inversion" mask="0x100000"/>
<bitfield name="INVEN5" caption="Output Waveform 5 Inversion" mask="0x200000"/>
<bitfield name="INVEN6" caption="Output Waveform 6 Inversion" mask="0x400000"/>
<bitfield name="INVEN7" caption="Output Waveform 7 Inversion" mask="0x800000"/>
<bitfield name="FILTERVAL0" caption="Non-Recoverable Fault Input 0 Filter Value" mask="0xF000000"/>
<bitfield name="FILTERVAL1" caption="Non-Recoverable Fault Input 1 Filter Value" mask="0xF0000000"/>
</register>
<register name="DBGCTRL" offset="0x1E" rw="RW" size="1" initval="0x00" caption="Debug Control">
<bitfield name="DBGRUN" caption="Debug Running Mode" mask="0x1"/>
<bitfield name="FDDBD" caption="Fault Detection on Debug Break Detection" mask="0x4"/>
</register>
<register name="EVCTRL" offset="0x20" rw="RW" size="4" initval="0x00000000" caption="Event Control">
<bitfield name="EVACT0" caption="Timer/counter Input Event0 Action" mask="0x7" values="TCC_EVCTRL__EVACT0"/>
<bitfield name="EVACT1" caption="Timer/counter Input Event1 Action" mask="0x38" values="TCC_EVCTRL__EVACT1"/>
<bitfield name="CNTSEL" caption="Timer/counter Output Event Mode" mask="0xC0" values="TCC_EVCTRL__CNTSEL"/>
<bitfield name="OVFEO" caption="Overflow/Underflow Output Event Enable" mask="0x100"/>
<bitfield name="TRGEO" caption="Retrigger Output Event Enable" mask="0x200"/>
<bitfield name="CNTEO" caption="Timer/counter Output Event Enable" mask="0x400"/>
<bitfield name="TCINV0" caption="Inverted Event 0 Input Enable" mask="0x1000"/>
<bitfield name="TCINV1" caption="Inverted Event 1 Input Enable" mask="0x2000"/>
<bitfield name="TCEI0" caption="Timer/counter Event 0 Input Enable" mask="0x4000"/>
<bitfield name="TCEI1" caption="Timer/counter Event 1 Input Enable" mask="0x8000"/>
<bitfield name="MCEI0" caption="Match or Capture Channel 0 Event Input Enable" mask="0x10000"/>
<bitfield name="MCEI1" caption="Match or Capture Channel 1 Event Input Enable" mask="0x20000"/>
<bitfield name="MCEI2" caption="Match or Capture Channel 2 Event Input Enable" mask="0x40000"/>
<bitfield name="MCEI3" caption="Match or Capture Channel 3 Event Input Enable" mask="0x80000"/>
<bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000000"/>
<bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000000"/>
<bitfield name="MCEO2" caption="Match or Capture Channel 2 Event Output Enable" mask="0x4000000"/>
<bitfield name="MCEO3" caption="Match or Capture Channel 3 Event Output Enable" mask="0x8000000"/>
</register>
<register name="INTENCLR" offset="0x24" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
<bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
<bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
<bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
<bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
<bitfield name="UFS" caption="Non-Recoverable Update Fault Interrupt Enable" mask="0x400"/>
<bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
<bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
<bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
<bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
<bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
<bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
<bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
<bitfield name="MC2" caption="Match or Capture Channel 2 Interrupt Enable" mask="0x40000"/>
<bitfield name="MC3" caption="Match or Capture Channel 3 Interrupt Enable" mask="0x80000"/>
</register>
<register name="INTENSET" offset="0x28" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
<bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
<bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
<bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
<bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
<bitfield name="UFS" caption="Non-Recoverable Update Fault Interrupt Enable" mask="0x400"/>
<bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
<bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
<bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
<bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
<bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
<bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
<bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
<bitfield name="MC2" caption="Match or Capture Channel 2 Interrupt Enable" mask="0x40000"/>
<bitfield name="MC3" caption="Match or Capture Channel 3 Interrupt Enable" mask="0x80000"/>
</register>
<register name="INTFLAG" offset="0x2C" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
<bitfield name="OVF" caption="Overflow" mask="0x1"/>
<bitfield name="TRG" caption="Retrigger" mask="0x2"/>
<bitfield name="CNT" caption="Counter" mask="0x4"/>
<bitfield name="ERR" caption="Error" mask="0x8"/>
<bitfield name="UFS" caption="Non-Recoverable Update Fault" mask="0x400"/>
<bitfield name="DFS" caption="Non-Recoverable Debug Fault" mask="0x800"/>
<bitfield name="FAULTA" caption="Recoverable Fault A" mask="0x1000"/>
<bitfield name="FAULTB" caption="Recoverable Fault B" mask="0x2000"/>
<bitfield name="FAULT0" caption="Non-Recoverable Fault 0" mask="0x4000"/>
<bitfield name="FAULT1" caption="Non-Recoverable Fault 1" mask="0x8000"/>
<bitfield name="MC0" caption="Match or Capture 0" mask="0x10000"/>
<bitfield name="MC1" caption="Match or Capture 1" mask="0x20000"/>
<bitfield name="MC2" caption="Match or Capture 2" mask="0x40000"/>
<bitfield name="MC3" caption="Match or Capture 3" mask="0x80000"/>
</register>
<register name="STATUS" offset="0x30" rw="RW" size="4" initval="0x00000001" caption="Status">
<bitfield name="STOP" caption="Stop" mask="0x1"/>
<bitfield name="IDX" caption="Ramp" mask="0x2"/>
<bitfield name="UFS" caption="Non-Recoverable Update Fault State" mask="0x4"/>
<bitfield name="DFS" caption="Non-Recoverable Debug Fault State" mask="0x8"/>
<bitfield name="SLAVE" caption="Slave" mask="0x10"/>
<bitfield name="PATTBV" caption="Pattern Buffer Valid" mask="0x20"/>
<bitfield name="WAVEBV" caption="Wave Buffer Valid" mask="0x40"/>
<bitfield name="PERBV" caption="Period Buffer Valid" mask="0x80"/>
<bitfield name="FAULTAIN" caption="Recoverable Fault A Input" mask="0x100"/>
<bitfield name="FAULTBIN" caption="Recoverable Fault B Input" mask="0x200"/>
<bitfield name="FAULT0IN" caption="Non-Recoverable Fault0 Input" mask="0x400"/>
<bitfield name="FAULT1IN" caption="Non-Recoverable Fault1 Input" mask="0x800"/>
<bitfield name="FAULTA" caption="Recoverable Fault A State" mask="0x1000"/>
<bitfield name="FAULTB" caption="Recoverable Fault B State" mask="0x2000"/>
<bitfield name="FAULT0" caption="Non-Recoverable Fault 0 State" mask="0x4000"/>
<bitfield name="FAULT1" caption="Non-Recoverable Fault 1 State" mask="0x8000"/>
<bitfield name="CCBV0" caption="Compare Channel 0 Buffer Valid" mask="0x10000"/>
<bitfield name="CCBV1" caption="Compare Channel 1 Buffer Valid" mask="0x20000"/>
<bitfield name="CCBV2" caption="Compare Channel 2 Buffer Valid" mask="0x40000"/>
<bitfield name="CCBV3" caption="Compare Channel 3 Buffer Valid" mask="0x80000"/>
<bitfield name="CMP0" caption="Compare Channel 0 Value" mask="0x1000000"/>
<bitfield name="CMP1" caption="Compare Channel 1 Value" mask="0x2000000"/>
<bitfield name="CMP2" caption="Compare Channel 2 Value" mask="0x4000000"/>
<bitfield name="CMP3" caption="Compare Channel 3 Value" mask="0x8000000"/>
</register>
<register name="COUNT" offset="0x34" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="Count">
<mode name="DITH4"/>
<mode name="DITH5"/>
<mode name="DITH6"/>
<mode name="DEFAULT"/>
<bitfield modes="DITH6" name="COUNT" caption="Counter Value" mask="0xFFFFC0"/>
<bitfield modes="DITH5" name="COUNT" caption="Counter Value" mask="0xFFFFE0"/>
<bitfield modes="DITH4" name="COUNT" caption="Counter Value" mask="0xFFFFF0"/>
<bitfield modes="DEFAULT" name="COUNT" caption="Counter Value" mask="0xFFFFFF"/>
</register>
<register name="PATT" offset="0x38" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Pattern">
<bitfield name="PGE0" caption="Pattern Generator 0 Output Enable" mask="0x1"/>
<bitfield name="PGE1" caption="Pattern Generator 1 Output Enable" mask="0x2"/>
<bitfield name="PGE2" caption="Pattern Generator 2 Output Enable" mask="0x4"/>
<bitfield name="PGE3" caption="Pattern Generator 3 Output Enable" mask="0x8"/>
<bitfield name="PGE4" caption="Pattern Generator 4 Output Enable" mask="0x10"/>
<bitfield name="PGE5" caption="Pattern Generator 5 Output Enable" mask="0x20"/>
<bitfield name="PGE6" caption="Pattern Generator 6 Output Enable" mask="0x40"/>
<bitfield name="PGE7" caption="Pattern Generator 7 Output Enable" mask="0x80"/>
<bitfield name="PGV0" caption="Pattern Generator 0 Output Value" mask="0x100"/>
<bitfield name="PGV1" caption="Pattern Generator 1 Output Value" mask="0x200"/>
<bitfield name="PGV2" caption="Pattern Generator 2 Output Value" mask="0x400"/>
<bitfield name="PGV3" caption="Pattern Generator 3 Output Value" mask="0x800"/>
<bitfield name="PGV4" caption="Pattern Generator 4 Output Value" mask="0x1000"/>
<bitfield name="PGV5" caption="Pattern Generator 5 Output Value" mask="0x2000"/>
<bitfield name="PGV6" caption="Pattern Generator 6 Output Value" mask="0x4000"/>
<bitfield name="PGV7" caption="Pattern Generator 7 Output Value" mask="0x8000"/>
</register>
<register name="WAVE" offset="0x3C" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Waveform Control">
<bitfield name="WAVEGEN" caption="Waveform Generation" mask="0x7" values="TCC_WAVE__WAVEGEN"/>
<bitfield name="RAMP" caption="Ramp Mode" mask="0x30" values="TCC_WAVE__RAMP"/>
<bitfield name="CIPEREN" caption="Circular period Enable" mask="0x80"/>
<bitfield name="CICCEN0" caption="Circular Channel 0 Enable" mask="0x100"/>
<bitfield name="CICCEN1" caption="Circular Channel 1 Enable" mask="0x200"/>
<bitfield name="CICCEN2" caption="Circular Channel 2 Enable" mask="0x400"/>
<bitfield name="CICCEN3" caption="Circular Channel 3 Enable" mask="0x800"/>
<bitfield name="POL0" caption="Channel 0 Polarity" mask="0x10000"/>
<bitfield name="POL1" caption="Channel 1 Polarity" mask="0x20000"/>
<bitfield name="POL2" caption="Channel 2 Polarity" mask="0x40000"/>
<bitfield name="POL3" caption="Channel 3 Polarity" mask="0x80000"/>
<bitfield name="SWAP0" caption="Swap DTI Output Pair 0" mask="0x1000000"/>
<bitfield name="SWAP1" caption="Swap DTI Output Pair 1" mask="0x2000000"/>
<bitfield name="SWAP2" caption="Swap DTI Output Pair 2" mask="0x4000000"/>
<bitfield name="SWAP3" caption="Swap DTI Output Pair 3" mask="0x8000000"/>
</register>
<register name="PER" offset="0x40" rw="RW" access="WSYNC" size="4" initval="0xFFFFFFFF" caption="Period">
<mode name="DITH4"/>
<mode name="DITH5"/>
<mode name="DITH6"/>
<mode name="DEFAULT"/>
<bitfield modes="DITH4" name="DITHERCY" caption="Dithering Cycle Number" mask="0xF"/>
<bitfield modes="DITH5" name="DITHERCY" caption="Dithering Cycle Number" mask="0x1F"/>
<bitfield modes="DITH6" name="DITHERCY" caption="Dithering Cycle Number" mask="0x3F"/>
<bitfield modes="DITH6" name="PER" caption="Period Value" mask="0xFFFFC0"/>
<bitfield modes="DITH5" name="PER" caption="Period Value" mask="0xFFFFE0"/>
<bitfield modes="DITH4" name="PER" caption="Period Value" mask="0xFFFFF0"/>
<bitfield modes="DEFAULT" name="PER" caption="Period Value" mask="0xFFFFFF"/>
</register>
<register name="CC" offset="0x44" rw="RW" size="4" count="4" initval="0x00000000" caption="Compare and Capture">
<mode name="DITH4"/>
<mode name="DITH5"/>
<mode name="DITH6"/>
<mode name="DEFAULT"/>
<bitfield modes="DITH4" name="DITHERCY" caption="Dithering Cycle Number" mask="0xF"/>
<bitfield modes="DITH5" name="DITHERCY" caption="Dithering Cycle Number" mask="0x1F"/>
<bitfield modes="DITH6" name="DITHERCY" caption="Dithering Cycle Number" mask="0x3F"/>
<bitfield modes="DITH6" name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFC0"/>
<bitfield modes="DITH5" name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFE0"/>
<bitfield modes="DITH4" name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFF0"/>
<bitfield modes="DEFAULT" name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFFF"/>
</register>
<register name="PATTB" offset="0x64" rw="RW" size="2" initval="0x0000" caption="Pattern Buffer">
<bitfield name="PGEB0" caption="Pattern Generator 0 Output Enable Buffer" mask="0x1"/>
<bitfield name="PGEB1" caption="Pattern Generator 1 Output Enable Buffer" mask="0x2"/>
<bitfield name="PGEB2" caption="Pattern Generator 2 Output Enable Buffer" mask="0x4"/>
<bitfield name="PGEB3" caption="Pattern Generator 3 Output Enable Buffer" mask="0x8"/>
<bitfield name="PGEB4" caption="Pattern Generator 4 Output Enable Buffer" mask="0x10"/>
<bitfield name="PGEB5" caption="Pattern Generator 5 Output Enable Buffer" mask="0x20"/>
<bitfield name="PGEB6" caption="Pattern Generator 6 Output Enable Buffer" mask="0x40"/>
<bitfield name="PGEB7" caption="Pattern Generator 7 Output Enable Buffer" mask="0x80"/>
<bitfield name="PGVB0" caption="Pattern Generator 0 Output Enable" mask="0x100"/>
<bitfield name="PGVB1" caption="Pattern Generator 1 Output Enable" mask="0x200"/>
<bitfield name="PGVB2" caption="Pattern Generator 2 Output Enable" mask="0x400"/>
<bitfield name="PGVB3" caption="Pattern Generator 3 Output Enable" mask="0x800"/>
<bitfield name="PGVB4" caption="Pattern Generator 4 Output Enable" mask="0x1000"/>
<bitfield name="PGVB5" caption="Pattern Generator 5 Output Enable" mask="0x2000"/>
<bitfield name="PGVB6" caption="Pattern Generator 6 Output Enable" mask="0x4000"/>
<bitfield name="PGVB7" caption="Pattern Generator 7 Output Enable" mask="0x8000"/>
</register>
<register name="WAVEB" offset="0x68" rw="RW" size="4" initval="0x00000000" caption="Waveform Control Buffer">
<bitfield name="WAVEGENB" caption="Waveform Generation Buffer" mask="0x7" values="TCC_WAVEB__WAVEGENB"/>
<bitfield name="RAMPB" caption="Ramp Mode Buffer" mask="0x30" values="TCC_WAVEB__RAMPB"/>
<bitfield name="CIPERENB" caption="Circular Period Enable Buffer" mask="0x80"/>
<bitfield name="CICCENB0" caption="Circular Channel 0 Enable Buffer" mask="0x100"/>
<bitfield name="CICCENB1" caption="Circular Channel 1 Enable Buffer" mask="0x200"/>
<bitfield name="CICCENB2" caption="Circular Channel 2 Enable Buffer" mask="0x400"/>
<bitfield name="CICCENB3" caption="Circular Channel 3 Enable Buffer" mask="0x800"/>
<bitfield name="POLB0" caption="Channel 0 Polarity Buffer" mask="0x10000"/>
<bitfield name="POLB1" caption="Channel 1 Polarity Buffer" mask="0x20000"/>
<bitfield name="POLB2" caption="Channel 2 Polarity Buffer" mask="0x40000"/>
<bitfield name="POLB3" caption="Channel 3 Polarity Buffer" mask="0x80000"/>
<bitfield name="SWAPB0" caption="Swap DTI Output Pair 0 Buffer" mask="0x1000000"/>
<bitfield name="SWAPB1" caption="Swap DTI Output Pair 1 Buffer" mask="0x2000000"/>
<bitfield name="SWAPB2" caption="Swap DTI Output Pair 2 Buffer" mask="0x4000000"/>
<bitfield name="SWAPB3" caption="Swap DTI Output Pair 3 Buffer" mask="0x8000000"/>
</register>
<register name="PERB" offset="0x6C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Period Buffer">
<mode name="DITH4"/>
<mode name="DITH5"/>
<mode name="DITH6"/>
<mode name="DEFAULT"/>
<bitfield modes="DITH4" name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0xF"/>
<bitfield modes="DITH5" name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
<bitfield modes="DITH6" name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
<bitfield modes="DITH6" name="PERB" caption="Period Buffer Value" mask="0xFFFFC0"/>
<bitfield modes="DITH5" name="PERB" caption="Period Buffer Value" mask="0xFFFFE0"/>
<bitfield modes="DITH4" name="PERB" caption="Period Buffer Value" mask="0xFFFFF0"/>
<bitfield modes="DEFAULT" name="PERB" caption="Period Buffer Value" mask="0xFFFFFF"/>
</register>
<register name="CCB" offset="0x70" rw="RW" size="4" count="4" initval="0x00000000" caption="Compare and Capture Buffer">
<mode name="DITH4"/>
<mode name="DITH5"/>
<mode name="DITH6"/>
<mode name="DEFAULT"/>
<bitfield modes="DITH4" name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0xF"/>
<bitfield modes="DITH5" name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
<bitfield modes="DITH6" name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
<bitfield modes="DITH6" name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFC0"/>
<bitfield modes="DITH5" name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFE0"/>
<bitfield modes="DITH4" name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFF0"/>
<bitfield modes="DEFAULT" name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFFF"/>
</register>
</register-group>
<value-group name="TCC_CTRLA__PRESCALER">
<value name="DIV1" caption="No division" value="0"/>
<value name="DIV2" caption="Divide by 2" value="1"/>
<value name="DIV4" caption="Divide by 4" value="2"/>
<value name="DIV8" caption="Divide by 8" value="3"/>
<value name="DIV16" caption="Divide by 16" value="4"/>
<value name="DIV64" caption="Divide by 64" value="5"/>
<value name="DIV256" caption="Divide by 256" value="6"/>
<value name="DIV1024" caption="Divide by 1024" value="7"/>
</value-group>
<value-group name="TCC_CTRLA__PRESCSYNC">
<value name="GCLK" caption="Reload or reset counter on next GCLK" value="0"/>
<value name="PRESC" caption="Reload or reset counter on next prescaler clock" value="1"/>
<value name="RESYNC" caption="Reload or reset counter on next GCLK and reset prescaler counter" value="2"/>
</value-group>
<value-group name="TCC_CTRLA__RESOLUTION">
<value name="NONE" caption="Dithering is disabled" value="0"/>
<value name="DITH4" caption="Dithering is done every 16 PWM frames" value="1"/>
<value name="DITH5" caption="Dithering is done every 32 PWM frames" value="2"/>
<value name="DITH6" caption="Dithering is done every 64 PWM frames" value="3"/>
</value-group>
<value-group name="TCC_CTRLBCLR__CMD">
<value name="NONE" caption="No action" value="0"/>
<value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
<value name="STOP" caption="Force stop" value="2"/>
<value name="UPDATE" caption="Force update of double buffered registers" value="3"/>
<value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
</value-group>
<value-group name="TCC_CTRLBCLR__IDXCMD">
<value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
<value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
<value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
<value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
</value-group>
<value-group name="TCC_CTRLBSET__CMD">
<value name="NONE" caption="No action" value="0"/>
<value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
<value name="STOP" caption="Force stop" value="2"/>
<value name="UPDATE" caption="Force update of double buffered registers" value="3"/>
<value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
</value-group>
<value-group name="TCC_CTRLBSET__IDXCMD">
<value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
<value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
<value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
<value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
</value-group>
<value-group name="TCC_FCTRLA__BLANK">
<value name="START" caption="Blanking applied from start of ramp" value="0"/>
<value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
<value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
<value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
</value-group>
<value-group name="TCC_FCTRLA__CAPTURE">
<value name="DISABLE" caption="No capture" value="0"/>
<value name="CAPT" caption="Capture on fault" value="1"/>
<value name="CAPTMIN" caption="Minimum capture" value="2"/>
<value name="CAPTMAX" caption="Maximum capture" value="3"/>
<value name="LOCMIN" caption="Minimum local detection" value="4"/>
<value name="LOCMAX" caption="Maximum local detection" value="5"/>
<value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
<value name="CAPTMARK" caption="Capture with ramp index as MSB value" value="7"/>
</value-group>
<value-group name="TCC_FCTRLA__CHSEL">
<value name="CC0" caption="Capture value stored in channel 0" value="0"/>
<value name="CC1" caption="Capture value stored in channel 1" value="1"/>
<value name="CC2" caption="Capture value stored in channel 2" value="2"/>
<value name="CC3" caption="Capture value stored in channel 3" value="3"/>
</value-group>
<value-group name="TCC_FCTRLA__HALT">
<value name="DISABLE" caption="Halt action disabled" value="0"/>
<value name="HW" caption="Hardware halt action" value="1"/>
<value name="SW" caption="Software halt action" value="2"/>
<value name="NR" caption="Non-recoverable fault" value="3"/>
</value-group>
<value-group name="TCC_FCTRLA__SRC">
<value name="DISABLE" caption="Fault input disabled" value="0"/>
<value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
<value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
<value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
</value-group>
<value-group name="TCC_FCTRLB__BLANK">
<value name="START" caption="Blanking applied from start of ramp" value="0"/>
<value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
<value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
<value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
</value-group>
<value-group name="TCC_FCTRLB__CAPTURE">
<value name="DISABLE" caption="No capture" value="0"/>
<value name="CAPT" caption="Capture on fault" value="1"/>
<value name="CAPTMIN" caption="Minimum capture" value="2"/>
<value name="CAPTMAX" caption="Maximum capture" value="3"/>
<value name="LOCMIN" caption="Minimum local detection" value="4"/>
<value name="LOCMAX" caption="Maximum local detection" value="5"/>
<value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
<value name="CAPTMARK" caption="Capture with ramp index as MSB value" value="7"/>
</value-group>
<value-group name="TCC_FCTRLB__CHSEL">
<value name="CC0" caption="Capture value stored in channel 0" value="0"/>
<value name="CC1" caption="Capture value stored in channel 1" value="1"/>
<value name="CC2" caption="Capture value stored in channel 2" value="2"/>
<value name="CC3" caption="Capture value stored in channel 3" value="3"/>
</value-group>
<value-group name="TCC_FCTRLB__HALT">
<value name="DISABLE" caption="Halt action disabled" value="0"/>
<value name="HW" caption="Hardware halt action" value="1"/>
<value name="SW" caption="Software halt action" value="2"/>
<value name="NR" caption="Non-recoverable fault" value="3"/>
</value-group>
<value-group name="TCC_FCTRLB__SRC">
<value name="DISABLE" caption="Fault input disabled" value="0"/>
<value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
<value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
<value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
</value-group>
<value-group name="TCC_EVCTRL__CNTSEL">
<value name="START" caption="An interrupt/event is generated when a new counter cycle starts" value="0"/>
<value name="END" caption="An interrupt/event is generated when a counter cycle ends" value="1"/>
<value name="BETWEEN" caption="An interrupt/event is generated when a counter cycle ends, except for the first and last cycles" value="2"/>
<value name="BOUNDARY" caption="An interrupt/event is generated when a new counter cycle starts or a counter cycle ends" value="3"/>
</value-group>
<value-group name="TCC_EVCTRL__EVACT0">
<value name="OFF" caption="Event action disabled" value="0"/>
<value name="RETRIGGER" caption="Start, restart or re-trigger counter on event" value="1"/>
<value name="COUNTEV" caption="Count on event" value="2"/>
<value name="START" caption="Start counter on event" value="3"/>
<value name="INC" caption="Increment counter on event" value="4"/>
<value name="COUNT" caption="Count on active state of asynchronous event" value="5"/>
<value name="STAMP" caption="Stamp capture" value="6"/>
<value name="FAULT" caption="Non-recoverable fault" value="7"/>
</value-group>
<value-group name="TCC_EVCTRL__EVACT1">
<value name="OFF" caption="Event action disabled" value="0"/>
<value name="RETRIGGER" caption="Re-trigger counter on event" value="1"/>
<value name="DIR" caption="Direction control" value="2"/>
<value name="STOP" caption="Stop counter on event" value="3"/>
<value name="DEC" caption="Decrement counter on event" value="4"/>
<value name="PPW" caption="Period capture value in CC0 register, pulse width capture value in CC1 register" value="5"/>
<value name="PWP" caption="Period capture value in CC1 register, pulse width capture value in CC0 register" value="6"/>
<value name="FAULT" caption="Non-recoverable fault" value="7"/>
</value-group>
<value-group name="TCC_WAVE__RAMP">
<value name="RAMP1" caption="RAMP1 operation" value="0"/>
<value name="RAMP2A" caption="Alternative RAMP2 operation" value="1"/>
<value name="RAMP2" caption="RAMP2 operation" value="2"/>
<value name="RAMP2C" caption="Critical RAMP2 operation" value="3"/>
</value-group>
<value-group name="TCC_WAVE__WAVEGEN">
<value name="NFRQ" caption="Normal frequency" value="0"/>
<value name="MFRQ" caption="Match frequency" value="1"/>
<value name="NPWM" caption="Normal PWM" value="2"/>
<value name="DSCRITICAL" caption="Dual-slope critical" value="4"/>
<value name="DSBOTTOM" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO" value="5"/>
<value name="DSBOTH" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" value="6"/>
<value name="DSTOP" caption="Dual-slope with interrupt/event condition when COUNT reaches TOP" value="7"/>
</value-group>
<value-group name="TCC_WAVEB__RAMPB">
<value name="RAMP1" caption="RAMP1 operation" value="0"/>
<value name="RAMP2A" caption="Alternative RAMP2 operation" value="1"/>
<value name="RAMP2" caption="RAMP2 operation" value="2"/>
<value name="RAMP2C" caption="Critical RAMP2 operation" value="3"/>
</value-group>
<value-group name="TCC_WAVEB__WAVEGENB">
<value name="NFRQ" caption="Normal frequency" value="0"/>
<value name="MFRQ" caption="Match frequency" value="1"/>
<value name="NPWM" caption="Normal PWM" value="2"/>
<value name="DSCRITICAL" caption="Dual-slope critical" value="4"/>
<value name="DSBOTTOM" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO" value="5"/>
<value name="DSBOTH" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" value="6"/>
<value name="DSTOP" caption="Dual-slope with interrupt/event condition when COUNT reaches TOP" value="7"/>
</value-group>
</module>
<module name="WDT" id="U2203" version="2.0.0" caption="Watchdog Timer">
<register-group name="WDT" caption="Watchdog Timer">
<register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
<bitfield name="ENABLE" caption="Enable" mask="0x2"/>
<bitfield name="WEN" caption="Watchdog Timer Window Mode Enable" mask="0x4"/>
<bitfield name="ALWAYSON" caption="Always-On" mask="0x80"/>
</register>
<register name="CONFIG" offset="0x1" rw="RW" access="WSYNC" size="1" initval="0xBB" caption="Configuration">
<bitfield name="PER" caption="Time-Out Period" mask="0xF" values="WDT_CONFIG__PER"/>
<bitfield name="WINDOW" caption="Window Mode Time-Out Period" mask="0xF0" values="WDT_CONFIG__WINDOW"/>
</register>
<register name="EWCTRL" offset="0x2" rw="RW" size="1" initval="0x0B" caption="Early Warning Interrupt Control">
<bitfield name="EWOFFSET" caption="Early Warning Interrupt Time Offset" mask="0xF" values="WDT_EWCTRL__EWOFFSET"/>
</register>
<register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
<bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
</register>
<register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
<bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
</register>
<register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
<bitfield name="EW" caption="Early Warning" mask="0x1"/>
</register>
<register name="STATUS" offset="0x7" rw="R" size="1" initval="0x00" caption="Status">
<bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
</register>
<register name="CLEAR" offset="0x8" rw="W" access="WSYNC" size="1" initval="0x00" caption="Clear">
<bitfield name="CLEAR" caption="Watchdog Clear" mask="0xFF" values="WDT_CLEAR__CLEAR"/>
</register>
</register-group>
<value-group name="WDT_CONFIG__PER">
<value name="8" caption="8 clock cycles" value="0x0"/>
<value name="16" caption="16 clock cycles" value="0x1"/>
<value name="32" caption="32 clock cycles" value="0x2"/>
<value name="64" caption="64 clock cycles" value="0x3"/>
<value name="128" caption="128 clock cycles" value="0x4"/>
<value name="256" caption="256 clock cycles" value="0x5"/>
<value name="512" caption="512 clock cycles" value="0x6"/>
<value name="1K" caption="1024 clock cycles" value="0x7"/>
<value name="2K" caption="2048 clock cycles" value="0x8"/>
<value name="4K" caption="4096 clock cycles" value="0x9"/>
<value name="8K" caption="8192 clock cycles" value="0xA"/>
<value name="16K" caption="16384 clock cycles" value="0xB"/>
</value-group>
<value-group name="WDT_CONFIG__WINDOW">
<value name="8" caption="8 clock cycles" value="0x0"/>
<value name="16" caption="16 clock cycles" value="0x1"/>
<value name="32" caption="32 clock cycles" value="0x2"/>
<value name="64" caption="64 clock cycles" value="0x3"/>
<value name="128" caption="128 clock cycles" value="0x4"/>
<value name="256" caption="256 clock cycles" value="0x5"/>
<value name="512" caption="512 clock cycles" value="0x6"/>
<value name="1K" caption="1024 clock cycles" value="0x7"/>
<value name="2K" caption="2048 clock cycles" value="0x8"/>
<value name="4K" caption="4096 clock cycles" value="0x9"/>
<value name="8K" caption="8192 clock cycles" value="0xA"/>
<value name="16K" caption="16384 clock cycles" value="0xB"/>
</value-group>
<value-group name="WDT_EWCTRL__EWOFFSET">
<value name="8" caption="8 clock cycles" value="0x0"/>
<value name="16" caption="16 clock cycles" value="0x1"/>
<value name="32" caption="32 clock cycles" value="0x2"/>
<value name="64" caption="64 clock cycles" value="0x3"/>
<value name="128" caption="128 clock cycles" value="0x4"/>
<value name="256" caption="256 clock cycles" value="0x5"/>
<value name="512" caption="512 clock cycles" value="0x6"/>
<value name="1K" caption="1024 clock cycles" value="0x7"/>
<value name="2K" caption="2048 clock cycles" value="0x8"/>
<value name="4K" caption="4096 clock cycles" value="0x9"/>
<value name="8K" caption="8192 clock cycles" value="0xA"/>
<value name="16K" caption="16384 clock cycles" value="0xB"/>
</value-group>
<value-group name="WDT_CLEAR__CLEAR">
<value name="KEY" caption="Clear Key" value="0xA5"/>
</value-group>
</module>
<module name="NVIC" version="1.0.0" caption="Nested Vectored Interrupt Controller">
<register-group name="NVIC" caption="Nested Vectored Interrupt Controller">
<register name="ISER" offset="0x0" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Interrupt Set Enable Register">
<bitfield name="SETENA" caption="Interrupt set enable bits" mask="0x1FFFFFFF"/>
</register>
<register name="ICER" offset="0x80" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Interrupt Clear Enable Register">
<bitfield name="CLRENA" caption="Interrupt clear-enable bits" mask="0x1FFFFFFF"/>
</register>
<register name="ISPR" offset="0x100" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Interrupt Set Pending Register">
<bitfield name="SETPEND" caption="Interrupt set-pending bits" mask="0x1FFFFFFF"/>
</register>
<register name="ICPR" offset="0x180" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Interrupt Clear Pending Register">
<bitfield name="CLRPEND" caption="Interrupt clear-pending bits" mask="0x1FFFFFFF"/>
</register>
<register name="IPR" offset="0x300" rw="RW" size="4" access-size="4" count="8" initval="0x00000000" caption="Interrupt Priority Register n">
<bitfield name="PRI0" caption="Priority of interrupt n" mask="0x3"/>
<bitfield name="PRI1" caption="Priority of interrupt n" mask="0x300"/>
<bitfield name="PRI2" caption="Priority of interrupt n" mask="0x30000"/>
<bitfield name="PRI3" caption="Priority of interrupt n" mask="0x3000000"/>
</register>
</register-group>
</module>
<module name="SysTick" version="1.0.0" caption="System timer">
<register-group name="SysTick" caption="System timer">
<register name="CSR" offset="0x0" rw="RW" size="4" access-size="4" initval="0x4" caption="SysTick Control and Status Register">
<bitfield name="ENABLE" caption="SysTick Counter Enable" mask="0x1" values="SysTick_CSR__ENABLE"/>
<bitfield name="TICKINT" caption="SysTick Exception Request Enable" mask="0x2" values="SysTick_CSR__TICKINT"/>
<bitfield name="CLKSOURCE" caption="Clock Source 0=external, 1=processor" mask="0x4" values="SysTick_CSR__CLKSOURCE"/>
<bitfield name="COUNTFLAG" caption="Timer counted to 0 since last read of register" mask="0x10000"/>
</register>
<register name="RVR" offset="0x4" rw="RW" size="4" access-size="4" caption="SysTick Reload Value Register">
<bitfield name="RELOAD" caption="Value to load into the SysTick Current Value Register when the counter reaches 0" mask="0xFFFFFF"/>
</register>
<register name="CVR" offset="0x8" rw="RW" size="4" access-size="4" caption="SysTick Current Value Register">
<bitfield name="CURRENT" caption="Current value at the time the register is accessed" mask="0xFFFFFF"/>
</register>
<register name="CALIB" offset="0xC" rw="R" size="4" access-size="4" initval="0" caption="SysTick Calibration Value Register">
<bitfield name="TENMS" caption="Reload value to use for 10ms timing" mask="0xFFFFFF"/>
<bitfield name="SKEW" caption="TENMS is rounded from non-integer ratio" mask="0x40000000" values="SysTick_CALIB__SKEW"/>
<bitfield name="NOREF" caption="No Separate Reference Clock" mask="0x80000000" values="SysTick_CALIB__NOREF"/>
</register>
</register-group>
<value-group name="SysTick_CSR__CLKSOURCE">
<value name="VALUE_0" caption="External clock" value="0"/>
<value name="VALUE_1" caption="Processor clock" value="1"/>
</value-group>
<value-group name="SysTick_CSR__ENABLE">
<value name="VALUE_0" caption="Counter disabled" value="0"/>
<value name="VALUE_1" caption="Counter enabled" value="1"/>
</value-group>
<value-group name="SysTick_CSR__TICKINT">
<value name="VALUE_0" caption="Counting down to 0 does not assert the SysTick exception request" value="0"/>
<value name="VALUE_1" caption="Counting down to 0 asserts the SysTick exception request" value="1"/>
</value-group>
<value-group name="SysTick_CALIB__NOREF">
<value name="VALUE_0" caption="The reference clock is provided" value="0"/>
<value name="VALUE_1" caption="The reference clock is not provided" value="1"/>
</value-group>
<value-group name="SysTick_CALIB__SKEW">
<value name="VALUE_0" caption="10ms calibration value is exact" value="0"/>
<value name="VALUE_1" caption="10ms calibration value is inexact, because of the clock frequency" value="1"/>
</value-group>
</module>
<module name="SystemControl" version="1.0.0" caption="System Control Registers">
<register-group name="SystemControl" caption="System Control Registers">
<register name="CPUID" offset="0xD00" rw="R" size="4" access-size="4" initval="0x410CC601" caption="CPUID Base Register">
<bitfield name="REVISION" caption="Minor revision number" mask="0xF"/>
<bitfield name="PARTNO" caption="Processor Part Number, 0xC60=Cortex-M0+" mask="0xFFF0"/>
<bitfield name="ARCHITECTURE" caption="Processor Architecture, 0xC=ARMv6-M" mask="0xF0000"/>
<bitfield name="VARIANT" caption="Major revision number" mask="0xF00000"/>
<bitfield name="IMPLEMENTER" caption="Implementer code, ARM=0x41" mask="0xFF000000"/>
</register>
<register name="ICSR" offset="0xD04" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Interrupt Control and State Register">
<bitfield name="VECTACTIVE" caption="Debug: Exception number of currently executing exception, or 0 if thread mode" mask="0x1FF"/>
<bitfield name="VECTPENDING" caption="Exception number of the highest priority pending enabled exception" mask="0x1FF000"/>
<bitfield name="ISRPENDING" caption="Debug: NVIC interrupt pending" mask="0x400000"/>
<bitfield name="ISRPREEMPT" caption="Debug: Pending exception serviced on exit from debug halt" mask="0x800000"/>
<bitfield name="PENDSTCLR" caption="SysTick exception clear-pending bit" mask="0x2000000" values="SystemControl_ICSR__PENDSTCLR"/>
<bitfield name="PENDSTSET" caption="SysTick exception set-pending bit" mask="0x4000000" values="SystemControl_ICSR__PENDSTSET"/>
<bitfield name="PENDSVCLR" caption="PendSV clear-pending bit" mask="0x8000000" values="SystemControl_ICSR__PENDSVCLR"/>
<bitfield name="PENDSVSET" caption="PendSV set-pending bit" mask="0x10000000" values="SystemControl_ICSR__PENDSVSET"/>
<bitfield name="NMIPENDSET" caption="NMI set-pending bit" mask="0x80000000" values="SystemControl_ICSR__NMIPENDSET"/>
</register>
<register name="VTOR" offset="0xD08" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Vector Table Offset Register">
<bitfield name="TBLOFF" caption="Vector table base offset" mask="0xFFFFFF80"/>
</register>
<register name="AIRCR" offset="0xD0C" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Application Interrupt and Reset Control Register">
<bitfield name="VECTCLRACTIVE" caption="Debug: Clear state information" mask="0x2"/>
<bitfield name="SYSRESETREQ" caption="System Reset Request" mask="0x4" values="SystemControl_AIRCR__SYSRESETREQ"/>
<bitfield name="ENDIANNESS" caption="Data Endianness, 0=little, 1=big" mask="0x8000" values="SystemControl_AIRCR__ENDIANNESS"/>
<bitfield name="VECTKEY" caption="Register key (0x05FA)" mask="0xFFFF0000"/>
</register>
<register name="SCR" offset="0xD10" rw="RW" size="4" access-size="4" initval="0x00000000" caption="System Control Register">
<bitfield name="SLEEPONEXIT" caption="Sleep-On-Exit when exiting Handler mode" mask="0x2" values="SystemControl_SCR__SLEEPONEXIT"/>
<bitfield name="SLEEPDEEP" caption="Uses Deep Sleep as low power mode" mask="0x4" values="SystemControl_SCR__SLEEPDEEP"/>
<bitfield name="SEVONPEND" caption="Send Event on Pending bit" mask="0x10" values="SystemControl_SCR__SEVONPEND"/>
</register>
<register name="CCR" offset="0xD14" rw="R" size="4" access-size="4" initval="0x00000204" caption="Configuration and Control Register">
<bitfield name="UNALIGN_TRP" caption="Unaligned accesses generates a Hard Fault" mask="0x8" values="SystemControl_CCR__UNALIGN_TRP"/>
<bitfield name="STKALIGN" caption="Stack 8-byte aligned on exception entry" mask="0x200" values="SystemControl_CCR__STKALIGN"/>
</register>
<register name="SHPR2" offset="0xD1C" rw="RW" size="4" access-size="4" initval="0x00000000" caption="System Handler Priority Register 2">
<bitfield name="PRI_11" caption="Priority of system handler 11, SVCall" mask="0xFF000000"/>
</register>
<register name="SHPR3" offset="0xD20" rw="RW" size="4" access-size="4" initval="0x00000000" caption="System Handler Priority Register 3">
<bitfield name="PRI_14" caption="Priority of system handler 14, PendSV" mask="0xFF0000"/>
<bitfield name="PRI_15" caption="Priority of system handler 15, SysTick exception" mask="0xFF000000"/>
</register>
<register name="SHCSR" offset="0xD24" rw="RW" size="4" access-size="4" initval="0x00000000" caption="System Handler Control and State Register">
<bitfield name="SVCALLPENDED" caption="no description available" mask="0x8000"/>
</register>
<register name="DFSR" offset="0xD30" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Debug Fault Status Register">
<bitfield name="HALTED" caption="Halt request debug event active" mask="0x1"/>
<bitfield name="BKPT" caption="Breakpoint debug event" mask="0x2"/>
<bitfield name="DWTTRAP" caption="DWT debug event" mask="0x4"/>
<bitfield name="VCATCH" caption="Vector catch debug event" mask="0x8"/>
<bitfield name="EXTERNAL" caption="EDBGRQ debug event" mask="0x10"/>
</register>
</register-group>
<value-group name="SystemControl_ICSR__NMIPENDSET">
<value name="VALUE_0" caption="Write: no effect; read: NMI exception is not pending" value="0"/>
<value name="VALUE_1" caption="Write: changes NMI exception state to pending; read: NMI exception is pending" value="1"/>
</value-group>
<value-group name="SystemControl_ICSR__PENDSTCLR">
<value name="VALUE_0" caption="No effect" value="0"/>
<value name="VALUE_1" caption="Removes the pending state from the SysTick exception" value="1"/>
</value-group>
<value-group name="SystemControl_ICSR__PENDSTSET">
<value name="VALUE_0" caption="Write: no effect; read: SysTick exception is not pending" value="0"/>
<value name="VALUE_1" caption="Write: changes SysTick exception state to pending; read: SysTick exception is pending" value="1"/>
</value-group>
<value-group name="SystemControl_ICSR__PENDSVCLR">
<value name="VALUE_0" caption="No effect" value="0"/>
<value name="VALUE_1" caption="Removes the pending state from the PendSV exception" value="1"/>
</value-group>
<value-group name="SystemControl_ICSR__PENDSVSET">
<value name="VALUE_0" caption="Write: no effect; read: PendSV exception is not pending" value="0"/>
<value name="VALUE_1" caption="Write: changes PendSV exception state to pending; read: PendSV exception is pending" value="1"/>
</value-group>
<value-group name="SystemControl_AIRCR__ENDIANNESS">
<value name="VALUE_0" caption="Little-endian" value="0"/>
<value name="VALUE_1" caption="Big-endian" value="1"/>
</value-group>
<value-group name="SystemControl_AIRCR__SYSRESETREQ">
<value name="VALUE_0" caption="No system reset request" value="0"/>
<value name="VALUE_1" caption="Asserts a signal to the outer system that requests a reset" value="1"/>
</value-group>
<value-group name="SystemControl_SCR__SEVONPEND">
<value name="VALUE_0" caption="Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded" value="0"/>
<value name="VALUE_1" caption="Enabled events and all interrupts, including disabled interrupts, can wakeup the processor" value="1"/>
</value-group>
<value-group name="SystemControl_SCR__SLEEPDEEP">
<value name="VALUE_0" caption="Sleep" value="0"/>
<value name="VALUE_1" caption="Deep sleep" value="1"/>
</value-group>
<value-group name="SystemControl_SCR__SLEEPONEXIT">
<value name="VALUE_0" caption="O not sleep when returning to Thread mode" value="0"/>
<value name="VALUE_1" caption="Enter sleep, or deep sleep, on return from an ISR" value="1"/>
</value-group>
<value-group name="SystemControl_CCR__STKALIGN">
<value name="VALUE_0" caption="4-byte aligned" value="0"/>
<value name="VALUE_1" caption="8-byte aligned" value="1"/>
</value-group>
<value-group name="SystemControl_CCR__UNALIGN_TRP">
<value name="VALUE_0" caption="Do not trap unaligned halfword and word accesses" value="0"/>
<value name="VALUE_1" caption="Trap unaligned halfword and word accesses" value="1"/>
</value-group>
</module>
</modules>
<pinouts>
<pinout name="SAMD21G1xL" caption="SAMD21G1xL">
<pin position="1" pad="PA02"/>
<pin position="2" pad="PA03"/>
<pin position="3" pad="PB04"/>
<pin position="4" pad="PB05"/>
<pin position="5" pad="GNDANA"/>
<pin position="6" pad="VDDANA"/>
<pin position="7" pad="PB08"/>
<pin position="8" pad="PB09"/>
<pin position="9" pad="PA04"/>
<pin position="10" pad="PA05"/>
<pin position="11" pad="PA06"/>
<pin position="12" pad="PA07"/>
<pin position="13" pad="PA08"/>
<pin position="14" pad="PA09"/>
<pin position="15" pad="PA10"/>
<pin position="16" pad="PA11"/>
<pin position="17" pad="VDDIO"/>
<pin position="18" pad="GNDIO"/>
<pin position="19" pad="PB10"/>
<pin position="20" pad="PB11"/>
<pin position="21" pad="PA12"/>
<pin position="22" pad="PA13"/>
<pin position="23" pad="PA14"/>
<pin position="24" pad="PA15"/>
<pin position="25" pad="PA16"/>
<pin position="26" pad="PA17"/>
<pin position="27" pad="PA18"/>
<pin position="28" pad="PA19"/>
<pin position="29" pad="PA20"/>
<pin position="30" pad="PA21"/>
<pin position="31" pad="PA22"/>
<pin position="32" pad="PA23"/>
<pin position="33" pad="PA24"/>
<pin position="34" pad="PA25"/>
<pin position="35" pad="GNDIO"/>
<pin position="36" pad="VDDIO"/>
<pin position="37" pad="PA27"/>
<pin position="38" pad="RESET_N"/>
<pin position="39" pad="PA28"/>
<pin position="40" pad="GNDIO"/>
<pin position="41" pad="VDDCORE"/>
<pin position="42" pad="VDDIN"/>
<pin position="43" pad="PA30"/>
<pin position="44" pad="PA31"/>
<pin position="45" pad="PB00"/>
<pin position="46" pad="PB01"/>
<pin position="47" pad="PB02"/>
<pin position="48" pad="PB03"/>
</pinout>
</pinouts>
</avr-tools-device-file>