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170 lines
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170 lines
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4 years ago
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<div id="projectname">SAME54P20A Test Project
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<div class="summary">
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<a href="#pub-attribs">Data Fields</a> </div>
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<div class="headertitle">
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<div class="title">TcCount8 Struct Reference</div> </div>
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<div class="contents">
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<p>TC_COUNT8 hardware registers.
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<a href="structTcCount8.html#details">More...</a></p>
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<p><code>#include <<a class="el" href="tc_8h_source.html">tc.h</a>></code></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
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Data Fields</h2></td></tr>
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<tr class="memitem:a21e470a693ab9a740db77ae81a32a204"><td class="memItemLeft" align="right" valign="top"><a id="a21e470a693ab9a740db77ae81a32a204"></a>
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__IO <a class="el" href="unionTC__CTRLA__Type.html">TC_CTRLA_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcCount8.html#a21e470a693ab9a740db77ae81a32a204">CTRLA</a></td></tr>
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<tr class="memdesc:a21e470a693ab9a740db77ae81a32a204"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00 (R/W 32) Control A. <br /></td></tr>
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<tr class="separator:a21e470a693ab9a740db77ae81a32a204"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abaaa0d5d4c7229363bb86f848c833d44"><td class="memItemLeft" align="right" valign="top"><a id="abaaa0d5d4c7229363bb86f848c833d44"></a>
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__IO <a class="el" href="unionTC__CTRLBCLR__Type.html">TC_CTRLBCLR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcCount8.html#abaaa0d5d4c7229363bb86f848c833d44">CTRLBCLR</a></td></tr>
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<tr class="memdesc:abaaa0d5d4c7229363bb86f848c833d44"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x04 (R/W 8) Control B Clear. <br /></td></tr>
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<tr class="separator:abaaa0d5d4c7229363bb86f848c833d44"><td class="memSeparator" colspan="2"> </td></tr>
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__IO <a class="el" href="unionTC__CTRLBSET__Type.html">TC_CTRLBSET_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcCount8.html#a73eb558d0c3044cda0b077a127ec310e">CTRLBSET</a></td></tr>
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<tr class="memdesc:a73eb558d0c3044cda0b077a127ec310e"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x05 (R/W 8) Control B Set. <br /></td></tr>
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__IO <a class="el" href="unionTC__EVCTRL__Type.html">TC_EVCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcCount8.html#aa480b79673b58b625051603406154192">EVCTRL</a></td></tr>
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<tr class="memdesc:aa480b79673b58b625051603406154192"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x06 (R/W 16) Event Control. <br /></td></tr>
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<tr class="separator:aa480b79673b58b625051603406154192"><td class="memSeparator" colspan="2"> </td></tr>
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__IO <a class="el" href="unionTC__INTENCLR__Type.html">TC_INTENCLR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcCount8.html#a06374e1d0aeda26de80ba031b6f199e3">INTENCLR</a></td></tr>
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<tr class="memdesc:a06374e1d0aeda26de80ba031b6f199e3"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x08 (R/W 8) Interrupt Enable Clear. <br /></td></tr>
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__IO <a class="el" href="unionTC__INTENSET__Type.html">TC_INTENSET_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcCount8.html#acfb9d660f23d4eb039b9f9fe4cf05ae6">INTENSET</a></td></tr>
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<tr class="memdesc:acfb9d660f23d4eb039b9f9fe4cf05ae6"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x09 (R/W 8) Interrupt Enable Set. <br /></td></tr>
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__IO <a class="el" href="unionTC__INTFLAG__Type.html">TC_INTFLAG_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcCount8.html#a880de196c959459996c34fc09a3b0931">INTFLAG</a></td></tr>
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<tr class="memdesc:a880de196c959459996c34fc09a3b0931"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear. <br /></td></tr>
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__IO <a class="el" href="unionTC__STATUS__Type.html">TC_STATUS_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcCount8.html#a1a7aed76a285ba4836a6fe9efbaa705a">STATUS</a></td></tr>
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<tr class="memdesc:a1a7aed76a285ba4836a6fe9efbaa705a"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0B (R/W 8) Status. <br /></td></tr>
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<tr class="memitem:a0bc830a79dcf2aceafca52bc429b523c"><td class="memItemLeft" align="right" valign="top"><a id="a0bc830a79dcf2aceafca52bc429b523c"></a>
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__IO <a class="el" href="unionTC__WAVE__Type.html">TC_WAVE_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcCount8.html#a0bc830a79dcf2aceafca52bc429b523c">WAVE</a></td></tr>
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<tr class="memdesc:a0bc830a79dcf2aceafca52bc429b523c"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0C (R/W 8) Waveform Generation Control. <br /></td></tr>
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<tr class="separator:a0bc830a79dcf2aceafca52bc429b523c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a23889449cd650031c370b1f03f0086c9"><td class="memItemLeft" align="right" valign="top"><a id="a23889449cd650031c370b1f03f0086c9"></a>
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__IO <a class="el" href="unionTC__DRVCTRL__Type.html">TC_DRVCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcCount8.html#a23889449cd650031c370b1f03f0086c9">DRVCTRL</a></td></tr>
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<tr class="memdesc:a23889449cd650031c370b1f03f0086c9"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0D (R/W 8) Control C. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved1</b> [0x1]</td></tr>
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<tr class="separator:a48c6b267e0e3bdee3f4922ca42a66273"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7018e4fc53620e33ef25040c46a76ebf"><td class="memItemLeft" align="right" valign="top"><a id="a7018e4fc53620e33ef25040c46a76ebf"></a>
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__IO <a class="el" href="unionTC__DBGCTRL__Type.html">TC_DBGCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcCount8.html#a7018e4fc53620e33ef25040c46a76ebf">DBGCTRL</a></td></tr>
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<tr class="memdesc:a7018e4fc53620e33ef25040c46a76ebf"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0F (R/W 8) Debug Control. <br /></td></tr>
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<tr class="separator:a7018e4fc53620e33ef25040c46a76ebf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a77b15b99edea84545027d3e0c2db75ed"><td class="memItemLeft" align="right" valign="top"><a id="a77b15b99edea84545027d3e0c2db75ed"></a>
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__I <a class="el" href="unionTC__SYNCBUSY__Type.html">TC_SYNCBUSY_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcCount8.html#a77b15b99edea84545027d3e0c2db75ed">SYNCBUSY</a></td></tr>
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<tr class="memdesc:a77b15b99edea84545027d3e0c2db75ed"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x10 (R/ 32) Synchronization Status. <br /></td></tr>
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<tr class="separator:a77b15b99edea84545027d3e0c2db75ed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8eb17b36ee1d22d0fcc456fe1e997c27"><td class="memItemLeft" align="right" valign="top"><a id="a8eb17b36ee1d22d0fcc456fe1e997c27"></a>
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__IO <a class="el" href="unionTC__COUNT8__COUNT__Type.html">TC_COUNT8_COUNT_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcCount8.html#a8eb17b36ee1d22d0fcc456fe1e997c27">COUNT</a></td></tr>
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<tr class="memdesc:a8eb17b36ee1d22d0fcc456fe1e997c27"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x14 (R/W 8) COUNT8 Count. <br /></td></tr>
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<tr class="separator:a8eb17b36ee1d22d0fcc456fe1e997c27"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a87593919da2e8cd700e3e7f538367d0c"><td class="memItemLeft" align="right" valign="top"><a id="a87593919da2e8cd700e3e7f538367d0c"></a>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved2</b> [0x6]</td></tr>
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<tr class="separator:a87593919da2e8cd700e3e7f538367d0c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a65ca77877619f7224efe3bd897d60111"><td class="memItemLeft" align="right" valign="top"><a id="a65ca77877619f7224efe3bd897d60111"></a>
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__IO <a class="el" href="unionTC__COUNT8__PER__Type.html">TC_COUNT8_PER_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcCount8.html#a65ca77877619f7224efe3bd897d60111">PER</a></td></tr>
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<tr class="memdesc:a65ca77877619f7224efe3bd897d60111"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1B (R/W 8) COUNT8 Period. <br /></td></tr>
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<tr class="separator:a65ca77877619f7224efe3bd897d60111"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a63f3513aba9d9cb6c35ac47fdeca38f8"><td class="memItemLeft" align="right" valign="top"><a id="a63f3513aba9d9cb6c35ac47fdeca38f8"></a>
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__IO <a class="el" href="unionTC__COUNT8__CC__Type.html">TC_COUNT8_CC_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcCount8.html#a63f3513aba9d9cb6c35ac47fdeca38f8">CC</a> [2]</td></tr>
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<tr class="memdesc:a63f3513aba9d9cb6c35ac47fdeca38f8"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1C (R/W 8) COUNT8 Compare and Capture. <br /></td></tr>
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<tr class="separator:a63f3513aba9d9cb6c35ac47fdeca38f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acecf5406789382c5d22ed187c3c8e3ed"><td class="memItemLeft" align="right" valign="top"><a id="acecf5406789382c5d22ed187c3c8e3ed"></a>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved3</b> [0x11]</td></tr>
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<tr class="separator:acecf5406789382c5d22ed187c3c8e3ed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1f3009b7014485cceb3f7aafc786ce5c"><td class="memItemLeft" align="right" valign="top"><a id="a1f3009b7014485cceb3f7aafc786ce5c"></a>
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__IO <a class="el" href="unionTC__COUNT8__PERBUF__Type.html">TC_COUNT8_PERBUF_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcCount8.html#a1f3009b7014485cceb3f7aafc786ce5c">PERBUF</a></td></tr>
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<tr class="memdesc:a1f3009b7014485cceb3f7aafc786ce5c"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x2F (R/W 8) COUNT8 Period Buffer. <br /></td></tr>
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__IO <a class="el" href="unionTC__COUNT8__CCBUF__Type.html">TC_COUNT8_CCBUF_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structTcCount8.html#ad61b04161f510eb7d65eb3f21215bf62">CCBUF</a> [2]</td></tr>
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<tr class="memdesc:ad61b04161f510eb7d65eb3f21215bf62"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x30 (R/W 8) COUNT8 Compare and Capture Buffer. <br /></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>TC_COUNT8 hardware registers. </p>
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<p class="definition">Definition at line <a class="el" href="tc_8h_source.html#l00769">769</a> of file <a class="el" href="tc_8h_source.html">tc.h</a>.</p>
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</div><hr/>The documentation for this struct was generated from the following file:<ul>
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<li>/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/<a class="el" href="tc_8h_source.html">tc.h</a></li>
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