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4 years ago
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<a href="#pub-attribs">Data Fields</a> </div>
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<div class="title">Eic Struct Reference</div> </div>
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<div class="contents">
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<p>EIC hardware registers.
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<a href="structEic.html#details">More...</a></p>
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<p><code>#include <<a class="el" href="component_2eic_8h_source.html">eic.h</a>></code></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
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Data Fields</h2></td></tr>
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<tr class="memitem:a3d945ae1fb5d005dae206bdcec01db95"><td class="memItemLeft" align="right" valign="top"><a id="a3d945ae1fb5d005dae206bdcec01db95"></a>
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__IO <a class="el" href="unionEIC__CTRLA__Type.html">EIC_CTRLA_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structEic.html#a3d945ae1fb5d005dae206bdcec01db95">CTRLA</a></td></tr>
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<tr class="memdesc:a3d945ae1fb5d005dae206bdcec01db95"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00 (R/W 8) Control A. <br /></td></tr>
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<tr class="memitem:abe387c3f6c50f72e37e91adf3d9eac06"><td class="memItemLeft" align="right" valign="top"><a id="abe387c3f6c50f72e37e91adf3d9eac06"></a>
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__IO <a class="el" href="unionEIC__NMICTRL__Type.html">EIC_NMICTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structEic.html#abe387c3f6c50f72e37e91adf3d9eac06">NMICTRL</a></td></tr>
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<tr class="memdesc:abe387c3f6c50f72e37e91adf3d9eac06"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x01 (R/W 8) Non-Maskable Interrupt Control. <br /></td></tr>
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<tr class="separator:abe387c3f6c50f72e37e91adf3d9eac06"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5e489fa962a835e2d06a4dceb6e2b7b8"><td class="memItemLeft" align="right" valign="top"><a id="a5e489fa962a835e2d06a4dceb6e2b7b8"></a>
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__IO <a class="el" href="unionEIC__NMIFLAG__Type.html">EIC_NMIFLAG_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structEic.html#a5e489fa962a835e2d06a4dceb6e2b7b8">NMIFLAG</a></td></tr>
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<tr class="memdesc:a5e489fa962a835e2d06a4dceb6e2b7b8"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x02 (R/W 16) Non-Maskable Interrupt Flag Status and Clear. <br /></td></tr>
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<tr class="memitem:a857746620cc45693036554a5441ade79"><td class="memItemLeft" align="right" valign="top"><a id="a857746620cc45693036554a5441ade79"></a>
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__I <a class="el" href="unionEIC__SYNCBUSY__Type.html">EIC_SYNCBUSY_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structEic.html#a857746620cc45693036554a5441ade79">SYNCBUSY</a></td></tr>
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<tr class="memdesc:a857746620cc45693036554a5441ade79"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x04 (R/ 32) Synchronization Busy. <br /></td></tr>
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__IO <a class="el" href="unionEIC__EVCTRL__Type.html">EIC_EVCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structEic.html#a228fdf5b1f970d352ab14e03de8f4d35">EVCTRL</a></td></tr>
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<tr class="memdesc:a228fdf5b1f970d352ab14e03de8f4d35"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x08 (R/W 32) Event Control. <br /></td></tr>
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__IO <a class="el" href="unionEIC__INTENCLR__Type.html">EIC_INTENCLR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structEic.html#ac499ecb4ba54624fb0f534bfff917bcc">INTENCLR</a></td></tr>
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<tr class="memdesc:ac499ecb4ba54624fb0f534bfff917bcc"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0C (R/W 32) Interrupt Enable Clear. <br /></td></tr>
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__IO <a class="el" href="unionEIC__INTENSET__Type.html">EIC_INTENSET_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structEic.html#ac9db1d0fed533fb55777efe3f1d98c69">INTENSET</a></td></tr>
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<tr class="memdesc:ac9db1d0fed533fb55777efe3f1d98c69"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x10 (R/W 32) Interrupt Enable Set. <br /></td></tr>
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<tr class="memitem:a487a1c3a7123a446a051251d64aba60f"><td class="memItemLeft" align="right" valign="top"><a id="a487a1c3a7123a446a051251d64aba60f"></a>
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__IO <a class="el" href="unionEIC__INTFLAG__Type.html">EIC_INTFLAG_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structEic.html#a487a1c3a7123a446a051251d64aba60f">INTFLAG</a></td></tr>
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<tr class="memdesc:a487a1c3a7123a446a051251d64aba60f"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x14 (R/W 32) Interrupt Flag Status and Clear. <br /></td></tr>
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<tr class="memitem:afeaef43f4273900190ad63f2b28484bf"><td class="memItemLeft" align="right" valign="top"><a id="afeaef43f4273900190ad63f2b28484bf"></a>
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__IO <a class="el" href="unionEIC__ASYNCH__Type.html">EIC_ASYNCH_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structEic.html#afeaef43f4273900190ad63f2b28484bf">ASYNCH</a></td></tr>
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<tr class="memdesc:afeaef43f4273900190ad63f2b28484bf"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x18 (R/W 32) External Interrupt Asynchronous Mode. <br /></td></tr>
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<tr class="memitem:a95e5655d7106c582cb9e93e65825309b"><td class="memItemLeft" align="right" valign="top"><a id="a95e5655d7106c582cb9e93e65825309b"></a>
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__IO <a class="el" href="unionEIC__CONFIG__Type.html">EIC_CONFIG_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structEic.html#a95e5655d7106c582cb9e93e65825309b">CONFIG</a> [2]</td></tr>
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<tr class="memdesc:a95e5655d7106c582cb9e93e65825309b"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1C (R/W 32) External Interrupt Sense Configuration. <br /></td></tr>
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<tr class="memitem:aa8ad901e1ddf8513778da3312f036e6f"><td class="memItemLeft" align="right" valign="top"><a id="aa8ad901e1ddf8513778da3312f036e6f"></a>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved1</b> [0xC]</td></tr>
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<tr class="memitem:a519456f45a9143228c193e35df43837d"><td class="memItemLeft" align="right" valign="top"><a id="a519456f45a9143228c193e35df43837d"></a>
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__IO <a class="el" href="unionEIC__DEBOUNCEN__Type.html">EIC_DEBOUNCEN_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structEic.html#a519456f45a9143228c193e35df43837d">DEBOUNCEN</a></td></tr>
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<tr class="memdesc:a519456f45a9143228c193e35df43837d"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x30 (R/W 32) Debouncer Enable. <br /></td></tr>
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<tr class="memitem:a60c2b51111dc88120f0748e946350ba4"><td class="memItemLeft" align="right" valign="top"><a id="a60c2b51111dc88120f0748e946350ba4"></a>
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__IO <a class="el" href="unionEIC__DPRESCALER__Type.html">EIC_DPRESCALER_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structEic.html#a60c2b51111dc88120f0748e946350ba4">DPRESCALER</a></td></tr>
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<tr class="memdesc:a60c2b51111dc88120f0748e946350ba4"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x34 (R/W 32) Debouncer Prescaler. <br /></td></tr>
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<tr class="memitem:a28fd24a69edd14ae2c0889f2268f7273"><td class="memItemLeft" align="right" valign="top"><a id="a28fd24a69edd14ae2c0889f2268f7273"></a>
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__I <a class="el" href="unionEIC__PINSTATE__Type.html">EIC_PINSTATE_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structEic.html#a28fd24a69edd14ae2c0889f2268f7273">PINSTATE</a></td></tr>
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<tr class="memdesc:a28fd24a69edd14ae2c0889f2268f7273"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x38 (R/ 32) Pin State. <br /></td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>EIC hardware registers. </p>
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<p class="definition">Definition at line <a class="el" href="component_2eic_8h_source.html#l00477">477</a> of file <a class="el" href="component_2eic_8h_source.html">eic.h</a>.</p>
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</div><hr/>The documentation for this struct was generated from the following file:<ul>
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<li>/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/<a class="el" href="component_2eic_8h_source.html">eic.h</a></li>
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</ul>
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</div><!-- contents -->
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Generated by <a href="http://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.8.20
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</small></address>
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</body>
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