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102 lines
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102 lines
8.3 KiB
HTML
4 years ago
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<title>i386-Variations - Using as</title>
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<meta name="description" content="Using as">
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<link title="Top" rel="start" href="index.html#Top">
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<link rel="up" href="i386_002dSyntax.html#i386_002dSyntax" title="i386-Syntax">
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<link rel="next" href="i386_002dChars.html#i386_002dChars" title="i386-Chars">
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<link href="http://www.gnu.org/software/texinfo/" rel="generator-home" title="Texinfo Homepage">
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<!--
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This file documents the GNU Assembler "as".
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Copyright (C) 1991-2015 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.3
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or any later version published by the Free Software Foundation;
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with no Invariant Sections, with no Front-Cover Texts, and with no
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Back-Cover Texts. A copy of the license is included in the
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section entitled ``GNU Free Documentation License''.
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--></style>
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</head>
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<body>
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<div class="node">
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<a name="i386-Variations"></a>
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<a name="i386_002dVariations"></a>
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<p>
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Next: <a rel="next" accesskey="n" href="i386_002dChars.html#i386_002dChars">i386-Chars</a>,
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Up: <a rel="up" accesskey="u" href="i386_002dSyntax.html#i386_002dSyntax">i386-Syntax</a>
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<hr>
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</div>
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<h5 class="subsubsection">9.15.3.1 AT&T Syntax versus Intel Syntax</h5>
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<p><a name="index-i386-intel_005fsyntax-pseudo-op-1028"></a><a name="index-intel_005fsyntax-pseudo-op_002c-i386-1029"></a><a name="index-i386-att_005fsyntax-pseudo-op-1030"></a><a name="index-att_005fsyntax-pseudo-op_002c-i386-1031"></a><a name="index-i386-syntax-compatibility-1032"></a><a name="index-syntax-compatibility_002c-i386-1033"></a><a name="index-x86_002d64-intel_005fsyntax-pseudo-op-1034"></a><a name="index-intel_005fsyntax-pseudo-op_002c-x86_002d64-1035"></a><a name="index-x86_002d64-att_005fsyntax-pseudo-op-1036"></a><a name="index-att_005fsyntax-pseudo-op_002c-x86_002d64-1037"></a><a name="index-x86_002d64-syntax-compatibility-1038"></a><a name="index-syntax-compatibility_002c-x86_002d64-1039"></a>
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<code>as</code> now supports assembly using Intel assembler syntax.
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<code>.intel_syntax</code> selects Intel mode, and <code>.att_syntax</code> switches
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back to the usual AT&T mode for compatibility with the output of
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<code>gcc</code>. Either of these directives may have an optional
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argument, <code>prefix</code>, or <code>noprefix</code> specifying whether registers
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require a ‘<samp><span class="samp">%</span></samp>’ prefix. AT&T System V/386 assembler syntax is quite
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different from Intel syntax. We mention these differences because
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almost all 80386 documents use Intel syntax. Notable differences
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between the two syntaxes are:
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<p><a name="index-immediate-operands_002c-i386-1040"></a><a name="index-i386-immediate-operands-1041"></a><a name="index-register-operands_002c-i386-1042"></a><a name="index-i386-register-operands-1043"></a><a name="index-jump_002fcall-operands_002c-i386-1044"></a><a name="index-i386-jump_002fcall-operands-1045"></a><a name="index-operand-delimiters_002c-i386-1046"></a>
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<a name="index-immediate-operands_002c-x86_002d64-1047"></a><a name="index-x86_002d64-immediate-operands-1048"></a><a name="index-register-operands_002c-x86_002d64-1049"></a><a name="index-x86_002d64-register-operands-1050"></a><a name="index-jump_002fcall-operands_002c-x86_002d64-1051"></a><a name="index-x86_002d64-jump_002fcall-operands-1052"></a><a name="index-operand-delimiters_002c-x86_002d64-1053"></a>
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<ul>
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<li>AT&T immediate operands are preceded by ‘<samp><span class="samp">$</span></samp>’; Intel immediate
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operands are undelimited (Intel ‘<samp><span class="samp">push 4</span></samp>’ is AT&T ‘<samp><span class="samp">pushl $4</span></samp>’).
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AT&T register operands are preceded by ‘<samp><span class="samp">%</span></samp>’; Intel register operands
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are undelimited. AT&T absolute (as opposed to PC relative) jump/call
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operands are prefixed by ‘<samp><span class="samp">*</span></samp>’; they are undelimited in Intel syntax.
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<p><a name="index-i386-source_002c-destination-operands-1054"></a><a name="index-source_002c-destination-operands_003b-i386-1055"></a><a name="index-x86_002d64-source_002c-destination-operands-1056"></a><a name="index-source_002c-destination-operands_003b-x86_002d64-1057"></a><li>AT&T and Intel syntax use the opposite order for source and destination
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operands. Intel ‘<samp><span class="samp">add eax, 4</span></samp>’ is ‘<samp><span class="samp">addl $4, %eax</span></samp>’. The
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‘<samp><span class="samp">source, dest</span></samp>’ convention is maintained for compatibility with
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previous Unix assemblers. Note that ‘<samp><span class="samp">bound</span></samp>’, ‘<samp><span class="samp">invlpga</span></samp>’, and
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instructions with 2 immediate operands, such as the ‘<samp><span class="samp">enter</span></samp>’
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instruction, do <em>not</em> have reversed order. <a href="i386_002dBugs.html#i386_002dBugs">i386-Bugs</a>.
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<p><a name="index-mnemonic-suffixes_002c-i386-1058"></a><a name="index-sizes-operands_002c-i386-1059"></a><a name="index-i386-size-suffixes-1060"></a><a name="index-mnemonic-suffixes_002c-x86_002d64-1061"></a><a name="index-sizes-operands_002c-x86_002d64-1062"></a><a name="index-x86_002d64-size-suffixes-1063"></a><li>In AT&T syntax the size of memory operands is determined from the last
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character of the instruction mnemonic. Mnemonic suffixes of ‘<samp><span class="samp">b</span></samp>’,
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‘<samp><span class="samp">w</span></samp>’, ‘<samp><span class="samp">l</span></samp>’ and ‘<samp><span class="samp">q</span></samp>’ specify byte (8-bit), word (16-bit), long
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(32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes
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this by prefixing memory operands (<em>not</em> the instruction mnemonics) with
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‘<samp><span class="samp">byte ptr</span></samp>’, ‘<samp><span class="samp">word ptr</span></samp>’, ‘<samp><span class="samp">dword ptr</span></samp>’ and ‘<samp><span class="samp">qword ptr</span></samp>’. Thus,
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Intel ‘<samp><span class="samp">mov al, byte ptr </span><var>foo</var></samp>’ is ‘<samp><span class="samp">movb </span><var>foo</var><span class="samp">, %al</span></samp>’ in AT&T
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syntax.
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<p>In 64-bit code, ‘<samp><span class="samp">movabs</span></samp>’ can be used to encode the ‘<samp><span class="samp">mov</span></samp>’
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instruction with the 64-bit displacement or immediate operand.
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<p><a name="index-return-instructions_002c-i386-1064"></a><a name="index-i386-jump_002c-call_002c-return-1065"></a><a name="index-return-instructions_002c-x86_002d64-1066"></a><a name="index-x86_002d64-jump_002c-call_002c-return-1067"></a><li>Immediate form long jumps and calls are
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‘<samp><span class="samp">lcall/ljmp $</span><var>section</var><span class="samp">, $</span><var>offset</var></samp>’ in AT&T syntax; the
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Intel syntax is
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‘<samp><span class="samp">call/jmp far </span><var>section</var><span class="samp">:</span><var>offset</var></samp>’. Also, the far return
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instruction
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is ‘<samp><span class="samp">lret $</span><var>stack-adjust</var></samp>’ in AT&T syntax; Intel syntax is
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‘<samp><span class="samp">ret far </span><var>stack-adjust</var></samp>’.
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<p><a name="index-sections_002c-i386-1068"></a><a name="index-i386-sections-1069"></a><a name="index-sections_002c-x86_002d64-1070"></a><a name="index-x86_002d64-sections-1071"></a><li>The AT&T assembler does not provide support for multiple section
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programs. Unix style systems expect all programs to be single sections.
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</ul>
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</body></html>
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