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289 lines
16 KiB
HTML
4 years ago
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<head>
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<title>i386-Options - Using as</title>
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<meta name="description" content="Using as">
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<link title="Top" rel="start" href="index.html#Top">
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<link rel="up" href="i386_002dDependent.html#i386_002dDependent" title="i386-Dependent">
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<link rel="next" href="i386_002dDirectives.html#i386_002dDirectives" title="i386-Directives">
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<link href="http://www.gnu.org/software/texinfo/" rel="generator-home" title="Texinfo Homepage">
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<!--
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This file documents the GNU Assembler "as".
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Copyright (C) 1991-2015 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.3
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or any later version published by the Free Software Foundation;
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with no Invariant Sections, with no Front-Cover Texts, and with no
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Back-Cover Texts. A copy of the license is included in the
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section entitled ``GNU Free Documentation License''.
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-->
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--></style>
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</head>
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<body>
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<div class="node">
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<a name="i386-Options"></a>
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<a name="i386_002dOptions"></a>
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<p>
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Next: <a rel="next" accesskey="n" href="i386_002dDirectives.html#i386_002dDirectives">i386-Directives</a>,
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Up: <a rel="up" accesskey="u" href="i386_002dDependent.html#i386_002dDependent">i386-Dependent</a>
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<hr>
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</div>
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<h4 class="subsection">9.15.1 Options</h4>
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<p><a name="index-options-for-i386-983"></a><a name="index-options-for-x86_002d64-984"></a><a name="index-i386-options-985"></a><a name="index-x86_002d64-options-986"></a>
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The i386 version of <code>as</code> has a few machine
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dependent options:
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<!-- man begin OPTIONS -->
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<a name="index-g_t_0040samp_007b_002d_002d32_007d-option_002c-i386-987"></a>
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<a name="index-g_t_0040samp_007b_002d_002d32_007d-option_002c-x86_002d64-988"></a>
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<a name="index-g_t_0040samp_007b_002d_002dx32_007d-option_002c-i386-989"></a>
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<a name="index-g_t_0040samp_007b_002d_002dx32_007d-option_002c-x86_002d64-990"></a>
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<a name="index-g_t_0040samp_007b_002d_002d64_007d-option_002c-i386-991"></a>
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<a name="index-g_t_0040samp_007b_002d_002d64_007d-option_002c-x86_002d64-992"></a>
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<dl><dt><code>--32 | --x32 | --64</code><dd>Select the word size, either 32 bits or 64 bits. ‘<samp><span class="samp">--32</span></samp>’
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implies Intel i386 architecture, while ‘<samp><span class="samp">--x32</span></samp>’ and ‘<samp><span class="samp">--64</span></samp>’
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imply AMD x86-64 architecture with 32-bit or 64-bit word-size
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respectively.
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<p>These options are only available with the ELF object file format, and
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require that the necessary BFD support has been included (on a 32-bit
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platform you have to add –enable-64-bit-bfd to configure enable 64-bit
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usage and use x86-64 as target platform).
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<br><dt><code>-n</code><dd>By default, x86 GAS replaces multiple nop instructions used for
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alignment within code sections with multi-byte nop instructions such
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as leal 0(%esi,1),%esi. This switch disables the optimization.
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<p><a name="index-g_t_0040samp_007b_002d_002ddivide_007d-option_002c-i386-993"></a><br><dt><code>--divide</code><dd>On SVR4-derived platforms, the character ‘<samp><span class="samp">/</span></samp>’ is treated as a comment
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character, which means that it cannot be used in expressions. The
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‘<samp><span class="samp">--divide</span></samp>’ option turns ‘<samp><span class="samp">/</span></samp>’ into a normal character. This does
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not disable ‘<samp><span class="samp">/</span></samp>’ at the beginning of a line starting a comment, or
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affect using ‘<samp><span class="samp">#</span></samp>’ for starting a comment.
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<p><a name="index-g_t_0040samp_007b_002dmarch_003d_007d-option_002c-i386-994"></a><a name="index-g_t_0040samp_007b_002dmarch_003d_007d-option_002c-x86_002d64-995"></a><br><dt><code>-march=</code><var>CPU</var><code>[+</code><var>EXTENSION</var><code>...]</code><dd>This option specifies the target processor. The assembler will
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issue an error message if an attempt is made to assemble an instruction
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which will not execute on the target processor. The following
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processor names are recognized:
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<code>i8086</code>,
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<code>i186</code>,
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<code>i286</code>,
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<code>i386</code>,
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<code>i486</code>,
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<code>i586</code>,
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<code>i686</code>,
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<code>pentium</code>,
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<code>pentiumpro</code>,
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<code>pentiumii</code>,
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<code>pentiumiii</code>,
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<code>pentium4</code>,
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<code>prescott</code>,
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<code>nocona</code>,
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<code>core</code>,
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<code>core2</code>,
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<code>corei7</code>,
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<code>l1om</code>,
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<code>k1om</code>,
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<code>iamcu</code>,
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<code>k6</code>,
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<code>k6_2</code>,
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<code>athlon</code>,
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<code>opteron</code>,
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<code>k8</code>,
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<code>amdfam10</code>,
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<code>bdver1</code>,
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<code>bdver2</code>,
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<code>bdver3</code>,
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<code>bdver4</code>,
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<code>znver1</code>,
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<code>btver1</code>,
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<code>btver2</code>,
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<code>generic32</code> and
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<code>generic64</code>.
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<p>In addition to the basic instruction set, the assembler can be told to
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accept various extension mnemonics. For example,
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<code>-march=i686+sse4+vmx</code> extends <var>i686</var> with <var>sse4</var> and
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<var>vmx</var>. The following extensions are currently supported:
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<code>8087</code>,
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<code>287</code>,
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<code>387</code>,
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<code>no87</code>,
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<code>mmx</code>,
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<code>nommx</code>,
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<code>sse</code>,
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<code>sse2</code>,
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<code>sse3</code>,
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<code>ssse3</code>,
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<code>sse4.1</code>,
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<code>sse4.2</code>,
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<code>sse4</code>,
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<code>nosse</code>,
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<code>avx</code>,
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<code>avx2</code>,
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<code>adx</code>,
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<code>rdseed</code>,
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<code>prfchw</code>,
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<code>smap</code>,
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<code>mpx</code>,
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<code>sha</code>,
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<code>prefetchwt1</code>,
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<code>clflushopt</code>,
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<code>se1</code>,
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<code>clwb</code>,
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<code>pcommit</code>,
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<code>avx512f</code>,
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<code>avx512cd</code>,
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<code>avx512er</code>,
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<code>avx512pf</code>,
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<code>avx512vl</code>,
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<code>avx512bw</code>,
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<code>avx512dq</code>,
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<code>avx512ifma</code>,
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<code>avx512vbmi</code>,
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<code>noavx</code>,
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<code>vmx</code>,
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<code>vmfunc</code>,
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<code>smx</code>,
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<code>xsave</code>,
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<code>xsaveopt</code>,
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<code>xsavec</code>,
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<code>xsaves</code>,
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<code>aes</code>,
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<code>pclmul</code>,
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<code>fsgsbase</code>,
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<code>rdrnd</code>,
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<code>f16c</code>,
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<code>bmi2</code>,
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<code>fma</code>,
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<code>movbe</code>,
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<code>ept</code>,
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<code>lzcnt</code>,
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<code>hle</code>,
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<code>rtm</code>,
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<code>invpcid</code>,
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<code>clflush</code>,
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<code>mwaitx</code>,
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<code>clzero</code>,
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<code>lwp</code>,
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<code>fma4</code>,
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<code>xop</code>,
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<code>cx16</code>,
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<code>syscall</code>,
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<code>rdtscp</code>,
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<code>3dnow</code>,
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<code>3dnowa</code>,
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<code>sse4a</code>,
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<code>sse5</code>,
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<code>svme</code>,
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<code>abm</code> and
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<code>padlock</code>.
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Note that rather than extending a basic instruction set, the extension
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mnemonics starting with <code>no</code> revoke the respective functionality.
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<p>When the <code>.arch</code> directive is used with <samp><span class="option">-march</span></samp>, the
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<code>.arch</code> directive will take precedent.
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<p><a name="index-g_t_0040samp_007b_002dmtune_003d_007d-option_002c-i386-996"></a><a name="index-g_t_0040samp_007b_002dmtune_003d_007d-option_002c-x86_002d64-997"></a><br><dt><code>-mtune=</code><var>CPU</var><dd>This option specifies a processor to optimize for. When used in
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conjunction with the <samp><span class="option">-march</span></samp> option, only instructions
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of the processor specified by the <samp><span class="option">-march</span></samp> option will be
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generated.
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<p>Valid <var>CPU</var> values are identical to the processor list of
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<samp><span class="option">-march=</span><var>CPU</var></samp>.
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<p><a name="index-g_t_0040samp_007b_002dmsse2avx_007d-option_002c-i386-998"></a><a name="index-g_t_0040samp_007b_002dmsse2avx_007d-option_002c-x86_002d64-999"></a><br><dt><code>-msse2avx</code><dd>This option specifies that the assembler should encode SSE instructions
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with VEX prefix.
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<p><a name="index-g_t_0040samp_007b_002dmsse_002dcheck_003d_007d-option_002c-i386-1000"></a><a name="index-g_t_0040samp_007b_002dmsse_002dcheck_003d_007d-option_002c-x86_002d64-1001"></a><br><dt><code>-msse-check=</code><var>none</var><dt><code>-msse-check=</code><var>warning</var><dt><code>-msse-check=</code><var>error</var><dd>These options control if the assembler should check SSE instructions.
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<samp><span class="option">-msse-check=</span><var>none</var></samp> will make the assembler not to check SSE
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instructions, which is the default. <samp><span class="option">-msse-check=</span><var>warning</var></samp>
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will make the assembler issue a warning for any SSE instruction.
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<samp><span class="option">-msse-check=</span><var>error</var></samp> will make the assembler issue an error
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for any SSE instruction.
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<p><a name="index-g_t_0040samp_007b_002dmavxscalar_003d_007d-option_002c-i386-1002"></a><a name="index-g_t_0040samp_007b_002dmavxscalar_003d_007d-option_002c-x86_002d64-1003"></a><br><dt><code>-mavxscalar=</code><var>128</var><dt><code>-mavxscalar=</code><var>256</var><dd>These options control how the assembler should encode scalar AVX
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instructions. <samp><span class="option">-mavxscalar=</span><var>128</var></samp> will encode scalar
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AVX instructions with 128bit vector length, which is the default.
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<samp><span class="option">-mavxscalar=</span><var>256</var></samp> will encode scalar AVX instructions
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with 256bit vector length.
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<p><a name="index-g_t_0040samp_007b_002dmevexlig_003d_007d-option_002c-i386-1004"></a><a name="index-g_t_0040samp_007b_002dmevexlig_003d_007d-option_002c-x86_002d64-1005"></a><br><dt><code>-mevexlig=</code><var>128</var><dt><code>-mevexlig=</code><var>256</var><dt><code>-mevexlig=</code><var>512</var><dd>These options control how the assembler should encode length-ignored
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(LIG) EVEX instructions. <samp><span class="option">-mevexlig=</span><var>128</var></samp> will encode LIG
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EVEX instructions with 128bit vector length, which is the default.
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<samp><span class="option">-mevexlig=</span><var>256</var></samp> and <samp><span class="option">-mevexlig=</span><var>512</var></samp> will
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encode LIG EVEX instructions with 256bit and 512bit vector length,
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respectively.
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<p><a name="index-g_t_0040samp_007b_002dmevexwig_003d_007d-option_002c-i386-1006"></a><a name="index-g_t_0040samp_007b_002dmevexwig_003d_007d-option_002c-x86_002d64-1007"></a><br><dt><code>-mevexwig=</code><var>0</var><dt><code>-mevexwig=</code><var>1</var><dd>These options control how the assembler should encode w-ignored (WIG)
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EVEX instructions. <samp><span class="option">-mevexwig=</span><var>0</var></samp> will encode WIG
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EVEX instructions with evex.w = 0, which is the default.
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<samp><span class="option">-mevexwig=</span><var>1</var></samp> will encode WIG EVEX instructions with
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evex.w = 1.
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<p><a name="index-g_t_0040samp_007b_002dmmnemonic_003d_007d-option_002c-i386-1008"></a><a name="index-g_t_0040samp_007b_002dmmnemonic_003d_007d-option_002c-x86_002d64-1009"></a><br><dt><code>-mmnemonic=</code><var>att</var><dt><code>-mmnemonic=</code><var>intel</var><dd>This option specifies instruction mnemonic for matching instructions.
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The <code>.att_mnemonic</code> and <code>.intel_mnemonic</code> directives will
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take precedent.
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<p><a name="index-g_t_0040samp_007b_002dmsyntax_003d_007d-option_002c-i386-1010"></a><a name="index-g_t_0040samp_007b_002dmsyntax_003d_007d-option_002c-x86_002d64-1011"></a><br><dt><code>-msyntax=</code><var>att</var><dt><code>-msyntax=</code><var>intel</var><dd>This option specifies instruction syntax when processing instructions.
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The <code>.att_syntax</code> and <code>.intel_syntax</code> directives will
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take precedent.
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<p><a name="index-g_t_0040samp_007b_002dmnaked_002dreg_007d-option_002c-i386-1012"></a><a name="index-g_t_0040samp_007b_002dmnaked_002dreg_007d-option_002c-x86_002d64-1013"></a><br><dt><code>-mnaked-reg</code><dd>This opetion specifies that registers don't require a ‘<samp><span class="samp">%</span></samp>’ prefix.
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The <code>.att_syntax</code> and <code>.intel_syntax</code> directives will take precedent.
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<p><a name="index-g_t_0040samp_007b_002dmadd_002dbnd_002dprefix_007d-option_002c-i386-1014"></a><a name="index-g_t_0040samp_007b_002dmadd_002dbnd_002dprefix_007d-option_002c-x86_002d64-1015"></a><br><dt><code>-madd-bnd-prefix</code><dd>This option forces the assembler to add BND prefix to all branches, even
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if such prefix was not explicitly specified in the source code.
|
||
|
|
|
||
|
|
<p><a name="index-g_t_0040samp_007b_002dmshared_007d-option_002c-i386-1016"></a><a name="index-g_t_0040samp_007b_002dmshared_007d-option_002c-x86_002d64-1017"></a><br><dt><code>-mno-shared</code><dd>On ELF target, the assembler normally optimizes out non-PLT relocations
|
||
|
|
against defined non-weak global branch targets with default visibility.
|
||
|
|
The ‘<samp><span class="samp">-mshared</span></samp>’ option tells the assembler to generate code which
|
||
|
|
may go into a shared library where all non-weak global branch targets
|
||
|
|
with default visibility can be preempted. The resulting code is
|
||
|
|
slightly bigger. This option only affects the handling of branch
|
||
|
|
instructions.
|
||
|
|
|
||
|
|
<p><a name="index-g_t_0040samp_007b_002dmbig_002dobj_007d-option_002c-x86_002d64-1018"></a><br><dt><code>-mbig-obj</code><dd>On x86-64 PE/COFF target this option forces the use of big object file
|
||
|
|
format, which allows more than 32768 sections.
|
||
|
|
|
||
|
|
<p><a name="index-g_t_0040samp_007b_002dmomit_002dlock_002dprefix_003d_007d-option_002c-i386-1019"></a><a name="index-g_t_0040samp_007b_002dmomit_002dlock_002dprefix_003d_007d-option_002c-x86_002d64-1020"></a><br><dt><code>-momit-lock-prefix=</code><var>no</var><dt><code>-momit-lock-prefix=</code><var>yes</var><dd>These options control how the assembler should encode lock prefix.
|
||
|
|
This option is intended as a workaround for processors, that fail on
|
||
|
|
lock prefix. This option can only be safely used with single-core,
|
||
|
|
single-thread computers
|
||
|
|
<samp><span class="option">-momit-lock-prefix=</span><var>yes</var></samp> will omit all lock prefixes.
|
||
|
|
<samp><span class="option">-momit-lock-prefix=</span><var>no</var></samp> will encode lock prefix as usual,
|
||
|
|
which is the default.
|
||
|
|
|
||
|
|
<p><a name="index-g_t_0040samp_007b_002dmevexrcig_003d_007d-option_002c-i386-1021"></a><a name="index-g_t_0040samp_007b_002dmevexrcig_003d_007d-option_002c-x86_002d64-1022"></a><br><dt><code>-mevexrcig=</code><var>rne</var><dt><code>-mevexrcig=</code><var>rd</var><dt><code>-mevexrcig=</code><var>ru</var><dt><code>-mevexrcig=</code><var>rz</var><dd>These options control how the assembler should encode SAE-only
|
||
|
|
EVEX instructions. <samp><span class="option">-mevexrcig=</span><var>rne</var></samp> will encode RC bits
|
||
|
|
of EVEX instruction with 00, which is the default.
|
||
|
|
<samp><span class="option">-mevexrcig=</span><var>rd</var></samp>, <samp><span class="option">-mevexrcig=</span><var>ru</var></samp>
|
||
|
|
and <samp><span class="option">-mevexrcig=</span><var>rz</var></samp> will encode SAE-only EVEX instructions
|
||
|
|
with 01, 10 and 11 RC bits, respectively.
|
||
|
|
|
||
|
|
<p><a name="index-g_t_0040samp_007b_002dmamd64_007d-option_002c-x86_002d64-1023"></a><a name="index-g_t_0040samp_007b_002dmintel64_007d-option_002c-x86_002d64-1024"></a><br><dt><code>-mamd64</code><dt><code>-mintel64</code><dd>This option specifies that the assembler should accept only AMD64 or
|
||
|
|
Intel64 ISA in 64-bit mode. The default is to accept both.
|
||
|
|
|
||
|
|
</dl>
|
||
|
|
<!-- man end -->
|
||
|
|
|
||
|
|
</body></html>
|
||
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