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217 lines
11 KiB
HTML
217 lines
11 KiB
HTML
4 years ago
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<html lang="en">
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<title>Sparc-Regs - Using as</title>
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<meta name="description" content="Using as">
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<link title="Top" rel="start" href="index.html#Top">
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<link rel="up" href="Sparc_002dSyntax.html#Sparc_002dSyntax" title="Sparc-Syntax">
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<link rel="prev" href="Sparc_002dChars.html#Sparc_002dChars" title="Sparc-Chars">
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<link rel="next" href="Sparc_002dConstants.html#Sparc_002dConstants" title="Sparc-Constants">
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<link href="http://www.gnu.org/software/texinfo/" rel="generator-home" title="Texinfo Homepage">
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<!--
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This file documents the GNU Assembler "as".
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Copyright (C) 1991-2015 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.3
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or any later version published by the Free Software Foundation;
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with no Invariant Sections, with no Front-Cover Texts, and with no
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Back-Cover Texts. A copy of the license is included in the
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section entitled ``GNU Free Documentation License''.
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--></style>
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</head>
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<body>
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<div class="node">
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<a name="Sparc-Regs"></a>
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<a name="Sparc_002dRegs"></a>
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<p>
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Next: <a rel="next" accesskey="n" href="Sparc_002dConstants.html#Sparc_002dConstants">Sparc-Constants</a>,
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Previous: <a rel="previous" accesskey="p" href="Sparc_002dChars.html#Sparc_002dChars">Sparc-Chars</a>,
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Up: <a rel="up" accesskey="u" href="Sparc_002dSyntax.html#Sparc_002dSyntax">Sparc-Syntax</a>
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<hr>
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</div>
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<h5 class="subsubsection">9.42.3.2 Register Names</h5>
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<p><a name="index-Sparc-registers-2022"></a><a name="index-register-names_002c-Sparc-2023"></a>
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The Sparc integer register file is broken down into global,
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outgoing, local, and incoming.
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<ul>
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<li>The 8 global registers are referred to as ‘<samp><span class="samp">%g</span><var>n</var></samp>’.
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<li>The 8 outgoing registers are referred to as ‘<samp><span class="samp">%o</span><var>n</var></samp>’.
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<li>The 8 local registers are referred to as ‘<samp><span class="samp">%l</span><var>n</var></samp>’.
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<li>The 8 incoming registers are referred to as ‘<samp><span class="samp">%i</span><var>n</var></samp>’.
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<li>The frame pointer register ‘<samp><span class="samp">%i6</span></samp>’ can be referenced using
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the alias ‘<samp><span class="samp">%fp</span></samp>’.
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<li>The stack pointer register ‘<samp><span class="samp">%o6</span></samp>’ can be referenced using
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the alias ‘<samp><span class="samp">%sp</span></samp>’.
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</ul>
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<p>Floating point registers are simply referred to as ‘<samp><span class="samp">%f</span><var>n</var></samp>’.
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When assembling for pre-V9, only 32 floating point registers
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are available. For V9 and later there are 64, but there are
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restrictions when referencing the upper 32 registers. They
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can only be accessed as double or quad, and thus only even
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or quad numbered accesses are allowed. For example, ‘<samp><span class="samp">%f34</span></samp>’
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is a legal floating point register, but ‘<samp><span class="samp">%f35</span></samp>’ is not.
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<p>Certain V9 instructions allow access to ancillary state registers.
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Most simply they can be referred to as ‘<samp><span class="samp">%asr</span><var>n</var></samp>’ where
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<var>n</var> can be from 16 to 31. However, there are some aliases
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defined to reference ASR registers defined for various UltraSPARC
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processors:
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<ul>
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<li>The tick compare register is referred to as ‘<samp><span class="samp">%tick_cmpr</span></samp>’.
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<li>The system tick register is referred to as ‘<samp><span class="samp">%stick</span></samp>’. An alias,
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‘<samp><span class="samp">%sys_tick</span></samp>’, exists but is deprecated and should not be used
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by new software.
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<li>The system tick compare register is referred to as ‘<samp><span class="samp">%stick_cmpr</span></samp>’.
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An alias, ‘<samp><span class="samp">%sys_tick_cmpr</span></samp>’, exists but is deprecated and should
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not be used by new software.
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<li>The software interrupt register is referred to as ‘<samp><span class="samp">%softint</span></samp>’.
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<li>The set software interrupt register is referred to as ‘<samp><span class="samp">%set_softint</span></samp>’.
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The mnemonic ‘<samp><span class="samp">%softint_set</span></samp>’ is provided as an alias.
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<li>The clear software interrupt register is referred to as
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‘<samp><span class="samp">%clear_softint</span></samp>’. The mnemonic ‘<samp><span class="samp">%softint_clear</span></samp>’ is provided
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as an alias.
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<li>The performance instrumentation counters register is referred to as
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‘<samp><span class="samp">%pic</span></samp>’.
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<li>The performance control register is referred to as ‘<samp><span class="samp">%pcr</span></samp>’.
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<li>The graphics status register is referred to as ‘<samp><span class="samp">%gsr</span></samp>’.
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<li>The V9 dispatch control register is referred to as ‘<samp><span class="samp">%dcr</span></samp>’.
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</ul>
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<p>Various V9 branch and conditional move instructions allow
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specification of which set of integer condition codes to
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test. These are referred to as ‘<samp><span class="samp">%xcc</span></samp>’ and ‘<samp><span class="samp">%icc</span></samp>’.
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<p>Additionally, GAS supports the so-called “natural” condition codes;
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these are referred to as ‘<samp><span class="samp">%ncc</span></samp>’ and reference to ‘<samp><span class="samp">%icc</span></samp>’ if
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the word size is 32, ‘<samp><span class="samp">%xcc</span></samp>’ if the word size is 64.
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<p>In V9, there are 4 sets of floating point condition codes
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which are referred to as ‘<samp><span class="samp">%fcc</span><var>n</var></samp>’.
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<p>Several special privileged and non-privileged registers
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exist:
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<ul>
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<li>The V9 address space identifier register is referred to as ‘<samp><span class="samp">%asi</span></samp>’.
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<li>The V9 restorable windows register is referred to as ‘<samp><span class="samp">%canrestore</span></samp>’.
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<li>The V9 savable windows register is referred to as ‘<samp><span class="samp">%cansave</span></samp>’.
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<li>The V9 clean windows register is referred to as ‘<samp><span class="samp">%cleanwin</span></samp>’.
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<li>The V9 current window pointer register is referred to as ‘<samp><span class="samp">%cwp</span></samp>’.
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<li>The floating-point queue register is referred to as ‘<samp><span class="samp">%fq</span></samp>’.
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<li>The V8 co-processor queue register is referred to as ‘<samp><span class="samp">%cq</span></samp>’.
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<li>The floating point status register is referred to as ‘<samp><span class="samp">%fsr</span></samp>’.
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<li>The other windows register is referred to as ‘<samp><span class="samp">%otherwin</span></samp>’.
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<li>The V9 program counter register is referred to as ‘<samp><span class="samp">%pc</span></samp>’.
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<li>The V9 next program counter register is referred to as ‘<samp><span class="samp">%npc</span></samp>’.
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<li>The V9 processor interrupt level register is referred to as ‘<samp><span class="samp">%pil</span></samp>’.
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<li>The V9 processor state register is referred to as ‘<samp><span class="samp">%pstate</span></samp>’.
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<li>The trap base address register is referred to as ‘<samp><span class="samp">%tba</span></samp>’.
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<li>The V9 tick register is referred to as ‘<samp><span class="samp">%tick</span></samp>’.
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<li>The V9 trap level is referred to as ‘<samp><span class="samp">%tl</span></samp>’.
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<li>The V9 trap program counter is referred to as ‘<samp><span class="samp">%tpc</span></samp>’.
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<li>The V9 trap next program counter is referred to as ‘<samp><span class="samp">%tnpc</span></samp>’.
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<li>The V9 trap state is referred to as ‘<samp><span class="samp">%tstate</span></samp>’.
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<li>The V9 trap type is referred to as ‘<samp><span class="samp">%tt</span></samp>’.
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<li>The V9 condition codes is referred to as ‘<samp><span class="samp">%ccr</span></samp>’.
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<li>The V9 floating-point registers state is referred to as ‘<samp><span class="samp">%fprs</span></samp>’.
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<li>The V9 version register is referred to as ‘<samp><span class="samp">%ver</span></samp>’.
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<li>The V9 window state register is referred to as ‘<samp><span class="samp">%wstate</span></samp>’.
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<li>The Y register is referred to as ‘<samp><span class="samp">%y</span></samp>’.
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<li>The V8 window invalid mask register is referred to as ‘<samp><span class="samp">%wim</span></samp>’.
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<li>The V8 processor state register is referred to as ‘<samp><span class="samp">%psr</span></samp>’.
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<li>The V9 global register level register is referred to as ‘<samp><span class="samp">%gl</span></samp>’.
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</ul>
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<p>Several special register names exist for hypervisor mode code:
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<ul>
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<li>The hyperprivileged processor state register is referred to as
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‘<samp><span class="samp">%hpstate</span></samp>’.
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<li>The hyperprivileged trap state register is referred to as ‘<samp><span class="samp">%htstate</span></samp>’.
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<li>The hyperprivileged interrupt pending register is referred to as
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‘<samp><span class="samp">%hintp</span></samp>’.
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<li>The hyperprivileged trap base address register is referred to as
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‘<samp><span class="samp">%htba</span></samp>’.
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<li>The hyperprivileged implementation version register is referred
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to as ‘<samp><span class="samp">%hver</span></samp>’.
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<li>The hyperprivileged system tick offset register is referred to as
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‘<samp><span class="samp">%hstick_offset</span></samp>’. Note that there is no ‘<samp><span class="samp">%hstick</span></samp>’ register,
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the normal ‘<samp><span class="samp">%stick</span></samp>’ is used.
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<li>The hyperprivileged system tick enable register is referred to as
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‘<samp><span class="samp">%hstick_enable</span></samp>’.
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<li>The hyperprivileged system tick compare register is referred
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to as ‘<samp><span class="samp">%hstick_cmpr</span></samp>’.
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</ul>
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</body></html>
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