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90 lines
7.3 KiB
C
90 lines
7.3 KiB
C
4 years ago
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/**
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* \brief Component description for RSTC
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*
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* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
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*
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* Subject to your compliance with these terms, you may use Microchip software and any derivatives
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* exclusively with Microchip products. It is your responsibility to comply with third party license
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* terms applicable to your use of third party software (including open source software) that may
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* accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
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* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
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* FITNESS FOR A PARTICULAR PURPOSE.
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*
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* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
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* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
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* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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*/
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/* file generated from device description version 2020-09-28T13:45:00Z */
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#ifndef _SAMD51_RSTC_COMPONENT_H_
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#define _SAMD51_RSTC_COMPONENT_H_
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/* ************************************************************************** */
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/* SOFTWARE API DEFINITION FOR RSTC */
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/* ************************************************************************** */
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/* -------- RSTC_RCAUSE : (RSTC Offset: 0x00) ( R/ 8) Reset Cause -------- */
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#define RSTC_RCAUSE_POR_Pos _U_(0) /**< (RSTC_RCAUSE) Power On Reset Position */
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#define RSTC_RCAUSE_POR_Msk (_U_(0x1) << RSTC_RCAUSE_POR_Pos) /**< (RSTC_RCAUSE) Power On Reset Mask */
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#define RSTC_RCAUSE_POR(value) (RSTC_RCAUSE_POR_Msk & ((value) << RSTC_RCAUSE_POR_Pos))
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#define RSTC_RCAUSE_BODCORE_Pos _U_(1) /**< (RSTC_RCAUSE) Brown Out CORE Detector Reset Position */
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#define RSTC_RCAUSE_BODCORE_Msk (_U_(0x1) << RSTC_RCAUSE_BODCORE_Pos) /**< (RSTC_RCAUSE) Brown Out CORE Detector Reset Mask */
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#define RSTC_RCAUSE_BODCORE(value) (RSTC_RCAUSE_BODCORE_Msk & ((value) << RSTC_RCAUSE_BODCORE_Pos))
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#define RSTC_RCAUSE_BODVDD_Pos _U_(2) /**< (RSTC_RCAUSE) Brown Out VDD Detector Reset Position */
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#define RSTC_RCAUSE_BODVDD_Msk (_U_(0x1) << RSTC_RCAUSE_BODVDD_Pos) /**< (RSTC_RCAUSE) Brown Out VDD Detector Reset Mask */
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#define RSTC_RCAUSE_BODVDD(value) (RSTC_RCAUSE_BODVDD_Msk & ((value) << RSTC_RCAUSE_BODVDD_Pos))
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#define RSTC_RCAUSE_NVM_Pos _U_(3) /**< (RSTC_RCAUSE) NVM Reset Position */
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#define RSTC_RCAUSE_NVM_Msk (_U_(0x1) << RSTC_RCAUSE_NVM_Pos) /**< (RSTC_RCAUSE) NVM Reset Mask */
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#define RSTC_RCAUSE_NVM(value) (RSTC_RCAUSE_NVM_Msk & ((value) << RSTC_RCAUSE_NVM_Pos))
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#define RSTC_RCAUSE_EXT_Pos _U_(4) /**< (RSTC_RCAUSE) External Reset Position */
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#define RSTC_RCAUSE_EXT_Msk (_U_(0x1) << RSTC_RCAUSE_EXT_Pos) /**< (RSTC_RCAUSE) External Reset Mask */
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#define RSTC_RCAUSE_EXT(value) (RSTC_RCAUSE_EXT_Msk & ((value) << RSTC_RCAUSE_EXT_Pos))
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#define RSTC_RCAUSE_WDT_Pos _U_(5) /**< (RSTC_RCAUSE) Watchdog Reset Position */
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#define RSTC_RCAUSE_WDT_Msk (_U_(0x1) << RSTC_RCAUSE_WDT_Pos) /**< (RSTC_RCAUSE) Watchdog Reset Mask */
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#define RSTC_RCAUSE_WDT(value) (RSTC_RCAUSE_WDT_Msk & ((value) << RSTC_RCAUSE_WDT_Pos))
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#define RSTC_RCAUSE_SYST_Pos _U_(6) /**< (RSTC_RCAUSE) System Reset Request Position */
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#define RSTC_RCAUSE_SYST_Msk (_U_(0x1) << RSTC_RCAUSE_SYST_Pos) /**< (RSTC_RCAUSE) System Reset Request Mask */
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#define RSTC_RCAUSE_SYST(value) (RSTC_RCAUSE_SYST_Msk & ((value) << RSTC_RCAUSE_SYST_Pos))
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#define RSTC_RCAUSE_BACKUP_Pos _U_(7) /**< (RSTC_RCAUSE) Backup Reset Position */
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#define RSTC_RCAUSE_BACKUP_Msk (_U_(0x1) << RSTC_RCAUSE_BACKUP_Pos) /**< (RSTC_RCAUSE) Backup Reset Mask */
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#define RSTC_RCAUSE_BACKUP(value) (RSTC_RCAUSE_BACKUP_Msk & ((value) << RSTC_RCAUSE_BACKUP_Pos))
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#define RSTC_RCAUSE_Msk _U_(0xFF) /**< (RSTC_RCAUSE) Register Mask */
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/* -------- RSTC_BKUPEXIT : (RSTC Offset: 0x02) ( R/ 8) Backup Exit Source -------- */
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#define RSTC_BKUPEXIT_RESETVALUE _U_(0x00) /**< (RSTC_BKUPEXIT) Backup Exit Source Reset Value */
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#define RSTC_BKUPEXIT_RTC_Pos _U_(1) /**< (RSTC_BKUPEXIT) Real Timer Counter Interrupt Position */
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#define RSTC_BKUPEXIT_RTC_Msk (_U_(0x1) << RSTC_BKUPEXIT_RTC_Pos) /**< (RSTC_BKUPEXIT) Real Timer Counter Interrupt Mask */
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#define RSTC_BKUPEXIT_RTC(value) (RSTC_BKUPEXIT_RTC_Msk & ((value) << RSTC_BKUPEXIT_RTC_Pos))
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#define RSTC_BKUPEXIT_BBPS_Pos _U_(2) /**< (RSTC_BKUPEXIT) Battery Backup Power Switch Position */
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#define RSTC_BKUPEXIT_BBPS_Msk (_U_(0x1) << RSTC_BKUPEXIT_BBPS_Pos) /**< (RSTC_BKUPEXIT) Battery Backup Power Switch Mask */
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#define RSTC_BKUPEXIT_BBPS(value) (RSTC_BKUPEXIT_BBPS_Msk & ((value) << RSTC_BKUPEXIT_BBPS_Pos))
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#define RSTC_BKUPEXIT_HIB_Pos _U_(7) /**< (RSTC_BKUPEXIT) Hibernate Position */
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#define RSTC_BKUPEXIT_HIB_Msk (_U_(0x1) << RSTC_BKUPEXIT_HIB_Pos) /**< (RSTC_BKUPEXIT) Hibernate Mask */
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#define RSTC_BKUPEXIT_HIB(value) (RSTC_BKUPEXIT_HIB_Msk & ((value) << RSTC_BKUPEXIT_HIB_Pos))
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#define RSTC_BKUPEXIT_Msk _U_(0x86) /**< (RSTC_BKUPEXIT) Register Mask */
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/** \brief RSTC register offsets definitions */
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#define RSTC_RCAUSE_REG_OFST (0x00) /**< (RSTC_RCAUSE) Reset Cause Offset */
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#define RSTC_BKUPEXIT_REG_OFST (0x02) /**< (RSTC_BKUPEXIT) Backup Exit Source Offset */
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#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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/** \brief RSTC register API structure */
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typedef struct
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{ /* Reset Controller */
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__I uint8_t RSTC_RCAUSE; /**< Offset: 0x00 (R/ 8) Reset Cause */
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__I uint8_t Reserved1[0x01];
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__I uint8_t RSTC_BKUPEXIT; /**< Offset: 0x02 (R/ 8) Backup Exit Source */
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} rstc_registers_t;
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#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAMD51_RSTC_COMPONENT_H_ */
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