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8773 lines
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8773 lines
1.4 MiB
HTML
4 years ago
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<title>SAME54P20A Test Project: /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/pio/same54n20a.h File Reference</title>
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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_0e02049879cfa95c4b33945e3bf1e6f2.html">pio</a></li> </ul>
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<a href="#define-members">Macros</a> </div>
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<div class="title">same54n20a.h File Reference</div> </div>
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<div class="contents">
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<p>Peripheral I/O description for SAME54N20A.
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<a href="#details">More...</a></p>
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<p><a href="pio_2same54n20a_8h_source.html">Go to the source code of this file.</a></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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Macros</h2></td></tr>
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<tr class="memitem:abb9f31e152cd30e3bc8bbec8f07dc267"><td class="memItemLeft" align="right" valign="top"><a id="abb9f31e152cd30e3bc8bbec8f07dc267"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#abb9f31e152cd30e3bc8bbec8f07dc267">PIN_PA00</a>   0</td></tr>
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<tr class="memdesc:abb9f31e152cd30e3bc8bbec8f07dc267"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PA00. <br /></td></tr>
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<tr class="separator:abb9f31e152cd30e3bc8bbec8f07dc267"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af2409650ce529705cf78bceb5d72d90a"><td class="memItemLeft" align="right" valign="top"><a id="af2409650ce529705cf78bceb5d72d90a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af2409650ce529705cf78bceb5d72d90a">PORT_PA00</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 0)</td></tr>
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<tr class="memdesc:af2409650ce529705cf78bceb5d72d90a"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PA00. <br /></td></tr>
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<tr class="separator:af2409650ce529705cf78bceb5d72d90a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad0b4b0dcc92986a8c5526c4490ed7f32"><td class="memItemLeft" align="right" valign="top"><a id="ad0b4b0dcc92986a8c5526c4490ed7f32"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad0b4b0dcc92986a8c5526c4490ed7f32">PIN_PA01</a>   1</td></tr>
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<tr class="memdesc:ad0b4b0dcc92986a8c5526c4490ed7f32"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PA01. <br /></td></tr>
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<tr class="separator:ad0b4b0dcc92986a8c5526c4490ed7f32"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae876f4972599c364263f58ceb138fb36"><td class="memItemLeft" align="right" valign="top"><a id="ae876f4972599c364263f58ceb138fb36"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae876f4972599c364263f58ceb138fb36">PORT_PA01</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 1)</td></tr>
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<tr class="memdesc:ae876f4972599c364263f58ceb138fb36"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PA01. <br /></td></tr>
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<tr class="separator:ae876f4972599c364263f58ceb138fb36"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ada4a90557e056a63a5c13b11343471ab"><td class="memItemLeft" align="right" valign="top"><a id="ada4a90557e056a63a5c13b11343471ab"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ada4a90557e056a63a5c13b11343471ab">PIN_PA02</a>   2</td></tr>
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<tr class="memdesc:ada4a90557e056a63a5c13b11343471ab"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PA02. <br /></td></tr>
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<tr class="separator:ada4a90557e056a63a5c13b11343471ab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aee75baf72f1a956d7481fe7214626d9a"><td class="memItemLeft" align="right" valign="top"><a id="aee75baf72f1a956d7481fe7214626d9a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aee75baf72f1a956d7481fe7214626d9a">PORT_PA02</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 2)</td></tr>
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<tr class="memdesc:aee75baf72f1a956d7481fe7214626d9a"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PA02. <br /></td></tr>
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<tr class="separator:aee75baf72f1a956d7481fe7214626d9a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a32b9f520e39b943f78a864645721a9d6"><td class="memItemLeft" align="right" valign="top"><a id="a32b9f520e39b943f78a864645721a9d6"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a32b9f520e39b943f78a864645721a9d6">PIN_PA03</a>   3</td></tr>
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<tr class="memdesc:a32b9f520e39b943f78a864645721a9d6"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PA03. <br /></td></tr>
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<tr class="separator:a32b9f520e39b943f78a864645721a9d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac29ed2e1051f06c5261133efcab551ea"><td class="memItemLeft" align="right" valign="top"><a id="ac29ed2e1051f06c5261133efcab551ea"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac29ed2e1051f06c5261133efcab551ea">PORT_PA03</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 3)</td></tr>
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<tr class="memdesc:ac29ed2e1051f06c5261133efcab551ea"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PA03. <br /></td></tr>
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<tr class="separator:ac29ed2e1051f06c5261133efcab551ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aad65b053a42add45bba004f34776e0d6"><td class="memItemLeft" align="right" valign="top"><a id="aad65b053a42add45bba004f34776e0d6"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aad65b053a42add45bba004f34776e0d6">PIN_PA04</a>   4</td></tr>
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<tr class="memdesc:aad65b053a42add45bba004f34776e0d6"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PA04. <br /></td></tr>
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<tr class="separator:aad65b053a42add45bba004f34776e0d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac034e8474ff5a9102cb1f3353a6a998e"><td class="memItemLeft" align="right" valign="top"><a id="ac034e8474ff5a9102cb1f3353a6a998e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac034e8474ff5a9102cb1f3353a6a998e">PORT_PA04</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 4)</td></tr>
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||
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<tr class="memdesc:ac034e8474ff5a9102cb1f3353a6a998e"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PA04. <br /></td></tr>
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<tr class="separator:ac034e8474ff5a9102cb1f3353a6a998e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9527e3de1cb13d3530c6519ef35866be"><td class="memItemLeft" align="right" valign="top"><a id="a9527e3de1cb13d3530c6519ef35866be"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a9527e3de1cb13d3530c6519ef35866be">PIN_PA05</a>   5</td></tr>
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||
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<tr class="memdesc:a9527e3de1cb13d3530c6519ef35866be"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PA05. <br /></td></tr>
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<tr class="separator:a9527e3de1cb13d3530c6519ef35866be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab796eb8a827e6f8a4e30e3fab0490f01"><td class="memItemLeft" align="right" valign="top"><a id="ab796eb8a827e6f8a4e30e3fab0490f01"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab796eb8a827e6f8a4e30e3fab0490f01">PORT_PA05</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 5)</td></tr>
|
||
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<tr class="memdesc:ab796eb8a827e6f8a4e30e3fab0490f01"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PA05. <br /></td></tr>
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||
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<tr class="separator:ab796eb8a827e6f8a4e30e3fab0490f01"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:aaebb84fd9405e339ed98b122aabcd65f"><td class="memItemLeft" align="right" valign="top"><a id="aaebb84fd9405e339ed98b122aabcd65f"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aaebb84fd9405e339ed98b122aabcd65f">PIN_PA06</a>   6</td></tr>
|
||
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<tr class="memdesc:aaebb84fd9405e339ed98b122aabcd65f"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PA06. <br /></td></tr>
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||
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<tr class="separator:aaebb84fd9405e339ed98b122aabcd65f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa800e01368070dd5fbadabb6c14ac822"><td class="memItemLeft" align="right" valign="top"><a id="aa800e01368070dd5fbadabb6c14ac822"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa800e01368070dd5fbadabb6c14ac822">PORT_PA06</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 6)</td></tr>
|
||
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<tr class="memdesc:aa800e01368070dd5fbadabb6c14ac822"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PA06. <br /></td></tr>
|
||
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<tr class="separator:aa800e01368070dd5fbadabb6c14ac822"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a0c4f2e2dc54ee3ccb3ed39933cf29386"><td class="memItemLeft" align="right" valign="top"><a id="a0c4f2e2dc54ee3ccb3ed39933cf29386"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0c4f2e2dc54ee3ccb3ed39933cf29386">PIN_PA07</a>   7</td></tr>
|
||
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<tr class="memdesc:a0c4f2e2dc54ee3ccb3ed39933cf29386"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PA07. <br /></td></tr>
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<tr class="separator:a0c4f2e2dc54ee3ccb3ed39933cf29386"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:af660550bc2db4cd7211f8e2b46066748"><td class="memItemLeft" align="right" valign="top"><a id="af660550bc2db4cd7211f8e2b46066748"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af660550bc2db4cd7211f8e2b46066748">PORT_PA07</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 7)</td></tr>
|
||
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<tr class="memdesc:af660550bc2db4cd7211f8e2b46066748"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PA07. <br /></td></tr>
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<tr class="separator:af660550bc2db4cd7211f8e2b46066748"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7dc08bf81d9967156de18aae2cb5fe46"><td class="memItemLeft" align="right" valign="top"><a id="a7dc08bf81d9967156de18aae2cb5fe46"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7dc08bf81d9967156de18aae2cb5fe46">PIN_PA08</a>   8</td></tr>
|
||
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<tr class="memdesc:a7dc08bf81d9967156de18aae2cb5fe46"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PA08. <br /></td></tr>
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<tr class="separator:a7dc08bf81d9967156de18aae2cb5fe46"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af410e24130dfd6e46e4faffa84da401b"><td class="memItemLeft" align="right" valign="top"><a id="af410e24130dfd6e46e4faffa84da401b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af410e24130dfd6e46e4faffa84da401b">PORT_PA08</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 8)</td></tr>
|
||
|
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<tr class="memdesc:af410e24130dfd6e46e4faffa84da401b"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PA08. <br /></td></tr>
|
||
|
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<tr class="separator:af410e24130dfd6e46e4faffa84da401b"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:ac14663d14647a4a629d8dc37616bf7e4"><td class="memItemLeft" align="right" valign="top"><a id="ac14663d14647a4a629d8dc37616bf7e4"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac14663d14647a4a629d8dc37616bf7e4">PIN_PA09</a>   9</td></tr>
|
||
|
|
<tr class="memdesc:ac14663d14647a4a629d8dc37616bf7e4"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PA09. <br /></td></tr>
|
||
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<tr class="separator:ac14663d14647a4a629d8dc37616bf7e4"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a97d148669034739988aaf6c85b4ee217"><td class="memItemLeft" align="right" valign="top"><a id="a97d148669034739988aaf6c85b4ee217"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a97d148669034739988aaf6c85b4ee217">PORT_PA09</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 9)</td></tr>
|
||
|
|
<tr class="memdesc:a97d148669034739988aaf6c85b4ee217"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PA09. <br /></td></tr>
|
||
|
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<tr class="separator:a97d148669034739988aaf6c85b4ee217"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a8bdc2380ba42c8288b661ced1f678933"><td class="memItemLeft" align="right" valign="top"><a id="a8bdc2380ba42c8288b661ced1f678933"></a>
|
||
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|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8bdc2380ba42c8288b661ced1f678933">PIN_PA10</a>   10</td></tr>
|
||
|
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<tr class="memdesc:a8bdc2380ba42c8288b661ced1f678933"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PA10. <br /></td></tr>
|
||
|
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<tr class="separator:a8bdc2380ba42c8288b661ced1f678933"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a4002c2a633fb13e1183f1782660a8ded"><td class="memItemLeft" align="right" valign="top"><a id="a4002c2a633fb13e1183f1782660a8ded"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4002c2a633fb13e1183f1782660a8ded">PORT_PA10</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 10)</td></tr>
|
||
|
|
<tr class="memdesc:a4002c2a633fb13e1183f1782660a8ded"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PA10. <br /></td></tr>
|
||
|
|
<tr class="separator:a4002c2a633fb13e1183f1782660a8ded"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a01f1322d5a1df159a79f1a9cdf4201d2"><td class="memItemLeft" align="right" valign="top"><a id="a01f1322d5a1df159a79f1a9cdf4201d2"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a01f1322d5a1df159a79f1a9cdf4201d2">PIN_PA11</a>   11</td></tr>
|
||
|
|
<tr class="memdesc:a01f1322d5a1df159a79f1a9cdf4201d2"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PA11. <br /></td></tr>
|
||
|
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<tr class="separator:a01f1322d5a1df159a79f1a9cdf4201d2"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a0d86f5c542131de55bff6d9ba96ae4fb"><td class="memItemLeft" align="right" valign="top"><a id="a0d86f5c542131de55bff6d9ba96ae4fb"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0d86f5c542131de55bff6d9ba96ae4fb">PORT_PA11</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 11)</td></tr>
|
||
|
|
<tr class="memdesc:a0d86f5c542131de55bff6d9ba96ae4fb"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PA11. <br /></td></tr>
|
||
|
|
<tr class="separator:a0d86f5c542131de55bff6d9ba96ae4fb"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a2ffb0dfd383bdc2f6e8f41a9ef0d4955"><td class="memItemLeft" align="right" valign="top"><a id="a2ffb0dfd383bdc2f6e8f41a9ef0d4955"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2ffb0dfd383bdc2f6e8f41a9ef0d4955">PIN_PA12</a>   12</td></tr>
|
||
|
|
<tr class="memdesc:a2ffb0dfd383bdc2f6e8f41a9ef0d4955"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PA12. <br /></td></tr>
|
||
|
|
<tr class="separator:a2ffb0dfd383bdc2f6e8f41a9ef0d4955"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a484876b223a5e7f3f58eb14a32e69295"><td class="memItemLeft" align="right" valign="top"><a id="a484876b223a5e7f3f58eb14a32e69295"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a484876b223a5e7f3f58eb14a32e69295">PORT_PA12</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 12)</td></tr>
|
||
|
|
<tr class="memdesc:a484876b223a5e7f3f58eb14a32e69295"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PA12. <br /></td></tr>
|
||
|
|
<tr class="separator:a484876b223a5e7f3f58eb14a32e69295"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a4180bdc6fd7252cff2ffe28176866028"><td class="memItemLeft" align="right" valign="top"><a id="a4180bdc6fd7252cff2ffe28176866028"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4180bdc6fd7252cff2ffe28176866028">PIN_PA13</a>   13</td></tr>
|
||
|
|
<tr class="memdesc:a4180bdc6fd7252cff2ffe28176866028"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PA13. <br /></td></tr>
|
||
|
|
<tr class="separator:a4180bdc6fd7252cff2ffe28176866028"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:aec93b60ace96611ab9e9a926eafc7e2e"><td class="memItemLeft" align="right" valign="top"><a id="aec93b60ace96611ab9e9a926eafc7e2e"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aec93b60ace96611ab9e9a926eafc7e2e">PORT_PA13</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 13)</td></tr>
|
||
|
|
<tr class="memdesc:aec93b60ace96611ab9e9a926eafc7e2e"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PA13. <br /></td></tr>
|
||
|
|
<tr class="separator:aec93b60ace96611ab9e9a926eafc7e2e"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:ad71083de279943a97f0a159c824c290b"><td class="memItemLeft" align="right" valign="top"><a id="ad71083de279943a97f0a159c824c290b"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad71083de279943a97f0a159c824c290b">PIN_PA14</a>   14</td></tr>
|
||
|
|
<tr class="memdesc:ad71083de279943a97f0a159c824c290b"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PA14. <br /></td></tr>
|
||
|
|
<tr class="separator:ad71083de279943a97f0a159c824c290b"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a93290c47fdda2baa183e0540d79dda0c"><td class="memItemLeft" align="right" valign="top"><a id="a93290c47fdda2baa183e0540d79dda0c"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a93290c47fdda2baa183e0540d79dda0c">PORT_PA14</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 14)</td></tr>
|
||
|
|
<tr class="memdesc:a93290c47fdda2baa183e0540d79dda0c"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PA14. <br /></td></tr>
|
||
|
|
<tr class="separator:a93290c47fdda2baa183e0540d79dda0c"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:abaad308f0408bf5d3f1fe558f3d26e5e"><td class="memItemLeft" align="right" valign="top"><a id="abaad308f0408bf5d3f1fe558f3d26e5e"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#abaad308f0408bf5d3f1fe558f3d26e5e">PIN_PA15</a>   15</td></tr>
|
||
|
|
<tr class="memdesc:abaad308f0408bf5d3f1fe558f3d26e5e"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PA15. <br /></td></tr>
|
||
|
|
<tr class="separator:abaad308f0408bf5d3f1fe558f3d26e5e"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:ad3db381b789793febb5224d4d6d98584"><td class="memItemLeft" align="right" valign="top"><a id="ad3db381b789793febb5224d4d6d98584"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad3db381b789793febb5224d4d6d98584">PORT_PA15</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 15)</td></tr>
|
||
|
|
<tr class="memdesc:ad3db381b789793febb5224d4d6d98584"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PA15. <br /></td></tr>
|
||
|
|
<tr class="separator:ad3db381b789793febb5224d4d6d98584"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:af95063d900dacae04c7700184f817d88"><td class="memItemLeft" align="right" valign="top"><a id="af95063d900dacae04c7700184f817d88"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af95063d900dacae04c7700184f817d88">PIN_PA16</a>   16</td></tr>
|
||
|
|
<tr class="memdesc:af95063d900dacae04c7700184f817d88"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PA16. <br /></td></tr>
|
||
|
|
<tr class="separator:af95063d900dacae04c7700184f817d88"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:ab60c2f0e015476f7dd36d8a522deab85"><td class="memItemLeft" align="right" valign="top"><a id="ab60c2f0e015476f7dd36d8a522deab85"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab60c2f0e015476f7dd36d8a522deab85">PORT_PA16</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 16)</td></tr>
|
||
|
|
<tr class="memdesc:ab60c2f0e015476f7dd36d8a522deab85"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PA16. <br /></td></tr>
|
||
|
|
<tr class="separator:ab60c2f0e015476f7dd36d8a522deab85"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a66f8d032baf3fb0bc60f2dc70ef0e587"><td class="memItemLeft" align="right" valign="top"><a id="a66f8d032baf3fb0bc60f2dc70ef0e587"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a66f8d032baf3fb0bc60f2dc70ef0e587">PIN_PA17</a>   17</td></tr>
|
||
|
|
<tr class="memdesc:a66f8d032baf3fb0bc60f2dc70ef0e587"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PA17. <br /></td></tr>
|
||
|
|
<tr class="separator:a66f8d032baf3fb0bc60f2dc70ef0e587"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a54d352801be55a1f99b1bd17e7183702"><td class="memItemLeft" align="right" valign="top"><a id="a54d352801be55a1f99b1bd17e7183702"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a54d352801be55a1f99b1bd17e7183702">PORT_PA17</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 17)</td></tr>
|
||
|
|
<tr class="memdesc:a54d352801be55a1f99b1bd17e7183702"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PA17. <br /></td></tr>
|
||
|
|
<tr class="separator:a54d352801be55a1f99b1bd17e7183702"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a9695bdcd8129ad83a871ad6b259dfcd5"><td class="memItemLeft" align="right" valign="top"><a id="a9695bdcd8129ad83a871ad6b259dfcd5"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a9695bdcd8129ad83a871ad6b259dfcd5">PIN_PA18</a>   18</td></tr>
|
||
|
|
<tr class="memdesc:a9695bdcd8129ad83a871ad6b259dfcd5"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PA18. <br /></td></tr>
|
||
|
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<tr class="separator:a9695bdcd8129ad83a871ad6b259dfcd5"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:adfd9c418c179cff56c445c46e6b15a25"><td class="memItemLeft" align="right" valign="top"><a id="adfd9c418c179cff56c445c46e6b15a25"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#adfd9c418c179cff56c445c46e6b15a25">PORT_PA18</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 18)</td></tr>
|
||
|
|
<tr class="memdesc:adfd9c418c179cff56c445c46e6b15a25"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PA18. <br /></td></tr>
|
||
|
|
<tr class="separator:adfd9c418c179cff56c445c46e6b15a25"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a58254064b915fd09ca35601ceebcf27f"><td class="memItemLeft" align="right" valign="top"><a id="a58254064b915fd09ca35601ceebcf27f"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a58254064b915fd09ca35601ceebcf27f">PIN_PA19</a>   19</td></tr>
|
||
|
|
<tr class="memdesc:a58254064b915fd09ca35601ceebcf27f"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PA19. <br /></td></tr>
|
||
|
|
<tr class="separator:a58254064b915fd09ca35601ceebcf27f"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:aa6c67ad40f0ffeef27f4a4fc7b1bb9f7"><td class="memItemLeft" align="right" valign="top"><a id="aa6c67ad40f0ffeef27f4a4fc7b1bb9f7"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa6c67ad40f0ffeef27f4a4fc7b1bb9f7">PORT_PA19</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 19)</td></tr>
|
||
|
|
<tr class="memdesc:aa6c67ad40f0ffeef27f4a4fc7b1bb9f7"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PA19. <br /></td></tr>
|
||
|
|
<tr class="separator:aa6c67ad40f0ffeef27f4a4fc7b1bb9f7"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a00c77a5c19a99cee2402fc83b04c02d5"><td class="memItemLeft" align="right" valign="top"><a id="a00c77a5c19a99cee2402fc83b04c02d5"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a00c77a5c19a99cee2402fc83b04c02d5">PIN_PA20</a>   20</td></tr>
|
||
|
|
<tr class="memdesc:a00c77a5c19a99cee2402fc83b04c02d5"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PA20. <br /></td></tr>
|
||
|
|
<tr class="separator:a00c77a5c19a99cee2402fc83b04c02d5"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:aba99808fe0ae7db4067a8ffdd4eba36b"><td class="memItemLeft" align="right" valign="top"><a id="aba99808fe0ae7db4067a8ffdd4eba36b"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aba99808fe0ae7db4067a8ffdd4eba36b">PORT_PA20</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 20)</td></tr>
|
||
|
|
<tr class="memdesc:aba99808fe0ae7db4067a8ffdd4eba36b"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PA20. <br /></td></tr>
|
||
|
|
<tr class="separator:aba99808fe0ae7db4067a8ffdd4eba36b"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:af985624239bfbec119533432376256b8"><td class="memItemLeft" align="right" valign="top"><a id="af985624239bfbec119533432376256b8"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af985624239bfbec119533432376256b8">PIN_PA21</a>   21</td></tr>
|
||
|
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<tr class="memdesc:af985624239bfbec119533432376256b8"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PA21. <br /></td></tr>
|
||
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<tr class="separator:af985624239bfbec119533432376256b8"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:a99affd47a6238969d3f2775cd75818a9"><td class="memItemLeft" align="right" valign="top"><a id="a99affd47a6238969d3f2775cd75818a9"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a99affd47a6238969d3f2775cd75818a9">PORT_PA21</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 21)</td></tr>
|
||
|
|
<tr class="memdesc:a99affd47a6238969d3f2775cd75818a9"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PA21. <br /></td></tr>
|
||
|
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<tr class="separator:a99affd47a6238969d3f2775cd75818a9"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:ac9cc1f345184e86b5481800a38f67b73"><td class="memItemLeft" align="right" valign="top"><a id="ac9cc1f345184e86b5481800a38f67b73"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac9cc1f345184e86b5481800a38f67b73">PIN_PA22</a>   22</td></tr>
|
||
|
|
<tr class="memdesc:ac9cc1f345184e86b5481800a38f67b73"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PA22. <br /></td></tr>
|
||
|
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<tr class="separator:ac9cc1f345184e86b5481800a38f67b73"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a91346dac1f98836d316f1a38aea7cbd6"><td class="memItemLeft" align="right" valign="top"><a id="a91346dac1f98836d316f1a38aea7cbd6"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a91346dac1f98836d316f1a38aea7cbd6">PORT_PA22</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 22)</td></tr>
|
||
|
|
<tr class="memdesc:a91346dac1f98836d316f1a38aea7cbd6"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PA22. <br /></td></tr>
|
||
|
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<tr class="separator:a91346dac1f98836d316f1a38aea7cbd6"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a6ca014c55f45ce023918c585433c67af"><td class="memItemLeft" align="right" valign="top"><a id="a6ca014c55f45ce023918c585433c67af"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6ca014c55f45ce023918c585433c67af">PIN_PA23</a>   23</td></tr>
|
||
|
|
<tr class="memdesc:a6ca014c55f45ce023918c585433c67af"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PA23. <br /></td></tr>
|
||
|
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<tr class="separator:a6ca014c55f45ce023918c585433c67af"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a3de7ac24ce6b0e80e842e55d41250842"><td class="memItemLeft" align="right" valign="top"><a id="a3de7ac24ce6b0e80e842e55d41250842"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3de7ac24ce6b0e80e842e55d41250842">PORT_PA23</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 23)</td></tr>
|
||
|
|
<tr class="memdesc:a3de7ac24ce6b0e80e842e55d41250842"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PA23. <br /></td></tr>
|
||
|
|
<tr class="separator:a3de7ac24ce6b0e80e842e55d41250842"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:abee6df88d9fba25b98a4421947f6b358"><td class="memItemLeft" align="right" valign="top"><a id="abee6df88d9fba25b98a4421947f6b358"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#abee6df88d9fba25b98a4421947f6b358">PIN_PA24</a>   24</td></tr>
|
||
|
|
<tr class="memdesc:abee6df88d9fba25b98a4421947f6b358"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PA24. <br /></td></tr>
|
||
|
|
<tr class="separator:abee6df88d9fba25b98a4421947f6b358"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a6d0bd987a61b4fc97aa25d05fe08ceb6"><td class="memItemLeft" align="right" valign="top"><a id="a6d0bd987a61b4fc97aa25d05fe08ceb6"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6d0bd987a61b4fc97aa25d05fe08ceb6">PORT_PA24</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 24)</td></tr>
|
||
|
|
<tr class="memdesc:a6d0bd987a61b4fc97aa25d05fe08ceb6"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PA24. <br /></td></tr>
|
||
|
|
<tr class="separator:a6d0bd987a61b4fc97aa25d05fe08ceb6"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:abf0af39e3f1759f7806d7d4678c1652b"><td class="memItemLeft" align="right" valign="top"><a id="abf0af39e3f1759f7806d7d4678c1652b"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#abf0af39e3f1759f7806d7d4678c1652b">PIN_PA25</a>   25</td></tr>
|
||
|
|
<tr class="memdesc:abf0af39e3f1759f7806d7d4678c1652b"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PA25. <br /></td></tr>
|
||
|
|
<tr class="separator:abf0af39e3f1759f7806d7d4678c1652b"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a0b41284cc6b961106eb1bc1f2d885421"><td class="memItemLeft" align="right" valign="top"><a id="a0b41284cc6b961106eb1bc1f2d885421"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0b41284cc6b961106eb1bc1f2d885421">PORT_PA25</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 25)</td></tr>
|
||
|
|
<tr class="memdesc:a0b41284cc6b961106eb1bc1f2d885421"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PA25. <br /></td></tr>
|
||
|
|
<tr class="separator:a0b41284cc6b961106eb1bc1f2d885421"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a3794cc9242203d349103ba1249e5d587"><td class="memItemLeft" align="right" valign="top"><a id="a3794cc9242203d349103ba1249e5d587"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3794cc9242203d349103ba1249e5d587">PIN_PA27</a>   27</td></tr>
|
||
|
|
<tr class="memdesc:a3794cc9242203d349103ba1249e5d587"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PA27. <br /></td></tr>
|
||
|
|
<tr class="separator:a3794cc9242203d349103ba1249e5d587"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a2fc26d65fb6c211495737354784f321c"><td class="memItemLeft" align="right" valign="top"><a id="a2fc26d65fb6c211495737354784f321c"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2fc26d65fb6c211495737354784f321c">PORT_PA27</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 27)</td></tr>
|
||
|
|
<tr class="memdesc:a2fc26d65fb6c211495737354784f321c"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PA27. <br /></td></tr>
|
||
|
|
<tr class="separator:a2fc26d65fb6c211495737354784f321c"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:aabc7384a581a9f8558c32585582f1be1"><td class="memItemLeft" align="right" valign="top"><a id="aabc7384a581a9f8558c32585582f1be1"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aabc7384a581a9f8558c32585582f1be1">PIN_PA30</a>   30</td></tr>
|
||
|
|
<tr class="memdesc:aabc7384a581a9f8558c32585582f1be1"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PA30. <br /></td></tr>
|
||
|
|
<tr class="separator:aabc7384a581a9f8558c32585582f1be1"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a8b04708887ae99c0822c2ef30c210cde"><td class="memItemLeft" align="right" valign="top"><a id="a8b04708887ae99c0822c2ef30c210cde"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8b04708887ae99c0822c2ef30c210cde">PORT_PA30</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 30)</td></tr>
|
||
|
|
<tr class="memdesc:a8b04708887ae99c0822c2ef30c210cde"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PA30. <br /></td></tr>
|
||
|
|
<tr class="separator:a8b04708887ae99c0822c2ef30c210cde"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a151d10c7fdacaac78b00e59dee16cd6f"><td class="memItemLeft" align="right" valign="top"><a id="a151d10c7fdacaac78b00e59dee16cd6f"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a151d10c7fdacaac78b00e59dee16cd6f">PIN_PA31</a>   31</td></tr>
|
||
|
|
<tr class="memdesc:a151d10c7fdacaac78b00e59dee16cd6f"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PA31. <br /></td></tr>
|
||
|
|
<tr class="separator:a151d10c7fdacaac78b00e59dee16cd6f"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a667ef2f989f05c60028945244e000274"><td class="memItemLeft" align="right" valign="top"><a id="a667ef2f989f05c60028945244e000274"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a667ef2f989f05c60028945244e000274">PORT_PA31</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 31)</td></tr>
|
||
|
|
<tr class="memdesc:a667ef2f989f05c60028945244e000274"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PA31. <br /></td></tr>
|
||
|
|
<tr class="separator:a667ef2f989f05c60028945244e000274"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:aaee350eaf010d48a2c6efae0a1632f7c"><td class="memItemLeft" align="right" valign="top"><a id="aaee350eaf010d48a2c6efae0a1632f7c"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aaee350eaf010d48a2c6efae0a1632f7c">PIN_PB00</a>   32</td></tr>
|
||
|
|
<tr class="memdesc:aaee350eaf010d48a2c6efae0a1632f7c"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PB00. <br /></td></tr>
|
||
|
|
<tr class="separator:aaee350eaf010d48a2c6efae0a1632f7c"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a24a20b3fea76e7a8b04d12dec26cb027"><td class="memItemLeft" align="right" valign="top"><a id="a24a20b3fea76e7a8b04d12dec26cb027"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a24a20b3fea76e7a8b04d12dec26cb027">PORT_PB00</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 0)</td></tr>
|
||
|
|
<tr class="memdesc:a24a20b3fea76e7a8b04d12dec26cb027"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PB00. <br /></td></tr>
|
||
|
|
<tr class="separator:a24a20b3fea76e7a8b04d12dec26cb027"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:aa599b1c1a8440ecffbf5fba215984c75"><td class="memItemLeft" align="right" valign="top"><a id="aa599b1c1a8440ecffbf5fba215984c75"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa599b1c1a8440ecffbf5fba215984c75">PIN_PB01</a>   33</td></tr>
|
||
|
|
<tr class="memdesc:aa599b1c1a8440ecffbf5fba215984c75"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PB01. <br /></td></tr>
|
||
|
|
<tr class="separator:aa599b1c1a8440ecffbf5fba215984c75"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a3e6fdff2c294277f350d50fd2c68bab3"><td class="memItemLeft" align="right" valign="top"><a id="a3e6fdff2c294277f350d50fd2c68bab3"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3e6fdff2c294277f350d50fd2c68bab3">PORT_PB01</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 1)</td></tr>
|
||
|
|
<tr class="memdesc:a3e6fdff2c294277f350d50fd2c68bab3"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PB01. <br /></td></tr>
|
||
|
|
<tr class="separator:a3e6fdff2c294277f350d50fd2c68bab3"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a19ef30fcec1b8ad27ff954975a005850"><td class="memItemLeft" align="right" valign="top"><a id="a19ef30fcec1b8ad27ff954975a005850"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a19ef30fcec1b8ad27ff954975a005850">PIN_PB02</a>   34</td></tr>
|
||
|
|
<tr class="memdesc:a19ef30fcec1b8ad27ff954975a005850"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PB02. <br /></td></tr>
|
||
|
|
<tr class="separator:a19ef30fcec1b8ad27ff954975a005850"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:ab203d5081034b1a5ed00cc6dc17ae95d"><td class="memItemLeft" align="right" valign="top"><a id="ab203d5081034b1a5ed00cc6dc17ae95d"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab203d5081034b1a5ed00cc6dc17ae95d">PORT_PB02</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 2)</td></tr>
|
||
|
|
<tr class="memdesc:ab203d5081034b1a5ed00cc6dc17ae95d"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PB02. <br /></td></tr>
|
||
|
|
<tr class="separator:ab203d5081034b1a5ed00cc6dc17ae95d"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:ab8f19878aac1648cb688cfcf0eec3fb5"><td class="memItemLeft" align="right" valign="top"><a id="ab8f19878aac1648cb688cfcf0eec3fb5"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab8f19878aac1648cb688cfcf0eec3fb5">PIN_PB03</a>   35</td></tr>
|
||
|
|
<tr class="memdesc:ab8f19878aac1648cb688cfcf0eec3fb5"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PB03. <br /></td></tr>
|
||
|
|
<tr class="separator:ab8f19878aac1648cb688cfcf0eec3fb5"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a15fc59f02619ede74c6b608a5a16ef62"><td class="memItemLeft" align="right" valign="top"><a id="a15fc59f02619ede74c6b608a5a16ef62"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a15fc59f02619ede74c6b608a5a16ef62">PORT_PB03</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 3)</td></tr>
|
||
|
|
<tr class="memdesc:a15fc59f02619ede74c6b608a5a16ef62"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PB03. <br /></td></tr>
|
||
|
|
<tr class="separator:a15fc59f02619ede74c6b608a5a16ef62"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:ab4f72feca4eed2b50fb246dc2d59241d"><td class="memItemLeft" align="right" valign="top"><a id="ab4f72feca4eed2b50fb246dc2d59241d"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab4f72feca4eed2b50fb246dc2d59241d">PIN_PB04</a>   36</td></tr>
|
||
|
|
<tr class="memdesc:ab4f72feca4eed2b50fb246dc2d59241d"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PB04. <br /></td></tr>
|
||
|
|
<tr class="separator:ab4f72feca4eed2b50fb246dc2d59241d"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:ab5ff6aadaa17e6ce8d11529ddb86e913"><td class="memItemLeft" align="right" valign="top"><a id="ab5ff6aadaa17e6ce8d11529ddb86e913"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab5ff6aadaa17e6ce8d11529ddb86e913">PORT_PB04</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 4)</td></tr>
|
||
|
|
<tr class="memdesc:ab5ff6aadaa17e6ce8d11529ddb86e913"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PB04. <br /></td></tr>
|
||
|
|
<tr class="separator:ab5ff6aadaa17e6ce8d11529ddb86e913"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:ae62ed501d1f5f6cdc6bf605742aeb778"><td class="memItemLeft" align="right" valign="top"><a id="ae62ed501d1f5f6cdc6bf605742aeb778"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae62ed501d1f5f6cdc6bf605742aeb778">PIN_PB05</a>   37</td></tr>
|
||
|
|
<tr class="memdesc:ae62ed501d1f5f6cdc6bf605742aeb778"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PB05. <br /></td></tr>
|
||
|
|
<tr class="separator:ae62ed501d1f5f6cdc6bf605742aeb778"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a5829d2e80f94c709ce3c81cd96eba594"><td class="memItemLeft" align="right" valign="top"><a id="a5829d2e80f94c709ce3c81cd96eba594"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5829d2e80f94c709ce3c81cd96eba594">PORT_PB05</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 5)</td></tr>
|
||
|
|
<tr class="memdesc:a5829d2e80f94c709ce3c81cd96eba594"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PB05. <br /></td></tr>
|
||
|
|
<tr class="separator:a5829d2e80f94c709ce3c81cd96eba594"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a342eea40b1bafb1afe71ff68854d9747"><td class="memItemLeft" align="right" valign="top"><a id="a342eea40b1bafb1afe71ff68854d9747"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a342eea40b1bafb1afe71ff68854d9747">PIN_PB06</a>   38</td></tr>
|
||
|
|
<tr class="memdesc:a342eea40b1bafb1afe71ff68854d9747"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PB06. <br /></td></tr>
|
||
|
|
<tr class="separator:a342eea40b1bafb1afe71ff68854d9747"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:aaec9efecd9a29f2cfc1f4099c79efcd7"><td class="memItemLeft" align="right" valign="top"><a id="aaec9efecd9a29f2cfc1f4099c79efcd7"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aaec9efecd9a29f2cfc1f4099c79efcd7">PORT_PB06</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 6)</td></tr>
|
||
|
|
<tr class="memdesc:aaec9efecd9a29f2cfc1f4099c79efcd7"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PB06. <br /></td></tr>
|
||
|
|
<tr class="separator:aaec9efecd9a29f2cfc1f4099c79efcd7"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a381a8ad61ecb02a4d455cd92a5a5fb1e"><td class="memItemLeft" align="right" valign="top"><a id="a381a8ad61ecb02a4d455cd92a5a5fb1e"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a381a8ad61ecb02a4d455cd92a5a5fb1e">PIN_PB07</a>   39</td></tr>
|
||
|
|
<tr class="memdesc:a381a8ad61ecb02a4d455cd92a5a5fb1e"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PB07. <br /></td></tr>
|
||
|
|
<tr class="separator:a381a8ad61ecb02a4d455cd92a5a5fb1e"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a90db5e987c3e8d9bf6d07aca7ed3ca93"><td class="memItemLeft" align="right" valign="top"><a id="a90db5e987c3e8d9bf6d07aca7ed3ca93"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a90db5e987c3e8d9bf6d07aca7ed3ca93">PORT_PB07</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 7)</td></tr>
|
||
|
|
<tr class="memdesc:a90db5e987c3e8d9bf6d07aca7ed3ca93"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PB07. <br /></td></tr>
|
||
|
|
<tr class="separator:a90db5e987c3e8d9bf6d07aca7ed3ca93"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a8b8f5e8b769787a4ce5a9b53388acc0e"><td class="memItemLeft" align="right" valign="top"><a id="a8b8f5e8b769787a4ce5a9b53388acc0e"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8b8f5e8b769787a4ce5a9b53388acc0e">PIN_PB08</a>   40</td></tr>
|
||
|
|
<tr class="memdesc:a8b8f5e8b769787a4ce5a9b53388acc0e"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PB08. <br /></td></tr>
|
||
|
|
<tr class="separator:a8b8f5e8b769787a4ce5a9b53388acc0e"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a8f41524b9dee7a9ed113322b5f8e2663"><td class="memItemLeft" align="right" valign="top"><a id="a8f41524b9dee7a9ed113322b5f8e2663"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8f41524b9dee7a9ed113322b5f8e2663">PORT_PB08</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 8)</td></tr>
|
||
|
|
<tr class="memdesc:a8f41524b9dee7a9ed113322b5f8e2663"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PB08. <br /></td></tr>
|
||
|
|
<tr class="separator:a8f41524b9dee7a9ed113322b5f8e2663"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a123a2189653c39f91fc0231945166826"><td class="memItemLeft" align="right" valign="top"><a id="a123a2189653c39f91fc0231945166826"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a123a2189653c39f91fc0231945166826">PIN_PB09</a>   41</td></tr>
|
||
|
|
<tr class="memdesc:a123a2189653c39f91fc0231945166826"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PB09. <br /></td></tr>
|
||
|
|
<tr class="separator:a123a2189653c39f91fc0231945166826"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a2306731061c4957fb522091fab1fcbde"><td class="memItemLeft" align="right" valign="top"><a id="a2306731061c4957fb522091fab1fcbde"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2306731061c4957fb522091fab1fcbde">PORT_PB09</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 9)</td></tr>
|
||
|
|
<tr class="memdesc:a2306731061c4957fb522091fab1fcbde"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PB09. <br /></td></tr>
|
||
|
|
<tr class="separator:a2306731061c4957fb522091fab1fcbde"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:ace5077df47f85d8716961068d23999f9"><td class="memItemLeft" align="right" valign="top"><a id="ace5077df47f85d8716961068d23999f9"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ace5077df47f85d8716961068d23999f9">PIN_PB10</a>   42</td></tr>
|
||
|
|
<tr class="memdesc:ace5077df47f85d8716961068d23999f9"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PB10. <br /></td></tr>
|
||
|
|
<tr class="separator:ace5077df47f85d8716961068d23999f9"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a0b997f045f6040bd59acdef30f6f7110"><td class="memItemLeft" align="right" valign="top"><a id="a0b997f045f6040bd59acdef30f6f7110"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0b997f045f6040bd59acdef30f6f7110">PORT_PB10</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 10)</td></tr>
|
||
|
|
<tr class="memdesc:a0b997f045f6040bd59acdef30f6f7110"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PB10. <br /></td></tr>
|
||
|
|
<tr class="separator:a0b997f045f6040bd59acdef30f6f7110"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:aa67c3fe74fde6a524858a0dd54809391"><td class="memItemLeft" align="right" valign="top"><a id="aa67c3fe74fde6a524858a0dd54809391"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa67c3fe74fde6a524858a0dd54809391">PIN_PB11</a>   43</td></tr>
|
||
|
|
<tr class="memdesc:aa67c3fe74fde6a524858a0dd54809391"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PB11. <br /></td></tr>
|
||
|
|
<tr class="separator:aa67c3fe74fde6a524858a0dd54809391"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a1ccf3cd8ad10fc9741c4b312067ddc79"><td class="memItemLeft" align="right" valign="top"><a id="a1ccf3cd8ad10fc9741c4b312067ddc79"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1ccf3cd8ad10fc9741c4b312067ddc79">PORT_PB11</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 11)</td></tr>
|
||
|
|
<tr class="memdesc:a1ccf3cd8ad10fc9741c4b312067ddc79"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PB11. <br /></td></tr>
|
||
|
|
<tr class="separator:a1ccf3cd8ad10fc9741c4b312067ddc79"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a4c73054a65245b26b8d56438c269a5f8"><td class="memItemLeft" align="right" valign="top"><a id="a4c73054a65245b26b8d56438c269a5f8"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4c73054a65245b26b8d56438c269a5f8">PIN_PB12</a>   44</td></tr>
|
||
|
|
<tr class="memdesc:a4c73054a65245b26b8d56438c269a5f8"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PB12. <br /></td></tr>
|
||
|
|
<tr class="separator:a4c73054a65245b26b8d56438c269a5f8"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:ad7faa5aa61654ec1cc9b73c6c891e63d"><td class="memItemLeft" align="right" valign="top"><a id="ad7faa5aa61654ec1cc9b73c6c891e63d"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad7faa5aa61654ec1cc9b73c6c891e63d">PORT_PB12</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 12)</td></tr>
|
||
|
|
<tr class="memdesc:ad7faa5aa61654ec1cc9b73c6c891e63d"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PB12. <br /></td></tr>
|
||
|
|
<tr class="separator:ad7faa5aa61654ec1cc9b73c6c891e63d"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:aac822122271e05b08d918692cd81ebe9"><td class="memItemLeft" align="right" valign="top"><a id="aac822122271e05b08d918692cd81ebe9"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aac822122271e05b08d918692cd81ebe9">PIN_PB13</a>   45</td></tr>
|
||
|
|
<tr class="memdesc:aac822122271e05b08d918692cd81ebe9"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PB13. <br /></td></tr>
|
||
|
|
<tr class="separator:aac822122271e05b08d918692cd81ebe9"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:ab8c288952382d41b0f988263f2431f5e"><td class="memItemLeft" align="right" valign="top"><a id="ab8c288952382d41b0f988263f2431f5e"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab8c288952382d41b0f988263f2431f5e">PORT_PB13</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 13)</td></tr>
|
||
|
|
<tr class="memdesc:ab8c288952382d41b0f988263f2431f5e"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PB13. <br /></td></tr>
|
||
|
|
<tr class="separator:ab8c288952382d41b0f988263f2431f5e"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a886b07fd0b01a62c7236bfac719c0d85"><td class="memItemLeft" align="right" valign="top"><a id="a886b07fd0b01a62c7236bfac719c0d85"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a886b07fd0b01a62c7236bfac719c0d85">PIN_PB14</a>   46</td></tr>
|
||
|
|
<tr class="memdesc:a886b07fd0b01a62c7236bfac719c0d85"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PB14. <br /></td></tr>
|
||
|
|
<tr class="separator:a886b07fd0b01a62c7236bfac719c0d85"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a32bc1dd688c97d54a2a9e9d34f1e5cc3"><td class="memItemLeft" align="right" valign="top"><a id="a32bc1dd688c97d54a2a9e9d34f1e5cc3"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a32bc1dd688c97d54a2a9e9d34f1e5cc3">PORT_PB14</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 14)</td></tr>
|
||
|
|
<tr class="memdesc:a32bc1dd688c97d54a2a9e9d34f1e5cc3"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PB14. <br /></td></tr>
|
||
|
|
<tr class="separator:a32bc1dd688c97d54a2a9e9d34f1e5cc3"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a2dfe52fc70c0fa20c50efcb5260b7f6e"><td class="memItemLeft" align="right" valign="top"><a id="a2dfe52fc70c0fa20c50efcb5260b7f6e"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2dfe52fc70c0fa20c50efcb5260b7f6e">PIN_PB15</a>   47</td></tr>
|
||
|
|
<tr class="memdesc:a2dfe52fc70c0fa20c50efcb5260b7f6e"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PB15. <br /></td></tr>
|
||
|
|
<tr class="separator:a2dfe52fc70c0fa20c50efcb5260b7f6e"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:af09dfb22f84aca0ec53dd7c0354ea5a8"><td class="memItemLeft" align="right" valign="top"><a id="af09dfb22f84aca0ec53dd7c0354ea5a8"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af09dfb22f84aca0ec53dd7c0354ea5a8">PORT_PB15</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 15)</td></tr>
|
||
|
|
<tr class="memdesc:af09dfb22f84aca0ec53dd7c0354ea5a8"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PB15. <br /></td></tr>
|
||
|
|
<tr class="separator:af09dfb22f84aca0ec53dd7c0354ea5a8"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a2638b944d2f382c990e0a4c6810aea1e"><td class="memItemLeft" align="right" valign="top"><a id="a2638b944d2f382c990e0a4c6810aea1e"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2638b944d2f382c990e0a4c6810aea1e">PIN_PB16</a>   48</td></tr>
|
||
|
|
<tr class="memdesc:a2638b944d2f382c990e0a4c6810aea1e"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PB16. <br /></td></tr>
|
||
|
|
<tr class="separator:a2638b944d2f382c990e0a4c6810aea1e"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a78ca7ff8dfdbaaaac7d25499b54dcc19"><td class="memItemLeft" align="right" valign="top"><a id="a78ca7ff8dfdbaaaac7d25499b54dcc19"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a78ca7ff8dfdbaaaac7d25499b54dcc19">PORT_PB16</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 16)</td></tr>
|
||
|
|
<tr class="memdesc:a78ca7ff8dfdbaaaac7d25499b54dcc19"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PB16. <br /></td></tr>
|
||
|
|
<tr class="separator:a78ca7ff8dfdbaaaac7d25499b54dcc19"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:a7589e10e4bc65e51d370b6fb985d8f2c"><td class="memItemLeft" align="right" valign="top"><a id="a7589e10e4bc65e51d370b6fb985d8f2c"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7589e10e4bc65e51d370b6fb985d8f2c">PIN_PB17</a>   49</td></tr>
|
||
|
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<tr class="memdesc:a7589e10e4bc65e51d370b6fb985d8f2c"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PB17. <br /></td></tr>
|
||
|
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<tr class="separator:a7589e10e4bc65e51d370b6fb985d8f2c"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:acdd1bb42d5a959b7f69d87d8b491d28e"><td class="memItemLeft" align="right" valign="top"><a id="acdd1bb42d5a959b7f69d87d8b491d28e"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#acdd1bb42d5a959b7f69d87d8b491d28e">PORT_PB17</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 17)</td></tr>
|
||
|
|
<tr class="memdesc:acdd1bb42d5a959b7f69d87d8b491d28e"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PB17. <br /></td></tr>
|
||
|
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<tr class="separator:acdd1bb42d5a959b7f69d87d8b491d28e"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a5b1dde7ce3380c9ccaebded4d6169a8a"><td class="memItemLeft" align="right" valign="top"><a id="a5b1dde7ce3380c9ccaebded4d6169a8a"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5b1dde7ce3380c9ccaebded4d6169a8a">PIN_PB18</a>   50</td></tr>
|
||
|
|
<tr class="memdesc:a5b1dde7ce3380c9ccaebded4d6169a8a"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PB18. <br /></td></tr>
|
||
|
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<tr class="separator:a5b1dde7ce3380c9ccaebded4d6169a8a"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a80afd65b4a2022a58f03ee893c4093a7"><td class="memItemLeft" align="right" valign="top"><a id="a80afd65b4a2022a58f03ee893c4093a7"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a80afd65b4a2022a58f03ee893c4093a7">PORT_PB18</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 18)</td></tr>
|
||
|
|
<tr class="memdesc:a80afd65b4a2022a58f03ee893c4093a7"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PB18. <br /></td></tr>
|
||
|
|
<tr class="separator:a80afd65b4a2022a58f03ee893c4093a7"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:acc8605a048a9bed0bef57e14d7443cd2"><td class="memItemLeft" align="right" valign="top"><a id="acc8605a048a9bed0bef57e14d7443cd2"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#acc8605a048a9bed0bef57e14d7443cd2">PIN_PB19</a>   51</td></tr>
|
||
|
|
<tr class="memdesc:acc8605a048a9bed0bef57e14d7443cd2"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PB19. <br /></td></tr>
|
||
|
|
<tr class="separator:acc8605a048a9bed0bef57e14d7443cd2"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:aeb3e0516ff8cd5e6cddfac6deccd6618"><td class="memItemLeft" align="right" valign="top"><a id="aeb3e0516ff8cd5e6cddfac6deccd6618"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aeb3e0516ff8cd5e6cddfac6deccd6618">PORT_PB19</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 19)</td></tr>
|
||
|
|
<tr class="memdesc:aeb3e0516ff8cd5e6cddfac6deccd6618"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PB19. <br /></td></tr>
|
||
|
|
<tr class="separator:aeb3e0516ff8cd5e6cddfac6deccd6618"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:af7836380ea76d57950f3bf4237e778c9"><td class="memItemLeft" align="right" valign="top"><a id="af7836380ea76d57950f3bf4237e778c9"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af7836380ea76d57950f3bf4237e778c9">PIN_PB20</a>   52</td></tr>
|
||
|
|
<tr class="memdesc:af7836380ea76d57950f3bf4237e778c9"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PB20. <br /></td></tr>
|
||
|
|
<tr class="separator:af7836380ea76d57950f3bf4237e778c9"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a6b03947ff8645b11acba69970ceaad46"><td class="memItemLeft" align="right" valign="top"><a id="a6b03947ff8645b11acba69970ceaad46"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6b03947ff8645b11acba69970ceaad46">PORT_PB20</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 20)</td></tr>
|
||
|
|
<tr class="memdesc:a6b03947ff8645b11acba69970ceaad46"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PB20. <br /></td></tr>
|
||
|
|
<tr class="separator:a6b03947ff8645b11acba69970ceaad46"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a03a2942cf80fd3bd4dcbac6cd406a2a0"><td class="memItemLeft" align="right" valign="top"><a id="a03a2942cf80fd3bd4dcbac6cd406a2a0"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a03a2942cf80fd3bd4dcbac6cd406a2a0">PIN_PB21</a>   53</td></tr>
|
||
|
|
<tr class="memdesc:a03a2942cf80fd3bd4dcbac6cd406a2a0"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PB21. <br /></td></tr>
|
||
|
|
<tr class="separator:a03a2942cf80fd3bd4dcbac6cd406a2a0"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a8e399c6b3ff8105829beca75120784a8"><td class="memItemLeft" align="right" valign="top"><a id="a8e399c6b3ff8105829beca75120784a8"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8e399c6b3ff8105829beca75120784a8">PORT_PB21</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 21)</td></tr>
|
||
|
|
<tr class="memdesc:a8e399c6b3ff8105829beca75120784a8"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PB21. <br /></td></tr>
|
||
|
|
<tr class="separator:a8e399c6b3ff8105829beca75120784a8"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a5f8249fb7d7568f6ac27dd4e38171724"><td class="memItemLeft" align="right" valign="top"><a id="a5f8249fb7d7568f6ac27dd4e38171724"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5f8249fb7d7568f6ac27dd4e38171724">PIN_PB22</a>   54</td></tr>
|
||
|
|
<tr class="memdesc:a5f8249fb7d7568f6ac27dd4e38171724"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PB22. <br /></td></tr>
|
||
|
|
<tr class="separator:a5f8249fb7d7568f6ac27dd4e38171724"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a95a4b81bf0cc07bbb8a655b9ddf26a72"><td class="memItemLeft" align="right" valign="top"><a id="a95a4b81bf0cc07bbb8a655b9ddf26a72"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a95a4b81bf0cc07bbb8a655b9ddf26a72">PORT_PB22</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 22)</td></tr>
|
||
|
|
<tr class="memdesc:a95a4b81bf0cc07bbb8a655b9ddf26a72"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PB22. <br /></td></tr>
|
||
|
|
<tr class="separator:a95a4b81bf0cc07bbb8a655b9ddf26a72"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a78443bb5df689db4f8d87386e31775db"><td class="memItemLeft" align="right" valign="top"><a id="a78443bb5df689db4f8d87386e31775db"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a78443bb5df689db4f8d87386e31775db">PIN_PB23</a>   55</td></tr>
|
||
|
|
<tr class="memdesc:a78443bb5df689db4f8d87386e31775db"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PB23. <br /></td></tr>
|
||
|
|
<tr class="separator:a78443bb5df689db4f8d87386e31775db"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a91aa71a43b5c03cfde8f8f8957a7bcbe"><td class="memItemLeft" align="right" valign="top"><a id="a91aa71a43b5c03cfde8f8f8957a7bcbe"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a91aa71a43b5c03cfde8f8f8957a7bcbe">PORT_PB23</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 23)</td></tr>
|
||
|
|
<tr class="memdesc:a91aa71a43b5c03cfde8f8f8957a7bcbe"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PB23. <br /></td></tr>
|
||
|
|
<tr class="separator:a91aa71a43b5c03cfde8f8f8957a7bcbe"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a717e2ab04772dbf3c0e00416a5e373d4"><td class="memItemLeft" align="right" valign="top"><a id="a717e2ab04772dbf3c0e00416a5e373d4"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a717e2ab04772dbf3c0e00416a5e373d4">PIN_PB24</a>   56</td></tr>
|
||
|
|
<tr class="memdesc:a717e2ab04772dbf3c0e00416a5e373d4"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PB24. <br /></td></tr>
|
||
|
|
<tr class="separator:a717e2ab04772dbf3c0e00416a5e373d4"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:ae1b80241734d6ccb2ffe2a96d25fe0f7"><td class="memItemLeft" align="right" valign="top"><a id="ae1b80241734d6ccb2ffe2a96d25fe0f7"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae1b80241734d6ccb2ffe2a96d25fe0f7">PORT_PB24</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 24)</td></tr>
|
||
|
|
<tr class="memdesc:ae1b80241734d6ccb2ffe2a96d25fe0f7"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PB24. <br /></td></tr>
|
||
|
|
<tr class="separator:ae1b80241734d6ccb2ffe2a96d25fe0f7"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:ab7eb0e34282b5fbcd617566cb8ce47f8"><td class="memItemLeft" align="right" valign="top"><a id="ab7eb0e34282b5fbcd617566cb8ce47f8"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab7eb0e34282b5fbcd617566cb8ce47f8">PIN_PB25</a>   57</td></tr>
|
||
|
|
<tr class="memdesc:ab7eb0e34282b5fbcd617566cb8ce47f8"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PB25. <br /></td></tr>
|
||
|
|
<tr class="separator:ab7eb0e34282b5fbcd617566cb8ce47f8"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a69f2f7dbd3584ce22441ca4c3033106e"><td class="memItemLeft" align="right" valign="top"><a id="a69f2f7dbd3584ce22441ca4c3033106e"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a69f2f7dbd3584ce22441ca4c3033106e">PORT_PB25</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 25)</td></tr>
|
||
|
|
<tr class="memdesc:a69f2f7dbd3584ce22441ca4c3033106e"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PB25. <br /></td></tr>
|
||
|
|
<tr class="separator:a69f2f7dbd3584ce22441ca4c3033106e"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a5ff751a11f710f459e0ccb12b6db3e29"><td class="memItemLeft" align="right" valign="top"><a id="a5ff751a11f710f459e0ccb12b6db3e29"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5ff751a11f710f459e0ccb12b6db3e29">PIN_PB30</a>   62</td></tr>
|
||
|
|
<tr class="memdesc:a5ff751a11f710f459e0ccb12b6db3e29"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PB30. <br /></td></tr>
|
||
|
|
<tr class="separator:a5ff751a11f710f459e0ccb12b6db3e29"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a27df2398dd0fdf6b00f124d9adfba340"><td class="memItemLeft" align="right" valign="top"><a id="a27df2398dd0fdf6b00f124d9adfba340"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a27df2398dd0fdf6b00f124d9adfba340">PORT_PB30</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 30)</td></tr>
|
||
|
|
<tr class="memdesc:a27df2398dd0fdf6b00f124d9adfba340"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PB30. <br /></td></tr>
|
||
|
|
<tr class="separator:a27df2398dd0fdf6b00f124d9adfba340"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a72a0012b6ea518e8159189ee2168a78d"><td class="memItemLeft" align="right" valign="top"><a id="a72a0012b6ea518e8159189ee2168a78d"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a72a0012b6ea518e8159189ee2168a78d">PIN_PB31</a>   63</td></tr>
|
||
|
|
<tr class="memdesc:a72a0012b6ea518e8159189ee2168a78d"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PB31. <br /></td></tr>
|
||
|
|
<tr class="separator:a72a0012b6ea518e8159189ee2168a78d"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:aa83c53d5443d75e444f99bfb30ba6fac"><td class="memItemLeft" align="right" valign="top"><a id="aa83c53d5443d75e444f99bfb30ba6fac"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa83c53d5443d75e444f99bfb30ba6fac">PORT_PB31</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 31)</td></tr>
|
||
|
|
<tr class="memdesc:aa83c53d5443d75e444f99bfb30ba6fac"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PB31. <br /></td></tr>
|
||
|
|
<tr class="separator:aa83c53d5443d75e444f99bfb30ba6fac"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:aff1ff6d0b345cc4df265248e7477fbe1"><td class="memItemLeft" align="right" valign="top"><a id="aff1ff6d0b345cc4df265248e7477fbe1"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aff1ff6d0b345cc4df265248e7477fbe1">PIN_PC00</a>   64</td></tr>
|
||
|
|
<tr class="memdesc:aff1ff6d0b345cc4df265248e7477fbe1"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PC00. <br /></td></tr>
|
||
|
|
<tr class="separator:aff1ff6d0b345cc4df265248e7477fbe1"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a11c2ad8d86644aed31f81d4f8c28c058"><td class="memItemLeft" align="right" valign="top"><a id="a11c2ad8d86644aed31f81d4f8c28c058"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a11c2ad8d86644aed31f81d4f8c28c058">PORT_PC00</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 0)</td></tr>
|
||
|
|
<tr class="memdesc:a11c2ad8d86644aed31f81d4f8c28c058"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PC00. <br /></td></tr>
|
||
|
|
<tr class="separator:a11c2ad8d86644aed31f81d4f8c28c058"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a660f2c4b8185501aedfb0ffcc7d7b5e5"><td class="memItemLeft" align="right" valign="top"><a id="a660f2c4b8185501aedfb0ffcc7d7b5e5"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a660f2c4b8185501aedfb0ffcc7d7b5e5">PIN_PC01</a>   65</td></tr>
|
||
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<tr class="memdesc:a660f2c4b8185501aedfb0ffcc7d7b5e5"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PC01. <br /></td></tr>
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<tr class="separator:a660f2c4b8185501aedfb0ffcc7d7b5e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6bbc571416914e21fc6886d985de7d45"><td class="memItemLeft" align="right" valign="top"><a id="a6bbc571416914e21fc6886d985de7d45"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6bbc571416914e21fc6886d985de7d45">PORT_PC01</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 1)</td></tr>
|
||
|
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<tr class="memdesc:a6bbc571416914e21fc6886d985de7d45"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PC01. <br /></td></tr>
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<tr class="separator:a6bbc571416914e21fc6886d985de7d45"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a00962afe8103e69f974c3e0b2d8b5460"><td class="memItemLeft" align="right" valign="top"><a id="a00962afe8103e69f974c3e0b2d8b5460"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a00962afe8103e69f974c3e0b2d8b5460">PIN_PC02</a>   66</td></tr>
|
||
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<tr class="memdesc:a00962afe8103e69f974c3e0b2d8b5460"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PC02. <br /></td></tr>
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<tr class="separator:a00962afe8103e69f974c3e0b2d8b5460"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a0bae21ce0219c7b02ed1f8cc7fa8eb0e"><td class="memItemLeft" align="right" valign="top"><a id="a0bae21ce0219c7b02ed1f8cc7fa8eb0e"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0bae21ce0219c7b02ed1f8cc7fa8eb0e">PORT_PC02</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 2)</td></tr>
|
||
|
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<tr class="memdesc:a0bae21ce0219c7b02ed1f8cc7fa8eb0e"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PC02. <br /></td></tr>
|
||
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<tr class="separator:a0bae21ce0219c7b02ed1f8cc7fa8eb0e"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:abd5606317bd1a2b543feb22345d24dce"><td class="memItemLeft" align="right" valign="top"><a id="abd5606317bd1a2b543feb22345d24dce"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#abd5606317bd1a2b543feb22345d24dce">PIN_PC03</a>   67</td></tr>
|
||
|
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<tr class="memdesc:abd5606317bd1a2b543feb22345d24dce"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PC03. <br /></td></tr>
|
||
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<tr class="separator:abd5606317bd1a2b543feb22345d24dce"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a713db11fba4c30b49c3ba91694ce7005"><td class="memItemLeft" align="right" valign="top"><a id="a713db11fba4c30b49c3ba91694ce7005"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a713db11fba4c30b49c3ba91694ce7005">PORT_PC03</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 3)</td></tr>
|
||
|
|
<tr class="memdesc:a713db11fba4c30b49c3ba91694ce7005"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PC03. <br /></td></tr>
|
||
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<tr class="separator:a713db11fba4c30b49c3ba91694ce7005"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a113284b163f89067ff5cbeca3064d635"><td class="memItemLeft" align="right" valign="top"><a id="a113284b163f89067ff5cbeca3064d635"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a113284b163f89067ff5cbeca3064d635">PIN_PC05</a>   69</td></tr>
|
||
|
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<tr class="memdesc:a113284b163f89067ff5cbeca3064d635"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PC05. <br /></td></tr>
|
||
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<tr class="separator:a113284b163f89067ff5cbeca3064d635"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:a1c3caebf2592426330ddbc91613dbe3f"><td class="memItemLeft" align="right" valign="top"><a id="a1c3caebf2592426330ddbc91613dbe3f"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1c3caebf2592426330ddbc91613dbe3f">PORT_PC05</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 5)</td></tr>
|
||
|
|
<tr class="memdesc:a1c3caebf2592426330ddbc91613dbe3f"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PC05. <br /></td></tr>
|
||
|
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<tr class="separator:a1c3caebf2592426330ddbc91613dbe3f"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:ac482b80449bc985c512a6070377e63a0"><td class="memItemLeft" align="right" valign="top"><a id="ac482b80449bc985c512a6070377e63a0"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac482b80449bc985c512a6070377e63a0">PIN_PC06</a>   70</td></tr>
|
||
|
|
<tr class="memdesc:ac482b80449bc985c512a6070377e63a0"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PC06. <br /></td></tr>
|
||
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<tr class="separator:ac482b80449bc985c512a6070377e63a0"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a00badc056aab21797bcf477e27000e59"><td class="memItemLeft" align="right" valign="top"><a id="a00badc056aab21797bcf477e27000e59"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a00badc056aab21797bcf477e27000e59">PORT_PC06</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 6)</td></tr>
|
||
|
|
<tr class="memdesc:a00badc056aab21797bcf477e27000e59"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PC06. <br /></td></tr>
|
||
|
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<tr class="separator:a00badc056aab21797bcf477e27000e59"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:a2f88164c5c1d9f191d8ab143a4a93b8f"><td class="memItemLeft" align="right" valign="top"><a id="a2f88164c5c1d9f191d8ab143a4a93b8f"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2f88164c5c1d9f191d8ab143a4a93b8f">PIN_PC07</a>   71</td></tr>
|
||
|
|
<tr class="memdesc:a2f88164c5c1d9f191d8ab143a4a93b8f"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PC07. <br /></td></tr>
|
||
|
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<tr class="separator:a2f88164c5c1d9f191d8ab143a4a93b8f"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:ad47864c04a5f2f463c67f73e2797b4a1"><td class="memItemLeft" align="right" valign="top"><a id="ad47864c04a5f2f463c67f73e2797b4a1"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad47864c04a5f2f463c67f73e2797b4a1">PORT_PC07</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 7)</td></tr>
|
||
|
|
<tr class="memdesc:ad47864c04a5f2f463c67f73e2797b4a1"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PC07. <br /></td></tr>
|
||
|
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<tr class="separator:ad47864c04a5f2f463c67f73e2797b4a1"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:aff6b265d92a4e897c638c1eee384ec8c"><td class="memItemLeft" align="right" valign="top"><a id="aff6b265d92a4e897c638c1eee384ec8c"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aff6b265d92a4e897c638c1eee384ec8c">PIN_PC10</a>   74</td></tr>
|
||
|
|
<tr class="memdesc:aff6b265d92a4e897c638c1eee384ec8c"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PC10. <br /></td></tr>
|
||
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<tr class="separator:aff6b265d92a4e897c638c1eee384ec8c"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:a0d556ea272a97d6e5dfa4aef4efa6120"><td class="memItemLeft" align="right" valign="top"><a id="a0d556ea272a97d6e5dfa4aef4efa6120"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0d556ea272a97d6e5dfa4aef4efa6120">PORT_PC10</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 10)</td></tr>
|
||
|
|
<tr class="memdesc:a0d556ea272a97d6e5dfa4aef4efa6120"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PC10. <br /></td></tr>
|
||
|
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<tr class="separator:a0d556ea272a97d6e5dfa4aef4efa6120"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:af5383801c643a912e585fd88a5e74355"><td class="memItemLeft" align="right" valign="top"><a id="af5383801c643a912e585fd88a5e74355"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af5383801c643a912e585fd88a5e74355">PIN_PC11</a>   75</td></tr>
|
||
|
|
<tr class="memdesc:af5383801c643a912e585fd88a5e74355"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PC11. <br /></td></tr>
|
||
|
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<tr class="separator:af5383801c643a912e585fd88a5e74355"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:ab26bfe978997514d19bf0774f7ac8886"><td class="memItemLeft" align="right" valign="top"><a id="ab26bfe978997514d19bf0774f7ac8886"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab26bfe978997514d19bf0774f7ac8886">PORT_PC11</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 11)</td></tr>
|
||
|
|
<tr class="memdesc:ab26bfe978997514d19bf0774f7ac8886"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PC11. <br /></td></tr>
|
||
|
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<tr class="separator:ab26bfe978997514d19bf0774f7ac8886"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a3cd7dc7eacdf635f5961b88cf8e9615c"><td class="memItemLeft" align="right" valign="top"><a id="a3cd7dc7eacdf635f5961b88cf8e9615c"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3cd7dc7eacdf635f5961b88cf8e9615c">PIN_PC12</a>   76</td></tr>
|
||
|
|
<tr class="memdesc:a3cd7dc7eacdf635f5961b88cf8e9615c"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PC12. <br /></td></tr>
|
||
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<tr class="separator:a3cd7dc7eacdf635f5961b88cf8e9615c"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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|
<tr class="memitem:a905c16857a69276631ade450d5cd7773"><td class="memItemLeft" align="right" valign="top"><a id="a905c16857a69276631ade450d5cd7773"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a905c16857a69276631ade450d5cd7773">PORT_PC12</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 12)</td></tr>
|
||
|
|
<tr class="memdesc:a905c16857a69276631ade450d5cd7773"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PC12. <br /></td></tr>
|
||
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<tr class="separator:a905c16857a69276631ade450d5cd7773"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a8b2bddce7b7c86858425a98b38b66f72"><td class="memItemLeft" align="right" valign="top"><a id="a8b2bddce7b7c86858425a98b38b66f72"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8b2bddce7b7c86858425a98b38b66f72">PIN_PC13</a>   77</td></tr>
|
||
|
|
<tr class="memdesc:a8b2bddce7b7c86858425a98b38b66f72"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PC13. <br /></td></tr>
|
||
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<tr class="separator:a8b2bddce7b7c86858425a98b38b66f72"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a6d2def8b2e60b67f9143d64cb1dc6c41"><td class="memItemLeft" align="right" valign="top"><a id="a6d2def8b2e60b67f9143d64cb1dc6c41"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6d2def8b2e60b67f9143d64cb1dc6c41">PORT_PC13</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 13)</td></tr>
|
||
|
|
<tr class="memdesc:a6d2def8b2e60b67f9143d64cb1dc6c41"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PC13. <br /></td></tr>
|
||
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<tr class="separator:a6d2def8b2e60b67f9143d64cb1dc6c41"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:a4b5d8d4c929b4211beaf0c37369192e1"><td class="memItemLeft" align="right" valign="top"><a id="a4b5d8d4c929b4211beaf0c37369192e1"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4b5d8d4c929b4211beaf0c37369192e1">PIN_PC14</a>   78</td></tr>
|
||
|
|
<tr class="memdesc:a4b5d8d4c929b4211beaf0c37369192e1"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PC14. <br /></td></tr>
|
||
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<tr class="separator:a4b5d8d4c929b4211beaf0c37369192e1"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a081fad1e7cbd9b3a45b2337b99044087"><td class="memItemLeft" align="right" valign="top"><a id="a081fad1e7cbd9b3a45b2337b99044087"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a081fad1e7cbd9b3a45b2337b99044087">PORT_PC14</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 14)</td></tr>
|
||
|
|
<tr class="memdesc:a081fad1e7cbd9b3a45b2337b99044087"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PC14. <br /></td></tr>
|
||
|
|
<tr class="separator:a081fad1e7cbd9b3a45b2337b99044087"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a67fdf6e33ae3300beb2300d92faf106a"><td class="memItemLeft" align="right" valign="top"><a id="a67fdf6e33ae3300beb2300d92faf106a"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a67fdf6e33ae3300beb2300d92faf106a">PIN_PC15</a>   79</td></tr>
|
||
|
|
<tr class="memdesc:a67fdf6e33ae3300beb2300d92faf106a"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PC15. <br /></td></tr>
|
||
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<tr class="separator:a67fdf6e33ae3300beb2300d92faf106a"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:adb50ba68b94556d52f19e689442c20e9"><td class="memItemLeft" align="right" valign="top"><a id="adb50ba68b94556d52f19e689442c20e9"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#adb50ba68b94556d52f19e689442c20e9">PORT_PC15</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 15)</td></tr>
|
||
|
|
<tr class="memdesc:adb50ba68b94556d52f19e689442c20e9"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PC15. <br /></td></tr>
|
||
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<tr class="separator:adb50ba68b94556d52f19e689442c20e9"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:a34f523d2ae97243b4c35725ef40b902d"><td class="memItemLeft" align="right" valign="top"><a id="a34f523d2ae97243b4c35725ef40b902d"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a34f523d2ae97243b4c35725ef40b902d">PIN_PC16</a>   80</td></tr>
|
||
|
|
<tr class="memdesc:a34f523d2ae97243b4c35725ef40b902d"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PC16. <br /></td></tr>
|
||
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<tr class="separator:a34f523d2ae97243b4c35725ef40b902d"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:a2bac9beedae61de427547a9c1c717e2b"><td class="memItemLeft" align="right" valign="top"><a id="a2bac9beedae61de427547a9c1c717e2b"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2bac9beedae61de427547a9c1c717e2b">PORT_PC16</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 16)</td></tr>
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||
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<tr class="memdesc:a2bac9beedae61de427547a9c1c717e2b"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PC16. <br /></td></tr>
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<tr class="separator:a2bac9beedae61de427547a9c1c717e2b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a74254fd4866b493faed97034af306210"><td class="memItemLeft" align="right" valign="top"><a id="a74254fd4866b493faed97034af306210"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a74254fd4866b493faed97034af306210">PIN_PC17</a>   81</td></tr>
|
||
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<tr class="memdesc:a74254fd4866b493faed97034af306210"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PC17. <br /></td></tr>
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<tr class="separator:a74254fd4866b493faed97034af306210"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:ad6518af86729aa8ff01df7e35fd79ae3"><td class="memItemLeft" align="right" valign="top"><a id="ad6518af86729aa8ff01df7e35fd79ae3"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad6518af86729aa8ff01df7e35fd79ae3">PORT_PC17</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 17)</td></tr>
|
||
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<tr class="memdesc:ad6518af86729aa8ff01df7e35fd79ae3"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PC17. <br /></td></tr>
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<tr class="separator:ad6518af86729aa8ff01df7e35fd79ae3"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a92d75c7dac26934a8687165c023c542b"><td class="memItemLeft" align="right" valign="top"><a id="a92d75c7dac26934a8687165c023c542b"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a92d75c7dac26934a8687165c023c542b">PIN_PC18</a>   82</td></tr>
|
||
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<tr class="memdesc:a92d75c7dac26934a8687165c023c542b"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PC18. <br /></td></tr>
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<tr class="separator:a92d75c7dac26934a8687165c023c542b"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:ae3d795043c31e9ff3166671f9d2f4bdf"><td class="memItemLeft" align="right" valign="top"><a id="ae3d795043c31e9ff3166671f9d2f4bdf"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae3d795043c31e9ff3166671f9d2f4bdf">PORT_PC18</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 18)</td></tr>
|
||
|
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<tr class="memdesc:ae3d795043c31e9ff3166671f9d2f4bdf"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PC18. <br /></td></tr>
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||
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<tr class="separator:ae3d795043c31e9ff3166671f9d2f4bdf"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:aaed3b1e599aec3466f800bf9ce0d81b4"><td class="memItemLeft" align="right" valign="top"><a id="aaed3b1e599aec3466f800bf9ce0d81b4"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aaed3b1e599aec3466f800bf9ce0d81b4">PIN_PC19</a>   83</td></tr>
|
||
|
|
<tr class="memdesc:aaed3b1e599aec3466f800bf9ce0d81b4"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PC19. <br /></td></tr>
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<tr class="separator:aaed3b1e599aec3466f800bf9ce0d81b4"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a46d059dbfb05f60216f1bf806999c68c"><td class="memItemLeft" align="right" valign="top"><a id="a46d059dbfb05f60216f1bf806999c68c"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a46d059dbfb05f60216f1bf806999c68c">PORT_PC19</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 19)</td></tr>
|
||
|
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<tr class="memdesc:a46d059dbfb05f60216f1bf806999c68c"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PC19. <br /></td></tr>
|
||
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<tr class="separator:a46d059dbfb05f60216f1bf806999c68c"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:aa7b1542f26578e30975a3a87cc25de30"><td class="memItemLeft" align="right" valign="top"><a id="aa7b1542f26578e30975a3a87cc25de30"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa7b1542f26578e30975a3a87cc25de30">PIN_PC20</a>   84</td></tr>
|
||
|
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<tr class="memdesc:aa7b1542f26578e30975a3a87cc25de30"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PC20. <br /></td></tr>
|
||
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<tr class="separator:aa7b1542f26578e30975a3a87cc25de30"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:a114010c47944330971bab1bf0d022f5b"><td class="memItemLeft" align="right" valign="top"><a id="a114010c47944330971bab1bf0d022f5b"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a114010c47944330971bab1bf0d022f5b">PORT_PC20</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 20)</td></tr>
|
||
|
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<tr class="memdesc:a114010c47944330971bab1bf0d022f5b"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PC20. <br /></td></tr>
|
||
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<tr class="separator:a114010c47944330971bab1bf0d022f5b"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a8dce6d205cc0732e2f3223c4cf95b474"><td class="memItemLeft" align="right" valign="top"><a id="a8dce6d205cc0732e2f3223c4cf95b474"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8dce6d205cc0732e2f3223c4cf95b474">PIN_PC21</a>   85</td></tr>
|
||
|
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<tr class="memdesc:a8dce6d205cc0732e2f3223c4cf95b474"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PC21. <br /></td></tr>
|
||
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<tr class="separator:a8dce6d205cc0732e2f3223c4cf95b474"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:aba86406cdfef8644b1bccd64e613dbd0"><td class="memItemLeft" align="right" valign="top"><a id="aba86406cdfef8644b1bccd64e613dbd0"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aba86406cdfef8644b1bccd64e613dbd0">PORT_PC21</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 21)</td></tr>
|
||
|
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<tr class="memdesc:aba86406cdfef8644b1bccd64e613dbd0"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PC21. <br /></td></tr>
|
||
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<tr class="separator:aba86406cdfef8644b1bccd64e613dbd0"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:aacb6b9d263b7f09938ebbaa80e6bc073"><td class="memItemLeft" align="right" valign="top"><a id="aacb6b9d263b7f09938ebbaa80e6bc073"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aacb6b9d263b7f09938ebbaa80e6bc073">PIN_PC24</a>   88</td></tr>
|
||
|
|
<tr class="memdesc:aacb6b9d263b7f09938ebbaa80e6bc073"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PC24. <br /></td></tr>
|
||
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<tr class="separator:aacb6b9d263b7f09938ebbaa80e6bc073"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:a68381d5e1c3a845e0aa0a5da77435fa8"><td class="memItemLeft" align="right" valign="top"><a id="a68381d5e1c3a845e0aa0a5da77435fa8"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a68381d5e1c3a845e0aa0a5da77435fa8">PORT_PC24</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 24)</td></tr>
|
||
|
|
<tr class="memdesc:a68381d5e1c3a845e0aa0a5da77435fa8"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PC24. <br /></td></tr>
|
||
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<tr class="separator:a68381d5e1c3a845e0aa0a5da77435fa8"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:a716f129b19cde1b4c7d6010f31d1916c"><td class="memItemLeft" align="right" valign="top"><a id="a716f129b19cde1b4c7d6010f31d1916c"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a716f129b19cde1b4c7d6010f31d1916c">PIN_PC25</a>   89</td></tr>
|
||
|
|
<tr class="memdesc:a716f129b19cde1b4c7d6010f31d1916c"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PC25. <br /></td></tr>
|
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<tr class="separator:a716f129b19cde1b4c7d6010f31d1916c"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a3aebbd81aa907d14cf796d637dde8ac5"><td class="memItemLeft" align="right" valign="top"><a id="a3aebbd81aa907d14cf796d637dde8ac5"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3aebbd81aa907d14cf796d637dde8ac5">PORT_PC25</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 25)</td></tr>
|
||
|
|
<tr class="memdesc:a3aebbd81aa907d14cf796d637dde8ac5"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PC25. <br /></td></tr>
|
||
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<tr class="separator:a3aebbd81aa907d14cf796d637dde8ac5"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a7d2a96003b5360413e5d28fa4974a565"><td class="memItemLeft" align="right" valign="top"><a id="a7d2a96003b5360413e5d28fa4974a565"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7d2a96003b5360413e5d28fa4974a565">PIN_PC26</a>   90</td></tr>
|
||
|
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<tr class="memdesc:a7d2a96003b5360413e5d28fa4974a565"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PC26. <br /></td></tr>
|
||
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<tr class="separator:a7d2a96003b5360413e5d28fa4974a565"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a588ed15e3f1c67b8a14b27b57062b0a5"><td class="memItemLeft" align="right" valign="top"><a id="a588ed15e3f1c67b8a14b27b57062b0a5"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a588ed15e3f1c67b8a14b27b57062b0a5">PORT_PC26</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 26)</td></tr>
|
||
|
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<tr class="memdesc:a588ed15e3f1c67b8a14b27b57062b0a5"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PC26. <br /></td></tr>
|
||
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<tr class="separator:a588ed15e3f1c67b8a14b27b57062b0a5"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:a5b4e751041e7b348eddfea3b2f7b226d"><td class="memItemLeft" align="right" valign="top"><a id="a5b4e751041e7b348eddfea3b2f7b226d"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5b4e751041e7b348eddfea3b2f7b226d">PIN_PC27</a>   91</td></tr>
|
||
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<tr class="memdesc:a5b4e751041e7b348eddfea3b2f7b226d"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PC27. <br /></td></tr>
|
||
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<tr class="separator:a5b4e751041e7b348eddfea3b2f7b226d"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a1f8da01ce32bc343dba25fc04b12b803"><td class="memItemLeft" align="right" valign="top"><a id="a1f8da01ce32bc343dba25fc04b12b803"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1f8da01ce32bc343dba25fc04b12b803">PORT_PC27</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 27)</td></tr>
|
||
|
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<tr class="memdesc:a1f8da01ce32bc343dba25fc04b12b803"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PC27. <br /></td></tr>
|
||
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<tr class="separator:a1f8da01ce32bc343dba25fc04b12b803"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a6446765e7207e11ed7d52629fc5894d9"><td class="memItemLeft" align="right" valign="top"><a id="a6446765e7207e11ed7d52629fc5894d9"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6446765e7207e11ed7d52629fc5894d9">PIN_PC28</a>   92</td></tr>
|
||
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<tr class="memdesc:a6446765e7207e11ed7d52629fc5894d9"><td class="mdescLeft"> </td><td class="mdescRight">Pin Number for PC28. <br /></td></tr>
|
||
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<tr class="separator:a6446765e7207e11ed7d52629fc5894d9"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a8849ed04d8c4488e2e2c74b150049ce4"><td class="memItemLeft" align="right" valign="top"><a id="a8849ed04d8c4488e2e2c74b150049ce4"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8849ed04d8c4488e2e2c74b150049ce4">PORT_PC28</a>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 28)</td></tr>
|
||
|
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<tr class="memdesc:a8849ed04d8c4488e2e2c74b150049ce4"><td class="mdescLeft"> </td><td class="mdescRight">PORT Mask for PC28. <br /></td></tr>
|
||
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<tr class="separator:a8849ed04d8c4488e2e2c74b150049ce4"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:ac30d97ce1522129bc0b1f36d2b3716a6"><td class="memItemLeft" align="right" valign="top"><a id="ac30d97ce1522129bc0b1f36d2b3716a6"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac30d97ce1522129bc0b1f36d2b3716a6">PIN_PA30H_CM4_SWCLK</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(30)</td></tr>
|
||
|
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<tr class="memdesc:ac30d97ce1522129bc0b1f36d2b3716a6"><td class="mdescLeft"> </td><td class="mdescRight">CM4 signal: SWCLK on PA30 mux H. <br /></td></tr>
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||
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<tr class="separator:ac30d97ce1522129bc0b1f36d2b3716a6"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a0c65b0c544ff6fce3adb23d5e6bf716d"><td class="memItemLeft" align="right" valign="top"><a id="a0c65b0c544ff6fce3adb23d5e6bf716d"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA30H_CM4_SWCLK</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
|
||
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<tr class="separator:a0c65b0c544ff6fce3adb23d5e6bf716d"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:ab5a23c0f938c3d1c22c287998ab13fe7"><td class="memItemLeft" align="right" valign="top"><a id="ab5a23c0f938c3d1c22c287998ab13fe7"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA30H_CM4_SWCLK</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ac30d97ce1522129bc0b1f36d2b3716a6">PIN_PA30H_CM4_SWCLK</a> << 16) | MUX_PA30H_CM4_SWCLK)</td></tr>
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||
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<tr class="separator:ab5a23c0f938c3d1c22c287998ab13fe7"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a2db5cd0ec298274a56776ed672f08617"><td class="memItemLeft" align="right" valign="top"><a id="a2db5cd0ec298274a56776ed672f08617"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA30H_CM4_SWCLK</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 30)</td></tr>
|
||
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<tr class="separator:a2db5cd0ec298274a56776ed672f08617"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a8071d6e81449cdd3b4270600468e02e7"><td class="memItemLeft" align="right" valign="top"><a id="a8071d6e81449cdd3b4270600468e02e7"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8071d6e81449cdd3b4270600468e02e7">PIN_PC27M_CM4_SWO</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(91)</td></tr>
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<tr class="memdesc:a8071d6e81449cdd3b4270600468e02e7"><td class="mdescLeft"> </td><td class="mdescRight">CM4 signal: SWO on PC27 mux M. <br /></td></tr>
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<tr class="separator:a8071d6e81449cdd3b4270600468e02e7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac19a12c32e77be0877daf6f82374dbb8"><td class="memItemLeft" align="right" valign="top"><a id="ac19a12c32e77be0877daf6f82374dbb8"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC27M_CM4_SWO</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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<tr class="separator:ac19a12c32e77be0877daf6f82374dbb8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a049591d57d5573a50c7e46539d9ac8be"><td class="memItemLeft" align="right" valign="top"><a id="a049591d57d5573a50c7e46539d9ac8be"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC27M_CM4_SWO</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a8071d6e81449cdd3b4270600468e02e7">PIN_PC27M_CM4_SWO</a> << 16) | MUX_PC27M_CM4_SWO)</td></tr>
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<tr class="separator:a049591d57d5573a50c7e46539d9ac8be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a279610a20565ad1759e06e196d1c4384"><td class="memItemLeft" align="right" valign="top"><a id="a279610a20565ad1759e06e196d1c4384"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC27M_CM4_SWO</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 27)</td></tr>
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<tr class="separator:a279610a20565ad1759e06e196d1c4384"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3a8561e0a90e065dd61d350761cd1eaf"><td class="memItemLeft" align="right" valign="top"><a id="a3a8561e0a90e065dd61d350761cd1eaf"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3a8561e0a90e065dd61d350761cd1eaf">PIN_PB30H_CM4_SWO</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(62)</td></tr>
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||
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<tr class="memdesc:a3a8561e0a90e065dd61d350761cd1eaf"><td class="mdescLeft"> </td><td class="mdescRight">CM4 signal: SWO on PB30 mux H. <br /></td></tr>
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<tr class="separator:a3a8561e0a90e065dd61d350761cd1eaf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6056aab398e8039f6b9720d6a83b4e46"><td class="memItemLeft" align="right" valign="top"><a id="a6056aab398e8039f6b9720d6a83b4e46"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB30H_CM4_SWO</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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<tr class="separator:a6056aab398e8039f6b9720d6a83b4e46"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a06b1c46c23ceeee462fac8d5d2ca343b"><td class="memItemLeft" align="right" valign="top"><a id="a06b1c46c23ceeee462fac8d5d2ca343b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB30H_CM4_SWO</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a3a8561e0a90e065dd61d350761cd1eaf">PIN_PB30H_CM4_SWO</a> << 16) | MUX_PB30H_CM4_SWO)</td></tr>
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<tr class="separator:a06b1c46c23ceeee462fac8d5d2ca343b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a42e3ce523838f9185778cf67a551f7a1"><td class="memItemLeft" align="right" valign="top"><a id="a42e3ce523838f9185778cf67a551f7a1"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB30H_CM4_SWO</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 30)</td></tr>
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<tr class="separator:a42e3ce523838f9185778cf67a551f7a1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa1ca59541b63748b4fbcc23bd1224e71"><td class="memItemLeft" align="right" valign="top"><a id="aa1ca59541b63748b4fbcc23bd1224e71"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa1ca59541b63748b4fbcc23bd1224e71">PIN_PC27H_CM4_TRACECLK</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(91)</td></tr>
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||
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<tr class="memdesc:aa1ca59541b63748b4fbcc23bd1224e71"><td class="mdescLeft"> </td><td class="mdescRight">CM4 signal: TRACECLK on PC27 mux H. <br /></td></tr>
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<tr class="separator:aa1ca59541b63748b4fbcc23bd1224e71"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6d33d9e10a4e7090cb56a7aa48e1869b"><td class="memItemLeft" align="right" valign="top"><a id="a6d33d9e10a4e7090cb56a7aa48e1869b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC27H_CM4_TRACECLK</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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<tr class="separator:a6d33d9e10a4e7090cb56a7aa48e1869b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3114cf3f1fa91a70079ed30453b2f9a4"><td class="memItemLeft" align="right" valign="top"><a id="a3114cf3f1fa91a70079ed30453b2f9a4"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC27H_CM4_TRACECLK</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aa1ca59541b63748b4fbcc23bd1224e71">PIN_PC27H_CM4_TRACECLK</a> << 16) | MUX_PC27H_CM4_TRACECLK)</td></tr>
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<tr class="separator:a3114cf3f1fa91a70079ed30453b2f9a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab4f43087c696c9ebd201ad79901dc3eb"><td class="memItemLeft" align="right" valign="top"><a id="ab4f43087c696c9ebd201ad79901dc3eb"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC27H_CM4_TRACECLK</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 27)</td></tr>
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||
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<tr class="separator:ab4f43087c696c9ebd201ad79901dc3eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae01143cd9657810e8f27788a0c5df0c3"><td class="memItemLeft" align="right" valign="top"><a id="ae01143cd9657810e8f27788a0c5df0c3"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae01143cd9657810e8f27788a0c5df0c3">PIN_PC28H_CM4_TRACEDATA0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(92)</td></tr>
|
||
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<tr class="memdesc:ae01143cd9657810e8f27788a0c5df0c3"><td class="mdescLeft"> </td><td class="mdescRight">CM4 signal: TRACEDATA0 on PC28 mux H. <br /></td></tr>
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||
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<tr class="separator:ae01143cd9657810e8f27788a0c5df0c3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adc5ec3c4d39d1f533fd616ff6e2f6ad0"><td class="memItemLeft" align="right" valign="top"><a id="adc5ec3c4d39d1f533fd616ff6e2f6ad0"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC28H_CM4_TRACEDATA0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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||
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<tr class="separator:adc5ec3c4d39d1f533fd616ff6e2f6ad0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a98ba8aae000fc6d6e095d6d05b7c1703"><td class="memItemLeft" align="right" valign="top"><a id="a98ba8aae000fc6d6e095d6d05b7c1703"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC28H_CM4_TRACEDATA0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ae01143cd9657810e8f27788a0c5df0c3">PIN_PC28H_CM4_TRACEDATA0</a> << 16) | MUX_PC28H_CM4_TRACEDATA0)</td></tr>
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<tr class="separator:a98ba8aae000fc6d6e095d6d05b7c1703"><td class="memSeparator" colspan="2"> </td></tr>
|
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<tr class="memitem:a400b3789bb9f74489ae913db3a34cf53"><td class="memItemLeft" align="right" valign="top"><a id="a400b3789bb9f74489ae913db3a34cf53"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC28H_CM4_TRACEDATA0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 28)</td></tr>
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||
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<tr class="separator:a400b3789bb9f74489ae913db3a34cf53"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3adc9d84ffc839f073d5e8e8b8670060"><td class="memItemLeft" align="right" valign="top"><a id="a3adc9d84ffc839f073d5e8e8b8670060"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3adc9d84ffc839f073d5e8e8b8670060">PIN_PC26H_CM4_TRACEDATA1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(90)</td></tr>
|
||
|
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<tr class="memdesc:a3adc9d84ffc839f073d5e8e8b8670060"><td class="mdescLeft"> </td><td class="mdescRight">CM4 signal: TRACEDATA1 on PC26 mux H. <br /></td></tr>
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<tr class="separator:a3adc9d84ffc839f073d5e8e8b8670060"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9dc7dcbc77e8e5c9afa6c735eb564004"><td class="memItemLeft" align="right" valign="top"><a id="a9dc7dcbc77e8e5c9afa6c735eb564004"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC26H_CM4_TRACEDATA1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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||
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<tr class="separator:a9dc7dcbc77e8e5c9afa6c735eb564004"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aaf6d292d5d0477ed110c1e78b82a008d"><td class="memItemLeft" align="right" valign="top"><a id="aaf6d292d5d0477ed110c1e78b82a008d"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC26H_CM4_TRACEDATA1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a3adc9d84ffc839f073d5e8e8b8670060">PIN_PC26H_CM4_TRACEDATA1</a> << 16) | MUX_PC26H_CM4_TRACEDATA1)</td></tr>
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<tr class="separator:aaf6d292d5d0477ed110c1e78b82a008d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7c459e55aa7cd4afe525904bfb88f269"><td class="memItemLeft" align="right" valign="top"><a id="a7c459e55aa7cd4afe525904bfb88f269"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC26H_CM4_TRACEDATA1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 26)</td></tr>
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||
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<tr class="separator:a7c459e55aa7cd4afe525904bfb88f269"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae7aa796f50af9fcf9fd32a26580011d8"><td class="memItemLeft" align="right" valign="top"><a id="ae7aa796f50af9fcf9fd32a26580011d8"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae7aa796f50af9fcf9fd32a26580011d8">PIN_PC25H_CM4_TRACEDATA2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(89)</td></tr>
|
||
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<tr class="memdesc:ae7aa796f50af9fcf9fd32a26580011d8"><td class="mdescLeft"> </td><td class="mdescRight">CM4 signal: TRACEDATA2 on PC25 mux H. <br /></td></tr>
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<tr class="separator:ae7aa796f50af9fcf9fd32a26580011d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af9766f76594af91648cb05fb244a0697"><td class="memItemLeft" align="right" valign="top"><a id="af9766f76594af91648cb05fb244a0697"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC25H_CM4_TRACEDATA2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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||
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<tr class="separator:af9766f76594af91648cb05fb244a0697"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a51e13fb7b730a069891f7c226b90d040"><td class="memItemLeft" align="right" valign="top"><a id="a51e13fb7b730a069891f7c226b90d040"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC25H_CM4_TRACEDATA2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ae7aa796f50af9fcf9fd32a26580011d8">PIN_PC25H_CM4_TRACEDATA2</a> << 16) | MUX_PC25H_CM4_TRACEDATA2)</td></tr>
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<tr class="separator:a51e13fb7b730a069891f7c226b90d040"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a039ede21e9f869e5ae1ffbb141797497"><td class="memItemLeft" align="right" valign="top"><a id="a039ede21e9f869e5ae1ffbb141797497"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC25H_CM4_TRACEDATA2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 25)</td></tr>
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||
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<tr class="separator:a039ede21e9f869e5ae1ffbb141797497"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a915cf57cd29849d3110a2251e203c99d"><td class="memItemLeft" align="right" valign="top"><a id="a915cf57cd29849d3110a2251e203c99d"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a915cf57cd29849d3110a2251e203c99d">PIN_PC24H_CM4_TRACEDATA3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(88)</td></tr>
|
||
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<tr class="memdesc:a915cf57cd29849d3110a2251e203c99d"><td class="mdescLeft"> </td><td class="mdescRight">CM4 signal: TRACEDATA3 on PC24 mux H. <br /></td></tr>
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||
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<tr class="separator:a915cf57cd29849d3110a2251e203c99d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad1dcc24e77c1af0f08aa5d6942c1b487"><td class="memItemLeft" align="right" valign="top"><a id="ad1dcc24e77c1af0f08aa5d6942c1b487"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC24H_CM4_TRACEDATA3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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||
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<tr class="separator:ad1dcc24e77c1af0f08aa5d6942c1b487"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a5f556c8675272b5dfc3829eef9aaff68"><td class="memItemLeft" align="right" valign="top"><a id="a5f556c8675272b5dfc3829eef9aaff68"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC24H_CM4_TRACEDATA3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a915cf57cd29849d3110a2251e203c99d">PIN_PC24H_CM4_TRACEDATA3</a> << 16) | MUX_PC24H_CM4_TRACEDATA3)</td></tr>
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<tr class="separator:a5f556c8675272b5dfc3829eef9aaff68"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af89bd9f887b56b0e8328fdc3b428e28e"><td class="memItemLeft" align="right" valign="top"><a id="af89bd9f887b56b0e8328fdc3b428e28e"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC24H_CM4_TRACEDATA3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 24)</td></tr>
|
||
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<tr class="separator:af89bd9f887b56b0e8328fdc3b428e28e"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a762acdd8b05ad3c153f614b1f2ea9ca9"><td class="memItemLeft" align="right" valign="top"><a id="a762acdd8b05ad3c153f614b1f2ea9ca9"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a762acdd8b05ad3c153f614b1f2ea9ca9">PIN_PA03B_ANAREF_VREF0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
|
||
|
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<tr class="memdesc:a762acdd8b05ad3c153f614b1f2ea9ca9"><td class="mdescLeft"> </td><td class="mdescRight">ANAREF signal: VREF0 on PA03 mux B. <br /></td></tr>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA03B_ANAREF_VREF0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="memitem:a7ff8b6b73b61d826351573c363e00120"><td class="memItemLeft" align="right" valign="top"><a id="a7ff8b6b73b61d826351573c363e00120"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA03B_ANAREF_VREF0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a762acdd8b05ad3c153f614b1f2ea9ca9">PIN_PA03B_ANAREF_VREF0</a> << 16) | MUX_PA03B_ANAREF_VREF0)</td></tr>
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<tr class="memitem:aa3d70365134a8a5b8c16b2c9025f5ee7"><td class="memItemLeft" align="right" valign="top"><a id="aa3d70365134a8a5b8c16b2c9025f5ee7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA03B_ANAREF_VREF0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 3)</td></tr>
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<tr class="memitem:a45b296ef4b8ce5a77d37fe26b1c6d517"><td class="memItemLeft" align="right" valign="top"><a id="a45b296ef4b8ce5a77d37fe26b1c6d517"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a45b296ef4b8ce5a77d37fe26b1c6d517">PIN_PA04B_ANAREF_VREF1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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<tr class="memdesc:a45b296ef4b8ce5a77d37fe26b1c6d517"><td class="mdescLeft"> </td><td class="mdescRight">ANAREF signal: VREF1 on PA04 mux B. <br /></td></tr>
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<tr class="memitem:a5379104c62481b23015d01471bc9bcde"><td class="memItemLeft" align="right" valign="top"><a id="a5379104c62481b23015d01471bc9bcde"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA04B_ANAREF_VREF1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="memitem:aa1a94b2a4889f78731d18d5f1c29c43d"><td class="memItemLeft" align="right" valign="top"><a id="aa1a94b2a4889f78731d18d5f1c29c43d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA04B_ANAREF_VREF1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a45b296ef4b8ce5a77d37fe26b1c6d517">PIN_PA04B_ANAREF_VREF1</a> << 16) | MUX_PA04B_ANAREF_VREF1)</td></tr>
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<tr class="memitem:ab7e2a048e44860b1ba92cfc894c83da2"><td class="memItemLeft" align="right" valign="top"><a id="ab7e2a048e44860b1ba92cfc894c83da2"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA04B_ANAREF_VREF1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 4)</td></tr>
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<tr class="memitem:aae159b86068948394d159978d9026b73"><td class="memItemLeft" align="right" valign="top"><a id="aae159b86068948394d159978d9026b73"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aae159b86068948394d159978d9026b73">PIN_PA06B_ANAREF_VREF2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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<tr class="memdesc:aae159b86068948394d159978d9026b73"><td class="mdescLeft"> </td><td class="mdescRight">ANAREF signal: VREF2 on PA06 mux B. <br /></td></tr>
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<tr class="memitem:a7a788b1e4c62409abc4737eadfc40151"><td class="memItemLeft" align="right" valign="top"><a id="a7a788b1e4c62409abc4737eadfc40151"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA06B_ANAREF_VREF2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="memitem:a9a300313c49fcbf17f4d8cb040619e52"><td class="memItemLeft" align="right" valign="top"><a id="a9a300313c49fcbf17f4d8cb040619e52"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA06B_ANAREF_VREF2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aae159b86068948394d159978d9026b73">PIN_PA06B_ANAREF_VREF2</a> << 16) | MUX_PA06B_ANAREF_VREF2)</td></tr>
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<tr class="memitem:a7aa2e05e0fc4b2a95db46ff3661b2f34"><td class="memItemLeft" align="right" valign="top"><a id="a7aa2e05e0fc4b2a95db46ff3661b2f34"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA06B_ANAREF_VREF2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 6)</td></tr>
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<tr class="memitem:ab9a874d00e015ca69f9a1a21e0a0620a"><td class="memItemLeft" align="right" valign="top"><a id="ab9a874d00e015ca69f9a1a21e0a0620a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab9a874d00e015ca69f9a1a21e0a0620a">PIN_PA30M_GCLK_IO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(30)</td></tr>
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<tr class="memdesc:ab9a874d00e015ca69f9a1a21e0a0620a"><td class="mdescLeft"> </td><td class="mdescRight">GCLK signal: IO0 on PA30 mux M. <br /></td></tr>
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<tr class="memitem:a9b16e21fec65c5c532626ba471718aac"><td class="memItemLeft" align="right" valign="top"><a id="a9b16e21fec65c5c532626ba471718aac"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA30M_GCLK_IO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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<tr class="memitem:a8881b2fe2ef6e63680e66def28c22f3d"><td class="memItemLeft" align="right" valign="top"><a id="a8881b2fe2ef6e63680e66def28c22f3d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA30M_GCLK_IO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ab9a874d00e015ca69f9a1a21e0a0620a">PIN_PA30M_GCLK_IO0</a> << 16) | MUX_PA30M_GCLK_IO0)</td></tr>
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<tr class="memitem:a7f57a6ab65d9050b820ad55b536031e2"><td class="memItemLeft" align="right" valign="top"><a id="a7f57a6ab65d9050b820ad55b536031e2"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA30M_GCLK_IO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 30)</td></tr>
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<tr class="memitem:a1e5d68018ee6a759db41160940c972df"><td class="memItemLeft" align="right" valign="top"><a id="a1e5d68018ee6a759db41160940c972df"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1e5d68018ee6a759db41160940c972df">PIN_PB14M_GCLK_IO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(46)</td></tr>
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<tr class="memdesc:a1e5d68018ee6a759db41160940c972df"><td class="mdescLeft"> </td><td class="mdescRight">GCLK signal: IO0 on PB14 mux M. <br /></td></tr>
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<tr class="memitem:a4197b5763add230da4cb3e8482107d4c"><td class="memItemLeft" align="right" valign="top"><a id="a4197b5763add230da4cb3e8482107d4c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB14M_GCLK_IO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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<tr class="memitem:ad57066a441a3a125d81af5f188b86def"><td class="memItemLeft" align="right" valign="top"><a id="ad57066a441a3a125d81af5f188b86def"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB14M_GCLK_IO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a1e5d68018ee6a759db41160940c972df">PIN_PB14M_GCLK_IO0</a> << 16) | MUX_PB14M_GCLK_IO0)</td></tr>
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<tr class="memitem:a1cde9d2f07e7537a22bd2e33a14d6665"><td class="memItemLeft" align="right" valign="top"><a id="a1cde9d2f07e7537a22bd2e33a14d6665"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB14M_GCLK_IO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 14)</td></tr>
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<tr class="separator:a1cde9d2f07e7537a22bd2e33a14d6665"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac696ca40352e783026f12d10d5e0e519"><td class="memItemLeft" align="right" valign="top"><a id="ac696ca40352e783026f12d10d5e0e519"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac696ca40352e783026f12d10d5e0e519">PIN_PA14M_GCLK_IO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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<tr class="memdesc:ac696ca40352e783026f12d10d5e0e519"><td class="mdescLeft"> </td><td class="mdescRight">GCLK signal: IO0 on PA14 mux M. <br /></td></tr>
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<tr class="separator:ac696ca40352e783026f12d10d5e0e519"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad416e834c76acdc734ebb9756b3a65e9"><td class="memItemLeft" align="right" valign="top"><a id="ad416e834c76acdc734ebb9756b3a65e9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA14M_GCLK_IO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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<tr class="separator:ad416e834c76acdc734ebb9756b3a65e9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a78d15b5492af0dc7f267fa5b781754bf"><td class="memItemLeft" align="right" valign="top"><a id="a78d15b5492af0dc7f267fa5b781754bf"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA14M_GCLK_IO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ac696ca40352e783026f12d10d5e0e519">PIN_PA14M_GCLK_IO0</a> << 16) | MUX_PA14M_GCLK_IO0)</td></tr>
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<tr class="memitem:ac8de072e36d7025064c64ed8d6599271"><td class="memItemLeft" align="right" valign="top"><a id="ac8de072e36d7025064c64ed8d6599271"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA14M_GCLK_IO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 14)</td></tr>
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<tr class="separator:ac8de072e36d7025064c64ed8d6599271"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5b559a0afd7254c03927b5373902d1e8"><td class="memItemLeft" align="right" valign="top"><a id="a5b559a0afd7254c03927b5373902d1e8"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5b559a0afd7254c03927b5373902d1e8">PIN_PB22M_GCLK_IO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(54)</td></tr>
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<tr class="memdesc:a5b559a0afd7254c03927b5373902d1e8"><td class="mdescLeft"> </td><td class="mdescRight">GCLK signal: IO0 on PB22 mux M. <br /></td></tr>
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<tr class="separator:a5b559a0afd7254c03927b5373902d1e8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8e7f052f1b12ce395f44d975ce9f47d7"><td class="memItemLeft" align="right" valign="top"><a id="a8e7f052f1b12ce395f44d975ce9f47d7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB22M_GCLK_IO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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<tr class="separator:a8e7f052f1b12ce395f44d975ce9f47d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adbfa280e1dd2b57a9679a2c34c1b33ed"><td class="memItemLeft" align="right" valign="top"><a id="adbfa280e1dd2b57a9679a2c34c1b33ed"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB22M_GCLK_IO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a5b559a0afd7254c03927b5373902d1e8">PIN_PB22M_GCLK_IO0</a> << 16) | MUX_PB22M_GCLK_IO0)</td></tr>
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<tr class="separator:adbfa280e1dd2b57a9679a2c34c1b33ed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3960eab52d7db4aaebbf4a0e31907e0d"><td class="memItemLeft" align="right" valign="top"><a id="a3960eab52d7db4aaebbf4a0e31907e0d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB22M_GCLK_IO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 22)</td></tr>
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<tr class="separator:a3960eab52d7db4aaebbf4a0e31907e0d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4a63ef1b82dfcb6701b8ffe412264a22"><td class="memItemLeft" align="right" valign="top"><a id="a4a63ef1b82dfcb6701b8ffe412264a22"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4a63ef1b82dfcb6701b8ffe412264a22">PIN_PB15M_GCLK_IO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(47)</td></tr>
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<tr class="memdesc:a4a63ef1b82dfcb6701b8ffe412264a22"><td class="mdescLeft"> </td><td class="mdescRight">GCLK signal: IO1 on PB15 mux M. <br /></td></tr>
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<tr class="separator:a4a63ef1b82dfcb6701b8ffe412264a22"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae405929c93db4ffa5c7781f1bbbb78b9"><td class="memItemLeft" align="right" valign="top"><a id="ae405929c93db4ffa5c7781f1bbbb78b9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB15M_GCLK_IO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB15M_GCLK_IO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a4a63ef1b82dfcb6701b8ffe412264a22">PIN_PB15M_GCLK_IO1</a> << 16) | MUX_PB15M_GCLK_IO1)</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB15M_GCLK_IO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 15)</td></tr>
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<tr class="memitem:a6e20628fc876d9117bf503d6eaa942a1"><td class="memItemLeft" align="right" valign="top"><a id="a6e20628fc876d9117bf503d6eaa942a1"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6e20628fc876d9117bf503d6eaa942a1">PIN_PA15M_GCLK_IO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(15)</td></tr>
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<tr class="memdesc:a6e20628fc876d9117bf503d6eaa942a1"><td class="mdescLeft"> </td><td class="mdescRight">GCLK signal: IO1 on PA15 mux M. <br /></td></tr>
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<tr class="memitem:ab71d8c24da49cd2ba8c6c575368dd481"><td class="memItemLeft" align="right" valign="top"><a id="ab71d8c24da49cd2ba8c6c575368dd481"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA15M_GCLK_IO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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<tr class="memitem:a3f9ec1664fa2f9342c1cd05c97115b85"><td class="memItemLeft" align="right" valign="top"><a id="a3f9ec1664fa2f9342c1cd05c97115b85"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA15M_GCLK_IO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a6e20628fc876d9117bf503d6eaa942a1">PIN_PA15M_GCLK_IO1</a> << 16) | MUX_PA15M_GCLK_IO1)</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA15M_GCLK_IO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 15)</td></tr>
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<tr class="memitem:adc21f08982588ae0cd26d31112a9afb6"><td class="memItemLeft" align="right" valign="top"><a id="adc21f08982588ae0cd26d31112a9afb6"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#adc21f08982588ae0cd26d31112a9afb6">PIN_PB23M_GCLK_IO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(55)</td></tr>
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<tr class="memdesc:adc21f08982588ae0cd26d31112a9afb6"><td class="mdescLeft"> </td><td class="mdescRight">GCLK signal: IO1 on PB23 mux M. <br /></td></tr>
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<tr class="memitem:a87e3080d430383bc639b8ef718d68f8b"><td class="memItemLeft" align="right" valign="top"><a id="a87e3080d430383bc639b8ef718d68f8b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB23M_GCLK_IO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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<tr class="memitem:aaa9f3eee6e92855b989b9a03f2a14b4f"><td class="memItemLeft" align="right" valign="top"><a id="aaa9f3eee6e92855b989b9a03f2a14b4f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB23M_GCLK_IO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#adc21f08982588ae0cd26d31112a9afb6">PIN_PB23M_GCLK_IO1</a> << 16) | MUX_PB23M_GCLK_IO1)</td></tr>
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<tr class="memitem:a97858462665a4c98f7abbe5d8cc85627"><td class="memItemLeft" align="right" valign="top"><a id="a97858462665a4c98f7abbe5d8cc85627"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB23M_GCLK_IO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 23)</td></tr>
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<tr class="memitem:ad00930c9669ccac44b6079fae3d367a5"><td class="memItemLeft" align="right" valign="top"><a id="ad00930c9669ccac44b6079fae3d367a5"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad00930c9669ccac44b6079fae3d367a5">PIN_PA27M_GCLK_IO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(27)</td></tr>
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<tr class="memdesc:ad00930c9669ccac44b6079fae3d367a5"><td class="mdescLeft"> </td><td class="mdescRight">GCLK signal: IO1 on PA27 mux M. <br /></td></tr>
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<tr class="memitem:a2892fd9e619242841df5e34360850ca6"><td class="memItemLeft" align="right" valign="top"><a id="a2892fd9e619242841df5e34360850ca6"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA27M_GCLK_IO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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<tr class="memitem:a7abc69485b0735e51f412f5a9cc7f269"><td class="memItemLeft" align="right" valign="top"><a id="a7abc69485b0735e51f412f5a9cc7f269"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA27M_GCLK_IO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ad00930c9669ccac44b6079fae3d367a5">PIN_PA27M_GCLK_IO1</a> << 16) | MUX_PA27M_GCLK_IO1)</td></tr>
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<tr class="memitem:af145b95ae928f0a0a3e66e646b04af60"><td class="memItemLeft" align="right" valign="top"><a id="af145b95ae928f0a0a3e66e646b04af60"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA27M_GCLK_IO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 27)</td></tr>
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<tr class="separator:af145b95ae928f0a0a3e66e646b04af60"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a457dc2d8c6bd8fc1cc7c6c0729537699"><td class="memItemLeft" align="right" valign="top"><a id="a457dc2d8c6bd8fc1cc7c6c0729537699"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a457dc2d8c6bd8fc1cc7c6c0729537699">PIN_PA16M_GCLK_IO2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(16)</td></tr>
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<tr class="memdesc:a457dc2d8c6bd8fc1cc7c6c0729537699"><td class="mdescLeft"> </td><td class="mdescRight">GCLK signal: IO2 on PA16 mux M. <br /></td></tr>
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<tr class="memitem:abe3628a33d2365ac03f50985d0fedecd"><td class="memItemLeft" align="right" valign="top"><a id="abe3628a33d2365ac03f50985d0fedecd"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA16M_GCLK_IO2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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<tr class="memitem:a53fa066eee8c8b5587144b3e5760a71f"><td class="memItemLeft" align="right" valign="top"><a id="a53fa066eee8c8b5587144b3e5760a71f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA16M_GCLK_IO2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a457dc2d8c6bd8fc1cc7c6c0729537699">PIN_PA16M_GCLK_IO2</a> << 16) | MUX_PA16M_GCLK_IO2)</td></tr>
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<tr class="memitem:aa29c6c597563578fb5594e6fb1113cba"><td class="memItemLeft" align="right" valign="top"><a id="aa29c6c597563578fb5594e6fb1113cba"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA16M_GCLK_IO2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 16)</td></tr>
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<tr class="separator:aa29c6c597563578fb5594e6fb1113cba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2753ed51490a54b091736203342d418e"><td class="memItemLeft" align="right" valign="top"><a id="a2753ed51490a54b091736203342d418e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2753ed51490a54b091736203342d418e">PIN_PB16M_GCLK_IO2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(48)</td></tr>
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<tr class="memdesc:a2753ed51490a54b091736203342d418e"><td class="mdescLeft"> </td><td class="mdescRight">GCLK signal: IO2 on PB16 mux M. <br /></td></tr>
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<tr class="separator:a2753ed51490a54b091736203342d418e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abad6c31c8ad3aa4fb4a7a92224715085"><td class="memItemLeft" align="right" valign="top"><a id="abad6c31c8ad3aa4fb4a7a92224715085"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB16M_GCLK_IO2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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<tr class="separator:abad6c31c8ad3aa4fb4a7a92224715085"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2c9e62892e6128f64d17f7510178227a"><td class="memItemLeft" align="right" valign="top"><a id="a2c9e62892e6128f64d17f7510178227a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB16M_GCLK_IO2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a2753ed51490a54b091736203342d418e">PIN_PB16M_GCLK_IO2</a> << 16) | MUX_PB16M_GCLK_IO2)</td></tr>
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<tr class="memitem:a02edbf1c6371daef4f4fb5a25602bee3"><td class="memItemLeft" align="right" valign="top"><a id="a02edbf1c6371daef4f4fb5a25602bee3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB16M_GCLK_IO2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 16)</td></tr>
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<tr class="separator:a02edbf1c6371daef4f4fb5a25602bee3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8d867fb31bb6b5bc4decdf980784c5b1"><td class="memItemLeft" align="right" valign="top"><a id="a8d867fb31bb6b5bc4decdf980784c5b1"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8d867fb31bb6b5bc4decdf980784c5b1">PIN_PA17M_GCLK_IO3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(17)</td></tr>
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<tr class="memdesc:a8d867fb31bb6b5bc4decdf980784c5b1"><td class="mdescLeft"> </td><td class="mdescRight">GCLK signal: IO3 on PA17 mux M. <br /></td></tr>
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<tr class="separator:a8d867fb31bb6b5bc4decdf980784c5b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac8d813a1536aae637c46c14080e8704a"><td class="memItemLeft" align="right" valign="top"><a id="ac8d813a1536aae637c46c14080e8704a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA17M_GCLK_IO3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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<tr class="separator:ac8d813a1536aae637c46c14080e8704a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3befc3ce46b97618ec2923a3ca93680b"><td class="memItemLeft" align="right" valign="top"><a id="a3befc3ce46b97618ec2923a3ca93680b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA17M_GCLK_IO3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a8d867fb31bb6b5bc4decdf980784c5b1">PIN_PA17M_GCLK_IO3</a> << 16) | MUX_PA17M_GCLK_IO3)</td></tr>
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<tr class="separator:a3befc3ce46b97618ec2923a3ca93680b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a69db2d9109089fa2bb440cd92b4ca989"><td class="memItemLeft" align="right" valign="top"><a id="a69db2d9109089fa2bb440cd92b4ca989"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA17M_GCLK_IO3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 17)</td></tr>
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<tr class="separator:a69db2d9109089fa2bb440cd92b4ca989"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3894cd80572f34d2fc8d2efc36a713a5"><td class="memItemLeft" align="right" valign="top"><a id="a3894cd80572f34d2fc8d2efc36a713a5"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3894cd80572f34d2fc8d2efc36a713a5">PIN_PB17M_GCLK_IO3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(49)</td></tr>
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<tr class="memdesc:a3894cd80572f34d2fc8d2efc36a713a5"><td class="mdescLeft"> </td><td class="mdescRight">GCLK signal: IO3 on PB17 mux M. <br /></td></tr>
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<tr class="separator:a3894cd80572f34d2fc8d2efc36a713a5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a27999a2be79ceeda0ad02291dd5b8d51"><td class="memItemLeft" align="right" valign="top"><a id="a27999a2be79ceeda0ad02291dd5b8d51"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB17M_GCLK_IO3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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<tr class="separator:a27999a2be79ceeda0ad02291dd5b8d51"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a854410fb532c19ea24f22ad396e82e36"><td class="memItemLeft" align="right" valign="top"><a id="a854410fb532c19ea24f22ad396e82e36"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB17M_GCLK_IO3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a3894cd80572f34d2fc8d2efc36a713a5">PIN_PB17M_GCLK_IO3</a> << 16) | MUX_PB17M_GCLK_IO3)</td></tr>
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<tr class="memitem:a673506669e6db7ebfd15fa6871046378"><td class="memItemLeft" align="right" valign="top"><a id="a673506669e6db7ebfd15fa6871046378"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB17M_GCLK_IO3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 17)</td></tr>
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<tr class="memitem:aee4918311027732854180cbdf54c2d8e"><td class="memItemLeft" align="right" valign="top"><a id="aee4918311027732854180cbdf54c2d8e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aee4918311027732854180cbdf54c2d8e">PIN_PA10M_GCLK_IO4</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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<tr class="memdesc:aee4918311027732854180cbdf54c2d8e"><td class="mdescLeft"> </td><td class="mdescRight">GCLK signal: IO4 on PA10 mux M. <br /></td></tr>
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<tr class="memitem:a71874db468485659bdfc6b8abe022519"><td class="memItemLeft" align="right" valign="top"><a id="a71874db468485659bdfc6b8abe022519"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA10M_GCLK_IO4</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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<tr class="memitem:afd3febe5357b6209d04592fa0adc7fb9"><td class="memItemLeft" align="right" valign="top"><a id="afd3febe5357b6209d04592fa0adc7fb9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA10M_GCLK_IO4</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aee4918311027732854180cbdf54c2d8e">PIN_PA10M_GCLK_IO4</a> << 16) | MUX_PA10M_GCLK_IO4)</td></tr>
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<tr class="memitem:abe2040c3ddbb4ab59d797054e4aacfb1"><td class="memItemLeft" align="right" valign="top"><a id="abe2040c3ddbb4ab59d797054e4aacfb1"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA10M_GCLK_IO4</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 10)</td></tr>
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<tr class="separator:abe2040c3ddbb4ab59d797054e4aacfb1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a88cb37ac0bd1a5c7723311306be5e642"><td class="memItemLeft" align="right" valign="top"><a id="a88cb37ac0bd1a5c7723311306be5e642"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a88cb37ac0bd1a5c7723311306be5e642">PIN_PB10M_GCLK_IO4</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(42)</td></tr>
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<tr class="memdesc:a88cb37ac0bd1a5c7723311306be5e642"><td class="mdescLeft"> </td><td class="mdescRight">GCLK signal: IO4 on PB10 mux M. <br /></td></tr>
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<tr class="memitem:a1f51d18d8e0a09fb06ce331e76badce0"><td class="memItemLeft" align="right" valign="top"><a id="a1f51d18d8e0a09fb06ce331e76badce0"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB10M_GCLK_IO4</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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<tr class="separator:a1f51d18d8e0a09fb06ce331e76badce0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a26e77eb2233ffd0fb585b51d3fb53b71"><td class="memItemLeft" align="right" valign="top"><a id="a26e77eb2233ffd0fb585b51d3fb53b71"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB10M_GCLK_IO4</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a88cb37ac0bd1a5c7723311306be5e642">PIN_PB10M_GCLK_IO4</a> << 16) | MUX_PB10M_GCLK_IO4)</td></tr>
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<tr class="memitem:adca40eb5b531de66ce8905c2e401d9bf"><td class="memItemLeft" align="right" valign="top"><a id="adca40eb5b531de66ce8905c2e401d9bf"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB10M_GCLK_IO4</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 10)</td></tr>
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<tr class="separator:adca40eb5b531de66ce8905c2e401d9bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4ad767bc21897dddf65164822d66481a"><td class="memItemLeft" align="right" valign="top"><a id="a4ad767bc21897dddf65164822d66481a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4ad767bc21897dddf65164822d66481a">PIN_PB18M_GCLK_IO4</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(50)</td></tr>
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<tr class="memdesc:a4ad767bc21897dddf65164822d66481a"><td class="mdescLeft"> </td><td class="mdescRight">GCLK signal: IO4 on PB18 mux M. <br /></td></tr>
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<tr class="separator:a4ad767bc21897dddf65164822d66481a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af28196e2fcf12b040004ab7474a4f811"><td class="memItemLeft" align="right" valign="top"><a id="af28196e2fcf12b040004ab7474a4f811"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB18M_GCLK_IO4</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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<tr class="separator:af28196e2fcf12b040004ab7474a4f811"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2bf595cbd01ae70f8e4ec3fc3b59bcc3"><td class="memItemLeft" align="right" valign="top"><a id="a2bf595cbd01ae70f8e4ec3fc3b59bcc3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB18M_GCLK_IO4</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a4ad767bc21897dddf65164822d66481a">PIN_PB18M_GCLK_IO4</a> << 16) | MUX_PB18M_GCLK_IO4)</td></tr>
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<tr class="separator:a2bf595cbd01ae70f8e4ec3fc3b59bcc3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a110e6c82275e385bc3aea9cd0d6586e4"><td class="memItemLeft" align="right" valign="top"><a id="a110e6c82275e385bc3aea9cd0d6586e4"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB18M_GCLK_IO4</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 18)</td></tr>
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<tr class="separator:a110e6c82275e385bc3aea9cd0d6586e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a37854bd98ef7819fa2b03209a7aad89c"><td class="memItemLeft" align="right" valign="top"><a id="a37854bd98ef7819fa2b03209a7aad89c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a37854bd98ef7819fa2b03209a7aad89c">PIN_PA11M_GCLK_IO5</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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<tr class="memdesc:a37854bd98ef7819fa2b03209a7aad89c"><td class="mdescLeft"> </td><td class="mdescRight">GCLK signal: IO5 on PA11 mux M. <br /></td></tr>
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<tr class="separator:a37854bd98ef7819fa2b03209a7aad89c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a063afcdd44e13c283b1afddd87dbc9c8"><td class="memItemLeft" align="right" valign="top"><a id="a063afcdd44e13c283b1afddd87dbc9c8"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA11M_GCLK_IO5</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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<tr class="separator:a063afcdd44e13c283b1afddd87dbc9c8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6518bdaaf6bd9dbc73252cd10b77bedb"><td class="memItemLeft" align="right" valign="top"><a id="a6518bdaaf6bd9dbc73252cd10b77bedb"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA11M_GCLK_IO5</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a37854bd98ef7819fa2b03209a7aad89c">PIN_PA11M_GCLK_IO5</a> << 16) | MUX_PA11M_GCLK_IO5)</td></tr>
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<tr class="separator:a6518bdaaf6bd9dbc73252cd10b77bedb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aaed91b35338780db575573513bce3818"><td class="memItemLeft" align="right" valign="top"><a id="aaed91b35338780db575573513bce3818"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA11M_GCLK_IO5</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 11)</td></tr>
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<tr class="separator:aaed91b35338780db575573513bce3818"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a35918243c25bab659d09ffa49b4c9405"><td class="memItemLeft" align="right" valign="top"><a id="a35918243c25bab659d09ffa49b4c9405"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a35918243c25bab659d09ffa49b4c9405">PIN_PB11M_GCLK_IO5</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(43)</td></tr>
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<tr class="memdesc:a35918243c25bab659d09ffa49b4c9405"><td class="mdescLeft"> </td><td class="mdescRight">GCLK signal: IO5 on PB11 mux M. <br /></td></tr>
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<tr class="separator:a35918243c25bab659d09ffa49b4c9405"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3825f3ed62f7cd7bd9c48794427fbb41"><td class="memItemLeft" align="right" valign="top"><a id="a3825f3ed62f7cd7bd9c48794427fbb41"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB11M_GCLK_IO5</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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<tr class="separator:a3825f3ed62f7cd7bd9c48794427fbb41"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa8561782c9483b119c881fb0ed356e1d"><td class="memItemLeft" align="right" valign="top"><a id="aa8561782c9483b119c881fb0ed356e1d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB11M_GCLK_IO5</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a35918243c25bab659d09ffa49b4c9405">PIN_PB11M_GCLK_IO5</a> << 16) | MUX_PB11M_GCLK_IO5)</td></tr>
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<tr class="separator:aa8561782c9483b119c881fb0ed356e1d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1aed8129cafa99f5f17ffe9d7b480e13"><td class="memItemLeft" align="right" valign="top"><a id="a1aed8129cafa99f5f17ffe9d7b480e13"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB11M_GCLK_IO5</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 11)</td></tr>
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<tr class="separator:a1aed8129cafa99f5f17ffe9d7b480e13"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aaea9a8b767bdae695a011935e8d39355"><td class="memItemLeft" align="right" valign="top"><a id="aaea9a8b767bdae695a011935e8d39355"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aaea9a8b767bdae695a011935e8d39355">PIN_PB19M_GCLK_IO5</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(51)</td></tr>
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<tr class="memdesc:aaea9a8b767bdae695a011935e8d39355"><td class="mdescLeft"> </td><td class="mdescRight">GCLK signal: IO5 on PB19 mux M. <br /></td></tr>
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<tr class="separator:aaea9a8b767bdae695a011935e8d39355"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a542656d1afd8811b7d5fad725ab7324f"><td class="memItemLeft" align="right" valign="top"><a id="a542656d1afd8811b7d5fad725ab7324f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB19M_GCLK_IO5</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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<tr class="separator:a542656d1afd8811b7d5fad725ab7324f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aab751130b00d056ff53fe63dd0a4ad38"><td class="memItemLeft" align="right" valign="top"><a id="aab751130b00d056ff53fe63dd0a4ad38"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB19M_GCLK_IO5</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aaea9a8b767bdae695a011935e8d39355">PIN_PB19M_GCLK_IO5</a> << 16) | MUX_PB19M_GCLK_IO5)</td></tr>
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<tr class="separator:aab751130b00d056ff53fe63dd0a4ad38"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3672a018e36df4db262fb3aaa57df021"><td class="memItemLeft" align="right" valign="top"><a id="a3672a018e36df4db262fb3aaa57df021"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB19M_GCLK_IO5</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 19)</td></tr>
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<tr class="separator:a3672a018e36df4db262fb3aaa57df021"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a683f912ed6abbaf0791f577933b56d5c"><td class="memItemLeft" align="right" valign="top"><a id="a683f912ed6abbaf0791f577933b56d5c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a683f912ed6abbaf0791f577933b56d5c">PIN_PB12M_GCLK_IO6</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(44)</td></tr>
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<tr class="memdesc:a683f912ed6abbaf0791f577933b56d5c"><td class="mdescLeft"> </td><td class="mdescRight">GCLK signal: IO6 on PB12 mux M. <br /></td></tr>
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<tr class="separator:a683f912ed6abbaf0791f577933b56d5c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1faa3d505d4460309bd30206db0c094a"><td class="memItemLeft" align="right" valign="top"><a id="a1faa3d505d4460309bd30206db0c094a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB12M_GCLK_IO6</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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<tr class="separator:a1faa3d505d4460309bd30206db0c094a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af78cd2a614c457e5bfdd8f66a017c791"><td class="memItemLeft" align="right" valign="top"><a id="af78cd2a614c457e5bfdd8f66a017c791"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB12M_GCLK_IO6</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a683f912ed6abbaf0791f577933b56d5c">PIN_PB12M_GCLK_IO6</a> << 16) | MUX_PB12M_GCLK_IO6)</td></tr>
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<tr class="separator:af78cd2a614c457e5bfdd8f66a017c791"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a67ceeaa9a0c916f6f81c1879e08358fb"><td class="memItemLeft" align="right" valign="top"><a id="a67ceeaa9a0c916f6f81c1879e08358fb"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB12M_GCLK_IO6</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 12)</td></tr>
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<tr class="separator:a67ceeaa9a0c916f6f81c1879e08358fb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a073dada98d20a9c650ad8c7af49137e4"><td class="memItemLeft" align="right" valign="top"><a id="a073dada98d20a9c650ad8c7af49137e4"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a073dada98d20a9c650ad8c7af49137e4">PIN_PB20M_GCLK_IO6</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(52)</td></tr>
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<tr class="memdesc:a073dada98d20a9c650ad8c7af49137e4"><td class="mdescLeft"> </td><td class="mdescRight">GCLK signal: IO6 on PB20 mux M. <br /></td></tr>
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<tr class="memitem:a983c10f8fa1a2c73c010b4899e03eaaa"><td class="memItemLeft" align="right" valign="top"><a id="a983c10f8fa1a2c73c010b4899e03eaaa"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB20M_GCLK_IO6</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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<tr class="separator:a983c10f8fa1a2c73c010b4899e03eaaa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a243b249155024dfaf4fdf2775b3da871"><td class="memItemLeft" align="right" valign="top"><a id="a243b249155024dfaf4fdf2775b3da871"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB20M_GCLK_IO6</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a073dada98d20a9c650ad8c7af49137e4">PIN_PB20M_GCLK_IO6</a> << 16) | MUX_PB20M_GCLK_IO6)</td></tr>
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<tr class="memitem:a59faa523fcb94249eeda1f3402b8b656"><td class="memItemLeft" align="right" valign="top"><a id="a59faa523fcb94249eeda1f3402b8b656"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB20M_GCLK_IO6</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 20)</td></tr>
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<tr class="separator:a59faa523fcb94249eeda1f3402b8b656"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6510bd93510d1d8abfcd8d8abcd64746"><td class="memItemLeft" align="right" valign="top"><a id="a6510bd93510d1d8abfcd8d8abcd64746"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6510bd93510d1d8abfcd8d8abcd64746">PIN_PB13M_GCLK_IO7</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(45)</td></tr>
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<tr class="memdesc:a6510bd93510d1d8abfcd8d8abcd64746"><td class="mdescLeft"> </td><td class="mdescRight">GCLK signal: IO7 on PB13 mux M. <br /></td></tr>
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<tr class="separator:a6510bd93510d1d8abfcd8d8abcd64746"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9f4a8f00c74663895b7bceedaca9c79a"><td class="memItemLeft" align="right" valign="top"><a id="a9f4a8f00c74663895b7bceedaca9c79a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB13M_GCLK_IO7</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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<tr class="separator:a9f4a8f00c74663895b7bceedaca9c79a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acdca26a0f1bf9758e1deaedd60920ce7"><td class="memItemLeft" align="right" valign="top"><a id="acdca26a0f1bf9758e1deaedd60920ce7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB13M_GCLK_IO7</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a6510bd93510d1d8abfcd8d8abcd64746">PIN_PB13M_GCLK_IO7</a> << 16) | MUX_PB13M_GCLK_IO7)</td></tr>
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<tr class="separator:acdca26a0f1bf9758e1deaedd60920ce7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a68daafef40f6e181d844482df7055230"><td class="memItemLeft" align="right" valign="top"><a id="a68daafef40f6e181d844482df7055230"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB13M_GCLK_IO7</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 13)</td></tr>
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<tr class="separator:a68daafef40f6e181d844482df7055230"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1b42da4c72c1e5e4aef2cb417bfa88b1"><td class="memItemLeft" align="right" valign="top"><a id="a1b42da4c72c1e5e4aef2cb417bfa88b1"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1b42da4c72c1e5e4aef2cb417bfa88b1">PIN_PB21M_GCLK_IO7</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(53)</td></tr>
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<tr class="memdesc:a1b42da4c72c1e5e4aef2cb417bfa88b1"><td class="mdescLeft"> </td><td class="mdescRight">GCLK signal: IO7 on PB21 mux M. <br /></td></tr>
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<tr class="separator:a1b42da4c72c1e5e4aef2cb417bfa88b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af52c6b65bb9beb13d06ccfca3a09bb39"><td class="memItemLeft" align="right" valign="top"><a id="af52c6b65bb9beb13d06ccfca3a09bb39"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB21M_GCLK_IO7</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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<tr class="separator:af52c6b65bb9beb13d06ccfca3a09bb39"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a752c3c468bf4883000bdd88e13a4a5ce"><td class="memItemLeft" align="right" valign="top"><a id="a752c3c468bf4883000bdd88e13a4a5ce"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB21M_GCLK_IO7</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a1b42da4c72c1e5e4aef2cb417bfa88b1">PIN_PB21M_GCLK_IO7</a> << 16) | MUX_PB21M_GCLK_IO7)</td></tr>
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<tr class="separator:a752c3c468bf4883000bdd88e13a4a5ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a47b96fd369ee0a8bf8679bbcf0641586"><td class="memItemLeft" align="right" valign="top"><a id="a47b96fd369ee0a8bf8679bbcf0641586"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB21M_GCLK_IO7</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 21)</td></tr>
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<tr class="separator:a47b96fd369ee0a8bf8679bbcf0641586"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a283c31c34ebe58501071a14230504e28"><td class="memItemLeft" align="right" valign="top"><a id="a283c31c34ebe58501071a14230504e28"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a283c31c34ebe58501071a14230504e28">PIN_PA00A_EIC_EXTINT0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="memdesc:a283c31c34ebe58501071a14230504e28"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT0 on PA00 mux A. <br /></td></tr>
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<tr class="separator:a283c31c34ebe58501071a14230504e28"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ada8786bd83b71e9b93e72c86cbc0fcee"><td class="memItemLeft" align="right" valign="top"><a id="ada8786bd83b71e9b93e72c86cbc0fcee"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA00A_EIC_EXTINT0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:ada8786bd83b71e9b93e72c86cbc0fcee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a065904abb03cbe2481f588419ceef660"><td class="memItemLeft" align="right" valign="top"><a id="a065904abb03cbe2481f588419ceef660"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA00A_EIC_EXTINT0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a283c31c34ebe58501071a14230504e28">PIN_PA00A_EIC_EXTINT0</a> << 16) | MUX_PA00A_EIC_EXTINT0)</td></tr>
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<tr class="separator:a065904abb03cbe2481f588419ceef660"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af60b1526b1304025ea62531112f0bddc"><td class="memItemLeft" align="right" valign="top"><a id="af60b1526b1304025ea62531112f0bddc"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA00A_EIC_EXTINT0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 0)</td></tr>
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<tr class="separator:af60b1526b1304025ea62531112f0bddc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aef1ff14a903c5484430241fdcb78475e"><td class="memItemLeft" align="right" valign="top"><a id="aef1ff14a903c5484430241fdcb78475e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aef1ff14a903c5484430241fdcb78475e">PIN_PA00A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="memdesc:aef1ff14a903c5484430241fdcb78475e"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PA00 External Interrupt Line. <br /></td></tr>
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<tr class="separator:aef1ff14a903c5484430241fdcb78475e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0d770aa7d3ddd4cad47c946b1a3da6c9"><td class="memItemLeft" align="right" valign="top"><a id="a0d770aa7d3ddd4cad47c946b1a3da6c9"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0d770aa7d3ddd4cad47c946b1a3da6c9">PIN_PA16A_EIC_EXTINT0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(16)</td></tr>
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<tr class="memdesc:a0d770aa7d3ddd4cad47c946b1a3da6c9"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT0 on PA16 mux A. <br /></td></tr>
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<tr class="separator:a0d770aa7d3ddd4cad47c946b1a3da6c9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aba036c07999fa9cff65d066004c0cb87"><td class="memItemLeft" align="right" valign="top"><a id="aba036c07999fa9cff65d066004c0cb87"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA16A_EIC_EXTINT0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:aba036c07999fa9cff65d066004c0cb87"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a00d55a483781054df8cd5141f0a6744b"><td class="memItemLeft" align="right" valign="top"><a id="a00d55a483781054df8cd5141f0a6744b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA16A_EIC_EXTINT0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a0d770aa7d3ddd4cad47c946b1a3da6c9">PIN_PA16A_EIC_EXTINT0</a> << 16) | MUX_PA16A_EIC_EXTINT0)</td></tr>
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<tr class="separator:a00d55a483781054df8cd5141f0a6744b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aca2857e5b2fe094781d0cc5822897a64"><td class="memItemLeft" align="right" valign="top"><a id="aca2857e5b2fe094781d0cc5822897a64"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA16A_EIC_EXTINT0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 16)</td></tr>
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<tr class="separator:aca2857e5b2fe094781d0cc5822897a64"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afc2fba86df87333e6fdc40b51773849e"><td class="memItemLeft" align="right" valign="top"><a id="afc2fba86df87333e6fdc40b51773849e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#afc2fba86df87333e6fdc40b51773849e">PIN_PA16A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="memdesc:afc2fba86df87333e6fdc40b51773849e"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PA16 External Interrupt Line. <br /></td></tr>
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<tr class="separator:afc2fba86df87333e6fdc40b51773849e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab4dde340f20a4cf17a79fbf78915221e"><td class="memItemLeft" align="right" valign="top"><a id="ab4dde340f20a4cf17a79fbf78915221e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab4dde340f20a4cf17a79fbf78915221e">PIN_PB00A_EIC_EXTINT0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(32)</td></tr>
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<tr class="memdesc:ab4dde340f20a4cf17a79fbf78915221e"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT0 on PB00 mux A. <br /></td></tr>
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<tr class="separator:ab4dde340f20a4cf17a79fbf78915221e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab4aad90b428cca1ca340f131f6671a97"><td class="memItemLeft" align="right" valign="top"><a id="ab4aad90b428cca1ca340f131f6671a97"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB00A_EIC_EXTINT0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:ab4aad90b428cca1ca340f131f6671a97"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a408cc226e18de90936f788baf837ee45"><td class="memItemLeft" align="right" valign="top"><a id="a408cc226e18de90936f788baf837ee45"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB00A_EIC_EXTINT0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ab4dde340f20a4cf17a79fbf78915221e">PIN_PB00A_EIC_EXTINT0</a> << 16) | MUX_PB00A_EIC_EXTINT0)</td></tr>
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<tr class="separator:a408cc226e18de90936f788baf837ee45"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac17d1eb887a086a5f3d4cfac81aab20c"><td class="memItemLeft" align="right" valign="top"><a id="ac17d1eb887a086a5f3d4cfac81aab20c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB00A_EIC_EXTINT0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 0)</td></tr>
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<tr class="separator:ac17d1eb887a086a5f3d4cfac81aab20c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8583a3ee73c8d6a94d17a06fdad7610c"><td class="memItemLeft" align="right" valign="top"><a id="a8583a3ee73c8d6a94d17a06fdad7610c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8583a3ee73c8d6a94d17a06fdad7610c">PIN_PB00A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="memdesc:a8583a3ee73c8d6a94d17a06fdad7610c"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PB00 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a8583a3ee73c8d6a94d17a06fdad7610c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3cdb969253e905e519355e82aff95ba5"><td class="memItemLeft" align="right" valign="top"><a id="a3cdb969253e905e519355e82aff95ba5"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3cdb969253e905e519355e82aff95ba5">PIN_PB16A_EIC_EXTINT0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(48)</td></tr>
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<tr class="memdesc:a3cdb969253e905e519355e82aff95ba5"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT0 on PB16 mux A. <br /></td></tr>
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<tr class="separator:a3cdb969253e905e519355e82aff95ba5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:add2c1164d3514b606deb5b8e55b5429c"><td class="memItemLeft" align="right" valign="top"><a id="add2c1164d3514b606deb5b8e55b5429c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB16A_EIC_EXTINT0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:add2c1164d3514b606deb5b8e55b5429c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4eabb97637dc042b3c80ce1a5e3d7ee7"><td class="memItemLeft" align="right" valign="top"><a id="a4eabb97637dc042b3c80ce1a5e3d7ee7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB16A_EIC_EXTINT0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a3cdb969253e905e519355e82aff95ba5">PIN_PB16A_EIC_EXTINT0</a> << 16) | MUX_PB16A_EIC_EXTINT0)</td></tr>
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<tr class="separator:a4eabb97637dc042b3c80ce1a5e3d7ee7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad29ea8f7424bc4792daa2167f7a4c795"><td class="memItemLeft" align="right" valign="top"><a id="ad29ea8f7424bc4792daa2167f7a4c795"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB16A_EIC_EXTINT0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 16)</td></tr>
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<tr class="separator:ad29ea8f7424bc4792daa2167f7a4c795"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a43d653f1eac9c2bfb0a5bd347f1e45f5"><td class="memItemLeft" align="right" valign="top"><a id="a43d653f1eac9c2bfb0a5bd347f1e45f5"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a43d653f1eac9c2bfb0a5bd347f1e45f5">PIN_PB16A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="memdesc:a43d653f1eac9c2bfb0a5bd347f1e45f5"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PB16 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a43d653f1eac9c2bfb0a5bd347f1e45f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a44cd6df5789f3992386fb18f1c6574f6"><td class="memItemLeft" align="right" valign="top"><a id="a44cd6df5789f3992386fb18f1c6574f6"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a44cd6df5789f3992386fb18f1c6574f6">PIN_PC00A_EIC_EXTINT0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(64)</td></tr>
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<tr class="memdesc:a44cd6df5789f3992386fb18f1c6574f6"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT0 on PC00 mux A. <br /></td></tr>
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<tr class="separator:a44cd6df5789f3992386fb18f1c6574f6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a05efe014544e46335d76d7283a42317d"><td class="memItemLeft" align="right" valign="top"><a id="a05efe014544e46335d76d7283a42317d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC00A_EIC_EXTINT0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a05efe014544e46335d76d7283a42317d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3d774d7cb86bdd9a81cc565542159f54"><td class="memItemLeft" align="right" valign="top"><a id="a3d774d7cb86bdd9a81cc565542159f54"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC00A_EIC_EXTINT0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a44cd6df5789f3992386fb18f1c6574f6">PIN_PC00A_EIC_EXTINT0</a> << 16) | MUX_PC00A_EIC_EXTINT0)</td></tr>
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<tr class="separator:a3d774d7cb86bdd9a81cc565542159f54"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac9513623bff29236cf3009e9394df22c"><td class="memItemLeft" align="right" valign="top"><a id="ac9513623bff29236cf3009e9394df22c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC00A_EIC_EXTINT0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 0)</td></tr>
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<tr class="separator:ac9513623bff29236cf3009e9394df22c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab845418a9f9b8cb51139923c37ba67c3"><td class="memItemLeft" align="right" valign="top"><a id="ab845418a9f9b8cb51139923c37ba67c3"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab845418a9f9b8cb51139923c37ba67c3">PIN_PC00A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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||
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<tr class="memdesc:ab845418a9f9b8cb51139923c37ba67c3"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PC00 External Interrupt Line. <br /></td></tr>
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<tr class="separator:ab845418a9f9b8cb51139923c37ba67c3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4577c1ecbc3142a5c7cd489371c88670"><td class="memItemLeft" align="right" valign="top"><a id="a4577c1ecbc3142a5c7cd489371c88670"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4577c1ecbc3142a5c7cd489371c88670">PIN_PC16A_EIC_EXTINT0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(80)</td></tr>
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||
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<tr class="memdesc:a4577c1ecbc3142a5c7cd489371c88670"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT0 on PC16 mux A. <br /></td></tr>
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<tr class="separator:a4577c1ecbc3142a5c7cd489371c88670"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa5f507d665150eee15d06b952b51320d"><td class="memItemLeft" align="right" valign="top"><a id="aa5f507d665150eee15d06b952b51320d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC16A_EIC_EXTINT0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:aa5f507d665150eee15d06b952b51320d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab16a63d72090853177da5b383eff4723"><td class="memItemLeft" align="right" valign="top"><a id="ab16a63d72090853177da5b383eff4723"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC16A_EIC_EXTINT0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a4577c1ecbc3142a5c7cd489371c88670">PIN_PC16A_EIC_EXTINT0</a> << 16) | MUX_PC16A_EIC_EXTINT0)</td></tr>
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<tr class="separator:ab16a63d72090853177da5b383eff4723"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a250975677f70169a56fb26e4d6545c51"><td class="memItemLeft" align="right" valign="top"><a id="a250975677f70169a56fb26e4d6545c51"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC16A_EIC_EXTINT0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 16)</td></tr>
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<tr class="separator:a250975677f70169a56fb26e4d6545c51"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a997b3fa16417fa67f725ac5c8559a036"><td class="memItemLeft" align="right" valign="top"><a id="a997b3fa16417fa67f725ac5c8559a036"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a997b3fa16417fa67f725ac5c8559a036">PIN_PC16A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
|
||
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<tr class="memdesc:a997b3fa16417fa67f725ac5c8559a036"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PC16 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a997b3fa16417fa67f725ac5c8559a036"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a256def0777a25758382d17d13cdb78fc"><td class="memItemLeft" align="right" valign="top"><a id="a256def0777a25758382d17d13cdb78fc"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a256def0777a25758382d17d13cdb78fc">PIN_PA01A_EIC_EXTINT1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
|
||
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<tr class="memdesc:a256def0777a25758382d17d13cdb78fc"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT1 on PA01 mux A. <br /></td></tr>
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<tr class="separator:a256def0777a25758382d17d13cdb78fc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7348ea9f6afb7f419d46efa1ba892423"><td class="memItemLeft" align="right" valign="top"><a id="a7348ea9f6afb7f419d46efa1ba892423"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA01A_EIC_EXTINT1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a7348ea9f6afb7f419d46efa1ba892423"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3747b408691555270ac9554a8f62ca98"><td class="memItemLeft" align="right" valign="top"><a id="a3747b408691555270ac9554a8f62ca98"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA01A_EIC_EXTINT1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a256def0777a25758382d17d13cdb78fc">PIN_PA01A_EIC_EXTINT1</a> << 16) | MUX_PA01A_EIC_EXTINT1)</td></tr>
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<tr class="separator:a3747b408691555270ac9554a8f62ca98"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0afe1c453fc1a9df0d89d204b0ae1c82"><td class="memItemLeft" align="right" valign="top"><a id="a0afe1c453fc1a9df0d89d204b0ae1c82"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA01A_EIC_EXTINT1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 1)</td></tr>
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<tr class="separator:a0afe1c453fc1a9df0d89d204b0ae1c82"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1886a08201ef40b8f967b8e093144cf2"><td class="memItemLeft" align="right" valign="top"><a id="a1886a08201ef40b8f967b8e093144cf2"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1886a08201ef40b8f967b8e093144cf2">PIN_PA01A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
|
||
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<tr class="memdesc:a1886a08201ef40b8f967b8e093144cf2"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PA01 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a1886a08201ef40b8f967b8e093144cf2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af79887da5633d1254eb6c8b333c47db6"><td class="memItemLeft" align="right" valign="top"><a id="af79887da5633d1254eb6c8b333c47db6"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af79887da5633d1254eb6c8b333c47db6">PIN_PA17A_EIC_EXTINT1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(17)</td></tr>
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||
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<tr class="memdesc:af79887da5633d1254eb6c8b333c47db6"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT1 on PA17 mux A. <br /></td></tr>
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<tr class="separator:af79887da5633d1254eb6c8b333c47db6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a352f692a4f3df851a0100958065b41df"><td class="memItemLeft" align="right" valign="top"><a id="a352f692a4f3df851a0100958065b41df"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA17A_EIC_EXTINT1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a352f692a4f3df851a0100958065b41df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4de8edee33089c27a2615fcf2f09cacb"><td class="memItemLeft" align="right" valign="top"><a id="a4de8edee33089c27a2615fcf2f09cacb"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA17A_EIC_EXTINT1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#af79887da5633d1254eb6c8b333c47db6">PIN_PA17A_EIC_EXTINT1</a> << 16) | MUX_PA17A_EIC_EXTINT1)</td></tr>
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<tr class="separator:a4de8edee33089c27a2615fcf2f09cacb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab060b607ea5e30310762192efa275adc"><td class="memItemLeft" align="right" valign="top"><a id="ab060b607ea5e30310762192efa275adc"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA17A_EIC_EXTINT1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 17)</td></tr>
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||
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<tr class="separator:ab060b607ea5e30310762192efa275adc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2e6eb3b0e73b998c18da45bf342f359a"><td class="memItemLeft" align="right" valign="top"><a id="a2e6eb3b0e73b998c18da45bf342f359a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2e6eb3b0e73b998c18da45bf342f359a">PIN_PA17A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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||
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<tr class="memdesc:a2e6eb3b0e73b998c18da45bf342f359a"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PA17 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a2e6eb3b0e73b998c18da45bf342f359a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afaf80286ec3dd70e08637188c66b6a0a"><td class="memItemLeft" align="right" valign="top"><a id="afaf80286ec3dd70e08637188c66b6a0a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#afaf80286ec3dd70e08637188c66b6a0a">PIN_PB01A_EIC_EXTINT1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(33)</td></tr>
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||
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<tr class="memdesc:afaf80286ec3dd70e08637188c66b6a0a"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT1 on PB01 mux A. <br /></td></tr>
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<tr class="separator:afaf80286ec3dd70e08637188c66b6a0a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa272f04e4deddb17d9024556284a85a2"><td class="memItemLeft" align="right" valign="top"><a id="aa272f04e4deddb17d9024556284a85a2"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB01A_EIC_EXTINT1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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||
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<tr class="separator:aa272f04e4deddb17d9024556284a85a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aad33e850756b6fee75356208a080d44e"><td class="memItemLeft" align="right" valign="top"><a id="aad33e850756b6fee75356208a080d44e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB01A_EIC_EXTINT1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#afaf80286ec3dd70e08637188c66b6a0a">PIN_PB01A_EIC_EXTINT1</a> << 16) | MUX_PB01A_EIC_EXTINT1)</td></tr>
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<tr class="separator:aad33e850756b6fee75356208a080d44e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac028ac220cd887bf26614ffd8c4b1a6f"><td class="memItemLeft" align="right" valign="top"><a id="ac028ac220cd887bf26614ffd8c4b1a6f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB01A_EIC_EXTINT1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 1)</td></tr>
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<tr class="separator:ac028ac220cd887bf26614ffd8c4b1a6f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a21d47712199a969466553ab3597f04c2"><td class="memItemLeft" align="right" valign="top"><a id="a21d47712199a969466553ab3597f04c2"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a21d47712199a969466553ab3597f04c2">PIN_PB01A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="memdesc:a21d47712199a969466553ab3597f04c2"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PB01 External Interrupt Line. <br /></td></tr>
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<tr class="memitem:afa4edebc2d5a45eb26b3d1cec0a71960"><td class="memItemLeft" align="right" valign="top"><a id="afa4edebc2d5a45eb26b3d1cec0a71960"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#afa4edebc2d5a45eb26b3d1cec0a71960">PIN_PB17A_EIC_EXTINT1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(49)</td></tr>
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<tr class="memdesc:afa4edebc2d5a45eb26b3d1cec0a71960"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT1 on PB17 mux A. <br /></td></tr>
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<tr class="separator:afa4edebc2d5a45eb26b3d1cec0a71960"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ace535ea6b1b0210c4560a454d1b2dd54"><td class="memItemLeft" align="right" valign="top"><a id="ace535ea6b1b0210c4560a454d1b2dd54"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB17A_EIC_EXTINT1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:ace535ea6b1b0210c4560a454d1b2dd54"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aaa6f50a2f9b946f1d9b8125c0d52cd95"><td class="memItemLeft" align="right" valign="top"><a id="aaa6f50a2f9b946f1d9b8125c0d52cd95"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB17A_EIC_EXTINT1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#afa4edebc2d5a45eb26b3d1cec0a71960">PIN_PB17A_EIC_EXTINT1</a> << 16) | MUX_PB17A_EIC_EXTINT1)</td></tr>
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<tr class="separator:aaa6f50a2f9b946f1d9b8125c0d52cd95"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae46a5a8c726f611b938449db89ff2230"><td class="memItemLeft" align="right" valign="top"><a id="ae46a5a8c726f611b938449db89ff2230"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB17A_EIC_EXTINT1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 17)</td></tr>
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<tr class="separator:ae46a5a8c726f611b938449db89ff2230"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4e4b9e5ee67364d1135dfb55d7bc0db4"><td class="memItemLeft" align="right" valign="top"><a id="a4e4b9e5ee67364d1135dfb55d7bc0db4"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4e4b9e5ee67364d1135dfb55d7bc0db4">PIN_PB17A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="memdesc:a4e4b9e5ee67364d1135dfb55d7bc0db4"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PB17 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a4e4b9e5ee67364d1135dfb55d7bc0db4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a320a5efa3dd816ea43d7edf1d66723a4"><td class="memItemLeft" align="right" valign="top"><a id="a320a5efa3dd816ea43d7edf1d66723a4"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a320a5efa3dd816ea43d7edf1d66723a4">PIN_PC01A_EIC_EXTINT1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(65)</td></tr>
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<tr class="memdesc:a320a5efa3dd816ea43d7edf1d66723a4"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT1 on PC01 mux A. <br /></td></tr>
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<tr class="separator:a320a5efa3dd816ea43d7edf1d66723a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9b5ca7665c9ece4d1f8cc61f6fd046e6"><td class="memItemLeft" align="right" valign="top"><a id="a9b5ca7665c9ece4d1f8cc61f6fd046e6"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC01A_EIC_EXTINT1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a9b5ca7665c9ece4d1f8cc61f6fd046e6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a363246b6f40567971a5e4fc4e32a31e3"><td class="memItemLeft" align="right" valign="top"><a id="a363246b6f40567971a5e4fc4e32a31e3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC01A_EIC_EXTINT1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a320a5efa3dd816ea43d7edf1d66723a4">PIN_PC01A_EIC_EXTINT1</a> << 16) | MUX_PC01A_EIC_EXTINT1)</td></tr>
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<tr class="separator:a363246b6f40567971a5e4fc4e32a31e3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a56e111c1b4bf112e4daa1510468ba100"><td class="memItemLeft" align="right" valign="top"><a id="a56e111c1b4bf112e4daa1510468ba100"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC01A_EIC_EXTINT1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 1)</td></tr>
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<tr class="separator:a56e111c1b4bf112e4daa1510468ba100"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af1230535ca94de25c2346a1a6e25d372"><td class="memItemLeft" align="right" valign="top"><a id="af1230535ca94de25c2346a1a6e25d372"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af1230535ca94de25c2346a1a6e25d372">PIN_PC01A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="memdesc:af1230535ca94de25c2346a1a6e25d372"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PC01 External Interrupt Line. <br /></td></tr>
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<tr class="separator:af1230535ca94de25c2346a1a6e25d372"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aaf8d7c6a329bd1361e6d7868046f1834"><td class="memItemLeft" align="right" valign="top"><a id="aaf8d7c6a329bd1361e6d7868046f1834"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aaf8d7c6a329bd1361e6d7868046f1834">PIN_PC17A_EIC_EXTINT1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(81)</td></tr>
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<tr class="memdesc:aaf8d7c6a329bd1361e6d7868046f1834"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT1 on PC17 mux A. <br /></td></tr>
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<tr class="separator:aaf8d7c6a329bd1361e6d7868046f1834"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4db71e0d4d0402040321539b824bdc45"><td class="memItemLeft" align="right" valign="top"><a id="a4db71e0d4d0402040321539b824bdc45"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC17A_EIC_EXTINT1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a4db71e0d4d0402040321539b824bdc45"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae3584f30d14d51ee5e1e89ee52bdbf51"><td class="memItemLeft" align="right" valign="top"><a id="ae3584f30d14d51ee5e1e89ee52bdbf51"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC17A_EIC_EXTINT1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aaf8d7c6a329bd1361e6d7868046f1834">PIN_PC17A_EIC_EXTINT1</a> << 16) | MUX_PC17A_EIC_EXTINT1)</td></tr>
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<tr class="separator:ae3584f30d14d51ee5e1e89ee52bdbf51"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abfe6d074de8022ada55d92533be1933f"><td class="memItemLeft" align="right" valign="top"><a id="abfe6d074de8022ada55d92533be1933f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC17A_EIC_EXTINT1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 17)</td></tr>
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<tr class="separator:abfe6d074de8022ada55d92533be1933f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5e9f7f738e5df9c1a8cae678a2b809c4"><td class="memItemLeft" align="right" valign="top"><a id="a5e9f7f738e5df9c1a8cae678a2b809c4"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5e9f7f738e5df9c1a8cae678a2b809c4">PIN_PC17A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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||
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<tr class="memdesc:a5e9f7f738e5df9c1a8cae678a2b809c4"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PC17 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a5e9f7f738e5df9c1a8cae678a2b809c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aea7fe40459b7796f18577ecfc01f8a47"><td class="memItemLeft" align="right" valign="top"><a id="aea7fe40459b7796f18577ecfc01f8a47"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aea7fe40459b7796f18577ecfc01f8a47">PIN_PA02A_EIC_EXTINT2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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<tr class="memdesc:aea7fe40459b7796f18577ecfc01f8a47"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT2 on PA02 mux A. <br /></td></tr>
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<tr class="separator:aea7fe40459b7796f18577ecfc01f8a47"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9056e32c23fa12d0cd584561cea16ec5"><td class="memItemLeft" align="right" valign="top"><a id="a9056e32c23fa12d0cd584561cea16ec5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA02A_EIC_EXTINT2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a9056e32c23fa12d0cd584561cea16ec5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a43666db54b4bdbe4375f6763048e484f"><td class="memItemLeft" align="right" valign="top"><a id="a43666db54b4bdbe4375f6763048e484f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA02A_EIC_EXTINT2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aea7fe40459b7796f18577ecfc01f8a47">PIN_PA02A_EIC_EXTINT2</a> << 16) | MUX_PA02A_EIC_EXTINT2)</td></tr>
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<tr class="separator:a43666db54b4bdbe4375f6763048e484f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab6c8c47a763bb4b6e58519a8b2d04191"><td class="memItemLeft" align="right" valign="top"><a id="ab6c8c47a763bb4b6e58519a8b2d04191"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA02A_EIC_EXTINT2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 2)</td></tr>
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<tr class="separator:ab6c8c47a763bb4b6e58519a8b2d04191"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac72f6cd470f25893de46ce66022ac430"><td class="memItemLeft" align="right" valign="top"><a id="ac72f6cd470f25893de46ce66022ac430"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac72f6cd470f25893de46ce66022ac430">PIN_PA02A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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<tr class="memdesc:ac72f6cd470f25893de46ce66022ac430"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PA02 External Interrupt Line. <br /></td></tr>
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<tr class="separator:ac72f6cd470f25893de46ce66022ac430"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a60fce7e2f63922c011117e19a3d85191"><td class="memItemLeft" align="right" valign="top"><a id="a60fce7e2f63922c011117e19a3d85191"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a60fce7e2f63922c011117e19a3d85191">PIN_PA18A_EIC_EXTINT2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(18)</td></tr>
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<tr class="memdesc:a60fce7e2f63922c011117e19a3d85191"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT2 on PA18 mux A. <br /></td></tr>
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<tr class="separator:a60fce7e2f63922c011117e19a3d85191"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac2b51002feb487fd52c962f4b9a08eda"><td class="memItemLeft" align="right" valign="top"><a id="ac2b51002feb487fd52c962f4b9a08eda"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA18A_EIC_EXTINT2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:ac2b51002feb487fd52c962f4b9a08eda"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ada91c6def2bba0144f4bcb92a4cb7853"><td class="memItemLeft" align="right" valign="top"><a id="ada91c6def2bba0144f4bcb92a4cb7853"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA18A_EIC_EXTINT2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a60fce7e2f63922c011117e19a3d85191">PIN_PA18A_EIC_EXTINT2</a> << 16) | MUX_PA18A_EIC_EXTINT2)</td></tr>
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<tr class="separator:ada91c6def2bba0144f4bcb92a4cb7853"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0b070f61e8ebe258c5dda170e9718d3e"><td class="memItemLeft" align="right" valign="top"><a id="a0b070f61e8ebe258c5dda170e9718d3e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA18A_EIC_EXTINT2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 18)</td></tr>
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<tr class="separator:a0b070f61e8ebe258c5dda170e9718d3e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a869336c0bb7a7af7f36e7d01343b9740"><td class="memItemLeft" align="right" valign="top"><a id="a869336c0bb7a7af7f36e7d01343b9740"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a869336c0bb7a7af7f36e7d01343b9740">PIN_PA18A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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<tr class="memdesc:a869336c0bb7a7af7f36e7d01343b9740"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PA18 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a869336c0bb7a7af7f36e7d01343b9740"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8c14eeab8dec7db30a3a08d9b4f65d94"><td class="memItemLeft" align="right" valign="top"><a id="a8c14eeab8dec7db30a3a08d9b4f65d94"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8c14eeab8dec7db30a3a08d9b4f65d94">PIN_PB02A_EIC_EXTINT2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(34)</td></tr>
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||
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<tr class="memdesc:a8c14eeab8dec7db30a3a08d9b4f65d94"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT2 on PB02 mux A. <br /></td></tr>
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<tr class="separator:a8c14eeab8dec7db30a3a08d9b4f65d94"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2039d3e296842f6bbbceca1e20c3ddea"><td class="memItemLeft" align="right" valign="top"><a id="a2039d3e296842f6bbbceca1e20c3ddea"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB02A_EIC_EXTINT2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="memitem:aa5aa8c72c175bd49d2e2538c3a555c16"><td class="memItemLeft" align="right" valign="top"><a id="aa5aa8c72c175bd49d2e2538c3a555c16"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB02A_EIC_EXTINT2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a8c14eeab8dec7db30a3a08d9b4f65d94">PIN_PB02A_EIC_EXTINT2</a> << 16) | MUX_PB02A_EIC_EXTINT2)</td></tr>
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<tr class="separator:aa5aa8c72c175bd49d2e2538c3a555c16"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3a4a388384b54af6254e6152be60ff77"><td class="memItemLeft" align="right" valign="top"><a id="a3a4a388384b54af6254e6152be60ff77"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB02A_EIC_EXTINT2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 2)</td></tr>
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<tr class="separator:a3a4a388384b54af6254e6152be60ff77"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a44892b8dfdec0c99ceb1c2619d4a008d"><td class="memItemLeft" align="right" valign="top"><a id="a44892b8dfdec0c99ceb1c2619d4a008d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a44892b8dfdec0c99ceb1c2619d4a008d">PIN_PB02A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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<tr class="memdesc:a44892b8dfdec0c99ceb1c2619d4a008d"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PB02 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a44892b8dfdec0c99ceb1c2619d4a008d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a408a2a17c0e02ea6d30cd4b47776b67b"><td class="memItemLeft" align="right" valign="top"><a id="a408a2a17c0e02ea6d30cd4b47776b67b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a408a2a17c0e02ea6d30cd4b47776b67b">PIN_PB18A_EIC_EXTINT2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(50)</td></tr>
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<tr class="memdesc:a408a2a17c0e02ea6d30cd4b47776b67b"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT2 on PB18 mux A. <br /></td></tr>
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<tr class="separator:a408a2a17c0e02ea6d30cd4b47776b67b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aefef7fa72093f44fb580ba85f5f6ea36"><td class="memItemLeft" align="right" valign="top"><a id="aefef7fa72093f44fb580ba85f5f6ea36"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB18A_EIC_EXTINT2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:aefef7fa72093f44fb580ba85f5f6ea36"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af2d77bc1b5116ce69c3436389e242ad3"><td class="memItemLeft" align="right" valign="top"><a id="af2d77bc1b5116ce69c3436389e242ad3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB18A_EIC_EXTINT2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a408a2a17c0e02ea6d30cd4b47776b67b">PIN_PB18A_EIC_EXTINT2</a> << 16) | MUX_PB18A_EIC_EXTINT2)</td></tr>
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<tr class="separator:af2d77bc1b5116ce69c3436389e242ad3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4a62297bcd5c475a7cf3438d89fa89dd"><td class="memItemLeft" align="right" valign="top"><a id="a4a62297bcd5c475a7cf3438d89fa89dd"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB18A_EIC_EXTINT2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 18)</td></tr>
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<tr class="separator:a4a62297bcd5c475a7cf3438d89fa89dd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a912a1c19c620af64c76728d4c4f33a66"><td class="memItemLeft" align="right" valign="top"><a id="a912a1c19c620af64c76728d4c4f33a66"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a912a1c19c620af64c76728d4c4f33a66">PIN_PB18A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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<tr class="memdesc:a912a1c19c620af64c76728d4c4f33a66"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PB18 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a912a1c19c620af64c76728d4c4f33a66"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa823536240b45e7eca5a7ac3b394cb9b"><td class="memItemLeft" align="right" valign="top"><a id="aa823536240b45e7eca5a7ac3b394cb9b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa823536240b45e7eca5a7ac3b394cb9b">PIN_PC02A_EIC_EXTINT2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(66)</td></tr>
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<tr class="memdesc:aa823536240b45e7eca5a7ac3b394cb9b"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT2 on PC02 mux A. <br /></td></tr>
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<tr class="separator:aa823536240b45e7eca5a7ac3b394cb9b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5ad70fb8cb6fe2ad60403fbf1ce9ffb5"><td class="memItemLeft" align="right" valign="top"><a id="a5ad70fb8cb6fe2ad60403fbf1ce9ffb5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC02A_EIC_EXTINT2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a5ad70fb8cb6fe2ad60403fbf1ce9ffb5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa099b6a4d05189fee84c77fd29047181"><td class="memItemLeft" align="right" valign="top"><a id="aa099b6a4d05189fee84c77fd29047181"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC02A_EIC_EXTINT2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aa823536240b45e7eca5a7ac3b394cb9b">PIN_PC02A_EIC_EXTINT2</a> << 16) | MUX_PC02A_EIC_EXTINT2)</td></tr>
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<tr class="separator:aa099b6a4d05189fee84c77fd29047181"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a252c8f7ab543079b083831d4ddc0834c"><td class="memItemLeft" align="right" valign="top"><a id="a252c8f7ab543079b083831d4ddc0834c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC02A_EIC_EXTINT2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 2)</td></tr>
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<tr class="separator:a252c8f7ab543079b083831d4ddc0834c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a774f55a73a80e6912d6b69693c88163b"><td class="memItemLeft" align="right" valign="top"><a id="a774f55a73a80e6912d6b69693c88163b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a774f55a73a80e6912d6b69693c88163b">PIN_PC02A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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<tr class="memdesc:a774f55a73a80e6912d6b69693c88163b"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PC02 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a774f55a73a80e6912d6b69693c88163b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a293c09db7067876174ae2b5aa59cce0b"><td class="memItemLeft" align="right" valign="top"><a id="a293c09db7067876174ae2b5aa59cce0b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a293c09db7067876174ae2b5aa59cce0b">PIN_PC18A_EIC_EXTINT2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(82)</td></tr>
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||
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<tr class="memdesc:a293c09db7067876174ae2b5aa59cce0b"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT2 on PC18 mux A. <br /></td></tr>
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<tr class="separator:a293c09db7067876174ae2b5aa59cce0b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5654fa3a5d01bf39231fed51327a3a74"><td class="memItemLeft" align="right" valign="top"><a id="a5654fa3a5d01bf39231fed51327a3a74"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC18A_EIC_EXTINT2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a5654fa3a5d01bf39231fed51327a3a74"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3f1fd39dc1e4e8af28bf9848152034b0"><td class="memItemLeft" align="right" valign="top"><a id="a3f1fd39dc1e4e8af28bf9848152034b0"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC18A_EIC_EXTINT2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a293c09db7067876174ae2b5aa59cce0b">PIN_PC18A_EIC_EXTINT2</a> << 16) | MUX_PC18A_EIC_EXTINT2)</td></tr>
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<tr class="separator:a3f1fd39dc1e4e8af28bf9848152034b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af57f2e9c9f31939531edcbfc6d0d65f7"><td class="memItemLeft" align="right" valign="top"><a id="af57f2e9c9f31939531edcbfc6d0d65f7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC18A_EIC_EXTINT2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 18)</td></tr>
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<tr class="separator:af57f2e9c9f31939531edcbfc6d0d65f7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa9c4ff69b685ce241c7b911b91b36f4a"><td class="memItemLeft" align="right" valign="top"><a id="aa9c4ff69b685ce241c7b911b91b36f4a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa9c4ff69b685ce241c7b911b91b36f4a">PIN_PC18A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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<tr class="memdesc:aa9c4ff69b685ce241c7b911b91b36f4a"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PC18 External Interrupt Line. <br /></td></tr>
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<tr class="separator:aa9c4ff69b685ce241c7b911b91b36f4a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a42aaac29dcc7aa7033b8626b04be9b22"><td class="memItemLeft" align="right" valign="top"><a id="a42aaac29dcc7aa7033b8626b04be9b22"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a42aaac29dcc7aa7033b8626b04be9b22">PIN_PA03A_EIC_EXTINT3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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||
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<tr class="memdesc:a42aaac29dcc7aa7033b8626b04be9b22"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT3 on PA03 mux A. <br /></td></tr>
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<tr class="separator:a42aaac29dcc7aa7033b8626b04be9b22"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adda8e3425b85e2ce6239e5545ead9df3"><td class="memItemLeft" align="right" valign="top"><a id="adda8e3425b85e2ce6239e5545ead9df3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA03A_EIC_EXTINT3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:adda8e3425b85e2ce6239e5545ead9df3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad84a5e1ff52843fbb3efbad78fd3060c"><td class="memItemLeft" align="right" valign="top"><a id="ad84a5e1ff52843fbb3efbad78fd3060c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA03A_EIC_EXTINT3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a42aaac29dcc7aa7033b8626b04be9b22">PIN_PA03A_EIC_EXTINT3</a> << 16) | MUX_PA03A_EIC_EXTINT3)</td></tr>
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<tr class="separator:ad84a5e1ff52843fbb3efbad78fd3060c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a25f0e6957f0c1cc9d478318d4f474617"><td class="memItemLeft" align="right" valign="top"><a id="a25f0e6957f0c1cc9d478318d4f474617"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA03A_EIC_EXTINT3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 3)</td></tr>
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<tr class="separator:a25f0e6957f0c1cc9d478318d4f474617"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac8e49fd7497460bfe7fbfb958547af00"><td class="memItemLeft" align="right" valign="top"><a id="ac8e49fd7497460bfe7fbfb958547af00"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac8e49fd7497460bfe7fbfb958547af00">PIN_PA03A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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||
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<tr class="memdesc:ac8e49fd7497460bfe7fbfb958547af00"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PA03 External Interrupt Line. <br /></td></tr>
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<tr class="separator:ac8e49fd7497460bfe7fbfb958547af00"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a87bc382027baedde18eb6502dec9a3b9"><td class="memItemLeft" align="right" valign="top"><a id="a87bc382027baedde18eb6502dec9a3b9"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a87bc382027baedde18eb6502dec9a3b9">PIN_PA19A_EIC_EXTINT3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(19)</td></tr>
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||
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<tr class="memdesc:a87bc382027baedde18eb6502dec9a3b9"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT3 on PA19 mux A. <br /></td></tr>
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<tr class="separator:a87bc382027baedde18eb6502dec9a3b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5d0046f9b2d5ac10094b7fcb123fdf31"><td class="memItemLeft" align="right" valign="top"><a id="a5d0046f9b2d5ac10094b7fcb123fdf31"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA19A_EIC_EXTINT3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a5d0046f9b2d5ac10094b7fcb123fdf31"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac6b408e2acde93d937829a1800a88146"><td class="memItemLeft" align="right" valign="top"><a id="ac6b408e2acde93d937829a1800a88146"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA19A_EIC_EXTINT3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a87bc382027baedde18eb6502dec9a3b9">PIN_PA19A_EIC_EXTINT3</a> << 16) | MUX_PA19A_EIC_EXTINT3)</td></tr>
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<tr class="separator:ac6b408e2acde93d937829a1800a88146"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abc03166cfe6bb0b35afec08977b31c1f"><td class="memItemLeft" align="right" valign="top"><a id="abc03166cfe6bb0b35afec08977b31c1f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA19A_EIC_EXTINT3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 19)</td></tr>
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||
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<tr class="memitem:a3e66edf4111ce73457ba2c4466dcb69f"><td class="memItemLeft" align="right" valign="top"><a id="a3e66edf4111ce73457ba2c4466dcb69f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3e66edf4111ce73457ba2c4466dcb69f">PIN_PA19A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="memdesc:a3e66edf4111ce73457ba2c4466dcb69f"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PA19 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a3e66edf4111ce73457ba2c4466dcb69f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3dcd20be32a645261f5975e310086298"><td class="memItemLeft" align="right" valign="top"><a id="a3dcd20be32a645261f5975e310086298"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3dcd20be32a645261f5975e310086298">PIN_PB03A_EIC_EXTINT3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(35)</td></tr>
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<tr class="memdesc:a3dcd20be32a645261f5975e310086298"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT3 on PB03 mux A. <br /></td></tr>
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<tr class="separator:a3dcd20be32a645261f5975e310086298"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aee71faad30286d0fff026876677f22b0"><td class="memItemLeft" align="right" valign="top"><a id="aee71faad30286d0fff026876677f22b0"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB03A_EIC_EXTINT3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:aee71faad30286d0fff026876677f22b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a57676139b08dd1f4fb3c250e695a90f5"><td class="memItemLeft" align="right" valign="top"><a id="a57676139b08dd1f4fb3c250e695a90f5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB03A_EIC_EXTINT3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a3dcd20be32a645261f5975e310086298">PIN_PB03A_EIC_EXTINT3</a> << 16) | MUX_PB03A_EIC_EXTINT3)</td></tr>
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<tr class="separator:a57676139b08dd1f4fb3c250e695a90f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9b55211288e12e913df5dc9cb1f7d8e5"><td class="memItemLeft" align="right" valign="top"><a id="a9b55211288e12e913df5dc9cb1f7d8e5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB03A_EIC_EXTINT3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 3)</td></tr>
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<tr class="separator:a9b55211288e12e913df5dc9cb1f7d8e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8406108b540b453e6116fbf2204f023a"><td class="memItemLeft" align="right" valign="top"><a id="a8406108b540b453e6116fbf2204f023a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8406108b540b453e6116fbf2204f023a">PIN_PB03A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="memdesc:a8406108b540b453e6116fbf2204f023a"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PB03 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a8406108b540b453e6116fbf2204f023a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac0b122ae8a806ac50ee7e8d6809e3d06"><td class="memItemLeft" align="right" valign="top"><a id="ac0b122ae8a806ac50ee7e8d6809e3d06"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac0b122ae8a806ac50ee7e8d6809e3d06">PIN_PB19A_EIC_EXTINT3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(51)</td></tr>
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<tr class="memdesc:ac0b122ae8a806ac50ee7e8d6809e3d06"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT3 on PB19 mux A. <br /></td></tr>
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<tr class="separator:ac0b122ae8a806ac50ee7e8d6809e3d06"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a02de5ec1df08c34d94c32a40fd80e222"><td class="memItemLeft" align="right" valign="top"><a id="a02de5ec1df08c34d94c32a40fd80e222"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB19A_EIC_EXTINT3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a02de5ec1df08c34d94c32a40fd80e222"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8b9e3a7c04c7ab1405d57b20292272d4"><td class="memItemLeft" align="right" valign="top"><a id="a8b9e3a7c04c7ab1405d57b20292272d4"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB19A_EIC_EXTINT3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ac0b122ae8a806ac50ee7e8d6809e3d06">PIN_PB19A_EIC_EXTINT3</a> << 16) | MUX_PB19A_EIC_EXTINT3)</td></tr>
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<tr class="separator:a8b9e3a7c04c7ab1405d57b20292272d4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a743f40df3571125b3bb420e67da5ee03"><td class="memItemLeft" align="right" valign="top"><a id="a743f40df3571125b3bb420e67da5ee03"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB19A_EIC_EXTINT3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 19)</td></tr>
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<tr class="separator:a743f40df3571125b3bb420e67da5ee03"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2be5ac46af5d8688b6de379d2a226c2b"><td class="memItemLeft" align="right" valign="top"><a id="a2be5ac46af5d8688b6de379d2a226c2b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2be5ac46af5d8688b6de379d2a226c2b">PIN_PB19A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
|
||
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<tr class="memdesc:a2be5ac46af5d8688b6de379d2a226c2b"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PB19 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a2be5ac46af5d8688b6de379d2a226c2b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abc5c80949166cae594213904371cf97a"><td class="memItemLeft" align="right" valign="top"><a id="abc5c80949166cae594213904371cf97a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#abc5c80949166cae594213904371cf97a">PIN_PC03A_EIC_EXTINT3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(67)</td></tr>
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||
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<tr class="memdesc:abc5c80949166cae594213904371cf97a"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT3 on PC03 mux A. <br /></td></tr>
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<tr class="separator:abc5c80949166cae594213904371cf97a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acbf374c186bd659e2ec758bf6be8bf1a"><td class="memItemLeft" align="right" valign="top"><a id="acbf374c186bd659e2ec758bf6be8bf1a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC03A_EIC_EXTINT3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:acbf374c186bd659e2ec758bf6be8bf1a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0352b8ae38bbe340db6b624387ad44ad"><td class="memItemLeft" align="right" valign="top"><a id="a0352b8ae38bbe340db6b624387ad44ad"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC03A_EIC_EXTINT3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#abc5c80949166cae594213904371cf97a">PIN_PC03A_EIC_EXTINT3</a> << 16) | MUX_PC03A_EIC_EXTINT3)</td></tr>
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<tr class="separator:a0352b8ae38bbe340db6b624387ad44ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac68dba06e244c80a93e993ed73ba69a9"><td class="memItemLeft" align="right" valign="top"><a id="ac68dba06e244c80a93e993ed73ba69a9"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC03A_EIC_EXTINT3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 3)</td></tr>
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||
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<tr class="separator:ac68dba06e244c80a93e993ed73ba69a9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5f2b5bd0a2210b716700abfc04e6e049"><td class="memItemLeft" align="right" valign="top"><a id="a5f2b5bd0a2210b716700abfc04e6e049"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5f2b5bd0a2210b716700abfc04e6e049">PIN_PC03A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
|
||
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<tr class="memdesc:a5f2b5bd0a2210b716700abfc04e6e049"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PC03 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a5f2b5bd0a2210b716700abfc04e6e049"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7dc953f6e486ad0b220a992377fa3f0a"><td class="memItemLeft" align="right" valign="top"><a id="a7dc953f6e486ad0b220a992377fa3f0a"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7dc953f6e486ad0b220a992377fa3f0a">PIN_PC19A_EIC_EXTINT3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(83)</td></tr>
|
||
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<tr class="memdesc:a7dc953f6e486ad0b220a992377fa3f0a"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT3 on PC19 mux A. <br /></td></tr>
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<tr class="separator:a7dc953f6e486ad0b220a992377fa3f0a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aee75a36bd782b2971fa2c53422e8a12d"><td class="memItemLeft" align="right" valign="top"><a id="aee75a36bd782b2971fa2c53422e8a12d"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC19A_EIC_EXTINT3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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||
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<tr class="separator:aee75a36bd782b2971fa2c53422e8a12d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3c23f2cc891f0adeb5690d1fd812a6de"><td class="memItemLeft" align="right" valign="top"><a id="a3c23f2cc891f0adeb5690d1fd812a6de"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC19A_EIC_EXTINT3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a7dc953f6e486ad0b220a992377fa3f0a">PIN_PC19A_EIC_EXTINT3</a> << 16) | MUX_PC19A_EIC_EXTINT3)</td></tr>
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<tr class="separator:a3c23f2cc891f0adeb5690d1fd812a6de"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af4e73644fa8819abf4ad3ee8b521fa36"><td class="memItemLeft" align="right" valign="top"><a id="af4e73644fa8819abf4ad3ee8b521fa36"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC19A_EIC_EXTINT3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 19)</td></tr>
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<tr class="separator:af4e73644fa8819abf4ad3ee8b521fa36"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0a3819d4def71f3c9e050a10135ec2f0"><td class="memItemLeft" align="right" valign="top"><a id="a0a3819d4def71f3c9e050a10135ec2f0"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0a3819d4def71f3c9e050a10135ec2f0">PIN_PC19A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
|
||
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<tr class="memdesc:a0a3819d4def71f3c9e050a10135ec2f0"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PC19 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a0a3819d4def71f3c9e050a10135ec2f0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a11527baace52338b39921887a555e478"><td class="memItemLeft" align="right" valign="top"><a id="a11527baace52338b39921887a555e478"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a11527baace52338b39921887a555e478">PIN_PA04A_EIC_EXTINT4</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
|
||
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<tr class="memdesc:a11527baace52338b39921887a555e478"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT4 on PA04 mux A. <br /></td></tr>
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<tr class="separator:a11527baace52338b39921887a555e478"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae7325e071c80ecbc0815859adb266b87"><td class="memItemLeft" align="right" valign="top"><a id="ae7325e071c80ecbc0815859adb266b87"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA04A_EIC_EXTINT4</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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||
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<tr class="separator:ae7325e071c80ecbc0815859adb266b87"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1af8c0604d6fd444c05c2022b0e3b5c4"><td class="memItemLeft" align="right" valign="top"><a id="a1af8c0604d6fd444c05c2022b0e3b5c4"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA04A_EIC_EXTINT4</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a11527baace52338b39921887a555e478">PIN_PA04A_EIC_EXTINT4</a> << 16) | MUX_PA04A_EIC_EXTINT4)</td></tr>
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<tr class="separator:a1af8c0604d6fd444c05c2022b0e3b5c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae25d340a48921df98df1600f89765afd"><td class="memItemLeft" align="right" valign="top"><a id="ae25d340a48921df98df1600f89765afd"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA04A_EIC_EXTINT4</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 4)</td></tr>
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||
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<tr class="separator:ae25d340a48921df98df1600f89765afd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1f0f4a3dafb40f7230781e4c4ce2702c"><td class="memItemLeft" align="right" valign="top"><a id="a1f0f4a3dafb40f7230781e4c4ce2702c"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1f0f4a3dafb40f7230781e4c4ce2702c">PIN_PA04A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
|
||
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<tr class="memdesc:a1f0f4a3dafb40f7230781e4c4ce2702c"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PA04 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a1f0f4a3dafb40f7230781e4c4ce2702c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5ea1669d366f3cba00fb9d875d6c324c"><td class="memItemLeft" align="right" valign="top"><a id="a5ea1669d366f3cba00fb9d875d6c324c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5ea1669d366f3cba00fb9d875d6c324c">PIN_PA20A_EIC_EXTINT4</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(20)</td></tr>
|
||
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<tr class="memdesc:a5ea1669d366f3cba00fb9d875d6c324c"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT4 on PA20 mux A. <br /></td></tr>
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<tr class="separator:a5ea1669d366f3cba00fb9d875d6c324c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a777bc09e6273aee42c5b2d1a730e4e86"><td class="memItemLeft" align="right" valign="top"><a id="a777bc09e6273aee42c5b2d1a730e4e86"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA20A_EIC_EXTINT4</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a777bc09e6273aee42c5b2d1a730e4e86"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa516830a0feaed8d1124cc4d47541481"><td class="memItemLeft" align="right" valign="top"><a id="aa516830a0feaed8d1124cc4d47541481"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA20A_EIC_EXTINT4</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a5ea1669d366f3cba00fb9d875d6c324c">PIN_PA20A_EIC_EXTINT4</a> << 16) | MUX_PA20A_EIC_EXTINT4)</td></tr>
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<tr class="memitem:a8d59ae55301f4caff2c9d3d61a4e6b32"><td class="memItemLeft" align="right" valign="top"><a id="a8d59ae55301f4caff2c9d3d61a4e6b32"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA20A_EIC_EXTINT4</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 20)</td></tr>
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<tr class="separator:a8d59ae55301f4caff2c9d3d61a4e6b32"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a73f5a2d7f2b1096fb1db71c984108ef8"><td class="memItemLeft" align="right" valign="top"><a id="a73f5a2d7f2b1096fb1db71c984108ef8"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a73f5a2d7f2b1096fb1db71c984108ef8">PIN_PA20A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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<tr class="memdesc:a73f5a2d7f2b1096fb1db71c984108ef8"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PA20 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a73f5a2d7f2b1096fb1db71c984108ef8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2fc2cfd9a8382477493f71f73bfb7455"><td class="memItemLeft" align="right" valign="top"><a id="a2fc2cfd9a8382477493f71f73bfb7455"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2fc2cfd9a8382477493f71f73bfb7455">PIN_PB04A_EIC_EXTINT4</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(36)</td></tr>
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<tr class="memdesc:a2fc2cfd9a8382477493f71f73bfb7455"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT4 on PB04 mux A. <br /></td></tr>
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<tr class="separator:a2fc2cfd9a8382477493f71f73bfb7455"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7f6000b0eacaaba1538ec2a0cf404a71"><td class="memItemLeft" align="right" valign="top"><a id="a7f6000b0eacaaba1538ec2a0cf404a71"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB04A_EIC_EXTINT4</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a7f6000b0eacaaba1538ec2a0cf404a71"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab4e046f51ad6b5fb50b32fb65616f6e6"><td class="memItemLeft" align="right" valign="top"><a id="ab4e046f51ad6b5fb50b32fb65616f6e6"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB04A_EIC_EXTINT4</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a2fc2cfd9a8382477493f71f73bfb7455">PIN_PB04A_EIC_EXTINT4</a> << 16) | MUX_PB04A_EIC_EXTINT4)</td></tr>
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<tr class="separator:ab4e046f51ad6b5fb50b32fb65616f6e6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa6fd44c74e50ce2081c34461fa50d1a8"><td class="memItemLeft" align="right" valign="top"><a id="aa6fd44c74e50ce2081c34461fa50d1a8"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB04A_EIC_EXTINT4</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 4)</td></tr>
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<tr class="separator:aa6fd44c74e50ce2081c34461fa50d1a8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac18cf3795486541d5eb1e0dbfc889193"><td class="memItemLeft" align="right" valign="top"><a id="ac18cf3795486541d5eb1e0dbfc889193"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac18cf3795486541d5eb1e0dbfc889193">PIN_PB04A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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<tr class="memdesc:ac18cf3795486541d5eb1e0dbfc889193"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PB04 External Interrupt Line. <br /></td></tr>
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<tr class="separator:ac18cf3795486541d5eb1e0dbfc889193"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a940a059f979672aa696603fa8f96d882"><td class="memItemLeft" align="right" valign="top"><a id="a940a059f979672aa696603fa8f96d882"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a940a059f979672aa696603fa8f96d882">PIN_PB20A_EIC_EXTINT4</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(52)</td></tr>
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||
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<tr class="memdesc:a940a059f979672aa696603fa8f96d882"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT4 on PB20 mux A. <br /></td></tr>
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<tr class="separator:a940a059f979672aa696603fa8f96d882"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3777907c24098da91560626a0d558944"><td class="memItemLeft" align="right" valign="top"><a id="a3777907c24098da91560626a0d558944"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB20A_EIC_EXTINT4</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a3777907c24098da91560626a0d558944"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0ed9775396f51c873b6cb783835b18ec"><td class="memItemLeft" align="right" valign="top"><a id="a0ed9775396f51c873b6cb783835b18ec"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB20A_EIC_EXTINT4</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a940a059f979672aa696603fa8f96d882">PIN_PB20A_EIC_EXTINT4</a> << 16) | MUX_PB20A_EIC_EXTINT4)</td></tr>
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<tr class="separator:a0ed9775396f51c873b6cb783835b18ec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa91ae5cf592a4d88316a7d311b8b1580"><td class="memItemLeft" align="right" valign="top"><a id="aa91ae5cf592a4d88316a7d311b8b1580"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB20A_EIC_EXTINT4</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 20)</td></tr>
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<tr class="separator:aa91ae5cf592a4d88316a7d311b8b1580"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aaeb10a8a35fdb068eee286e52ee02af4"><td class="memItemLeft" align="right" valign="top"><a id="aaeb10a8a35fdb068eee286e52ee02af4"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aaeb10a8a35fdb068eee286e52ee02af4">PIN_PB20A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
|
||
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<tr class="memdesc:aaeb10a8a35fdb068eee286e52ee02af4"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PB20 External Interrupt Line. <br /></td></tr>
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<tr class="separator:aaeb10a8a35fdb068eee286e52ee02af4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a10685b6be087f0b8fbd969cf8d166325"><td class="memItemLeft" align="right" valign="top"><a id="a10685b6be087f0b8fbd969cf8d166325"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a10685b6be087f0b8fbd969cf8d166325">PIN_PC20A_EIC_EXTINT4</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(84)</td></tr>
|
||
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<tr class="memdesc:a10685b6be087f0b8fbd969cf8d166325"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT4 on PC20 mux A. <br /></td></tr>
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<tr class="separator:a10685b6be087f0b8fbd969cf8d166325"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a39f330e4e5b702e96b8821ea954f1577"><td class="memItemLeft" align="right" valign="top"><a id="a39f330e4e5b702e96b8821ea954f1577"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC20A_EIC_EXTINT4</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a39f330e4e5b702e96b8821ea954f1577"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a74ec0d3fd8cfd9b3cc25023c0ee981f9"><td class="memItemLeft" align="right" valign="top"><a id="a74ec0d3fd8cfd9b3cc25023c0ee981f9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC20A_EIC_EXTINT4</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a10685b6be087f0b8fbd969cf8d166325">PIN_PC20A_EIC_EXTINT4</a> << 16) | MUX_PC20A_EIC_EXTINT4)</td></tr>
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<tr class="separator:a74ec0d3fd8cfd9b3cc25023c0ee981f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0d810b4b9ee0e40c801160ed0048f3d0"><td class="memItemLeft" align="right" valign="top"><a id="a0d810b4b9ee0e40c801160ed0048f3d0"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC20A_EIC_EXTINT4</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 20)</td></tr>
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<tr class="separator:a0d810b4b9ee0e40c801160ed0048f3d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afc62543d33955913a0ad181b6ad806ab"><td class="memItemLeft" align="right" valign="top"><a id="afc62543d33955913a0ad181b6ad806ab"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#afc62543d33955913a0ad181b6ad806ab">PIN_PC20A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
|
||
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<tr class="memdesc:afc62543d33955913a0ad181b6ad806ab"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PC20 External Interrupt Line. <br /></td></tr>
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<tr class="separator:afc62543d33955913a0ad181b6ad806ab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab3a5812b14b4e665e37fe7feffc2ca28"><td class="memItemLeft" align="right" valign="top"><a id="ab3a5812b14b4e665e37fe7feffc2ca28"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab3a5812b14b4e665e37fe7feffc2ca28">PIN_PA05A_EIC_EXTINT5</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
|
||
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<tr class="memdesc:ab3a5812b14b4e665e37fe7feffc2ca28"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT5 on PA05 mux A. <br /></td></tr>
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<tr class="separator:ab3a5812b14b4e665e37fe7feffc2ca28"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a98e3e5363288146c4fd85a57cab91177"><td class="memItemLeft" align="right" valign="top"><a id="a98e3e5363288146c4fd85a57cab91177"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA05A_EIC_EXTINT5</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a98e3e5363288146c4fd85a57cab91177"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a897e7265fe3daaf4409eee3ed91cdc5a"><td class="memItemLeft" align="right" valign="top"><a id="a897e7265fe3daaf4409eee3ed91cdc5a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA05A_EIC_EXTINT5</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ab3a5812b14b4e665e37fe7feffc2ca28">PIN_PA05A_EIC_EXTINT5</a> << 16) | MUX_PA05A_EIC_EXTINT5)</td></tr>
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<tr class="separator:a897e7265fe3daaf4409eee3ed91cdc5a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae224ddad329879027148b80f8b9a8878"><td class="memItemLeft" align="right" valign="top"><a id="ae224ddad329879027148b80f8b9a8878"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA05A_EIC_EXTINT5</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 5)</td></tr>
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||
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<tr class="separator:ae224ddad329879027148b80f8b9a8878"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa627ad4fb760883d9d2415eb5f281bf7"><td class="memItemLeft" align="right" valign="top"><a id="aa627ad4fb760883d9d2415eb5f281bf7"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa627ad4fb760883d9d2415eb5f281bf7">PIN_PA05A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
|
||
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<tr class="memdesc:aa627ad4fb760883d9d2415eb5f281bf7"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PA05 External Interrupt Line. <br /></td></tr>
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<tr class="separator:aa627ad4fb760883d9d2415eb5f281bf7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3b3b91c79d4686e749c0fd1db1451ab3"><td class="memItemLeft" align="right" valign="top"><a id="a3b3b91c79d4686e749c0fd1db1451ab3"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3b3b91c79d4686e749c0fd1db1451ab3">PIN_PA21A_EIC_EXTINT5</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(21)</td></tr>
|
||
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<tr class="memdesc:a3b3b91c79d4686e749c0fd1db1451ab3"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT5 on PA21 mux A. <br /></td></tr>
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<tr class="separator:a3b3b91c79d4686e749c0fd1db1451ab3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a141629c6ef06469903d613d6ae914e5c"><td class="memItemLeft" align="right" valign="top"><a id="a141629c6ef06469903d613d6ae914e5c"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA21A_EIC_EXTINT5</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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||
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<tr class="separator:a141629c6ef06469903d613d6ae914e5c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3b6460f30b71a2bbfa648dfd3a31eb53"><td class="memItemLeft" align="right" valign="top"><a id="a3b6460f30b71a2bbfa648dfd3a31eb53"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA21A_EIC_EXTINT5</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a3b3b91c79d4686e749c0fd1db1451ab3">PIN_PA21A_EIC_EXTINT5</a> << 16) | MUX_PA21A_EIC_EXTINT5)</td></tr>
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<tr class="separator:a3b6460f30b71a2bbfa648dfd3a31eb53"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9e4af585055705a352cd7e9f40865ed3"><td class="memItemLeft" align="right" valign="top"><a id="a9e4af585055705a352cd7e9f40865ed3"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA21A_EIC_EXTINT5</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 21)</td></tr>
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||
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<tr class="memitem:a0c457ef450e9143703eea4a0f32c2e5f"><td class="memItemLeft" align="right" valign="top"><a id="a0c457ef450e9143703eea4a0f32c2e5f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0c457ef450e9143703eea4a0f32c2e5f">PIN_PA21A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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<tr class="memdesc:a0c457ef450e9143703eea4a0f32c2e5f"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PA21 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a0c457ef450e9143703eea4a0f32c2e5f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1784ce6f743bcf2969d6f8e8f68ddb6e"><td class="memItemLeft" align="right" valign="top"><a id="a1784ce6f743bcf2969d6f8e8f68ddb6e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1784ce6f743bcf2969d6f8e8f68ddb6e">PIN_PB05A_EIC_EXTINT5</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(37)</td></tr>
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<tr class="memdesc:a1784ce6f743bcf2969d6f8e8f68ddb6e"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT5 on PB05 mux A. <br /></td></tr>
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<tr class="separator:a1784ce6f743bcf2969d6f8e8f68ddb6e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8258e6b15a8be8aaeb53a872cb445367"><td class="memItemLeft" align="right" valign="top"><a id="a8258e6b15a8be8aaeb53a872cb445367"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB05A_EIC_EXTINT5</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a8258e6b15a8be8aaeb53a872cb445367"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af7569c445701797dbe2add59b7bda2ca"><td class="memItemLeft" align="right" valign="top"><a id="af7569c445701797dbe2add59b7bda2ca"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB05A_EIC_EXTINT5</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a1784ce6f743bcf2969d6f8e8f68ddb6e">PIN_PB05A_EIC_EXTINT5</a> << 16) | MUX_PB05A_EIC_EXTINT5)</td></tr>
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<tr class="memitem:a23a8bc51bec664451ae483fbbb997d11"><td class="memItemLeft" align="right" valign="top"><a id="a23a8bc51bec664451ae483fbbb997d11"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB05A_EIC_EXTINT5</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 5)</td></tr>
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<tr class="separator:a23a8bc51bec664451ae483fbbb997d11"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2ea02d04015a7dcf12f503abbc00e96b"><td class="memItemLeft" align="right" valign="top"><a id="a2ea02d04015a7dcf12f503abbc00e96b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2ea02d04015a7dcf12f503abbc00e96b">PIN_PB05A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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<tr class="memdesc:a2ea02d04015a7dcf12f503abbc00e96b"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PB05 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a2ea02d04015a7dcf12f503abbc00e96b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4108f90fa6f73a09eaffaaa1bce9ff82"><td class="memItemLeft" align="right" valign="top"><a id="a4108f90fa6f73a09eaffaaa1bce9ff82"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4108f90fa6f73a09eaffaaa1bce9ff82">PIN_PB21A_EIC_EXTINT5</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(53)</td></tr>
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<tr class="memdesc:a4108f90fa6f73a09eaffaaa1bce9ff82"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT5 on PB21 mux A. <br /></td></tr>
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<tr class="separator:a4108f90fa6f73a09eaffaaa1bce9ff82"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af0dacacabcebf355dfdc98a861d9e1fa"><td class="memItemLeft" align="right" valign="top"><a id="af0dacacabcebf355dfdc98a861d9e1fa"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB21A_EIC_EXTINT5</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:af0dacacabcebf355dfdc98a861d9e1fa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a93643c0949effaa3b12abfc5a179963b"><td class="memItemLeft" align="right" valign="top"><a id="a93643c0949effaa3b12abfc5a179963b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB21A_EIC_EXTINT5</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a4108f90fa6f73a09eaffaaa1bce9ff82">PIN_PB21A_EIC_EXTINT5</a> << 16) | MUX_PB21A_EIC_EXTINT5)</td></tr>
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<tr class="separator:a93643c0949effaa3b12abfc5a179963b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af76620ec5c3f87a24ec65b92f3033564"><td class="memItemLeft" align="right" valign="top"><a id="af76620ec5c3f87a24ec65b92f3033564"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB21A_EIC_EXTINT5</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 21)</td></tr>
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<tr class="separator:af76620ec5c3f87a24ec65b92f3033564"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa60a17a6b56b26d23018ed497514bb10"><td class="memItemLeft" align="right" valign="top"><a id="aa60a17a6b56b26d23018ed497514bb10"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa60a17a6b56b26d23018ed497514bb10">PIN_PB21A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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||
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<tr class="memdesc:aa60a17a6b56b26d23018ed497514bb10"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PB21 External Interrupt Line. <br /></td></tr>
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<tr class="separator:aa60a17a6b56b26d23018ed497514bb10"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afb3a787a6d8ac84e614a4b1ea48ae35b"><td class="memItemLeft" align="right" valign="top"><a id="afb3a787a6d8ac84e614a4b1ea48ae35b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#afb3a787a6d8ac84e614a4b1ea48ae35b">PIN_PC05A_EIC_EXTINT5</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(69)</td></tr>
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||
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<tr class="memdesc:afb3a787a6d8ac84e614a4b1ea48ae35b"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT5 on PC05 mux A. <br /></td></tr>
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<tr class="separator:afb3a787a6d8ac84e614a4b1ea48ae35b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a711380c280f32036c09449229637ef56"><td class="memItemLeft" align="right" valign="top"><a id="a711380c280f32036c09449229637ef56"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC05A_EIC_EXTINT5</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a711380c280f32036c09449229637ef56"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2412e8a08e6c24f9d36f8732b2ce5ec2"><td class="memItemLeft" align="right" valign="top"><a id="a2412e8a08e6c24f9d36f8732b2ce5ec2"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC05A_EIC_EXTINT5</b>   ((<a class="el" href="pio_2same54p20a_8h.html#afb3a787a6d8ac84e614a4b1ea48ae35b">PIN_PC05A_EIC_EXTINT5</a> << 16) | MUX_PC05A_EIC_EXTINT5)</td></tr>
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<tr class="separator:a2412e8a08e6c24f9d36f8732b2ce5ec2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acaa003eb827007d02cc02229b422f3ad"><td class="memItemLeft" align="right" valign="top"><a id="acaa003eb827007d02cc02229b422f3ad"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC05A_EIC_EXTINT5</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 5)</td></tr>
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<tr class="separator:acaa003eb827007d02cc02229b422f3ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0ae7530209f4c97c662d2d19161c87bd"><td class="memItemLeft" align="right" valign="top"><a id="a0ae7530209f4c97c662d2d19161c87bd"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0ae7530209f4c97c662d2d19161c87bd">PIN_PC05A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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||
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<tr class="memdesc:a0ae7530209f4c97c662d2d19161c87bd"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PC05 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a0ae7530209f4c97c662d2d19161c87bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab37b60dceb30edb3b9b228b2f8639a7c"><td class="memItemLeft" align="right" valign="top"><a id="ab37b60dceb30edb3b9b228b2f8639a7c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab37b60dceb30edb3b9b228b2f8639a7c">PIN_PC21A_EIC_EXTINT5</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(85)</td></tr>
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||
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<tr class="memdesc:ab37b60dceb30edb3b9b228b2f8639a7c"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT5 on PC21 mux A. <br /></td></tr>
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<tr class="separator:ab37b60dceb30edb3b9b228b2f8639a7c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a817048e77fab42aaee7b90aafe68927e"><td class="memItemLeft" align="right" valign="top"><a id="a817048e77fab42aaee7b90aafe68927e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC21A_EIC_EXTINT5</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a817048e77fab42aaee7b90aafe68927e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4c3f8f6e24c45d932cee573326477b8f"><td class="memItemLeft" align="right" valign="top"><a id="a4c3f8f6e24c45d932cee573326477b8f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC21A_EIC_EXTINT5</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ab37b60dceb30edb3b9b228b2f8639a7c">PIN_PC21A_EIC_EXTINT5</a> << 16) | MUX_PC21A_EIC_EXTINT5)</td></tr>
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<tr class="separator:a4c3f8f6e24c45d932cee573326477b8f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae063cd2fdeeb35fc5b59f6c68c88950e"><td class="memItemLeft" align="right" valign="top"><a id="ae063cd2fdeeb35fc5b59f6c68c88950e"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC21A_EIC_EXTINT5</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 21)</td></tr>
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<tr class="separator:ae063cd2fdeeb35fc5b59f6c68c88950e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a754c03e54d118ce8af8bb3891992f5b3"><td class="memItemLeft" align="right" valign="top"><a id="a754c03e54d118ce8af8bb3891992f5b3"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a754c03e54d118ce8af8bb3891992f5b3">PIN_PC21A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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||
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<tr class="memdesc:a754c03e54d118ce8af8bb3891992f5b3"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PC21 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a754c03e54d118ce8af8bb3891992f5b3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5840dd08c2b6e1baf335ef2078c14bce"><td class="memItemLeft" align="right" valign="top"><a id="a5840dd08c2b6e1baf335ef2078c14bce"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5840dd08c2b6e1baf335ef2078c14bce">PIN_PA06A_EIC_EXTINT6</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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||
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<tr class="memdesc:a5840dd08c2b6e1baf335ef2078c14bce"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT6 on PA06 mux A. <br /></td></tr>
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<tr class="separator:a5840dd08c2b6e1baf335ef2078c14bce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abadf4489f0aca056eef6db2c4b69607b"><td class="memItemLeft" align="right" valign="top"><a id="abadf4489f0aca056eef6db2c4b69607b"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA06A_EIC_EXTINT6</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:abadf4489f0aca056eef6db2c4b69607b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8333375e6249d85a69310b526b7ddd60"><td class="memItemLeft" align="right" valign="top"><a id="a8333375e6249d85a69310b526b7ddd60"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA06A_EIC_EXTINT6</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a5840dd08c2b6e1baf335ef2078c14bce">PIN_PA06A_EIC_EXTINT6</a> << 16) | MUX_PA06A_EIC_EXTINT6)</td></tr>
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<tr class="separator:a8333375e6249d85a69310b526b7ddd60"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abf76a00ace69ae9a5c1213ced23caa9d"><td class="memItemLeft" align="right" valign="top"><a id="abf76a00ace69ae9a5c1213ced23caa9d"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA06A_EIC_EXTINT6</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 6)</td></tr>
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<tr class="separator:abf76a00ace69ae9a5c1213ced23caa9d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a42510dcf38687fa280faa25504561fb7"><td class="memItemLeft" align="right" valign="top"><a id="a42510dcf38687fa280faa25504561fb7"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a42510dcf38687fa280faa25504561fb7">PIN_PA06A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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||
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<tr class="memdesc:a42510dcf38687fa280faa25504561fb7"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PA06 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a42510dcf38687fa280faa25504561fb7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab3bc619f3136780a6c4a3b0050c1c378"><td class="memItemLeft" align="right" valign="top"><a id="ab3bc619f3136780a6c4a3b0050c1c378"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab3bc619f3136780a6c4a3b0050c1c378">PIN_PA22A_EIC_EXTINT6</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(22)</td></tr>
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||
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<tr class="memdesc:ab3bc619f3136780a6c4a3b0050c1c378"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT6 on PA22 mux A. <br /></td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA22A_EIC_EXTINT6</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="memitem:a22ac84c431debd7180068af377aedeb9"><td class="memItemLeft" align="right" valign="top"><a id="a22ac84c431debd7180068af377aedeb9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA22A_EIC_EXTINT6</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ab3bc619f3136780a6c4a3b0050c1c378">PIN_PA22A_EIC_EXTINT6</a> << 16) | MUX_PA22A_EIC_EXTINT6)</td></tr>
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<tr class="memitem:a722902ba66c190211cab7ef38f4f71e5"><td class="memItemLeft" align="right" valign="top"><a id="a722902ba66c190211cab7ef38f4f71e5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA22A_EIC_EXTINT6</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 22)</td></tr>
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<tr class="memitem:a328966c338ba0a96eaaf67690e5617e7"><td class="memItemLeft" align="right" valign="top"><a id="a328966c338ba0a96eaaf67690e5617e7"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a328966c338ba0a96eaaf67690e5617e7">PIN_PA22A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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<tr class="memdesc:a328966c338ba0a96eaaf67690e5617e7"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PA22 External Interrupt Line. <br /></td></tr>
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<tr class="memitem:ad95c6f9a2f84236bfbb75eae2511fd3a"><td class="memItemLeft" align="right" valign="top"><a id="ad95c6f9a2f84236bfbb75eae2511fd3a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad95c6f9a2f84236bfbb75eae2511fd3a">PIN_PB06A_EIC_EXTINT6</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(38)</td></tr>
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<tr class="memdesc:ad95c6f9a2f84236bfbb75eae2511fd3a"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT6 on PB06 mux A. <br /></td></tr>
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<tr class="memitem:a9d2ef9e901ac3dedb374c977de06043c"><td class="memItemLeft" align="right" valign="top"><a id="a9d2ef9e901ac3dedb374c977de06043c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB06A_EIC_EXTINT6</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a9d2ef9e901ac3dedb374c977de06043c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac95bf37a2fe2cecfd1780a076e0691bb"><td class="memItemLeft" align="right" valign="top"><a id="ac95bf37a2fe2cecfd1780a076e0691bb"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB06A_EIC_EXTINT6</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ad95c6f9a2f84236bfbb75eae2511fd3a">PIN_PB06A_EIC_EXTINT6</a> << 16) | MUX_PB06A_EIC_EXTINT6)</td></tr>
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<tr class="memitem:a53c7a36fa4c73df35ea0432543849581"><td class="memItemLeft" align="right" valign="top"><a id="a53c7a36fa4c73df35ea0432543849581"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB06A_EIC_EXTINT6</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 6)</td></tr>
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<tr class="separator:a53c7a36fa4c73df35ea0432543849581"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acb0d8efe496f54a2f4fd8a85ac5e62e6"><td class="memItemLeft" align="right" valign="top"><a id="acb0d8efe496f54a2f4fd8a85ac5e62e6"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#acb0d8efe496f54a2f4fd8a85ac5e62e6">PIN_PB06A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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<tr class="memdesc:acb0d8efe496f54a2f4fd8a85ac5e62e6"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PB06 External Interrupt Line. <br /></td></tr>
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<tr class="separator:acb0d8efe496f54a2f4fd8a85ac5e62e6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3d86b2b73a6ea21b68f1c04389b6c27a"><td class="memItemLeft" align="right" valign="top"><a id="a3d86b2b73a6ea21b68f1c04389b6c27a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3d86b2b73a6ea21b68f1c04389b6c27a">PIN_PB22A_EIC_EXTINT6</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(54)</td></tr>
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<tr class="memdesc:a3d86b2b73a6ea21b68f1c04389b6c27a"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT6 on PB22 mux A. <br /></td></tr>
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<tr class="memitem:af5ce5ff6d9b3d26181716bf73ae3d377"><td class="memItemLeft" align="right" valign="top"><a id="af5ce5ff6d9b3d26181716bf73ae3d377"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB22A_EIC_EXTINT6</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:af5ce5ff6d9b3d26181716bf73ae3d377"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa5cb342a8e65afe153d303bf0391ea26"><td class="memItemLeft" align="right" valign="top"><a id="aa5cb342a8e65afe153d303bf0391ea26"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB22A_EIC_EXTINT6</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a3d86b2b73a6ea21b68f1c04389b6c27a">PIN_PB22A_EIC_EXTINT6</a> << 16) | MUX_PB22A_EIC_EXTINT6)</td></tr>
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<tr class="memitem:ac79719cfc0569872d8b0820b5716840e"><td class="memItemLeft" align="right" valign="top"><a id="ac79719cfc0569872d8b0820b5716840e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB22A_EIC_EXTINT6</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 22)</td></tr>
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<tr class="separator:ac79719cfc0569872d8b0820b5716840e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa23bff92eaba130a68175901064e7960"><td class="memItemLeft" align="right" valign="top"><a id="aa23bff92eaba130a68175901064e7960"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa23bff92eaba130a68175901064e7960">PIN_PB22A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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<tr class="memdesc:aa23bff92eaba130a68175901064e7960"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PB22 External Interrupt Line. <br /></td></tr>
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<tr class="separator:aa23bff92eaba130a68175901064e7960"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a21443ac8d7d6084c91f10c3e61d5a057"><td class="memItemLeft" align="right" valign="top"><a id="a21443ac8d7d6084c91f10c3e61d5a057"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a21443ac8d7d6084c91f10c3e61d5a057">PIN_PC06A_EIC_EXTINT6</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(70)</td></tr>
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<tr class="memdesc:a21443ac8d7d6084c91f10c3e61d5a057"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT6 on PC06 mux A. <br /></td></tr>
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<tr class="separator:a21443ac8d7d6084c91f10c3e61d5a057"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acbccd9b1fa4ba69e6c6261df1e64264a"><td class="memItemLeft" align="right" valign="top"><a id="acbccd9b1fa4ba69e6c6261df1e64264a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC06A_EIC_EXTINT6</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:acbccd9b1fa4ba69e6c6261df1e64264a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afe0495fd93f0541d08b5c1674402d0fa"><td class="memItemLeft" align="right" valign="top"><a id="afe0495fd93f0541d08b5c1674402d0fa"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC06A_EIC_EXTINT6</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a21443ac8d7d6084c91f10c3e61d5a057">PIN_PC06A_EIC_EXTINT6</a> << 16) | MUX_PC06A_EIC_EXTINT6)</td></tr>
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<tr class="memitem:ac0e38cebe94029fda9727635f5dd7a64"><td class="memItemLeft" align="right" valign="top"><a id="ac0e38cebe94029fda9727635f5dd7a64"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC06A_EIC_EXTINT6</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 6)</td></tr>
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<tr class="separator:ac0e38cebe94029fda9727635f5dd7a64"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4f5a33ca3710ef24b0b080bd0a8c369b"><td class="memItemLeft" align="right" valign="top"><a id="a4f5a33ca3710ef24b0b080bd0a8c369b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4f5a33ca3710ef24b0b080bd0a8c369b">PIN_PC06A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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<tr class="memdesc:a4f5a33ca3710ef24b0b080bd0a8c369b"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PC06 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a4f5a33ca3710ef24b0b080bd0a8c369b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afdb42a71714800264c9e3df2059ddc66"><td class="memItemLeft" align="right" valign="top"><a id="afdb42a71714800264c9e3df2059ddc66"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#afdb42a71714800264c9e3df2059ddc66">PIN_PA07A_EIC_EXTINT7</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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<tr class="memdesc:afdb42a71714800264c9e3df2059ddc66"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT7 on PA07 mux A. <br /></td></tr>
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<tr class="memitem:a18960827e58593bd00352677b8ca4908"><td class="memItemLeft" align="right" valign="top"><a id="a18960827e58593bd00352677b8ca4908"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA07A_EIC_EXTINT7</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a18960827e58593bd00352677b8ca4908"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:affff843ed4544b61bea125573704f436"><td class="memItemLeft" align="right" valign="top"><a id="affff843ed4544b61bea125573704f436"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA07A_EIC_EXTINT7</b>   ((<a class="el" href="pio_2same54p20a_8h.html#afdb42a71714800264c9e3df2059ddc66">PIN_PA07A_EIC_EXTINT7</a> << 16) | MUX_PA07A_EIC_EXTINT7)</td></tr>
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<tr class="separator:affff843ed4544b61bea125573704f436"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acfd410ec16223cd46c237fd5bdcf613a"><td class="memItemLeft" align="right" valign="top"><a id="acfd410ec16223cd46c237fd5bdcf613a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA07A_EIC_EXTINT7</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 7)</td></tr>
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<tr class="separator:acfd410ec16223cd46c237fd5bdcf613a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a93a0531700ef575536efd7099dbe4042"><td class="memItemLeft" align="right" valign="top"><a id="a93a0531700ef575536efd7099dbe4042"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a93a0531700ef575536efd7099dbe4042">PIN_PA07A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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<tr class="memdesc:a93a0531700ef575536efd7099dbe4042"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PA07 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a93a0531700ef575536efd7099dbe4042"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6dfe39bc5e36bf0ab08a94f59df5b5ca"><td class="memItemLeft" align="right" valign="top"><a id="a6dfe39bc5e36bf0ab08a94f59df5b5ca"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6dfe39bc5e36bf0ab08a94f59df5b5ca">PIN_PA23A_EIC_EXTINT7</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(23)</td></tr>
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<tr class="memdesc:a6dfe39bc5e36bf0ab08a94f59df5b5ca"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT7 on PA23 mux A. <br /></td></tr>
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<tr class="separator:a6dfe39bc5e36bf0ab08a94f59df5b5ca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aff89b3a903c65872d5657a3e7c141edb"><td class="memItemLeft" align="right" valign="top"><a id="aff89b3a903c65872d5657a3e7c141edb"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA23A_EIC_EXTINT7</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:aff89b3a903c65872d5657a3e7c141edb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a67f08ce6d770511d72f4539f961bcc96"><td class="memItemLeft" align="right" valign="top"><a id="a67f08ce6d770511d72f4539f961bcc96"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA23A_EIC_EXTINT7</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a6dfe39bc5e36bf0ab08a94f59df5b5ca">PIN_PA23A_EIC_EXTINT7</a> << 16) | MUX_PA23A_EIC_EXTINT7)</td></tr>
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<tr class="separator:a67f08ce6d770511d72f4539f961bcc96"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2494bcbdb52540f4de33e3d4cfac26fb"><td class="memItemLeft" align="right" valign="top"><a id="a2494bcbdb52540f4de33e3d4cfac26fb"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA23A_EIC_EXTINT7</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 23)</td></tr>
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<tr class="separator:a2494bcbdb52540f4de33e3d4cfac26fb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aec7c5d6aa48f6b16ad2e33c5a0839906"><td class="memItemLeft" align="right" valign="top"><a id="aec7c5d6aa48f6b16ad2e33c5a0839906"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aec7c5d6aa48f6b16ad2e33c5a0839906">PIN_PA23A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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<tr class="memdesc:aec7c5d6aa48f6b16ad2e33c5a0839906"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PA23 External Interrupt Line. <br /></td></tr>
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<tr class="separator:aec7c5d6aa48f6b16ad2e33c5a0839906"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aebbb52da93fec5f213a6a128aec88636"><td class="memItemLeft" align="right" valign="top"><a id="aebbb52da93fec5f213a6a128aec88636"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aebbb52da93fec5f213a6a128aec88636">PIN_PB07A_EIC_EXTINT7</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(39)</td></tr>
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<tr class="memdesc:aebbb52da93fec5f213a6a128aec88636"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT7 on PB07 mux A. <br /></td></tr>
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<tr class="separator:aebbb52da93fec5f213a6a128aec88636"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1b0c60d6edcc0cefc4c6ae2e7ba79c5f"><td class="memItemLeft" align="right" valign="top"><a id="a1b0c60d6edcc0cefc4c6ae2e7ba79c5f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB07A_EIC_EXTINT7</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a1b0c60d6edcc0cefc4c6ae2e7ba79c5f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acd0bc9103ec510624fe4eeb63600cdcf"><td class="memItemLeft" align="right" valign="top"><a id="acd0bc9103ec510624fe4eeb63600cdcf"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB07A_EIC_EXTINT7</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aebbb52da93fec5f213a6a128aec88636">PIN_PB07A_EIC_EXTINT7</a> << 16) | MUX_PB07A_EIC_EXTINT7)</td></tr>
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<tr class="separator:acd0bc9103ec510624fe4eeb63600cdcf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abb7806155489192e78d797a3937d4333"><td class="memItemLeft" align="right" valign="top"><a id="abb7806155489192e78d797a3937d4333"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB07A_EIC_EXTINT7</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 7)</td></tr>
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<tr class="separator:abb7806155489192e78d797a3937d4333"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a74530ce5c1d26c86980bb3909094e656"><td class="memItemLeft" align="right" valign="top"><a id="a74530ce5c1d26c86980bb3909094e656"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a74530ce5c1d26c86980bb3909094e656">PIN_PB07A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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<tr class="memdesc:a74530ce5c1d26c86980bb3909094e656"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PB07 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a74530ce5c1d26c86980bb3909094e656"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4def37025a5b72ef3c5d8c3dfb02a114"><td class="memItemLeft" align="right" valign="top"><a id="a4def37025a5b72ef3c5d8c3dfb02a114"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4def37025a5b72ef3c5d8c3dfb02a114">PIN_PB23A_EIC_EXTINT7</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(55)</td></tr>
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||
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<tr class="memdesc:a4def37025a5b72ef3c5d8c3dfb02a114"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT7 on PB23 mux A. <br /></td></tr>
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<tr class="separator:a4def37025a5b72ef3c5d8c3dfb02a114"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1ac1dc1ce0a4ad3fe935861081e80468"><td class="memItemLeft" align="right" valign="top"><a id="a1ac1dc1ce0a4ad3fe935861081e80468"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB23A_EIC_EXTINT7</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a1ac1dc1ce0a4ad3fe935861081e80468"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acd372d9970b59fc40de1869007e825e0"><td class="memItemLeft" align="right" valign="top"><a id="acd372d9970b59fc40de1869007e825e0"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB23A_EIC_EXTINT7</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a4def37025a5b72ef3c5d8c3dfb02a114">PIN_PB23A_EIC_EXTINT7</a> << 16) | MUX_PB23A_EIC_EXTINT7)</td></tr>
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<tr class="separator:acd372d9970b59fc40de1869007e825e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa0ef48da15aa613dc2696c9ee1392fd4"><td class="memItemLeft" align="right" valign="top"><a id="aa0ef48da15aa613dc2696c9ee1392fd4"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB23A_EIC_EXTINT7</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 23)</td></tr>
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<tr class="separator:aa0ef48da15aa613dc2696c9ee1392fd4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af38be5fde44dfd55bbdcf4bf7ca4b58a"><td class="memItemLeft" align="right" valign="top"><a id="af38be5fde44dfd55bbdcf4bf7ca4b58a"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af38be5fde44dfd55bbdcf4bf7ca4b58a">PIN_PB23A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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||
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<tr class="memdesc:af38be5fde44dfd55bbdcf4bf7ca4b58a"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PB23 External Interrupt Line. <br /></td></tr>
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<tr class="separator:af38be5fde44dfd55bbdcf4bf7ca4b58a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5392ffb9d2a08114d04e6c902b08b167"><td class="memItemLeft" align="right" valign="top"><a id="a5392ffb9d2a08114d04e6c902b08b167"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5392ffb9d2a08114d04e6c902b08b167">PIN_PA24A_EIC_EXTINT8</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(24)</td></tr>
|
||
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<tr class="memdesc:a5392ffb9d2a08114d04e6c902b08b167"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT8 on PA24 mux A. <br /></td></tr>
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<tr class="separator:a5392ffb9d2a08114d04e6c902b08b167"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9045dc54ca1a99e25bb65c460109b6ad"><td class="memItemLeft" align="right" valign="top"><a id="a9045dc54ca1a99e25bb65c460109b6ad"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA24A_EIC_EXTINT8</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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||
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<tr class="separator:a9045dc54ca1a99e25bb65c460109b6ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a18c1f0223e2a4d38400cb63e76bb41aa"><td class="memItemLeft" align="right" valign="top"><a id="a18c1f0223e2a4d38400cb63e76bb41aa"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA24A_EIC_EXTINT8</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a5392ffb9d2a08114d04e6c902b08b167">PIN_PA24A_EIC_EXTINT8</a> << 16) | MUX_PA24A_EIC_EXTINT8)</td></tr>
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<tr class="separator:a18c1f0223e2a4d38400cb63e76bb41aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae215561f8f3267e5ca9c6005a386be8c"><td class="memItemLeft" align="right" valign="top"><a id="ae215561f8f3267e5ca9c6005a386be8c"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA24A_EIC_EXTINT8</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 24)</td></tr>
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||
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<tr class="separator:ae215561f8f3267e5ca9c6005a386be8c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4709be5f65733369b1dcbc2b6563656e"><td class="memItemLeft" align="right" valign="top"><a id="a4709be5f65733369b1dcbc2b6563656e"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4709be5f65733369b1dcbc2b6563656e">PIN_PA24A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
|
||
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<tr class="memdesc:a4709be5f65733369b1dcbc2b6563656e"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PA24 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a4709be5f65733369b1dcbc2b6563656e"><td class="memSeparator" colspan="2"> </td></tr>
|
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<tr class="memitem:ad61d23a293dd02bc4fa8c32841f0a8a2"><td class="memItemLeft" align="right" valign="top"><a id="ad61d23a293dd02bc4fa8c32841f0a8a2"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad61d23a293dd02bc4fa8c32841f0a8a2">PIN_PB08A_EIC_EXTINT8</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(40)</td></tr>
|
||
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<tr class="memdesc:ad61d23a293dd02bc4fa8c32841f0a8a2"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT8 on PB08 mux A. <br /></td></tr>
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<tr class="separator:ad61d23a293dd02bc4fa8c32841f0a8a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a88eb116656a42c5b6c86b2a3c6ae5ae5"><td class="memItemLeft" align="right" valign="top"><a id="a88eb116656a42c5b6c86b2a3c6ae5ae5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB08A_EIC_EXTINT8</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a88eb116656a42c5b6c86b2a3c6ae5ae5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a58c868684e8fe463b369de38fee19341"><td class="memItemLeft" align="right" valign="top"><a id="a58c868684e8fe463b369de38fee19341"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB08A_EIC_EXTINT8</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ad61d23a293dd02bc4fa8c32841f0a8a2">PIN_PB08A_EIC_EXTINT8</a> << 16) | MUX_PB08A_EIC_EXTINT8)</td></tr>
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<tr class="separator:a58c868684e8fe463b369de38fee19341"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a78606c072f3b2b820a3e9a207e54fa82"><td class="memItemLeft" align="right" valign="top"><a id="a78606c072f3b2b820a3e9a207e54fa82"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB08A_EIC_EXTINT8</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 8)</td></tr>
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||
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<tr class="separator:a78606c072f3b2b820a3e9a207e54fa82"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab53200d5efdcb033f3da26a7be70e8f3"><td class="memItemLeft" align="right" valign="top"><a id="ab53200d5efdcb033f3da26a7be70e8f3"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab53200d5efdcb033f3da26a7be70e8f3">PIN_PB08A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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||
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<tr class="memdesc:ab53200d5efdcb033f3da26a7be70e8f3"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PB08 External Interrupt Line. <br /></td></tr>
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<tr class="separator:ab53200d5efdcb033f3da26a7be70e8f3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3b2bef04d823b1f5eb2e1013d93eae13"><td class="memItemLeft" align="right" valign="top"><a id="a3b2bef04d823b1f5eb2e1013d93eae13"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3b2bef04d823b1f5eb2e1013d93eae13">PIN_PB24A_EIC_EXTINT8</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(56)</td></tr>
|
||
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<tr class="memdesc:a3b2bef04d823b1f5eb2e1013d93eae13"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT8 on PB24 mux A. <br /></td></tr>
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<tr class="separator:a3b2bef04d823b1f5eb2e1013d93eae13"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a976896e4a576bd103553db88f1ef3024"><td class="memItemLeft" align="right" valign="top"><a id="a976896e4a576bd103553db88f1ef3024"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB24A_EIC_EXTINT8</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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||
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<tr class="separator:a976896e4a576bd103553db88f1ef3024"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab9b4a2159a3eb77f89f0cb74b9f6a147"><td class="memItemLeft" align="right" valign="top"><a id="ab9b4a2159a3eb77f89f0cb74b9f6a147"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB24A_EIC_EXTINT8</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a3b2bef04d823b1f5eb2e1013d93eae13">PIN_PB24A_EIC_EXTINT8</a> << 16) | MUX_PB24A_EIC_EXTINT8)</td></tr>
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<tr class="separator:ab9b4a2159a3eb77f89f0cb74b9f6a147"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac78b2894816754729c978cadf1c9e268"><td class="memItemLeft" align="right" valign="top"><a id="ac78b2894816754729c978cadf1c9e268"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB24A_EIC_EXTINT8</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 24)</td></tr>
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<tr class="separator:ac78b2894816754729c978cadf1c9e268"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae4a7b797304e5f352d073fd4673376d9"><td class="memItemLeft" align="right" valign="top"><a id="ae4a7b797304e5f352d073fd4673376d9"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae4a7b797304e5f352d073fd4673376d9">PIN_PB24A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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||
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<tr class="memdesc:ae4a7b797304e5f352d073fd4673376d9"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PB24 External Interrupt Line. <br /></td></tr>
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<tr class="separator:ae4a7b797304e5f352d073fd4673376d9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a891a9e1bb27a399c9aa9097085059ddb"><td class="memItemLeft" align="right" valign="top"><a id="a891a9e1bb27a399c9aa9097085059ddb"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a891a9e1bb27a399c9aa9097085059ddb">PIN_PC24A_EIC_EXTINT8</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(88)</td></tr>
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<tr class="memdesc:a891a9e1bb27a399c9aa9097085059ddb"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT8 on PC24 mux A. <br /></td></tr>
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<tr class="memitem:a4cac0a517a91d4283e497f46b44c7f4b"><td class="memItemLeft" align="right" valign="top"><a id="a4cac0a517a91d4283e497f46b44c7f4b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC24A_EIC_EXTINT8</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a4cac0a517a91d4283e497f46b44c7f4b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:affee09392e6f2da37c903ed8e4c80cd7"><td class="memItemLeft" align="right" valign="top"><a id="affee09392e6f2da37c903ed8e4c80cd7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC24A_EIC_EXTINT8</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a891a9e1bb27a399c9aa9097085059ddb">PIN_PC24A_EIC_EXTINT8</a> << 16) | MUX_PC24A_EIC_EXTINT8)</td></tr>
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<tr class="separator:affee09392e6f2da37c903ed8e4c80cd7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab7dd3acda3be2664388fddb12830462d"><td class="memItemLeft" align="right" valign="top"><a id="ab7dd3acda3be2664388fddb12830462d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC24A_EIC_EXTINT8</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 24)</td></tr>
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<tr class="separator:ab7dd3acda3be2664388fddb12830462d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a058921d5bed2542797dbd7dfd192f4fe"><td class="memItemLeft" align="right" valign="top"><a id="a058921d5bed2542797dbd7dfd192f4fe"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a058921d5bed2542797dbd7dfd192f4fe">PIN_PC24A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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<tr class="memdesc:a058921d5bed2542797dbd7dfd192f4fe"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PC24 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a058921d5bed2542797dbd7dfd192f4fe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1e78051967cbcffa4986bbcd1bd69c4b"><td class="memItemLeft" align="right" valign="top"><a id="a1e78051967cbcffa4986bbcd1bd69c4b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1e78051967cbcffa4986bbcd1bd69c4b">PIN_PA09A_EIC_EXTINT9</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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<tr class="memdesc:a1e78051967cbcffa4986bbcd1bd69c4b"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT9 on PA09 mux A. <br /></td></tr>
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<tr class="separator:a1e78051967cbcffa4986bbcd1bd69c4b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a44ad347925ab7aa0582188d6d31d96ac"><td class="memItemLeft" align="right" valign="top"><a id="a44ad347925ab7aa0582188d6d31d96ac"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA09A_EIC_EXTINT9</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a44ad347925ab7aa0582188d6d31d96ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afbdac1cdb6b0df4154d70ded5bc3ab26"><td class="memItemLeft" align="right" valign="top"><a id="afbdac1cdb6b0df4154d70ded5bc3ab26"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA09A_EIC_EXTINT9</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a1e78051967cbcffa4986bbcd1bd69c4b">PIN_PA09A_EIC_EXTINT9</a> << 16) | MUX_PA09A_EIC_EXTINT9)</td></tr>
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<tr class="separator:afbdac1cdb6b0df4154d70ded5bc3ab26"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab144d41c98cefbf15b38dd45ddeabc8d"><td class="memItemLeft" align="right" valign="top"><a id="ab144d41c98cefbf15b38dd45ddeabc8d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA09A_EIC_EXTINT9</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 9)</td></tr>
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<tr class="separator:ab144d41c98cefbf15b38dd45ddeabc8d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a10b3e3f45849bd53593acf73431f9b4d"><td class="memItemLeft" align="right" valign="top"><a id="a10b3e3f45849bd53593acf73431f9b4d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a10b3e3f45849bd53593acf73431f9b4d">PIN_PA09A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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<tr class="memdesc:a10b3e3f45849bd53593acf73431f9b4d"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PA09 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a10b3e3f45849bd53593acf73431f9b4d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a39df155b7196d41fd91a93b55c1a3b4d"><td class="memItemLeft" align="right" valign="top"><a id="a39df155b7196d41fd91a93b55c1a3b4d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a39df155b7196d41fd91a93b55c1a3b4d">PIN_PA25A_EIC_EXTINT9</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(25)</td></tr>
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||
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<tr class="memdesc:a39df155b7196d41fd91a93b55c1a3b4d"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT9 on PA25 mux A. <br /></td></tr>
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<tr class="separator:a39df155b7196d41fd91a93b55c1a3b4d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a01c358bb74781b86fbc4f0b89c265c6c"><td class="memItemLeft" align="right" valign="top"><a id="a01c358bb74781b86fbc4f0b89c265c6c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA25A_EIC_EXTINT9</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a01c358bb74781b86fbc4f0b89c265c6c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a17e3c837429e2bbfca12802181032050"><td class="memItemLeft" align="right" valign="top"><a id="a17e3c837429e2bbfca12802181032050"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA25A_EIC_EXTINT9</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a39df155b7196d41fd91a93b55c1a3b4d">PIN_PA25A_EIC_EXTINT9</a> << 16) | MUX_PA25A_EIC_EXTINT9)</td></tr>
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<tr class="separator:a17e3c837429e2bbfca12802181032050"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0de19c39ee53360d3114f2f57b9fc966"><td class="memItemLeft" align="right" valign="top"><a id="a0de19c39ee53360d3114f2f57b9fc966"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA25A_EIC_EXTINT9</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 25)</td></tr>
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<tr class="separator:a0de19c39ee53360d3114f2f57b9fc966"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab8ee9293ffea6d03e4b0307f129469bb"><td class="memItemLeft" align="right" valign="top"><a id="ab8ee9293ffea6d03e4b0307f129469bb"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab8ee9293ffea6d03e4b0307f129469bb">PIN_PA25A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
|
||
|
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<tr class="memdesc:ab8ee9293ffea6d03e4b0307f129469bb"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PA25 External Interrupt Line. <br /></td></tr>
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<tr class="separator:ab8ee9293ffea6d03e4b0307f129469bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a54511e0d8c786b2e9f9254986fd0218c"><td class="memItemLeft" align="right" valign="top"><a id="a54511e0d8c786b2e9f9254986fd0218c"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a54511e0d8c786b2e9f9254986fd0218c">PIN_PB09A_EIC_EXTINT9</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(41)</td></tr>
|
||
|
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<tr class="memdesc:a54511e0d8c786b2e9f9254986fd0218c"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT9 on PB09 mux A. <br /></td></tr>
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<tr class="separator:a54511e0d8c786b2e9f9254986fd0218c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a74f00a0b8ee43ec0d36f4e1376a0fad1"><td class="memItemLeft" align="right" valign="top"><a id="a74f00a0b8ee43ec0d36f4e1376a0fad1"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB09A_EIC_EXTINT9</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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||
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<tr class="separator:a74f00a0b8ee43ec0d36f4e1376a0fad1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4a491e25aded49ea7cf9a86d9778d69e"><td class="memItemLeft" align="right" valign="top"><a id="a4a491e25aded49ea7cf9a86d9778d69e"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB09A_EIC_EXTINT9</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a54511e0d8c786b2e9f9254986fd0218c">PIN_PB09A_EIC_EXTINT9</a> << 16) | MUX_PB09A_EIC_EXTINT9)</td></tr>
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<tr class="separator:a4a491e25aded49ea7cf9a86d9778d69e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a018dc0a9b70280bdd0049f9928a98b66"><td class="memItemLeft" align="right" valign="top"><a id="a018dc0a9b70280bdd0049f9928a98b66"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB09A_EIC_EXTINT9</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 9)</td></tr>
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||
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<tr class="separator:a018dc0a9b70280bdd0049f9928a98b66"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a10bc7a34f5797ee1e596b87ce0a5a673"><td class="memItemLeft" align="right" valign="top"><a id="a10bc7a34f5797ee1e596b87ce0a5a673"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a10bc7a34f5797ee1e596b87ce0a5a673">PIN_PB09A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
|
||
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<tr class="memdesc:a10bc7a34f5797ee1e596b87ce0a5a673"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PB09 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a10bc7a34f5797ee1e596b87ce0a5a673"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa027e3d920e60849d3bc0b8be0e2d584"><td class="memItemLeft" align="right" valign="top"><a id="aa027e3d920e60849d3bc0b8be0e2d584"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa027e3d920e60849d3bc0b8be0e2d584">PIN_PB25A_EIC_EXTINT9</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(57)</td></tr>
|
||
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<tr class="memdesc:aa027e3d920e60849d3bc0b8be0e2d584"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT9 on PB25 mux A. <br /></td></tr>
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<tr class="separator:aa027e3d920e60849d3bc0b8be0e2d584"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af661452e9e07942e47fb3322b2b778c1"><td class="memItemLeft" align="right" valign="top"><a id="af661452e9e07942e47fb3322b2b778c1"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB25A_EIC_EXTINT9</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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||
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<tr class="separator:af661452e9e07942e47fb3322b2b778c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3c9897a139ae87c2733cf105640ecdda"><td class="memItemLeft" align="right" valign="top"><a id="a3c9897a139ae87c2733cf105640ecdda"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB25A_EIC_EXTINT9</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aa027e3d920e60849d3bc0b8be0e2d584">PIN_PB25A_EIC_EXTINT9</a> << 16) | MUX_PB25A_EIC_EXTINT9)</td></tr>
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<tr class="separator:a3c9897a139ae87c2733cf105640ecdda"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a268ec1ff937cb6b2942030e940b250d8"><td class="memItemLeft" align="right" valign="top"><a id="a268ec1ff937cb6b2942030e940b250d8"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB25A_EIC_EXTINT9</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 25)</td></tr>
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<tr class="separator:a268ec1ff937cb6b2942030e940b250d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a559b557f5767773de2aef70fc2091e09"><td class="memItemLeft" align="right" valign="top"><a id="a559b557f5767773de2aef70fc2091e09"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a559b557f5767773de2aef70fc2091e09">PIN_PB25A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
|
||
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<tr class="memdesc:a559b557f5767773de2aef70fc2091e09"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PB25 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a559b557f5767773de2aef70fc2091e09"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9b1f615d6c036a90f8c3f2073726b4d8"><td class="memItemLeft" align="right" valign="top"><a id="a9b1f615d6c036a90f8c3f2073726b4d8"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a9b1f615d6c036a90f8c3f2073726b4d8">PIN_PC07A_EIC_EXTINT9</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(71)</td></tr>
|
||
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<tr class="memdesc:a9b1f615d6c036a90f8c3f2073726b4d8"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT9 on PC07 mux A. <br /></td></tr>
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<tr class="separator:a9b1f615d6c036a90f8c3f2073726b4d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abd10254be8b39bd4b00a667175ae5133"><td class="memItemLeft" align="right" valign="top"><a id="abd10254be8b39bd4b00a667175ae5133"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC07A_EIC_EXTINT9</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:abd10254be8b39bd4b00a667175ae5133"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af1f53acf7dfc2a49f1a1e806c73a6a93"><td class="memItemLeft" align="right" valign="top"><a id="af1f53acf7dfc2a49f1a1e806c73a6a93"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC07A_EIC_EXTINT9</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a9b1f615d6c036a90f8c3f2073726b4d8">PIN_PC07A_EIC_EXTINT9</a> << 16) | MUX_PC07A_EIC_EXTINT9)</td></tr>
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<tr class="memitem:a141ed1f0f6b2f3d25af0738b2e37ff2b"><td class="memItemLeft" align="right" valign="top"><a id="a141ed1f0f6b2f3d25af0738b2e37ff2b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC07A_EIC_EXTINT9</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 7)</td></tr>
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<tr class="separator:a141ed1f0f6b2f3d25af0738b2e37ff2b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae77819da8fb6731812fa964ca75638a1"><td class="memItemLeft" align="right" valign="top"><a id="ae77819da8fb6731812fa964ca75638a1"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae77819da8fb6731812fa964ca75638a1">PIN_PC07A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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<tr class="memdesc:ae77819da8fb6731812fa964ca75638a1"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PC07 External Interrupt Line. <br /></td></tr>
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<tr class="separator:ae77819da8fb6731812fa964ca75638a1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a34924d3f1c67b2324255389b25651bdb"><td class="memItemLeft" align="right" valign="top"><a id="a34924d3f1c67b2324255389b25651bdb"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a34924d3f1c67b2324255389b25651bdb">PIN_PC25A_EIC_EXTINT9</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(89)</td></tr>
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<tr class="memdesc:a34924d3f1c67b2324255389b25651bdb"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT9 on PC25 mux A. <br /></td></tr>
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<tr class="separator:a34924d3f1c67b2324255389b25651bdb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a49ede3aaa64af59a49af3a5f3509a4b7"><td class="memItemLeft" align="right" valign="top"><a id="a49ede3aaa64af59a49af3a5f3509a4b7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC25A_EIC_EXTINT9</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a49ede3aaa64af59a49af3a5f3509a4b7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0e3f62bc3aee5a84a49edb0b47cf5022"><td class="memItemLeft" align="right" valign="top"><a id="a0e3f62bc3aee5a84a49edb0b47cf5022"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC25A_EIC_EXTINT9</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a34924d3f1c67b2324255389b25651bdb">PIN_PC25A_EIC_EXTINT9</a> << 16) | MUX_PC25A_EIC_EXTINT9)</td></tr>
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<tr class="separator:a0e3f62bc3aee5a84a49edb0b47cf5022"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a90b8d745ef86715091367f8ac2e75b5f"><td class="memItemLeft" align="right" valign="top"><a id="a90b8d745ef86715091367f8ac2e75b5f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC25A_EIC_EXTINT9</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 25)</td></tr>
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<tr class="separator:a90b8d745ef86715091367f8ac2e75b5f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3a70e4355e455509a04587815d09b282"><td class="memItemLeft" align="right" valign="top"><a id="a3a70e4355e455509a04587815d09b282"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3a70e4355e455509a04587815d09b282">PIN_PC25A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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<tr class="memdesc:a3a70e4355e455509a04587815d09b282"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PC25 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a3a70e4355e455509a04587815d09b282"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8b2c811c3267616edc080b0bff76d475"><td class="memItemLeft" align="right" valign="top"><a id="a8b2c811c3267616edc080b0bff76d475"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8b2c811c3267616edc080b0bff76d475">PIN_PA10A_EIC_EXTINT10</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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<tr class="memdesc:a8b2c811c3267616edc080b0bff76d475"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT10 on PA10 mux A. <br /></td></tr>
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<tr class="separator:a8b2c811c3267616edc080b0bff76d475"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6b3e0ae410515ba4be948eb46dd27ee3"><td class="memItemLeft" align="right" valign="top"><a id="a6b3e0ae410515ba4be948eb46dd27ee3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA10A_EIC_EXTINT10</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a6b3e0ae410515ba4be948eb46dd27ee3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ace7672d5552b27a53f47b3d6a269f7c0"><td class="memItemLeft" align="right" valign="top"><a id="ace7672d5552b27a53f47b3d6a269f7c0"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA10A_EIC_EXTINT10</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a8b2c811c3267616edc080b0bff76d475">PIN_PA10A_EIC_EXTINT10</a> << 16) | MUX_PA10A_EIC_EXTINT10)</td></tr>
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<tr class="separator:ace7672d5552b27a53f47b3d6a269f7c0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5e6d005919f95bfe9332cc2ba000b68e"><td class="memItemLeft" align="right" valign="top"><a id="a5e6d005919f95bfe9332cc2ba000b68e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA10A_EIC_EXTINT10</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 10)</td></tr>
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<tr class="separator:a5e6d005919f95bfe9332cc2ba000b68e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac63edbcc5aa61044348f6c140f9b5d93"><td class="memItemLeft" align="right" valign="top"><a id="ac63edbcc5aa61044348f6c140f9b5d93"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac63edbcc5aa61044348f6c140f9b5d93">PIN_PA10A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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||
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<tr class="memdesc:ac63edbcc5aa61044348f6c140f9b5d93"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PA10 External Interrupt Line. <br /></td></tr>
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<tr class="separator:ac63edbcc5aa61044348f6c140f9b5d93"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0bbc187130701ad43c72a960b24e2a12"><td class="memItemLeft" align="right" valign="top"><a id="a0bbc187130701ad43c72a960b24e2a12"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0bbc187130701ad43c72a960b24e2a12">PIN_PB10A_EIC_EXTINT10</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(42)</td></tr>
|
||
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<tr class="memdesc:a0bbc187130701ad43c72a960b24e2a12"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT10 on PB10 mux A. <br /></td></tr>
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<tr class="separator:a0bbc187130701ad43c72a960b24e2a12"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0d02853fb394353482c38c70e6c53a09"><td class="memItemLeft" align="right" valign="top"><a id="a0d02853fb394353482c38c70e6c53a09"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB10A_EIC_EXTINT10</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a0d02853fb394353482c38c70e6c53a09"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab297d74c0a55eb3afc0b9ad26b971e32"><td class="memItemLeft" align="right" valign="top"><a id="ab297d74c0a55eb3afc0b9ad26b971e32"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB10A_EIC_EXTINT10</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a0bbc187130701ad43c72a960b24e2a12">PIN_PB10A_EIC_EXTINT10</a> << 16) | MUX_PB10A_EIC_EXTINT10)</td></tr>
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<tr class="separator:ab297d74c0a55eb3afc0b9ad26b971e32"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5625e5068616c618f0554eda3188f9ad"><td class="memItemLeft" align="right" valign="top"><a id="a5625e5068616c618f0554eda3188f9ad"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB10A_EIC_EXTINT10</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 10)</td></tr>
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<tr class="separator:a5625e5068616c618f0554eda3188f9ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a299b82012bb5d767607e5b17432f56fe"><td class="memItemLeft" align="right" valign="top"><a id="a299b82012bb5d767607e5b17432f56fe"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a299b82012bb5d767607e5b17432f56fe">PIN_PB10A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
|
||
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<tr class="memdesc:a299b82012bb5d767607e5b17432f56fe"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PB10 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a299b82012bb5d767607e5b17432f56fe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a69f1e93024e115b1c5c7dd0aabc34007"><td class="memItemLeft" align="right" valign="top"><a id="a69f1e93024e115b1c5c7dd0aabc34007"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a69f1e93024e115b1c5c7dd0aabc34007">PIN_PC10A_EIC_EXTINT10</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(74)</td></tr>
|
||
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<tr class="memdesc:a69f1e93024e115b1c5c7dd0aabc34007"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT10 on PC10 mux A. <br /></td></tr>
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<tr class="separator:a69f1e93024e115b1c5c7dd0aabc34007"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a19486cfc19127937ad809926096215b1"><td class="memItemLeft" align="right" valign="top"><a id="a19486cfc19127937ad809926096215b1"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC10A_EIC_EXTINT10</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a19486cfc19127937ad809926096215b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a710d82328d45c5c4e72bb3e232c53d01"><td class="memItemLeft" align="right" valign="top"><a id="a710d82328d45c5c4e72bb3e232c53d01"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC10A_EIC_EXTINT10</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a69f1e93024e115b1c5c7dd0aabc34007">PIN_PC10A_EIC_EXTINT10</a> << 16) | MUX_PC10A_EIC_EXTINT10)</td></tr>
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<tr class="separator:a710d82328d45c5c4e72bb3e232c53d01"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abc49f69da0ce5445e3ecc28a99c21c5b"><td class="memItemLeft" align="right" valign="top"><a id="abc49f69da0ce5445e3ecc28a99c21c5b"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC10A_EIC_EXTINT10</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 10)</td></tr>
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||
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<tr class="separator:abc49f69da0ce5445e3ecc28a99c21c5b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aba72c1c36fef61558ece1c1b55966203"><td class="memItemLeft" align="right" valign="top"><a id="aba72c1c36fef61558ece1c1b55966203"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aba72c1c36fef61558ece1c1b55966203">PIN_PC10A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
|
||
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<tr class="memdesc:aba72c1c36fef61558ece1c1b55966203"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PC10 External Interrupt Line. <br /></td></tr>
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||
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<tr class="separator:aba72c1c36fef61558ece1c1b55966203"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adbc1d8036ba72a5dc9aa4ed8e9c16bf4"><td class="memItemLeft" align="right" valign="top"><a id="adbc1d8036ba72a5dc9aa4ed8e9c16bf4"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#adbc1d8036ba72a5dc9aa4ed8e9c16bf4">PIN_PC26A_EIC_EXTINT10</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(90)</td></tr>
|
||
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<tr class="memdesc:adbc1d8036ba72a5dc9aa4ed8e9c16bf4"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT10 on PC26 mux A. <br /></td></tr>
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<tr class="separator:adbc1d8036ba72a5dc9aa4ed8e9c16bf4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6f2a6b65e15cfaa0307657f871602f17"><td class="memItemLeft" align="right" valign="top"><a id="a6f2a6b65e15cfaa0307657f871602f17"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC26A_EIC_EXTINT10</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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||
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<tr class="separator:a6f2a6b65e15cfaa0307657f871602f17"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a14ce6266d93d978ad4e9fbc3f77c1581"><td class="memItemLeft" align="right" valign="top"><a id="a14ce6266d93d978ad4e9fbc3f77c1581"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC26A_EIC_EXTINT10</b>   ((<a class="el" href="pio_2same54p20a_8h.html#adbc1d8036ba72a5dc9aa4ed8e9c16bf4">PIN_PC26A_EIC_EXTINT10</a> << 16) | MUX_PC26A_EIC_EXTINT10)</td></tr>
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<tr class="separator:a14ce6266d93d978ad4e9fbc3f77c1581"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a368a6ebe641b99d291764bb3a4126ddd"><td class="memItemLeft" align="right" valign="top"><a id="a368a6ebe641b99d291764bb3a4126ddd"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC26A_EIC_EXTINT10</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 26)</td></tr>
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||
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<tr class="separator:a368a6ebe641b99d291764bb3a4126ddd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a850b82f73b12eb38b0996dd0f3f50cb5"><td class="memItemLeft" align="right" valign="top"><a id="a850b82f73b12eb38b0996dd0f3f50cb5"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a850b82f73b12eb38b0996dd0f3f50cb5">PIN_PC26A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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||
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<tr class="memdesc:a850b82f73b12eb38b0996dd0f3f50cb5"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PC26 External Interrupt Line. <br /></td></tr>
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<tr class="memitem:a3657e3eaf7afcbeb5f745b100e1b7553"><td class="memItemLeft" align="right" valign="top"><a id="a3657e3eaf7afcbeb5f745b100e1b7553"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3657e3eaf7afcbeb5f745b100e1b7553">PIN_PA11A_EIC_EXTINT11</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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<tr class="memdesc:a3657e3eaf7afcbeb5f745b100e1b7553"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT11 on PA11 mux A. <br /></td></tr>
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<tr class="memitem:a45eed35dc289e5cc04aa6a6615253a74"><td class="memItemLeft" align="right" valign="top"><a id="a45eed35dc289e5cc04aa6a6615253a74"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA11A_EIC_EXTINT11</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a45eed35dc289e5cc04aa6a6615253a74"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2ce7db1cd13991b83601a2fa6a0cdd77"><td class="memItemLeft" align="right" valign="top"><a id="a2ce7db1cd13991b83601a2fa6a0cdd77"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA11A_EIC_EXTINT11</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a3657e3eaf7afcbeb5f745b100e1b7553">PIN_PA11A_EIC_EXTINT11</a> << 16) | MUX_PA11A_EIC_EXTINT11)</td></tr>
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<tr class="separator:a2ce7db1cd13991b83601a2fa6a0cdd77"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a148bad391719e0548f4d1ea7de1661df"><td class="memItemLeft" align="right" valign="top"><a id="a148bad391719e0548f4d1ea7de1661df"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA11A_EIC_EXTINT11</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 11)</td></tr>
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<tr class="separator:a148bad391719e0548f4d1ea7de1661df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a07f5583af3fda141d507c62491604576"><td class="memItemLeft" align="right" valign="top"><a id="a07f5583af3fda141d507c62491604576"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a07f5583af3fda141d507c62491604576">PIN_PA11A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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<tr class="memdesc:a07f5583af3fda141d507c62491604576"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PA11 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a07f5583af3fda141d507c62491604576"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a82d3925fbe91ae83d5696cecee79bd0f"><td class="memItemLeft" align="right" valign="top"><a id="a82d3925fbe91ae83d5696cecee79bd0f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a82d3925fbe91ae83d5696cecee79bd0f">PIN_PA27A_EIC_EXTINT11</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(27)</td></tr>
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<tr class="memdesc:a82d3925fbe91ae83d5696cecee79bd0f"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT11 on PA27 mux A. <br /></td></tr>
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<tr class="separator:a82d3925fbe91ae83d5696cecee79bd0f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4bd9465b4a951e8c9ca97a9d67fec93c"><td class="memItemLeft" align="right" valign="top"><a id="a4bd9465b4a951e8c9ca97a9d67fec93c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA27A_EIC_EXTINT11</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a4bd9465b4a951e8c9ca97a9d67fec93c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a90ad4f174230a0d7ea9e502089e3b1a1"><td class="memItemLeft" align="right" valign="top"><a id="a90ad4f174230a0d7ea9e502089e3b1a1"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA27A_EIC_EXTINT11</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a82d3925fbe91ae83d5696cecee79bd0f">PIN_PA27A_EIC_EXTINT11</a> << 16) | MUX_PA27A_EIC_EXTINT11)</td></tr>
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<tr class="separator:a90ad4f174230a0d7ea9e502089e3b1a1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afba601764aa8b77ca6fb16f7b1b30b75"><td class="memItemLeft" align="right" valign="top"><a id="afba601764aa8b77ca6fb16f7b1b30b75"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA27A_EIC_EXTINT11</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 27)</td></tr>
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<tr class="separator:afba601764aa8b77ca6fb16f7b1b30b75"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a629eb4033ad4c842b29a72a2be4f61d9"><td class="memItemLeft" align="right" valign="top"><a id="a629eb4033ad4c842b29a72a2be4f61d9"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a629eb4033ad4c842b29a72a2be4f61d9">PIN_PA27A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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<tr class="memdesc:a629eb4033ad4c842b29a72a2be4f61d9"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PA27 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a629eb4033ad4c842b29a72a2be4f61d9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac2c2a072fc6ccf668486f50d41045b78"><td class="memItemLeft" align="right" valign="top"><a id="ac2c2a072fc6ccf668486f50d41045b78"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac2c2a072fc6ccf668486f50d41045b78">PIN_PB11A_EIC_EXTINT11</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(43)</td></tr>
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<tr class="memdesc:ac2c2a072fc6ccf668486f50d41045b78"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT11 on PB11 mux A. <br /></td></tr>
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<tr class="separator:ac2c2a072fc6ccf668486f50d41045b78"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4835efb8f3f8bc9ffa5e5e0def57b3dc"><td class="memItemLeft" align="right" valign="top"><a id="a4835efb8f3f8bc9ffa5e5e0def57b3dc"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB11A_EIC_EXTINT11</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a4835efb8f3f8bc9ffa5e5e0def57b3dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8f5178653d8d64abdf42d531ddde7505"><td class="memItemLeft" align="right" valign="top"><a id="a8f5178653d8d64abdf42d531ddde7505"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB11A_EIC_EXTINT11</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ac2c2a072fc6ccf668486f50d41045b78">PIN_PB11A_EIC_EXTINT11</a> << 16) | MUX_PB11A_EIC_EXTINT11)</td></tr>
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<tr class="separator:a8f5178653d8d64abdf42d531ddde7505"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae0e931313dad35be320355dd61b7398d"><td class="memItemLeft" align="right" valign="top"><a id="ae0e931313dad35be320355dd61b7398d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB11A_EIC_EXTINT11</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 11)</td></tr>
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<tr class="separator:ae0e931313dad35be320355dd61b7398d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa8771096fea5a2bbf5781b1365b40b9a"><td class="memItemLeft" align="right" valign="top"><a id="aa8771096fea5a2bbf5781b1365b40b9a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa8771096fea5a2bbf5781b1365b40b9a">PIN_PB11A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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<tr class="memdesc:aa8771096fea5a2bbf5781b1365b40b9a"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PB11 External Interrupt Line. <br /></td></tr>
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<tr class="separator:aa8771096fea5a2bbf5781b1365b40b9a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9eeb1998bf1a323d3c93c33c05c3e366"><td class="memItemLeft" align="right" valign="top"><a id="a9eeb1998bf1a323d3c93c33c05c3e366"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a9eeb1998bf1a323d3c93c33c05c3e366">PIN_PC11A_EIC_EXTINT11</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(75)</td></tr>
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<tr class="memdesc:a9eeb1998bf1a323d3c93c33c05c3e366"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT11 on PC11 mux A. <br /></td></tr>
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<tr class="separator:a9eeb1998bf1a323d3c93c33c05c3e366"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa848b6b4733245d66a8f3db23ea14232"><td class="memItemLeft" align="right" valign="top"><a id="aa848b6b4733245d66a8f3db23ea14232"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC11A_EIC_EXTINT11</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:aa848b6b4733245d66a8f3db23ea14232"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a012e63acdb5efd7af61bf81993a0881f"><td class="memItemLeft" align="right" valign="top"><a id="a012e63acdb5efd7af61bf81993a0881f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC11A_EIC_EXTINT11</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a9eeb1998bf1a323d3c93c33c05c3e366">PIN_PC11A_EIC_EXTINT11</a> << 16) | MUX_PC11A_EIC_EXTINT11)</td></tr>
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<tr class="separator:a012e63acdb5efd7af61bf81993a0881f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a168fe19417ef3ded9e3ebe06459b5302"><td class="memItemLeft" align="right" valign="top"><a id="a168fe19417ef3ded9e3ebe06459b5302"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC11A_EIC_EXTINT11</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 11)</td></tr>
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<tr class="separator:a168fe19417ef3ded9e3ebe06459b5302"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a61460200c4f743e3d81b0092498dd7d4"><td class="memItemLeft" align="right" valign="top"><a id="a61460200c4f743e3d81b0092498dd7d4"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a61460200c4f743e3d81b0092498dd7d4">PIN_PC11A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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<tr class="memdesc:a61460200c4f743e3d81b0092498dd7d4"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PC11 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a61460200c4f743e3d81b0092498dd7d4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a30ded42b8250b74e112c5362b83e32ac"><td class="memItemLeft" align="right" valign="top"><a id="a30ded42b8250b74e112c5362b83e32ac"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a30ded42b8250b74e112c5362b83e32ac">PIN_PC27A_EIC_EXTINT11</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(91)</td></tr>
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<tr class="memdesc:a30ded42b8250b74e112c5362b83e32ac"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT11 on PC27 mux A. <br /></td></tr>
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<tr class="separator:a30ded42b8250b74e112c5362b83e32ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2d6fdf9afe3572b0c9d67b192f17708a"><td class="memItemLeft" align="right" valign="top"><a id="a2d6fdf9afe3572b0c9d67b192f17708a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC27A_EIC_EXTINT11</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a2d6fdf9afe3572b0c9d67b192f17708a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a19da8ae63da3495932ed315ab8e9de77"><td class="memItemLeft" align="right" valign="top"><a id="a19da8ae63da3495932ed315ab8e9de77"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC27A_EIC_EXTINT11</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a30ded42b8250b74e112c5362b83e32ac">PIN_PC27A_EIC_EXTINT11</a> << 16) | MUX_PC27A_EIC_EXTINT11)</td></tr>
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<tr class="separator:a19da8ae63da3495932ed315ab8e9de77"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a32865cc34bff6308e9304682aab95f39"><td class="memItemLeft" align="right" valign="top"><a id="a32865cc34bff6308e9304682aab95f39"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC27A_EIC_EXTINT11</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 27)</td></tr>
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<tr class="separator:a32865cc34bff6308e9304682aab95f39"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a53caacf24a9b4c7d592c1c68a521fa9d"><td class="memItemLeft" align="right" valign="top"><a id="a53caacf24a9b4c7d592c1c68a521fa9d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a53caacf24a9b4c7d592c1c68a521fa9d">PIN_PC27A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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<tr class="memdesc:a53caacf24a9b4c7d592c1c68a521fa9d"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PC27 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a53caacf24a9b4c7d592c1c68a521fa9d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a419f1aea38758fba2ad9508d1e8915ab"><td class="memItemLeft" align="right" valign="top"><a id="a419f1aea38758fba2ad9508d1e8915ab"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a419f1aea38758fba2ad9508d1e8915ab">PIN_PA12A_EIC_EXTINT12</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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<tr class="memdesc:a419f1aea38758fba2ad9508d1e8915ab"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT12 on PA12 mux A. <br /></td></tr>
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<tr class="separator:a419f1aea38758fba2ad9508d1e8915ab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a26a578a855d3555eb362aad0a777d251"><td class="memItemLeft" align="right" valign="top"><a id="a26a578a855d3555eb362aad0a777d251"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA12A_EIC_EXTINT12</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="memitem:a57b6e0d2290ea3bbe0822451b86decb2"><td class="memItemLeft" align="right" valign="top"><a id="a57b6e0d2290ea3bbe0822451b86decb2"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA12A_EIC_EXTINT12</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a419f1aea38758fba2ad9508d1e8915ab">PIN_PA12A_EIC_EXTINT12</a> << 16) | MUX_PA12A_EIC_EXTINT12)</td></tr>
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<tr class="memitem:ae1fdf6b8f5132f15937474baf864518a"><td class="memItemLeft" align="right" valign="top"><a id="ae1fdf6b8f5132f15937474baf864518a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA12A_EIC_EXTINT12</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 12)</td></tr>
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<tr class="separator:ae1fdf6b8f5132f15937474baf864518a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a945f93983309a0fc25eae757bc4a5dcb"><td class="memItemLeft" align="right" valign="top"><a id="a945f93983309a0fc25eae757bc4a5dcb"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a945f93983309a0fc25eae757bc4a5dcb">PIN_PA12A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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<tr class="memdesc:a945f93983309a0fc25eae757bc4a5dcb"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PA12 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a945f93983309a0fc25eae757bc4a5dcb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a622fd72ad9576c628a9c01207688df4d"><td class="memItemLeft" align="right" valign="top"><a id="a622fd72ad9576c628a9c01207688df4d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a622fd72ad9576c628a9c01207688df4d">PIN_PB12A_EIC_EXTINT12</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(44)</td></tr>
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<tr class="memdesc:a622fd72ad9576c628a9c01207688df4d"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT12 on PB12 mux A. <br /></td></tr>
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<tr class="memitem:afda1ae74a5ed4fa76b69df73385a9fb6"><td class="memItemLeft" align="right" valign="top"><a id="afda1ae74a5ed4fa76b69df73385a9fb6"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB12A_EIC_EXTINT12</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:afda1ae74a5ed4fa76b69df73385a9fb6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad602d36824778980df6c626e0746c1d5"><td class="memItemLeft" align="right" valign="top"><a id="ad602d36824778980df6c626e0746c1d5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB12A_EIC_EXTINT12</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a622fd72ad9576c628a9c01207688df4d">PIN_PB12A_EIC_EXTINT12</a> << 16) | MUX_PB12A_EIC_EXTINT12)</td></tr>
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<tr class="memitem:aae9688b311e7cc32d8dd94522c9b6d63"><td class="memItemLeft" align="right" valign="top"><a id="aae9688b311e7cc32d8dd94522c9b6d63"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB12A_EIC_EXTINT12</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 12)</td></tr>
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<tr class="separator:aae9688b311e7cc32d8dd94522c9b6d63"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a20213283160ed1e94398c3caf0f47f80"><td class="memItemLeft" align="right" valign="top"><a id="a20213283160ed1e94398c3caf0f47f80"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a20213283160ed1e94398c3caf0f47f80">PIN_PB12A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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<tr class="memdesc:a20213283160ed1e94398c3caf0f47f80"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PB12 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a20213283160ed1e94398c3caf0f47f80"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af07f4f0f8321b7cda8f9b0fd675f0af3"><td class="memItemLeft" align="right" valign="top"><a id="af07f4f0f8321b7cda8f9b0fd675f0af3"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af07f4f0f8321b7cda8f9b0fd675f0af3">PIN_PC12A_EIC_EXTINT12</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(76)</td></tr>
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<tr class="memdesc:af07f4f0f8321b7cda8f9b0fd675f0af3"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT12 on PC12 mux A. <br /></td></tr>
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<tr class="separator:af07f4f0f8321b7cda8f9b0fd675f0af3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a214c5c7ee7eea73e222a2c1cbfd5ffa3"><td class="memItemLeft" align="right" valign="top"><a id="a214c5c7ee7eea73e222a2c1cbfd5ffa3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC12A_EIC_EXTINT12</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a214c5c7ee7eea73e222a2c1cbfd5ffa3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a801bc37d3ea97ab7dbcead56036da395"><td class="memItemLeft" align="right" valign="top"><a id="a801bc37d3ea97ab7dbcead56036da395"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC12A_EIC_EXTINT12</b>   ((<a class="el" href="pio_2same54p20a_8h.html#af07f4f0f8321b7cda8f9b0fd675f0af3">PIN_PC12A_EIC_EXTINT12</a> << 16) | MUX_PC12A_EIC_EXTINT12)</td></tr>
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<tr class="separator:a801bc37d3ea97ab7dbcead56036da395"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae396474af1ac55ae878753827eb8d5ce"><td class="memItemLeft" align="right" valign="top"><a id="ae396474af1ac55ae878753827eb8d5ce"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC12A_EIC_EXTINT12</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 12)</td></tr>
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<tr class="separator:ae396474af1ac55ae878753827eb8d5ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a904bd02861f200a708506d64bc8b1054"><td class="memItemLeft" align="right" valign="top"><a id="a904bd02861f200a708506d64bc8b1054"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a904bd02861f200a708506d64bc8b1054">PIN_PC12A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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||
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<tr class="memdesc:a904bd02861f200a708506d64bc8b1054"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PC12 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a904bd02861f200a708506d64bc8b1054"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a20effc1231f3a2798443f6bc6b670bec"><td class="memItemLeft" align="right" valign="top"><a id="a20effc1231f3a2798443f6bc6b670bec"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a20effc1231f3a2798443f6bc6b670bec">PIN_PC28A_EIC_EXTINT12</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(92)</td></tr>
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<tr class="memdesc:a20effc1231f3a2798443f6bc6b670bec"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT12 on PC28 mux A. <br /></td></tr>
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<tr class="separator:a20effc1231f3a2798443f6bc6b670bec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad90116a756741fc88d25ffed0cb736bc"><td class="memItemLeft" align="right" valign="top"><a id="ad90116a756741fc88d25ffed0cb736bc"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC28A_EIC_EXTINT12</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:ad90116a756741fc88d25ffed0cb736bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3606cd30d01be973bf74a378ff3dcaa8"><td class="memItemLeft" align="right" valign="top"><a id="a3606cd30d01be973bf74a378ff3dcaa8"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC28A_EIC_EXTINT12</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a20effc1231f3a2798443f6bc6b670bec">PIN_PC28A_EIC_EXTINT12</a> << 16) | MUX_PC28A_EIC_EXTINT12)</td></tr>
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<tr class="separator:a3606cd30d01be973bf74a378ff3dcaa8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acac7eabc0fb2bcd13045b6d84045f285"><td class="memItemLeft" align="right" valign="top"><a id="acac7eabc0fb2bcd13045b6d84045f285"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC28A_EIC_EXTINT12</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 28)</td></tr>
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<tr class="separator:acac7eabc0fb2bcd13045b6d84045f285"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae12a87002c813f473f3601d6f4a26180"><td class="memItemLeft" align="right" valign="top"><a id="ae12a87002c813f473f3601d6f4a26180"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae12a87002c813f473f3601d6f4a26180">PIN_PC28A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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||
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<tr class="memdesc:ae12a87002c813f473f3601d6f4a26180"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PC28 External Interrupt Line. <br /></td></tr>
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<tr class="separator:ae12a87002c813f473f3601d6f4a26180"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9a43983f5cd1bfedf36b9c6dfcc4e80c"><td class="memItemLeft" align="right" valign="top"><a id="a9a43983f5cd1bfedf36b9c6dfcc4e80c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a9a43983f5cd1bfedf36b9c6dfcc4e80c">PIN_PA13A_EIC_EXTINT13</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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||
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<tr class="memdesc:a9a43983f5cd1bfedf36b9c6dfcc4e80c"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT13 on PA13 mux A. <br /></td></tr>
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<tr class="separator:a9a43983f5cd1bfedf36b9c6dfcc4e80c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad27b6aa8def318c1c27ca2db71d81c03"><td class="memItemLeft" align="right" valign="top"><a id="ad27b6aa8def318c1c27ca2db71d81c03"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA13A_EIC_EXTINT13</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:ad27b6aa8def318c1c27ca2db71d81c03"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a90af31d47f5bcb0ac46b4361c68068b9"><td class="memItemLeft" align="right" valign="top"><a id="a90af31d47f5bcb0ac46b4361c68068b9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA13A_EIC_EXTINT13</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a9a43983f5cd1bfedf36b9c6dfcc4e80c">PIN_PA13A_EIC_EXTINT13</a> << 16) | MUX_PA13A_EIC_EXTINT13)</td></tr>
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<tr class="separator:a90af31d47f5bcb0ac46b4361c68068b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac4670a53bab519d3932047ea5acd8f61"><td class="memItemLeft" align="right" valign="top"><a id="ac4670a53bab519d3932047ea5acd8f61"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA13A_EIC_EXTINT13</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 13)</td></tr>
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<tr class="separator:ac4670a53bab519d3932047ea5acd8f61"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7b27ffa7e40d98061e8f87e6d2938543"><td class="memItemLeft" align="right" valign="top"><a id="a7b27ffa7e40d98061e8f87e6d2938543"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7b27ffa7e40d98061e8f87e6d2938543">PIN_PA13A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
|
||
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<tr class="memdesc:a7b27ffa7e40d98061e8f87e6d2938543"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PA13 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a7b27ffa7e40d98061e8f87e6d2938543"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a30ef1606e3c2432323e5296bbf806969"><td class="memItemLeft" align="right" valign="top"><a id="a30ef1606e3c2432323e5296bbf806969"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a30ef1606e3c2432323e5296bbf806969">PIN_PB13A_EIC_EXTINT13</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(45)</td></tr>
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||
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<tr class="memdesc:a30ef1606e3c2432323e5296bbf806969"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT13 on PB13 mux A. <br /></td></tr>
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<tr class="separator:a30ef1606e3c2432323e5296bbf806969"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8c4f393f8a2e30a3a7c1557daf00a553"><td class="memItemLeft" align="right" valign="top"><a id="a8c4f393f8a2e30a3a7c1557daf00a553"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB13A_EIC_EXTINT13</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a8c4f393f8a2e30a3a7c1557daf00a553"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abab1affc7258db4864783bd0680e64e5"><td class="memItemLeft" align="right" valign="top"><a id="abab1affc7258db4864783bd0680e64e5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB13A_EIC_EXTINT13</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a30ef1606e3c2432323e5296bbf806969">PIN_PB13A_EIC_EXTINT13</a> << 16) | MUX_PB13A_EIC_EXTINT13)</td></tr>
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<tr class="separator:abab1affc7258db4864783bd0680e64e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7ece78b1bb8b7dfe96bf75fdd616110a"><td class="memItemLeft" align="right" valign="top"><a id="a7ece78b1bb8b7dfe96bf75fdd616110a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB13A_EIC_EXTINT13</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 13)</td></tr>
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||
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<tr class="separator:a7ece78b1bb8b7dfe96bf75fdd616110a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abc2373bc00dc6426c18883d73cd921e4"><td class="memItemLeft" align="right" valign="top"><a id="abc2373bc00dc6426c18883d73cd921e4"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#abc2373bc00dc6426c18883d73cd921e4">PIN_PB13A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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<tr class="memdesc:abc2373bc00dc6426c18883d73cd921e4"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PB13 External Interrupt Line. <br /></td></tr>
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<tr class="separator:abc2373bc00dc6426c18883d73cd921e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4c7e68b1de314167020c22878192a4ee"><td class="memItemLeft" align="right" valign="top"><a id="a4c7e68b1de314167020c22878192a4ee"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4c7e68b1de314167020c22878192a4ee">PIN_PC13A_EIC_EXTINT13</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(77)</td></tr>
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<tr class="memdesc:a4c7e68b1de314167020c22878192a4ee"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT13 on PC13 mux A. <br /></td></tr>
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<tr class="separator:a4c7e68b1de314167020c22878192a4ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3531d94e59aacba4403390a9b2072b3a"><td class="memItemLeft" align="right" valign="top"><a id="a3531d94e59aacba4403390a9b2072b3a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC13A_EIC_EXTINT13</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a3531d94e59aacba4403390a9b2072b3a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac8c86bcd20aec186e8c8f6bef6ec0d9f"><td class="memItemLeft" align="right" valign="top"><a id="ac8c86bcd20aec186e8c8f6bef6ec0d9f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC13A_EIC_EXTINT13</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a4c7e68b1de314167020c22878192a4ee">PIN_PC13A_EIC_EXTINT13</a> << 16) | MUX_PC13A_EIC_EXTINT13)</td></tr>
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<tr class="separator:ac8c86bcd20aec186e8c8f6bef6ec0d9f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7154c705482a99952cb8965802c66e76"><td class="memItemLeft" align="right" valign="top"><a id="a7154c705482a99952cb8965802c66e76"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC13A_EIC_EXTINT13</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 13)</td></tr>
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<tr class="separator:a7154c705482a99952cb8965802c66e76"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af133e675c28b62bc17622079cc5ad73c"><td class="memItemLeft" align="right" valign="top"><a id="af133e675c28b62bc17622079cc5ad73c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af133e675c28b62bc17622079cc5ad73c">PIN_PC13A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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<tr class="memdesc:af133e675c28b62bc17622079cc5ad73c"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PC13 External Interrupt Line. <br /></td></tr>
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<tr class="separator:af133e675c28b62bc17622079cc5ad73c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab929da45737573301da1d2fdaf47258f"><td class="memItemLeft" align="right" valign="top"><a id="ab929da45737573301da1d2fdaf47258f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab929da45737573301da1d2fdaf47258f">PIN_PA30A_EIC_EXTINT14</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(30)</td></tr>
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<tr class="memdesc:ab929da45737573301da1d2fdaf47258f"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT14 on PA30 mux A. <br /></td></tr>
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<tr class="separator:ab929da45737573301da1d2fdaf47258f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5226c3af01b72e857bdf6d33b6016c1a"><td class="memItemLeft" align="right" valign="top"><a id="a5226c3af01b72e857bdf6d33b6016c1a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA30A_EIC_EXTINT14</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a5226c3af01b72e857bdf6d33b6016c1a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3ca66000e2c68f079ed87c21ad10bd3e"><td class="memItemLeft" align="right" valign="top"><a id="a3ca66000e2c68f079ed87c21ad10bd3e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA30A_EIC_EXTINT14</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ab929da45737573301da1d2fdaf47258f">PIN_PA30A_EIC_EXTINT14</a> << 16) | MUX_PA30A_EIC_EXTINT14)</td></tr>
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<tr class="separator:a3ca66000e2c68f079ed87c21ad10bd3e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9476ee40eb7ee42bb50c5079fdcfe275"><td class="memItemLeft" align="right" valign="top"><a id="a9476ee40eb7ee42bb50c5079fdcfe275"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA30A_EIC_EXTINT14</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 30)</td></tr>
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<tr class="separator:a9476ee40eb7ee42bb50c5079fdcfe275"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a47e6e6a6f95588257a6dfdb1f9ed4e57"><td class="memItemLeft" align="right" valign="top"><a id="a47e6e6a6f95588257a6dfdb1f9ed4e57"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a47e6e6a6f95588257a6dfdb1f9ed4e57">PIN_PA30A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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||
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<tr class="memdesc:a47e6e6a6f95588257a6dfdb1f9ed4e57"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PA30 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a47e6e6a6f95588257a6dfdb1f9ed4e57"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a97b02a75f517744286a792170b1b7007"><td class="memItemLeft" align="right" valign="top"><a id="a97b02a75f517744286a792170b1b7007"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a97b02a75f517744286a792170b1b7007">PIN_PB14A_EIC_EXTINT14</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(46)</td></tr>
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||
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<tr class="memdesc:a97b02a75f517744286a792170b1b7007"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT14 on PB14 mux A. <br /></td></tr>
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<tr class="separator:a97b02a75f517744286a792170b1b7007"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad29925a7b34bd6bcf03b3cace21ea476"><td class="memItemLeft" align="right" valign="top"><a id="ad29925a7b34bd6bcf03b3cace21ea476"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB14A_EIC_EXTINT14</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:ad29925a7b34bd6bcf03b3cace21ea476"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac3753b411b7b24386dfc7b997a6c743f"><td class="memItemLeft" align="right" valign="top"><a id="ac3753b411b7b24386dfc7b997a6c743f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB14A_EIC_EXTINT14</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a97b02a75f517744286a792170b1b7007">PIN_PB14A_EIC_EXTINT14</a> << 16) | MUX_PB14A_EIC_EXTINT14)</td></tr>
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<tr class="separator:ac3753b411b7b24386dfc7b997a6c743f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a52425edcacc0184d96e13195c10abd7c"><td class="memItemLeft" align="right" valign="top"><a id="a52425edcacc0184d96e13195c10abd7c"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB14A_EIC_EXTINT14</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 14)</td></tr>
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<tr class="separator:a52425edcacc0184d96e13195c10abd7c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1da4ac8484e7935c6b8bdac5293cb17e"><td class="memItemLeft" align="right" valign="top"><a id="a1da4ac8484e7935c6b8bdac5293cb17e"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1da4ac8484e7935c6b8bdac5293cb17e">PIN_PB14A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
|
||
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<tr class="memdesc:a1da4ac8484e7935c6b8bdac5293cb17e"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PB14 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a1da4ac8484e7935c6b8bdac5293cb17e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a01cb0425b89b425f6281cf047d07d5c5"><td class="memItemLeft" align="right" valign="top"><a id="a01cb0425b89b425f6281cf047d07d5c5"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a01cb0425b89b425f6281cf047d07d5c5">PIN_PB30A_EIC_EXTINT14</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(62)</td></tr>
|
||
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<tr class="memdesc:a01cb0425b89b425f6281cf047d07d5c5"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT14 on PB30 mux A. <br /></td></tr>
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<tr class="separator:a01cb0425b89b425f6281cf047d07d5c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7d476f529fde9466271e923eb32b8b39"><td class="memItemLeft" align="right" valign="top"><a id="a7d476f529fde9466271e923eb32b8b39"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB30A_EIC_EXTINT14</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a7d476f529fde9466271e923eb32b8b39"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0ce03bbdfcebf997e27c103a4e32139b"><td class="memItemLeft" align="right" valign="top"><a id="a0ce03bbdfcebf997e27c103a4e32139b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB30A_EIC_EXTINT14</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a01cb0425b89b425f6281cf047d07d5c5">PIN_PB30A_EIC_EXTINT14</a> << 16) | MUX_PB30A_EIC_EXTINT14)</td></tr>
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<tr class="separator:a0ce03bbdfcebf997e27c103a4e32139b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acb96e58d3dec6fe861d4ab213213149f"><td class="memItemLeft" align="right" valign="top"><a id="acb96e58d3dec6fe861d4ab213213149f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB30A_EIC_EXTINT14</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 30)</td></tr>
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<tr class="separator:acb96e58d3dec6fe861d4ab213213149f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a92135bc9b73d6bf0b069ad66f4567d3d"><td class="memItemLeft" align="right" valign="top"><a id="a92135bc9b73d6bf0b069ad66f4567d3d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a92135bc9b73d6bf0b069ad66f4567d3d">PIN_PB30A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
|
||
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<tr class="memdesc:a92135bc9b73d6bf0b069ad66f4567d3d"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PB30 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a92135bc9b73d6bf0b069ad66f4567d3d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad508de42194b497772ad8bb605b9325a"><td class="memItemLeft" align="right" valign="top"><a id="ad508de42194b497772ad8bb605b9325a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad508de42194b497772ad8bb605b9325a">PIN_PC14A_EIC_EXTINT14</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(78)</td></tr>
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||
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<tr class="memdesc:ad508de42194b497772ad8bb605b9325a"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT14 on PC14 mux A. <br /></td></tr>
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<tr class="separator:ad508de42194b497772ad8bb605b9325a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a819b4c732a8053ddcac715b5e929a210"><td class="memItemLeft" align="right" valign="top"><a id="a819b4c732a8053ddcac715b5e929a210"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC14A_EIC_EXTINT14</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a819b4c732a8053ddcac715b5e929a210"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae651cbf42593232881932836750bbf43"><td class="memItemLeft" align="right" valign="top"><a id="ae651cbf42593232881932836750bbf43"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC14A_EIC_EXTINT14</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ad508de42194b497772ad8bb605b9325a">PIN_PC14A_EIC_EXTINT14</a> << 16) | MUX_PC14A_EIC_EXTINT14)</td></tr>
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<tr class="separator:ae651cbf42593232881932836750bbf43"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2dc589ebb89aab2669479404d610d910"><td class="memItemLeft" align="right" valign="top"><a id="a2dc589ebb89aab2669479404d610d910"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC14A_EIC_EXTINT14</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 14)</td></tr>
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||
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<tr class="separator:a2dc589ebb89aab2669479404d610d910"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3a4cb92927b0055d3d527ca6ebc74caf"><td class="memItemLeft" align="right" valign="top"><a id="a3a4cb92927b0055d3d527ca6ebc74caf"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3a4cb92927b0055d3d527ca6ebc74caf">PIN_PC14A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
|
||
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<tr class="memdesc:a3a4cb92927b0055d3d527ca6ebc74caf"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PC14 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a3a4cb92927b0055d3d527ca6ebc74caf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa46158d922bcbc88aa8a9f8a5adac460"><td class="memItemLeft" align="right" valign="top"><a id="aa46158d922bcbc88aa8a9f8a5adac460"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa46158d922bcbc88aa8a9f8a5adac460">PIN_PA14A_EIC_EXTINT14</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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||
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<tr class="memdesc:aa46158d922bcbc88aa8a9f8a5adac460"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT14 on PA14 mux A. <br /></td></tr>
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<tr class="separator:aa46158d922bcbc88aa8a9f8a5adac460"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afeb03044b3ae72cc083bf75edd71caf2"><td class="memItemLeft" align="right" valign="top"><a id="afeb03044b3ae72cc083bf75edd71caf2"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA14A_EIC_EXTINT14</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="memitem:acd04dc85dd82af514fd78127a6d13449"><td class="memItemLeft" align="right" valign="top"><a id="acd04dc85dd82af514fd78127a6d13449"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA14A_EIC_EXTINT14</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aa46158d922bcbc88aa8a9f8a5adac460">PIN_PA14A_EIC_EXTINT14</a> << 16) | MUX_PA14A_EIC_EXTINT14)</td></tr>
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<tr class="memitem:a180fbf3388d91a02092b87609583ffa5"><td class="memItemLeft" align="right" valign="top"><a id="a180fbf3388d91a02092b87609583ffa5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA14A_EIC_EXTINT14</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 14)</td></tr>
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<tr class="separator:a180fbf3388d91a02092b87609583ffa5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1bbcdf32200b0955ec73f1282beb45cd"><td class="memItemLeft" align="right" valign="top"><a id="a1bbcdf32200b0955ec73f1282beb45cd"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1bbcdf32200b0955ec73f1282beb45cd">PIN_PA14A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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<tr class="memdesc:a1bbcdf32200b0955ec73f1282beb45cd"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PA14 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a1bbcdf32200b0955ec73f1282beb45cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6cf6ad0634cbb035d1c78c40cfc0ed7e"><td class="memItemLeft" align="right" valign="top"><a id="a6cf6ad0634cbb035d1c78c40cfc0ed7e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6cf6ad0634cbb035d1c78c40cfc0ed7e">PIN_PA15A_EIC_EXTINT15</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(15)</td></tr>
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<tr class="memdesc:a6cf6ad0634cbb035d1c78c40cfc0ed7e"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT15 on PA15 mux A. <br /></td></tr>
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<tr class="separator:a6cf6ad0634cbb035d1c78c40cfc0ed7e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4454df2977df5f5052c8cfa9aa7bb949"><td class="memItemLeft" align="right" valign="top"><a id="a4454df2977df5f5052c8cfa9aa7bb949"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA15A_EIC_EXTINT15</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a4454df2977df5f5052c8cfa9aa7bb949"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa82833fe8b0e407c256328205ffa03a7"><td class="memItemLeft" align="right" valign="top"><a id="aa82833fe8b0e407c256328205ffa03a7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA15A_EIC_EXTINT15</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a6cf6ad0634cbb035d1c78c40cfc0ed7e">PIN_PA15A_EIC_EXTINT15</a> << 16) | MUX_PA15A_EIC_EXTINT15)</td></tr>
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<tr class="separator:aa82833fe8b0e407c256328205ffa03a7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1ba0268457afacea6a282cd387e957c5"><td class="memItemLeft" align="right" valign="top"><a id="a1ba0268457afacea6a282cd387e957c5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA15A_EIC_EXTINT15</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 15)</td></tr>
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<tr class="separator:a1ba0268457afacea6a282cd387e957c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a04708a0ba5288c8c83fa7f9951e67108"><td class="memItemLeft" align="right" valign="top"><a id="a04708a0ba5288c8c83fa7f9951e67108"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a04708a0ba5288c8c83fa7f9951e67108">PIN_PA15A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(15)</td></tr>
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<tr class="memdesc:a04708a0ba5288c8c83fa7f9951e67108"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PA15 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a04708a0ba5288c8c83fa7f9951e67108"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6cd3d723ca05fcfd7304061e94ab9ba5"><td class="memItemLeft" align="right" valign="top"><a id="a6cd3d723ca05fcfd7304061e94ab9ba5"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6cd3d723ca05fcfd7304061e94ab9ba5">PIN_PA31A_EIC_EXTINT15</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(31)</td></tr>
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<tr class="memdesc:a6cd3d723ca05fcfd7304061e94ab9ba5"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT15 on PA31 mux A. <br /></td></tr>
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<tr class="separator:a6cd3d723ca05fcfd7304061e94ab9ba5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2c553098ba56862a2461969da78f74d8"><td class="memItemLeft" align="right" valign="top"><a id="a2c553098ba56862a2461969da78f74d8"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA31A_EIC_EXTINT15</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a2c553098ba56862a2461969da78f74d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a04ecabfccfaf12079385c37488a48365"><td class="memItemLeft" align="right" valign="top"><a id="a04ecabfccfaf12079385c37488a48365"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA31A_EIC_EXTINT15</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a6cd3d723ca05fcfd7304061e94ab9ba5">PIN_PA31A_EIC_EXTINT15</a> << 16) | MUX_PA31A_EIC_EXTINT15)</td></tr>
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<tr class="separator:a04ecabfccfaf12079385c37488a48365"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5bf3452f8f0f51238699ba569fb0294e"><td class="memItemLeft" align="right" valign="top"><a id="a5bf3452f8f0f51238699ba569fb0294e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA31A_EIC_EXTINT15</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 31)</td></tr>
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<tr class="separator:a5bf3452f8f0f51238699ba569fb0294e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac167894f3689f4ed6bb85f957a075458"><td class="memItemLeft" align="right" valign="top"><a id="ac167894f3689f4ed6bb85f957a075458"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac167894f3689f4ed6bb85f957a075458">PIN_PA31A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(15)</td></tr>
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||
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<tr class="memdesc:ac167894f3689f4ed6bb85f957a075458"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PA31 External Interrupt Line. <br /></td></tr>
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<tr class="separator:ac167894f3689f4ed6bb85f957a075458"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2c1ca8280e17a6d444adcd97451e4bbf"><td class="memItemLeft" align="right" valign="top"><a id="a2c1ca8280e17a6d444adcd97451e4bbf"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2c1ca8280e17a6d444adcd97451e4bbf">PIN_PB15A_EIC_EXTINT15</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(47)</td></tr>
|
||
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<tr class="memdesc:a2c1ca8280e17a6d444adcd97451e4bbf"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT15 on PB15 mux A. <br /></td></tr>
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<tr class="separator:a2c1ca8280e17a6d444adcd97451e4bbf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa01d8a9c2f695d01f97b6e6fa6db0569"><td class="memItemLeft" align="right" valign="top"><a id="aa01d8a9c2f695d01f97b6e6fa6db0569"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB15A_EIC_EXTINT15</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:aa01d8a9c2f695d01f97b6e6fa6db0569"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae62d0f19e68ed9f40d154a62c818ad37"><td class="memItemLeft" align="right" valign="top"><a id="ae62d0f19e68ed9f40d154a62c818ad37"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB15A_EIC_EXTINT15</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a2c1ca8280e17a6d444adcd97451e4bbf">PIN_PB15A_EIC_EXTINT15</a> << 16) | MUX_PB15A_EIC_EXTINT15)</td></tr>
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<tr class="separator:ae62d0f19e68ed9f40d154a62c818ad37"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab10ac696e83fe283b49ff47323fa935a"><td class="memItemLeft" align="right" valign="top"><a id="ab10ac696e83fe283b49ff47323fa935a"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB15A_EIC_EXTINT15</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 15)</td></tr>
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<tr class="separator:ab10ac696e83fe283b49ff47323fa935a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a05751f6bb89213029c029c1c044b55a1"><td class="memItemLeft" align="right" valign="top"><a id="a05751f6bb89213029c029c1c044b55a1"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a05751f6bb89213029c029c1c044b55a1">PIN_PB15A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(15)</td></tr>
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||
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<tr class="memdesc:a05751f6bb89213029c029c1c044b55a1"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PB15 External Interrupt Line. <br /></td></tr>
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<tr class="separator:a05751f6bb89213029c029c1c044b55a1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7b7eedd2bc11496a2d6e3b0ce088b1a8"><td class="memItemLeft" align="right" valign="top"><a id="a7b7eedd2bc11496a2d6e3b0ce088b1a8"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7b7eedd2bc11496a2d6e3b0ce088b1a8">PIN_PB31A_EIC_EXTINT15</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(63)</td></tr>
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||
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<tr class="memdesc:a7b7eedd2bc11496a2d6e3b0ce088b1a8"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT15 on PB31 mux A. <br /></td></tr>
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<tr class="separator:a7b7eedd2bc11496a2d6e3b0ce088b1a8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4d02ee50a82d4a25ae368b5d721bdffe"><td class="memItemLeft" align="right" valign="top"><a id="a4d02ee50a82d4a25ae368b5d721bdffe"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB31A_EIC_EXTINT15</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a4d02ee50a82d4a25ae368b5d721bdffe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a912f20c733cbea9bd0f3b6c684078535"><td class="memItemLeft" align="right" valign="top"><a id="a912f20c733cbea9bd0f3b6c684078535"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB31A_EIC_EXTINT15</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a7b7eedd2bc11496a2d6e3b0ce088b1a8">PIN_PB31A_EIC_EXTINT15</a> << 16) | MUX_PB31A_EIC_EXTINT15)</td></tr>
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<tr class="separator:a912f20c733cbea9bd0f3b6c684078535"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a735c05a88e3cebf51572b9d3e38193df"><td class="memItemLeft" align="right" valign="top"><a id="a735c05a88e3cebf51572b9d3e38193df"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB31A_EIC_EXTINT15</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 31)</td></tr>
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<tr class="separator:a735c05a88e3cebf51572b9d3e38193df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abc5b58d0f258b283d19c693854b815b2"><td class="memItemLeft" align="right" valign="top"><a id="abc5b58d0f258b283d19c693854b815b2"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#abc5b58d0f258b283d19c693854b815b2">PIN_PB31A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(15)</td></tr>
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||
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<tr class="memdesc:abc5b58d0f258b283d19c693854b815b2"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PB31 External Interrupt Line. <br /></td></tr>
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<tr class="separator:abc5b58d0f258b283d19c693854b815b2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7ddcaa66fca7de1e5b0478242247c162"><td class="memItemLeft" align="right" valign="top"><a id="a7ddcaa66fca7de1e5b0478242247c162"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7ddcaa66fca7de1e5b0478242247c162">PIN_PC15A_EIC_EXTINT15</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(79)</td></tr>
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||
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<tr class="memdesc:a7ddcaa66fca7de1e5b0478242247c162"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: EXTINT15 on PC15 mux A. <br /></td></tr>
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<tr class="separator:a7ddcaa66fca7de1e5b0478242247c162"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a61e618321b491dd45f6f512ca6e840d9"><td class="memItemLeft" align="right" valign="top"><a id="a61e618321b491dd45f6f512ca6e840d9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC15A_EIC_EXTINT15</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a61e618321b491dd45f6f512ca6e840d9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4a913070a899274d1d85b3785b96682e"><td class="memItemLeft" align="right" valign="top"><a id="a4a913070a899274d1d85b3785b96682e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC15A_EIC_EXTINT15</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a7ddcaa66fca7de1e5b0478242247c162">PIN_PC15A_EIC_EXTINT15</a> << 16) | MUX_PC15A_EIC_EXTINT15)</td></tr>
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<tr class="separator:a4a913070a899274d1d85b3785b96682e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0ad43f64a02035c019fd22ceedf66b21"><td class="memItemLeft" align="right" valign="top"><a id="a0ad43f64a02035c019fd22ceedf66b21"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC15A_EIC_EXTINT15</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 15)</td></tr>
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<tr class="separator:a0ad43f64a02035c019fd22ceedf66b21"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aab2fbc27e2c4dac81f43ccafd97fc1ac"><td class="memItemLeft" align="right" valign="top"><a id="aab2fbc27e2c4dac81f43ccafd97fc1ac"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aab2fbc27e2c4dac81f43ccafd97fc1ac">PIN_PC15A_EIC_EXTINT_NUM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(15)</td></tr>
|
||
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<tr class="memdesc:aab2fbc27e2c4dac81f43ccafd97fc1ac"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: PIN_PC15 External Interrupt Line. <br /></td></tr>
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<tr class="separator:aab2fbc27e2c4dac81f43ccafd97fc1ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1082084482a49eaf19b717ea1a7bb3ad"><td class="memItemLeft" align="right" valign="top"><a id="a1082084482a49eaf19b717ea1a7bb3ad"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1082084482a49eaf19b717ea1a7bb3ad">PIN_PA08A_EIC_NMI</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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||
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<tr class="memdesc:a1082084482a49eaf19b717ea1a7bb3ad"><td class="mdescLeft"> </td><td class="mdescRight">EIC signal: NMI on PA08 mux A. <br /></td></tr>
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<tr class="separator:a1082084482a49eaf19b717ea1a7bb3ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5328c5c8021b33b51b63f187ed173390"><td class="memItemLeft" align="right" valign="top"><a id="a5328c5c8021b33b51b63f187ed173390"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA08A_EIC_NMI</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
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<tr class="separator:a5328c5c8021b33b51b63f187ed173390"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aeb76f4d8b7ecae628b6e71099bd1ce58"><td class="memItemLeft" align="right" valign="top"><a id="aeb76f4d8b7ecae628b6e71099bd1ce58"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA08A_EIC_NMI</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a1082084482a49eaf19b717ea1a7bb3ad">PIN_PA08A_EIC_NMI</a> << 16) | MUX_PA08A_EIC_NMI)</td></tr>
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<tr class="separator:aeb76f4d8b7ecae628b6e71099bd1ce58"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a08bf77f657857513cab021c089de731a"><td class="memItemLeft" align="right" valign="top"><a id="a08bf77f657857513cab021c089de731a"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA08A_EIC_NMI</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 8)</td></tr>
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||
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<tr class="separator:a08bf77f657857513cab021c089de731a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a179ea5ec9f89f81e55c6888eb824d068"><td class="memItemLeft" align="right" valign="top"><a id="a179ea5ec9f89f81e55c6888eb824d068"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a179ea5ec9f89f81e55c6888eb824d068">PIN_PA04D_SERCOM0_PAD0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
|
||
|
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<tr class="memdesc:a179ea5ec9f89f81e55c6888eb824d068"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM0 signal: PAD0 on PA04 mux D. <br /></td></tr>
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<tr class="separator:a179ea5ec9f89f81e55c6888eb824d068"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8e8324cbccc3035afacafd70f27af149"><td class="memItemLeft" align="right" valign="top"><a id="a8e8324cbccc3035afacafd70f27af149"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA04D_SERCOM0_PAD0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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||
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<tr class="separator:a8e8324cbccc3035afacafd70f27af149"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a713922b8d0cfc81d4825b7f86b0af387"><td class="memItemLeft" align="right" valign="top"><a id="a713922b8d0cfc81d4825b7f86b0af387"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA04D_SERCOM0_PAD0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a179ea5ec9f89f81e55c6888eb824d068">PIN_PA04D_SERCOM0_PAD0</a> << 16) | MUX_PA04D_SERCOM0_PAD0)</td></tr>
|
||
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<tr class="separator:a713922b8d0cfc81d4825b7f86b0af387"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a23d319898dd21ef56b838e5456396975"><td class="memItemLeft" align="right" valign="top"><a id="a23d319898dd21ef56b838e5456396975"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA04D_SERCOM0_PAD0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 4)</td></tr>
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||
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<tr class="separator:a23d319898dd21ef56b838e5456396975"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af82f0b07767c68a5157629f3b61921fb"><td class="memItemLeft" align="right" valign="top"><a id="af82f0b07767c68a5157629f3b61921fb"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af82f0b07767c68a5157629f3b61921fb">PIN_PC17D_SERCOM0_PAD0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(81)</td></tr>
|
||
|
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<tr class="memdesc:af82f0b07767c68a5157629f3b61921fb"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM0 signal: PAD0 on PC17 mux D. <br /></td></tr>
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||
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<tr class="separator:af82f0b07767c68a5157629f3b61921fb"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a284c0b55899720d1a7563d7d25de827d"><td class="memItemLeft" align="right" valign="top"><a id="a284c0b55899720d1a7563d7d25de827d"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC17D_SERCOM0_PAD0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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||
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<tr class="separator:a284c0b55899720d1a7563d7d25de827d"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a7a6b93edb140ad404b471a657ac0d7ee"><td class="memItemLeft" align="right" valign="top"><a id="a7a6b93edb140ad404b471a657ac0d7ee"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC17D_SERCOM0_PAD0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#af82f0b07767c68a5157629f3b61921fb">PIN_PC17D_SERCOM0_PAD0</a> << 16) | MUX_PC17D_SERCOM0_PAD0)</td></tr>
|
||
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<tr class="separator:a7a6b93edb140ad404b471a657ac0d7ee"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:ab26d5ff6652f087dadd3414b4e52318c"><td class="memItemLeft" align="right" valign="top"><a id="ab26d5ff6652f087dadd3414b4e52318c"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC17D_SERCOM0_PAD0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 17)</td></tr>
|
||
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<tr class="separator:ab26d5ff6652f087dadd3414b4e52318c"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a7932baad01e0dab934e930095d07bcd6"><td class="memItemLeft" align="right" valign="top"><a id="a7932baad01e0dab934e930095d07bcd6"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7932baad01e0dab934e930095d07bcd6">PIN_PA08C_SERCOM0_PAD0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
|
||
|
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<tr class="memdesc:a7932baad01e0dab934e930095d07bcd6"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM0 signal: PAD0 on PA08 mux C. <br /></td></tr>
|
||
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<tr class="separator:a7932baad01e0dab934e930095d07bcd6"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:af5ce60440662e4e2916a8fd41a58beed"><td class="memItemLeft" align="right" valign="top"><a id="af5ce60440662e4e2916a8fd41a58beed"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA08C_SERCOM0_PAD0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
|
||
|
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<tr class="separator:af5ce60440662e4e2916a8fd41a58beed"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:ab0d7bbfa94f1f6e8c6668f0d5ec7048d"><td class="memItemLeft" align="right" valign="top"><a id="ab0d7bbfa94f1f6e8c6668f0d5ec7048d"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA08C_SERCOM0_PAD0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a7932baad01e0dab934e930095d07bcd6">PIN_PA08C_SERCOM0_PAD0</a> << 16) | MUX_PA08C_SERCOM0_PAD0)</td></tr>
|
||
|
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<tr class="separator:ab0d7bbfa94f1f6e8c6668f0d5ec7048d"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:ad06fd0dbb089460e2dcec043021add98"><td class="memItemLeft" align="right" valign="top"><a id="ad06fd0dbb089460e2dcec043021add98"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA08C_SERCOM0_PAD0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 8)</td></tr>
|
||
|
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<tr class="separator:ad06fd0dbb089460e2dcec043021add98"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a68c65cb9314acd3059939a65386da260"><td class="memItemLeft" align="right" valign="top"><a id="a68c65cb9314acd3059939a65386da260"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a68c65cb9314acd3059939a65386da260">PIN_PB24C_SERCOM0_PAD0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(56)</td></tr>
|
||
|
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<tr class="memdesc:a68c65cb9314acd3059939a65386da260"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM0 signal: PAD0 on PB24 mux C. <br /></td></tr>
|
||
|
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<tr class="separator:a68c65cb9314acd3059939a65386da260"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a9dee09c689062e15ce5eba41e4664e93"><td class="memItemLeft" align="right" valign="top"><a id="a9dee09c689062e15ce5eba41e4664e93"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB24C_SERCOM0_PAD0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
|
||
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<tr class="separator:a9dee09c689062e15ce5eba41e4664e93"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a3cef9bedf91cfe16d93b468cdb786371"><td class="memItemLeft" align="right" valign="top"><a id="a3cef9bedf91cfe16d93b468cdb786371"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB24C_SERCOM0_PAD0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a68c65cb9314acd3059939a65386da260">PIN_PB24C_SERCOM0_PAD0</a> << 16) | MUX_PB24C_SERCOM0_PAD0)</td></tr>
|
||
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<tr class="separator:a3cef9bedf91cfe16d93b468cdb786371"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:ac6008b648989ef35f592b1de0cc43672"><td class="memItemLeft" align="right" valign="top"><a id="ac6008b648989ef35f592b1de0cc43672"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB24C_SERCOM0_PAD0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 24)</td></tr>
|
||
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<tr class="separator:ac6008b648989ef35f592b1de0cc43672"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:ad4d21dc85a7896730e71d86ef2257ce7"><td class="memItemLeft" align="right" valign="top"><a id="ad4d21dc85a7896730e71d86ef2257ce7"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad4d21dc85a7896730e71d86ef2257ce7">PIN_PA05D_SERCOM0_PAD1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
|
||
|
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<tr class="memdesc:ad4d21dc85a7896730e71d86ef2257ce7"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM0 signal: PAD1 on PA05 mux D. <br /></td></tr>
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||
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<tr class="separator:ad4d21dc85a7896730e71d86ef2257ce7"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a362da559e366e93a9bc77161ac522407"><td class="memItemLeft" align="right" valign="top"><a id="a362da559e366e93a9bc77161ac522407"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA05D_SERCOM0_PAD1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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||
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<tr class="separator:a362da559e366e93a9bc77161ac522407"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:af8ccef59b8088e0ac4d3b60a243716b0"><td class="memItemLeft" align="right" valign="top"><a id="af8ccef59b8088e0ac4d3b60a243716b0"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA05D_SERCOM0_PAD1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ad4d21dc85a7896730e71d86ef2257ce7">PIN_PA05D_SERCOM0_PAD1</a> << 16) | MUX_PA05D_SERCOM0_PAD1)</td></tr>
|
||
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<tr class="separator:af8ccef59b8088e0ac4d3b60a243716b0"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a45bb47472d700e552604c14b8a7d32ef"><td class="memItemLeft" align="right" valign="top"><a id="a45bb47472d700e552604c14b8a7d32ef"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA05D_SERCOM0_PAD1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 5)</td></tr>
|
||
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<tr class="separator:a45bb47472d700e552604c14b8a7d32ef"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:af1f93a79bbac9d49650c6f2eda340468"><td class="memItemLeft" align="right" valign="top"><a id="af1f93a79bbac9d49650c6f2eda340468"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af1f93a79bbac9d49650c6f2eda340468">PIN_PC16D_SERCOM0_PAD1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(80)</td></tr>
|
||
|
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<tr class="memdesc:af1f93a79bbac9d49650c6f2eda340468"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM0 signal: PAD1 on PC16 mux D. <br /></td></tr>
|
||
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<tr class="separator:af1f93a79bbac9d49650c6f2eda340468"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a1bfd7b96db912e490413ae3704670c3a"><td class="memItemLeft" align="right" valign="top"><a id="a1bfd7b96db912e490413ae3704670c3a"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC16D_SERCOM0_PAD1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
|
||
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<tr class="separator:a1bfd7b96db912e490413ae3704670c3a"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a1972b369a55094e59bd586c38464eeb3"><td class="memItemLeft" align="right" valign="top"><a id="a1972b369a55094e59bd586c38464eeb3"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC16D_SERCOM0_PAD1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#af1f93a79bbac9d49650c6f2eda340468">PIN_PC16D_SERCOM0_PAD1</a> << 16) | MUX_PC16D_SERCOM0_PAD1)</td></tr>
|
||
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<tr class="separator:a1972b369a55094e59bd586c38464eeb3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7c211bb6529943fd506f05d0e2d228c3"><td class="memItemLeft" align="right" valign="top"><a id="a7c211bb6529943fd506f05d0e2d228c3"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC16D_SERCOM0_PAD1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 16)</td></tr>
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<tr class="separator:a7c211bb6529943fd506f05d0e2d228c3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9f5d8762f7ec6b0dcac7c7b86fb12601"><td class="memItemLeft" align="right" valign="top"><a id="a9f5d8762f7ec6b0dcac7c7b86fb12601"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a9f5d8762f7ec6b0dcac7c7b86fb12601">PIN_PA09C_SERCOM0_PAD1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
|
||
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<tr class="memdesc:a9f5d8762f7ec6b0dcac7c7b86fb12601"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM0 signal: PAD1 on PA09 mux C. <br /></td></tr>
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<tr class="separator:a9f5d8762f7ec6b0dcac7c7b86fb12601"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8af6d194e0161e10b49f4c1f4ab9b134"><td class="memItemLeft" align="right" valign="top"><a id="a8af6d194e0161e10b49f4c1f4ab9b134"></a>
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA09C_SERCOM0_PAD1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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<tr class="separator:a8af6d194e0161e10b49f4c1f4ab9b134"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a02ae6a6881ed2c20aefaf2291f0c9487"><td class="memItemLeft" align="right" valign="top"><a id="a02ae6a6881ed2c20aefaf2291f0c9487"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA09C_SERCOM0_PAD1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a9f5d8762f7ec6b0dcac7c7b86fb12601">PIN_PA09C_SERCOM0_PAD1</a> << 16) | MUX_PA09C_SERCOM0_PAD1)</td></tr>
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<tr class="separator:a02ae6a6881ed2c20aefaf2291f0c9487"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a1f18cf8f69a3845958684a7364d3b1a6"><td class="memItemLeft" align="right" valign="top"><a id="a1f18cf8f69a3845958684a7364d3b1a6"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA09C_SERCOM0_PAD1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 9)</td></tr>
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||
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<tr class="separator:a1f18cf8f69a3845958684a7364d3b1a6"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a027cd8b69276dbef2c76f5e793d8e3d5"><td class="memItemLeft" align="right" valign="top"><a id="a027cd8b69276dbef2c76f5e793d8e3d5"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a027cd8b69276dbef2c76f5e793d8e3d5">PIN_PB25C_SERCOM0_PAD1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(57)</td></tr>
|
||
|
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<tr class="memdesc:a027cd8b69276dbef2c76f5e793d8e3d5"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM0 signal: PAD1 on PB25 mux C. <br /></td></tr>
|
||
|
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<tr class="separator:a027cd8b69276dbef2c76f5e793d8e3d5"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:ac98b0e644669237ab442671be0e60024"><td class="memItemLeft" align="right" valign="top"><a id="ac98b0e644669237ab442671be0e60024"></a>
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||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB25C_SERCOM0_PAD1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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||
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<tr class="separator:ac98b0e644669237ab442671be0e60024"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3c0c4033ceceaa16053b58e842069882"><td class="memItemLeft" align="right" valign="top"><a id="a3c0c4033ceceaa16053b58e842069882"></a>
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||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB25C_SERCOM0_PAD1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a027cd8b69276dbef2c76f5e793d8e3d5">PIN_PB25C_SERCOM0_PAD1</a> << 16) | MUX_PB25C_SERCOM0_PAD1)</td></tr>
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<tr class="separator:a3c0c4033ceceaa16053b58e842069882"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:acab84d7fcfd505a488d06d8863f7dcc2"><td class="memItemLeft" align="right" valign="top"><a id="acab84d7fcfd505a488d06d8863f7dcc2"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB25C_SERCOM0_PAD1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 25)</td></tr>
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||
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<tr class="separator:acab84d7fcfd505a488d06d8863f7dcc2"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a98a180a87e96b753c4f160089bb07718"><td class="memItemLeft" align="right" valign="top"><a id="a98a180a87e96b753c4f160089bb07718"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a98a180a87e96b753c4f160089bb07718">PIN_PA06D_SERCOM0_PAD2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
|
||
|
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<tr class="memdesc:a98a180a87e96b753c4f160089bb07718"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM0 signal: PAD2 on PA06 mux D. <br /></td></tr>
|
||
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<tr class="separator:a98a180a87e96b753c4f160089bb07718"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a25de23edd1641cf6eaf5ad387cd628d6"><td class="memItemLeft" align="right" valign="top"><a id="a25de23edd1641cf6eaf5ad387cd628d6"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA06D_SERCOM0_PAD2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
|
||
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<tr class="separator:a25de23edd1641cf6eaf5ad387cd628d6"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:aaee1db140cc139a595c34cc55d03f6b8"><td class="memItemLeft" align="right" valign="top"><a id="aaee1db140cc139a595c34cc55d03f6b8"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA06D_SERCOM0_PAD2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a98a180a87e96b753c4f160089bb07718">PIN_PA06D_SERCOM0_PAD2</a> << 16) | MUX_PA06D_SERCOM0_PAD2)</td></tr>
|
||
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<tr class="separator:aaee1db140cc139a595c34cc55d03f6b8"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:ae5a636f4bc1ddd0610037e7575b21fa0"><td class="memItemLeft" align="right" valign="top"><a id="ae5a636f4bc1ddd0610037e7575b21fa0"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA06D_SERCOM0_PAD2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 6)</td></tr>
|
||
|
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<tr class="separator:ae5a636f4bc1ddd0610037e7575b21fa0"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a852521514fdecc6b2c89ba04401095f7"><td class="memItemLeft" align="right" valign="top"><a id="a852521514fdecc6b2c89ba04401095f7"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a852521514fdecc6b2c89ba04401095f7">PIN_PC18D_SERCOM0_PAD2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(82)</td></tr>
|
||
|
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<tr class="memdesc:a852521514fdecc6b2c89ba04401095f7"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM0 signal: PAD2 on PC18 mux D. <br /></td></tr>
|
||
|
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<tr class="separator:a852521514fdecc6b2c89ba04401095f7"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:adc7733e06232b6ecb28b9fb0329a5c87"><td class="memItemLeft" align="right" valign="top"><a id="adc7733e06232b6ecb28b9fb0329a5c87"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC18D_SERCOM0_PAD2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
|
||
|
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<tr class="separator:adc7733e06232b6ecb28b9fb0329a5c87"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:a6ff1b93514705412fceddb40b2eecadc"><td class="memItemLeft" align="right" valign="top"><a id="a6ff1b93514705412fceddb40b2eecadc"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC18D_SERCOM0_PAD2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a852521514fdecc6b2c89ba04401095f7">PIN_PC18D_SERCOM0_PAD2</a> << 16) | MUX_PC18D_SERCOM0_PAD2)</td></tr>
|
||
|
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<tr class="separator:a6ff1b93514705412fceddb40b2eecadc"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:a265ef0c36e1e0ffcd0bebd5070a677a1"><td class="memItemLeft" align="right" valign="top"><a id="a265ef0c36e1e0ffcd0bebd5070a677a1"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC18D_SERCOM0_PAD2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 18)</td></tr>
|
||
|
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<tr class="separator:a265ef0c36e1e0ffcd0bebd5070a677a1"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:aaf92a25fb30b2f6e4aa133df5bab7e4d"><td class="memItemLeft" align="right" valign="top"><a id="aaf92a25fb30b2f6e4aa133df5bab7e4d"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aaf92a25fb30b2f6e4aa133df5bab7e4d">PIN_PA10C_SERCOM0_PAD2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
|
||
|
|
<tr class="memdesc:aaf92a25fb30b2f6e4aa133df5bab7e4d"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM0 signal: PAD2 on PA10 mux C. <br /></td></tr>
|
||
|
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<tr class="separator:aaf92a25fb30b2f6e4aa133df5bab7e4d"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:a6a8b277af50be354044f0e52b0a10363"><td class="memItemLeft" align="right" valign="top"><a id="a6a8b277af50be354044f0e52b0a10363"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA10C_SERCOM0_PAD2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
|
||
|
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<tr class="separator:a6a8b277af50be354044f0e52b0a10363"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:a4b83a7f81d56fae5703ec1e226a3c06e"><td class="memItemLeft" align="right" valign="top"><a id="a4b83a7f81d56fae5703ec1e226a3c06e"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA10C_SERCOM0_PAD2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aaf92a25fb30b2f6e4aa133df5bab7e4d">PIN_PA10C_SERCOM0_PAD2</a> << 16) | MUX_PA10C_SERCOM0_PAD2)</td></tr>
|
||
|
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<tr class="separator:a4b83a7f81d56fae5703ec1e226a3c06e"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:abe20d3a20a40556c96be667e49788451"><td class="memItemLeft" align="right" valign="top"><a id="abe20d3a20a40556c96be667e49788451"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA10C_SERCOM0_PAD2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 10)</td></tr>
|
||
|
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<tr class="separator:abe20d3a20a40556c96be667e49788451"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:a464743cf87518ab58841dbb67cdcf839"><td class="memItemLeft" align="right" valign="top"><a id="a464743cf87518ab58841dbb67cdcf839"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a464743cf87518ab58841dbb67cdcf839">PIN_PC24C_SERCOM0_PAD2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(88)</td></tr>
|
||
|
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<tr class="memdesc:a464743cf87518ab58841dbb67cdcf839"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM0 signal: PAD2 on PC24 mux C. <br /></td></tr>
|
||
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<tr class="separator:a464743cf87518ab58841dbb67cdcf839"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a1caa1fef5bb642856149691453193cae"><td class="memItemLeft" align="right" valign="top"><a id="a1caa1fef5bb642856149691453193cae"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC24C_SERCOM0_PAD2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
|
||
|
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<tr class="separator:a1caa1fef5bb642856149691453193cae"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a1fa05c75f4b64e1f059a41733f063816"><td class="memItemLeft" align="right" valign="top"><a id="a1fa05c75f4b64e1f059a41733f063816"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC24C_SERCOM0_PAD2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a464743cf87518ab58841dbb67cdcf839">PIN_PC24C_SERCOM0_PAD2</a> << 16) | MUX_PC24C_SERCOM0_PAD2)</td></tr>
|
||
|
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<tr class="separator:a1fa05c75f4b64e1f059a41733f063816"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:a0f02d6b9ac8d54d63dd80ef0953b520c"><td class="memItemLeft" align="right" valign="top"><a id="a0f02d6b9ac8d54d63dd80ef0953b520c"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC24C_SERCOM0_PAD2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 24)</td></tr>
|
||
|
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<tr class="separator:a0f02d6b9ac8d54d63dd80ef0953b520c"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:ab0d8d9333afa2bfd599a2b08a3af2997"><td class="memItemLeft" align="right" valign="top"><a id="ab0d8d9333afa2bfd599a2b08a3af2997"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab0d8d9333afa2bfd599a2b08a3af2997">PIN_PA07D_SERCOM0_PAD3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
|
||
|
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<tr class="memdesc:ab0d8d9333afa2bfd599a2b08a3af2997"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM0 signal: PAD3 on PA07 mux D. <br /></td></tr>
|
||
|
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<tr class="separator:ab0d8d9333afa2bfd599a2b08a3af2997"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:ac2957b6c89f052335e9235e1438fe71b"><td class="memItemLeft" align="right" valign="top"><a id="ac2957b6c89f052335e9235e1438fe71b"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA07D_SERCOM0_PAD3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
|
||
|
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<tr class="separator:ac2957b6c89f052335e9235e1438fe71b"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:acd0fbf9c178814bd35328744a3f6df97"><td class="memItemLeft" align="right" valign="top"><a id="acd0fbf9c178814bd35328744a3f6df97"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA07D_SERCOM0_PAD3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ab0d8d9333afa2bfd599a2b08a3af2997">PIN_PA07D_SERCOM0_PAD3</a> << 16) | MUX_PA07D_SERCOM0_PAD3)</td></tr>
|
||
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<tr class="separator:acd0fbf9c178814bd35328744a3f6df97"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a7ba581e683fc05c49a691cef52427dc6"><td class="memItemLeft" align="right" valign="top"><a id="a7ba581e683fc05c49a691cef52427dc6"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA07D_SERCOM0_PAD3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 7)</td></tr>
|
||
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<tr class="separator:a7ba581e683fc05c49a691cef52427dc6"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a7c38c4bae42bda928c5cc59815707783"><td class="memItemLeft" align="right" valign="top"><a id="a7c38c4bae42bda928c5cc59815707783"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7c38c4bae42bda928c5cc59815707783">PIN_PC19D_SERCOM0_PAD3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(83)</td></tr>
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<tr class="memdesc:a7c38c4bae42bda928c5cc59815707783"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM0 signal: PAD3 on PC19 mux D. <br /></td></tr>
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<tr class="separator:a7c38c4bae42bda928c5cc59815707783"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afd281c898eba8a8c722852d469a51f01"><td class="memItemLeft" align="right" valign="top"><a id="afd281c898eba8a8c722852d469a51f01"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC19D_SERCOM0_PAD3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="separator:afd281c898eba8a8c722852d469a51f01"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a81a28089866d29c9a067e4e7dbc04c16"><td class="memItemLeft" align="right" valign="top"><a id="a81a28089866d29c9a067e4e7dbc04c16"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC19D_SERCOM0_PAD3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a7c38c4bae42bda928c5cc59815707783">PIN_PC19D_SERCOM0_PAD3</a> << 16) | MUX_PC19D_SERCOM0_PAD3)</td></tr>
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<tr class="separator:a81a28089866d29c9a067e4e7dbc04c16"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa5334e2910af0a1d0380767655fb9dcc"><td class="memItemLeft" align="right" valign="top"><a id="aa5334e2910af0a1d0380767655fb9dcc"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC19D_SERCOM0_PAD3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 19)</td></tr>
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<tr class="separator:aa5334e2910af0a1d0380767655fb9dcc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a60e3a9a915d036f33dc5e928877f81b8"><td class="memItemLeft" align="right" valign="top"><a id="a60e3a9a915d036f33dc5e928877f81b8"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a60e3a9a915d036f33dc5e928877f81b8">PIN_PA11C_SERCOM0_PAD3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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||
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<tr class="memdesc:a60e3a9a915d036f33dc5e928877f81b8"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM0 signal: PAD3 on PA11 mux C. <br /></td></tr>
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<tr class="separator:a60e3a9a915d036f33dc5e928877f81b8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac613c101e48b4cadeeadee08968d2651"><td class="memItemLeft" align="right" valign="top"><a id="ac613c101e48b4cadeeadee08968d2651"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA11C_SERCOM0_PAD3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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<tr class="separator:ac613c101e48b4cadeeadee08968d2651"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a934adc4f69392ac742fdbd5c71dac08b"><td class="memItemLeft" align="right" valign="top"><a id="a934adc4f69392ac742fdbd5c71dac08b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA11C_SERCOM0_PAD3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a60e3a9a915d036f33dc5e928877f81b8">PIN_PA11C_SERCOM0_PAD3</a> << 16) | MUX_PA11C_SERCOM0_PAD3)</td></tr>
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<tr class="separator:a934adc4f69392ac742fdbd5c71dac08b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a92390776053d4c31744fadcf9dc5b956"><td class="memItemLeft" align="right" valign="top"><a id="a92390776053d4c31744fadcf9dc5b956"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA11C_SERCOM0_PAD3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 11)</td></tr>
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<tr class="separator:a92390776053d4c31744fadcf9dc5b956"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a433553a16e011f69a5cd45b84ab93927"><td class="memItemLeft" align="right" valign="top"><a id="a433553a16e011f69a5cd45b84ab93927"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a433553a16e011f69a5cd45b84ab93927">PIN_PC25C_SERCOM0_PAD3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(89)</td></tr>
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||
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<tr class="memdesc:a433553a16e011f69a5cd45b84ab93927"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM0 signal: PAD3 on PC25 mux C. <br /></td></tr>
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<tr class="separator:a433553a16e011f69a5cd45b84ab93927"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac284725d1627d909b08e3c48dc0c3670"><td class="memItemLeft" align="right" valign="top"><a id="ac284725d1627d909b08e3c48dc0c3670"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC25C_SERCOM0_PAD3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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<tr class="separator:ac284725d1627d909b08e3c48dc0c3670"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad463cc74d0bc17a331089bd25f309883"><td class="memItemLeft" align="right" valign="top"><a id="ad463cc74d0bc17a331089bd25f309883"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC25C_SERCOM0_PAD3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a433553a16e011f69a5cd45b84ab93927">PIN_PC25C_SERCOM0_PAD3</a> << 16) | MUX_PC25C_SERCOM0_PAD3)</td></tr>
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<tr class="separator:ad463cc74d0bc17a331089bd25f309883"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac94adafa1742eed36d5806d87c81539c"><td class="memItemLeft" align="right" valign="top"><a id="ac94adafa1742eed36d5806d87c81539c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC25C_SERCOM0_PAD3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 25)</td></tr>
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||
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<tr class="separator:ac94adafa1742eed36d5806d87c81539c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7f1a5fa24eb08e5056d1eb8eefe6a14c"><td class="memItemLeft" align="right" valign="top"><a id="a7f1a5fa24eb08e5056d1eb8eefe6a14c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7f1a5fa24eb08e5056d1eb8eefe6a14c">PIN_PA00D_SERCOM1_PAD0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
|
||
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<tr class="memdesc:a7f1a5fa24eb08e5056d1eb8eefe6a14c"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM1 signal: PAD0 on PA00 mux D. <br /></td></tr>
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<tr class="separator:a7f1a5fa24eb08e5056d1eb8eefe6a14c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a44e28f475a8417d8a0df6dff0533275c"><td class="memItemLeft" align="right" valign="top"><a id="a44e28f475a8417d8a0df6dff0533275c"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA00D_SERCOM1_PAD0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="separator:a44e28f475a8417d8a0df6dff0533275c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af243556f5a6f2b6ef1b27419714f47f8"><td class="memItemLeft" align="right" valign="top"><a id="af243556f5a6f2b6ef1b27419714f47f8"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA00D_SERCOM1_PAD0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a7f1a5fa24eb08e5056d1eb8eefe6a14c">PIN_PA00D_SERCOM1_PAD0</a> << 16) | MUX_PA00D_SERCOM1_PAD0)</td></tr>
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<tr class="separator:af243556f5a6f2b6ef1b27419714f47f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a04fde95efc3090c95f29ad8d74211f58"><td class="memItemLeft" align="right" valign="top"><a id="a04fde95efc3090c95f29ad8d74211f58"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA00D_SERCOM1_PAD0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 0)</td></tr>
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||
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<tr class="separator:a04fde95efc3090c95f29ad8d74211f58"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afe7b3ffb79c98ff2acbeec19eccfe9d0"><td class="memItemLeft" align="right" valign="top"><a id="afe7b3ffb79c98ff2acbeec19eccfe9d0"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#afe7b3ffb79c98ff2acbeec19eccfe9d0">PIN_PA16C_SERCOM1_PAD0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(16)</td></tr>
|
||
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<tr class="memdesc:afe7b3ffb79c98ff2acbeec19eccfe9d0"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM1 signal: PAD0 on PA16 mux C. <br /></td></tr>
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<tr class="separator:afe7b3ffb79c98ff2acbeec19eccfe9d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3a49267e065d8a58120c73f8ee34365b"><td class="memItemLeft" align="right" valign="top"><a id="a3a49267e065d8a58120c73f8ee34365b"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA16C_SERCOM1_PAD0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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||
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<tr class="separator:a3a49267e065d8a58120c73f8ee34365b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4ad061fad9fa2c90b4930fc7a437b61c"><td class="memItemLeft" align="right" valign="top"><a id="a4ad061fad9fa2c90b4930fc7a437b61c"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA16C_SERCOM1_PAD0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#afe7b3ffb79c98ff2acbeec19eccfe9d0">PIN_PA16C_SERCOM1_PAD0</a> << 16) | MUX_PA16C_SERCOM1_PAD0)</td></tr>
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<tr class="separator:a4ad061fad9fa2c90b4930fc7a437b61c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a67930502b6d950cd41fa1c7d4aaaedcc"><td class="memItemLeft" align="right" valign="top"><a id="a67930502b6d950cd41fa1c7d4aaaedcc"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA16C_SERCOM1_PAD0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 16)</td></tr>
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||
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<tr class="separator:a67930502b6d950cd41fa1c7d4aaaedcc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:addd37b78a4a3156ed361f5ac6f7d3d1c"><td class="memItemLeft" align="right" valign="top"><a id="addd37b78a4a3156ed361f5ac6f7d3d1c"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#addd37b78a4a3156ed361f5ac6f7d3d1c">PIN_PC27C_SERCOM1_PAD0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(91)</td></tr>
|
||
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<tr class="memdesc:addd37b78a4a3156ed361f5ac6f7d3d1c"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM1 signal: PAD0 on PC27 mux C. <br /></td></tr>
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<tr class="separator:addd37b78a4a3156ed361f5ac6f7d3d1c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a45262da6a0843811201aade53cda90d8"><td class="memItemLeft" align="right" valign="top"><a id="a45262da6a0843811201aade53cda90d8"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC27C_SERCOM1_PAD0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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||
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<tr class="separator:a45262da6a0843811201aade53cda90d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abe5d48387b21c94c815fb473da04d46f"><td class="memItemLeft" align="right" valign="top"><a id="abe5d48387b21c94c815fb473da04d46f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC27C_SERCOM1_PAD0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#addd37b78a4a3156ed361f5ac6f7d3d1c">PIN_PC27C_SERCOM1_PAD0</a> << 16) | MUX_PC27C_SERCOM1_PAD0)</td></tr>
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<tr class="separator:abe5d48387b21c94c815fb473da04d46f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1572b560be4fdd0131ae85a754f77f18"><td class="memItemLeft" align="right" valign="top"><a id="a1572b560be4fdd0131ae85a754f77f18"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC27C_SERCOM1_PAD0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 27)</td></tr>
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||
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<tr class="separator:a1572b560be4fdd0131ae85a754f77f18"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aea8ebe3945e66f4e86d3ef17c82d1035"><td class="memItemLeft" align="right" valign="top"><a id="aea8ebe3945e66f4e86d3ef17c82d1035"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aea8ebe3945e66f4e86d3ef17c82d1035">PIN_PA01D_SERCOM1_PAD1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
|
||
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<tr class="memdesc:aea8ebe3945e66f4e86d3ef17c82d1035"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM1 signal: PAD1 on PA01 mux D. <br /></td></tr>
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||
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<tr class="separator:aea8ebe3945e66f4e86d3ef17c82d1035"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aaab5aa3d802fead33c148cb0755b7ccd"><td class="memItemLeft" align="right" valign="top"><a id="aaab5aa3d802fead33c148cb0755b7ccd"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA01D_SERCOM1_PAD1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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||
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<tr class="separator:aaab5aa3d802fead33c148cb0755b7ccd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a893a5226dae319bea9e02362ad9bbcfd"><td class="memItemLeft" align="right" valign="top"><a id="a893a5226dae319bea9e02362ad9bbcfd"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA01D_SERCOM1_PAD1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aea8ebe3945e66f4e86d3ef17c82d1035">PIN_PA01D_SERCOM1_PAD1</a> << 16) | MUX_PA01D_SERCOM1_PAD1)</td></tr>
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<tr class="separator:a893a5226dae319bea9e02362ad9bbcfd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad10da938b5023f54df5a6f9f7dc26897"><td class="memItemLeft" align="right" valign="top"><a id="ad10da938b5023f54df5a6f9f7dc26897"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA01D_SERCOM1_PAD1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 1)</td></tr>
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||
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<tr class="separator:ad10da938b5023f54df5a6f9f7dc26897"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:ab5870755f6280141bd85ff709b97c71b"><td class="memItemLeft" align="right" valign="top"><a id="ab5870755f6280141bd85ff709b97c71b"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab5870755f6280141bd85ff709b97c71b">PIN_PA17C_SERCOM1_PAD1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(17)</td></tr>
|
||
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<tr class="memdesc:ab5870755f6280141bd85ff709b97c71b"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM1 signal: PAD1 on PA17 mux C. <br /></td></tr>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA17C_SERCOM1_PAD1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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<tr class="memitem:afb9b85de68d63dec32ee0caeb2bf826b"><td class="memItemLeft" align="right" valign="top"><a id="afb9b85de68d63dec32ee0caeb2bf826b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA17C_SERCOM1_PAD1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ab5870755f6280141bd85ff709b97c71b">PIN_PA17C_SERCOM1_PAD1</a> << 16) | MUX_PA17C_SERCOM1_PAD1)</td></tr>
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<tr class="memitem:a2bdfbd6da5f26cc5f81922680d932b68"><td class="memItemLeft" align="right" valign="top"><a id="a2bdfbd6da5f26cc5f81922680d932b68"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA17C_SERCOM1_PAD1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 17)</td></tr>
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<tr class="separator:a2bdfbd6da5f26cc5f81922680d932b68"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae6cc937345ff396800352e1403b3df6e"><td class="memItemLeft" align="right" valign="top"><a id="ae6cc937345ff396800352e1403b3df6e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae6cc937345ff396800352e1403b3df6e">PIN_PC28C_SERCOM1_PAD1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(92)</td></tr>
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<tr class="memdesc:ae6cc937345ff396800352e1403b3df6e"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM1 signal: PAD1 on PC28 mux C. <br /></td></tr>
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<tr class="separator:ae6cc937345ff396800352e1403b3df6e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab0264b53c2048a726943e7175a6d510e"><td class="memItemLeft" align="right" valign="top"><a id="ab0264b53c2048a726943e7175a6d510e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC28C_SERCOM1_PAD1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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<tr class="separator:ab0264b53c2048a726943e7175a6d510e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4e8d6a8a98281177d615e2d808a5358c"><td class="memItemLeft" align="right" valign="top"><a id="a4e8d6a8a98281177d615e2d808a5358c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC28C_SERCOM1_PAD1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ae6cc937345ff396800352e1403b3df6e">PIN_PC28C_SERCOM1_PAD1</a> << 16) | MUX_PC28C_SERCOM1_PAD1)</td></tr>
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<tr class="separator:a4e8d6a8a98281177d615e2d808a5358c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4e0c90e9fb48e77554d1b835253027c8"><td class="memItemLeft" align="right" valign="top"><a id="a4e0c90e9fb48e77554d1b835253027c8"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC28C_SERCOM1_PAD1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 28)</td></tr>
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<tr class="separator:a4e0c90e9fb48e77554d1b835253027c8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a174823ce52f5a2bd5c316b7a8bddf1f8"><td class="memItemLeft" align="right" valign="top"><a id="a174823ce52f5a2bd5c316b7a8bddf1f8"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a174823ce52f5a2bd5c316b7a8bddf1f8">PIN_PA30D_SERCOM1_PAD2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(30)</td></tr>
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||
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<tr class="memdesc:a174823ce52f5a2bd5c316b7a8bddf1f8"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM1 signal: PAD2 on PA30 mux D. <br /></td></tr>
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<tr class="separator:a174823ce52f5a2bd5c316b7a8bddf1f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa7c7d89ac4f6fdb1169bf39d3ab32525"><td class="memItemLeft" align="right" valign="top"><a id="aa7c7d89ac4f6fdb1169bf39d3ab32525"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA30D_SERCOM1_PAD2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="separator:aa7c7d89ac4f6fdb1169bf39d3ab32525"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7f11e86320d09560f7e755cb30f723ae"><td class="memItemLeft" align="right" valign="top"><a id="a7f11e86320d09560f7e755cb30f723ae"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA30D_SERCOM1_PAD2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a174823ce52f5a2bd5c316b7a8bddf1f8">PIN_PA30D_SERCOM1_PAD2</a> << 16) | MUX_PA30D_SERCOM1_PAD2)</td></tr>
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<tr class="separator:a7f11e86320d09560f7e755cb30f723ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2eedb76a3713ae52880c04ee5d383be7"><td class="memItemLeft" align="right" valign="top"><a id="a2eedb76a3713ae52880c04ee5d383be7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA30D_SERCOM1_PAD2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 30)</td></tr>
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<tr class="separator:a2eedb76a3713ae52880c04ee5d383be7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3288224f49ad40a523bb06d304fb139d"><td class="memItemLeft" align="right" valign="top"><a id="a3288224f49ad40a523bb06d304fb139d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3288224f49ad40a523bb06d304fb139d">PIN_PA18C_SERCOM1_PAD2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(18)</td></tr>
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||
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<tr class="memdesc:a3288224f49ad40a523bb06d304fb139d"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM1 signal: PAD2 on PA18 mux C. <br /></td></tr>
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<tr class="separator:a3288224f49ad40a523bb06d304fb139d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab08ad5711c6fcc0a47334407f626a877"><td class="memItemLeft" align="right" valign="top"><a id="ab08ad5711c6fcc0a47334407f626a877"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA18C_SERCOM1_PAD2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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<tr class="separator:ab08ad5711c6fcc0a47334407f626a877"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a84a8bfa73b3db83978c6fcd7d3ed214d"><td class="memItemLeft" align="right" valign="top"><a id="a84a8bfa73b3db83978c6fcd7d3ed214d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA18C_SERCOM1_PAD2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a3288224f49ad40a523bb06d304fb139d">PIN_PA18C_SERCOM1_PAD2</a> << 16) | MUX_PA18C_SERCOM1_PAD2)</td></tr>
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<tr class="separator:a84a8bfa73b3db83978c6fcd7d3ed214d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abecbb8b55e2b66dc34b3e9c7a1a78044"><td class="memItemLeft" align="right" valign="top"><a id="abecbb8b55e2b66dc34b3e9c7a1a78044"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA18C_SERCOM1_PAD2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 18)</td></tr>
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<tr class="separator:abecbb8b55e2b66dc34b3e9c7a1a78044"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a876739751d00a5e098bc52d03378669a"><td class="memItemLeft" align="right" valign="top"><a id="a876739751d00a5e098bc52d03378669a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a876739751d00a5e098bc52d03378669a">PIN_PB22C_SERCOM1_PAD2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(54)</td></tr>
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||
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<tr class="memdesc:a876739751d00a5e098bc52d03378669a"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM1 signal: PAD2 on PB22 mux C. <br /></td></tr>
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<tr class="separator:a876739751d00a5e098bc52d03378669a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa72001886eef38d3fe33429e93857f94"><td class="memItemLeft" align="right" valign="top"><a id="aa72001886eef38d3fe33429e93857f94"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB22C_SERCOM1_PAD2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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<tr class="separator:aa72001886eef38d3fe33429e93857f94"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a07c1838cd435d279865942d3f7691a55"><td class="memItemLeft" align="right" valign="top"><a id="a07c1838cd435d279865942d3f7691a55"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB22C_SERCOM1_PAD2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a876739751d00a5e098bc52d03378669a">PIN_PB22C_SERCOM1_PAD2</a> << 16) | MUX_PB22C_SERCOM1_PAD2)</td></tr>
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<tr class="separator:a07c1838cd435d279865942d3f7691a55"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aed56c012755c4a18307f1123bf2c9a6d"><td class="memItemLeft" align="right" valign="top"><a id="aed56c012755c4a18307f1123bf2c9a6d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB22C_SERCOM1_PAD2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 22)</td></tr>
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<tr class="separator:aed56c012755c4a18307f1123bf2c9a6d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa462211d59fefd3ceccb2f5ce40d800b"><td class="memItemLeft" align="right" valign="top"><a id="aa462211d59fefd3ceccb2f5ce40d800b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa462211d59fefd3ceccb2f5ce40d800b">PIN_PA31D_SERCOM1_PAD3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(31)</td></tr>
|
||
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<tr class="memdesc:aa462211d59fefd3ceccb2f5ce40d800b"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM1 signal: PAD3 on PA31 mux D. <br /></td></tr>
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<tr class="separator:aa462211d59fefd3ceccb2f5ce40d800b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0f65750136310131acf9513b395323e7"><td class="memItemLeft" align="right" valign="top"><a id="a0f65750136310131acf9513b395323e7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA31D_SERCOM1_PAD3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="separator:a0f65750136310131acf9513b395323e7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a31d726c708adf48b36945c98abb20c3b"><td class="memItemLeft" align="right" valign="top"><a id="a31d726c708adf48b36945c98abb20c3b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA31D_SERCOM1_PAD3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aa462211d59fefd3ceccb2f5ce40d800b">PIN_PA31D_SERCOM1_PAD3</a> << 16) | MUX_PA31D_SERCOM1_PAD3)</td></tr>
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<tr class="separator:a31d726c708adf48b36945c98abb20c3b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4a662c00b054f5f315a14968b876ff5c"><td class="memItemLeft" align="right" valign="top"><a id="a4a662c00b054f5f315a14968b876ff5c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA31D_SERCOM1_PAD3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 31)</td></tr>
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||
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<tr class="separator:a4a662c00b054f5f315a14968b876ff5c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8605e46feb172377bc736e2c869009fe"><td class="memItemLeft" align="right" valign="top"><a id="a8605e46feb172377bc736e2c869009fe"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8605e46feb172377bc736e2c869009fe">PIN_PA19C_SERCOM1_PAD3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(19)</td></tr>
|
||
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<tr class="memdesc:a8605e46feb172377bc736e2c869009fe"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM1 signal: PAD3 on PA19 mux C. <br /></td></tr>
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<tr class="separator:a8605e46feb172377bc736e2c869009fe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afffa146931ef7264b84718543d086d22"><td class="memItemLeft" align="right" valign="top"><a id="afffa146931ef7264b84718543d086d22"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA19C_SERCOM1_PAD3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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<tr class="separator:afffa146931ef7264b84718543d086d22"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a22b3034c9e13388c4194905594c0b52a"><td class="memItemLeft" align="right" valign="top"><a id="a22b3034c9e13388c4194905594c0b52a"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA19C_SERCOM1_PAD3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a8605e46feb172377bc736e2c869009fe">PIN_PA19C_SERCOM1_PAD3</a> << 16) | MUX_PA19C_SERCOM1_PAD3)</td></tr>
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<tr class="separator:a22b3034c9e13388c4194905594c0b52a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac7c5cbaf07d7659e78a060b17696a367"><td class="memItemLeft" align="right" valign="top"><a id="ac7c5cbaf07d7659e78a060b17696a367"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA19C_SERCOM1_PAD3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 19)</td></tr>
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||
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<tr class="separator:ac7c5cbaf07d7659e78a060b17696a367"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae12453a3e26c6af1bfbdfda91112470c"><td class="memItemLeft" align="right" valign="top"><a id="ae12453a3e26c6af1bfbdfda91112470c"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae12453a3e26c6af1bfbdfda91112470c">PIN_PB23C_SERCOM1_PAD3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(55)</td></tr>
|
||
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<tr class="memdesc:ae12453a3e26c6af1bfbdfda91112470c"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM1 signal: PAD3 on PB23 mux C. <br /></td></tr>
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<tr class="separator:ae12453a3e26c6af1bfbdfda91112470c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a902b145e7edee63750e20927837faff6"><td class="memItemLeft" align="right" valign="top"><a id="a902b145e7edee63750e20927837faff6"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB23C_SERCOM1_PAD3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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<tr class="memitem:a48e1365e4b4bd35538dea543c93589c1"><td class="memItemLeft" align="right" valign="top"><a id="a48e1365e4b4bd35538dea543c93589c1"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB23C_SERCOM1_PAD3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ae12453a3e26c6af1bfbdfda91112470c">PIN_PB23C_SERCOM1_PAD3</a> << 16) | MUX_PB23C_SERCOM1_PAD3)</td></tr>
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<tr class="separator:a48e1365e4b4bd35538dea543c93589c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac7f23b5282175966f9abb25477498a3f"><td class="memItemLeft" align="right" valign="top"><a id="ac7f23b5282175966f9abb25477498a3f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB23C_SERCOM1_PAD3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 23)</td></tr>
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<tr class="separator:ac7f23b5282175966f9abb25477498a3f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a96cb98a981bc9c4f238d9a9f03fddc02"><td class="memItemLeft" align="right" valign="top"><a id="a96cb98a981bc9c4f238d9a9f03fddc02"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a96cb98a981bc9c4f238d9a9f03fddc02">PIN_PA04E_TC0_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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<tr class="memdesc:a96cb98a981bc9c4f238d9a9f03fddc02"><td class="mdescLeft"> </td><td class="mdescRight">TC0 signal: WO0 on PA04 mux E. <br /></td></tr>
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<tr class="separator:a96cb98a981bc9c4f238d9a9f03fddc02"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab06410dbf303f42809f438e7561863be"><td class="memItemLeft" align="right" valign="top"><a id="ab06410dbf303f42809f438e7561863be"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA04E_TC0_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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<tr class="separator:ab06410dbf303f42809f438e7561863be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aedb4670a64b467b83ebbd7e37833cc0e"><td class="memItemLeft" align="right" valign="top"><a id="aedb4670a64b467b83ebbd7e37833cc0e"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA04E_TC0_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a96cb98a981bc9c4f238d9a9f03fddc02">PIN_PA04E_TC0_WO0</a> << 16) | MUX_PA04E_TC0_WO0)</td></tr>
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<tr class="separator:aedb4670a64b467b83ebbd7e37833cc0e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5e679e8b3a3685e6f1866e8fd685715c"><td class="memItemLeft" align="right" valign="top"><a id="a5e679e8b3a3685e6f1866e8fd685715c"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA04E_TC0_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 4)</td></tr>
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||
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<tr class="separator:a5e679e8b3a3685e6f1866e8fd685715c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a49ff4304622eae5e2c1b0480a9bd0fd1"><td class="memItemLeft" align="right" valign="top"><a id="a49ff4304622eae5e2c1b0480a9bd0fd1"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a49ff4304622eae5e2c1b0480a9bd0fd1">PIN_PA08E_TC0_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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||
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<tr class="memdesc:a49ff4304622eae5e2c1b0480a9bd0fd1"><td class="mdescLeft"> </td><td class="mdescRight">TC0 signal: WO0 on PA08 mux E. <br /></td></tr>
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<tr class="separator:a49ff4304622eae5e2c1b0480a9bd0fd1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab945a4f99dd09424ff4acaad9e536197"><td class="memItemLeft" align="right" valign="top"><a id="ab945a4f99dd09424ff4acaad9e536197"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA08E_TC0_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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||
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<tr class="separator:ab945a4f99dd09424ff4acaad9e536197"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad7bd0e7894e7bba0137e507ca60e6e98"><td class="memItemLeft" align="right" valign="top"><a id="ad7bd0e7894e7bba0137e507ca60e6e98"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA08E_TC0_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a49ff4304622eae5e2c1b0480a9bd0fd1">PIN_PA08E_TC0_WO0</a> << 16) | MUX_PA08E_TC0_WO0)</td></tr>
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<tr class="separator:ad7bd0e7894e7bba0137e507ca60e6e98"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a114c0bf64d40b428a1f401ae3e956678"><td class="memItemLeft" align="right" valign="top"><a id="a114c0bf64d40b428a1f401ae3e956678"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA08E_TC0_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 8)</td></tr>
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||
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<tr class="separator:a114c0bf64d40b428a1f401ae3e956678"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:addd26211e641ab0933399ed1b89fb2fd"><td class="memItemLeft" align="right" valign="top"><a id="addd26211e641ab0933399ed1b89fb2fd"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#addd26211e641ab0933399ed1b89fb2fd">PIN_PB30E_TC0_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(62)</td></tr>
|
||
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<tr class="memdesc:addd26211e641ab0933399ed1b89fb2fd"><td class="mdescLeft"> </td><td class="mdescRight">TC0 signal: WO0 on PB30 mux E. <br /></td></tr>
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<tr class="separator:addd26211e641ab0933399ed1b89fb2fd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae3a8bc470bdef3afe2d25d2e434effef"><td class="memItemLeft" align="right" valign="top"><a id="ae3a8bc470bdef3afe2d25d2e434effef"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB30E_TC0_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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||
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<tr class="separator:ae3a8bc470bdef3afe2d25d2e434effef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af8acd4b4861e080c99ae09f26c66881d"><td class="memItemLeft" align="right" valign="top"><a id="af8acd4b4861e080c99ae09f26c66881d"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB30E_TC0_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#addd26211e641ab0933399ed1b89fb2fd">PIN_PB30E_TC0_WO0</a> << 16) | MUX_PB30E_TC0_WO0)</td></tr>
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<tr class="separator:af8acd4b4861e080c99ae09f26c66881d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a01261568a599b529a67e59e3bc60461f"><td class="memItemLeft" align="right" valign="top"><a id="a01261568a599b529a67e59e3bc60461f"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB30E_TC0_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 30)</td></tr>
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||
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<tr class="separator:a01261568a599b529a67e59e3bc60461f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a690d541b2f41b5cd008524c402a3ba07"><td class="memItemLeft" align="right" valign="top"><a id="a690d541b2f41b5cd008524c402a3ba07"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a690d541b2f41b5cd008524c402a3ba07">PIN_PA05E_TC0_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
|
||
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<tr class="memdesc:a690d541b2f41b5cd008524c402a3ba07"><td class="mdescLeft"> </td><td class="mdescRight">TC0 signal: WO1 on PA05 mux E. <br /></td></tr>
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<tr class="separator:a690d541b2f41b5cd008524c402a3ba07"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae12b49176cb6198b6f20587f003b3367"><td class="memItemLeft" align="right" valign="top"><a id="ae12b49176cb6198b6f20587f003b3367"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA05E_TC0_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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||
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<tr class="separator:ae12b49176cb6198b6f20587f003b3367"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:af28e2d362305005dd31c6f3aac23fef0"><td class="memItemLeft" align="right" valign="top"><a id="af28e2d362305005dd31c6f3aac23fef0"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA05E_TC0_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a690d541b2f41b5cd008524c402a3ba07">PIN_PA05E_TC0_WO1</a> << 16) | MUX_PA05E_TC0_WO1)</td></tr>
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<tr class="separator:af28e2d362305005dd31c6f3aac23fef0"><td class="memSeparator" colspan="2"> </td></tr>
|
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<tr class="memitem:a7762cbfb518939e43fff62125bc13fe1"><td class="memItemLeft" align="right" valign="top"><a id="a7762cbfb518939e43fff62125bc13fe1"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA05E_TC0_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 5)</td></tr>
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||
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<tr class="separator:a7762cbfb518939e43fff62125bc13fe1"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a7efda3b84fd3ef46234de7e3f0ae867d"><td class="memItemLeft" align="right" valign="top"><a id="a7efda3b84fd3ef46234de7e3f0ae867d"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7efda3b84fd3ef46234de7e3f0ae867d">PIN_PA09E_TC0_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
|
||
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<tr class="memdesc:a7efda3b84fd3ef46234de7e3f0ae867d"><td class="mdescLeft"> </td><td class="mdescRight">TC0 signal: WO1 on PA09 mux E. <br /></td></tr>
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<tr class="separator:a7efda3b84fd3ef46234de7e3f0ae867d"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a5913e433b4a3d5c7d9b16b8f45396e89"><td class="memItemLeft" align="right" valign="top"><a id="a5913e433b4a3d5c7d9b16b8f45396e89"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA09E_TC0_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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||
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<tr class="separator:a5913e433b4a3d5c7d9b16b8f45396e89"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3347182d4f4085f5b1f7ffbb030c4a84"><td class="memItemLeft" align="right" valign="top"><a id="a3347182d4f4085f5b1f7ffbb030c4a84"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA09E_TC0_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a7efda3b84fd3ef46234de7e3f0ae867d">PIN_PA09E_TC0_WO1</a> << 16) | MUX_PA09E_TC0_WO1)</td></tr>
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||
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<tr class="separator:a3347182d4f4085f5b1f7ffbb030c4a84"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8ff325e0b4e748507895e1440eda1cbd"><td class="memItemLeft" align="right" valign="top"><a id="a8ff325e0b4e748507895e1440eda1cbd"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA09E_TC0_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 9)</td></tr>
|
||
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<tr class="separator:a8ff325e0b4e748507895e1440eda1cbd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5e4a347ac0c282ef3d940f5c18bd6fec"><td class="memItemLeft" align="right" valign="top"><a id="a5e4a347ac0c282ef3d940f5c18bd6fec"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5e4a347ac0c282ef3d940f5c18bd6fec">PIN_PB31E_TC0_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(63)</td></tr>
|
||
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<tr class="memdesc:a5e4a347ac0c282ef3d940f5c18bd6fec"><td class="mdescLeft"> </td><td class="mdescRight">TC0 signal: WO1 on PB31 mux E. <br /></td></tr>
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<tr class="separator:a5e4a347ac0c282ef3d940f5c18bd6fec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae2183437ade7baf4a0d416635cd63201"><td class="memItemLeft" align="right" valign="top"><a id="ae2183437ade7baf4a0d416635cd63201"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB31E_TC0_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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||
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<tr class="separator:ae2183437ade7baf4a0d416635cd63201"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7df2f73db2e5bb6319ec0f3f56ccc823"><td class="memItemLeft" align="right" valign="top"><a id="a7df2f73db2e5bb6319ec0f3f56ccc823"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB31E_TC0_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a5e4a347ac0c282ef3d940f5c18bd6fec">PIN_PB31E_TC0_WO1</a> << 16) | MUX_PB31E_TC0_WO1)</td></tr>
|
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<tr class="separator:a7df2f73db2e5bb6319ec0f3f56ccc823"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2ac61dd8c6fd357d738dce036ef50a1f"><td class="memItemLeft" align="right" valign="top"><a id="a2ac61dd8c6fd357d738dce036ef50a1f"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB31E_TC0_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 31)</td></tr>
|
||
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<tr class="separator:a2ac61dd8c6fd357d738dce036ef50a1f"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a0b1a620114f9f8556b888ef1b4b44589"><td class="memItemLeft" align="right" valign="top"><a id="a0b1a620114f9f8556b888ef1b4b44589"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0b1a620114f9f8556b888ef1b4b44589">PIN_PA06E_TC1_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
|
||
|
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<tr class="memdesc:a0b1a620114f9f8556b888ef1b4b44589"><td class="mdescLeft"> </td><td class="mdescRight">TC1 signal: WO0 on PA06 mux E. <br /></td></tr>
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<tr class="separator:a0b1a620114f9f8556b888ef1b4b44589"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a92f16ea653186c2dbb26273cbcfcac3f"><td class="memItemLeft" align="right" valign="top"><a id="a92f16ea653186c2dbb26273cbcfcac3f"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA06E_TC1_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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||
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<tr class="separator:a92f16ea653186c2dbb26273cbcfcac3f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a23377b96307d89f24d5f1a1fa3e32606"><td class="memItemLeft" align="right" valign="top"><a id="a23377b96307d89f24d5f1a1fa3e32606"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA06E_TC1_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a0b1a620114f9f8556b888ef1b4b44589">PIN_PA06E_TC1_WO0</a> << 16) | MUX_PA06E_TC1_WO0)</td></tr>
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||
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<tr class="memitem:ac2c6ef7f12637bae79e48338a7ef3534"><td class="memItemLeft" align="right" valign="top"><a id="ac2c6ef7f12637bae79e48338a7ef3534"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA06E_TC1_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 6)</td></tr>
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<tr class="separator:ac2c6ef7f12637bae79e48338a7ef3534"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a769ef151929a870e73e8d41f6a241768"><td class="memItemLeft" align="right" valign="top"><a id="a769ef151929a870e73e8d41f6a241768"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a769ef151929a870e73e8d41f6a241768">PIN_PA10E_TC1_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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<tr class="memdesc:a769ef151929a870e73e8d41f6a241768"><td class="mdescLeft"> </td><td class="mdescRight">TC1 signal: WO0 on PA10 mux E. <br /></td></tr>
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<tr class="separator:a769ef151929a870e73e8d41f6a241768"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a439b3932488f18b4228750611febd2e3"><td class="memItemLeft" align="right" valign="top"><a id="a439b3932488f18b4228750611febd2e3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA10E_TC1_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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<tr class="separator:a439b3932488f18b4228750611febd2e3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aee05dd23ad4b12a6d9b53332c950c7fc"><td class="memItemLeft" align="right" valign="top"><a id="aee05dd23ad4b12a6d9b53332c950c7fc"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA10E_TC1_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a769ef151929a870e73e8d41f6a241768">PIN_PA10E_TC1_WO0</a> << 16) | MUX_PA10E_TC1_WO0)</td></tr>
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<tr class="separator:aee05dd23ad4b12a6d9b53332c950c7fc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6da8b47871dce846ce1e4fb1ee83356b"><td class="memItemLeft" align="right" valign="top"><a id="a6da8b47871dce846ce1e4fb1ee83356b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA10E_TC1_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 10)</td></tr>
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<tr class="separator:a6da8b47871dce846ce1e4fb1ee83356b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abc7767be99b0228b55d59c09ad446b8a"><td class="memItemLeft" align="right" valign="top"><a id="abc7767be99b0228b55d59c09ad446b8a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#abc7767be99b0228b55d59c09ad446b8a">PIN_PA07E_TC1_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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<tr class="memdesc:abc7767be99b0228b55d59c09ad446b8a"><td class="mdescLeft"> </td><td class="mdescRight">TC1 signal: WO1 on PA07 mux E. <br /></td></tr>
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<tr class="separator:abc7767be99b0228b55d59c09ad446b8a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7acfa48a234cf53696b2980257c71567"><td class="memItemLeft" align="right" valign="top"><a id="a7acfa48a234cf53696b2980257c71567"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA07E_TC1_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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<tr class="separator:a7acfa48a234cf53696b2980257c71567"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a596bc9bca8b0f3990acbc96a009fe9c5"><td class="memItemLeft" align="right" valign="top"><a id="a596bc9bca8b0f3990acbc96a009fe9c5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA07E_TC1_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#abc7767be99b0228b55d59c09ad446b8a">PIN_PA07E_TC1_WO1</a> << 16) | MUX_PA07E_TC1_WO1)</td></tr>
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<tr class="separator:a596bc9bca8b0f3990acbc96a009fe9c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a300dd29fde63794766ab0fda2807a2e1"><td class="memItemLeft" align="right" valign="top"><a id="a300dd29fde63794766ab0fda2807a2e1"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA07E_TC1_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 7)</td></tr>
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<tr class="separator:a300dd29fde63794766ab0fda2807a2e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2b4d6bddd8eba6f8cc18c90f4993f581"><td class="memItemLeft" align="right" valign="top"><a id="a2b4d6bddd8eba6f8cc18c90f4993f581"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2b4d6bddd8eba6f8cc18c90f4993f581">PIN_PA11E_TC1_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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||
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<tr class="memdesc:a2b4d6bddd8eba6f8cc18c90f4993f581"><td class="mdescLeft"> </td><td class="mdescRight">TC1 signal: WO1 on PA11 mux E. <br /></td></tr>
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<tr class="separator:a2b4d6bddd8eba6f8cc18c90f4993f581"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5855032247b89c3e5bd22efbb18cd280"><td class="memItemLeft" align="right" valign="top"><a id="a5855032247b89c3e5bd22efbb18cd280"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA11E_TC1_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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<tr class="separator:a5855032247b89c3e5bd22efbb18cd280"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab44522c2d807c9dfcf2a98a90c973434"><td class="memItemLeft" align="right" valign="top"><a id="ab44522c2d807c9dfcf2a98a90c973434"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA11E_TC1_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a2b4d6bddd8eba6f8cc18c90f4993f581">PIN_PA11E_TC1_WO1</a> << 16) | MUX_PA11E_TC1_WO1)</td></tr>
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<tr class="separator:ab44522c2d807c9dfcf2a98a90c973434"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acabc853fad03ec2d8104039aae8603fc"><td class="memItemLeft" align="right" valign="top"><a id="acabc853fad03ec2d8104039aae8603fc"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA11E_TC1_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 11)</td></tr>
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<tr class="separator:acabc853fad03ec2d8104039aae8603fc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0b8e7ed3fcaff1e2b5ade0945d8a7eb0"><td class="memItemLeft" align="right" valign="top"><a id="a0b8e7ed3fcaff1e2b5ade0945d8a7eb0"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0b8e7ed3fcaff1e2b5ade0945d8a7eb0">PIN_PA24H_USB_DM</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(24)</td></tr>
|
||
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<tr class="memdesc:a0b8e7ed3fcaff1e2b5ade0945d8a7eb0"><td class="mdescLeft"> </td><td class="mdescRight">USB signal: DM on PA24 mux H. <br /></td></tr>
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<tr class="separator:a0b8e7ed3fcaff1e2b5ade0945d8a7eb0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af91654d9184fbfe08ece8f5b32e5fb36"><td class="memItemLeft" align="right" valign="top"><a id="af91654d9184fbfe08ece8f5b32e5fb36"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA24H_USB_DM</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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<tr class="separator:af91654d9184fbfe08ece8f5b32e5fb36"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa80f1176cb62c61457884d1afc794828"><td class="memItemLeft" align="right" valign="top"><a id="aa80f1176cb62c61457884d1afc794828"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA24H_USB_DM</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a0b8e7ed3fcaff1e2b5ade0945d8a7eb0">PIN_PA24H_USB_DM</a> << 16) | MUX_PA24H_USB_DM)</td></tr>
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<tr class="separator:aa80f1176cb62c61457884d1afc794828"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae987919cc9e6dbf11c52c811f15a5be5"><td class="memItemLeft" align="right" valign="top"><a id="ae987919cc9e6dbf11c52c811f15a5be5"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA24H_USB_DM</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 24)</td></tr>
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||
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<tr class="separator:ae987919cc9e6dbf11c52c811f15a5be5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afeea74fc39b7f158ef211aa25cedee4c"><td class="memItemLeft" align="right" valign="top"><a id="afeea74fc39b7f158ef211aa25cedee4c"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#afeea74fc39b7f158ef211aa25cedee4c">PIN_PA25H_USB_DP</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(25)</td></tr>
|
||
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<tr class="memdesc:afeea74fc39b7f158ef211aa25cedee4c"><td class="mdescLeft"> </td><td class="mdescRight">USB signal: DP on PA25 mux H. <br /></td></tr>
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<tr class="separator:afeea74fc39b7f158ef211aa25cedee4c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad39274658aec1a5c801cf7676768023d"><td class="memItemLeft" align="right" valign="top"><a id="ad39274658aec1a5c801cf7676768023d"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA25H_USB_DP</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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<tr class="separator:ad39274658aec1a5c801cf7676768023d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abf0c2c1f8402f6d5631e8852244a2d28"><td class="memItemLeft" align="right" valign="top"><a id="abf0c2c1f8402f6d5631e8852244a2d28"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA25H_USB_DP</b>   ((<a class="el" href="pio_2same54p20a_8h.html#afeea74fc39b7f158ef211aa25cedee4c">PIN_PA25H_USB_DP</a> << 16) | MUX_PA25H_USB_DP)</td></tr>
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<tr class="separator:abf0c2c1f8402f6d5631e8852244a2d28"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7f71c3693a091af45624cd6e1bd40f0a"><td class="memItemLeft" align="right" valign="top"><a id="a7f71c3693a091af45624cd6e1bd40f0a"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA25H_USB_DP</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 25)</td></tr>
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<tr class="separator:a7f71c3693a091af45624cd6e1bd40f0a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4d9b36157980753639c3a13102d315d3"><td class="memItemLeft" align="right" valign="top"><a id="a4d9b36157980753639c3a13102d315d3"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4d9b36157980753639c3a13102d315d3">PIN_PA23H_USB_SOF_1KHZ</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(23)</td></tr>
|
||
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<tr class="memdesc:a4d9b36157980753639c3a13102d315d3"><td class="mdescLeft"> </td><td class="mdescRight">USB signal: SOF_1KHZ on PA23 mux H. <br /></td></tr>
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<tr class="separator:a4d9b36157980753639c3a13102d315d3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a48d5faef0d319842a436033e6aa9449c"><td class="memItemLeft" align="right" valign="top"><a id="a48d5faef0d319842a436033e6aa9449c"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA23H_USB_SOF_1KHZ</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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||
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<tr class="separator:a48d5faef0d319842a436033e6aa9449c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab1d128b719e378fba94a57283458bc13"><td class="memItemLeft" align="right" valign="top"><a id="ab1d128b719e378fba94a57283458bc13"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA23H_USB_SOF_1KHZ</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a4d9b36157980753639c3a13102d315d3">PIN_PA23H_USB_SOF_1KHZ</a> << 16) | MUX_PA23H_USB_SOF_1KHZ)</td></tr>
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<tr class="separator:ab1d128b719e378fba94a57283458bc13"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a41b9898f71a78ffbfc77aa7e2d39071a"><td class="memItemLeft" align="right" valign="top"><a id="a41b9898f71a78ffbfc77aa7e2d39071a"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA23H_USB_SOF_1KHZ</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 23)</td></tr>
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||
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<tr class="separator:a41b9898f71a78ffbfc77aa7e2d39071a"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:aaa6e047e0d2ef0f90256ce2e4a7e6265"><td class="memItemLeft" align="right" valign="top"><a id="aaa6e047e0d2ef0f90256ce2e4a7e6265"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aaa6e047e0d2ef0f90256ce2e4a7e6265">PIN_PB22H_USB_SOF_1KHZ</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(54)</td></tr>
|
||
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<tr class="memdesc:aaa6e047e0d2ef0f90256ce2e4a7e6265"><td class="mdescLeft"> </td><td class="mdescRight">USB signal: SOF_1KHZ on PB22 mux H. <br /></td></tr>
|
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<tr class="separator:aaa6e047e0d2ef0f90256ce2e4a7e6265"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a72950f1a9375737b904ec6655c7bd402"><td class="memItemLeft" align="right" valign="top"><a id="a72950f1a9375737b904ec6655c7bd402"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB22H_USB_SOF_1KHZ</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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||
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<tr class="separator:a72950f1a9375737b904ec6655c7bd402"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad84669e91d3951875650b973d2d14b68"><td class="memItemLeft" align="right" valign="top"><a id="ad84669e91d3951875650b973d2d14b68"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB22H_USB_SOF_1KHZ</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aaa6e047e0d2ef0f90256ce2e4a7e6265">PIN_PB22H_USB_SOF_1KHZ</a> << 16) | MUX_PB22H_USB_SOF_1KHZ)</td></tr>
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<tr class="separator:ad84669e91d3951875650b973d2d14b68"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a03186b103bcae9c183614b67919a4ddd"><td class="memItemLeft" align="right" valign="top"><a id="a03186b103bcae9c183614b67919a4ddd"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB22H_USB_SOF_1KHZ</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 22)</td></tr>
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<tr class="separator:a03186b103bcae9c183614b67919a4ddd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac5de783a40bb1bca0e1f78da985977d2"><td class="memItemLeft" align="right" valign="top"><a id="ac5de783a40bb1bca0e1f78da985977d2"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac5de783a40bb1bca0e1f78da985977d2">PIN_PA09D_SERCOM2_PAD0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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<tr class="memdesc:ac5de783a40bb1bca0e1f78da985977d2"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM2 signal: PAD0 on PA09 mux D. <br /></td></tr>
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<tr class="separator:ac5de783a40bb1bca0e1f78da985977d2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a45f5d775b65e12a263db90fb0b0b8996"><td class="memItemLeft" align="right" valign="top"><a id="a45f5d775b65e12a263db90fb0b0b8996"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA09D_SERCOM2_PAD0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="separator:a45f5d775b65e12a263db90fb0b0b8996"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1f7949eb21b60dabedb2cafe7d3a51e3"><td class="memItemLeft" align="right" valign="top"><a id="a1f7949eb21b60dabedb2cafe7d3a51e3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA09D_SERCOM2_PAD0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ac5de783a40bb1bca0e1f78da985977d2">PIN_PA09D_SERCOM2_PAD0</a> << 16) | MUX_PA09D_SERCOM2_PAD0)</td></tr>
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<tr class="separator:a1f7949eb21b60dabedb2cafe7d3a51e3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab682fdb4f8bb0d8cc9203b44e42bc295"><td class="memItemLeft" align="right" valign="top"><a id="ab682fdb4f8bb0d8cc9203b44e42bc295"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA09D_SERCOM2_PAD0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 9)</td></tr>
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<tr class="separator:ab682fdb4f8bb0d8cc9203b44e42bc295"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad9efbe6a006569dc39d2c545bea4b244"><td class="memItemLeft" align="right" valign="top"><a id="ad9efbe6a006569dc39d2c545bea4b244"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad9efbe6a006569dc39d2c545bea4b244">PIN_PB25D_SERCOM2_PAD0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(57)</td></tr>
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<tr class="memdesc:ad9efbe6a006569dc39d2c545bea4b244"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM2 signal: PAD0 on PB25 mux D. <br /></td></tr>
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<tr class="separator:ad9efbe6a006569dc39d2c545bea4b244"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab0ab2cfeb276b362a0410cdbc99b7838"><td class="memItemLeft" align="right" valign="top"><a id="ab0ab2cfeb276b362a0410cdbc99b7838"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB25D_SERCOM2_PAD0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="separator:ab0ab2cfeb276b362a0410cdbc99b7838"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a74ef1c9dd305592b287e97205326012f"><td class="memItemLeft" align="right" valign="top"><a id="a74ef1c9dd305592b287e97205326012f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB25D_SERCOM2_PAD0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ad9efbe6a006569dc39d2c545bea4b244">PIN_PB25D_SERCOM2_PAD0</a> << 16) | MUX_PB25D_SERCOM2_PAD0)</td></tr>
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<tr class="separator:a74ef1c9dd305592b287e97205326012f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1ff0d38a2fb1a70f75ddcc9070ca9896"><td class="memItemLeft" align="right" valign="top"><a id="a1ff0d38a2fb1a70f75ddcc9070ca9896"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB25D_SERCOM2_PAD0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 25)</td></tr>
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<tr class="separator:a1ff0d38a2fb1a70f75ddcc9070ca9896"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3d84d25427ce818aa6d829f84c947024"><td class="memItemLeft" align="right" valign="top"><a id="a3d84d25427ce818aa6d829f84c947024"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3d84d25427ce818aa6d829f84c947024">PIN_PA12C_SERCOM2_PAD0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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||
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<tr class="memdesc:a3d84d25427ce818aa6d829f84c947024"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM2 signal: PAD0 on PA12 mux C. <br /></td></tr>
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<tr class="separator:a3d84d25427ce818aa6d829f84c947024"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aac615bdb90cfc1525647b6a9df8efe99"><td class="memItemLeft" align="right" valign="top"><a id="aac615bdb90cfc1525647b6a9df8efe99"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA12C_SERCOM2_PAD0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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<tr class="separator:aac615bdb90cfc1525647b6a9df8efe99"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a71f172b8598e85a68acd33b15fab9748"><td class="memItemLeft" align="right" valign="top"><a id="a71f172b8598e85a68acd33b15fab9748"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA12C_SERCOM2_PAD0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a3d84d25427ce818aa6d829f84c947024">PIN_PA12C_SERCOM2_PAD0</a> << 16) | MUX_PA12C_SERCOM2_PAD0)</td></tr>
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<tr class="separator:a71f172b8598e85a68acd33b15fab9748"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a99c9c2cdd3c14337fe0a7fc0941dad9c"><td class="memItemLeft" align="right" valign="top"><a id="a99c9c2cdd3c14337fe0a7fc0941dad9c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA12C_SERCOM2_PAD0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 12)</td></tr>
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<tr class="separator:a99c9c2cdd3c14337fe0a7fc0941dad9c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6169a872ff65b63047f9b1fd6d7f0872"><td class="memItemLeft" align="right" valign="top"><a id="a6169a872ff65b63047f9b1fd6d7f0872"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6169a872ff65b63047f9b1fd6d7f0872">PIN_PA08D_SERCOM2_PAD1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
|
||
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<tr class="memdesc:a6169a872ff65b63047f9b1fd6d7f0872"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM2 signal: PAD1 on PA08 mux D. <br /></td></tr>
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<tr class="separator:a6169a872ff65b63047f9b1fd6d7f0872"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0b3f26733533af225b837bb685a89bfd"><td class="memItemLeft" align="right" valign="top"><a id="a0b3f26733533af225b837bb685a89bfd"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA08D_SERCOM2_PAD1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="separator:a0b3f26733533af225b837bb685a89bfd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad05e6313675a1d5577d49cd57f04c7d1"><td class="memItemLeft" align="right" valign="top"><a id="ad05e6313675a1d5577d49cd57f04c7d1"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA08D_SERCOM2_PAD1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a6169a872ff65b63047f9b1fd6d7f0872">PIN_PA08D_SERCOM2_PAD1</a> << 16) | MUX_PA08D_SERCOM2_PAD1)</td></tr>
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<tr class="separator:ad05e6313675a1d5577d49cd57f04c7d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acba1e31d16efbd8483711d60517ab304"><td class="memItemLeft" align="right" valign="top"><a id="acba1e31d16efbd8483711d60517ab304"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA08D_SERCOM2_PAD1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 8)</td></tr>
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<tr class="separator:acba1e31d16efbd8483711d60517ab304"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aace4ee51952113c11b2af1ed5299185e"><td class="memItemLeft" align="right" valign="top"><a id="aace4ee51952113c11b2af1ed5299185e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aace4ee51952113c11b2af1ed5299185e">PIN_PB24D_SERCOM2_PAD1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(56)</td></tr>
|
||
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<tr class="memdesc:aace4ee51952113c11b2af1ed5299185e"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM2 signal: PAD1 on PB24 mux D. <br /></td></tr>
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<tr class="separator:aace4ee51952113c11b2af1ed5299185e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a33c608dca623d7ed882ae243074b69ce"><td class="memItemLeft" align="right" valign="top"><a id="a33c608dca623d7ed882ae243074b69ce"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB24D_SERCOM2_PAD1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="separator:a33c608dca623d7ed882ae243074b69ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae40fe0629e7db88d6f8f1d10de051e03"><td class="memItemLeft" align="right" valign="top"><a id="ae40fe0629e7db88d6f8f1d10de051e03"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB24D_SERCOM2_PAD1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aace4ee51952113c11b2af1ed5299185e">PIN_PB24D_SERCOM2_PAD1</a> << 16) | MUX_PB24D_SERCOM2_PAD1)</td></tr>
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<tr class="separator:ae40fe0629e7db88d6f8f1d10de051e03"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a23f8e25e7eca86901af78336fa0d9b6b"><td class="memItemLeft" align="right" valign="top"><a id="a23f8e25e7eca86901af78336fa0d9b6b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB24D_SERCOM2_PAD1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 24)</td></tr>
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<tr class="separator:a23f8e25e7eca86901af78336fa0d9b6b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7db12df2b3d1bdd361857143b1bb54ba"><td class="memItemLeft" align="right" valign="top"><a id="a7db12df2b3d1bdd361857143b1bb54ba"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7db12df2b3d1bdd361857143b1bb54ba">PIN_PA13C_SERCOM2_PAD1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
|
||
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<tr class="memdesc:a7db12df2b3d1bdd361857143b1bb54ba"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM2 signal: PAD1 on PA13 mux C. <br /></td></tr>
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<tr class="separator:a7db12df2b3d1bdd361857143b1bb54ba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa213feab42d062631429b3dbeb459ac9"><td class="memItemLeft" align="right" valign="top"><a id="aa213feab42d062631429b3dbeb459ac9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA13C_SERCOM2_PAD1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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<tr class="separator:aa213feab42d062631429b3dbeb459ac9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:addc9bdbf1d8108413af750b7955c44bb"><td class="memItemLeft" align="right" valign="top"><a id="addc9bdbf1d8108413af750b7955c44bb"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA13C_SERCOM2_PAD1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a7db12df2b3d1bdd361857143b1bb54ba">PIN_PA13C_SERCOM2_PAD1</a> << 16) | MUX_PA13C_SERCOM2_PAD1)</td></tr>
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<tr class="separator:addc9bdbf1d8108413af750b7955c44bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a298bf7de26d81d07d3a0088c317273f1"><td class="memItemLeft" align="right" valign="top"><a id="a298bf7de26d81d07d3a0088c317273f1"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA13C_SERCOM2_PAD1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 13)</td></tr>
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<tr class="separator:a298bf7de26d81d07d3a0088c317273f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a074dbb37fca09ab1f66650959a41fd2c"><td class="memItemLeft" align="right" valign="top"><a id="a074dbb37fca09ab1f66650959a41fd2c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a074dbb37fca09ab1f66650959a41fd2c">PIN_PA10D_SERCOM2_PAD2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
|
||
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<tr class="memdesc:a074dbb37fca09ab1f66650959a41fd2c"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM2 signal: PAD2 on PA10 mux D. <br /></td></tr>
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<tr class="separator:a074dbb37fca09ab1f66650959a41fd2c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aef03ae6013d1c1b8dd30ea4476f414e6"><td class="memItemLeft" align="right" valign="top"><a id="aef03ae6013d1c1b8dd30ea4476f414e6"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA10D_SERCOM2_PAD2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="separator:aef03ae6013d1c1b8dd30ea4476f414e6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8b9e00361b08dde144aa6db249418760"><td class="memItemLeft" align="right" valign="top"><a id="a8b9e00361b08dde144aa6db249418760"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA10D_SERCOM2_PAD2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a074dbb37fca09ab1f66650959a41fd2c">PIN_PA10D_SERCOM2_PAD2</a> << 16) | MUX_PA10D_SERCOM2_PAD2)</td></tr>
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<tr class="separator:a8b9e00361b08dde144aa6db249418760"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1f8866ccec7fbc164f9db3e58a146674"><td class="memItemLeft" align="right" valign="top"><a id="a1f8866ccec7fbc164f9db3e58a146674"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA10D_SERCOM2_PAD2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 10)</td></tr>
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||
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<tr class="separator:a1f8866ccec7fbc164f9db3e58a146674"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2d3cc3363669ba47a8dafebe1e10ef61"><td class="memItemLeft" align="right" valign="top"><a id="a2d3cc3363669ba47a8dafebe1e10ef61"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2d3cc3363669ba47a8dafebe1e10ef61">PIN_PC24D_SERCOM2_PAD2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(88)</td></tr>
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||
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<tr class="memdesc:a2d3cc3363669ba47a8dafebe1e10ef61"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM2 signal: PAD2 on PC24 mux D. <br /></td></tr>
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<tr class="memitem:a3cf463a2a9755aae7b48fb9c7c8e7992"><td class="memItemLeft" align="right" valign="top"><a id="a3cf463a2a9755aae7b48fb9c7c8e7992"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC24D_SERCOM2_PAD2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="separator:a3cf463a2a9755aae7b48fb9c7c8e7992"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a758d310e851379991a9337ac0279021a"><td class="memItemLeft" align="right" valign="top"><a id="a758d310e851379991a9337ac0279021a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC24D_SERCOM2_PAD2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a2d3cc3363669ba47a8dafebe1e10ef61">PIN_PC24D_SERCOM2_PAD2</a> << 16) | MUX_PC24D_SERCOM2_PAD2)</td></tr>
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<tr class="memitem:af546035aa93c21355254a73cdb0c9c96"><td class="memItemLeft" align="right" valign="top"><a id="af546035aa93c21355254a73cdb0c9c96"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC24D_SERCOM2_PAD2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 24)</td></tr>
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<tr class="separator:af546035aa93c21355254a73cdb0c9c96"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac0e1daf7ba564bd868fdb4b53ada5751"><td class="memItemLeft" align="right" valign="top"><a id="ac0e1daf7ba564bd868fdb4b53ada5751"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac0e1daf7ba564bd868fdb4b53ada5751">PIN_PA14C_SERCOM2_PAD2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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<tr class="memdesc:ac0e1daf7ba564bd868fdb4b53ada5751"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM2 signal: PAD2 on PA14 mux C. <br /></td></tr>
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<tr class="separator:ac0e1daf7ba564bd868fdb4b53ada5751"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa0dd651d25075d3a82329f28ef8554a8"><td class="memItemLeft" align="right" valign="top"><a id="aa0dd651d25075d3a82329f28ef8554a8"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA14C_SERCOM2_PAD2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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<tr class="separator:aa0dd651d25075d3a82329f28ef8554a8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae08459e4fa34df183bac973b56e359f4"><td class="memItemLeft" align="right" valign="top"><a id="ae08459e4fa34df183bac973b56e359f4"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA14C_SERCOM2_PAD2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ac0e1daf7ba564bd868fdb4b53ada5751">PIN_PA14C_SERCOM2_PAD2</a> << 16) | MUX_PA14C_SERCOM2_PAD2)</td></tr>
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<tr class="memitem:ac59de336b6b5217ff41cfcc595ea2df9"><td class="memItemLeft" align="right" valign="top"><a id="ac59de336b6b5217ff41cfcc595ea2df9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA14C_SERCOM2_PAD2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 14)</td></tr>
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<tr class="separator:ac59de336b6b5217ff41cfcc595ea2df9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac266976ecf2df78224be648346faf789"><td class="memItemLeft" align="right" valign="top"><a id="ac266976ecf2df78224be648346faf789"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac266976ecf2df78224be648346faf789">PIN_PA11D_SERCOM2_PAD3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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<tr class="memdesc:ac266976ecf2df78224be648346faf789"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM2 signal: PAD3 on PA11 mux D. <br /></td></tr>
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<tr class="separator:ac266976ecf2df78224be648346faf789"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abbeaf90326dc24fa95566ad117da82e5"><td class="memItemLeft" align="right" valign="top"><a id="abbeaf90326dc24fa95566ad117da82e5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA11D_SERCOM2_PAD3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="separator:abbeaf90326dc24fa95566ad117da82e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4c3fdce09eaac07d6cf3525bbfcfb68c"><td class="memItemLeft" align="right" valign="top"><a id="a4c3fdce09eaac07d6cf3525bbfcfb68c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA11D_SERCOM2_PAD3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ac266976ecf2df78224be648346faf789">PIN_PA11D_SERCOM2_PAD3</a> << 16) | MUX_PA11D_SERCOM2_PAD3)</td></tr>
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<tr class="separator:a4c3fdce09eaac07d6cf3525bbfcfb68c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac41e28646debc10891d3079f29b61fe2"><td class="memItemLeft" align="right" valign="top"><a id="ac41e28646debc10891d3079f29b61fe2"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA11D_SERCOM2_PAD3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 11)</td></tr>
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<tr class="separator:ac41e28646debc10891d3079f29b61fe2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abfdc4d762c99b2e90ba5fcbbb486f47c"><td class="memItemLeft" align="right" valign="top"><a id="abfdc4d762c99b2e90ba5fcbbb486f47c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#abfdc4d762c99b2e90ba5fcbbb486f47c">PIN_PC25D_SERCOM2_PAD3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(89)</td></tr>
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||
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<tr class="memdesc:abfdc4d762c99b2e90ba5fcbbb486f47c"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM2 signal: PAD3 on PC25 mux D. <br /></td></tr>
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<tr class="separator:abfdc4d762c99b2e90ba5fcbbb486f47c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa1234333b2c6e1bebd60e6d1c946394f"><td class="memItemLeft" align="right" valign="top"><a id="aa1234333b2c6e1bebd60e6d1c946394f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC25D_SERCOM2_PAD3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="separator:aa1234333b2c6e1bebd60e6d1c946394f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a06e32410871f6ad116f9ec53669eb613"><td class="memItemLeft" align="right" valign="top"><a id="a06e32410871f6ad116f9ec53669eb613"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC25D_SERCOM2_PAD3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#abfdc4d762c99b2e90ba5fcbbb486f47c">PIN_PC25D_SERCOM2_PAD3</a> << 16) | MUX_PC25D_SERCOM2_PAD3)</td></tr>
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<tr class="separator:a06e32410871f6ad116f9ec53669eb613"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a082de3b90cd60d1a4a16d30787d2abd5"><td class="memItemLeft" align="right" valign="top"><a id="a082de3b90cd60d1a4a16d30787d2abd5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC25D_SERCOM2_PAD3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 25)</td></tr>
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<tr class="separator:a082de3b90cd60d1a4a16d30787d2abd5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af8dfa9adfe5ca9c951d4914889e0cda4"><td class="memItemLeft" align="right" valign="top"><a id="af8dfa9adfe5ca9c951d4914889e0cda4"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af8dfa9adfe5ca9c951d4914889e0cda4">PIN_PA15C_SERCOM2_PAD3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(15)</td></tr>
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||
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<tr class="memdesc:af8dfa9adfe5ca9c951d4914889e0cda4"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM2 signal: PAD3 on PA15 mux C. <br /></td></tr>
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<tr class="separator:af8dfa9adfe5ca9c951d4914889e0cda4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0c68af0faaebfe145679d04615165a20"><td class="memItemLeft" align="right" valign="top"><a id="a0c68af0faaebfe145679d04615165a20"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA15C_SERCOM2_PAD3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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<tr class="separator:a0c68af0faaebfe145679d04615165a20"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adfbf7933ae6bfe6b8b36508fcb7fd3b3"><td class="memItemLeft" align="right" valign="top"><a id="adfbf7933ae6bfe6b8b36508fcb7fd3b3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA15C_SERCOM2_PAD3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#af8dfa9adfe5ca9c951d4914889e0cda4">PIN_PA15C_SERCOM2_PAD3</a> << 16) | MUX_PA15C_SERCOM2_PAD3)</td></tr>
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<tr class="separator:adfbf7933ae6bfe6b8b36508fcb7fd3b3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a273b6da9e8d42ffd072b6afd12de29d7"><td class="memItemLeft" align="right" valign="top"><a id="a273b6da9e8d42ffd072b6afd12de29d7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA15C_SERCOM2_PAD3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 15)</td></tr>
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<tr class="separator:a273b6da9e8d42ffd072b6afd12de29d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a35a80f6f9d1bbc67e5481643bbb0bb83"><td class="memItemLeft" align="right" valign="top"><a id="a35a80f6f9d1bbc67e5481643bbb0bb83"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a35a80f6f9d1bbc67e5481643bbb0bb83">PIN_PA17D_SERCOM3_PAD0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(17)</td></tr>
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||
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<tr class="memdesc:a35a80f6f9d1bbc67e5481643bbb0bb83"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM3 signal: PAD0 on PA17 mux D. <br /></td></tr>
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<tr class="separator:a35a80f6f9d1bbc67e5481643bbb0bb83"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4cd7ee200346eb17fa30ec28cd25bdc9"><td class="memItemLeft" align="right" valign="top"><a id="a4cd7ee200346eb17fa30ec28cd25bdc9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA17D_SERCOM3_PAD0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="separator:a4cd7ee200346eb17fa30ec28cd25bdc9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac124e1569bbf702271838ed69193034e"><td class="memItemLeft" align="right" valign="top"><a id="ac124e1569bbf702271838ed69193034e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA17D_SERCOM3_PAD0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a35a80f6f9d1bbc67e5481643bbb0bb83">PIN_PA17D_SERCOM3_PAD0</a> << 16) | MUX_PA17D_SERCOM3_PAD0)</td></tr>
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<tr class="separator:ac124e1569bbf702271838ed69193034e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af382ca85ac997bc61b51c0d381daf1af"><td class="memItemLeft" align="right" valign="top"><a id="af382ca85ac997bc61b51c0d381daf1af"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA17D_SERCOM3_PAD0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 17)</td></tr>
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<tr class="separator:af382ca85ac997bc61b51c0d381daf1af"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9cd984c9db10e1b847bfc4224b7d324b"><td class="memItemLeft" align="right" valign="top"><a id="a9cd984c9db10e1b847bfc4224b7d324b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a9cd984c9db10e1b847bfc4224b7d324b">PIN_PA22C_SERCOM3_PAD0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(22)</td></tr>
|
||
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<tr class="memdesc:a9cd984c9db10e1b847bfc4224b7d324b"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM3 signal: PAD0 on PA22 mux C. <br /></td></tr>
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<tr class="separator:a9cd984c9db10e1b847bfc4224b7d324b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6cd6e38d54da57f09cffcf49248aeee3"><td class="memItemLeft" align="right" valign="top"><a id="a6cd6e38d54da57f09cffcf49248aeee3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA22C_SERCOM3_PAD0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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||
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<tr class="separator:a6cd6e38d54da57f09cffcf49248aeee3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2dc12737bd31027da2b88c88ddf2f480"><td class="memItemLeft" align="right" valign="top"><a id="a2dc12737bd31027da2b88c88ddf2f480"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA22C_SERCOM3_PAD0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a9cd984c9db10e1b847bfc4224b7d324b">PIN_PA22C_SERCOM3_PAD0</a> << 16) | MUX_PA22C_SERCOM3_PAD0)</td></tr>
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<tr class="separator:a2dc12737bd31027da2b88c88ddf2f480"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3208352082b6c8db3849c3481b6fc157"><td class="memItemLeft" align="right" valign="top"><a id="a3208352082b6c8db3849c3481b6fc157"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA22C_SERCOM3_PAD0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 22)</td></tr>
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<tr class="separator:a3208352082b6c8db3849c3481b6fc157"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a11b6ccdb29c02edd24e4083791682106"><td class="memItemLeft" align="right" valign="top"><a id="a11b6ccdb29c02edd24e4083791682106"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a11b6ccdb29c02edd24e4083791682106">PIN_PB20C_SERCOM3_PAD0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(52)</td></tr>
|
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<tr class="memdesc:a11b6ccdb29c02edd24e4083791682106"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM3 signal: PAD0 on PB20 mux C. <br /></td></tr>
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<tr class="separator:a11b6ccdb29c02edd24e4083791682106"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a47ba11ca8c68ae6b88a5175e4488dfdd"><td class="memItemLeft" align="right" valign="top"><a id="a47ba11ca8c68ae6b88a5175e4488dfdd"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB20C_SERCOM3_PAD0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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<tr class="separator:a47ba11ca8c68ae6b88a5175e4488dfdd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aee8316ae208ab3ac4439e087e3199f9c"><td class="memItemLeft" align="right" valign="top"><a id="aee8316ae208ab3ac4439e087e3199f9c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB20C_SERCOM3_PAD0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a11b6ccdb29c02edd24e4083791682106">PIN_PB20C_SERCOM3_PAD0</a> << 16) | MUX_PB20C_SERCOM3_PAD0)</td></tr>
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<tr class="separator:aee8316ae208ab3ac4439e087e3199f9c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a86097ff8fedbebc81de642b4c82d26e7"><td class="memItemLeft" align="right" valign="top"><a id="a86097ff8fedbebc81de642b4c82d26e7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB20C_SERCOM3_PAD0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 20)</td></tr>
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<tr class="separator:a86097ff8fedbebc81de642b4c82d26e7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7496dfac12b0c3c3379324b02df308a0"><td class="memItemLeft" align="right" valign="top"><a id="a7496dfac12b0c3c3379324b02df308a0"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7496dfac12b0c3c3379324b02df308a0">PIN_PA16D_SERCOM3_PAD1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(16)</td></tr>
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<tr class="memdesc:a7496dfac12b0c3c3379324b02df308a0"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM3 signal: PAD1 on PA16 mux D. <br /></td></tr>
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<tr class="separator:a7496dfac12b0c3c3379324b02df308a0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa6b8ab39e0aed90a61758feaa99870ea"><td class="memItemLeft" align="right" valign="top"><a id="aa6b8ab39e0aed90a61758feaa99870ea"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA16D_SERCOM3_PAD1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="separator:aa6b8ab39e0aed90a61758feaa99870ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac62724097e7403ed571b8ebf7b0a43e2"><td class="memItemLeft" align="right" valign="top"><a id="ac62724097e7403ed571b8ebf7b0a43e2"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA16D_SERCOM3_PAD1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a7496dfac12b0c3c3379324b02df308a0">PIN_PA16D_SERCOM3_PAD1</a> << 16) | MUX_PA16D_SERCOM3_PAD1)</td></tr>
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<tr class="separator:ac62724097e7403ed571b8ebf7b0a43e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa0ebaf7310d8df67675d766bbc09ce1a"><td class="memItemLeft" align="right" valign="top"><a id="aa0ebaf7310d8df67675d766bbc09ce1a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA16D_SERCOM3_PAD1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 16)</td></tr>
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<tr class="separator:aa0ebaf7310d8df67675d766bbc09ce1a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af3317ce41a4529ece8179416b7c1a56f"><td class="memItemLeft" align="right" valign="top"><a id="af3317ce41a4529ece8179416b7c1a56f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af3317ce41a4529ece8179416b7c1a56f">PIN_PA23C_SERCOM3_PAD1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(23)</td></tr>
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||
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<tr class="memdesc:af3317ce41a4529ece8179416b7c1a56f"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM3 signal: PAD1 on PA23 mux C. <br /></td></tr>
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<tr class="separator:af3317ce41a4529ece8179416b7c1a56f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7db75c79a9124dd0191c40f680abb506"><td class="memItemLeft" align="right" valign="top"><a id="a7db75c79a9124dd0191c40f680abb506"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA23C_SERCOM3_PAD1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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<tr class="separator:a7db75c79a9124dd0191c40f680abb506"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5bafe5c3611ad1e03fc59315a75d59b9"><td class="memItemLeft" align="right" valign="top"><a id="a5bafe5c3611ad1e03fc59315a75d59b9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA23C_SERCOM3_PAD1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#af3317ce41a4529ece8179416b7c1a56f">PIN_PA23C_SERCOM3_PAD1</a> << 16) | MUX_PA23C_SERCOM3_PAD1)</td></tr>
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<tr class="separator:a5bafe5c3611ad1e03fc59315a75d59b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3b9cfc3c2e016b6de20d901ea8bc7cf6"><td class="memItemLeft" align="right" valign="top"><a id="a3b9cfc3c2e016b6de20d901ea8bc7cf6"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA23C_SERCOM3_PAD1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 23)</td></tr>
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<tr class="separator:a3b9cfc3c2e016b6de20d901ea8bc7cf6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8d808bf85acfcc204156347146aa7118"><td class="memItemLeft" align="right" valign="top"><a id="a8d808bf85acfcc204156347146aa7118"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8d808bf85acfcc204156347146aa7118">PIN_PB21C_SERCOM3_PAD1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(53)</td></tr>
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||
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<tr class="memdesc:a8d808bf85acfcc204156347146aa7118"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM3 signal: PAD1 on PB21 mux C. <br /></td></tr>
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<tr class="separator:a8d808bf85acfcc204156347146aa7118"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afa9e2514be65a90fa2c12c063252051c"><td class="memItemLeft" align="right" valign="top"><a id="afa9e2514be65a90fa2c12c063252051c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB21C_SERCOM3_PAD1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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||
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<tr class="separator:afa9e2514be65a90fa2c12c063252051c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a29a82c4138b1698b4c112920c14f6d47"><td class="memItemLeft" align="right" valign="top"><a id="a29a82c4138b1698b4c112920c14f6d47"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB21C_SERCOM3_PAD1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a8d808bf85acfcc204156347146aa7118">PIN_PB21C_SERCOM3_PAD1</a> << 16) | MUX_PB21C_SERCOM3_PAD1)</td></tr>
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<tr class="separator:a29a82c4138b1698b4c112920c14f6d47"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3208ca5a8faef4000455af8c4c3b134d"><td class="memItemLeft" align="right" valign="top"><a id="a3208ca5a8faef4000455af8c4c3b134d"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB21C_SERCOM3_PAD1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 21)</td></tr>
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||
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<tr class="separator:a3208ca5a8faef4000455af8c4c3b134d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa99a01237c215665208d0d29b17a27d3"><td class="memItemLeft" align="right" valign="top"><a id="aa99a01237c215665208d0d29b17a27d3"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa99a01237c215665208d0d29b17a27d3">PIN_PA18D_SERCOM3_PAD2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(18)</td></tr>
|
||
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<tr class="memdesc:aa99a01237c215665208d0d29b17a27d3"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM3 signal: PAD2 on PA18 mux D. <br /></td></tr>
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<tr class="separator:aa99a01237c215665208d0d29b17a27d3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab7a7e0ae4d389d836ccad30d41064dda"><td class="memItemLeft" align="right" valign="top"><a id="ab7a7e0ae4d389d836ccad30d41064dda"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA18D_SERCOM3_PAD2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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||
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<tr class="separator:ab7a7e0ae4d389d836ccad30d41064dda"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af6cb9fda1d08852a9eb34e59a6103373"><td class="memItemLeft" align="right" valign="top"><a id="af6cb9fda1d08852a9eb34e59a6103373"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA18D_SERCOM3_PAD2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aa99a01237c215665208d0d29b17a27d3">PIN_PA18D_SERCOM3_PAD2</a> << 16) | MUX_PA18D_SERCOM3_PAD2)</td></tr>
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<tr class="separator:af6cb9fda1d08852a9eb34e59a6103373"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7d2c24af5e747978a094cca6c97bbe86"><td class="memItemLeft" align="right" valign="top"><a id="a7d2c24af5e747978a094cca6c97bbe86"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA18D_SERCOM3_PAD2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 18)</td></tr>
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||
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<tr class="separator:a7d2c24af5e747978a094cca6c97bbe86"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab474048e84d45a520ab940f5a02dd7a8"><td class="memItemLeft" align="right" valign="top"><a id="ab474048e84d45a520ab940f5a02dd7a8"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab474048e84d45a520ab940f5a02dd7a8">PIN_PA20D_SERCOM3_PAD2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(20)</td></tr>
|
||
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<tr class="memdesc:ab474048e84d45a520ab940f5a02dd7a8"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM3 signal: PAD2 on PA20 mux D. <br /></td></tr>
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<tr class="separator:ab474048e84d45a520ab940f5a02dd7a8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a13e72b6a4c06386561c40fae16443a6d"><td class="memItemLeft" align="right" valign="top"><a id="a13e72b6a4c06386561c40fae16443a6d"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA20D_SERCOM3_PAD2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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||
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<tr class="separator:a13e72b6a4c06386561c40fae16443a6d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a656ce062e01964de433bc1cf261c6e29"><td class="memItemLeft" align="right" valign="top"><a id="a656ce062e01964de433bc1cf261c6e29"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA20D_SERCOM3_PAD2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ab474048e84d45a520ab940f5a02dd7a8">PIN_PA20D_SERCOM3_PAD2</a> << 16) | MUX_PA20D_SERCOM3_PAD2)</td></tr>
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<tr class="separator:a656ce062e01964de433bc1cf261c6e29"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7c37d07ec319132cd76aa93abcf7327c"><td class="memItemLeft" align="right" valign="top"><a id="a7c37d07ec319132cd76aa93abcf7327c"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA20D_SERCOM3_PAD2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 20)</td></tr>
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||
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<tr class="separator:a7c37d07ec319132cd76aa93abcf7327c"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:af84b9177a74b0cbce8cef9dbd7e2114b"><td class="memItemLeft" align="right" valign="top"><a id="af84b9177a74b0cbce8cef9dbd7e2114b"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af84b9177a74b0cbce8cef9dbd7e2114b">PIN_PA24C_SERCOM3_PAD2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(24)</td></tr>
|
||
|
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<tr class="memdesc:af84b9177a74b0cbce8cef9dbd7e2114b"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM3 signal: PAD2 on PA24 mux C. <br /></td></tr>
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||
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<tr class="separator:af84b9177a74b0cbce8cef9dbd7e2114b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a91ceb09fa1663cd64f8d3b091a69a182"><td class="memItemLeft" align="right" valign="top"><a id="a91ceb09fa1663cd64f8d3b091a69a182"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA24C_SERCOM3_PAD2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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||
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<tr class="separator:a91ceb09fa1663cd64f8d3b091a69a182"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5c42ce61557386117e22bd24baab49dc"><td class="memItemLeft" align="right" valign="top"><a id="a5c42ce61557386117e22bd24baab49dc"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA24C_SERCOM3_PAD2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#af84b9177a74b0cbce8cef9dbd7e2114b">PIN_PA24C_SERCOM3_PAD2</a> << 16) | MUX_PA24C_SERCOM3_PAD2)</td></tr>
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<tr class="separator:a5c42ce61557386117e22bd24baab49dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a44410dd1b8faf275840b9e5f44e7bfdb"><td class="memItemLeft" align="right" valign="top"><a id="a44410dd1b8faf275840b9e5f44e7bfdb"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA24C_SERCOM3_PAD2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 24)</td></tr>
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||
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<tr class="separator:a44410dd1b8faf275840b9e5f44e7bfdb"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a2ed5bb59474047684f40617d5ecfd461"><td class="memItemLeft" align="right" valign="top"><a id="a2ed5bb59474047684f40617d5ecfd461"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2ed5bb59474047684f40617d5ecfd461">PIN_PA19D_SERCOM3_PAD3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(19)</td></tr>
|
||
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<tr class="memdesc:a2ed5bb59474047684f40617d5ecfd461"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM3 signal: PAD3 on PA19 mux D. <br /></td></tr>
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||
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<tr class="separator:a2ed5bb59474047684f40617d5ecfd461"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:ac72bb03f3f86ebef0b07224ecdcb812a"><td class="memItemLeft" align="right" valign="top"><a id="ac72bb03f3f86ebef0b07224ecdcb812a"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA19D_SERCOM3_PAD3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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||
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<tr class="separator:ac72bb03f3f86ebef0b07224ecdcb812a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac4e13b89d2d7a5f23fad197ddeaca2d3"><td class="memItemLeft" align="right" valign="top"><a id="ac4e13b89d2d7a5f23fad197ddeaca2d3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA19D_SERCOM3_PAD3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a2ed5bb59474047684f40617d5ecfd461">PIN_PA19D_SERCOM3_PAD3</a> << 16) | MUX_PA19D_SERCOM3_PAD3)</td></tr>
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<tr class="separator:ac4e13b89d2d7a5f23fad197ddeaca2d3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a444f91b8c8b9409a3e421368ef2de7f8"><td class="memItemLeft" align="right" valign="top"><a id="a444f91b8c8b9409a3e421368ef2de7f8"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA19D_SERCOM3_PAD3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 19)</td></tr>
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<tr class="separator:a444f91b8c8b9409a3e421368ef2de7f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3852b08953bca00e4840cf4017d856f6"><td class="memItemLeft" align="right" valign="top"><a id="a3852b08953bca00e4840cf4017d856f6"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3852b08953bca00e4840cf4017d856f6">PIN_PA21D_SERCOM3_PAD3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(21)</td></tr>
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<tr class="memdesc:a3852b08953bca00e4840cf4017d856f6"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM3 signal: PAD3 on PA21 mux D. <br /></td></tr>
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<tr class="separator:a3852b08953bca00e4840cf4017d856f6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a765c008384c388f7a90ac0a05dc8c8df"><td class="memItemLeft" align="right" valign="top"><a id="a765c008384c388f7a90ac0a05dc8c8df"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA21D_SERCOM3_PAD3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="separator:a765c008384c388f7a90ac0a05dc8c8df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a451cb69b9ae10fc343152d89eed0edc5"><td class="memItemLeft" align="right" valign="top"><a id="a451cb69b9ae10fc343152d89eed0edc5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA21D_SERCOM3_PAD3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a3852b08953bca00e4840cf4017d856f6">PIN_PA21D_SERCOM3_PAD3</a> << 16) | MUX_PA21D_SERCOM3_PAD3)</td></tr>
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<tr class="separator:a451cb69b9ae10fc343152d89eed0edc5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3ec023fd639c1022212a5cad19493f12"><td class="memItemLeft" align="right" valign="top"><a id="a3ec023fd639c1022212a5cad19493f12"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA21D_SERCOM3_PAD3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 21)</td></tr>
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<tr class="separator:a3ec023fd639c1022212a5cad19493f12"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7f86d5f1e4d85d8c3888682c2505a33f"><td class="memItemLeft" align="right" valign="top"><a id="a7f86d5f1e4d85d8c3888682c2505a33f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7f86d5f1e4d85d8c3888682c2505a33f">PIN_PA25C_SERCOM3_PAD3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(25)</td></tr>
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||
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<tr class="memdesc:a7f86d5f1e4d85d8c3888682c2505a33f"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM3 signal: PAD3 on PA25 mux C. <br /></td></tr>
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<tr class="separator:a7f86d5f1e4d85d8c3888682c2505a33f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab7cef86e0a84f2e8d9ac7a512ed639dc"><td class="memItemLeft" align="right" valign="top"><a id="ab7cef86e0a84f2e8d9ac7a512ed639dc"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA25C_SERCOM3_PAD3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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<tr class="separator:ab7cef86e0a84f2e8d9ac7a512ed639dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a91b225ee50c4f3ca42f449ef92f484f8"><td class="memItemLeft" align="right" valign="top"><a id="a91b225ee50c4f3ca42f449ef92f484f8"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA25C_SERCOM3_PAD3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a7f86d5f1e4d85d8c3888682c2505a33f">PIN_PA25C_SERCOM3_PAD3</a> << 16) | MUX_PA25C_SERCOM3_PAD3)</td></tr>
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<tr class="separator:a91b225ee50c4f3ca42f449ef92f484f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afcb5131fa87c5df77b89a1951ba3327f"><td class="memItemLeft" align="right" valign="top"><a id="afcb5131fa87c5df77b89a1951ba3327f"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA25C_SERCOM3_PAD3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 25)</td></tr>
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||
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<tr class="separator:afcb5131fa87c5df77b89a1951ba3327f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1447d994a01689c1f405ab71251dd10c"><td class="memItemLeft" align="right" valign="top"><a id="a1447d994a01689c1f405ab71251dd10c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1447d994a01689c1f405ab71251dd10c">PIN_PA20G_TCC0_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(20)</td></tr>
|
||
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<tr class="memdesc:a1447d994a01689c1f405ab71251dd10c"><td class="mdescLeft"> </td><td class="mdescRight">TCC0 signal: WO0 on PA20 mux G. <br /></td></tr>
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||
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<tr class="separator:a1447d994a01689c1f405ab71251dd10c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af28eeb3e560ba16befd33d5ec7530ea2"><td class="memItemLeft" align="right" valign="top"><a id="af28eeb3e560ba16befd33d5ec7530ea2"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA20G_TCC0_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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||
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<tr class="separator:af28eeb3e560ba16befd33d5ec7530ea2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3ba75946ec39e9164e39701792b4463b"><td class="memItemLeft" align="right" valign="top"><a id="a3ba75946ec39e9164e39701792b4463b"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA20G_TCC0_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a1447d994a01689c1f405ab71251dd10c">PIN_PA20G_TCC0_WO0</a> << 16) | MUX_PA20G_TCC0_WO0)</td></tr>
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<tr class="separator:a3ba75946ec39e9164e39701792b4463b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5103d026b5b2cd5c57d4c272a7a399f4"><td class="memItemLeft" align="right" valign="top"><a id="a5103d026b5b2cd5c57d4c272a7a399f4"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA20G_TCC0_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 20)</td></tr>
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||
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<tr class="separator:a5103d026b5b2cd5c57d4c272a7a399f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a29b479f14d4f419d7128c72481adaa69"><td class="memItemLeft" align="right" valign="top"><a id="a29b479f14d4f419d7128c72481adaa69"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a29b479f14d4f419d7128c72481adaa69">PIN_PB12G_TCC0_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(44)</td></tr>
|
||
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<tr class="memdesc:a29b479f14d4f419d7128c72481adaa69"><td class="mdescLeft"> </td><td class="mdescRight">TCC0 signal: WO0 on PB12 mux G. <br /></td></tr>
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<tr class="separator:a29b479f14d4f419d7128c72481adaa69"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aca14ac3eeb671109207e85e2844f5f4d"><td class="memItemLeft" align="right" valign="top"><a id="aca14ac3eeb671109207e85e2844f5f4d"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB12G_TCC0_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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<tr class="separator:aca14ac3eeb671109207e85e2844f5f4d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6fb2320ca61e224388f757c1a9353667"><td class="memItemLeft" align="right" valign="top"><a id="a6fb2320ca61e224388f757c1a9353667"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB12G_TCC0_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a29b479f14d4f419d7128c72481adaa69">PIN_PB12G_TCC0_WO0</a> << 16) | MUX_PB12G_TCC0_WO0)</td></tr>
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<tr class="separator:a6fb2320ca61e224388f757c1a9353667"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae1615c46bfe83c9bded81e7209e902ae"><td class="memItemLeft" align="right" valign="top"><a id="ae1615c46bfe83c9bded81e7209e902ae"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB12G_TCC0_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 12)</td></tr>
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||
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<tr class="separator:ae1615c46bfe83c9bded81e7209e902ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9bc32b65378a98bb6a0a33ac17503a9b"><td class="memItemLeft" align="right" valign="top"><a id="a9bc32b65378a98bb6a0a33ac17503a9b"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a9bc32b65378a98bb6a0a33ac17503a9b">PIN_PA08F_TCC0_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
|
||
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<tr class="memdesc:a9bc32b65378a98bb6a0a33ac17503a9b"><td class="mdescLeft"> </td><td class="mdescRight">TCC0 signal: WO0 on PA08 mux F. <br /></td></tr>
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<tr class="separator:a9bc32b65378a98bb6a0a33ac17503a9b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6e88a6489d25ee5e180b5d4a34e91648"><td class="memItemLeft" align="right" valign="top"><a id="a6e88a6489d25ee5e180b5d4a34e91648"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA08F_TCC0_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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||
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<tr class="separator:a6e88a6489d25ee5e180b5d4a34e91648"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a40550d9bf68bdacb73da15b6247336cd"><td class="memItemLeft" align="right" valign="top"><a id="a40550d9bf68bdacb73da15b6247336cd"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA08F_TCC0_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a9bc32b65378a98bb6a0a33ac17503a9b">PIN_PA08F_TCC0_WO0</a> << 16) | MUX_PA08F_TCC0_WO0)</td></tr>
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<tr class="separator:a40550d9bf68bdacb73da15b6247336cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac82be552f1f836d73a043494c516b2e9"><td class="memItemLeft" align="right" valign="top"><a id="ac82be552f1f836d73a043494c516b2e9"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA08F_TCC0_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 8)</td></tr>
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||
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<tr class="separator:ac82be552f1f836d73a043494c516b2e9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6ceeee3627613c8b5b8beeb576f782b9"><td class="memItemLeft" align="right" valign="top"><a id="a6ceeee3627613c8b5b8beeb576f782b9"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6ceeee3627613c8b5b8beeb576f782b9">PIN_PC10F_TCC0_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(74)</td></tr>
|
||
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<tr class="memdesc:a6ceeee3627613c8b5b8beeb576f782b9"><td class="mdescLeft"> </td><td class="mdescRight">TCC0 signal: WO0 on PC10 mux F. <br /></td></tr>
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<tr class="separator:a6ceeee3627613c8b5b8beeb576f782b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae4c6f5d65045f23bb24dbcaf3639711b"><td class="memItemLeft" align="right" valign="top"><a id="ae4c6f5d65045f23bb24dbcaf3639711b"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC10F_TCC0_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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||
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<tr class="separator:ae4c6f5d65045f23bb24dbcaf3639711b"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a0a4c752bf34d96c3f566e6d3b97ed866"><td class="memItemLeft" align="right" valign="top"><a id="a0a4c752bf34d96c3f566e6d3b97ed866"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC10F_TCC0_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a6ceeee3627613c8b5b8beeb576f782b9">PIN_PC10F_TCC0_WO0</a> << 16) | MUX_PC10F_TCC0_WO0)</td></tr>
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<tr class="separator:a0a4c752bf34d96c3f566e6d3b97ed866"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:af5054352943ee8cc98339b4f6169b3e2"><td class="memItemLeft" align="right" valign="top"><a id="af5054352943ee8cc98339b4f6169b3e2"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC10F_TCC0_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 10)</td></tr>
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||
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<tr class="separator:af5054352943ee8cc98339b4f6169b3e2"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:ab90dfd1c85797cfecee5618da9d2c8e1"><td class="memItemLeft" align="right" valign="top"><a id="ab90dfd1c85797cfecee5618da9d2c8e1"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab90dfd1c85797cfecee5618da9d2c8e1">PIN_PC16F_TCC0_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(80)</td></tr>
|
||
|
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<tr class="memdesc:ab90dfd1c85797cfecee5618da9d2c8e1"><td class="mdescLeft"> </td><td class="mdescRight">TCC0 signal: WO0 on PC16 mux F. <br /></td></tr>
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||
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<tr class="separator:ab90dfd1c85797cfecee5618da9d2c8e1"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a37385c0fc0a96d791ac9d0f1e718ec36"><td class="memItemLeft" align="right" valign="top"><a id="a37385c0fc0a96d791ac9d0f1e718ec36"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC16F_TCC0_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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||
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<tr class="separator:a37385c0fc0a96d791ac9d0f1e718ec36"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af3e69af26f104b8ea997b6245ba8ba79"><td class="memItemLeft" align="right" valign="top"><a id="af3e69af26f104b8ea997b6245ba8ba79"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC16F_TCC0_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ab90dfd1c85797cfecee5618da9d2c8e1">PIN_PC16F_TCC0_WO0</a> << 16) | MUX_PC16F_TCC0_WO0)</td></tr>
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<tr class="separator:af3e69af26f104b8ea997b6245ba8ba79"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a65918bceb15eb97c5f187b74b4895665"><td class="memItemLeft" align="right" valign="top"><a id="a65918bceb15eb97c5f187b74b4895665"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC16F_TCC0_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 16)</td></tr>
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<tr class="separator:a65918bceb15eb97c5f187b74b4895665"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a19850f46bc2077f7468e9c9122aff45b"><td class="memItemLeft" align="right" valign="top"><a id="a19850f46bc2077f7468e9c9122aff45b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a19850f46bc2077f7468e9c9122aff45b">PIN_PA21G_TCC0_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(21)</td></tr>
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<tr class="memdesc:a19850f46bc2077f7468e9c9122aff45b"><td class="mdescLeft"> </td><td class="mdescRight">TCC0 signal: WO1 on PA21 mux G. <br /></td></tr>
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<tr class="separator:a19850f46bc2077f7468e9c9122aff45b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af6fbbf083166e468146407f01cb43f32"><td class="memItemLeft" align="right" valign="top"><a id="af6fbbf083166e468146407f01cb43f32"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA21G_TCC0_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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<tr class="separator:af6fbbf083166e468146407f01cb43f32"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a16edb1d5ceb954de35722e6805084931"><td class="memItemLeft" align="right" valign="top"><a id="a16edb1d5ceb954de35722e6805084931"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA21G_TCC0_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a19850f46bc2077f7468e9c9122aff45b">PIN_PA21G_TCC0_WO1</a> << 16) | MUX_PA21G_TCC0_WO1)</td></tr>
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<tr class="separator:a16edb1d5ceb954de35722e6805084931"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a950ddcf6ef48310bb23856fd74e4d00a"><td class="memItemLeft" align="right" valign="top"><a id="a950ddcf6ef48310bb23856fd74e4d00a"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA21G_TCC0_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 21)</td></tr>
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||
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<tr class="separator:a950ddcf6ef48310bb23856fd74e4d00a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a344342f987fb95c5f8fcd7c5c563d6c6"><td class="memItemLeft" align="right" valign="top"><a id="a344342f987fb95c5f8fcd7c5c563d6c6"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a344342f987fb95c5f8fcd7c5c563d6c6">PIN_PB13G_TCC0_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(45)</td></tr>
|
||
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<tr class="memdesc:a344342f987fb95c5f8fcd7c5c563d6c6"><td class="mdescLeft"> </td><td class="mdescRight">TCC0 signal: WO1 on PB13 mux G. <br /></td></tr>
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<tr class="separator:a344342f987fb95c5f8fcd7c5c563d6c6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4e844bac5505a758c591ec06a8a05a4c"><td class="memItemLeft" align="right" valign="top"><a id="a4e844bac5505a758c591ec06a8a05a4c"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB13G_TCC0_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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<tr class="separator:a4e844bac5505a758c591ec06a8a05a4c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad010bfd7eb03801dea8922e0389656dd"><td class="memItemLeft" align="right" valign="top"><a id="ad010bfd7eb03801dea8922e0389656dd"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB13G_TCC0_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a344342f987fb95c5f8fcd7c5c563d6c6">PIN_PB13G_TCC0_WO1</a> << 16) | MUX_PB13G_TCC0_WO1)</td></tr>
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<tr class="separator:ad010bfd7eb03801dea8922e0389656dd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6f3e137af0148207196ff55153641277"><td class="memItemLeft" align="right" valign="top"><a id="a6f3e137af0148207196ff55153641277"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB13G_TCC0_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 13)</td></tr>
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||
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<tr class="separator:a6f3e137af0148207196ff55153641277"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad84013705279dd82d320a31f8973c20d"><td class="memItemLeft" align="right" valign="top"><a id="ad84013705279dd82d320a31f8973c20d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad84013705279dd82d320a31f8973c20d">PIN_PA09F_TCC0_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
|
||
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<tr class="memdesc:ad84013705279dd82d320a31f8973c20d"><td class="mdescLeft"> </td><td class="mdescRight">TCC0 signal: WO1 on PA09 mux F. <br /></td></tr>
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<tr class="separator:ad84013705279dd82d320a31f8973c20d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3360e0250282b5439244c54d846245e1"><td class="memItemLeft" align="right" valign="top"><a id="a3360e0250282b5439244c54d846245e1"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA09F_TCC0_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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||
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<tr class="separator:a3360e0250282b5439244c54d846245e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4eecc27aecf47ef6755842f19ee6fe0b"><td class="memItemLeft" align="right" valign="top"><a id="a4eecc27aecf47ef6755842f19ee6fe0b"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA09F_TCC0_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ad84013705279dd82d320a31f8973c20d">PIN_PA09F_TCC0_WO1</a> << 16) | MUX_PA09F_TCC0_WO1)</td></tr>
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<tr class="separator:a4eecc27aecf47ef6755842f19ee6fe0b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a28c5e81c4d4b14f50dadefb35725e93d"><td class="memItemLeft" align="right" valign="top"><a id="a28c5e81c4d4b14f50dadefb35725e93d"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA09F_TCC0_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 9)</td></tr>
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||
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<tr class="separator:a28c5e81c4d4b14f50dadefb35725e93d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8e0a101968ddee1f7d3183b108c18bdb"><td class="memItemLeft" align="right" valign="top"><a id="a8e0a101968ddee1f7d3183b108c18bdb"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8e0a101968ddee1f7d3183b108c18bdb">PIN_PC11F_TCC0_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(75)</td></tr>
|
||
|
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<tr class="memdesc:a8e0a101968ddee1f7d3183b108c18bdb"><td class="mdescLeft"> </td><td class="mdescRight">TCC0 signal: WO1 on PC11 mux F. <br /></td></tr>
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||
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<tr class="separator:a8e0a101968ddee1f7d3183b108c18bdb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a133ceb4ba8479dfa5d91738589aa838a"><td class="memItemLeft" align="right" valign="top"><a id="a133ceb4ba8479dfa5d91738589aa838a"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC11F_TCC0_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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||
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<tr class="separator:a133ceb4ba8479dfa5d91738589aa838a"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:ad1bef157148ecd7dbe3a2c3c7cbb65f6"><td class="memItemLeft" align="right" valign="top"><a id="ad1bef157148ecd7dbe3a2c3c7cbb65f6"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC11F_TCC0_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a8e0a101968ddee1f7d3183b108c18bdb">PIN_PC11F_TCC0_WO1</a> << 16) | MUX_PC11F_TCC0_WO1)</td></tr>
|
||
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<tr class="separator:ad1bef157148ecd7dbe3a2c3c7cbb65f6"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a6ec268fca73578fbe9781f5989d943e6"><td class="memItemLeft" align="right" valign="top"><a id="a6ec268fca73578fbe9781f5989d943e6"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC11F_TCC0_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 11)</td></tr>
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||
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<tr class="separator:a6ec268fca73578fbe9781f5989d943e6"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:af1e0a318f2bfedcad011325f4ccde590"><td class="memItemLeft" align="right" valign="top"><a id="af1e0a318f2bfedcad011325f4ccde590"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af1e0a318f2bfedcad011325f4ccde590">PIN_PC17F_TCC0_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(81)</td></tr>
|
||
|
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<tr class="memdesc:af1e0a318f2bfedcad011325f4ccde590"><td class="mdescLeft"> </td><td class="mdescRight">TCC0 signal: WO1 on PC17 mux F. <br /></td></tr>
|
||
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<tr class="separator:af1e0a318f2bfedcad011325f4ccde590"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0e22977d8938ebb8e878d12feabe1208"><td class="memItemLeft" align="right" valign="top"><a id="a0e22977d8938ebb8e878d12feabe1208"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC17F_TCC0_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
|
||
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<tr class="separator:a0e22977d8938ebb8e878d12feabe1208"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a59108f9155cdd41d4c96e4b63e489a0b"><td class="memItemLeft" align="right" valign="top"><a id="a59108f9155cdd41d4c96e4b63e489a0b"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC17F_TCC0_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#af1e0a318f2bfedcad011325f4ccde590">PIN_PC17F_TCC0_WO1</a> << 16) | MUX_PC17F_TCC0_WO1)</td></tr>
|
||
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<tr class="separator:a59108f9155cdd41d4c96e4b63e489a0b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5e841427a1549b07ac19dba07c0fbdec"><td class="memItemLeft" align="right" valign="top"><a id="a5e841427a1549b07ac19dba07c0fbdec"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC17F_TCC0_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 17)</td></tr>
|
||
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<tr class="separator:a5e841427a1549b07ac19dba07c0fbdec"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a57129d988e16abc9169b559813c66564"><td class="memItemLeft" align="right" valign="top"><a id="a57129d988e16abc9169b559813c66564"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a57129d988e16abc9169b559813c66564">PIN_PA22G_TCC0_WO2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(22)</td></tr>
|
||
|
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<tr class="memdesc:a57129d988e16abc9169b559813c66564"><td class="mdescLeft"> </td><td class="mdescRight">TCC0 signal: WO2 on PA22 mux G. <br /></td></tr>
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||
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<tr class="separator:a57129d988e16abc9169b559813c66564"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a51f2ef072f9e75a434ef17d05173b613"><td class="memItemLeft" align="right" valign="top"><a id="a51f2ef072f9e75a434ef17d05173b613"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA22G_TCC0_WO2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
|
||
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<tr class="separator:a51f2ef072f9e75a434ef17d05173b613"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a8f1d79f3de06c5ee1876f0f8e24f9004"><td class="memItemLeft" align="right" valign="top"><a id="a8f1d79f3de06c5ee1876f0f8e24f9004"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA22G_TCC0_WO2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a57129d988e16abc9169b559813c66564">PIN_PA22G_TCC0_WO2</a> << 16) | MUX_PA22G_TCC0_WO2)</td></tr>
|
||
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<tr class="separator:a8f1d79f3de06c5ee1876f0f8e24f9004"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a8ee884ca01cc4e17de77f77c2507cfc1"><td class="memItemLeft" align="right" valign="top"><a id="a8ee884ca01cc4e17de77f77c2507cfc1"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA22G_TCC0_WO2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 22)</td></tr>
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||
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<tr class="separator:a8ee884ca01cc4e17de77f77c2507cfc1"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a695a1e6c14936388d11246b1ae225957"><td class="memItemLeft" align="right" valign="top"><a id="a695a1e6c14936388d11246b1ae225957"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a695a1e6c14936388d11246b1ae225957">PIN_PB14G_TCC0_WO2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(46)</td></tr>
|
||
|
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<tr class="memdesc:a695a1e6c14936388d11246b1ae225957"><td class="mdescLeft"> </td><td class="mdescRight">TCC0 signal: WO2 on PB14 mux G. <br /></td></tr>
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||
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<tr class="separator:a695a1e6c14936388d11246b1ae225957"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9aa37d87b1978b91b9d5344128da13c9"><td class="memItemLeft" align="right" valign="top"><a id="a9aa37d87b1978b91b9d5344128da13c9"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB14G_TCC0_WO2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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||
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<tr class="separator:a9aa37d87b1978b91b9d5344128da13c9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7777020fb6b0deb4ff02f0fe3f1abc6a"><td class="memItemLeft" align="right" valign="top"><a id="a7777020fb6b0deb4ff02f0fe3f1abc6a"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB14G_TCC0_WO2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a695a1e6c14936388d11246b1ae225957">PIN_PB14G_TCC0_WO2</a> << 16) | MUX_PB14G_TCC0_WO2)</td></tr>
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||
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<tr class="separator:a7777020fb6b0deb4ff02f0fe3f1abc6a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a734cbdeb19dc945a6031412934baf44b"><td class="memItemLeft" align="right" valign="top"><a id="a734cbdeb19dc945a6031412934baf44b"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB14G_TCC0_WO2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 14)</td></tr>
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||
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<tr class="separator:a734cbdeb19dc945a6031412934baf44b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a828e7dcaf232b4411254cd2744cf137c"><td class="memItemLeft" align="right" valign="top"><a id="a828e7dcaf232b4411254cd2744cf137c"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a828e7dcaf232b4411254cd2744cf137c">PIN_PA10F_TCC0_WO2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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<tr class="memdesc:a828e7dcaf232b4411254cd2744cf137c"><td class="mdescLeft"> </td><td class="mdescRight">TCC0 signal: WO2 on PA10 mux F. <br /></td></tr>
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<tr class="separator:a828e7dcaf232b4411254cd2744cf137c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a39321e99a75efb82b64879c95a483e10"><td class="memItemLeft" align="right" valign="top"><a id="a39321e99a75efb82b64879c95a483e10"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA10F_TCC0_WO2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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<tr class="separator:a39321e99a75efb82b64879c95a483e10"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3bd0e070217c1f0b280835d897a98781"><td class="memItemLeft" align="right" valign="top"><a id="a3bd0e070217c1f0b280835d897a98781"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA10F_TCC0_WO2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a828e7dcaf232b4411254cd2744cf137c">PIN_PA10F_TCC0_WO2</a> << 16) | MUX_PA10F_TCC0_WO2)</td></tr>
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<tr class="separator:a3bd0e070217c1f0b280835d897a98781"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab66699212fc66b62d31f6673d079aed1"><td class="memItemLeft" align="right" valign="top"><a id="ab66699212fc66b62d31f6673d079aed1"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA10F_TCC0_WO2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 10)</td></tr>
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<tr class="separator:ab66699212fc66b62d31f6673d079aed1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a110c576a6cb94ca7ab46e98d042770f8"><td class="memItemLeft" align="right" valign="top"><a id="a110c576a6cb94ca7ab46e98d042770f8"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a110c576a6cb94ca7ab46e98d042770f8">PIN_PC12F_TCC0_WO2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(76)</td></tr>
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||
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<tr class="memdesc:a110c576a6cb94ca7ab46e98d042770f8"><td class="mdescLeft"> </td><td class="mdescRight">TCC0 signal: WO2 on PC12 mux F. <br /></td></tr>
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<tr class="separator:a110c576a6cb94ca7ab46e98d042770f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afa64fe6825207f6e3b57e476ea69a347"><td class="memItemLeft" align="right" valign="top"><a id="afa64fe6825207f6e3b57e476ea69a347"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC12F_TCC0_WO2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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<tr class="separator:afa64fe6825207f6e3b57e476ea69a347"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a359a75ff81eb0eb2bc5828f98cc8bb2c"><td class="memItemLeft" align="right" valign="top"><a id="a359a75ff81eb0eb2bc5828f98cc8bb2c"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC12F_TCC0_WO2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a110c576a6cb94ca7ab46e98d042770f8">PIN_PC12F_TCC0_WO2</a> << 16) | MUX_PC12F_TCC0_WO2)</td></tr>
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<tr class="separator:a359a75ff81eb0eb2bc5828f98cc8bb2c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a97a82378a1d08476edf483cc6319e593"><td class="memItemLeft" align="right" valign="top"><a id="a97a82378a1d08476edf483cc6319e593"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC12F_TCC0_WO2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 12)</td></tr>
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||
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<tr class="separator:a97a82378a1d08476edf483cc6319e593"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a600eacdd1f353c75f72a944849223155"><td class="memItemLeft" align="right" valign="top"><a id="a600eacdd1f353c75f72a944849223155"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a600eacdd1f353c75f72a944849223155">PIN_PC18F_TCC0_WO2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(82)</td></tr>
|
||
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<tr class="memdesc:a600eacdd1f353c75f72a944849223155"><td class="mdescLeft"> </td><td class="mdescRight">TCC0 signal: WO2 on PC18 mux F. <br /></td></tr>
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<tr class="separator:a600eacdd1f353c75f72a944849223155"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab74c9baecb3068f6668751d84756a3a9"><td class="memItemLeft" align="right" valign="top"><a id="ab74c9baecb3068f6668751d84756a3a9"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC18F_TCC0_WO2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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||
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<tr class="separator:ab74c9baecb3068f6668751d84756a3a9"><td class="memSeparator" colspan="2"> </td></tr>
|
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<tr class="memitem:a092bea20435929f3ef860eb54826c03b"><td class="memItemLeft" align="right" valign="top"><a id="a092bea20435929f3ef860eb54826c03b"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC18F_TCC0_WO2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a600eacdd1f353c75f72a944849223155">PIN_PC18F_TCC0_WO2</a> << 16) | MUX_PC18F_TCC0_WO2)</td></tr>
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<tr class="separator:a092bea20435929f3ef860eb54826c03b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a12a84691c7c540778d4dd84c6bc16875"><td class="memItemLeft" align="right" valign="top"><a id="a12a84691c7c540778d4dd84c6bc16875"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC18F_TCC0_WO2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 18)</td></tr>
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||
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<tr class="separator:a12a84691c7c540778d4dd84c6bc16875"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4f332786138b30fe8ec47042296bf22c"><td class="memItemLeft" align="right" valign="top"><a id="a4f332786138b30fe8ec47042296bf22c"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4f332786138b30fe8ec47042296bf22c">PIN_PA23G_TCC0_WO3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(23)</td></tr>
|
||
|
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<tr class="memdesc:a4f332786138b30fe8ec47042296bf22c"><td class="mdescLeft"> </td><td class="mdescRight">TCC0 signal: WO3 on PA23 mux G. <br /></td></tr>
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||
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<tr class="separator:a4f332786138b30fe8ec47042296bf22c"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a0267984f9e4d90ed282dfeca34e796c2"><td class="memItemLeft" align="right" valign="top"><a id="a0267984f9e4d90ed282dfeca34e796c2"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA23G_TCC0_WO3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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||
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<tr class="separator:a0267984f9e4d90ed282dfeca34e796c2"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a62ae0da6bb517ac46a2372926e9f2c72"><td class="memItemLeft" align="right" valign="top"><a id="a62ae0da6bb517ac46a2372926e9f2c72"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA23G_TCC0_WO3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a4f332786138b30fe8ec47042296bf22c">PIN_PA23G_TCC0_WO3</a> << 16) | MUX_PA23G_TCC0_WO3)</td></tr>
|
||
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<tr class="separator:a62ae0da6bb517ac46a2372926e9f2c72"><td class="memSeparator" colspan="2"> </td></tr>
|
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<tr class="memitem:aef5d58998578d1a7436dcf719400ad6c"><td class="memItemLeft" align="right" valign="top"><a id="aef5d58998578d1a7436dcf719400ad6c"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA23G_TCC0_WO3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 23)</td></tr>
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||
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<tr class="separator:aef5d58998578d1a7436dcf719400ad6c"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a74ac605097206091fdd52327badf7168"><td class="memItemLeft" align="right" valign="top"><a id="a74ac605097206091fdd52327badf7168"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a74ac605097206091fdd52327badf7168">PIN_PB15G_TCC0_WO3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(47)</td></tr>
|
||
|
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<tr class="memdesc:a74ac605097206091fdd52327badf7168"><td class="mdescLeft"> </td><td class="mdescRight">TCC0 signal: WO3 on PB15 mux G. <br /></td></tr>
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||
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<tr class="separator:a74ac605097206091fdd52327badf7168"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:ac0abdb8ef982e0fb2c2c3ce0bf0ae2cf"><td class="memItemLeft" align="right" valign="top"><a id="ac0abdb8ef982e0fb2c2c3ce0bf0ae2cf"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB15G_TCC0_WO3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
|
||
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<tr class="separator:ac0abdb8ef982e0fb2c2c3ce0bf0ae2cf"><td class="memSeparator" colspan="2"> </td></tr>
|
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<tr class="memitem:a869788012a48155ebb24fedd1817710a"><td class="memItemLeft" align="right" valign="top"><a id="a869788012a48155ebb24fedd1817710a"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB15G_TCC0_WO3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a74ac605097206091fdd52327badf7168">PIN_PB15G_TCC0_WO3</a> << 16) | MUX_PB15G_TCC0_WO3)</td></tr>
|
||
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<tr class="separator:a869788012a48155ebb24fedd1817710a"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a76341563383ce75e05314b11d3a862e2"><td class="memItemLeft" align="right" valign="top"><a id="a76341563383ce75e05314b11d3a862e2"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB15G_TCC0_WO3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 15)</td></tr>
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||
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<tr class="separator:a76341563383ce75e05314b11d3a862e2"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a73713eaacd87c4cef91a080dbd9fce06"><td class="memItemLeft" align="right" valign="top"><a id="a73713eaacd87c4cef91a080dbd9fce06"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a73713eaacd87c4cef91a080dbd9fce06">PIN_PA11F_TCC0_WO3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
|
||
|
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<tr class="memdesc:a73713eaacd87c4cef91a080dbd9fce06"><td class="mdescLeft"> </td><td class="mdescRight">TCC0 signal: WO3 on PA11 mux F. <br /></td></tr>
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<tr class="separator:a73713eaacd87c4cef91a080dbd9fce06"><td class="memSeparator" colspan="2"> </td></tr>
|
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<tr class="memitem:a99f9d0a0fa80dc6a1fdddb0df18c9aba"><td class="memItemLeft" align="right" valign="top"><a id="a99f9d0a0fa80dc6a1fdddb0df18c9aba"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA11F_TCC0_WO3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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||
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<tr class="separator:a99f9d0a0fa80dc6a1fdddb0df18c9aba"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:aaefebf491a2db13d566fb27eccd2c371"><td class="memItemLeft" align="right" valign="top"><a id="aaefebf491a2db13d566fb27eccd2c371"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA11F_TCC0_WO3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a73713eaacd87c4cef91a080dbd9fce06">PIN_PA11F_TCC0_WO3</a> << 16) | MUX_PA11F_TCC0_WO3)</td></tr>
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||
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<tr class="separator:aaefebf491a2db13d566fb27eccd2c371"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af84f106f9d6274765a3cb3a3f2b325af"><td class="memItemLeft" align="right" valign="top"><a id="af84f106f9d6274765a3cb3a3f2b325af"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA11F_TCC0_WO3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 11)</td></tr>
|
||
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<tr class="separator:af84f106f9d6274765a3cb3a3f2b325af"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a08989fda0b125c2861bd331a33f02f9c"><td class="memItemLeft" align="right" valign="top"><a id="a08989fda0b125c2861bd331a33f02f9c"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a08989fda0b125c2861bd331a33f02f9c">PIN_PC13F_TCC0_WO3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(77)</td></tr>
|
||
|
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<tr class="memdesc:a08989fda0b125c2861bd331a33f02f9c"><td class="mdescLeft"> </td><td class="mdescRight">TCC0 signal: WO3 on PC13 mux F. <br /></td></tr>
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||
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<tr class="separator:a08989fda0b125c2861bd331a33f02f9c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a595408d7db85556404ce76659b906870"><td class="memItemLeft" align="right" valign="top"><a id="a595408d7db85556404ce76659b906870"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC13F_TCC0_WO3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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||
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<tr class="separator:a595408d7db85556404ce76659b906870"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a9e1a8d6147dd71b94dba550527f8f9e9"><td class="memItemLeft" align="right" valign="top"><a id="a9e1a8d6147dd71b94dba550527f8f9e9"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC13F_TCC0_WO3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a08989fda0b125c2861bd331a33f02f9c">PIN_PC13F_TCC0_WO3</a> << 16) | MUX_PC13F_TCC0_WO3)</td></tr>
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||
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<tr class="separator:a9e1a8d6147dd71b94dba550527f8f9e9"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:ad7964545c603b34f54fb8c0c387c333b"><td class="memItemLeft" align="right" valign="top"><a id="ad7964545c603b34f54fb8c0c387c333b"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC13F_TCC0_WO3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 13)</td></tr>
|
||
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<tr class="separator:ad7964545c603b34f54fb8c0c387c333b"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a2fe547b96432ddefef5ef7da1e97b170"><td class="memItemLeft" align="right" valign="top"><a id="a2fe547b96432ddefef5ef7da1e97b170"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2fe547b96432ddefef5ef7da1e97b170">PIN_PC19F_TCC0_WO3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(83)</td></tr>
|
||
|
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<tr class="memdesc:a2fe547b96432ddefef5ef7da1e97b170"><td class="mdescLeft"> </td><td class="mdescRight">TCC0 signal: WO3 on PC19 mux F. <br /></td></tr>
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||
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<tr class="separator:a2fe547b96432ddefef5ef7da1e97b170"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a64edcc05b3f56f3fa5c2c16199b09bba"><td class="memItemLeft" align="right" valign="top"><a id="a64edcc05b3f56f3fa5c2c16199b09bba"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC19F_TCC0_WO3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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<tr class="separator:a64edcc05b3f56f3fa5c2c16199b09bba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7f49c1136c1858300b7ad8bff933ce23"><td class="memItemLeft" align="right" valign="top"><a id="a7f49c1136c1858300b7ad8bff933ce23"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC19F_TCC0_WO3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a2fe547b96432ddefef5ef7da1e97b170">PIN_PC19F_TCC0_WO3</a> << 16) | MUX_PC19F_TCC0_WO3)</td></tr>
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<tr class="separator:a7f49c1136c1858300b7ad8bff933ce23"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a31e78cdae4e2b9a13790db915065be60"><td class="memItemLeft" align="right" valign="top"><a id="a31e78cdae4e2b9a13790db915065be60"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC19F_TCC0_WO3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 19)</td></tr>
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<tr class="separator:a31e78cdae4e2b9a13790db915065be60"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae50242b252fbffc8f87d2715509e5bb0"><td class="memItemLeft" align="right" valign="top"><a id="ae50242b252fbffc8f87d2715509e5bb0"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae50242b252fbffc8f87d2715509e5bb0">PIN_PA16G_TCC0_WO4</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(16)</td></tr>
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||
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<tr class="memdesc:ae50242b252fbffc8f87d2715509e5bb0"><td class="mdescLeft"> </td><td class="mdescRight">TCC0 signal: WO4 on PA16 mux G. <br /></td></tr>
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<tr class="separator:ae50242b252fbffc8f87d2715509e5bb0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac78a93c4a94fc05269bd1d7f576ddde6"><td class="memItemLeft" align="right" valign="top"><a id="ac78a93c4a94fc05269bd1d7f576ddde6"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA16G_TCC0_WO4</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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<tr class="separator:ac78a93c4a94fc05269bd1d7f576ddde6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1365ccf1d09385e54bb372d581d128d9"><td class="memItemLeft" align="right" valign="top"><a id="a1365ccf1d09385e54bb372d581d128d9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA16G_TCC0_WO4</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ae50242b252fbffc8f87d2715509e5bb0">PIN_PA16G_TCC0_WO4</a> << 16) | MUX_PA16G_TCC0_WO4)</td></tr>
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<tr class="separator:a1365ccf1d09385e54bb372d581d128d9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a45b5f0d8a9650b6cb3964b9bb8ee9120"><td class="memItemLeft" align="right" valign="top"><a id="a45b5f0d8a9650b6cb3964b9bb8ee9120"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA16G_TCC0_WO4</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 16)</td></tr>
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||
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<tr class="separator:a45b5f0d8a9650b6cb3964b9bb8ee9120"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3e9a78573fd9db9a3c5d5c5304e57fe7"><td class="memItemLeft" align="right" valign="top"><a id="a3e9a78573fd9db9a3c5d5c5304e57fe7"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3e9a78573fd9db9a3c5d5c5304e57fe7">PIN_PB16G_TCC0_WO4</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(48)</td></tr>
|
||
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<tr class="memdesc:a3e9a78573fd9db9a3c5d5c5304e57fe7"><td class="mdescLeft"> </td><td class="mdescRight">TCC0 signal: WO4 on PB16 mux G. <br /></td></tr>
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<tr class="separator:a3e9a78573fd9db9a3c5d5c5304e57fe7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac077edfef7bbca682879058aaf54d775"><td class="memItemLeft" align="right" valign="top"><a id="ac077edfef7bbca682879058aaf54d775"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB16G_TCC0_WO4</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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<tr class="separator:ac077edfef7bbca682879058aaf54d775"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4fd936322ea6948b4e977da6ac697cd8"><td class="memItemLeft" align="right" valign="top"><a id="a4fd936322ea6948b4e977da6ac697cd8"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB16G_TCC0_WO4</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a3e9a78573fd9db9a3c5d5c5304e57fe7">PIN_PB16G_TCC0_WO4</a> << 16) | MUX_PB16G_TCC0_WO4)</td></tr>
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<tr class="separator:a4fd936322ea6948b4e977da6ac697cd8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6f57ca5f33ea72b55c3bf47af6634aa4"><td class="memItemLeft" align="right" valign="top"><a id="a6f57ca5f33ea72b55c3bf47af6634aa4"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB16G_TCC0_WO4</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 16)</td></tr>
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||
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<tr class="separator:a6f57ca5f33ea72b55c3bf47af6634aa4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a39092863d440aacb6bbc8639c23f134c"><td class="memItemLeft" align="right" valign="top"><a id="a39092863d440aacb6bbc8639c23f134c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a39092863d440aacb6bbc8639c23f134c">PIN_PB10F_TCC0_WO4</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(42)</td></tr>
|
||
|
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<tr class="memdesc:a39092863d440aacb6bbc8639c23f134c"><td class="mdescLeft"> </td><td class="mdescRight">TCC0 signal: WO4 on PB10 mux F. <br /></td></tr>
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||
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<tr class="separator:a39092863d440aacb6bbc8639c23f134c"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a5524ba865f435eabb164f36863efd7a9"><td class="memItemLeft" align="right" valign="top"><a id="a5524ba865f435eabb164f36863efd7a9"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB10F_TCC0_WO4</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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||
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<tr class="separator:a5524ba865f435eabb164f36863efd7a9"><td class="memSeparator" colspan="2"> </td></tr>
|
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<tr class="memitem:a4adf5b5d45905ac3f784baa4bac6949f"><td class="memItemLeft" align="right" valign="top"><a id="a4adf5b5d45905ac3f784baa4bac6949f"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB10F_TCC0_WO4</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a39092863d440aacb6bbc8639c23f134c">PIN_PB10F_TCC0_WO4</a> << 16) | MUX_PB10F_TCC0_WO4)</td></tr>
|
||
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<tr class="separator:a4adf5b5d45905ac3f784baa4bac6949f"><td class="memSeparator" colspan="2"> </td></tr>
|
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<tr class="memitem:a201f471863118f7f8efe8c0dbce424e4"><td class="memItemLeft" align="right" valign="top"><a id="a201f471863118f7f8efe8c0dbce424e4"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB10F_TCC0_WO4</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 10)</td></tr>
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||
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<tr class="separator:a201f471863118f7f8efe8c0dbce424e4"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a46190b2208f375c663b37bc37dcbdfcc"><td class="memItemLeft" align="right" valign="top"><a id="a46190b2208f375c663b37bc37dcbdfcc"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a46190b2208f375c663b37bc37dcbdfcc">PIN_PC14F_TCC0_WO4</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(78)</td></tr>
|
||
|
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<tr class="memdesc:a46190b2208f375c663b37bc37dcbdfcc"><td class="mdescLeft"> </td><td class="mdescRight">TCC0 signal: WO4 on PC14 mux F. <br /></td></tr>
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||
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<tr class="separator:a46190b2208f375c663b37bc37dcbdfcc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af837a6906507458406f193023ec3844a"><td class="memItemLeft" align="right" valign="top"><a id="af837a6906507458406f193023ec3844a"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC14F_TCC0_WO4</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
|
||
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<tr class="separator:af837a6906507458406f193023ec3844a"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a295b32ffc975a71ab16f19a02bf0b071"><td class="memItemLeft" align="right" valign="top"><a id="a295b32ffc975a71ab16f19a02bf0b071"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC14F_TCC0_WO4</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a46190b2208f375c663b37bc37dcbdfcc">PIN_PC14F_TCC0_WO4</a> << 16) | MUX_PC14F_TCC0_WO4)</td></tr>
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<tr class="separator:a295b32ffc975a71ab16f19a02bf0b071"><td class="memSeparator" colspan="2"> </td></tr>
|
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<tr class="memitem:a2407bd7249c31d5666573b9d4c1e3187"><td class="memItemLeft" align="right" valign="top"><a id="a2407bd7249c31d5666573b9d4c1e3187"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC14F_TCC0_WO4</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 14)</td></tr>
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||
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<tr class="separator:a2407bd7249c31d5666573b9d4c1e3187"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a6a91473ab529126eacf6a59913ae3a76"><td class="memItemLeft" align="right" valign="top"><a id="a6a91473ab529126eacf6a59913ae3a76"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6a91473ab529126eacf6a59913ae3a76">PIN_PC20F_TCC0_WO4</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(84)</td></tr>
|
||
|
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<tr class="memdesc:a6a91473ab529126eacf6a59913ae3a76"><td class="mdescLeft"> </td><td class="mdescRight">TCC0 signal: WO4 on PC20 mux F. <br /></td></tr>
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||
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<tr class="separator:a6a91473ab529126eacf6a59913ae3a76"><td class="memSeparator" colspan="2"> </td></tr>
|
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<tr class="memitem:a1c3e83745a4e9bfaa7ca6a6fa8f439cc"><td class="memItemLeft" align="right" valign="top"><a id="a1c3e83745a4e9bfaa7ca6a6fa8f439cc"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC20F_TCC0_WO4</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
|
||
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<tr class="separator:a1c3e83745a4e9bfaa7ca6a6fa8f439cc"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a9cb8ea29045df2da35a3e204da7a3fd0"><td class="memItemLeft" align="right" valign="top"><a id="a9cb8ea29045df2da35a3e204da7a3fd0"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC20F_TCC0_WO4</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a6a91473ab529126eacf6a59913ae3a76">PIN_PC20F_TCC0_WO4</a> << 16) | MUX_PC20F_TCC0_WO4)</td></tr>
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<tr class="separator:a9cb8ea29045df2da35a3e204da7a3fd0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac4418fc70307e1e211871921a577b41f"><td class="memItemLeft" align="right" valign="top"><a id="ac4418fc70307e1e211871921a577b41f"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC20F_TCC0_WO4</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 20)</td></tr>
|
||
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<tr class="separator:ac4418fc70307e1e211871921a577b41f"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a93942ed172fd0c8e8cbe233cca49c7ae"><td class="memItemLeft" align="right" valign="top"><a id="a93942ed172fd0c8e8cbe233cca49c7ae"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a93942ed172fd0c8e8cbe233cca49c7ae">PIN_PA17G_TCC0_WO5</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(17)</td></tr>
|
||
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<tr class="memdesc:a93942ed172fd0c8e8cbe233cca49c7ae"><td class="mdescLeft"> </td><td class="mdescRight">TCC0 signal: WO5 on PA17 mux G. <br /></td></tr>
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||
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<tr class="separator:a93942ed172fd0c8e8cbe233cca49c7ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac6f4cf9fbac54d6e4cf7d437fc360fd7"><td class="memItemLeft" align="right" valign="top"><a id="ac6f4cf9fbac54d6e4cf7d437fc360fd7"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA17G_TCC0_WO5</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
|
||
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<tr class="separator:ac6f4cf9fbac54d6e4cf7d437fc360fd7"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a64a51f2f33e321d8969974cb970f1162"><td class="memItemLeft" align="right" valign="top"><a id="a64a51f2f33e321d8969974cb970f1162"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA17G_TCC0_WO5</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a93942ed172fd0c8e8cbe233cca49c7ae">PIN_PA17G_TCC0_WO5</a> << 16) | MUX_PA17G_TCC0_WO5)</td></tr>
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<tr class="separator:a64a51f2f33e321d8969974cb970f1162"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5821791029a779e7bc84a8242d1b56d0"><td class="memItemLeft" align="right" valign="top"><a id="a5821791029a779e7bc84a8242d1b56d0"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA17G_TCC0_WO5</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 17)</td></tr>
|
||
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<tr class="separator:a5821791029a779e7bc84a8242d1b56d0"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a29e9e728fc3f3361eafff32f81910739"><td class="memItemLeft" align="right" valign="top"><a id="a29e9e728fc3f3361eafff32f81910739"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a29e9e728fc3f3361eafff32f81910739">PIN_PB17G_TCC0_WO5</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(49)</td></tr>
|
||
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<tr class="memdesc:a29e9e728fc3f3361eafff32f81910739"><td class="mdescLeft"> </td><td class="mdescRight">TCC0 signal: WO5 on PB17 mux G. <br /></td></tr>
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||
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<tr class="separator:a29e9e728fc3f3361eafff32f81910739"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a161e24a326ca381949ebd20f4ea61b01"><td class="memItemLeft" align="right" valign="top"><a id="a161e24a326ca381949ebd20f4ea61b01"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB17G_TCC0_WO5</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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||
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<tr class="separator:a161e24a326ca381949ebd20f4ea61b01"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7179e22839feea81931a0d6836a63254"><td class="memItemLeft" align="right" valign="top"><a id="a7179e22839feea81931a0d6836a63254"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB17G_TCC0_WO5</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a29e9e728fc3f3361eafff32f81910739">PIN_PB17G_TCC0_WO5</a> << 16) | MUX_PB17G_TCC0_WO5)</td></tr>
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<tr class="separator:a7179e22839feea81931a0d6836a63254"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a043fe6c287cf08153facc5520601a2c9"><td class="memItemLeft" align="right" valign="top"><a id="a043fe6c287cf08153facc5520601a2c9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB17G_TCC0_WO5</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 17)</td></tr>
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||
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<tr class="separator:a043fe6c287cf08153facc5520601a2c9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a53b3ae2877edaff5fdc3d34f8ebddab0"><td class="memItemLeft" align="right" valign="top"><a id="a53b3ae2877edaff5fdc3d34f8ebddab0"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a53b3ae2877edaff5fdc3d34f8ebddab0">PIN_PB11F_TCC0_WO5</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(43)</td></tr>
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||
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<tr class="memdesc:a53b3ae2877edaff5fdc3d34f8ebddab0"><td class="mdescLeft"> </td><td class="mdescRight">TCC0 signal: WO5 on PB11 mux F. <br /></td></tr>
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<tr class="separator:a53b3ae2877edaff5fdc3d34f8ebddab0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad5c8dd72fa5c0cc42431357e556d03ae"><td class="memItemLeft" align="right" valign="top"><a id="ad5c8dd72fa5c0cc42431357e556d03ae"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB11F_TCC0_WO5</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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<tr class="separator:ad5c8dd72fa5c0cc42431357e556d03ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3c7119dc1472b295fb6a5c7c062ff4cb"><td class="memItemLeft" align="right" valign="top"><a id="a3c7119dc1472b295fb6a5c7c062ff4cb"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB11F_TCC0_WO5</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a53b3ae2877edaff5fdc3d34f8ebddab0">PIN_PB11F_TCC0_WO5</a> << 16) | MUX_PB11F_TCC0_WO5)</td></tr>
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<tr class="separator:a3c7119dc1472b295fb6a5c7c062ff4cb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a47ecdd8c9f874d652eab4b6878ad5f5f"><td class="memItemLeft" align="right" valign="top"><a id="a47ecdd8c9f874d652eab4b6878ad5f5f"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB11F_TCC0_WO5</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 11)</td></tr>
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||
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<tr class="separator:a47ecdd8c9f874d652eab4b6878ad5f5f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa9885f60f08de80c908068a654bc7e91"><td class="memItemLeft" align="right" valign="top"><a id="aa9885f60f08de80c908068a654bc7e91"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa9885f60f08de80c908068a654bc7e91">PIN_PC15F_TCC0_WO5</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(79)</td></tr>
|
||
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<tr class="memdesc:aa9885f60f08de80c908068a654bc7e91"><td class="mdescLeft"> </td><td class="mdescRight">TCC0 signal: WO5 on PC15 mux F. <br /></td></tr>
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<tr class="separator:aa9885f60f08de80c908068a654bc7e91"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a20980283a2e646c2237b40cf958706c3"><td class="memItemLeft" align="right" valign="top"><a id="a20980283a2e646c2237b40cf958706c3"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC15F_TCC0_WO5</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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||
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<tr class="separator:a20980283a2e646c2237b40cf958706c3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a82ab8a5db1127d58381a42a7ac510a18"><td class="memItemLeft" align="right" valign="top"><a id="a82ab8a5db1127d58381a42a7ac510a18"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC15F_TCC0_WO5</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aa9885f60f08de80c908068a654bc7e91">PIN_PC15F_TCC0_WO5</a> << 16) | MUX_PC15F_TCC0_WO5)</td></tr>
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<tr class="separator:a82ab8a5db1127d58381a42a7ac510a18"><td class="memSeparator" colspan="2"> </td></tr>
|
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<tr class="memitem:a9cd2ab5dd9254f903147a3abac17d3e3"><td class="memItemLeft" align="right" valign="top"><a id="a9cd2ab5dd9254f903147a3abac17d3e3"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC15F_TCC0_WO5</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 15)</td></tr>
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||
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<tr class="separator:a9cd2ab5dd9254f903147a3abac17d3e3"><td class="memSeparator" colspan="2"> </td></tr>
|
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<tr class="memitem:a8b7983d112e62bf3ad40f6f63887f6c5"><td class="memItemLeft" align="right" valign="top"><a id="a8b7983d112e62bf3ad40f6f63887f6c5"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8b7983d112e62bf3ad40f6f63887f6c5">PIN_PC21F_TCC0_WO5</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(85)</td></tr>
|
||
|
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<tr class="memdesc:a8b7983d112e62bf3ad40f6f63887f6c5"><td class="mdescLeft"> </td><td class="mdescRight">TCC0 signal: WO5 on PC21 mux F. <br /></td></tr>
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||
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<tr class="separator:a8b7983d112e62bf3ad40f6f63887f6c5"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a027db322a087c263fcd868fdc2f8782b"><td class="memItemLeft" align="right" valign="top"><a id="a027db322a087c263fcd868fdc2f8782b"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC21F_TCC0_WO5</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
|
||
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<tr class="separator:a027db322a087c263fcd868fdc2f8782b"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a34f27c4007cb4e899b8fc410f99a90ec"><td class="memItemLeft" align="right" valign="top"><a id="a34f27c4007cb4e899b8fc410f99a90ec"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC21F_TCC0_WO5</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a8b7983d112e62bf3ad40f6f63887f6c5">PIN_PC21F_TCC0_WO5</a> << 16) | MUX_PC21F_TCC0_WO5)</td></tr>
|
||
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<tr class="separator:a34f27c4007cb4e899b8fc410f99a90ec"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:aa68ff25a9cb572273bacb14c4b156bee"><td class="memItemLeft" align="right" valign="top"><a id="aa68ff25a9cb572273bacb14c4b156bee"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC21F_TCC0_WO5</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 21)</td></tr>
|
||
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<tr class="separator:aa68ff25a9cb572273bacb14c4b156bee"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:ada6ef2e4e4def6c96f1b1108ce0f934c"><td class="memItemLeft" align="right" valign="top"><a id="ada6ef2e4e4def6c96f1b1108ce0f934c"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ada6ef2e4e4def6c96f1b1108ce0f934c">PIN_PA18G_TCC0_WO6</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(18)</td></tr>
|
||
|
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<tr class="memdesc:ada6ef2e4e4def6c96f1b1108ce0f934c"><td class="mdescLeft"> </td><td class="mdescRight">TCC0 signal: WO6 on PA18 mux G. <br /></td></tr>
|
||
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<tr class="separator:ada6ef2e4e4def6c96f1b1108ce0f934c"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:ac4eec5ee8095b2fc921ed57bb6a1abff"><td class="memItemLeft" align="right" valign="top"><a id="ac4eec5ee8095b2fc921ed57bb6a1abff"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA18G_TCC0_WO6</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
|
||
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<tr class="separator:ac4eec5ee8095b2fc921ed57bb6a1abff"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:ae598614bce03e10a72c00cf843ae3ec3"><td class="memItemLeft" align="right" valign="top"><a id="ae598614bce03e10a72c00cf843ae3ec3"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA18G_TCC0_WO6</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ada6ef2e4e4def6c96f1b1108ce0f934c">PIN_PA18G_TCC0_WO6</a> << 16) | MUX_PA18G_TCC0_WO6)</td></tr>
|
||
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<tr class="separator:ae598614bce03e10a72c00cf843ae3ec3"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:ab13516fbd7d0323e70955b09417ee7c6"><td class="memItemLeft" align="right" valign="top"><a id="ab13516fbd7d0323e70955b09417ee7c6"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA18G_TCC0_WO6</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 18)</td></tr>
|
||
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<tr class="separator:ab13516fbd7d0323e70955b09417ee7c6"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:a882b1b416376154d24e207f02b56d0e7"><td class="memItemLeft" align="right" valign="top"><a id="a882b1b416376154d24e207f02b56d0e7"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a882b1b416376154d24e207f02b56d0e7">PIN_PB30G_TCC0_WO6</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(62)</td></tr>
|
||
|
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<tr class="memdesc:a882b1b416376154d24e207f02b56d0e7"><td class="mdescLeft"> </td><td class="mdescRight">TCC0 signal: WO6 on PB30 mux G. <br /></td></tr>
|
||
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<tr class="separator:a882b1b416376154d24e207f02b56d0e7"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a6c7af913d6e383a73be55c6722a4ccdd"><td class="memItemLeft" align="right" valign="top"><a id="a6c7af913d6e383a73be55c6722a4ccdd"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB30G_TCC0_WO6</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
|
||
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<tr class="separator:a6c7af913d6e383a73be55c6722a4ccdd"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a0a50da7fa44f14bdbfac629e19fbea06"><td class="memItemLeft" align="right" valign="top"><a id="a0a50da7fa44f14bdbfac629e19fbea06"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB30G_TCC0_WO6</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a882b1b416376154d24e207f02b56d0e7">PIN_PB30G_TCC0_WO6</a> << 16) | MUX_PB30G_TCC0_WO6)</td></tr>
|
||
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<tr class="separator:a0a50da7fa44f14bdbfac629e19fbea06"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:aebf6ed1bbf5d345fc591da65dbe54130"><td class="memItemLeft" align="right" valign="top"><a id="aebf6ed1bbf5d345fc591da65dbe54130"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB30G_TCC0_WO6</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 30)</td></tr>
|
||
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<tr class="separator:aebf6ed1bbf5d345fc591da65dbe54130"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a809f70a2f3aa323f63066eac22b626d9"><td class="memItemLeft" align="right" valign="top"><a id="a809f70a2f3aa323f63066eac22b626d9"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a809f70a2f3aa323f63066eac22b626d9">PIN_PA12F_TCC0_WO6</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
|
||
|
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<tr class="memdesc:a809f70a2f3aa323f63066eac22b626d9"><td class="mdescLeft"> </td><td class="mdescRight">TCC0 signal: WO6 on PA12 mux F. <br /></td></tr>
|
||
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<tr class="separator:a809f70a2f3aa323f63066eac22b626d9"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a437f190be587d505138d43cd245d5106"><td class="memItemLeft" align="right" valign="top"><a id="a437f190be587d505138d43cd245d5106"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA12F_TCC0_WO6</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
|
||
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<tr class="separator:a437f190be587d505138d43cd245d5106"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a787437f0d37f0b792a1a21e6e934d7ab"><td class="memItemLeft" align="right" valign="top"><a id="a787437f0d37f0b792a1a21e6e934d7ab"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA12F_TCC0_WO6</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a809f70a2f3aa323f63066eac22b626d9">PIN_PA12F_TCC0_WO6</a> << 16) | MUX_PA12F_TCC0_WO6)</td></tr>
|
||
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<tr class="separator:a787437f0d37f0b792a1a21e6e934d7ab"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:af4220eb8410b2dc5c1413a056ae7525b"><td class="memItemLeft" align="right" valign="top"><a id="af4220eb8410b2dc5c1413a056ae7525b"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA12F_TCC0_WO6</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 12)</td></tr>
|
||
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<tr class="separator:af4220eb8410b2dc5c1413a056ae7525b"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:ac03791587b7a8e16bdf63fa7d217e3cb"><td class="memItemLeft" align="right" valign="top"><a id="ac03791587b7a8e16bdf63fa7d217e3cb"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac03791587b7a8e16bdf63fa7d217e3cb">PIN_PA19G_TCC0_WO7</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(19)</td></tr>
|
||
|
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<tr class="memdesc:ac03791587b7a8e16bdf63fa7d217e3cb"><td class="mdescLeft"> </td><td class="mdescRight">TCC0 signal: WO7 on PA19 mux G. <br /></td></tr>
|
||
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<tr class="separator:ac03791587b7a8e16bdf63fa7d217e3cb"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a6bc363d934f013d50e899767165139a9"><td class="memItemLeft" align="right" valign="top"><a id="a6bc363d934f013d50e899767165139a9"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA19G_TCC0_WO7</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
|
||
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<tr class="separator:a6bc363d934f013d50e899767165139a9"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a7cdfb56108aeff63f988649bb48e0a2b"><td class="memItemLeft" align="right" valign="top"><a id="a7cdfb56108aeff63f988649bb48e0a2b"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA19G_TCC0_WO7</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ac03791587b7a8e16bdf63fa7d217e3cb">PIN_PA19G_TCC0_WO7</a> << 16) | MUX_PA19G_TCC0_WO7)</td></tr>
|
||
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<tr class="separator:a7cdfb56108aeff63f988649bb48e0a2b"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:ae5e51be280bfcda29680892640ebcd72"><td class="memItemLeft" align="right" valign="top"><a id="ae5e51be280bfcda29680892640ebcd72"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA19G_TCC0_WO7</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 19)</td></tr>
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<tr class="separator:ae5e51be280bfcda29680892640ebcd72"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aca1f8264ff07ed2a77f3b89f7d000aef"><td class="memItemLeft" align="right" valign="top"><a id="aca1f8264ff07ed2a77f3b89f7d000aef"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aca1f8264ff07ed2a77f3b89f7d000aef">PIN_PB31G_TCC0_WO7</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(63)</td></tr>
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<tr class="memdesc:aca1f8264ff07ed2a77f3b89f7d000aef"><td class="mdescLeft"> </td><td class="mdescRight">TCC0 signal: WO7 on PB31 mux G. <br /></td></tr>
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<tr class="separator:aca1f8264ff07ed2a77f3b89f7d000aef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad76b1ba13833c667782aae7505047bef"><td class="memItemLeft" align="right" valign="top"><a id="ad76b1ba13833c667782aae7505047bef"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB31G_TCC0_WO7</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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<tr class="separator:ad76b1ba13833c667782aae7505047bef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a85ca0d99c5b9a267bfc3e31d3088574f"><td class="memItemLeft" align="right" valign="top"><a id="a85ca0d99c5b9a267bfc3e31d3088574f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB31G_TCC0_WO7</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aca1f8264ff07ed2a77f3b89f7d000aef">PIN_PB31G_TCC0_WO7</a> << 16) | MUX_PB31G_TCC0_WO7)</td></tr>
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<tr class="separator:a85ca0d99c5b9a267bfc3e31d3088574f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad69373dad9462c9f83ccce70ac62b6ac"><td class="memItemLeft" align="right" valign="top"><a id="ad69373dad9462c9f83ccce70ac62b6ac"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB31G_TCC0_WO7</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 31)</td></tr>
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||
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<tr class="separator:ad69373dad9462c9f83ccce70ac62b6ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a51c8872260371d9c285570be341f6bc2"><td class="memItemLeft" align="right" valign="top"><a id="a51c8872260371d9c285570be341f6bc2"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a51c8872260371d9c285570be341f6bc2">PIN_PA13F_TCC0_WO7</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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||
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<tr class="memdesc:a51c8872260371d9c285570be341f6bc2"><td class="mdescLeft"> </td><td class="mdescRight">TCC0 signal: WO7 on PA13 mux F. <br /></td></tr>
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<tr class="separator:a51c8872260371d9c285570be341f6bc2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a46f4897ee840d66d204aad5b6f9f92db"><td class="memItemLeft" align="right" valign="top"><a id="a46f4897ee840d66d204aad5b6f9f92db"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA13F_TCC0_WO7</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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<tr class="separator:a46f4897ee840d66d204aad5b6f9f92db"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad18957db9f1645d4b9e41cfe0e242068"><td class="memItemLeft" align="right" valign="top"><a id="ad18957db9f1645d4b9e41cfe0e242068"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA13F_TCC0_WO7</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a51c8872260371d9c285570be341f6bc2">PIN_PA13F_TCC0_WO7</a> << 16) | MUX_PA13F_TCC0_WO7)</td></tr>
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<tr class="separator:ad18957db9f1645d4b9e41cfe0e242068"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1acdf061adce4589adb52ec2ccf41e16"><td class="memItemLeft" align="right" valign="top"><a id="a1acdf061adce4589adb52ec2ccf41e16"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA13F_TCC0_WO7</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 13)</td></tr>
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||
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<tr class="separator:a1acdf061adce4589adb52ec2ccf41e16"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3894371599a07265b37600df157d1d49"><td class="memItemLeft" align="right" valign="top"><a id="a3894371599a07265b37600df157d1d49"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3894371599a07265b37600df157d1d49">PIN_PB10G_TCC1_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(42)</td></tr>
|
||
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<tr class="memdesc:a3894371599a07265b37600df157d1d49"><td class="mdescLeft"> </td><td class="mdescRight">TCC1 signal: WO0 on PB10 mux G. <br /></td></tr>
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<tr class="separator:a3894371599a07265b37600df157d1d49"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8bb39b073f4f5f75fa4929423fd66570"><td class="memItemLeft" align="right" valign="top"><a id="a8bb39b073f4f5f75fa4929423fd66570"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB10G_TCC1_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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||
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<tr class="separator:a8bb39b073f4f5f75fa4929423fd66570"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a95b2423652677e4c762653bfececea7e"><td class="memItemLeft" align="right" valign="top"><a id="a95b2423652677e4c762653bfececea7e"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB10G_TCC1_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a3894371599a07265b37600df157d1d49">PIN_PB10G_TCC1_WO0</a> << 16) | MUX_PB10G_TCC1_WO0)</td></tr>
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<tr class="separator:a95b2423652677e4c762653bfececea7e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a604bf69bf12ce7a4eb80680826faf7b6"><td class="memItemLeft" align="right" valign="top"><a id="a604bf69bf12ce7a4eb80680826faf7b6"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB10G_TCC1_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 10)</td></tr>
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||
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<tr class="separator:a604bf69bf12ce7a4eb80680826faf7b6"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a82aabf58d9a048b474d306bd3c7f0a13"><td class="memItemLeft" align="right" valign="top"><a id="a82aabf58d9a048b474d306bd3c7f0a13"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a82aabf58d9a048b474d306bd3c7f0a13">PIN_PC14G_TCC1_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(78)</td></tr>
|
||
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<tr class="memdesc:a82aabf58d9a048b474d306bd3c7f0a13"><td class="mdescLeft"> </td><td class="mdescRight">TCC1 signal: WO0 on PC14 mux G. <br /></td></tr>
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||
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<tr class="separator:a82aabf58d9a048b474d306bd3c7f0a13"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6dfc452ab9e8dff0ca062acd75eac81f"><td class="memItemLeft" align="right" valign="top"><a id="a6dfc452ab9e8dff0ca062acd75eac81f"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC14G_TCC1_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
|
||
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<tr class="separator:a6dfc452ab9e8dff0ca062acd75eac81f"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a49a5cee9968b0d11948ee85005001b70"><td class="memItemLeft" align="right" valign="top"><a id="a49a5cee9968b0d11948ee85005001b70"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC14G_TCC1_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a82aabf58d9a048b474d306bd3c7f0a13">PIN_PC14G_TCC1_WO0</a> << 16) | MUX_PC14G_TCC1_WO0)</td></tr>
|
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<tr class="separator:a49a5cee9968b0d11948ee85005001b70"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3e35b2a40b187215cd19de99e28274be"><td class="memItemLeft" align="right" valign="top"><a id="a3e35b2a40b187215cd19de99e28274be"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC14G_TCC1_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 14)</td></tr>
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||
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<tr class="separator:a3e35b2a40b187215cd19de99e28274be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a31611c15d2aac8e9dc9459123e5567df"><td class="memItemLeft" align="right" valign="top"><a id="a31611c15d2aac8e9dc9459123e5567df"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a31611c15d2aac8e9dc9459123e5567df">PIN_PA16F_TCC1_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(16)</td></tr>
|
||
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<tr class="memdesc:a31611c15d2aac8e9dc9459123e5567df"><td class="mdescLeft"> </td><td class="mdescRight">TCC1 signal: WO0 on PA16 mux F. <br /></td></tr>
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||
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<tr class="separator:a31611c15d2aac8e9dc9459123e5567df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afb669426acedce77c2f414eb920e49d4"><td class="memItemLeft" align="right" valign="top"><a id="afb669426acedce77c2f414eb920e49d4"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA16F_TCC1_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
|
||
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<tr class="separator:afb669426acedce77c2f414eb920e49d4"><td class="memSeparator" colspan="2"> </td></tr>
|
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<tr class="memitem:a48f454cfc9b7735ee70025ede5fa5c3b"><td class="memItemLeft" align="right" valign="top"><a id="a48f454cfc9b7735ee70025ede5fa5c3b"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA16F_TCC1_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a31611c15d2aac8e9dc9459123e5567df">PIN_PA16F_TCC1_WO0</a> << 16) | MUX_PA16F_TCC1_WO0)</td></tr>
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<tr class="separator:a48f454cfc9b7735ee70025ede5fa5c3b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a96a6ccf57ac0f5da212828a423d837a8"><td class="memItemLeft" align="right" valign="top"><a id="a96a6ccf57ac0f5da212828a423d837a8"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA16F_TCC1_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 16)</td></tr>
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||
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<tr class="separator:a96a6ccf57ac0f5da212828a423d837a8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5669aa6b3cdffd5151dca255e3ad25b3"><td class="memItemLeft" align="right" valign="top"><a id="a5669aa6b3cdffd5151dca255e3ad25b3"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5669aa6b3cdffd5151dca255e3ad25b3">PIN_PB18F_TCC1_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(50)</td></tr>
|
||
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<tr class="memdesc:a5669aa6b3cdffd5151dca255e3ad25b3"><td class="mdescLeft"> </td><td class="mdescRight">TCC1 signal: WO0 on PB18 mux F. <br /></td></tr>
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<tr class="separator:a5669aa6b3cdffd5151dca255e3ad25b3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa97ed0edb35a384120cbe2f69931ec63"><td class="memItemLeft" align="right" valign="top"><a id="aa97ed0edb35a384120cbe2f69931ec63"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB18F_TCC1_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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||
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<tr class="separator:aa97ed0edb35a384120cbe2f69931ec63"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aad28226279fdbc7887d3c8408b5d672e"><td class="memItemLeft" align="right" valign="top"><a id="aad28226279fdbc7887d3c8408b5d672e"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB18F_TCC1_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a5669aa6b3cdffd5151dca255e3ad25b3">PIN_PB18F_TCC1_WO0</a> << 16) | MUX_PB18F_TCC1_WO0)</td></tr>
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<tr class="separator:aad28226279fdbc7887d3c8408b5d672e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af539a162ca06cce63aa0f2e8876c577a"><td class="memItemLeft" align="right" valign="top"><a id="af539a162ca06cce63aa0f2e8876c577a"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB18F_TCC1_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 18)</td></tr>
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||
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<tr class="separator:af539a162ca06cce63aa0f2e8876c577a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8e4547dd54f9ab97b5b9057442170540"><td class="memItemLeft" align="right" valign="top"><a id="a8e4547dd54f9ab97b5b9057442170540"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8e4547dd54f9ab97b5b9057442170540">PIN_PB11G_TCC1_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(43)</td></tr>
|
||
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<tr class="memdesc:a8e4547dd54f9ab97b5b9057442170540"><td class="mdescLeft"> </td><td class="mdescRight">TCC1 signal: WO1 on PB11 mux G. <br /></td></tr>
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<tr class="separator:a8e4547dd54f9ab97b5b9057442170540"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad4a801ac12512cea131058a77b245575"><td class="memItemLeft" align="right" valign="top"><a id="ad4a801ac12512cea131058a77b245575"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB11G_TCC1_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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||
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<tr class="separator:ad4a801ac12512cea131058a77b245575"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6cf751d76d2b653734f7945d5ac8d2eb"><td class="memItemLeft" align="right" valign="top"><a id="a6cf751d76d2b653734f7945d5ac8d2eb"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB11G_TCC1_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a8e4547dd54f9ab97b5b9057442170540">PIN_PB11G_TCC1_WO1</a> << 16) | MUX_PB11G_TCC1_WO1)</td></tr>
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<tr class="separator:a6cf751d76d2b653734f7945d5ac8d2eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0a48da6b6a879a14db44fc68e1fe9e3a"><td class="memItemLeft" align="right" valign="top"><a id="a0a48da6b6a879a14db44fc68e1fe9e3a"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB11G_TCC1_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 11)</td></tr>
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||
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<tr class="separator:a0a48da6b6a879a14db44fc68e1fe9e3a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2fb8a8cc8d8886a6b688a8ea597ad112"><td class="memItemLeft" align="right" valign="top"><a id="a2fb8a8cc8d8886a6b688a8ea597ad112"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2fb8a8cc8d8886a6b688a8ea597ad112">PIN_PC15G_TCC1_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(79)</td></tr>
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<tr class="memdesc:a2fb8a8cc8d8886a6b688a8ea597ad112"><td class="mdescLeft"> </td><td class="mdescRight">TCC1 signal: WO1 on PC15 mux G. <br /></td></tr>
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<tr class="memitem:adb7423a996fbec6aea5b514d7cd50a9d"><td class="memItemLeft" align="right" valign="top"><a id="adb7423a996fbec6aea5b514d7cd50a9d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC15G_TCC1_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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<tr class="separator:adb7423a996fbec6aea5b514d7cd50a9d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab9fee9bfd4c8224f8673e51c865be7f2"><td class="memItemLeft" align="right" valign="top"><a id="ab9fee9bfd4c8224f8673e51c865be7f2"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC15G_TCC1_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a2fb8a8cc8d8886a6b688a8ea597ad112">PIN_PC15G_TCC1_WO1</a> << 16) | MUX_PC15G_TCC1_WO1)</td></tr>
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<tr class="separator:ab9fee9bfd4c8224f8673e51c865be7f2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af610d9b9ea5b3e6db80785f7ae235b75"><td class="memItemLeft" align="right" valign="top"><a id="af610d9b9ea5b3e6db80785f7ae235b75"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC15G_TCC1_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 15)</td></tr>
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<tr class="separator:af610d9b9ea5b3e6db80785f7ae235b75"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa42a8593f2233adb8b91b85272c4051d"><td class="memItemLeft" align="right" valign="top"><a id="aa42a8593f2233adb8b91b85272c4051d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa42a8593f2233adb8b91b85272c4051d">PIN_PA17F_TCC1_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(17)</td></tr>
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<tr class="memdesc:aa42a8593f2233adb8b91b85272c4051d"><td class="mdescLeft"> </td><td class="mdescRight">TCC1 signal: WO1 on PA17 mux F. <br /></td></tr>
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<tr class="separator:aa42a8593f2233adb8b91b85272c4051d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae3115ae4dc2401e0ff6245a0b308f8f0"><td class="memItemLeft" align="right" valign="top"><a id="ae3115ae4dc2401e0ff6245a0b308f8f0"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA17F_TCC1_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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<tr class="separator:ae3115ae4dc2401e0ff6245a0b308f8f0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3547ea399a98ff0bdf42f080f3e13006"><td class="memItemLeft" align="right" valign="top"><a id="a3547ea399a98ff0bdf42f080f3e13006"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA17F_TCC1_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aa42a8593f2233adb8b91b85272c4051d">PIN_PA17F_TCC1_WO1</a> << 16) | MUX_PA17F_TCC1_WO1)</td></tr>
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<tr class="separator:a3547ea399a98ff0bdf42f080f3e13006"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adda0c9fbd8d1fd5662a216b9efcacc4f"><td class="memItemLeft" align="right" valign="top"><a id="adda0c9fbd8d1fd5662a216b9efcacc4f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA17F_TCC1_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 17)</td></tr>
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<tr class="separator:adda0c9fbd8d1fd5662a216b9efcacc4f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a91769fd831aced51b7bc7f2c931a16d6"><td class="memItemLeft" align="right" valign="top"><a id="a91769fd831aced51b7bc7f2c931a16d6"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a91769fd831aced51b7bc7f2c931a16d6">PIN_PB19F_TCC1_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(51)</td></tr>
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<tr class="memdesc:a91769fd831aced51b7bc7f2c931a16d6"><td class="mdescLeft"> </td><td class="mdescRight">TCC1 signal: WO1 on PB19 mux F. <br /></td></tr>
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<tr class="separator:a91769fd831aced51b7bc7f2c931a16d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2f4cc7fd109075d03a567aa015a0209f"><td class="memItemLeft" align="right" valign="top"><a id="a2f4cc7fd109075d03a567aa015a0209f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB19F_TCC1_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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<tr class="separator:a2f4cc7fd109075d03a567aa015a0209f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0fa254bb67cae0be3c5983607ead78ee"><td class="memItemLeft" align="right" valign="top"><a id="a0fa254bb67cae0be3c5983607ead78ee"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB19F_TCC1_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a91769fd831aced51b7bc7f2c931a16d6">PIN_PB19F_TCC1_WO1</a> << 16) | MUX_PB19F_TCC1_WO1)</td></tr>
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<tr class="separator:a0fa254bb67cae0be3c5983607ead78ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a606a781295cc5b28d5e60b9f6f54e5be"><td class="memItemLeft" align="right" valign="top"><a id="a606a781295cc5b28d5e60b9f6f54e5be"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB19F_TCC1_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 19)</td></tr>
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<tr class="separator:a606a781295cc5b28d5e60b9f6f54e5be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6cb1ea1431c1af56edd96f2f70e517a3"><td class="memItemLeft" align="right" valign="top"><a id="a6cb1ea1431c1af56edd96f2f70e517a3"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6cb1ea1431c1af56edd96f2f70e517a3">PIN_PA12G_TCC1_WO2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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<tr class="memdesc:a6cb1ea1431c1af56edd96f2f70e517a3"><td class="mdescLeft"> </td><td class="mdescRight">TCC1 signal: WO2 on PA12 mux G. <br /></td></tr>
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<tr class="separator:a6cb1ea1431c1af56edd96f2f70e517a3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a71a311199971b833586ae86b512e2973"><td class="memItemLeft" align="right" valign="top"><a id="a71a311199971b833586ae86b512e2973"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA12G_TCC1_WO2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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<tr class="separator:a71a311199971b833586ae86b512e2973"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ade48861a55b56dda193331f56b644e89"><td class="memItemLeft" align="right" valign="top"><a id="ade48861a55b56dda193331f56b644e89"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA12G_TCC1_WO2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a6cb1ea1431c1af56edd96f2f70e517a3">PIN_PA12G_TCC1_WO2</a> << 16) | MUX_PA12G_TCC1_WO2)</td></tr>
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<tr class="separator:ade48861a55b56dda193331f56b644e89"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa667d1e8c5caf7d3b5d7498902b8a6fb"><td class="memItemLeft" align="right" valign="top"><a id="aa667d1e8c5caf7d3b5d7498902b8a6fb"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA12G_TCC1_WO2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 12)</td></tr>
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<tr class="separator:aa667d1e8c5caf7d3b5d7498902b8a6fb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a72f18803bcfe991b76bd7796818b2bdb"><td class="memItemLeft" align="right" valign="top"><a id="a72f18803bcfe991b76bd7796818b2bdb"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a72f18803bcfe991b76bd7796818b2bdb">PIN_PA14G_TCC1_WO2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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||
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<tr class="memdesc:a72f18803bcfe991b76bd7796818b2bdb"><td class="mdescLeft"> </td><td class="mdescRight">TCC1 signal: WO2 on PA14 mux G. <br /></td></tr>
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<tr class="separator:a72f18803bcfe991b76bd7796818b2bdb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afa4ae85097449ce3ed17a06781bb4dd0"><td class="memItemLeft" align="right" valign="top"><a id="afa4ae85097449ce3ed17a06781bb4dd0"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA14G_TCC1_WO2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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<tr class="separator:afa4ae85097449ce3ed17a06781bb4dd0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad0b5e37c43e5a94858e51dbdf871440a"><td class="memItemLeft" align="right" valign="top"><a id="ad0b5e37c43e5a94858e51dbdf871440a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA14G_TCC1_WO2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a72f18803bcfe991b76bd7796818b2bdb">PIN_PA14G_TCC1_WO2</a> << 16) | MUX_PA14G_TCC1_WO2)</td></tr>
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<tr class="separator:ad0b5e37c43e5a94858e51dbdf871440a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6762439d5f9cc01441277483a7335544"><td class="memItemLeft" align="right" valign="top"><a id="a6762439d5f9cc01441277483a7335544"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA14G_TCC1_WO2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 14)</td></tr>
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<tr class="separator:a6762439d5f9cc01441277483a7335544"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a43238670ea540fb013e9d1f3235401bc"><td class="memItemLeft" align="right" valign="top"><a id="a43238670ea540fb013e9d1f3235401bc"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a43238670ea540fb013e9d1f3235401bc">PIN_PA18F_TCC1_WO2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(18)</td></tr>
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||
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<tr class="memdesc:a43238670ea540fb013e9d1f3235401bc"><td class="mdescLeft"> </td><td class="mdescRight">TCC1 signal: WO2 on PA18 mux F. <br /></td></tr>
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<tr class="separator:a43238670ea540fb013e9d1f3235401bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abbb6e62d4867cccd22374201fc8f580e"><td class="memItemLeft" align="right" valign="top"><a id="abbb6e62d4867cccd22374201fc8f580e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA18F_TCC1_WO2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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<tr class="separator:abbb6e62d4867cccd22374201fc8f580e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa01937695a76025520cca3f5ec94ab2d"><td class="memItemLeft" align="right" valign="top"><a id="aa01937695a76025520cca3f5ec94ab2d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA18F_TCC1_WO2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a43238670ea540fb013e9d1f3235401bc">PIN_PA18F_TCC1_WO2</a> << 16) | MUX_PA18F_TCC1_WO2)</td></tr>
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<tr class="separator:aa01937695a76025520cca3f5ec94ab2d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6f1560a3bd2708ccb9c6fa4a94cdee45"><td class="memItemLeft" align="right" valign="top"><a id="a6f1560a3bd2708ccb9c6fa4a94cdee45"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA18F_TCC1_WO2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 18)</td></tr>
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<tr class="separator:a6f1560a3bd2708ccb9c6fa4a94cdee45"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a60770bf3d3cbdecf6ce2743a62875a83"><td class="memItemLeft" align="right" valign="top"><a id="a60770bf3d3cbdecf6ce2743a62875a83"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a60770bf3d3cbdecf6ce2743a62875a83">PIN_PB20F_TCC1_WO2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(52)</td></tr>
|
||
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<tr class="memdesc:a60770bf3d3cbdecf6ce2743a62875a83"><td class="mdescLeft"> </td><td class="mdescRight">TCC1 signal: WO2 on PB20 mux F. <br /></td></tr>
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<tr class="separator:a60770bf3d3cbdecf6ce2743a62875a83"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a773f46de6d834448c63a5cfaa8805572"><td class="memItemLeft" align="right" valign="top"><a id="a773f46de6d834448c63a5cfaa8805572"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB20F_TCC1_WO2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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<tr class="separator:a773f46de6d834448c63a5cfaa8805572"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac86cf19f04e97068f9e3f892f0e0547f"><td class="memItemLeft" align="right" valign="top"><a id="ac86cf19f04e97068f9e3f892f0e0547f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB20F_TCC1_WO2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a60770bf3d3cbdecf6ce2743a62875a83">PIN_PB20F_TCC1_WO2</a> << 16) | MUX_PB20F_TCC1_WO2)</td></tr>
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<tr class="separator:ac86cf19f04e97068f9e3f892f0e0547f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad8d9064eaeced648a6f8aa420fdb1e22"><td class="memItemLeft" align="right" valign="top"><a id="ad8d9064eaeced648a6f8aa420fdb1e22"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB20F_TCC1_WO2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 20)</td></tr>
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<tr class="separator:ad8d9064eaeced648a6f8aa420fdb1e22"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2f32f7220f69342cfd259de16180d3e7"><td class="memItemLeft" align="right" valign="top"><a id="a2f32f7220f69342cfd259de16180d3e7"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2f32f7220f69342cfd259de16180d3e7">PIN_PA13G_TCC1_WO3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
|
||
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<tr class="memdesc:a2f32f7220f69342cfd259de16180d3e7"><td class="mdescLeft"> </td><td class="mdescRight">TCC1 signal: WO3 on PA13 mux G. <br /></td></tr>
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<tr class="separator:a2f32f7220f69342cfd259de16180d3e7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af38d94472b9355a4d4bde35eca589024"><td class="memItemLeft" align="right" valign="top"><a id="af38d94472b9355a4d4bde35eca589024"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA13G_TCC1_WO3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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<tr class="memitem:aa816e4aac59ccc3e83e9a306c3aad089"><td class="memItemLeft" align="right" valign="top"><a id="aa816e4aac59ccc3e83e9a306c3aad089"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA13G_TCC1_WO3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a2f32f7220f69342cfd259de16180d3e7">PIN_PA13G_TCC1_WO3</a> << 16) | MUX_PA13G_TCC1_WO3)</td></tr>
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<tr class="separator:aa816e4aac59ccc3e83e9a306c3aad089"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a097fcfe5fe127d6126c21a6ccfb77827"><td class="memItemLeft" align="right" valign="top"><a id="a097fcfe5fe127d6126c21a6ccfb77827"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA13G_TCC1_WO3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 13)</td></tr>
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<tr class="separator:a097fcfe5fe127d6126c21a6ccfb77827"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4ecd9621ad04db21bd4f4ddbb96eab35"><td class="memItemLeft" align="right" valign="top"><a id="a4ecd9621ad04db21bd4f4ddbb96eab35"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4ecd9621ad04db21bd4f4ddbb96eab35">PIN_PA15G_TCC1_WO3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(15)</td></tr>
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<tr class="memdesc:a4ecd9621ad04db21bd4f4ddbb96eab35"><td class="mdescLeft"> </td><td class="mdescRight">TCC1 signal: WO3 on PA15 mux G. <br /></td></tr>
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<tr class="separator:a4ecd9621ad04db21bd4f4ddbb96eab35"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a58c507a535621d78df2c18217eef8d8f"><td class="memItemLeft" align="right" valign="top"><a id="a58c507a535621d78df2c18217eef8d8f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA15G_TCC1_WO3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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<tr class="separator:a58c507a535621d78df2c18217eef8d8f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a913964fdf8b1f625cea8f898d885cb2b"><td class="memItemLeft" align="right" valign="top"><a id="a913964fdf8b1f625cea8f898d885cb2b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA15G_TCC1_WO3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a4ecd9621ad04db21bd4f4ddbb96eab35">PIN_PA15G_TCC1_WO3</a> << 16) | MUX_PA15G_TCC1_WO3)</td></tr>
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<tr class="separator:a913964fdf8b1f625cea8f898d885cb2b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a70e05d5130188c42c01a28c510e09106"><td class="memItemLeft" align="right" valign="top"><a id="a70e05d5130188c42c01a28c510e09106"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA15G_TCC1_WO3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 15)</td></tr>
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<tr class="separator:a70e05d5130188c42c01a28c510e09106"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad69cf734b6bdef0e9edab0eac14156b7"><td class="memItemLeft" align="right" valign="top"><a id="ad69cf734b6bdef0e9edab0eac14156b7"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad69cf734b6bdef0e9edab0eac14156b7">PIN_PA19F_TCC1_WO3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(19)</td></tr>
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<tr class="memdesc:ad69cf734b6bdef0e9edab0eac14156b7"><td class="mdescLeft"> </td><td class="mdescRight">TCC1 signal: WO3 on PA19 mux F. <br /></td></tr>
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<tr class="separator:ad69cf734b6bdef0e9edab0eac14156b7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9931ab45dce039d11e30ff1f48e6abc5"><td class="memItemLeft" align="right" valign="top"><a id="a9931ab45dce039d11e30ff1f48e6abc5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA19F_TCC1_WO3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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<tr class="separator:a9931ab45dce039d11e30ff1f48e6abc5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a82a61fb9341b26966608e74a047d15cd"><td class="memItemLeft" align="right" valign="top"><a id="a82a61fb9341b26966608e74a047d15cd"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA19F_TCC1_WO3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ad69cf734b6bdef0e9edab0eac14156b7">PIN_PA19F_TCC1_WO3</a> << 16) | MUX_PA19F_TCC1_WO3)</td></tr>
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<tr class="separator:a82a61fb9341b26966608e74a047d15cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aca260836cf87fde25df7c82d3e8af2f1"><td class="memItemLeft" align="right" valign="top"><a id="aca260836cf87fde25df7c82d3e8af2f1"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA19F_TCC1_WO3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 19)</td></tr>
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<tr class="separator:aca260836cf87fde25df7c82d3e8af2f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af12e704c23f113594a0d323e035ce3df"><td class="memItemLeft" align="right" valign="top"><a id="af12e704c23f113594a0d323e035ce3df"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af12e704c23f113594a0d323e035ce3df">PIN_PB21F_TCC1_WO3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(53)</td></tr>
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<tr class="memdesc:af12e704c23f113594a0d323e035ce3df"><td class="mdescLeft"> </td><td class="mdescRight">TCC1 signal: WO3 on PB21 mux F. <br /></td></tr>
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<tr class="separator:af12e704c23f113594a0d323e035ce3df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a10b1901d48e862bcc0699673f98ea288"><td class="memItemLeft" align="right" valign="top"><a id="a10b1901d48e862bcc0699673f98ea288"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB21F_TCC1_WO3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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<tr class="separator:a10b1901d48e862bcc0699673f98ea288"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a94d21149caebba79d6226fbc55c51b04"><td class="memItemLeft" align="right" valign="top"><a id="a94d21149caebba79d6226fbc55c51b04"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB21F_TCC1_WO3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#af12e704c23f113594a0d323e035ce3df">PIN_PB21F_TCC1_WO3</a> << 16) | MUX_PB21F_TCC1_WO3)</td></tr>
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<tr class="separator:a94d21149caebba79d6226fbc55c51b04"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab75dffaca3ce251475bffde540423d90"><td class="memItemLeft" align="right" valign="top"><a id="ab75dffaca3ce251475bffde540423d90"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB21F_TCC1_WO3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 21)</td></tr>
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||
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<tr class="separator:ab75dffaca3ce251475bffde540423d90"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aad716983261739485a92fb5e554befcf"><td class="memItemLeft" align="right" valign="top"><a id="aad716983261739485a92fb5e554befcf"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aad716983261739485a92fb5e554befcf">PIN_PA08G_TCC1_WO4</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
|
||
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<tr class="memdesc:aad716983261739485a92fb5e554befcf"><td class="mdescLeft"> </td><td class="mdescRight">TCC1 signal: WO4 on PA08 mux G. <br /></td></tr>
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<tr class="separator:aad716983261739485a92fb5e554befcf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae93805f012e8d3c651f085136c6b7a7c"><td class="memItemLeft" align="right" valign="top"><a id="ae93805f012e8d3c651f085136c6b7a7c"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA08G_TCC1_WO4</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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<tr class="separator:ae93805f012e8d3c651f085136c6b7a7c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9130ba97521898a11cfe6de628625664"><td class="memItemLeft" align="right" valign="top"><a id="a9130ba97521898a11cfe6de628625664"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA08G_TCC1_WO4</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aad716983261739485a92fb5e554befcf">PIN_PA08G_TCC1_WO4</a> << 16) | MUX_PA08G_TCC1_WO4)</td></tr>
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<tr class="separator:a9130ba97521898a11cfe6de628625664"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a838408415c19b8d154a8f1d98d808c8a"><td class="memItemLeft" align="right" valign="top"><a id="a838408415c19b8d154a8f1d98d808c8a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA08G_TCC1_WO4</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 8)</td></tr>
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<tr class="separator:a838408415c19b8d154a8f1d98d808c8a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7bceef27f65e38d27ddb39710633de66"><td class="memItemLeft" align="right" valign="top"><a id="a7bceef27f65e38d27ddb39710633de66"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7bceef27f65e38d27ddb39710633de66">PIN_PC10G_TCC1_WO4</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(74)</td></tr>
|
||
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<tr class="memdesc:a7bceef27f65e38d27ddb39710633de66"><td class="mdescLeft"> </td><td class="mdescRight">TCC1 signal: WO4 on PC10 mux G. <br /></td></tr>
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<tr class="separator:a7bceef27f65e38d27ddb39710633de66"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae0eb2b862b74eb4856f6af2fd946dfbf"><td class="memItemLeft" align="right" valign="top"><a id="ae0eb2b862b74eb4856f6af2fd946dfbf"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC10G_TCC1_WO4</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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<tr class="separator:ae0eb2b862b74eb4856f6af2fd946dfbf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aba206630d923ad99af78edf51e58cda6"><td class="memItemLeft" align="right" valign="top"><a id="aba206630d923ad99af78edf51e58cda6"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC10G_TCC1_WO4</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a7bceef27f65e38d27ddb39710633de66">PIN_PC10G_TCC1_WO4</a> << 16) | MUX_PC10G_TCC1_WO4)</td></tr>
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<tr class="separator:aba206630d923ad99af78edf51e58cda6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa7aeb68727a2338755d856158c38ba86"><td class="memItemLeft" align="right" valign="top"><a id="aa7aeb68727a2338755d856158c38ba86"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC10G_TCC1_WO4</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 10)</td></tr>
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||
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<tr class="separator:aa7aeb68727a2338755d856158c38ba86"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aab44949b2d8566e58368729075bfd9e3"><td class="memItemLeft" align="right" valign="top"><a id="aab44949b2d8566e58368729075bfd9e3"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aab44949b2d8566e58368729075bfd9e3">PIN_PA20F_TCC1_WO4</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(20)</td></tr>
|
||
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<tr class="memdesc:aab44949b2d8566e58368729075bfd9e3"><td class="mdescLeft"> </td><td class="mdescRight">TCC1 signal: WO4 on PA20 mux F. <br /></td></tr>
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<tr class="separator:aab44949b2d8566e58368729075bfd9e3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab54a1a409c119d14601e6cef72d8bfd1"><td class="memItemLeft" align="right" valign="top"><a id="ab54a1a409c119d14601e6cef72d8bfd1"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA20F_TCC1_WO4</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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<tr class="separator:ab54a1a409c119d14601e6cef72d8bfd1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9debc156398b97af745c6bfd4af5cb2a"><td class="memItemLeft" align="right" valign="top"><a id="a9debc156398b97af745c6bfd4af5cb2a"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA20F_TCC1_WO4</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aab44949b2d8566e58368729075bfd9e3">PIN_PA20F_TCC1_WO4</a> << 16) | MUX_PA20F_TCC1_WO4)</td></tr>
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<tr class="separator:a9debc156398b97af745c6bfd4af5cb2a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9cb4fafafdb12ad4d00f9ac4d0a334b6"><td class="memItemLeft" align="right" valign="top"><a id="a9cb4fafafdb12ad4d00f9ac4d0a334b6"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA20F_TCC1_WO4</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 20)</td></tr>
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||
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<tr class="separator:a9cb4fafafdb12ad4d00f9ac4d0a334b6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2fefa33580727587333b52f159af7556"><td class="memItemLeft" align="right" valign="top"><a id="a2fefa33580727587333b52f159af7556"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2fefa33580727587333b52f159af7556">PIN_PA09G_TCC1_WO5</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
|
||
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<tr class="memdesc:a2fefa33580727587333b52f159af7556"><td class="mdescLeft"> </td><td class="mdescRight">TCC1 signal: WO5 on PA09 mux G. <br /></td></tr>
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<tr class="separator:a2fefa33580727587333b52f159af7556"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac83c5b9af2d912deb13f3ece5964a695"><td class="memItemLeft" align="right" valign="top"><a id="ac83c5b9af2d912deb13f3ece5964a695"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA09G_TCC1_WO5</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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<tr class="separator:ac83c5b9af2d912deb13f3ece5964a695"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab52c0bab470e17080f2ca119411800e2"><td class="memItemLeft" align="right" valign="top"><a id="ab52c0bab470e17080f2ca119411800e2"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA09G_TCC1_WO5</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a2fefa33580727587333b52f159af7556">PIN_PA09G_TCC1_WO5</a> << 16) | MUX_PA09G_TCC1_WO5)</td></tr>
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<tr class="separator:ab52c0bab470e17080f2ca119411800e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4bb476fc127006e953f47eabedbd2529"><td class="memItemLeft" align="right" valign="top"><a id="a4bb476fc127006e953f47eabedbd2529"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA09G_TCC1_WO5</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 9)</td></tr>
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<tr class="separator:a4bb476fc127006e953f47eabedbd2529"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab4a2fd55ec4b67b41d9801c71279fbc6"><td class="memItemLeft" align="right" valign="top"><a id="ab4a2fd55ec4b67b41d9801c71279fbc6"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab4a2fd55ec4b67b41d9801c71279fbc6">PIN_PC11G_TCC1_WO5</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(75)</td></tr>
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<tr class="memdesc:ab4a2fd55ec4b67b41d9801c71279fbc6"><td class="mdescLeft"> </td><td class="mdescRight">TCC1 signal: WO5 on PC11 mux G. <br /></td></tr>
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<tr class="separator:ab4a2fd55ec4b67b41d9801c71279fbc6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a85a1efdb24978c5bb8b1526c42a34fd8"><td class="memItemLeft" align="right" valign="top"><a id="a85a1efdb24978c5bb8b1526c42a34fd8"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC11G_TCC1_WO5</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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<tr class="separator:a85a1efdb24978c5bb8b1526c42a34fd8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad62c04c29f8d8a19e5c9f56a513e4dd4"><td class="memItemLeft" align="right" valign="top"><a id="ad62c04c29f8d8a19e5c9f56a513e4dd4"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC11G_TCC1_WO5</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ab4a2fd55ec4b67b41d9801c71279fbc6">PIN_PC11G_TCC1_WO5</a> << 16) | MUX_PC11G_TCC1_WO5)</td></tr>
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<tr class="separator:ad62c04c29f8d8a19e5c9f56a513e4dd4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adf345651a25346de4ecb55233012b6a2"><td class="memItemLeft" align="right" valign="top"><a id="adf345651a25346de4ecb55233012b6a2"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC11G_TCC1_WO5</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 11)</td></tr>
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<tr class="separator:adf345651a25346de4ecb55233012b6a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad828de97f945f3acfc68a0a616433d3e"><td class="memItemLeft" align="right" valign="top"><a id="ad828de97f945f3acfc68a0a616433d3e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad828de97f945f3acfc68a0a616433d3e">PIN_PA21F_TCC1_WO5</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(21)</td></tr>
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||
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<tr class="memdesc:ad828de97f945f3acfc68a0a616433d3e"><td class="mdescLeft"> </td><td class="mdescRight">TCC1 signal: WO5 on PA21 mux F. <br /></td></tr>
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<tr class="separator:ad828de97f945f3acfc68a0a616433d3e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af7075aac264713e2f46786453bfb8a9c"><td class="memItemLeft" align="right" valign="top"><a id="af7075aac264713e2f46786453bfb8a9c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA21F_TCC1_WO5</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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<tr class="separator:af7075aac264713e2f46786453bfb8a9c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abc5ecfe7ef842f7357851d39b509d41c"><td class="memItemLeft" align="right" valign="top"><a id="abc5ecfe7ef842f7357851d39b509d41c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA21F_TCC1_WO5</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ad828de97f945f3acfc68a0a616433d3e">PIN_PA21F_TCC1_WO5</a> << 16) | MUX_PA21F_TCC1_WO5)</td></tr>
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<tr class="separator:abc5ecfe7ef842f7357851d39b509d41c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2655bda83e92d5a9678936f31720d550"><td class="memItemLeft" align="right" valign="top"><a id="a2655bda83e92d5a9678936f31720d550"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA21F_TCC1_WO5</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 21)</td></tr>
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||
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<tr class="separator:a2655bda83e92d5a9678936f31720d550"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0b5c35beb3b82628543b2e3dda2af769"><td class="memItemLeft" align="right" valign="top"><a id="a0b5c35beb3b82628543b2e3dda2af769"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0b5c35beb3b82628543b2e3dda2af769">PIN_PA10G_TCC1_WO6</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
|
||
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<tr class="memdesc:a0b5c35beb3b82628543b2e3dda2af769"><td class="mdescLeft"> </td><td class="mdescRight">TCC1 signal: WO6 on PA10 mux G. <br /></td></tr>
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<tr class="separator:a0b5c35beb3b82628543b2e3dda2af769"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aca114d8ab81c27fe5bbab64b8affd075"><td class="memItemLeft" align="right" valign="top"><a id="aca114d8ab81c27fe5bbab64b8affd075"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA10G_TCC1_WO6</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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<tr class="separator:aca114d8ab81c27fe5bbab64b8affd075"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af89d2b700ebdcf079f69ac0acc56f6f3"><td class="memItemLeft" align="right" valign="top"><a id="af89d2b700ebdcf079f69ac0acc56f6f3"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA10G_TCC1_WO6</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a0b5c35beb3b82628543b2e3dda2af769">PIN_PA10G_TCC1_WO6</a> << 16) | MUX_PA10G_TCC1_WO6)</td></tr>
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<tr class="separator:af89d2b700ebdcf079f69ac0acc56f6f3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0426aed8dda2db316ce70cc5e77357ed"><td class="memItemLeft" align="right" valign="top"><a id="a0426aed8dda2db316ce70cc5e77357ed"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA10G_TCC1_WO6</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 10)</td></tr>
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||
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<tr class="separator:a0426aed8dda2db316ce70cc5e77357ed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5d4e4164de6400a9fdcb98ce2d37408f"><td class="memItemLeft" align="right" valign="top"><a id="a5d4e4164de6400a9fdcb98ce2d37408f"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5d4e4164de6400a9fdcb98ce2d37408f">PIN_PC12G_TCC1_WO6</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(76)</td></tr>
|
||
|
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<tr class="memdesc:a5d4e4164de6400a9fdcb98ce2d37408f"><td class="mdescLeft"> </td><td class="mdescRight">TCC1 signal: WO6 on PC12 mux G. <br /></td></tr>
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<tr class="separator:a5d4e4164de6400a9fdcb98ce2d37408f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aeae6fdc59622bf597bae8427b5ea1554"><td class="memItemLeft" align="right" valign="top"><a id="aeae6fdc59622bf597bae8427b5ea1554"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC12G_TCC1_WO6</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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<tr class="separator:aeae6fdc59622bf597bae8427b5ea1554"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6514a5c79b8e77fd2b43b1cf287c7e4c"><td class="memItemLeft" align="right" valign="top"><a id="a6514a5c79b8e77fd2b43b1cf287c7e4c"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC12G_TCC1_WO6</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a5d4e4164de6400a9fdcb98ce2d37408f">PIN_PC12G_TCC1_WO6</a> << 16) | MUX_PC12G_TCC1_WO6)</td></tr>
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<tr class="separator:a6514a5c79b8e77fd2b43b1cf287c7e4c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a527047921c84c5e9bfce9ebfc880299d"><td class="memItemLeft" align="right" valign="top"><a id="a527047921c84c5e9bfce9ebfc880299d"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC12G_TCC1_WO6</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 12)</td></tr>
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||
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<tr class="separator:a527047921c84c5e9bfce9ebfc880299d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3dc60af5cdbe8f66dc2bcac771ed1ea0"><td class="memItemLeft" align="right" valign="top"><a id="a3dc60af5cdbe8f66dc2bcac771ed1ea0"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3dc60af5cdbe8f66dc2bcac771ed1ea0">PIN_PA22F_TCC1_WO6</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(22)</td></tr>
|
||
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<tr class="memdesc:a3dc60af5cdbe8f66dc2bcac771ed1ea0"><td class="mdescLeft"> </td><td class="mdescRight">TCC1 signal: WO6 on PA22 mux F. <br /></td></tr>
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<tr class="separator:a3dc60af5cdbe8f66dc2bcac771ed1ea0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a693a3cceb8f6a42c33f4f8242c8ff23d"><td class="memItemLeft" align="right" valign="top"><a id="a693a3cceb8f6a42c33f4f8242c8ff23d"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA22F_TCC1_WO6</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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||
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<tr class="separator:a693a3cceb8f6a42c33f4f8242c8ff23d"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:ad1fc3ffb2b547cf8807dc267cadc6487"><td class="memItemLeft" align="right" valign="top"><a id="ad1fc3ffb2b547cf8807dc267cadc6487"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA22F_TCC1_WO6</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a3dc60af5cdbe8f66dc2bcac771ed1ea0">PIN_PA22F_TCC1_WO6</a> << 16) | MUX_PA22F_TCC1_WO6)</td></tr>
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<tr class="separator:ad1fc3ffb2b547cf8807dc267cadc6487"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6c080c5c2fab6f7080bce4b1e2f91c63"><td class="memItemLeft" align="right" valign="top"><a id="a6c080c5c2fab6f7080bce4b1e2f91c63"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA22F_TCC1_WO6</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 22)</td></tr>
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||
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<tr class="separator:a6c080c5c2fab6f7080bce4b1e2f91c63"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a4b791e77a8fa7a3c1a40f55262c771f4"><td class="memItemLeft" align="right" valign="top"><a id="a4b791e77a8fa7a3c1a40f55262c771f4"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4b791e77a8fa7a3c1a40f55262c771f4">PIN_PA11G_TCC1_WO7</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
|
||
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<tr class="memdesc:a4b791e77a8fa7a3c1a40f55262c771f4"><td class="mdescLeft"> </td><td class="mdescRight">TCC1 signal: WO7 on PA11 mux G. <br /></td></tr>
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<tr class="separator:a4b791e77a8fa7a3c1a40f55262c771f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa63d16fed51e839a3cdd319c7fc94b58"><td class="memItemLeft" align="right" valign="top"><a id="aa63d16fed51e839a3cdd319c7fc94b58"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA11G_TCC1_WO7</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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||
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<tr class="separator:aa63d16fed51e839a3cdd319c7fc94b58"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a28c0b2688478fc530db7b31acfde7844"><td class="memItemLeft" align="right" valign="top"><a id="a28c0b2688478fc530db7b31acfde7844"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA11G_TCC1_WO7</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a4b791e77a8fa7a3c1a40f55262c771f4">PIN_PA11G_TCC1_WO7</a> << 16) | MUX_PA11G_TCC1_WO7)</td></tr>
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<tr class="separator:a28c0b2688478fc530db7b31acfde7844"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a511e0f27f4a91d51dfa179e61ea72c18"><td class="memItemLeft" align="right" valign="top"><a id="a511e0f27f4a91d51dfa179e61ea72c18"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA11G_TCC1_WO7</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 11)</td></tr>
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||
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<tr class="separator:a511e0f27f4a91d51dfa179e61ea72c18"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad9bf895100c37405ff6e98c89edd189c"><td class="memItemLeft" align="right" valign="top"><a id="ad9bf895100c37405ff6e98c89edd189c"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad9bf895100c37405ff6e98c89edd189c">PIN_PC13G_TCC1_WO7</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(77)</td></tr>
|
||
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<tr class="memdesc:ad9bf895100c37405ff6e98c89edd189c"><td class="mdescLeft"> </td><td class="mdescRight">TCC1 signal: WO7 on PC13 mux G. <br /></td></tr>
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<tr class="separator:ad9bf895100c37405ff6e98c89edd189c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3e3be65482183964d0429e29544e102d"><td class="memItemLeft" align="right" valign="top"><a id="a3e3be65482183964d0429e29544e102d"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC13G_TCC1_WO7</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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||
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<tr class="separator:a3e3be65482183964d0429e29544e102d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2b4f1dee519afb65e5a3af612dd288cc"><td class="memItemLeft" align="right" valign="top"><a id="a2b4f1dee519afb65e5a3af612dd288cc"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC13G_TCC1_WO7</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ad9bf895100c37405ff6e98c89edd189c">PIN_PC13G_TCC1_WO7</a> << 16) | MUX_PC13G_TCC1_WO7)</td></tr>
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<tr class="separator:a2b4f1dee519afb65e5a3af612dd288cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af027d9db3c021c01b80c0aac92e151a2"><td class="memItemLeft" align="right" valign="top"><a id="af027d9db3c021c01b80c0aac92e151a2"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC13G_TCC1_WO7</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 13)</td></tr>
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<tr class="separator:af027d9db3c021c01b80c0aac92e151a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a314ab3a9ff0f51027281c79227c26078"><td class="memItemLeft" align="right" valign="top"><a id="a314ab3a9ff0f51027281c79227c26078"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a314ab3a9ff0f51027281c79227c26078">PIN_PA23F_TCC1_WO7</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(23)</td></tr>
|
||
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<tr class="memdesc:a314ab3a9ff0f51027281c79227c26078"><td class="mdescLeft"> </td><td class="mdescRight">TCC1 signal: WO7 on PA23 mux F. <br /></td></tr>
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<tr class="separator:a314ab3a9ff0f51027281c79227c26078"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a11357fcfbc315b5c927de93aa1a48e49"><td class="memItemLeft" align="right" valign="top"><a id="a11357fcfbc315b5c927de93aa1a48e49"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA23F_TCC1_WO7</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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<tr class="separator:a11357fcfbc315b5c927de93aa1a48e49"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab984f0009a6dc303e712a0d24672d664"><td class="memItemLeft" align="right" valign="top"><a id="ab984f0009a6dc303e712a0d24672d664"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA23F_TCC1_WO7</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a314ab3a9ff0f51027281c79227c26078">PIN_PA23F_TCC1_WO7</a> << 16) | MUX_PA23F_TCC1_WO7)</td></tr>
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<tr class="separator:ab984f0009a6dc303e712a0d24672d664"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad0e6c376f815547c8766d33003b09091"><td class="memItemLeft" align="right" valign="top"><a id="ad0e6c376f815547c8766d33003b09091"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA23F_TCC1_WO7</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 23)</td></tr>
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<tr class="separator:ad0e6c376f815547c8766d33003b09091"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa761970c4cdbf930364f75bef19e7ef5"><td class="memItemLeft" align="right" valign="top"><a id="aa761970c4cdbf930364f75bef19e7ef5"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa761970c4cdbf930364f75bef19e7ef5">PIN_PA12E_TC2_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
|
||
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<tr class="memdesc:aa761970c4cdbf930364f75bef19e7ef5"><td class="mdescLeft"> </td><td class="mdescRight">TC2 signal: WO0 on PA12 mux E. <br /></td></tr>
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<tr class="separator:aa761970c4cdbf930364f75bef19e7ef5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae86947caf3fc77398b6f6614a3034e91"><td class="memItemLeft" align="right" valign="top"><a id="ae86947caf3fc77398b6f6614a3034e91"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA12E_TC2_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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<tr class="separator:ae86947caf3fc77398b6f6614a3034e91"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a435886bd03a592e40ee2a1ac1cbac6cd"><td class="memItemLeft" align="right" valign="top"><a id="a435886bd03a592e40ee2a1ac1cbac6cd"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA12E_TC2_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aa761970c4cdbf930364f75bef19e7ef5">PIN_PA12E_TC2_WO0</a> << 16) | MUX_PA12E_TC2_WO0)</td></tr>
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<tr class="separator:a435886bd03a592e40ee2a1ac1cbac6cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad87060d3f29fe3c328db154f1b1e74ee"><td class="memItemLeft" align="right" valign="top"><a id="ad87060d3f29fe3c328db154f1b1e74ee"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA12E_TC2_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 12)</td></tr>
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||
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<tr class="separator:ad87060d3f29fe3c328db154f1b1e74ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8d7eddbf3d5b6030518ae474afc417a4"><td class="memItemLeft" align="right" valign="top"><a id="a8d7eddbf3d5b6030518ae474afc417a4"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8d7eddbf3d5b6030518ae474afc417a4">PIN_PA16E_TC2_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(16)</td></tr>
|
||
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<tr class="memdesc:a8d7eddbf3d5b6030518ae474afc417a4"><td class="mdescLeft"> </td><td class="mdescRight">TC2 signal: WO0 on PA16 mux E. <br /></td></tr>
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<tr class="separator:a8d7eddbf3d5b6030518ae474afc417a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aed63616fb5564c54ce24694e9c6ca265"><td class="memItemLeft" align="right" valign="top"><a id="aed63616fb5564c54ce24694e9c6ca265"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA16E_TC2_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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||
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<tr class="separator:aed63616fb5564c54ce24694e9c6ca265"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5f965f4a9406247f96bdf7011ba62df8"><td class="memItemLeft" align="right" valign="top"><a id="a5f965f4a9406247f96bdf7011ba62df8"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA16E_TC2_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a8d7eddbf3d5b6030518ae474afc417a4">PIN_PA16E_TC2_WO0</a> << 16) | MUX_PA16E_TC2_WO0)</td></tr>
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<tr class="separator:a5f965f4a9406247f96bdf7011ba62df8"><td class="memSeparator" colspan="2"> </td></tr>
|
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<tr class="memitem:a6a1d2c73e5edfae897750e2e2da34373"><td class="memItemLeft" align="right" valign="top"><a id="a6a1d2c73e5edfae897750e2e2da34373"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA16E_TC2_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 16)</td></tr>
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||
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<tr class="separator:a6a1d2c73e5edfae897750e2e2da34373"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9992a46283cbefd638c25c11299473e6"><td class="memItemLeft" align="right" valign="top"><a id="a9992a46283cbefd638c25c11299473e6"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a9992a46283cbefd638c25c11299473e6">PIN_PA00E_TC2_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(0)</td></tr>
|
||
|
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<tr class="memdesc:a9992a46283cbefd638c25c11299473e6"><td class="mdescLeft"> </td><td class="mdescRight">TC2 signal: WO0 on PA00 mux E. <br /></td></tr>
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<tr class="separator:a9992a46283cbefd638c25c11299473e6"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a25de78a39b045b111871f268bf0de1ee"><td class="memItemLeft" align="right" valign="top"><a id="a25de78a39b045b111871f268bf0de1ee"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA00E_TC2_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
|
||
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<tr class="separator:a25de78a39b045b111871f268bf0de1ee"><td class="memSeparator" colspan="2"> </td></tr>
|
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<tr class="memitem:a994e1f246cc815f1bbab87e55d27ca78"><td class="memItemLeft" align="right" valign="top"><a id="a994e1f246cc815f1bbab87e55d27ca78"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA00E_TC2_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a9992a46283cbefd638c25c11299473e6">PIN_PA00E_TC2_WO0</a> << 16) | MUX_PA00E_TC2_WO0)</td></tr>
|
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<tr class="separator:a994e1f246cc815f1bbab87e55d27ca78"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a9ca3501039890036bcb120df9a0448dd"><td class="memItemLeft" align="right" valign="top"><a id="a9ca3501039890036bcb120df9a0448dd"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA00E_TC2_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 0)</td></tr>
|
||
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<tr class="separator:a9ca3501039890036bcb120df9a0448dd"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:adf9ba2f85b9f5683706a12af451d037e"><td class="memItemLeft" align="right" valign="top"><a id="adf9ba2f85b9f5683706a12af451d037e"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#adf9ba2f85b9f5683706a12af451d037e">PIN_PA01E_TC2_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
|
||
|
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<tr class="memdesc:adf9ba2f85b9f5683706a12af451d037e"><td class="mdescLeft"> </td><td class="mdescRight">TC2 signal: WO1 on PA01 mux E. <br /></td></tr>
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<tr class="separator:adf9ba2f85b9f5683706a12af451d037e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aff90c9e4dad6241effc868c4e28c5970"><td class="memItemLeft" align="right" valign="top"><a id="aff90c9e4dad6241effc868c4e28c5970"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA01E_TC2_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
|
||
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<tr class="separator:aff90c9e4dad6241effc868c4e28c5970"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a128910d50cf35530417053a2d0489f9a"><td class="memItemLeft" align="right" valign="top"><a id="a128910d50cf35530417053a2d0489f9a"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA01E_TC2_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#adf9ba2f85b9f5683706a12af451d037e">PIN_PA01E_TC2_WO1</a> << 16) | MUX_PA01E_TC2_WO1)</td></tr>
|
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<tr class="separator:a128910d50cf35530417053a2d0489f9a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac0dd553ae44bcb2282df5333df8a8e7c"><td class="memItemLeft" align="right" valign="top"><a id="ac0dd553ae44bcb2282df5333df8a8e7c"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA01E_TC2_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 1)</td></tr>
|
||
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<tr class="separator:ac0dd553ae44bcb2282df5333df8a8e7c"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a4ad884ff60803c898735bfbc4b9b6a01"><td class="memItemLeft" align="right" valign="top"><a id="a4ad884ff60803c898735bfbc4b9b6a01"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4ad884ff60803c898735bfbc4b9b6a01">PIN_PA13E_TC2_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
|
||
|
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<tr class="memdesc:a4ad884ff60803c898735bfbc4b9b6a01"><td class="mdescLeft"> </td><td class="mdescRight">TC2 signal: WO1 on PA13 mux E. <br /></td></tr>
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<tr class="separator:a4ad884ff60803c898735bfbc4b9b6a01"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad5369afc109fa6c79b2b578331a2fefd"><td class="memItemLeft" align="right" valign="top"><a id="ad5369afc109fa6c79b2b578331a2fefd"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA13E_TC2_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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||
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<tr class="separator:ad5369afc109fa6c79b2b578331a2fefd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abe7fd4c40d0fe65e45dc9082298e0f11"><td class="memItemLeft" align="right" valign="top"><a id="abe7fd4c40d0fe65e45dc9082298e0f11"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA13E_TC2_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a4ad884ff60803c898735bfbc4b9b6a01">PIN_PA13E_TC2_WO1</a> << 16) | MUX_PA13E_TC2_WO1)</td></tr>
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<tr class="separator:abe7fd4c40d0fe65e45dc9082298e0f11"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1cb4fe4ae1ce6427e9301defdae8c987"><td class="memItemLeft" align="right" valign="top"><a id="a1cb4fe4ae1ce6427e9301defdae8c987"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA13E_TC2_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 13)</td></tr>
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||
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<tr class="separator:a1cb4fe4ae1ce6427e9301defdae8c987"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a4c473a6ac59c3836decf88485c83d7d4"><td class="memItemLeft" align="right" valign="top"><a id="a4c473a6ac59c3836decf88485c83d7d4"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4c473a6ac59c3836decf88485c83d7d4">PIN_PA17E_TC2_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(17)</td></tr>
|
||
|
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<tr class="memdesc:a4c473a6ac59c3836decf88485c83d7d4"><td class="mdescLeft"> </td><td class="mdescRight">TC2 signal: WO1 on PA17 mux E. <br /></td></tr>
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<tr class="separator:a4c473a6ac59c3836decf88485c83d7d4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aca540b9bd4d002d8a1bae836d4cf4e17"><td class="memItemLeft" align="right" valign="top"><a id="aca540b9bd4d002d8a1bae836d4cf4e17"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA17E_TC2_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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||
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<tr class="separator:aca540b9bd4d002d8a1bae836d4cf4e17"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9847977ac26c071d3b38cf51a4837a93"><td class="memItemLeft" align="right" valign="top"><a id="a9847977ac26c071d3b38cf51a4837a93"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA17E_TC2_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a4c473a6ac59c3836decf88485c83d7d4">PIN_PA17E_TC2_WO1</a> << 16) | MUX_PA17E_TC2_WO1)</td></tr>
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<tr class="separator:a9847977ac26c071d3b38cf51a4837a93"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4c1a9c2348cb482ecd59c43116a6c7b8"><td class="memItemLeft" align="right" valign="top"><a id="a4c1a9c2348cb482ecd59c43116a6c7b8"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA17E_TC2_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 17)</td></tr>
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<tr class="separator:a4c1a9c2348cb482ecd59c43116a6c7b8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a939926952c9ac148cafb3711de6c49bb"><td class="memItemLeft" align="right" valign="top"><a id="a939926952c9ac148cafb3711de6c49bb"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a939926952c9ac148cafb3711de6c49bb">PIN_PA18E_TC3_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(18)</td></tr>
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<tr class="memdesc:a939926952c9ac148cafb3711de6c49bb"><td class="mdescLeft"> </td><td class="mdescRight">TC3 signal: WO0 on PA18 mux E. <br /></td></tr>
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<tr class="memitem:ab30b46a8560942ffeff7264f3fd8d438"><td class="memItemLeft" align="right" valign="top"><a id="ab30b46a8560942ffeff7264f3fd8d438"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA18E_TC3_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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<tr class="separator:ab30b46a8560942ffeff7264f3fd8d438"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a969e04b75ccb38097630ffd103980036"><td class="memItemLeft" align="right" valign="top"><a id="a969e04b75ccb38097630ffd103980036"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA18E_TC3_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a939926952c9ac148cafb3711de6c49bb">PIN_PA18E_TC3_WO0</a> << 16) | MUX_PA18E_TC3_WO0)</td></tr>
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<tr class="separator:a969e04b75ccb38097630ffd103980036"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a35ccdc75c0130fc480fb7a4dab9d19ac"><td class="memItemLeft" align="right" valign="top"><a id="a35ccdc75c0130fc480fb7a4dab9d19ac"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA18E_TC3_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 18)</td></tr>
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<tr class="separator:a35ccdc75c0130fc480fb7a4dab9d19ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0cfe738890e6273b42dc25d87ceacab9"><td class="memItemLeft" align="right" valign="top"><a id="a0cfe738890e6273b42dc25d87ceacab9"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0cfe738890e6273b42dc25d87ceacab9">PIN_PA14E_TC3_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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<tr class="memdesc:a0cfe738890e6273b42dc25d87ceacab9"><td class="mdescLeft"> </td><td class="mdescRight">TC3 signal: WO0 on PA14 mux E. <br /></td></tr>
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<tr class="separator:a0cfe738890e6273b42dc25d87ceacab9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae5bc61f67b7b3a9b03907303978ccc99"><td class="memItemLeft" align="right" valign="top"><a id="ae5bc61f67b7b3a9b03907303978ccc99"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA14E_TC3_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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<tr class="separator:ae5bc61f67b7b3a9b03907303978ccc99"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1c24e01c1121adf30e45a8b90886d0ca"><td class="memItemLeft" align="right" valign="top"><a id="a1c24e01c1121adf30e45a8b90886d0ca"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA14E_TC3_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a0cfe738890e6273b42dc25d87ceacab9">PIN_PA14E_TC3_WO0</a> << 16) | MUX_PA14E_TC3_WO0)</td></tr>
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<tr class="separator:a1c24e01c1121adf30e45a8b90886d0ca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2f735751b0533d85c3d023b5e1660b7c"><td class="memItemLeft" align="right" valign="top"><a id="a2f735751b0533d85c3d023b5e1660b7c"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA14E_TC3_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 14)</td></tr>
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<tr class="separator:a2f735751b0533d85c3d023b5e1660b7c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4cd9c042fff6cc0355d62086367932ec"><td class="memItemLeft" align="right" valign="top"><a id="a4cd9c042fff6cc0355d62086367932ec"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4cd9c042fff6cc0355d62086367932ec">PIN_PA15E_TC3_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(15)</td></tr>
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||
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<tr class="memdesc:a4cd9c042fff6cc0355d62086367932ec"><td class="mdescLeft"> </td><td class="mdescRight">TC3 signal: WO1 on PA15 mux E. <br /></td></tr>
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<tr class="separator:a4cd9c042fff6cc0355d62086367932ec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acfb7b830b89d234814b33c533d4e4af0"><td class="memItemLeft" align="right" valign="top"><a id="acfb7b830b89d234814b33c533d4e4af0"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA15E_TC3_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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||
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<tr class="separator:acfb7b830b89d234814b33c533d4e4af0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5a4015532d64748cb849d60f202e3135"><td class="memItemLeft" align="right" valign="top"><a id="a5a4015532d64748cb849d60f202e3135"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA15E_TC3_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a4cd9c042fff6cc0355d62086367932ec">PIN_PA15E_TC3_WO1</a> << 16) | MUX_PA15E_TC3_WO1)</td></tr>
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<tr class="separator:a5a4015532d64748cb849d60f202e3135"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4835559084a201d08c70b50785835117"><td class="memItemLeft" align="right" valign="top"><a id="a4835559084a201d08c70b50785835117"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA15E_TC3_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 15)</td></tr>
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||
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<tr class="separator:a4835559084a201d08c70b50785835117"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac3c5208b6eeef04e542f16e30e5b2e95"><td class="memItemLeft" align="right" valign="top"><a id="ac3c5208b6eeef04e542f16e30e5b2e95"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac3c5208b6eeef04e542f16e30e5b2e95">PIN_PA19E_TC3_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(19)</td></tr>
|
||
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<tr class="memdesc:ac3c5208b6eeef04e542f16e30e5b2e95"><td class="mdescLeft"> </td><td class="mdescRight">TC3 signal: WO1 on PA19 mux E. <br /></td></tr>
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<tr class="separator:ac3c5208b6eeef04e542f16e30e5b2e95"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa719b0dd0b45ca7c72564df0dc6efbe9"><td class="memItemLeft" align="right" valign="top"><a id="aa719b0dd0b45ca7c72564df0dc6efbe9"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA19E_TC3_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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||
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<tr class="separator:aa719b0dd0b45ca7c72564df0dc6efbe9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1eabe7642136da686024d8cc3fa48952"><td class="memItemLeft" align="right" valign="top"><a id="a1eabe7642136da686024d8cc3fa48952"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA19E_TC3_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ac3c5208b6eeef04e542f16e30e5b2e95">PIN_PA19E_TC3_WO1</a> << 16) | MUX_PA19E_TC3_WO1)</td></tr>
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<tr class="separator:a1eabe7642136da686024d8cc3fa48952"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7b79eca99dc6d2a620821cc2dd276a9d"><td class="memItemLeft" align="right" valign="top"><a id="a7b79eca99dc6d2a620821cc2dd276a9d"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA19E_TC3_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 19)</td></tr>
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||
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<tr class="separator:a7b79eca99dc6d2a620821cc2dd276a9d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0ab1381e84165e9ed82ff6e5d11c8888"><td class="memItemLeft" align="right" valign="top"><a id="a0ab1381e84165e9ed82ff6e5d11c8888"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0ab1381e84165e9ed82ff6e5d11c8888">PIN_PA23I_CAN0_RX</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(23)</td></tr>
|
||
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<tr class="memdesc:a0ab1381e84165e9ed82ff6e5d11c8888"><td class="mdescLeft"> </td><td class="mdescRight">CAN0 signal: RX on PA23 mux I. <br /></td></tr>
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<tr class="separator:a0ab1381e84165e9ed82ff6e5d11c8888"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a64d10f172574eb675a6376e91db4edeb"><td class="memItemLeft" align="right" valign="top"><a id="a64d10f172574eb675a6376e91db4edeb"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA23I_CAN0_RX</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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<tr class="separator:a64d10f172574eb675a6376e91db4edeb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3f0afedc0816e112ebbd067ef92ca919"><td class="memItemLeft" align="right" valign="top"><a id="a3f0afedc0816e112ebbd067ef92ca919"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA23I_CAN0_RX</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a0ab1381e84165e9ed82ff6e5d11c8888">PIN_PA23I_CAN0_RX</a> << 16) | MUX_PA23I_CAN0_RX)</td></tr>
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<tr class="separator:a3f0afedc0816e112ebbd067ef92ca919"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab6ae29ef9eaac3e987b369e7799e2a2b"><td class="memItemLeft" align="right" valign="top"><a id="ab6ae29ef9eaac3e987b369e7799e2a2b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA23I_CAN0_RX</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 23)</td></tr>
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||
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<tr class="separator:ab6ae29ef9eaac3e987b369e7799e2a2b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab3258c13b0ff5caa156ef75c35541558"><td class="memItemLeft" align="right" valign="top"><a id="ab3258c13b0ff5caa156ef75c35541558"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab3258c13b0ff5caa156ef75c35541558">PIN_PA25I_CAN0_RX</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(25)</td></tr>
|
||
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<tr class="memdesc:ab3258c13b0ff5caa156ef75c35541558"><td class="mdescLeft"> </td><td class="mdescRight">CAN0 signal: RX on PA25 mux I. <br /></td></tr>
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<tr class="separator:ab3258c13b0ff5caa156ef75c35541558"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6d9a277be4bcf21cdcb2d669bac9624f"><td class="memItemLeft" align="right" valign="top"><a id="a6d9a277be4bcf21cdcb2d669bac9624f"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA25I_CAN0_RX</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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||
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<tr class="separator:a6d9a277be4bcf21cdcb2d669bac9624f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab4fa8324566af235886971bff150d8af"><td class="memItemLeft" align="right" valign="top"><a id="ab4fa8324566af235886971bff150d8af"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA25I_CAN0_RX</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ab3258c13b0ff5caa156ef75c35541558">PIN_PA25I_CAN0_RX</a> << 16) | MUX_PA25I_CAN0_RX)</td></tr>
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<tr class="separator:ab4fa8324566af235886971bff150d8af"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a248e35c04a08d0817854d51dc26803e7"><td class="memItemLeft" align="right" valign="top"><a id="a248e35c04a08d0817854d51dc26803e7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA25I_CAN0_RX</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 25)</td></tr>
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||
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<tr class="separator:a248e35c04a08d0817854d51dc26803e7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a183b5e8cc25edc54870599afd59da7cb"><td class="memItemLeft" align="right" valign="top"><a id="a183b5e8cc25edc54870599afd59da7cb"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a183b5e8cc25edc54870599afd59da7cb">PIN_PA22I_CAN0_TX</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(22)</td></tr>
|
||
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<tr class="memdesc:a183b5e8cc25edc54870599afd59da7cb"><td class="mdescLeft"> </td><td class="mdescRight">CAN0 signal: TX on PA22 mux I. <br /></td></tr>
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<tr class="separator:a183b5e8cc25edc54870599afd59da7cb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa140f812ec313e975b78d5525802481a"><td class="memItemLeft" align="right" valign="top"><a id="aa140f812ec313e975b78d5525802481a"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA22I_CAN0_TX</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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||
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<tr class="separator:aa140f812ec313e975b78d5525802481a"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a4594f437d5a19f8980145175bfba6d26"><td class="memItemLeft" align="right" valign="top"><a id="a4594f437d5a19f8980145175bfba6d26"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA22I_CAN0_TX</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a183b5e8cc25edc54870599afd59da7cb">PIN_PA22I_CAN0_TX</a> << 16) | MUX_PA22I_CAN0_TX)</td></tr>
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<tr class="separator:a4594f437d5a19f8980145175bfba6d26"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad37da088c29249f21d5de3c8af8d8cfe"><td class="memItemLeft" align="right" valign="top"><a id="ad37da088c29249f21d5de3c8af8d8cfe"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA22I_CAN0_TX</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 22)</td></tr>
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||
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<tr class="separator:ad37da088c29249f21d5de3c8af8d8cfe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae2dcca4d5a79efc615601c5219eebd38"><td class="memItemLeft" align="right" valign="top"><a id="ae2dcca4d5a79efc615601c5219eebd38"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae2dcca4d5a79efc615601c5219eebd38">PIN_PA24I_CAN0_TX</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(24)</td></tr>
|
||
|
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<tr class="memdesc:ae2dcca4d5a79efc615601c5219eebd38"><td class="mdescLeft"> </td><td class="mdescRight">CAN0 signal: TX on PA24 mux I. <br /></td></tr>
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<tr class="separator:ae2dcca4d5a79efc615601c5219eebd38"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1c938be29584db9c1ee9fcfffcf2de8c"><td class="memItemLeft" align="right" valign="top"><a id="a1c938be29584db9c1ee9fcfffcf2de8c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA24I_CAN0_TX</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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<tr class="memitem:afac809b3165b10d21205802af3944022"><td class="memItemLeft" align="right" valign="top"><a id="afac809b3165b10d21205802af3944022"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA24I_CAN0_TX</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ae2dcca4d5a79efc615601c5219eebd38">PIN_PA24I_CAN0_TX</a> << 16) | MUX_PA24I_CAN0_TX)</td></tr>
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<tr class="separator:afac809b3165b10d21205802af3944022"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3198a34912db2a502b6c50d4aaf3dc32"><td class="memItemLeft" align="right" valign="top"><a id="a3198a34912db2a502b6c50d4aaf3dc32"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA24I_CAN0_TX</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 24)</td></tr>
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<tr class="separator:a3198a34912db2a502b6c50d4aaf3dc32"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a584ca0a63440951c28f70dbd39e056e6"><td class="memItemLeft" align="right" valign="top"><a id="a584ca0a63440951c28f70dbd39e056e6"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a584ca0a63440951c28f70dbd39e056e6">PIN_PB13H_CAN1_RX</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(45)</td></tr>
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<tr class="memdesc:a584ca0a63440951c28f70dbd39e056e6"><td class="mdescLeft"> </td><td class="mdescRight">CAN1 signal: RX on PB13 mux H. <br /></td></tr>
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<tr class="separator:a584ca0a63440951c28f70dbd39e056e6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2361963764909e6ad4d214bab4a284f9"><td class="memItemLeft" align="right" valign="top"><a id="a2361963764909e6ad4d214bab4a284f9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB13H_CAN1_RX</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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<tr class="separator:a2361963764909e6ad4d214bab4a284f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a671f8ed128c878da77b12cd0d72418d4"><td class="memItemLeft" align="right" valign="top"><a id="a671f8ed128c878da77b12cd0d72418d4"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB13H_CAN1_RX</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a584ca0a63440951c28f70dbd39e056e6">PIN_PB13H_CAN1_RX</a> << 16) | MUX_PB13H_CAN1_RX)</td></tr>
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<tr class="separator:a671f8ed128c878da77b12cd0d72418d4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa7b98184490b39402c9599b302281ed9"><td class="memItemLeft" align="right" valign="top"><a id="aa7b98184490b39402c9599b302281ed9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB13H_CAN1_RX</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 13)</td></tr>
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<tr class="separator:aa7b98184490b39402c9599b302281ed9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a90ba5deec4794ccbbf409a41eab91338"><td class="memItemLeft" align="right" valign="top"><a id="a90ba5deec4794ccbbf409a41eab91338"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a90ba5deec4794ccbbf409a41eab91338">PIN_PB15H_CAN1_RX</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(47)</td></tr>
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<tr class="memdesc:a90ba5deec4794ccbbf409a41eab91338"><td class="mdescLeft"> </td><td class="mdescRight">CAN1 signal: RX on PB15 mux H. <br /></td></tr>
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<tr class="separator:a90ba5deec4794ccbbf409a41eab91338"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acbc7dead92b0dd35dd8f61a992e65b63"><td class="memItemLeft" align="right" valign="top"><a id="acbc7dead92b0dd35dd8f61a992e65b63"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB15H_CAN1_RX</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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<tr class="separator:acbc7dead92b0dd35dd8f61a992e65b63"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab7c445ba3839b6d60e265ae06b9f114e"><td class="memItemLeft" align="right" valign="top"><a id="ab7c445ba3839b6d60e265ae06b9f114e"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB15H_CAN1_RX</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a90ba5deec4794ccbbf409a41eab91338">PIN_PB15H_CAN1_RX</a> << 16) | MUX_PB15H_CAN1_RX)</td></tr>
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<tr class="separator:ab7c445ba3839b6d60e265ae06b9f114e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aca80d42ebca68a2618ec945bc9b3d9b4"><td class="memItemLeft" align="right" valign="top"><a id="aca80d42ebca68a2618ec945bc9b3d9b4"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB15H_CAN1_RX</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 15)</td></tr>
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<tr class="separator:aca80d42ebca68a2618ec945bc9b3d9b4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae09e0cb0f9f4f021767197f474747eb3"><td class="memItemLeft" align="right" valign="top"><a id="ae09e0cb0f9f4f021767197f474747eb3"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae09e0cb0f9f4f021767197f474747eb3">PIN_PB12H_CAN1_TX</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(44)</td></tr>
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||
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<tr class="memdesc:ae09e0cb0f9f4f021767197f474747eb3"><td class="mdescLeft"> </td><td class="mdescRight">CAN1 signal: TX on PB12 mux H. <br /></td></tr>
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<tr class="separator:ae09e0cb0f9f4f021767197f474747eb3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa4c6e7797d795e1b07de0acbf9959882"><td class="memItemLeft" align="right" valign="top"><a id="aa4c6e7797d795e1b07de0acbf9959882"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB12H_CAN1_TX</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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<tr class="separator:aa4c6e7797d795e1b07de0acbf9959882"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abd2102b96eec9a1775f37ff416c56b1d"><td class="memItemLeft" align="right" valign="top"><a id="abd2102b96eec9a1775f37ff416c56b1d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB12H_CAN1_TX</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ae09e0cb0f9f4f021767197f474747eb3">PIN_PB12H_CAN1_TX</a> << 16) | MUX_PB12H_CAN1_TX)</td></tr>
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<tr class="separator:abd2102b96eec9a1775f37ff416c56b1d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8790a85837e52654f71ce7c631358cee"><td class="memItemLeft" align="right" valign="top"><a id="a8790a85837e52654f71ce7c631358cee"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB12H_CAN1_TX</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 12)</td></tr>
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<tr class="separator:a8790a85837e52654f71ce7c631358cee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad1d2bc25031f28aca25bf7faad2751d7"><td class="memItemLeft" align="right" valign="top"><a id="ad1d2bc25031f28aca25bf7faad2751d7"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad1d2bc25031f28aca25bf7faad2751d7">PIN_PB14H_CAN1_TX</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(46)</td></tr>
|
||
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<tr class="memdesc:ad1d2bc25031f28aca25bf7faad2751d7"><td class="mdescLeft"> </td><td class="mdescRight">CAN1 signal: TX on PB14 mux H. <br /></td></tr>
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<tr class="separator:ad1d2bc25031f28aca25bf7faad2751d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a25cde043af59e9a3f398eef18190c033"><td class="memItemLeft" align="right" valign="top"><a id="a25cde043af59e9a3f398eef18190c033"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB14H_CAN1_TX</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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<tr class="separator:a25cde043af59e9a3f398eef18190c033"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5a3bd90aec12994d7dd4aeb7dc1424a7"><td class="memItemLeft" align="right" valign="top"><a id="a5a3bd90aec12994d7dd4aeb7dc1424a7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB14H_CAN1_TX</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ad1d2bc25031f28aca25bf7faad2751d7">PIN_PB14H_CAN1_TX</a> << 16) | MUX_PB14H_CAN1_TX)</td></tr>
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<tr class="separator:a5a3bd90aec12994d7dd4aeb7dc1424a7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa16255d05c50f80d7f6d9d8ef51649eb"><td class="memItemLeft" align="right" valign="top"><a id="aa16255d05c50f80d7f6d9d8ef51649eb"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB14H_CAN1_TX</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 14)</td></tr>
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<tr class="separator:aa16255d05c50f80d7f6d9d8ef51649eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a115c1290a606c9eefaff58992feaefa5"><td class="memItemLeft" align="right" valign="top"><a id="a115c1290a606c9eefaff58992feaefa5"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a115c1290a606c9eefaff58992feaefa5">PIN_PC21L_GMAC_GCOL</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(85)</td></tr>
|
||
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<tr class="memdesc:a115c1290a606c9eefaff58992feaefa5"><td class="mdescLeft"> </td><td class="mdescRight">GMAC signal: GCOL on PC21 mux L. <br /></td></tr>
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<tr class="separator:a115c1290a606c9eefaff58992feaefa5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aee5ece0db3b81b79c73e4d9d7a8786c5"><td class="memItemLeft" align="right" valign="top"><a id="aee5ece0db3b81b79c73e4d9d7a8786c5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC21L_GMAC_GCOL</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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<tr class="separator:aee5ece0db3b81b79c73e4d9d7a8786c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a78bb9eb6ba0278ef8521e67b32f8f643"><td class="memItemLeft" align="right" valign="top"><a id="a78bb9eb6ba0278ef8521e67b32f8f643"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC21L_GMAC_GCOL</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a115c1290a606c9eefaff58992feaefa5">PIN_PC21L_GMAC_GCOL</a> << 16) | MUX_PC21L_GMAC_GCOL)</td></tr>
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<tr class="separator:a78bb9eb6ba0278ef8521e67b32f8f643"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7103592191c4c8aadd58547115bbb58c"><td class="memItemLeft" align="right" valign="top"><a id="a7103592191c4c8aadd58547115bbb58c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC21L_GMAC_GCOL</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 21)</td></tr>
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<tr class="separator:a7103592191c4c8aadd58547115bbb58c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a30a52fd41f3541a332b1a097fa9958f0"><td class="memItemLeft" align="right" valign="top"><a id="a30a52fd41f3541a332b1a097fa9958f0"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a30a52fd41f3541a332b1a097fa9958f0">PIN_PA16L_GMAC_GCRS</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(16)</td></tr>
|
||
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<tr class="memdesc:a30a52fd41f3541a332b1a097fa9958f0"><td class="mdescLeft"> </td><td class="mdescRight">GMAC signal: GCRS on PA16 mux L. <br /></td></tr>
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<tr class="separator:a30a52fd41f3541a332b1a097fa9958f0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad930520464db7e70b444637f84721d89"><td class="memItemLeft" align="right" valign="top"><a id="ad930520464db7e70b444637f84721d89"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA16L_GMAC_GCRS</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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<tr class="separator:ad930520464db7e70b444637f84721d89"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab3d9ed2d730786f7bc0eac3e29a7aff3"><td class="memItemLeft" align="right" valign="top"><a id="ab3d9ed2d730786f7bc0eac3e29a7aff3"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA16L_GMAC_GCRS</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a30a52fd41f3541a332b1a097fa9958f0">PIN_PA16L_GMAC_GCRS</a> << 16) | MUX_PA16L_GMAC_GCRS)</td></tr>
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<tr class="separator:ab3d9ed2d730786f7bc0eac3e29a7aff3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a57b6c6d4e28bc1a2f1972e4885e29ca3"><td class="memItemLeft" align="right" valign="top"><a id="a57b6c6d4e28bc1a2f1972e4885e29ca3"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA16L_GMAC_GCRS</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 16)</td></tr>
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||
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<tr class="separator:a57b6c6d4e28bc1a2f1972e4885e29ca3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8af84b30c55efdfb5a821fb897ce7a06"><td class="memItemLeft" align="right" valign="top"><a id="a8af84b30c55efdfb5a821fb897ce7a06"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8af84b30c55efdfb5a821fb897ce7a06">PIN_PA20L_GMAC_GMDC</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(20)</td></tr>
|
||
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<tr class="memdesc:a8af84b30c55efdfb5a821fb897ce7a06"><td class="mdescLeft"> </td><td class="mdescRight">GMAC signal: GMDC on PA20 mux L. <br /></td></tr>
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<tr class="separator:a8af84b30c55efdfb5a821fb897ce7a06"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9605891e87e48f8dfb4c59cd9a32ee2a"><td class="memItemLeft" align="right" valign="top"><a id="a9605891e87e48f8dfb4c59cd9a32ee2a"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA20L_GMAC_GMDC</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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<tr class="separator:a9605891e87e48f8dfb4c59cd9a32ee2a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afdc18e7d0dd747287f0af0d0f64043cd"><td class="memItemLeft" align="right" valign="top"><a id="afdc18e7d0dd747287f0af0d0f64043cd"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA20L_GMAC_GMDC</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a8af84b30c55efdfb5a821fb897ce7a06">PIN_PA20L_GMAC_GMDC</a> << 16) | MUX_PA20L_GMAC_GMDC)</td></tr>
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<tr class="separator:afdc18e7d0dd747287f0af0d0f64043cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7053803bc48d4365442d1d5e0c698437"><td class="memItemLeft" align="right" valign="top"><a id="a7053803bc48d4365442d1d5e0c698437"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA20L_GMAC_GMDC</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 20)</td></tr>
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||
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<tr class="separator:a7053803bc48d4365442d1d5e0c698437"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adc71e6b89c3acd2f53fa4511a57af468"><td class="memItemLeft" align="right" valign="top"><a id="adc71e6b89c3acd2f53fa4511a57af468"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#adc71e6b89c3acd2f53fa4511a57af468">PIN_PB14L_GMAC_GMDC</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(46)</td></tr>
|
||
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<tr class="memdesc:adc71e6b89c3acd2f53fa4511a57af468"><td class="mdescLeft"> </td><td class="mdescRight">GMAC signal: GMDC on PB14 mux L. <br /></td></tr>
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<tr class="separator:adc71e6b89c3acd2f53fa4511a57af468"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a210c3fd701c0e42eeae79b69b36daffd"><td class="memItemLeft" align="right" valign="top"><a id="a210c3fd701c0e42eeae79b69b36daffd"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB14L_GMAC_GMDC</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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||
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<tr class="separator:a210c3fd701c0e42eeae79b69b36daffd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a58958459511a22afaa032b5a841e3aaf"><td class="memItemLeft" align="right" valign="top"><a id="a58958459511a22afaa032b5a841e3aaf"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB14L_GMAC_GMDC</b>   ((<a class="el" href="pio_2same54p20a_8h.html#adc71e6b89c3acd2f53fa4511a57af468">PIN_PB14L_GMAC_GMDC</a> << 16) | MUX_PB14L_GMAC_GMDC)</td></tr>
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<tr class="separator:a58958459511a22afaa032b5a841e3aaf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a28c736f243ccb7fb417e9e8cfaa8a1d1"><td class="memItemLeft" align="right" valign="top"><a id="a28c736f243ccb7fb417e9e8cfaa8a1d1"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB14L_GMAC_GMDC</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 14)</td></tr>
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||
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<tr class="separator:a28c736f243ccb7fb417e9e8cfaa8a1d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a36f561d868f4a6c82e176311732a79c1"><td class="memItemLeft" align="right" valign="top"><a id="a36f561d868f4a6c82e176311732a79c1"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a36f561d868f4a6c82e176311732a79c1">PIN_PC11L_GMAC_GMDC</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(75)</td></tr>
|
||
|
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<tr class="memdesc:a36f561d868f4a6c82e176311732a79c1"><td class="mdescLeft"> </td><td class="mdescRight">GMAC signal: GMDC on PC11 mux L. <br /></td></tr>
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<tr class="separator:a36f561d868f4a6c82e176311732a79c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab3a2bdd1888bef60cc0876c1d4640218"><td class="memItemLeft" align="right" valign="top"><a id="ab3a2bdd1888bef60cc0876c1d4640218"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC11L_GMAC_GMDC</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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||
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<tr class="separator:ab3a2bdd1888bef60cc0876c1d4640218"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aff046f3aafc0b2b604b35d0f4efb6136"><td class="memItemLeft" align="right" valign="top"><a id="aff046f3aafc0b2b604b35d0f4efb6136"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC11L_GMAC_GMDC</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a36f561d868f4a6c82e176311732a79c1">PIN_PC11L_GMAC_GMDC</a> << 16) | MUX_PC11L_GMAC_GMDC)</td></tr>
|
||
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<tr class="separator:aff046f3aafc0b2b604b35d0f4efb6136"><td class="memSeparator" colspan="2"> </td></tr>
|
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<tr class="memitem:aba720483ec121b73f8bac1bd25130bc0"><td class="memItemLeft" align="right" valign="top"><a id="aba720483ec121b73f8bac1bd25130bc0"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC11L_GMAC_GMDC</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 11)</td></tr>
|
||
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<tr class="separator:aba720483ec121b73f8bac1bd25130bc0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1111da8cfd48df4f4e3119744075b4a1"><td class="memItemLeft" align="right" valign="top"><a id="a1111da8cfd48df4f4e3119744075b4a1"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1111da8cfd48df4f4e3119744075b4a1">PIN_PA21L_GMAC_GMDIO</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(21)</td></tr>
|
||
|
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<tr class="memdesc:a1111da8cfd48df4f4e3119744075b4a1"><td class="mdescLeft"> </td><td class="mdescRight">GMAC signal: GMDIO on PA21 mux L. <br /></td></tr>
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||
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<tr class="separator:a1111da8cfd48df4f4e3119744075b4a1"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a308413b50e83c59d6aeadcd7f8fbb9fb"><td class="memItemLeft" align="right" valign="top"><a id="a308413b50e83c59d6aeadcd7f8fbb9fb"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA21L_GMAC_GMDIO</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
|
||
|
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<tr class="separator:a308413b50e83c59d6aeadcd7f8fbb9fb"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:acc62b95595f5dacd852837c3049a06de"><td class="memItemLeft" align="right" valign="top"><a id="acc62b95595f5dacd852837c3049a06de"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA21L_GMAC_GMDIO</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a1111da8cfd48df4f4e3119744075b4a1">PIN_PA21L_GMAC_GMDIO</a> << 16) | MUX_PA21L_GMAC_GMDIO)</td></tr>
|
||
|
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<tr class="separator:acc62b95595f5dacd852837c3049a06de"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:af0bb3de64ecc2c7ef03916ea4446a069"><td class="memItemLeft" align="right" valign="top"><a id="af0bb3de64ecc2c7ef03916ea4446a069"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA21L_GMAC_GMDIO</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 21)</td></tr>
|
||
|
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<tr class="separator:af0bb3de64ecc2c7ef03916ea4446a069"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:afa846cf5d0331debc99f1dbc8387a36e"><td class="memItemLeft" align="right" valign="top"><a id="afa846cf5d0331debc99f1dbc8387a36e"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#afa846cf5d0331debc99f1dbc8387a36e">PIN_PB15L_GMAC_GMDIO</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(47)</td></tr>
|
||
|
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<tr class="memdesc:afa846cf5d0331debc99f1dbc8387a36e"><td class="mdescLeft"> </td><td class="mdescRight">GMAC signal: GMDIO on PB15 mux L. <br /></td></tr>
|
||
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<tr class="separator:afa846cf5d0331debc99f1dbc8387a36e"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a91f178f3ca18d508eed7c5e0f212d8da"><td class="memItemLeft" align="right" valign="top"><a id="a91f178f3ca18d508eed7c5e0f212d8da"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB15L_GMAC_GMDIO</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
|
||
|
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<tr class="separator:a91f178f3ca18d508eed7c5e0f212d8da"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a5ea89bb3ef8e0a06098586c2d89a7ca7"><td class="memItemLeft" align="right" valign="top"><a id="a5ea89bb3ef8e0a06098586c2d89a7ca7"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB15L_GMAC_GMDIO</b>   ((<a class="el" href="pio_2same54p20a_8h.html#afa846cf5d0331debc99f1dbc8387a36e">PIN_PB15L_GMAC_GMDIO</a> << 16) | MUX_PB15L_GMAC_GMDIO)</td></tr>
|
||
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<tr class="separator:a5ea89bb3ef8e0a06098586c2d89a7ca7"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:a7143d6bb98211a0be1f605bde959e22f"><td class="memItemLeft" align="right" valign="top"><a id="a7143d6bb98211a0be1f605bde959e22f"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB15L_GMAC_GMDIO</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 15)</td></tr>
|
||
|
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<tr class="separator:a7143d6bb98211a0be1f605bde959e22f"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:a54ec704f5561b7da7e544b787ef26df7"><td class="memItemLeft" align="right" valign="top"><a id="a54ec704f5561b7da7e544b787ef26df7"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a54ec704f5561b7da7e544b787ef26df7">PIN_PC12L_GMAC_GMDIO</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(76)</td></tr>
|
||
|
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<tr class="memdesc:a54ec704f5561b7da7e544b787ef26df7"><td class="mdescLeft"> </td><td class="mdescRight">GMAC signal: GMDIO on PC12 mux L. <br /></td></tr>
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||
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<tr class="separator:a54ec704f5561b7da7e544b787ef26df7"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:ae8c76b6cc33fa6823afcd576a52aaa9c"><td class="memItemLeft" align="right" valign="top"><a id="ae8c76b6cc33fa6823afcd576a52aaa9c"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC12L_GMAC_GMDIO</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
|
||
|
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<tr class="separator:ae8c76b6cc33fa6823afcd576a52aaa9c"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a4cfa0287850fe4734deb40ae78bc4912"><td class="memItemLeft" align="right" valign="top"><a id="a4cfa0287850fe4734deb40ae78bc4912"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC12L_GMAC_GMDIO</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a54ec704f5561b7da7e544b787ef26df7">PIN_PC12L_GMAC_GMDIO</a> << 16) | MUX_PC12L_GMAC_GMDIO)</td></tr>
|
||
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<tr class="separator:a4cfa0287850fe4734deb40ae78bc4912"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a01c1be97c4d0d62caf68a94c326281ca"><td class="memItemLeft" align="right" valign="top"><a id="a01c1be97c4d0d62caf68a94c326281ca"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC12L_GMAC_GMDIO</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 12)</td></tr>
|
||
|
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<tr class="separator:a01c1be97c4d0d62caf68a94c326281ca"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a3d056a847e807035865ed436adc526b5"><td class="memItemLeft" align="right" valign="top"><a id="a3d056a847e807035865ed436adc526b5"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3d056a847e807035865ed436adc526b5">PIN_PA13L_GMAC_GRX0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
|
||
|
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<tr class="memdesc:a3d056a847e807035865ed436adc526b5"><td class="mdescLeft"> </td><td class="mdescRight">GMAC signal: GRX0 on PA13 mux L. <br /></td></tr>
|
||
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<tr class="separator:a3d056a847e807035865ed436adc526b5"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a027d172034a36ff771e41c92566073f4"><td class="memItemLeft" align="right" valign="top"><a id="a027d172034a36ff771e41c92566073f4"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA13L_GMAC_GRX0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
|
||
|
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<tr class="separator:a027d172034a36ff771e41c92566073f4"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:ad3337690ec92787fc80512b15681cfa0"><td class="memItemLeft" align="right" valign="top"><a id="ad3337690ec92787fc80512b15681cfa0"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA13L_GMAC_GRX0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a3d056a847e807035865ed436adc526b5">PIN_PA13L_GMAC_GRX0</a> << 16) | MUX_PA13L_GMAC_GRX0)</td></tr>
|
||
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<tr class="separator:ad3337690ec92787fc80512b15681cfa0"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a1017ee86bfada3b37e4daf54956817fd"><td class="memItemLeft" align="right" valign="top"><a id="a1017ee86bfada3b37e4daf54956817fd"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA13L_GMAC_GRX0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 13)</td></tr>
|
||
|
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<tr class="separator:a1017ee86bfada3b37e4daf54956817fd"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a52ea5e39f29541db121496db418c807c"><td class="memItemLeft" align="right" valign="top"><a id="a52ea5e39f29541db121496db418c807c"></a>
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||
|
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a52ea5e39f29541db121496db418c807c">PIN_PA12L_GMAC_GRX1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
|
||
|
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<tr class="memdesc:a52ea5e39f29541db121496db418c807c"><td class="mdescLeft"> </td><td class="mdescRight">GMAC signal: GRX1 on PA12 mux L. <br /></td></tr>
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||
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<tr class="separator:a52ea5e39f29541db121496db418c807c"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a8d8bc22769f348f93fad1f2d2f59ada4"><td class="memItemLeft" align="right" valign="top"><a id="a8d8bc22769f348f93fad1f2d2f59ada4"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA12L_GMAC_GRX1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
|
||
|
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<tr class="separator:a8d8bc22769f348f93fad1f2d2f59ada4"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:abbd3c419d4e7e4c8349a6a459f7dd083"><td class="memItemLeft" align="right" valign="top"><a id="abbd3c419d4e7e4c8349a6a459f7dd083"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA12L_GMAC_GRX1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a52ea5e39f29541db121496db418c807c">PIN_PA12L_GMAC_GRX1</a> << 16) | MUX_PA12L_GMAC_GRX1)</td></tr>
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||
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<tr class="separator:abbd3c419d4e7e4c8349a6a459f7dd083"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a7e360af1851145d3382faa03d5f86327"><td class="memItemLeft" align="right" valign="top"><a id="a7e360af1851145d3382faa03d5f86327"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA12L_GMAC_GRX1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 12)</td></tr>
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||
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<tr class="separator:a7e360af1851145d3382faa03d5f86327"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a53fbb225398a1ff984b8672582b20703"><td class="memItemLeft" align="right" valign="top"><a id="a53fbb225398a1ff984b8672582b20703"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a53fbb225398a1ff984b8672582b20703">PIN_PC15L_GMAC_GRX2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(79)</td></tr>
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<tr class="memdesc:a53fbb225398a1ff984b8672582b20703"><td class="mdescLeft"> </td><td class="mdescRight">GMAC signal: GRX2 on PC15 mux L. <br /></td></tr>
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<tr class="separator:a53fbb225398a1ff984b8672582b20703"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3e431855f5c5b7664edd3fe29d3ec961"><td class="memItemLeft" align="right" valign="top"><a id="a3e431855f5c5b7664edd3fe29d3ec961"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC15L_GMAC_GRX2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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<tr class="separator:a3e431855f5c5b7664edd3fe29d3ec961"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a61aec35bba6b1402f8bfc3fc022956ce"><td class="memItemLeft" align="right" valign="top"><a id="a61aec35bba6b1402f8bfc3fc022956ce"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC15L_GMAC_GRX2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a53fbb225398a1ff984b8672582b20703">PIN_PC15L_GMAC_GRX2</a> << 16) | MUX_PC15L_GMAC_GRX2)</td></tr>
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<tr class="separator:a61aec35bba6b1402f8bfc3fc022956ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae82110ef48d6215eeceabee0ed94a91f"><td class="memItemLeft" align="right" valign="top"><a id="ae82110ef48d6215eeceabee0ed94a91f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC15L_GMAC_GRX2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 15)</td></tr>
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<tr class="separator:ae82110ef48d6215eeceabee0ed94a91f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a980218818061ced2a630067ecf434bf2"><td class="memItemLeft" align="right" valign="top"><a id="a980218818061ced2a630067ecf434bf2"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a980218818061ced2a630067ecf434bf2">PIN_PC14L_GMAC_GRX3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(78)</td></tr>
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||
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<tr class="memdesc:a980218818061ced2a630067ecf434bf2"><td class="mdescLeft"> </td><td class="mdescRight">GMAC signal: GRX3 on PC14 mux L. <br /></td></tr>
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<tr class="separator:a980218818061ced2a630067ecf434bf2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a722978595fb5fde3fe4a72508f70294a"><td class="memItemLeft" align="right" valign="top"><a id="a722978595fb5fde3fe4a72508f70294a"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC14L_GMAC_GRX3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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||
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<tr class="separator:a722978595fb5fde3fe4a72508f70294a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac1230fd9aa089d6faa37d777b321a773"><td class="memItemLeft" align="right" valign="top"><a id="ac1230fd9aa089d6faa37d777b321a773"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC14L_GMAC_GRX3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a980218818061ced2a630067ecf434bf2">PIN_PC14L_GMAC_GRX3</a> << 16) | MUX_PC14L_GMAC_GRX3)</td></tr>
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<tr class="separator:ac1230fd9aa089d6faa37d777b321a773"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:addd03aab08b3714b6b2aa9dcd12f329a"><td class="memItemLeft" align="right" valign="top"><a id="addd03aab08b3714b6b2aa9dcd12f329a"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC14L_GMAC_GRX3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 14)</td></tr>
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||
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<tr class="separator:addd03aab08b3714b6b2aa9dcd12f329a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a044d4c611bed186005ab1d48c0415402"><td class="memItemLeft" align="right" valign="top"><a id="a044d4c611bed186005ab1d48c0415402"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a044d4c611bed186005ab1d48c0415402">PIN_PC18L_GMAC_GRXCK</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(82)</td></tr>
|
||
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<tr class="memdesc:a044d4c611bed186005ab1d48c0415402"><td class="mdescLeft"> </td><td class="mdescRight">GMAC signal: GRXCK on PC18 mux L. <br /></td></tr>
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<tr class="separator:a044d4c611bed186005ab1d48c0415402"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acbb0764e5c6110af3992bbf11a66b353"><td class="memItemLeft" align="right" valign="top"><a id="acbb0764e5c6110af3992bbf11a66b353"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC18L_GMAC_GRXCK</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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||
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<tr class="separator:acbb0764e5c6110af3992bbf11a66b353"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8e065703c4ce78a7a45cc222e0ae6bd1"><td class="memItemLeft" align="right" valign="top"><a id="a8e065703c4ce78a7a45cc222e0ae6bd1"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC18L_GMAC_GRXCK</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a044d4c611bed186005ab1d48c0415402">PIN_PC18L_GMAC_GRXCK</a> << 16) | MUX_PC18L_GMAC_GRXCK)</td></tr>
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<tr class="separator:a8e065703c4ce78a7a45cc222e0ae6bd1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0396221d294c1935078136f32ac7a421"><td class="memItemLeft" align="right" valign="top"><a id="a0396221d294c1935078136f32ac7a421"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC18L_GMAC_GRXCK</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 18)</td></tr>
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||
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<tr class="separator:a0396221d294c1935078136f32ac7a421"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a229488f377e575ee45b2e979d7b43524"><td class="memItemLeft" align="right" valign="top"><a id="a229488f377e575ee45b2e979d7b43524"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a229488f377e575ee45b2e979d7b43524">PIN_PC20L_GMAC_GRXDV</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(84)</td></tr>
|
||
|
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<tr class="memdesc:a229488f377e575ee45b2e979d7b43524"><td class="mdescLeft"> </td><td class="mdescRight">GMAC signal: GRXDV on PC20 mux L. <br /></td></tr>
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||
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<tr class="separator:a229488f377e575ee45b2e979d7b43524"><td class="memSeparator" colspan="2"> </td></tr>
|
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<tr class="memitem:a481838b79693940a9292810f7ea8dbdb"><td class="memItemLeft" align="right" valign="top"><a id="a481838b79693940a9292810f7ea8dbdb"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC20L_GMAC_GRXDV</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
|
||
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<tr class="separator:a481838b79693940a9292810f7ea8dbdb"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a7796096454d5b12c14cf2adff224d637"><td class="memItemLeft" align="right" valign="top"><a id="a7796096454d5b12c14cf2adff224d637"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC20L_GMAC_GRXDV</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a229488f377e575ee45b2e979d7b43524">PIN_PC20L_GMAC_GRXDV</a> << 16) | MUX_PC20L_GMAC_GRXDV)</td></tr>
|
||
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<tr class="separator:a7796096454d5b12c14cf2adff224d637"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a9f944ad8400abb3c58606949e00f154a"><td class="memItemLeft" align="right" valign="top"><a id="a9f944ad8400abb3c58606949e00f154a"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC20L_GMAC_GRXDV</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 20)</td></tr>
|
||
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<tr class="separator:a9f944ad8400abb3c58606949e00f154a"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:ab38fbd555279a84084dd4411daf47ed0"><td class="memItemLeft" align="right" valign="top"><a id="ab38fbd555279a84084dd4411daf47ed0"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab38fbd555279a84084dd4411daf47ed0">PIN_PA15L_GMAC_GRXER</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(15)</td></tr>
|
||
|
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<tr class="memdesc:ab38fbd555279a84084dd4411daf47ed0"><td class="mdescLeft"> </td><td class="mdescRight">GMAC signal: GRXER on PA15 mux L. <br /></td></tr>
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<tr class="separator:ab38fbd555279a84084dd4411daf47ed0"><td class="memSeparator" colspan="2"> </td></tr>
|
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<tr class="memitem:a5cca3f6aa81debb01a9c0aa128d78a1d"><td class="memItemLeft" align="right" valign="top"><a id="a5cca3f6aa81debb01a9c0aa128d78a1d"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA15L_GMAC_GRXER</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
|
||
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<tr class="separator:a5cca3f6aa81debb01a9c0aa128d78a1d"><td class="memSeparator" colspan="2"> </td></tr>
|
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<tr class="memitem:acd5ce59d73c811e9242eb7ee2b77131f"><td class="memItemLeft" align="right" valign="top"><a id="acd5ce59d73c811e9242eb7ee2b77131f"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA15L_GMAC_GRXER</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ab38fbd555279a84084dd4411daf47ed0">PIN_PA15L_GMAC_GRXER</a> << 16) | MUX_PA15L_GMAC_GRXER)</td></tr>
|
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<tr class="separator:acd5ce59d73c811e9242eb7ee2b77131f"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:adb52f4d28347d19c93a234b298af0be6"><td class="memItemLeft" align="right" valign="top"><a id="adb52f4d28347d19c93a234b298af0be6"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA15L_GMAC_GRXER</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 15)</td></tr>
|
||
|
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<tr class="separator:adb52f4d28347d19c93a234b298af0be6"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a19e3ba66a99a24b2b4eeb4a0c661af0c"><td class="memItemLeft" align="right" valign="top"><a id="a19e3ba66a99a24b2b4eeb4a0c661af0c"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a19e3ba66a99a24b2b4eeb4a0c661af0c">PIN_PA18L_GMAC_GTX0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(18)</td></tr>
|
||
|
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<tr class="memdesc:a19e3ba66a99a24b2b4eeb4a0c661af0c"><td class="mdescLeft"> </td><td class="mdescRight">GMAC signal: GTX0 on PA18 mux L. <br /></td></tr>
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||
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<tr class="separator:a19e3ba66a99a24b2b4eeb4a0c661af0c"><td class="memSeparator" colspan="2"> </td></tr>
|
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<tr class="memitem:ad5103094b15b1d09dbf033fae920a5d0"><td class="memItemLeft" align="right" valign="top"><a id="ad5103094b15b1d09dbf033fae920a5d0"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA18L_GMAC_GTX0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
|
||
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<tr class="separator:ad5103094b15b1d09dbf033fae920a5d0"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:aa7c42b4581745259debf07dbbbc2d9c9"><td class="memItemLeft" align="right" valign="top"><a id="aa7c42b4581745259debf07dbbbc2d9c9"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA18L_GMAC_GTX0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a19e3ba66a99a24b2b4eeb4a0c661af0c">PIN_PA18L_GMAC_GTX0</a> << 16) | MUX_PA18L_GMAC_GTX0)</td></tr>
|
||
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<tr class="separator:aa7c42b4581745259debf07dbbbc2d9c9"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a2177e3c9285ef49ffb4f89417e3f9378"><td class="memItemLeft" align="right" valign="top"><a id="a2177e3c9285ef49ffb4f89417e3f9378"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA18L_GMAC_GTX0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 18)</td></tr>
|
||
|
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<tr class="separator:a2177e3c9285ef49ffb4f89417e3f9378"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:aa379452684952e8b6e874ec782be44a4"><td class="memItemLeft" align="right" valign="top"><a id="aa379452684952e8b6e874ec782be44a4"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa379452684952e8b6e874ec782be44a4">PIN_PA19L_GMAC_GTX1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(19)</td></tr>
|
||
|
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<tr class="memdesc:aa379452684952e8b6e874ec782be44a4"><td class="mdescLeft"> </td><td class="mdescRight">GMAC signal: GTX1 on PA19 mux L. <br /></td></tr>
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||
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<tr class="separator:aa379452684952e8b6e874ec782be44a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a73450ff0e55b421e8880e9e7fa14947c"><td class="memItemLeft" align="right" valign="top"><a id="a73450ff0e55b421e8880e9e7fa14947c"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA19L_GMAC_GTX1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
|
||
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<tr class="separator:a73450ff0e55b421e8880e9e7fa14947c"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:acb5addbd47af5095beff956d00ee3b51"><td class="memItemLeft" align="right" valign="top"><a id="acb5addbd47af5095beff956d00ee3b51"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA19L_GMAC_GTX1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aa379452684952e8b6e874ec782be44a4">PIN_PA19L_GMAC_GTX1</a> << 16) | MUX_PA19L_GMAC_GTX1)</td></tr>
|
||
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<tr class="separator:acb5addbd47af5095beff956d00ee3b51"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:ab3deb7758bc114474d5053bd02c293cc"><td class="memItemLeft" align="right" valign="top"><a id="ab3deb7758bc114474d5053bd02c293cc"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA19L_GMAC_GTX1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 19)</td></tr>
|
||
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<tr class="separator:ab3deb7758bc114474d5053bd02c293cc"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:ab10a78f9bbdcaf1d4e89c89b78b5cc2c"><td class="memItemLeft" align="right" valign="top"><a id="ab10a78f9bbdcaf1d4e89c89b78b5cc2c"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab10a78f9bbdcaf1d4e89c89b78b5cc2c">PIN_PC16L_GMAC_GTX2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(80)</td></tr>
|
||
|
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<tr class="memdesc:ab10a78f9bbdcaf1d4e89c89b78b5cc2c"><td class="mdescLeft"> </td><td class="mdescRight">GMAC signal: GTX2 on PC16 mux L. <br /></td></tr>
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||
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<tr class="separator:ab10a78f9bbdcaf1d4e89c89b78b5cc2c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a52bc9829505e1ab47b3cf8f30103a819"><td class="memItemLeft" align="right" valign="top"><a id="a52bc9829505e1ab47b3cf8f30103a819"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC16L_GMAC_GTX2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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<tr class="separator:a52bc9829505e1ab47b3cf8f30103a819"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad3e37cc8cab64b84990a06bd793b22ba"><td class="memItemLeft" align="right" valign="top"><a id="ad3e37cc8cab64b84990a06bd793b22ba"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC16L_GMAC_GTX2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ab10a78f9bbdcaf1d4e89c89b78b5cc2c">PIN_PC16L_GMAC_GTX2</a> << 16) | MUX_PC16L_GMAC_GTX2)</td></tr>
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<tr class="separator:ad3e37cc8cab64b84990a06bd793b22ba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a804d3465d34de4d5e85dae0d8223420b"><td class="memItemLeft" align="right" valign="top"><a id="a804d3465d34de4d5e85dae0d8223420b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC16L_GMAC_GTX2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 16)</td></tr>
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<tr class="separator:a804d3465d34de4d5e85dae0d8223420b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a039cbb68078932607f57e5b0e82c1125"><td class="memItemLeft" align="right" valign="top"><a id="a039cbb68078932607f57e5b0e82c1125"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a039cbb68078932607f57e5b0e82c1125">PIN_PC17L_GMAC_GTX3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(81)</td></tr>
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||
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<tr class="memdesc:a039cbb68078932607f57e5b0e82c1125"><td class="mdescLeft"> </td><td class="mdescRight">GMAC signal: GTX3 on PC17 mux L. <br /></td></tr>
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<tr class="separator:a039cbb68078932607f57e5b0e82c1125"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3f0240c5c0a0b8628c4d2abf148e67c0"><td class="memItemLeft" align="right" valign="top"><a id="a3f0240c5c0a0b8628c4d2abf148e67c0"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC17L_GMAC_GTX3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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<tr class="separator:a3f0240c5c0a0b8628c4d2abf148e67c0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a24f9b481d2c69b9a536661571af674c2"><td class="memItemLeft" align="right" valign="top"><a id="a24f9b481d2c69b9a536661571af674c2"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC17L_GMAC_GTX3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a039cbb68078932607f57e5b0e82c1125">PIN_PC17L_GMAC_GTX3</a> << 16) | MUX_PC17L_GMAC_GTX3)</td></tr>
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<tr class="separator:a24f9b481d2c69b9a536661571af674c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a60f3eeec102a25db18d853ab171a4504"><td class="memItemLeft" align="right" valign="top"><a id="a60f3eeec102a25db18d853ab171a4504"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC17L_GMAC_GTX3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 17)</td></tr>
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||
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<tr class="separator:a60f3eeec102a25db18d853ab171a4504"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aab984c5af62b27d4dc46d7206a53804c"><td class="memItemLeft" align="right" valign="top"><a id="aab984c5af62b27d4dc46d7206a53804c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aab984c5af62b27d4dc46d7206a53804c">PIN_PA14L_GMAC_GTXCK</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
|
||
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<tr class="memdesc:aab984c5af62b27d4dc46d7206a53804c"><td class="mdescLeft"> </td><td class="mdescRight">GMAC signal: GTXCK on PA14 mux L. <br /></td></tr>
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<tr class="separator:aab984c5af62b27d4dc46d7206a53804c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0a90926792039e5b0e7aee7c49201c9e"><td class="memItemLeft" align="right" valign="top"><a id="a0a90926792039e5b0e7aee7c49201c9e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA14L_GMAC_GTXCK</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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<tr class="separator:a0a90926792039e5b0e7aee7c49201c9e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5dc43da9ab42bdbe27d07373782a4d64"><td class="memItemLeft" align="right" valign="top"><a id="a5dc43da9ab42bdbe27d07373782a4d64"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA14L_GMAC_GTXCK</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aab984c5af62b27d4dc46d7206a53804c">PIN_PA14L_GMAC_GTXCK</a> << 16) | MUX_PA14L_GMAC_GTXCK)</td></tr>
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<tr class="separator:a5dc43da9ab42bdbe27d07373782a4d64"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a066c3f048cbebfa24bd24954a5cff717"><td class="memItemLeft" align="right" valign="top"><a id="a066c3f048cbebfa24bd24954a5cff717"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA14L_GMAC_GTXCK</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 14)</td></tr>
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||
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<tr class="separator:a066c3f048cbebfa24bd24954a5cff717"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a91ca86d30c57c664d734ca145699e43f"><td class="memItemLeft" align="right" valign="top"><a id="a91ca86d30c57c664d734ca145699e43f"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a91ca86d30c57c664d734ca145699e43f">PIN_PA17L_GMAC_GTXEN</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(17)</td></tr>
|
||
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<tr class="memdesc:a91ca86d30c57c664d734ca145699e43f"><td class="mdescLeft"> </td><td class="mdescRight">GMAC signal: GTXEN on PA17 mux L. <br /></td></tr>
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<tr class="separator:a91ca86d30c57c664d734ca145699e43f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab5ac1f8a1190c846f7d127d2b47f3d1c"><td class="memItemLeft" align="right" valign="top"><a id="ab5ac1f8a1190c846f7d127d2b47f3d1c"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA17L_GMAC_GTXEN</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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||
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<tr class="separator:ab5ac1f8a1190c846f7d127d2b47f3d1c"><td class="memSeparator" colspan="2"> </td></tr>
|
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<tr class="memitem:adc540eff2d0e1490024da8ece26cc54b"><td class="memItemLeft" align="right" valign="top"><a id="adc540eff2d0e1490024da8ece26cc54b"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA17L_GMAC_GTXEN</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a91ca86d30c57c664d734ca145699e43f">PIN_PA17L_GMAC_GTXEN</a> << 16) | MUX_PA17L_GMAC_GTXEN)</td></tr>
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<tr class="separator:adc540eff2d0e1490024da8ece26cc54b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a88f17d66d3cc7733a4f4949d8f91b0ce"><td class="memItemLeft" align="right" valign="top"><a id="a88f17d66d3cc7733a4f4949d8f91b0ce"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA17L_GMAC_GTXEN</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 17)</td></tr>
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||
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<tr class="separator:a88f17d66d3cc7733a4f4949d8f91b0ce"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:ad41704e2ca1173d39afcb2e451ace3aa"><td class="memItemLeft" align="right" valign="top"><a id="ad41704e2ca1173d39afcb2e451ace3aa"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad41704e2ca1173d39afcb2e451ace3aa">PIN_PC19L_GMAC_GTXER</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(83)</td></tr>
|
||
|
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<tr class="memdesc:ad41704e2ca1173d39afcb2e451ace3aa"><td class="mdescLeft"> </td><td class="mdescRight">GMAC signal: GTXER on PC19 mux L. <br /></td></tr>
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||
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<tr class="separator:ad41704e2ca1173d39afcb2e451ace3aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1cbe36133610d6d8e7e54524e87d5138"><td class="memItemLeft" align="right" valign="top"><a id="a1cbe36133610d6d8e7e54524e87d5138"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC19L_GMAC_GTXER</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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||
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<tr class="separator:a1cbe36133610d6d8e7e54524e87d5138"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a13eb839082e051e04c1c8a51b6a0b2bb"><td class="memItemLeft" align="right" valign="top"><a id="a13eb839082e051e04c1c8a51b6a0b2bb"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC19L_GMAC_GTXER</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ad41704e2ca1173d39afcb2e451ace3aa">PIN_PC19L_GMAC_GTXER</a> << 16) | MUX_PC19L_GMAC_GTXER)</td></tr>
|
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<tr class="separator:a13eb839082e051e04c1c8a51b6a0b2bb"><td class="memSeparator" colspan="2"> </td></tr>
|
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<tr class="memitem:a839180226f38454202d2496b81516293"><td class="memItemLeft" align="right" valign="top"><a id="a839180226f38454202d2496b81516293"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC19L_GMAC_GTXER</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 19)</td></tr>
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||
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<tr class="separator:a839180226f38454202d2496b81516293"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a5d94ca9b5e5a77c255a7b431e27670e5"><td class="memItemLeft" align="right" valign="top"><a id="a5d94ca9b5e5a77c255a7b431e27670e5"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5d94ca9b5e5a77c255a7b431e27670e5">PIN_PA14F_TCC2_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
|
||
|
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<tr class="memdesc:a5d94ca9b5e5a77c255a7b431e27670e5"><td class="mdescLeft"> </td><td class="mdescRight">TCC2 signal: WO0 on PA14 mux F. <br /></td></tr>
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||
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<tr class="separator:a5d94ca9b5e5a77c255a7b431e27670e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7aaa99599be177c84fd6e6478920deea"><td class="memItemLeft" align="right" valign="top"><a id="a7aaa99599be177c84fd6e6478920deea"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA14F_TCC2_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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||
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<tr class="separator:a7aaa99599be177c84fd6e6478920deea"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a51d0b573dea75c1d6c5647fe377b97a3"><td class="memItemLeft" align="right" valign="top"><a id="a51d0b573dea75c1d6c5647fe377b97a3"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA14F_TCC2_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a5d94ca9b5e5a77c255a7b431e27670e5">PIN_PA14F_TCC2_WO0</a> << 16) | MUX_PA14F_TCC2_WO0)</td></tr>
|
||
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<tr class="separator:a51d0b573dea75c1d6c5647fe377b97a3"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:aa75180335259addf592cec4cc9b02906"><td class="memItemLeft" align="right" valign="top"><a id="aa75180335259addf592cec4cc9b02906"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA14F_TCC2_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 14)</td></tr>
|
||
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<tr class="separator:aa75180335259addf592cec4cc9b02906"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:acb6632c273ffe1d343e0a36efd5e0dc9"><td class="memItemLeft" align="right" valign="top"><a id="acb6632c273ffe1d343e0a36efd5e0dc9"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#acb6632c273ffe1d343e0a36efd5e0dc9">PIN_PA30F_TCC2_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(30)</td></tr>
|
||
|
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<tr class="memdesc:acb6632c273ffe1d343e0a36efd5e0dc9"><td class="mdescLeft"> </td><td class="mdescRight">TCC2 signal: WO0 on PA30 mux F. <br /></td></tr>
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||
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<tr class="separator:acb6632c273ffe1d343e0a36efd5e0dc9"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a3bca90689c2730cd427164fdcdcb4b8d"><td class="memItemLeft" align="right" valign="top"><a id="a3bca90689c2730cd427164fdcdcb4b8d"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA30F_TCC2_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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||
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<tr class="separator:a3bca90689c2730cd427164fdcdcb4b8d"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a3c1e14d99a91c0c3b60c3e30e6923060"><td class="memItemLeft" align="right" valign="top"><a id="a3c1e14d99a91c0c3b60c3e30e6923060"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA30F_TCC2_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#acb6632c273ffe1d343e0a36efd5e0dc9">PIN_PA30F_TCC2_WO0</a> << 16) | MUX_PA30F_TCC2_WO0)</td></tr>
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||
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<tr class="separator:a3c1e14d99a91c0c3b60c3e30e6923060"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a93523fd3353b0b2074c4f114e4aa868c"><td class="memItemLeft" align="right" valign="top"><a id="a93523fd3353b0b2074c4f114e4aa868c"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA30F_TCC2_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 30)</td></tr>
|
||
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<tr class="separator:a93523fd3353b0b2074c4f114e4aa868c"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:ac37059c6ee20ff4531bdda29a275f8ec"><td class="memItemLeft" align="right" valign="top"><a id="ac37059c6ee20ff4531bdda29a275f8ec"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac37059c6ee20ff4531bdda29a275f8ec">PIN_PA15F_TCC2_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(15)</td></tr>
|
||
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<tr class="memdesc:ac37059c6ee20ff4531bdda29a275f8ec"><td class="mdescLeft"> </td><td class="mdescRight">TCC2 signal: WO1 on PA15 mux F. <br /></td></tr>
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||
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<tr class="separator:ac37059c6ee20ff4531bdda29a275f8ec"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:acf14dc543d8551c4b94da792809e0939"><td class="memItemLeft" align="right" valign="top"><a id="acf14dc543d8551c4b94da792809e0939"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA15F_TCC2_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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||
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<tr class="separator:acf14dc543d8551c4b94da792809e0939"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac914891ad4ee0f70ad7279f5453cb6ed"><td class="memItemLeft" align="right" valign="top"><a id="ac914891ad4ee0f70ad7279f5453cb6ed"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA15F_TCC2_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ac37059c6ee20ff4531bdda29a275f8ec">PIN_PA15F_TCC2_WO1</a> << 16) | MUX_PA15F_TCC2_WO1)</td></tr>
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<tr class="memitem:ab56bf3bfe54af5ba72c956f97b46a25a"><td class="memItemLeft" align="right" valign="top"><a id="ab56bf3bfe54af5ba72c956f97b46a25a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA15F_TCC2_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 15)</td></tr>
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<tr class="separator:ab56bf3bfe54af5ba72c956f97b46a25a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af36d2e860cbd5724583b1a383fa1d16d"><td class="memItemLeft" align="right" valign="top"><a id="af36d2e860cbd5724583b1a383fa1d16d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af36d2e860cbd5724583b1a383fa1d16d">PIN_PA31F_TCC2_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(31)</td></tr>
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<tr class="memdesc:af36d2e860cbd5724583b1a383fa1d16d"><td class="mdescLeft"> </td><td class="mdescRight">TCC2 signal: WO1 on PA31 mux F. <br /></td></tr>
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<tr class="separator:af36d2e860cbd5724583b1a383fa1d16d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a872ff670748002db9406358b2badecf8"><td class="memItemLeft" align="right" valign="top"><a id="a872ff670748002db9406358b2badecf8"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA31F_TCC2_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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<tr class="separator:a872ff670748002db9406358b2badecf8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae11644501706ce3ca845fdbb397658f0"><td class="memItemLeft" align="right" valign="top"><a id="ae11644501706ce3ca845fdbb397658f0"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA31F_TCC2_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#af36d2e860cbd5724583b1a383fa1d16d">PIN_PA31F_TCC2_WO1</a> << 16) | MUX_PA31F_TCC2_WO1)</td></tr>
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<tr class="separator:ae11644501706ce3ca845fdbb397658f0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9e347a6584237cfe25dce9a67814370d"><td class="memItemLeft" align="right" valign="top"><a id="a9e347a6584237cfe25dce9a67814370d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA31F_TCC2_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 31)</td></tr>
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<tr class="separator:a9e347a6584237cfe25dce9a67814370d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a617b0d99689e8a572aca78e221c0f6ce"><td class="memItemLeft" align="right" valign="top"><a id="a617b0d99689e8a572aca78e221c0f6ce"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a617b0d99689e8a572aca78e221c0f6ce">PIN_PA24F_TCC2_WO2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(24)</td></tr>
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<tr class="memdesc:a617b0d99689e8a572aca78e221c0f6ce"><td class="mdescLeft"> </td><td class="mdescRight">TCC2 signal: WO2 on PA24 mux F. <br /></td></tr>
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<tr class="separator:a617b0d99689e8a572aca78e221c0f6ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9281ed8f139c7d29e4f91dab7ae645cc"><td class="memItemLeft" align="right" valign="top"><a id="a9281ed8f139c7d29e4f91dab7ae645cc"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA24F_TCC2_WO2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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<tr class="separator:a9281ed8f139c7d29e4f91dab7ae645cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a83fabb0b10478e1d8bf896850fdd7152"><td class="memItemLeft" align="right" valign="top"><a id="a83fabb0b10478e1d8bf896850fdd7152"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA24F_TCC2_WO2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a617b0d99689e8a572aca78e221c0f6ce">PIN_PA24F_TCC2_WO2</a> << 16) | MUX_PA24F_TCC2_WO2)</td></tr>
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<tr class="separator:a83fabb0b10478e1d8bf896850fdd7152"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a27a02a87ffb3a5179589fe234bbd049b"><td class="memItemLeft" align="right" valign="top"><a id="a27a02a87ffb3a5179589fe234bbd049b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA24F_TCC2_WO2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 24)</td></tr>
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<tr class="separator:a27a02a87ffb3a5179589fe234bbd049b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af908ac4a465bba22033067bae2caf121"><td class="memItemLeft" align="right" valign="top"><a id="af908ac4a465bba22033067bae2caf121"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af908ac4a465bba22033067bae2caf121">PIN_PB02F_TCC2_WO2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(34)</td></tr>
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<tr class="memdesc:af908ac4a465bba22033067bae2caf121"><td class="mdescLeft"> </td><td class="mdescRight">TCC2 signal: WO2 on PB02 mux F. <br /></td></tr>
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<tr class="separator:af908ac4a465bba22033067bae2caf121"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a06a8091819107fb89527368047a1a167"><td class="memItemLeft" align="right" valign="top"><a id="a06a8091819107fb89527368047a1a167"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB02F_TCC2_WO2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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<tr class="separator:a06a8091819107fb89527368047a1a167"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a520288867eb236dabaf9140a43c66956"><td class="memItemLeft" align="right" valign="top"><a id="a520288867eb236dabaf9140a43c66956"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB02F_TCC2_WO2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#af908ac4a465bba22033067bae2caf121">PIN_PB02F_TCC2_WO2</a> << 16) | MUX_PB02F_TCC2_WO2)</td></tr>
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<tr class="separator:a520288867eb236dabaf9140a43c66956"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0cac8d1fd41cea19d0e4912eba0ad074"><td class="memItemLeft" align="right" valign="top"><a id="a0cac8d1fd41cea19d0e4912eba0ad074"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB02F_TCC2_WO2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 2)</td></tr>
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<tr class="separator:a0cac8d1fd41cea19d0e4912eba0ad074"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0a9beb6f78b08fb3136e72255b99de80"><td class="memItemLeft" align="right" valign="top"><a id="a0a9beb6f78b08fb3136e72255b99de80"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0a9beb6f78b08fb3136e72255b99de80">PIN_PB12F_TCC3_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(44)</td></tr>
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||
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<tr class="memdesc:a0a9beb6f78b08fb3136e72255b99de80"><td class="mdescLeft"> </td><td class="mdescRight">TCC3 signal: WO0 on PB12 mux F. <br /></td></tr>
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<tr class="separator:a0a9beb6f78b08fb3136e72255b99de80"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a972c70c42e6c96650ffd465b8703270a"><td class="memItemLeft" align="right" valign="top"><a id="a972c70c42e6c96650ffd465b8703270a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB12F_TCC3_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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<tr class="separator:a972c70c42e6c96650ffd465b8703270a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8efb525b0c33c34cdd51095f0be7995d"><td class="memItemLeft" align="right" valign="top"><a id="a8efb525b0c33c34cdd51095f0be7995d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB12F_TCC3_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a0a9beb6f78b08fb3136e72255b99de80">PIN_PB12F_TCC3_WO0</a> << 16) | MUX_PB12F_TCC3_WO0)</td></tr>
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<tr class="separator:a8efb525b0c33c34cdd51095f0be7995d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7f5e28c62ea6e9200425dd71ac9fffe7"><td class="memItemLeft" align="right" valign="top"><a id="a7f5e28c62ea6e9200425dd71ac9fffe7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB12F_TCC3_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 12)</td></tr>
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<tr class="separator:a7f5e28c62ea6e9200425dd71ac9fffe7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab8943f90bf7e6e08497e8d3e118303f8"><td class="memItemLeft" align="right" valign="top"><a id="ab8943f90bf7e6e08497e8d3e118303f8"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab8943f90bf7e6e08497e8d3e118303f8">PIN_PB16F_TCC3_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(48)</td></tr>
|
||
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<tr class="memdesc:ab8943f90bf7e6e08497e8d3e118303f8"><td class="mdescLeft"> </td><td class="mdescRight">TCC3 signal: WO0 on PB16 mux F. <br /></td></tr>
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<tr class="separator:ab8943f90bf7e6e08497e8d3e118303f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2f7b801b03fe448d97ba075bcf9433b3"><td class="memItemLeft" align="right" valign="top"><a id="a2f7b801b03fe448d97ba075bcf9433b3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB16F_TCC3_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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<tr class="separator:a2f7b801b03fe448d97ba075bcf9433b3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3f622ecaf73e402ba204a5d6b25883f0"><td class="memItemLeft" align="right" valign="top"><a id="a3f622ecaf73e402ba204a5d6b25883f0"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB16F_TCC3_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ab8943f90bf7e6e08497e8d3e118303f8">PIN_PB16F_TCC3_WO0</a> << 16) | MUX_PB16F_TCC3_WO0)</td></tr>
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<tr class="separator:a3f622ecaf73e402ba204a5d6b25883f0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a16846a69b5a98fbb028afe9baf63567e"><td class="memItemLeft" align="right" valign="top"><a id="a16846a69b5a98fbb028afe9baf63567e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB16F_TCC3_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 16)</td></tr>
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<tr class="separator:a16846a69b5a98fbb028afe9baf63567e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab75b553315a9ef7d5fd966c9d3ad1ea4"><td class="memItemLeft" align="right" valign="top"><a id="ab75b553315a9ef7d5fd966c9d3ad1ea4"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab75b553315a9ef7d5fd966c9d3ad1ea4">PIN_PB13F_TCC3_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(45)</td></tr>
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||
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<tr class="memdesc:ab75b553315a9ef7d5fd966c9d3ad1ea4"><td class="mdescLeft"> </td><td class="mdescRight">TCC3 signal: WO1 on PB13 mux F. <br /></td></tr>
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<tr class="separator:ab75b553315a9ef7d5fd966c9d3ad1ea4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2884683a26112493e40190f140a1a636"><td class="memItemLeft" align="right" valign="top"><a id="a2884683a26112493e40190f140a1a636"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB13F_TCC3_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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<tr class="separator:a2884683a26112493e40190f140a1a636"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5c5d2f01f31711b89a9026ba34052c46"><td class="memItemLeft" align="right" valign="top"><a id="a5c5d2f01f31711b89a9026ba34052c46"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB13F_TCC3_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ab75b553315a9ef7d5fd966c9d3ad1ea4">PIN_PB13F_TCC3_WO1</a> << 16) | MUX_PB13F_TCC3_WO1)</td></tr>
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<tr class="separator:a5c5d2f01f31711b89a9026ba34052c46"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6e84f65a6176020d23fd94673956f6ac"><td class="memItemLeft" align="right" valign="top"><a id="a6e84f65a6176020d23fd94673956f6ac"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB13F_TCC3_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 13)</td></tr>
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<tr class="separator:a6e84f65a6176020d23fd94673956f6ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ace6df54793a54cda67265be42b6add36"><td class="memItemLeft" align="right" valign="top"><a id="ace6df54793a54cda67265be42b6add36"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ace6df54793a54cda67265be42b6add36">PIN_PB17F_TCC3_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(49)</td></tr>
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||
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<tr class="memdesc:ace6df54793a54cda67265be42b6add36"><td class="mdescLeft"> </td><td class="mdescRight">TCC3 signal: WO1 on PB17 mux F. <br /></td></tr>
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<tr class="separator:ace6df54793a54cda67265be42b6add36"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a10c6ea2ed1443850ea881ccaddaa1d91"><td class="memItemLeft" align="right" valign="top"><a id="a10c6ea2ed1443850ea881ccaddaa1d91"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB17F_TCC3_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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<tr class="separator:a10c6ea2ed1443850ea881ccaddaa1d91"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aea556cbca896816c0f1f486c37d27842"><td class="memItemLeft" align="right" valign="top"><a id="aea556cbca896816c0f1f486c37d27842"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB17F_TCC3_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ace6df54793a54cda67265be42b6add36">PIN_PB17F_TCC3_WO1</a> << 16) | MUX_PB17F_TCC3_WO1)</td></tr>
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<tr class="separator:aea556cbca896816c0f1f486c37d27842"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a336491e29cbfcb032880f5285cfc27b9"><td class="memItemLeft" align="right" valign="top"><a id="a336491e29cbfcb032880f5285cfc27b9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB17F_TCC3_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 17)</td></tr>
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<tr class="separator:a336491e29cbfcb032880f5285cfc27b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa61338ee45dceb3ba53886cce92e37a2"><td class="memItemLeft" align="right" valign="top"><a id="aa61338ee45dceb3ba53886cce92e37a2"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa61338ee45dceb3ba53886cce92e37a2">PIN_PA22E_TC4_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(22)</td></tr>
|
||
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<tr class="memdesc:aa61338ee45dceb3ba53886cce92e37a2"><td class="mdescLeft"> </td><td class="mdescRight">TC4 signal: WO0 on PA22 mux E. <br /></td></tr>
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<tr class="separator:aa61338ee45dceb3ba53886cce92e37a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3cae00ac899046d6b1b439d9e71215ae"><td class="memItemLeft" align="right" valign="top"><a id="a3cae00ac899046d6b1b439d9e71215ae"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA22E_TC4_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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||
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<tr class="separator:a3cae00ac899046d6b1b439d9e71215ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a85b670a8dfe069c5b8ccccb5b4cbb7ea"><td class="memItemLeft" align="right" valign="top"><a id="a85b670a8dfe069c5b8ccccb5b4cbb7ea"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA22E_TC4_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aa61338ee45dceb3ba53886cce92e37a2">PIN_PA22E_TC4_WO0</a> << 16) | MUX_PA22E_TC4_WO0)</td></tr>
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<tr class="separator:a85b670a8dfe069c5b8ccccb5b4cbb7ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8d5ee5c91d3c861e7ec5aec1c82e09e1"><td class="memItemLeft" align="right" valign="top"><a id="a8d5ee5c91d3c861e7ec5aec1c82e09e1"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA22E_TC4_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 22)</td></tr>
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||
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<tr class="separator:a8d5ee5c91d3c861e7ec5aec1c82e09e1"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a5653360fe2e5042da32f829936f8daaf"><td class="memItemLeft" align="right" valign="top"><a id="a5653360fe2e5042da32f829936f8daaf"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5653360fe2e5042da32f829936f8daaf">PIN_PB08E_TC4_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(40)</td></tr>
|
||
|
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<tr class="memdesc:a5653360fe2e5042da32f829936f8daaf"><td class="mdescLeft"> </td><td class="mdescRight">TC4 signal: WO0 on PB08 mux E. <br /></td></tr>
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<tr class="separator:a5653360fe2e5042da32f829936f8daaf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a36fe1b62dca01e9293a83dd547760cfa"><td class="memItemLeft" align="right" valign="top"><a id="a36fe1b62dca01e9293a83dd547760cfa"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB08E_TC4_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
|
||
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<tr class="separator:a36fe1b62dca01e9293a83dd547760cfa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8d5bfdc4dda68751784990c8dce3e405"><td class="memItemLeft" align="right" valign="top"><a id="a8d5bfdc4dda68751784990c8dce3e405"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB08E_TC4_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a5653360fe2e5042da32f829936f8daaf">PIN_PB08E_TC4_WO0</a> << 16) | MUX_PB08E_TC4_WO0)</td></tr>
|
||
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<tr class="separator:a8d5bfdc4dda68751784990c8dce3e405"><td class="memSeparator" colspan="2"> </td></tr>
|
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<tr class="memitem:a178302f7e4b920c54b6b22da41ed4799"><td class="memItemLeft" align="right" valign="top"><a id="a178302f7e4b920c54b6b22da41ed4799"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB08E_TC4_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 8)</td></tr>
|
||
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<tr class="separator:a178302f7e4b920c54b6b22da41ed4799"><td class="memSeparator" colspan="2"> </td></tr>
|
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<tr class="memitem:ab6b809fa2a40673cd40cbbc7bd930a9d"><td class="memItemLeft" align="right" valign="top"><a id="ab6b809fa2a40673cd40cbbc7bd930a9d"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab6b809fa2a40673cd40cbbc7bd930a9d">PIN_PB12E_TC4_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(44)</td></tr>
|
||
|
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<tr class="memdesc:ab6b809fa2a40673cd40cbbc7bd930a9d"><td class="mdescLeft"> </td><td class="mdescRight">TC4 signal: WO0 on PB12 mux E. <br /></td></tr>
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||
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<tr class="separator:ab6b809fa2a40673cd40cbbc7bd930a9d"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:ab9c85ac354f387eb40aaec5c121b653b"><td class="memItemLeft" align="right" valign="top"><a id="ab9c85ac354f387eb40aaec5c121b653b"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB12E_TC4_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
|
||
|
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<tr class="separator:ab9c85ac354f387eb40aaec5c121b653b"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:ad3787c9572bd467c9a9ff56659c03dc2"><td class="memItemLeft" align="right" valign="top"><a id="ad3787c9572bd467c9a9ff56659c03dc2"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB12E_TC4_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ab6b809fa2a40673cd40cbbc7bd930a9d">PIN_PB12E_TC4_WO0</a> << 16) | MUX_PB12E_TC4_WO0)</td></tr>
|
||
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<tr class="separator:ad3787c9572bd467c9a9ff56659c03dc2"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a3aa93a02443cfb797547cfd58be6dc6f"><td class="memItemLeft" align="right" valign="top"><a id="a3aa93a02443cfb797547cfd58be6dc6f"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB12E_TC4_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 12)</td></tr>
|
||
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<tr class="separator:a3aa93a02443cfb797547cfd58be6dc6f"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:ab3b4ecc178d179b8b043c03dcb378e2b"><td class="memItemLeft" align="right" valign="top"><a id="ab3b4ecc178d179b8b043c03dcb378e2b"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab3b4ecc178d179b8b043c03dcb378e2b">PIN_PA23E_TC4_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(23)</td></tr>
|
||
|
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<tr class="memdesc:ab3b4ecc178d179b8b043c03dcb378e2b"><td class="mdescLeft"> </td><td class="mdescRight">TC4 signal: WO1 on PA23 mux E. <br /></td></tr>
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||
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<tr class="separator:ab3b4ecc178d179b8b043c03dcb378e2b"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a1898c89c7d338876e1be45f1497ecda1"><td class="memItemLeft" align="right" valign="top"><a id="a1898c89c7d338876e1be45f1497ecda1"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA23E_TC4_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
|
||
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<tr class="separator:a1898c89c7d338876e1be45f1497ecda1"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a76c55e684c8169637b7d737971d70d45"><td class="memItemLeft" align="right" valign="top"><a id="a76c55e684c8169637b7d737971d70d45"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA23E_TC4_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ab3b4ecc178d179b8b043c03dcb378e2b">PIN_PA23E_TC4_WO1</a> << 16) | MUX_PA23E_TC4_WO1)</td></tr>
|
||
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<tr class="separator:a76c55e684c8169637b7d737971d70d45"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a4f2ad5bb6e24a68c7c6d9f87dd6b1d13"><td class="memItemLeft" align="right" valign="top"><a id="a4f2ad5bb6e24a68c7c6d9f87dd6b1d13"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA23E_TC4_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 23)</td></tr>
|
||
|
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<tr class="separator:a4f2ad5bb6e24a68c7c6d9f87dd6b1d13"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:ac40d76856e1b03f2b9a73d245a502d9e"><td class="memItemLeft" align="right" valign="top"><a id="ac40d76856e1b03f2b9a73d245a502d9e"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac40d76856e1b03f2b9a73d245a502d9e">PIN_PB09E_TC4_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(41)</td></tr>
|
||
|
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<tr class="memdesc:ac40d76856e1b03f2b9a73d245a502d9e"><td class="mdescLeft"> </td><td class="mdescRight">TC4 signal: WO1 on PB09 mux E. <br /></td></tr>
|
||
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<tr class="separator:ac40d76856e1b03f2b9a73d245a502d9e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afb3920df8b62154d2e8cddd7011952ab"><td class="memItemLeft" align="right" valign="top"><a id="afb3920df8b62154d2e8cddd7011952ab"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB09E_TC4_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
|
||
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<tr class="separator:afb3920df8b62154d2e8cddd7011952ab"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a2c1af7c803f571c9583d815337d21231"><td class="memItemLeft" align="right" valign="top"><a id="a2c1af7c803f571c9583d815337d21231"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB09E_TC4_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ac40d76856e1b03f2b9a73d245a502d9e">PIN_PB09E_TC4_WO1</a> << 16) | MUX_PB09E_TC4_WO1)</td></tr>
|
||
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<tr class="separator:a2c1af7c803f571c9583d815337d21231"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a26261ec39058fc7c57e702f7048d4d79"><td class="memItemLeft" align="right" valign="top"><a id="a26261ec39058fc7c57e702f7048d4d79"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB09E_TC4_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 9)</td></tr>
|
||
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<tr class="separator:a26261ec39058fc7c57e702f7048d4d79"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:ab17c34e5d668dc3db35fdfe4ec67c91d"><td class="memItemLeft" align="right" valign="top"><a id="ab17c34e5d668dc3db35fdfe4ec67c91d"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab17c34e5d668dc3db35fdfe4ec67c91d">PIN_PB13E_TC4_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(45)</td></tr>
|
||
|
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<tr class="memdesc:ab17c34e5d668dc3db35fdfe4ec67c91d"><td class="mdescLeft"> </td><td class="mdescRight">TC4 signal: WO1 on PB13 mux E. <br /></td></tr>
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||
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<tr class="separator:ab17c34e5d668dc3db35fdfe4ec67c91d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1596bf26e7e5238979faa58bb9901666"><td class="memItemLeft" align="right" valign="top"><a id="a1596bf26e7e5238979faa58bb9901666"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB13E_TC4_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
|
||
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<tr class="separator:a1596bf26e7e5238979faa58bb9901666"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a33418c45a490b4dcbd62ed165c4e96ff"><td class="memItemLeft" align="right" valign="top"><a id="a33418c45a490b4dcbd62ed165c4e96ff"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB13E_TC4_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ab17c34e5d668dc3db35fdfe4ec67c91d">PIN_PB13E_TC4_WO1</a> << 16) | MUX_PB13E_TC4_WO1)</td></tr>
|
||
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<tr class="separator:a33418c45a490b4dcbd62ed165c4e96ff"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a702edfb4aea03b171c9b3a8290cd3bbd"><td class="memItemLeft" align="right" valign="top"><a id="a702edfb4aea03b171c9b3a8290cd3bbd"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB13E_TC4_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 13)</td></tr>
|
||
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<tr class="separator:a702edfb4aea03b171c9b3a8290cd3bbd"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a7fd3dfb1f952256b6f8b84dd50170639"><td class="memItemLeft" align="right" valign="top"><a id="a7fd3dfb1f952256b6f8b84dd50170639"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7fd3dfb1f952256b6f8b84dd50170639">PIN_PA24E_TC5_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(24)</td></tr>
|
||
|
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<tr class="memdesc:a7fd3dfb1f952256b6f8b84dd50170639"><td class="mdescLeft"> </td><td class="mdescRight">TC5 signal: WO0 on PA24 mux E. <br /></td></tr>
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||
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<tr class="separator:a7fd3dfb1f952256b6f8b84dd50170639"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:ab72a7fd7979169adeb45332101dad91c"><td class="memItemLeft" align="right" valign="top"><a id="ab72a7fd7979169adeb45332101dad91c"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA24E_TC5_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
|
||
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<tr class="separator:ab72a7fd7979169adeb45332101dad91c"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a62f8dc4e0570b300403dfe90324671f7"><td class="memItemLeft" align="right" valign="top"><a id="a62f8dc4e0570b300403dfe90324671f7"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA24E_TC5_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a7fd3dfb1f952256b6f8b84dd50170639">PIN_PA24E_TC5_WO0</a> << 16) | MUX_PA24E_TC5_WO0)</td></tr>
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||
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<tr class="separator:a62f8dc4e0570b300403dfe90324671f7"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:abda5f2cba963a71f865aa9c1aeb62eff"><td class="memItemLeft" align="right" valign="top"><a id="abda5f2cba963a71f865aa9c1aeb62eff"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA24E_TC5_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 24)</td></tr>
|
||
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<tr class="separator:abda5f2cba963a71f865aa9c1aeb62eff"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a507c6e9336a7c1ce63a4fa939dbd6bb4"><td class="memItemLeft" align="right" valign="top"><a id="a507c6e9336a7c1ce63a4fa939dbd6bb4"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a507c6e9336a7c1ce63a4fa939dbd6bb4">PIN_PB10E_TC5_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(42)</td></tr>
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<tr class="memdesc:a507c6e9336a7c1ce63a4fa939dbd6bb4"><td class="mdescLeft"> </td><td class="mdescRight">TC5 signal: WO0 on PB10 mux E. <br /></td></tr>
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<tr class="separator:a507c6e9336a7c1ce63a4fa939dbd6bb4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab1f760bcc8be12e1a5611f0a2b996d0e"><td class="memItemLeft" align="right" valign="top"><a id="ab1f760bcc8be12e1a5611f0a2b996d0e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB10E_TC5_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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<tr class="separator:ab1f760bcc8be12e1a5611f0a2b996d0e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa1403cc3866036d7735a27cf496b6f65"><td class="memItemLeft" align="right" valign="top"><a id="aa1403cc3866036d7735a27cf496b6f65"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB10E_TC5_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a507c6e9336a7c1ce63a4fa939dbd6bb4">PIN_PB10E_TC5_WO0</a> << 16) | MUX_PB10E_TC5_WO0)</td></tr>
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<tr class="memitem:a23507831bd49e5b4bbe423f96f91aa27"><td class="memItemLeft" align="right" valign="top"><a id="a23507831bd49e5b4bbe423f96f91aa27"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB10E_TC5_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 10)</td></tr>
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<tr class="separator:a23507831bd49e5b4bbe423f96f91aa27"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a24eb8bf26a40daa34a83d0f7e413ab99"><td class="memItemLeft" align="right" valign="top"><a id="a24eb8bf26a40daa34a83d0f7e413ab99"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a24eb8bf26a40daa34a83d0f7e413ab99">PIN_PB14E_TC5_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(46)</td></tr>
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<tr class="memdesc:a24eb8bf26a40daa34a83d0f7e413ab99"><td class="mdescLeft"> </td><td class="mdescRight">TC5 signal: WO0 on PB14 mux E. <br /></td></tr>
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<tr class="separator:a24eb8bf26a40daa34a83d0f7e413ab99"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab0933045e48b11522ee9ce2deeb9aa51"><td class="memItemLeft" align="right" valign="top"><a id="ab0933045e48b11522ee9ce2deeb9aa51"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB14E_TC5_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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<tr class="separator:ab0933045e48b11522ee9ce2deeb9aa51"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aec48fb721341c0440c3b0b9bec2f898c"><td class="memItemLeft" align="right" valign="top"><a id="aec48fb721341c0440c3b0b9bec2f898c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB14E_TC5_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a24eb8bf26a40daa34a83d0f7e413ab99">PIN_PB14E_TC5_WO0</a> << 16) | MUX_PB14E_TC5_WO0)</td></tr>
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<tr class="separator:aec48fb721341c0440c3b0b9bec2f898c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a51cad283d7c3ca9774ef680c06302145"><td class="memItemLeft" align="right" valign="top"><a id="a51cad283d7c3ca9774ef680c06302145"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB14E_TC5_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 14)</td></tr>
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<tr class="separator:a51cad283d7c3ca9774ef680c06302145"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab22c202ad376d93dd79a9913ee9fcf90"><td class="memItemLeft" align="right" valign="top"><a id="ab22c202ad376d93dd79a9913ee9fcf90"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab22c202ad376d93dd79a9913ee9fcf90">PIN_PA25E_TC5_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(25)</td></tr>
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<tr class="memdesc:ab22c202ad376d93dd79a9913ee9fcf90"><td class="mdescLeft"> </td><td class="mdescRight">TC5 signal: WO1 on PA25 mux E. <br /></td></tr>
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<tr class="separator:ab22c202ad376d93dd79a9913ee9fcf90"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa9cc1e2779529985414fa1377dec755d"><td class="memItemLeft" align="right" valign="top"><a id="aa9cc1e2779529985414fa1377dec755d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA25E_TC5_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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<tr class="separator:aa9cc1e2779529985414fa1377dec755d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a575c2e9a905d96173cae3e2cfe2746ba"><td class="memItemLeft" align="right" valign="top"><a id="a575c2e9a905d96173cae3e2cfe2746ba"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA25E_TC5_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ab22c202ad376d93dd79a9913ee9fcf90">PIN_PA25E_TC5_WO1</a> << 16) | MUX_PA25E_TC5_WO1)</td></tr>
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<tr class="separator:a575c2e9a905d96173cae3e2cfe2746ba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a641f318951bb16d151b401ad273a5b93"><td class="memItemLeft" align="right" valign="top"><a id="a641f318951bb16d151b401ad273a5b93"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA25E_TC5_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 25)</td></tr>
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<tr class="separator:a641f318951bb16d151b401ad273a5b93"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a72371b5ea4bd771cb2b96e82f412e65d"><td class="memItemLeft" align="right" valign="top"><a id="a72371b5ea4bd771cb2b96e82f412e65d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a72371b5ea4bd771cb2b96e82f412e65d">PIN_PB11E_TC5_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(43)</td></tr>
|
||
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<tr class="memdesc:a72371b5ea4bd771cb2b96e82f412e65d"><td class="mdescLeft"> </td><td class="mdescRight">TC5 signal: WO1 on PB11 mux E. <br /></td></tr>
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<tr class="separator:a72371b5ea4bd771cb2b96e82f412e65d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af5ce4c9437bdf2534862b68506bb1d59"><td class="memItemLeft" align="right" valign="top"><a id="af5ce4c9437bdf2534862b68506bb1d59"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB11E_TC5_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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<tr class="separator:af5ce4c9437bdf2534862b68506bb1d59"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afdddef96162dbebfd633cedb89770ac7"><td class="memItemLeft" align="right" valign="top"><a id="afdddef96162dbebfd633cedb89770ac7"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB11E_TC5_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a72371b5ea4bd771cb2b96e82f412e65d">PIN_PB11E_TC5_WO1</a> << 16) | MUX_PB11E_TC5_WO1)</td></tr>
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<tr class="separator:afdddef96162dbebfd633cedb89770ac7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae116d9762be96e55a2974b4f73969c7d"><td class="memItemLeft" align="right" valign="top"><a id="ae116d9762be96e55a2974b4f73969c7d"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB11E_TC5_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 11)</td></tr>
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||
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<tr class="separator:ae116d9762be96e55a2974b4f73969c7d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad46dc3d5731ff0d9169795cf7e83b68a"><td class="memItemLeft" align="right" valign="top"><a id="ad46dc3d5731ff0d9169795cf7e83b68a"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad46dc3d5731ff0d9169795cf7e83b68a">PIN_PB15E_TC5_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(47)</td></tr>
|
||
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<tr class="memdesc:ad46dc3d5731ff0d9169795cf7e83b68a"><td class="mdescLeft"> </td><td class="mdescRight">TC5 signal: WO1 on PB15 mux E. <br /></td></tr>
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<tr class="separator:ad46dc3d5731ff0d9169795cf7e83b68a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6f663d9648972be9b2ead17abc7559b9"><td class="memItemLeft" align="right" valign="top"><a id="a6f663d9648972be9b2ead17abc7559b9"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB15E_TC5_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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<tr class="separator:a6f663d9648972be9b2ead17abc7559b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0c33b4f66ffa28f9658eb2608084d3d2"><td class="memItemLeft" align="right" valign="top"><a id="a0c33b4f66ffa28f9658eb2608084d3d2"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB15E_TC5_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ad46dc3d5731ff0d9169795cf7e83b68a">PIN_PB15E_TC5_WO1</a> << 16) | MUX_PB15E_TC5_WO1)</td></tr>
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<tr class="separator:a0c33b4f66ffa28f9658eb2608084d3d2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adb970eafd87d0f0921e0e2739e6a0d01"><td class="memItemLeft" align="right" valign="top"><a id="adb970eafd87d0f0921e0e2739e6a0d01"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB15E_TC5_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 15)</td></tr>
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<tr class="separator:adb970eafd87d0f0921e0e2739e6a0d01"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac7fb39e38573e6a4b0ebeba213408fa7"><td class="memItemLeft" align="right" valign="top"><a id="ac7fb39e38573e6a4b0ebeba213408fa7"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac7fb39e38573e6a4b0ebeba213408fa7">PIN_PB18G_PDEC_QDI0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(50)</td></tr>
|
||
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<tr class="memdesc:ac7fb39e38573e6a4b0ebeba213408fa7"><td class="mdescLeft"> </td><td class="mdescRight">PDEC signal: QDI0 on PB18 mux G. <br /></td></tr>
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<tr class="separator:ac7fb39e38573e6a4b0ebeba213408fa7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad475f5e40c0bc8a6d737568074aff7bb"><td class="memItemLeft" align="right" valign="top"><a id="ad475f5e40c0bc8a6d737568074aff7bb"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB18G_PDEC_QDI0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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<tr class="separator:ad475f5e40c0bc8a6d737568074aff7bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8d076ae95d2316b20d47fab5f00fe4d9"><td class="memItemLeft" align="right" valign="top"><a id="a8d076ae95d2316b20d47fab5f00fe4d9"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB18G_PDEC_QDI0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ac7fb39e38573e6a4b0ebeba213408fa7">PIN_PB18G_PDEC_QDI0</a> << 16) | MUX_PB18G_PDEC_QDI0)</td></tr>
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<tr class="separator:a8d076ae95d2316b20d47fab5f00fe4d9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a750f96c47b74f1a4c0adef2fa0501a50"><td class="memItemLeft" align="right" valign="top"><a id="a750f96c47b74f1a4c0adef2fa0501a50"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB18G_PDEC_QDI0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 18)</td></tr>
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||
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<tr class="separator:a750f96c47b74f1a4c0adef2fa0501a50"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9e5853b7e4c261377514699da2408225"><td class="memItemLeft" align="right" valign="top"><a id="a9e5853b7e4c261377514699da2408225"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a9e5853b7e4c261377514699da2408225">PIN_PB23G_PDEC_QDI0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(55)</td></tr>
|
||
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<tr class="memdesc:a9e5853b7e4c261377514699da2408225"><td class="mdescLeft"> </td><td class="mdescRight">PDEC signal: QDI0 on PB23 mux G. <br /></td></tr>
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<tr class="separator:a9e5853b7e4c261377514699da2408225"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a34d3cc5034f685e337ee20bb3f15bd3b"><td class="memItemLeft" align="right" valign="top"><a id="a34d3cc5034f685e337ee20bb3f15bd3b"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB23G_PDEC_QDI0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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||
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<tr class="separator:a34d3cc5034f685e337ee20bb3f15bd3b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6981daf55502677c610c0aca7526e814"><td class="memItemLeft" align="right" valign="top"><a id="a6981daf55502677c610c0aca7526e814"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB23G_PDEC_QDI0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a9e5853b7e4c261377514699da2408225">PIN_PB23G_PDEC_QDI0</a> << 16) | MUX_PB23G_PDEC_QDI0)</td></tr>
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<tr class="separator:a6981daf55502677c610c0aca7526e814"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1e2e84a9a2e97db00be6d08199047717"><td class="memItemLeft" align="right" valign="top"><a id="a1e2e84a9a2e97db00be6d08199047717"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB23G_PDEC_QDI0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 23)</td></tr>
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||
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<tr class="separator:a1e2e84a9a2e97db00be6d08199047717"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a529504f16c061580273255e241dec40f"><td class="memItemLeft" align="right" valign="top"><a id="a529504f16c061580273255e241dec40f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a529504f16c061580273255e241dec40f">PIN_PC16G_PDEC_QDI0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(80)</td></tr>
|
||
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<tr class="memdesc:a529504f16c061580273255e241dec40f"><td class="mdescLeft"> </td><td class="mdescRight">PDEC signal: QDI0 on PC16 mux G. <br /></td></tr>
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<tr class="separator:a529504f16c061580273255e241dec40f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a17754820b922d5f5b2b5be1b3f6e4722"><td class="memItemLeft" align="right" valign="top"><a id="a17754820b922d5f5b2b5be1b3f6e4722"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC16G_PDEC_QDI0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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<tr class="memitem:ac7ea6700e9496081a0003171d3c6d564"><td class="memItemLeft" align="right" valign="top"><a id="ac7ea6700e9496081a0003171d3c6d564"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC16G_PDEC_QDI0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a529504f16c061580273255e241dec40f">PIN_PC16G_PDEC_QDI0</a> << 16) | MUX_PC16G_PDEC_QDI0)</td></tr>
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<tr class="memitem:a3ba199126867207630f14c2f9728e52d"><td class="memItemLeft" align="right" valign="top"><a id="a3ba199126867207630f14c2f9728e52d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC16G_PDEC_QDI0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 16)</td></tr>
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<tr class="memitem:a4ab63287710ede1aa24534d7233705c8"><td class="memItemLeft" align="right" valign="top"><a id="a4ab63287710ede1aa24534d7233705c8"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4ab63287710ede1aa24534d7233705c8">PIN_PA24G_PDEC_QDI0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(24)</td></tr>
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<tr class="memdesc:a4ab63287710ede1aa24534d7233705c8"><td class="mdescLeft"> </td><td class="mdescRight">PDEC signal: QDI0 on PA24 mux G. <br /></td></tr>
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<tr class="memitem:a5838dbb9d47302f97bc4e50e1845f922"><td class="memItemLeft" align="right" valign="top"><a id="a5838dbb9d47302f97bc4e50e1845f922"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA24G_PDEC_QDI0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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<tr class="separator:a5838dbb9d47302f97bc4e50e1845f922"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad0294cbfe296d0cf59f97ee5852f9d3b"><td class="memItemLeft" align="right" valign="top"><a id="ad0294cbfe296d0cf59f97ee5852f9d3b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA24G_PDEC_QDI0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a4ab63287710ede1aa24534d7233705c8">PIN_PA24G_PDEC_QDI0</a> << 16) | MUX_PA24G_PDEC_QDI0)</td></tr>
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<tr class="memitem:a2d79cb9385aed298940bb4507b6e9c8f"><td class="memItemLeft" align="right" valign="top"><a id="a2d79cb9385aed298940bb4507b6e9c8f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA24G_PDEC_QDI0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 24)</td></tr>
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<tr class="separator:a2d79cb9385aed298940bb4507b6e9c8f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7d280f8e7d1efece39af6e3871e96fd5"><td class="memItemLeft" align="right" valign="top"><a id="a7d280f8e7d1efece39af6e3871e96fd5"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7d280f8e7d1efece39af6e3871e96fd5">PIN_PB19G_PDEC_QDI1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(51)</td></tr>
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<tr class="memdesc:a7d280f8e7d1efece39af6e3871e96fd5"><td class="mdescLeft"> </td><td class="mdescRight">PDEC signal: QDI1 on PB19 mux G. <br /></td></tr>
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<tr class="separator:a7d280f8e7d1efece39af6e3871e96fd5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a62e27a9408c3055a2569e21aa1cfac31"><td class="memItemLeft" align="right" valign="top"><a id="a62e27a9408c3055a2569e21aa1cfac31"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB19G_PDEC_QDI1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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<tr class="separator:a62e27a9408c3055a2569e21aa1cfac31"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a47dd35e4589a8d0c1dad83120b2341f2"><td class="memItemLeft" align="right" valign="top"><a id="a47dd35e4589a8d0c1dad83120b2341f2"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB19G_PDEC_QDI1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a7d280f8e7d1efece39af6e3871e96fd5">PIN_PB19G_PDEC_QDI1</a> << 16) | MUX_PB19G_PDEC_QDI1)</td></tr>
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<tr class="separator:a47dd35e4589a8d0c1dad83120b2341f2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2509cab9e871f63dc798db1c36a177d2"><td class="memItemLeft" align="right" valign="top"><a id="a2509cab9e871f63dc798db1c36a177d2"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB19G_PDEC_QDI1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 19)</td></tr>
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<tr class="separator:a2509cab9e871f63dc798db1c36a177d2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a492a10d4f50b4521d2bb265177b44576"><td class="memItemLeft" align="right" valign="top"><a id="a492a10d4f50b4521d2bb265177b44576"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a492a10d4f50b4521d2bb265177b44576">PIN_PB24G_PDEC_QDI1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(56)</td></tr>
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<tr class="memdesc:a492a10d4f50b4521d2bb265177b44576"><td class="mdescLeft"> </td><td class="mdescRight">PDEC signal: QDI1 on PB24 mux G. <br /></td></tr>
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<tr class="separator:a492a10d4f50b4521d2bb265177b44576"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad1adea28395fb34b08d5cd0ea40ac897"><td class="memItemLeft" align="right" valign="top"><a id="ad1adea28395fb34b08d5cd0ea40ac897"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB24G_PDEC_QDI1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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<tr class="separator:ad1adea28395fb34b08d5cd0ea40ac897"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a175b1d935498ec1b39135f6a434ee837"><td class="memItemLeft" align="right" valign="top"><a id="a175b1d935498ec1b39135f6a434ee837"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB24G_PDEC_QDI1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a492a10d4f50b4521d2bb265177b44576">PIN_PB24G_PDEC_QDI1</a> << 16) | MUX_PB24G_PDEC_QDI1)</td></tr>
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<tr class="separator:a175b1d935498ec1b39135f6a434ee837"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1093628e77aa723eea1caf283a2b738f"><td class="memItemLeft" align="right" valign="top"><a id="a1093628e77aa723eea1caf283a2b738f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB24G_PDEC_QDI1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 24)</td></tr>
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<tr class="separator:a1093628e77aa723eea1caf283a2b738f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa139d121508ad7acd366f4bd04da16c8"><td class="memItemLeft" align="right" valign="top"><a id="aa139d121508ad7acd366f4bd04da16c8"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa139d121508ad7acd366f4bd04da16c8">PIN_PC17G_PDEC_QDI1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(81)</td></tr>
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<tr class="memdesc:aa139d121508ad7acd366f4bd04da16c8"><td class="mdescLeft"> </td><td class="mdescRight">PDEC signal: QDI1 on PC17 mux G. <br /></td></tr>
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<tr class="separator:aa139d121508ad7acd366f4bd04da16c8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af8acce787799d9a3ff00e06588f8263a"><td class="memItemLeft" align="right" valign="top"><a id="af8acce787799d9a3ff00e06588f8263a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC17G_PDEC_QDI1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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<tr class="separator:af8acce787799d9a3ff00e06588f8263a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aafbfa1117a1803df6f20fb4536f667c5"><td class="memItemLeft" align="right" valign="top"><a id="aafbfa1117a1803df6f20fb4536f667c5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC17G_PDEC_QDI1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aa139d121508ad7acd366f4bd04da16c8">PIN_PC17G_PDEC_QDI1</a> << 16) | MUX_PC17G_PDEC_QDI1)</td></tr>
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<tr class="separator:aafbfa1117a1803df6f20fb4536f667c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa25c527de12f4be8e0a728ed933ea537"><td class="memItemLeft" align="right" valign="top"><a id="aa25c527de12f4be8e0a728ed933ea537"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC17G_PDEC_QDI1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 17)</td></tr>
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<tr class="separator:aa25c527de12f4be8e0a728ed933ea537"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af9c611769bfd63f638c8471a6f3a66d8"><td class="memItemLeft" align="right" valign="top"><a id="af9c611769bfd63f638c8471a6f3a66d8"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af9c611769bfd63f638c8471a6f3a66d8">PIN_PA25G_PDEC_QDI1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(25)</td></tr>
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<tr class="memdesc:af9c611769bfd63f638c8471a6f3a66d8"><td class="mdescLeft"> </td><td class="mdescRight">PDEC signal: QDI1 on PA25 mux G. <br /></td></tr>
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<tr class="separator:af9c611769bfd63f638c8471a6f3a66d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae71f635caf016601fb6e839b59d3aa34"><td class="memItemLeft" align="right" valign="top"><a id="ae71f635caf016601fb6e839b59d3aa34"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA25G_PDEC_QDI1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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<tr class="separator:ae71f635caf016601fb6e839b59d3aa34"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad76cc11a57d9754ea02689bdf72ef45f"><td class="memItemLeft" align="right" valign="top"><a id="ad76cc11a57d9754ea02689bdf72ef45f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA25G_PDEC_QDI1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#af9c611769bfd63f638c8471a6f3a66d8">PIN_PA25G_PDEC_QDI1</a> << 16) | MUX_PA25G_PDEC_QDI1)</td></tr>
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<tr class="separator:ad76cc11a57d9754ea02689bdf72ef45f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ade6fc786dfb3ade09325f959ce55e65c"><td class="memItemLeft" align="right" valign="top"><a id="ade6fc786dfb3ade09325f959ce55e65c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA25G_PDEC_QDI1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 25)</td></tr>
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<tr class="separator:ade6fc786dfb3ade09325f959ce55e65c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a858c1f15237c51c39dc8abcefef51f69"><td class="memItemLeft" align="right" valign="top"><a id="a858c1f15237c51c39dc8abcefef51f69"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a858c1f15237c51c39dc8abcefef51f69">PIN_PB20G_PDEC_QDI2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(52)</td></tr>
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<tr class="memdesc:a858c1f15237c51c39dc8abcefef51f69"><td class="mdescLeft"> </td><td class="mdescRight">PDEC signal: QDI2 on PB20 mux G. <br /></td></tr>
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<tr class="separator:a858c1f15237c51c39dc8abcefef51f69"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a02dd5735cb62b36a9584c36471077294"><td class="memItemLeft" align="right" valign="top"><a id="a02dd5735cb62b36a9584c36471077294"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB20G_PDEC_QDI2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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<tr class="separator:a02dd5735cb62b36a9584c36471077294"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab7f96ca388e0426e1ecc925cd1507ee4"><td class="memItemLeft" align="right" valign="top"><a id="ab7f96ca388e0426e1ecc925cd1507ee4"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB20G_PDEC_QDI2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a858c1f15237c51c39dc8abcefef51f69">PIN_PB20G_PDEC_QDI2</a> << 16) | MUX_PB20G_PDEC_QDI2)</td></tr>
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<tr class="separator:ab7f96ca388e0426e1ecc925cd1507ee4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af6a36d62c099b42fa387980b3c32aae0"><td class="memItemLeft" align="right" valign="top"><a id="af6a36d62c099b42fa387980b3c32aae0"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB20G_PDEC_QDI2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 20)</td></tr>
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<tr class="separator:af6a36d62c099b42fa387980b3c32aae0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5689f57f16a33f29e98f56ec349b63fb"><td class="memItemLeft" align="right" valign="top"><a id="a5689f57f16a33f29e98f56ec349b63fb"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5689f57f16a33f29e98f56ec349b63fb">PIN_PB25G_PDEC_QDI2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(57)</td></tr>
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||
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<tr class="memdesc:a5689f57f16a33f29e98f56ec349b63fb"><td class="mdescLeft"> </td><td class="mdescRight">PDEC signal: QDI2 on PB25 mux G. <br /></td></tr>
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<tr class="separator:a5689f57f16a33f29e98f56ec349b63fb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afaaf65b8154469308398c03a919200b5"><td class="memItemLeft" align="right" valign="top"><a id="afaaf65b8154469308398c03a919200b5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB25G_PDEC_QDI2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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<tr class="separator:afaaf65b8154469308398c03a919200b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a47d880e44dc89c822ce8b54554500be6"><td class="memItemLeft" align="right" valign="top"><a id="a47d880e44dc89c822ce8b54554500be6"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB25G_PDEC_QDI2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a5689f57f16a33f29e98f56ec349b63fb">PIN_PB25G_PDEC_QDI2</a> << 16) | MUX_PB25G_PDEC_QDI2)</td></tr>
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<tr class="separator:a47d880e44dc89c822ce8b54554500be6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a266472ca7f230599edb20594728abc4d"><td class="memItemLeft" align="right" valign="top"><a id="a266472ca7f230599edb20594728abc4d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB25G_PDEC_QDI2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 25)</td></tr>
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<tr class="separator:a266472ca7f230599edb20594728abc4d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3c8d21b2d16e98d8be25c7386b3736a8"><td class="memItemLeft" align="right" valign="top"><a id="a3c8d21b2d16e98d8be25c7386b3736a8"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3c8d21b2d16e98d8be25c7386b3736a8">PIN_PC18G_PDEC_QDI2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(82)</td></tr>
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||
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<tr class="memdesc:a3c8d21b2d16e98d8be25c7386b3736a8"><td class="mdescLeft"> </td><td class="mdescRight">PDEC signal: QDI2 on PC18 mux G. <br /></td></tr>
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<tr class="separator:a3c8d21b2d16e98d8be25c7386b3736a8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aac0b72dd0a68def898caae13e891cca4"><td class="memItemLeft" align="right" valign="top"><a id="aac0b72dd0a68def898caae13e891cca4"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC18G_PDEC_QDI2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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<tr class="separator:aac0b72dd0a68def898caae13e891cca4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa886a42c0b9c7c357b940286e0816f41"><td class="memItemLeft" align="right" valign="top"><a id="aa886a42c0b9c7c357b940286e0816f41"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC18G_PDEC_QDI2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a3c8d21b2d16e98d8be25c7386b3736a8">PIN_PC18G_PDEC_QDI2</a> << 16) | MUX_PC18G_PDEC_QDI2)</td></tr>
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<tr class="separator:aa886a42c0b9c7c357b940286e0816f41"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae0cf5fccc28ed5e2f317ffab58e0ac30"><td class="memItemLeft" align="right" valign="top"><a id="ae0cf5fccc28ed5e2f317ffab58e0ac30"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC18G_PDEC_QDI2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 18)</td></tr>
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||
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<tr class="separator:ae0cf5fccc28ed5e2f317ffab58e0ac30"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7abeb51ca7fbfe8ec88df7a4f4d2933f"><td class="memItemLeft" align="right" valign="top"><a id="a7abeb51ca7fbfe8ec88df7a4f4d2933f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7abeb51ca7fbfe8ec88df7a4f4d2933f">PIN_PB22G_PDEC_QDI2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(54)</td></tr>
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||
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<tr class="memdesc:a7abeb51ca7fbfe8ec88df7a4f4d2933f"><td class="mdescLeft"> </td><td class="mdescRight">PDEC signal: QDI2 on PB22 mux G. <br /></td></tr>
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<tr class="separator:a7abeb51ca7fbfe8ec88df7a4f4d2933f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa858d3c2e3cd4aa357ed56852d7bb459"><td class="memItemLeft" align="right" valign="top"><a id="aa858d3c2e3cd4aa357ed56852d7bb459"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB22G_PDEC_QDI2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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<tr class="separator:aa858d3c2e3cd4aa357ed56852d7bb459"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a427797fb1eb0fccbe5788670dae2d3d7"><td class="memItemLeft" align="right" valign="top"><a id="a427797fb1eb0fccbe5788670dae2d3d7"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB22G_PDEC_QDI2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a7abeb51ca7fbfe8ec88df7a4f4d2933f">PIN_PB22G_PDEC_QDI2</a> << 16) | MUX_PB22G_PDEC_QDI2)</td></tr>
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<tr class="separator:a427797fb1eb0fccbe5788670dae2d3d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afad75be4d73971a5b97c1aa10d4507da"><td class="memItemLeft" align="right" valign="top"><a id="afad75be4d73971a5b97c1aa10d4507da"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB22G_PDEC_QDI2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 22)</td></tr>
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||
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<tr class="separator:afad75be4d73971a5b97c1aa10d4507da"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a181e0a4f47f8e8f3b1d79d02176dd26c"><td class="memItemLeft" align="right" valign="top"><a id="a181e0a4f47f8e8f3b1d79d02176dd26c"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a181e0a4f47f8e8f3b1d79d02176dd26c">PIN_PA04B_AC_AIN0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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||
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<tr class="memdesc:a181e0a4f47f8e8f3b1d79d02176dd26c"><td class="mdescLeft"> </td><td class="mdescRight">AC signal: AIN0 on PA04 mux B. <br /></td></tr>
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||
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<tr class="separator:a181e0a4f47f8e8f3b1d79d02176dd26c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aacb0de73f32b0931ecbddac9a5046fcb"><td class="memItemLeft" align="right" valign="top"><a id="aacb0de73f32b0931ecbddac9a5046fcb"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA04B_AC_AIN0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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||
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<tr class="separator:aacb0de73f32b0931ecbddac9a5046fcb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa725b7438deac9bac2c3565fca519c87"><td class="memItemLeft" align="right" valign="top"><a id="aa725b7438deac9bac2c3565fca519c87"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA04B_AC_AIN0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a181e0a4f47f8e8f3b1d79d02176dd26c">PIN_PA04B_AC_AIN0</a> << 16) | MUX_PA04B_AC_AIN0)</td></tr>
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<tr class="separator:aa725b7438deac9bac2c3565fca519c87"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a27fe78429e0d79e05166b5b7e71a635f"><td class="memItemLeft" align="right" valign="top"><a id="a27fe78429e0d79e05166b5b7e71a635f"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA04B_AC_AIN0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 4)</td></tr>
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||
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<tr class="separator:a27fe78429e0d79e05166b5b7e71a635f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a371630f713d57b3f41f708b1320358c9"><td class="memItemLeft" align="right" valign="top"><a id="a371630f713d57b3f41f708b1320358c9"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a371630f713d57b3f41f708b1320358c9">PIN_PA05B_AC_AIN1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
|
||
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<tr class="memdesc:a371630f713d57b3f41f708b1320358c9"><td class="mdescLeft"> </td><td class="mdescRight">AC signal: AIN1 on PA05 mux B. <br /></td></tr>
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||
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<tr class="separator:a371630f713d57b3f41f708b1320358c9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a038eae3b0a1c3d25bb124d453403efcc"><td class="memItemLeft" align="right" valign="top"><a id="a038eae3b0a1c3d25bb124d453403efcc"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA05B_AC_AIN1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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||
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<tr class="separator:a038eae3b0a1c3d25bb124d453403efcc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af24271aacbf73ea1e48b5b726848033a"><td class="memItemLeft" align="right" valign="top"><a id="af24271aacbf73ea1e48b5b726848033a"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA05B_AC_AIN1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a371630f713d57b3f41f708b1320358c9">PIN_PA05B_AC_AIN1</a> << 16) | MUX_PA05B_AC_AIN1)</td></tr>
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<tr class="separator:af24271aacbf73ea1e48b5b726848033a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7c134f0c41cadd4547c2990256db9fde"><td class="memItemLeft" align="right" valign="top"><a id="a7c134f0c41cadd4547c2990256db9fde"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA05B_AC_AIN1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 5)</td></tr>
|
||
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<tr class="separator:a7c134f0c41cadd4547c2990256db9fde"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a323ca7764bd09f550c2564a3913d50e0"><td class="memItemLeft" align="right" valign="top"><a id="a323ca7764bd09f550c2564a3913d50e0"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a323ca7764bd09f550c2564a3913d50e0">PIN_PA06B_AC_AIN2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
|
||
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<tr class="memdesc:a323ca7764bd09f550c2564a3913d50e0"><td class="mdescLeft"> </td><td class="mdescRight">AC signal: AIN2 on PA06 mux B. <br /></td></tr>
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<tr class="separator:a323ca7764bd09f550c2564a3913d50e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1cf568e41d6152bbf5019c8835cbf619"><td class="memItemLeft" align="right" valign="top"><a id="a1cf568e41d6152bbf5019c8835cbf619"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA06B_AC_AIN2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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||
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<tr class="separator:a1cf568e41d6152bbf5019c8835cbf619"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aff0b0e8aeb68be534152714bbdfab8a8"><td class="memItemLeft" align="right" valign="top"><a id="aff0b0e8aeb68be534152714bbdfab8a8"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA06B_AC_AIN2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a323ca7764bd09f550c2564a3913d50e0">PIN_PA06B_AC_AIN2</a> << 16) | MUX_PA06B_AC_AIN2)</td></tr>
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<tr class="separator:aff0b0e8aeb68be534152714bbdfab8a8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acbb4b99439ea4360165c9ab33227beef"><td class="memItemLeft" align="right" valign="top"><a id="acbb4b99439ea4360165c9ab33227beef"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA06B_AC_AIN2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 6)</td></tr>
|
||
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<tr class="separator:acbb4b99439ea4360165c9ab33227beef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aac4b0dec1c1c7442f3027aad45560115"><td class="memItemLeft" align="right" valign="top"><a id="aac4b0dec1c1c7442f3027aad45560115"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aac4b0dec1c1c7442f3027aad45560115">PIN_PA07B_AC_AIN3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
|
||
|
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<tr class="memdesc:aac4b0dec1c1c7442f3027aad45560115"><td class="mdescLeft"> </td><td class="mdescRight">AC signal: AIN3 on PA07 mux B. <br /></td></tr>
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||
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<tr class="separator:aac4b0dec1c1c7442f3027aad45560115"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8b866f26f4d2e1ecd59a5f22d3550432"><td class="memItemLeft" align="right" valign="top"><a id="a8b866f26f4d2e1ecd59a5f22d3550432"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA07B_AC_AIN3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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||
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<tr class="separator:a8b866f26f4d2e1ecd59a5f22d3550432"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac5328cf176b814be652c38c2e417d4aa"><td class="memItemLeft" align="right" valign="top"><a id="ac5328cf176b814be652c38c2e417d4aa"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA07B_AC_AIN3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aac4b0dec1c1c7442f3027aad45560115">PIN_PA07B_AC_AIN3</a> << 16) | MUX_PA07B_AC_AIN3)</td></tr>
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<tr class="separator:ac5328cf176b814be652c38c2e417d4aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac746f7cfbf05e02adf0ba384071b078d"><td class="memItemLeft" align="right" valign="top"><a id="ac746f7cfbf05e02adf0ba384071b078d"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA07B_AC_AIN3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 7)</td></tr>
|
||
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<tr class="separator:ac746f7cfbf05e02adf0ba384071b078d"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a14be1724e7f5ef5b9c94c94f3c8b4fd0"><td class="memItemLeft" align="right" valign="top"><a id="a14be1724e7f5ef5b9c94c94f3c8b4fd0"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a14be1724e7f5ef5b9c94c94f3c8b4fd0">PIN_PA12M_AC_CMP0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
|
||
|
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<tr class="memdesc:a14be1724e7f5ef5b9c94c94f3c8b4fd0"><td class="mdescLeft"> </td><td class="mdescRight">AC signal: CMP0 on PA12 mux M. <br /></td></tr>
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||
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<tr class="separator:a14be1724e7f5ef5b9c94c94f3c8b4fd0"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:acee7247ab010a5856e3cd8b1602ddeb7"><td class="memItemLeft" align="right" valign="top"><a id="acee7247ab010a5856e3cd8b1602ddeb7"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA12M_AC_CMP0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
|
||
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<tr class="separator:acee7247ab010a5856e3cd8b1602ddeb7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab9f930af0ce2fe9ee3ec7699f041229d"><td class="memItemLeft" align="right" valign="top"><a id="ab9f930af0ce2fe9ee3ec7699f041229d"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA12M_AC_CMP0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a14be1724e7f5ef5b9c94c94f3c8b4fd0">PIN_PA12M_AC_CMP0</a> << 16) | MUX_PA12M_AC_CMP0)</td></tr>
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<tr class="separator:ab9f930af0ce2fe9ee3ec7699f041229d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a81322af3155d4c0b81c08f9de4709e31"><td class="memItemLeft" align="right" valign="top"><a id="a81322af3155d4c0b81c08f9de4709e31"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA12M_AC_CMP0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 12)</td></tr>
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<tr class="memitem:a818e97d15fffe182de3dfea2734b2b0f"><td class="memItemLeft" align="right" valign="top"><a id="a818e97d15fffe182de3dfea2734b2b0f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a818e97d15fffe182de3dfea2734b2b0f">PIN_PA18M_AC_CMP0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(18)</td></tr>
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<tr class="memdesc:a818e97d15fffe182de3dfea2734b2b0f"><td class="mdescLeft"> </td><td class="mdescRight">AC signal: CMP0 on PA18 mux M. <br /></td></tr>
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<tr class="memitem:a86119d9c5aa593aeed40cf5741ae0b26"><td class="memItemLeft" align="right" valign="top"><a id="a86119d9c5aa593aeed40cf5741ae0b26"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA18M_AC_CMP0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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<tr class="separator:a86119d9c5aa593aeed40cf5741ae0b26"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a22e9dab18d78a691044d475144467ebc"><td class="memItemLeft" align="right" valign="top"><a id="a22e9dab18d78a691044d475144467ebc"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA18M_AC_CMP0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a818e97d15fffe182de3dfea2734b2b0f">PIN_PA18M_AC_CMP0</a> << 16) | MUX_PA18M_AC_CMP0)</td></tr>
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<tr class="memitem:afdb5934fe7603a937059d9217e856dec"><td class="memItemLeft" align="right" valign="top"><a id="afdb5934fe7603a937059d9217e856dec"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA18M_AC_CMP0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 18)</td></tr>
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<tr class="separator:afdb5934fe7603a937059d9217e856dec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac70e3e86e7648bfffd389730ef2d0245"><td class="memItemLeft" align="right" valign="top"><a id="ac70e3e86e7648bfffd389730ef2d0245"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac70e3e86e7648bfffd389730ef2d0245">PIN_PB24M_AC_CMP0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(56)</td></tr>
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<tr class="memdesc:ac70e3e86e7648bfffd389730ef2d0245"><td class="mdescLeft"> </td><td class="mdescRight">AC signal: CMP0 on PB24 mux M. <br /></td></tr>
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<tr class="separator:ac70e3e86e7648bfffd389730ef2d0245"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aab1f62904b93ce23bbfe7b083c0d835f"><td class="memItemLeft" align="right" valign="top"><a id="aab1f62904b93ce23bbfe7b083c0d835f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB24M_AC_CMP0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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<tr class="separator:aab1f62904b93ce23bbfe7b083c0d835f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4989feef205c5ebbc7258856dd7ba16d"><td class="memItemLeft" align="right" valign="top"><a id="a4989feef205c5ebbc7258856dd7ba16d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB24M_AC_CMP0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ac70e3e86e7648bfffd389730ef2d0245">PIN_PB24M_AC_CMP0</a> << 16) | MUX_PB24M_AC_CMP0)</td></tr>
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<tr class="memitem:a4c632a6714241ff13b972b9ee0417d90"><td class="memItemLeft" align="right" valign="top"><a id="a4c632a6714241ff13b972b9ee0417d90"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB24M_AC_CMP0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 24)</td></tr>
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<tr class="separator:a4c632a6714241ff13b972b9ee0417d90"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad505695604c6c01ae2a05a53226d943d"><td class="memItemLeft" align="right" valign="top"><a id="ad505695604c6c01ae2a05a53226d943d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad505695604c6c01ae2a05a53226d943d">PIN_PA13M_AC_CMP1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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<tr class="memdesc:ad505695604c6c01ae2a05a53226d943d"><td class="mdescLeft"> </td><td class="mdescRight">AC signal: CMP1 on PA13 mux M. <br /></td></tr>
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<tr class="separator:ad505695604c6c01ae2a05a53226d943d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6e28d99a49c1c658db9ca59b30d166d7"><td class="memItemLeft" align="right" valign="top"><a id="a6e28d99a49c1c658db9ca59b30d166d7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA13M_AC_CMP1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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<tr class="separator:a6e28d99a49c1c658db9ca59b30d166d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad3e99db872627938b530b197f1a53616"><td class="memItemLeft" align="right" valign="top"><a id="ad3e99db872627938b530b197f1a53616"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA13M_AC_CMP1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ad505695604c6c01ae2a05a53226d943d">PIN_PA13M_AC_CMP1</a> << 16) | MUX_PA13M_AC_CMP1)</td></tr>
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<tr class="separator:ad3e99db872627938b530b197f1a53616"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3d7a842447d2994b3f36ccdc6d753614"><td class="memItemLeft" align="right" valign="top"><a id="a3d7a842447d2994b3f36ccdc6d753614"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA13M_AC_CMP1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 13)</td></tr>
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<tr class="separator:a3d7a842447d2994b3f36ccdc6d753614"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab51a18fff0ed4e12fcc1d3e8c4480a72"><td class="memItemLeft" align="right" valign="top"><a id="ab51a18fff0ed4e12fcc1d3e8c4480a72"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab51a18fff0ed4e12fcc1d3e8c4480a72">PIN_PA19M_AC_CMP1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(19)</td></tr>
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<tr class="memdesc:ab51a18fff0ed4e12fcc1d3e8c4480a72"><td class="mdescLeft"> </td><td class="mdescRight">AC signal: CMP1 on PA19 mux M. <br /></td></tr>
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<tr class="separator:ab51a18fff0ed4e12fcc1d3e8c4480a72"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab0befb3668ac2377ddbc44d065b76c67"><td class="memItemLeft" align="right" valign="top"><a id="ab0befb3668ac2377ddbc44d065b76c67"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA19M_AC_CMP1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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<tr class="separator:ab0befb3668ac2377ddbc44d065b76c67"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8314854c9b518cf7f87a3005234306b9"><td class="memItemLeft" align="right" valign="top"><a id="a8314854c9b518cf7f87a3005234306b9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA19M_AC_CMP1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ab51a18fff0ed4e12fcc1d3e8c4480a72">PIN_PA19M_AC_CMP1</a> << 16) | MUX_PA19M_AC_CMP1)</td></tr>
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<tr class="separator:a8314854c9b518cf7f87a3005234306b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab769d8dfa2930d649c574d1accd4bf3e"><td class="memItemLeft" align="right" valign="top"><a id="ab769d8dfa2930d649c574d1accd4bf3e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA19M_AC_CMP1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 19)</td></tr>
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<tr class="separator:ab769d8dfa2930d649c574d1accd4bf3e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8a8370fd0a4d204daa83434d1fa58b4e"><td class="memItemLeft" align="right" valign="top"><a id="a8a8370fd0a4d204daa83434d1fa58b4e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8a8370fd0a4d204daa83434d1fa58b4e">PIN_PB25M_AC_CMP1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(57)</td></tr>
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<tr class="memdesc:a8a8370fd0a4d204daa83434d1fa58b4e"><td class="mdescLeft"> </td><td class="mdescRight">AC signal: CMP1 on PB25 mux M. <br /></td></tr>
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<tr class="separator:a8a8370fd0a4d204daa83434d1fa58b4e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa783a87509fc9fc1edd6a22ea0e3391e"><td class="memItemLeft" align="right" valign="top"><a id="aa783a87509fc9fc1edd6a22ea0e3391e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB25M_AC_CMP1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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<tr class="separator:aa783a87509fc9fc1edd6a22ea0e3391e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a917c6484f67704dd225eb9c4cb69bcb6"><td class="memItemLeft" align="right" valign="top"><a id="a917c6484f67704dd225eb9c4cb69bcb6"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB25M_AC_CMP1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a8a8370fd0a4d204daa83434d1fa58b4e">PIN_PB25M_AC_CMP1</a> << 16) | MUX_PB25M_AC_CMP1)</td></tr>
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<tr class="separator:a917c6484f67704dd225eb9c4cb69bcb6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af630d119cc3ab7b1cdcfa31c60f57772"><td class="memItemLeft" align="right" valign="top"><a id="af630d119cc3ab7b1cdcfa31c60f57772"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB25M_AC_CMP1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 25)</td></tr>
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<tr class="separator:af630d119cc3ab7b1cdcfa31c60f57772"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a31aec5c24c374327fac16080b33f8df8"><td class="memItemLeft" align="right" valign="top"><a id="a31aec5c24c374327fac16080b33f8df8"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a31aec5c24c374327fac16080b33f8df8">PIN_PB11H_QSPI_CS</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(43)</td></tr>
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<tr class="memdesc:a31aec5c24c374327fac16080b33f8df8"><td class="mdescLeft"> </td><td class="mdescRight">QSPI signal: CS on PB11 mux H. <br /></td></tr>
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<tr class="separator:a31aec5c24c374327fac16080b33f8df8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a998f0f3aad054758f0a9bdc8fea410d1"><td class="memItemLeft" align="right" valign="top"><a id="a998f0f3aad054758f0a9bdc8fea410d1"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB11H_QSPI_CS</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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<tr class="separator:a998f0f3aad054758f0a9bdc8fea410d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a402e57c10014bf5423b945d2afbf4bf9"><td class="memItemLeft" align="right" valign="top"><a id="a402e57c10014bf5423b945d2afbf4bf9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB11H_QSPI_CS</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a31aec5c24c374327fac16080b33f8df8">PIN_PB11H_QSPI_CS</a> << 16) | MUX_PB11H_QSPI_CS)</td></tr>
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<tr class="separator:a402e57c10014bf5423b945d2afbf4bf9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af7b1e888cd414229d0d31eb385d8dfcc"><td class="memItemLeft" align="right" valign="top"><a id="af7b1e888cd414229d0d31eb385d8dfcc"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB11H_QSPI_CS</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 11)</td></tr>
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<tr class="separator:af7b1e888cd414229d0d31eb385d8dfcc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1f56c929190a5353af478c2809e83a34"><td class="memItemLeft" align="right" valign="top"><a id="a1f56c929190a5353af478c2809e83a34"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1f56c929190a5353af478c2809e83a34">PIN_PA08H_QSPI_DATA0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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<tr class="memdesc:a1f56c929190a5353af478c2809e83a34"><td class="mdescLeft"> </td><td class="mdescRight">QSPI signal: DATA0 on PA08 mux H. <br /></td></tr>
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<tr class="separator:a1f56c929190a5353af478c2809e83a34"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a472ce46f7889eb6f54ad46b7f956050f"><td class="memItemLeft" align="right" valign="top"><a id="a472ce46f7889eb6f54ad46b7f956050f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA08H_QSPI_DATA0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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<tr class="separator:a472ce46f7889eb6f54ad46b7f956050f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af8b1e105de46ba8f4dac97da662c9499"><td class="memItemLeft" align="right" valign="top"><a id="af8b1e105de46ba8f4dac97da662c9499"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA08H_QSPI_DATA0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a1f56c929190a5353af478c2809e83a34">PIN_PA08H_QSPI_DATA0</a> << 16) | MUX_PA08H_QSPI_DATA0)</td></tr>
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<tr class="separator:af8b1e105de46ba8f4dac97da662c9499"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abb02cca2b5a272ff5ec50f2b24169aa4"><td class="memItemLeft" align="right" valign="top"><a id="abb02cca2b5a272ff5ec50f2b24169aa4"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA08H_QSPI_DATA0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 8)</td></tr>
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<tr class="separator:abb02cca2b5a272ff5ec50f2b24169aa4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3e393e86e8f99532da9af298966efb53"><td class="memItemLeft" align="right" valign="top"><a id="a3e393e86e8f99532da9af298966efb53"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3e393e86e8f99532da9af298966efb53">PIN_PA09H_QSPI_DATA1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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<tr class="memdesc:a3e393e86e8f99532da9af298966efb53"><td class="mdescLeft"> </td><td class="mdescRight">QSPI signal: DATA1 on PA09 mux H. <br /></td></tr>
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<tr class="memitem:a93adf2ed9383185c9e9d7d420483e12f"><td class="memItemLeft" align="right" valign="top"><a id="a93adf2ed9383185c9e9d7d420483e12f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA09H_QSPI_DATA1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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<tr class="memitem:aabbbba3f761bdbc91f5284c91f10394b"><td class="memItemLeft" align="right" valign="top"><a id="aabbbba3f761bdbc91f5284c91f10394b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA09H_QSPI_DATA1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a3e393e86e8f99532da9af298966efb53">PIN_PA09H_QSPI_DATA1</a> << 16) | MUX_PA09H_QSPI_DATA1)</td></tr>
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<tr class="memitem:a2f5b83f0fd029f5bf2e3f38a670ce38d"><td class="memItemLeft" align="right" valign="top"><a id="a2f5b83f0fd029f5bf2e3f38a670ce38d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA09H_QSPI_DATA1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 9)</td></tr>
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<tr class="separator:a2f5b83f0fd029f5bf2e3f38a670ce38d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:add1fac6b593768731ee682263f4eeb03"><td class="memItemLeft" align="right" valign="top"><a id="add1fac6b593768731ee682263f4eeb03"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#add1fac6b593768731ee682263f4eeb03">PIN_PA10H_QSPI_DATA2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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<tr class="memdesc:add1fac6b593768731ee682263f4eeb03"><td class="mdescLeft"> </td><td class="mdescRight">QSPI signal: DATA2 on PA10 mux H. <br /></td></tr>
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<tr class="memitem:ab94bf63043f6176ff58a6fa3afed20d0"><td class="memItemLeft" align="right" valign="top"><a id="ab94bf63043f6176ff58a6fa3afed20d0"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA10H_QSPI_DATA2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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<tr class="separator:ab94bf63043f6176ff58a6fa3afed20d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1ace7de2bf631d8ba31ecea3d64401ff"><td class="memItemLeft" align="right" valign="top"><a id="a1ace7de2bf631d8ba31ecea3d64401ff"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA10H_QSPI_DATA2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#add1fac6b593768731ee682263f4eeb03">PIN_PA10H_QSPI_DATA2</a> << 16) | MUX_PA10H_QSPI_DATA2)</td></tr>
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<tr class="memitem:a4ca13365897c93640e171b2d7d15a3c7"><td class="memItemLeft" align="right" valign="top"><a id="a4ca13365897c93640e171b2d7d15a3c7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA10H_QSPI_DATA2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 10)</td></tr>
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<tr class="separator:a4ca13365897c93640e171b2d7d15a3c7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa3da6ee8cf028b61b4987e27609f971c"><td class="memItemLeft" align="right" valign="top"><a id="aa3da6ee8cf028b61b4987e27609f971c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa3da6ee8cf028b61b4987e27609f971c">PIN_PA11H_QSPI_DATA3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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<tr class="memdesc:aa3da6ee8cf028b61b4987e27609f971c"><td class="mdescLeft"> </td><td class="mdescRight">QSPI signal: DATA3 on PA11 mux H. <br /></td></tr>
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<tr class="separator:aa3da6ee8cf028b61b4987e27609f971c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a153432555410351e12b7d64652cd2af6"><td class="memItemLeft" align="right" valign="top"><a id="a153432555410351e12b7d64652cd2af6"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA11H_QSPI_DATA3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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<tr class="separator:a153432555410351e12b7d64652cd2af6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a04e205f6f0189c2aec0d02b32355e8e4"><td class="memItemLeft" align="right" valign="top"><a id="a04e205f6f0189c2aec0d02b32355e8e4"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA11H_QSPI_DATA3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aa3da6ee8cf028b61b4987e27609f971c">PIN_PA11H_QSPI_DATA3</a> << 16) | MUX_PA11H_QSPI_DATA3)</td></tr>
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<tr class="separator:a04e205f6f0189c2aec0d02b32355e8e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a63c96dc3957e7dbcd33fb916e78b25b0"><td class="memItemLeft" align="right" valign="top"><a id="a63c96dc3957e7dbcd33fb916e78b25b0"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA11H_QSPI_DATA3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 11)</td></tr>
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<tr class="separator:a63c96dc3957e7dbcd33fb916e78b25b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aede71f5b54f159a1effe424366833e17"><td class="memItemLeft" align="right" valign="top"><a id="aede71f5b54f159a1effe424366833e17"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aede71f5b54f159a1effe424366833e17">PIN_PB10H_QSPI_SCK</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(42)</td></tr>
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<tr class="memdesc:aede71f5b54f159a1effe424366833e17"><td class="mdescLeft"> </td><td class="mdescRight">QSPI signal: SCK on PB10 mux H. <br /></td></tr>
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<tr class="separator:aede71f5b54f159a1effe424366833e17"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a398f8c0315873e9470b9b854be58d6fa"><td class="memItemLeft" align="right" valign="top"><a id="a398f8c0315873e9470b9b854be58d6fa"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB10H_QSPI_SCK</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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<tr class="separator:a398f8c0315873e9470b9b854be58d6fa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ace19267517445e126f92fcc8adfe0019"><td class="memItemLeft" align="right" valign="top"><a id="ace19267517445e126f92fcc8adfe0019"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB10H_QSPI_SCK</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aede71f5b54f159a1effe424366833e17">PIN_PB10H_QSPI_SCK</a> << 16) | MUX_PB10H_QSPI_SCK)</td></tr>
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<tr class="separator:ace19267517445e126f92fcc8adfe0019"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6d5114710d2abd5e0efec43335a6dc42"><td class="memItemLeft" align="right" valign="top"><a id="a6d5114710d2abd5e0efec43335a6dc42"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB10H_QSPI_SCK</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 10)</td></tr>
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<tr class="separator:a6d5114710d2abd5e0efec43335a6dc42"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a42187440e16ef275ae5cd6c2357ad694"><td class="memItemLeft" align="right" valign="top"><a id="a42187440e16ef275ae5cd6c2357ad694"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a42187440e16ef275ae5cd6c2357ad694">PIN_PA04N_CCL_IN0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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<tr class="memdesc:a42187440e16ef275ae5cd6c2357ad694"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: IN0 on PA04 mux N. <br /></td></tr>
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<tr class="separator:a42187440e16ef275ae5cd6c2357ad694"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a95f08580628a7544560f946c21ae73c4"><td class="memItemLeft" align="right" valign="top"><a id="a95f08580628a7544560f946c21ae73c4"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA04N_CCL_IN0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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<tr class="separator:a95f08580628a7544560f946c21ae73c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac2893fa167e23ec806691b7416b32d27"><td class="memItemLeft" align="right" valign="top"><a id="ac2893fa167e23ec806691b7416b32d27"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA04N_CCL_IN0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a42187440e16ef275ae5cd6c2357ad694">PIN_PA04N_CCL_IN0</a> << 16) | MUX_PA04N_CCL_IN0)</td></tr>
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<tr class="separator:ac2893fa167e23ec806691b7416b32d27"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab648d93cce0f748f5baf4dab0e2efcbb"><td class="memItemLeft" align="right" valign="top"><a id="ab648d93cce0f748f5baf4dab0e2efcbb"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA04N_CCL_IN0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 4)</td></tr>
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<tr class="separator:ab648d93cce0f748f5baf4dab0e2efcbb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad912a8ab729ff9e3592013be39a5a8d4"><td class="memItemLeft" align="right" valign="top"><a id="ad912a8ab729ff9e3592013be39a5a8d4"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad912a8ab729ff9e3592013be39a5a8d4">PIN_PA16N_CCL_IN0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(16)</td></tr>
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<tr class="memdesc:ad912a8ab729ff9e3592013be39a5a8d4"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: IN0 on PA16 mux N. <br /></td></tr>
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<tr class="separator:ad912a8ab729ff9e3592013be39a5a8d4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a959ff0cf7e060192dbd3cf558317e533"><td class="memItemLeft" align="right" valign="top"><a id="a959ff0cf7e060192dbd3cf558317e533"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA16N_CCL_IN0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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<tr class="separator:a959ff0cf7e060192dbd3cf558317e533"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af5a6f30681fe96a593bea8ac80115503"><td class="memItemLeft" align="right" valign="top"><a id="af5a6f30681fe96a593bea8ac80115503"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA16N_CCL_IN0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ad912a8ab729ff9e3592013be39a5a8d4">PIN_PA16N_CCL_IN0</a> << 16) | MUX_PA16N_CCL_IN0)</td></tr>
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<tr class="separator:af5a6f30681fe96a593bea8ac80115503"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a12d86c8dde7f949b42fb06b6c3147b7e"><td class="memItemLeft" align="right" valign="top"><a id="a12d86c8dde7f949b42fb06b6c3147b7e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA16N_CCL_IN0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 16)</td></tr>
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<tr class="separator:a12d86c8dde7f949b42fb06b6c3147b7e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa02cfb0c81f3c0f99f3ac828ed8aea71"><td class="memItemLeft" align="right" valign="top"><a id="aa02cfb0c81f3c0f99f3ac828ed8aea71"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa02cfb0c81f3c0f99f3ac828ed8aea71">PIN_PB22N_CCL_IN0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(54)</td></tr>
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<tr class="memdesc:aa02cfb0c81f3c0f99f3ac828ed8aea71"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: IN0 on PB22 mux N. <br /></td></tr>
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<tr class="separator:aa02cfb0c81f3c0f99f3ac828ed8aea71"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a291688c17d63d623796f8ff5214540fa"><td class="memItemLeft" align="right" valign="top"><a id="a291688c17d63d623796f8ff5214540fa"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB22N_CCL_IN0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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<tr class="separator:a291688c17d63d623796f8ff5214540fa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a327a6e5ce2e0fa9c7fba2d40dbd15eb7"><td class="memItemLeft" align="right" valign="top"><a id="a327a6e5ce2e0fa9c7fba2d40dbd15eb7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB22N_CCL_IN0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aa02cfb0c81f3c0f99f3ac828ed8aea71">PIN_PB22N_CCL_IN0</a> << 16) | MUX_PB22N_CCL_IN0)</td></tr>
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<tr class="separator:a327a6e5ce2e0fa9c7fba2d40dbd15eb7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6c61de14d35104d11ff1f364a7770b31"><td class="memItemLeft" align="right" valign="top"><a id="a6c61de14d35104d11ff1f364a7770b31"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB22N_CCL_IN0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 22)</td></tr>
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<tr class="separator:a6c61de14d35104d11ff1f364a7770b31"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa2cf0ddb8d47e79b6405245a359dcd51"><td class="memItemLeft" align="right" valign="top"><a id="aa2cf0ddb8d47e79b6405245a359dcd51"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa2cf0ddb8d47e79b6405245a359dcd51">PIN_PA05N_CCL_IN1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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<tr class="memdesc:aa2cf0ddb8d47e79b6405245a359dcd51"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: IN1 on PA05 mux N. <br /></td></tr>
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<tr class="separator:aa2cf0ddb8d47e79b6405245a359dcd51"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afc8f530bedcfac123bb9a53c2345ecc8"><td class="memItemLeft" align="right" valign="top"><a id="afc8f530bedcfac123bb9a53c2345ecc8"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA05N_CCL_IN1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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<tr class="memitem:a1f4435320978a408317a31a2fa21b6c0"><td class="memItemLeft" align="right" valign="top"><a id="a1f4435320978a408317a31a2fa21b6c0"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA05N_CCL_IN1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aa2cf0ddb8d47e79b6405245a359dcd51">PIN_PA05N_CCL_IN1</a> << 16) | MUX_PA05N_CCL_IN1)</td></tr>
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<tr class="memitem:af6b545149b48f5350c40762bb752758c"><td class="memItemLeft" align="right" valign="top"><a id="af6b545149b48f5350c40762bb752758c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA05N_CCL_IN1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 5)</td></tr>
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<tr class="memitem:a26704bd685973b7b55bcd94a1b648b28"><td class="memItemLeft" align="right" valign="top"><a id="a26704bd685973b7b55bcd94a1b648b28"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a26704bd685973b7b55bcd94a1b648b28">PIN_PA17N_CCL_IN1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(17)</td></tr>
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<tr class="memdesc:a26704bd685973b7b55bcd94a1b648b28"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: IN1 on PA17 mux N. <br /></td></tr>
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<tr class="separator:a26704bd685973b7b55bcd94a1b648b28"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0159f3442d16b102ba48d04bd2629b1b"><td class="memItemLeft" align="right" valign="top"><a id="a0159f3442d16b102ba48d04bd2629b1b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA17N_CCL_IN1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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<tr class="separator:a0159f3442d16b102ba48d04bd2629b1b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa7d00d8b347ead199518d4a6a25977e4"><td class="memItemLeft" align="right" valign="top"><a id="aa7d00d8b347ead199518d4a6a25977e4"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA17N_CCL_IN1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a26704bd685973b7b55bcd94a1b648b28">PIN_PA17N_CCL_IN1</a> << 16) | MUX_PA17N_CCL_IN1)</td></tr>
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<tr class="separator:aa7d00d8b347ead199518d4a6a25977e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac67e6122fc8fbb40c3ec70480d63013a"><td class="memItemLeft" align="right" valign="top"><a id="ac67e6122fc8fbb40c3ec70480d63013a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA17N_CCL_IN1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 17)</td></tr>
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<tr class="separator:ac67e6122fc8fbb40c3ec70480d63013a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0bd45176e0dce96a567d47fd10740ffd"><td class="memItemLeft" align="right" valign="top"><a id="a0bd45176e0dce96a567d47fd10740ffd"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0bd45176e0dce96a567d47fd10740ffd">PIN_PB00N_CCL_IN1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(32)</td></tr>
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<tr class="memdesc:a0bd45176e0dce96a567d47fd10740ffd"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: IN1 on PB00 mux N. <br /></td></tr>
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<tr class="separator:a0bd45176e0dce96a567d47fd10740ffd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a80dbdb801218e50dcaacce2088b41556"><td class="memItemLeft" align="right" valign="top"><a id="a80dbdb801218e50dcaacce2088b41556"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB00N_CCL_IN1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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<tr class="separator:a80dbdb801218e50dcaacce2088b41556"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a70301c79f4ad096c979131df238888cc"><td class="memItemLeft" align="right" valign="top"><a id="a70301c79f4ad096c979131df238888cc"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB00N_CCL_IN1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a0bd45176e0dce96a567d47fd10740ffd">PIN_PB00N_CCL_IN1</a> << 16) | MUX_PB00N_CCL_IN1)</td></tr>
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<tr class="separator:a70301c79f4ad096c979131df238888cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa8c25caa58543fce602702ea35f78abc"><td class="memItemLeft" align="right" valign="top"><a id="aa8c25caa58543fce602702ea35f78abc"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB00N_CCL_IN1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 0)</td></tr>
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<tr class="separator:aa8c25caa58543fce602702ea35f78abc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a30783890bdbe4487b6ec911d5b25c0f7"><td class="memItemLeft" align="right" valign="top"><a id="a30783890bdbe4487b6ec911d5b25c0f7"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a30783890bdbe4487b6ec911d5b25c0f7">PIN_PA06N_CCL_IN2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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<tr class="memdesc:a30783890bdbe4487b6ec911d5b25c0f7"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: IN2 on PA06 mux N. <br /></td></tr>
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<tr class="separator:a30783890bdbe4487b6ec911d5b25c0f7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a800eff674c29172aa7adc959e0e50eca"><td class="memItemLeft" align="right" valign="top"><a id="a800eff674c29172aa7adc959e0e50eca"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA06N_CCL_IN2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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<tr class="separator:a800eff674c29172aa7adc959e0e50eca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7c80f72ba7aea03585182fc989e60e9c"><td class="memItemLeft" align="right" valign="top"><a id="a7c80f72ba7aea03585182fc989e60e9c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA06N_CCL_IN2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a30783890bdbe4487b6ec911d5b25c0f7">PIN_PA06N_CCL_IN2</a> << 16) | MUX_PA06N_CCL_IN2)</td></tr>
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<tr class="separator:a7c80f72ba7aea03585182fc989e60e9c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa805ce7934e6bcf1e5e15073cbd21b4c"><td class="memItemLeft" align="right" valign="top"><a id="aa805ce7934e6bcf1e5e15073cbd21b4c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA06N_CCL_IN2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 6)</td></tr>
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<tr class="separator:aa805ce7934e6bcf1e5e15073cbd21b4c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a523b999dbb4c541f10d84e41f41f9fec"><td class="memItemLeft" align="right" valign="top"><a id="a523b999dbb4c541f10d84e41f41f9fec"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a523b999dbb4c541f10d84e41f41f9fec">PIN_PA18N_CCL_IN2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(18)</td></tr>
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||
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<tr class="memdesc:a523b999dbb4c541f10d84e41f41f9fec"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: IN2 on PA18 mux N. <br /></td></tr>
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<tr class="separator:a523b999dbb4c541f10d84e41f41f9fec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1357381866362b6b25157e7e6638f18c"><td class="memItemLeft" align="right" valign="top"><a id="a1357381866362b6b25157e7e6638f18c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA18N_CCL_IN2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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<tr class="separator:a1357381866362b6b25157e7e6638f18c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aaed1ad0cace2d9a0e0eda36bcb539f56"><td class="memItemLeft" align="right" valign="top"><a id="aaed1ad0cace2d9a0e0eda36bcb539f56"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA18N_CCL_IN2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a523b999dbb4c541f10d84e41f41f9fec">PIN_PA18N_CCL_IN2</a> << 16) | MUX_PA18N_CCL_IN2)</td></tr>
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<tr class="separator:aaed1ad0cace2d9a0e0eda36bcb539f56"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a49f22b97c40f218aa3ebb155e31ab7c9"><td class="memItemLeft" align="right" valign="top"><a id="a49f22b97c40f218aa3ebb155e31ab7c9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA18N_CCL_IN2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 18)</td></tr>
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<tr class="separator:a49f22b97c40f218aa3ebb155e31ab7c9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a75820aa12407e7562b27165c0f019f68"><td class="memItemLeft" align="right" valign="top"><a id="a75820aa12407e7562b27165c0f019f68"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a75820aa12407e7562b27165c0f019f68">PIN_PB01N_CCL_IN2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(33)</td></tr>
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||
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<tr class="memdesc:a75820aa12407e7562b27165c0f019f68"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: IN2 on PB01 mux N. <br /></td></tr>
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<tr class="separator:a75820aa12407e7562b27165c0f019f68"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aedba633afb9b80bca972d452bd58dd46"><td class="memItemLeft" align="right" valign="top"><a id="aedba633afb9b80bca972d452bd58dd46"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB01N_CCL_IN2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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<tr class="separator:aedba633afb9b80bca972d452bd58dd46"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae689eff228f84e07d979eeb60565cb08"><td class="memItemLeft" align="right" valign="top"><a id="ae689eff228f84e07d979eeb60565cb08"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB01N_CCL_IN2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a75820aa12407e7562b27165c0f019f68">PIN_PB01N_CCL_IN2</a> << 16) | MUX_PB01N_CCL_IN2)</td></tr>
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<tr class="separator:ae689eff228f84e07d979eeb60565cb08"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a01c5fd043ff2b1bd67fb21bac72cd9d5"><td class="memItemLeft" align="right" valign="top"><a id="a01c5fd043ff2b1bd67fb21bac72cd9d5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB01N_CCL_IN2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 1)</td></tr>
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||
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<tr class="separator:a01c5fd043ff2b1bd67fb21bac72cd9d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab8abb6052c59b4f4a406bed9cfc061a6"><td class="memItemLeft" align="right" valign="top"><a id="ab8abb6052c59b4f4a406bed9cfc061a6"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab8abb6052c59b4f4a406bed9cfc061a6">PIN_PA08N_CCL_IN3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
|
||
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<tr class="memdesc:ab8abb6052c59b4f4a406bed9cfc061a6"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: IN3 on PA08 mux N. <br /></td></tr>
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<tr class="separator:ab8abb6052c59b4f4a406bed9cfc061a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a55e38849b3035c54d232fdea1d7013e4"><td class="memItemLeft" align="right" valign="top"><a id="a55e38849b3035c54d232fdea1d7013e4"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA08N_CCL_IN3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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<tr class="separator:a55e38849b3035c54d232fdea1d7013e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a906ceb7157b66b922c0518e4466a6beb"><td class="memItemLeft" align="right" valign="top"><a id="a906ceb7157b66b922c0518e4466a6beb"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA08N_CCL_IN3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ab8abb6052c59b4f4a406bed9cfc061a6">PIN_PA08N_CCL_IN3</a> << 16) | MUX_PA08N_CCL_IN3)</td></tr>
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<tr class="separator:a906ceb7157b66b922c0518e4466a6beb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a995d7a60f3396bd16118e7b2fad43d24"><td class="memItemLeft" align="right" valign="top"><a id="a995d7a60f3396bd16118e7b2fad43d24"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA08N_CCL_IN3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 8)</td></tr>
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||
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<tr class="separator:a995d7a60f3396bd16118e7b2fad43d24"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a209a21781acd42a4266a726971ce4715"><td class="memItemLeft" align="right" valign="top"><a id="a209a21781acd42a4266a726971ce4715"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a209a21781acd42a4266a726971ce4715">PIN_PA30N_CCL_IN3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(30)</td></tr>
|
||
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<tr class="memdesc:a209a21781acd42a4266a726971ce4715"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: IN3 on PA30 mux N. <br /></td></tr>
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<tr class="separator:a209a21781acd42a4266a726971ce4715"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae0171078b28d0e1e8a172d921fb668ee"><td class="memItemLeft" align="right" valign="top"><a id="ae0171078b28d0e1e8a172d921fb668ee"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA30N_CCL_IN3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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<tr class="separator:ae0171078b28d0e1e8a172d921fb668ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0e62ed6f3fd3efd856f22837236ab23e"><td class="memItemLeft" align="right" valign="top"><a id="a0e62ed6f3fd3efd856f22837236ab23e"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA30N_CCL_IN3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a209a21781acd42a4266a726971ce4715">PIN_PA30N_CCL_IN3</a> << 16) | MUX_PA30N_CCL_IN3)</td></tr>
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<tr class="separator:a0e62ed6f3fd3efd856f22837236ab23e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae5fe4f96b7fe1c645c252bab8e185ae9"><td class="memItemLeft" align="right" valign="top"><a id="ae5fe4f96b7fe1c645c252bab8e185ae9"></a>
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA30N_CCL_IN3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 30)</td></tr>
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<tr class="separator:ae5fe4f96b7fe1c645c252bab8e185ae9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0fdd8f70cb065100975d214e1e5297f4"><td class="memItemLeft" align="right" valign="top"><a id="a0fdd8f70cb065100975d214e1e5297f4"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0fdd8f70cb065100975d214e1e5297f4">PIN_PA09N_CCL_IN4</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
|
||
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<tr class="memdesc:a0fdd8f70cb065100975d214e1e5297f4"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: IN4 on PA09 mux N. <br /></td></tr>
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<tr class="separator:a0fdd8f70cb065100975d214e1e5297f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab3ac6aea13b60603f136f0b06a6423e8"><td class="memItemLeft" align="right" valign="top"><a id="ab3ac6aea13b60603f136f0b06a6423e8"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA09N_CCL_IN4</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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<tr class="separator:ab3ac6aea13b60603f136f0b06a6423e8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3c109f049aa23dfd047fcc1c4c23c671"><td class="memItemLeft" align="right" valign="top"><a id="a3c109f049aa23dfd047fcc1c4c23c671"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA09N_CCL_IN4</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a0fdd8f70cb065100975d214e1e5297f4">PIN_PA09N_CCL_IN4</a> << 16) | MUX_PA09N_CCL_IN4)</td></tr>
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<tr class="separator:a3c109f049aa23dfd047fcc1c4c23c671"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2a6dd6152eab900522f17b1b65a32472"><td class="memItemLeft" align="right" valign="top"><a id="a2a6dd6152eab900522f17b1b65a32472"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA09N_CCL_IN4</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 9)</td></tr>
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||
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<tr class="separator:a2a6dd6152eab900522f17b1b65a32472"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4671f73b47879a0ee57c7a7185f80965"><td class="memItemLeft" align="right" valign="top"><a id="a4671f73b47879a0ee57c7a7185f80965"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4671f73b47879a0ee57c7a7185f80965">PIN_PC27N_CCL_IN4</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(91)</td></tr>
|
||
|
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<tr class="memdesc:a4671f73b47879a0ee57c7a7185f80965"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: IN4 on PC27 mux N. <br /></td></tr>
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<tr class="separator:a4671f73b47879a0ee57c7a7185f80965"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a83634a3fab3735da3ed710ccadcc776d"><td class="memItemLeft" align="right" valign="top"><a id="a83634a3fab3735da3ed710ccadcc776d"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC27N_CCL_IN4</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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||
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<tr class="separator:a83634a3fab3735da3ed710ccadcc776d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af69b0dccad47289a448f10f0e9247197"><td class="memItemLeft" align="right" valign="top"><a id="af69b0dccad47289a448f10f0e9247197"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC27N_CCL_IN4</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a4671f73b47879a0ee57c7a7185f80965">PIN_PC27N_CCL_IN4</a> << 16) | MUX_PC27N_CCL_IN4)</td></tr>
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<tr class="separator:af69b0dccad47289a448f10f0e9247197"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a65df3e1a06dea28fca95ce9d12fb171b"><td class="memItemLeft" align="right" valign="top"><a id="a65df3e1a06dea28fca95ce9d12fb171b"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC27N_CCL_IN4</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 27)</td></tr>
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||
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<tr class="separator:a65df3e1a06dea28fca95ce9d12fb171b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab5ab8798d19eb2220273f493b8a48832"><td class="memItemLeft" align="right" valign="top"><a id="ab5ab8798d19eb2220273f493b8a48832"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab5ab8798d19eb2220273f493b8a48832">PIN_PA10N_CCL_IN5</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
|
||
|
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<tr class="memdesc:ab5ab8798d19eb2220273f493b8a48832"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: IN5 on PA10 mux N. <br /></td></tr>
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||
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<tr class="separator:ab5ab8798d19eb2220273f493b8a48832"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:aeb71a6f9f895a5d9d677f5ca4c910d85"><td class="memItemLeft" align="right" valign="top"><a id="aeb71a6f9f895a5d9d677f5ca4c910d85"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA10N_CCL_IN5</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
|
||
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<tr class="separator:aeb71a6f9f895a5d9d677f5ca4c910d85"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:adfa636098f459fa734f5d030cf9f5906"><td class="memItemLeft" align="right" valign="top"><a id="adfa636098f459fa734f5d030cf9f5906"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA10N_CCL_IN5</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ab5ab8798d19eb2220273f493b8a48832">PIN_PA10N_CCL_IN5</a> << 16) | MUX_PA10N_CCL_IN5)</td></tr>
|
||
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<tr class="separator:adfa636098f459fa734f5d030cf9f5906"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a8d472c7ce1cd5ac699e328f718f73495"><td class="memItemLeft" align="right" valign="top"><a id="a8d472c7ce1cd5ac699e328f718f73495"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA10N_CCL_IN5</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 10)</td></tr>
|
||
|
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<tr class="separator:a8d472c7ce1cd5ac699e328f718f73495"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a7f1fc902563874dc2cfb0d987299767f"><td class="memItemLeft" align="right" valign="top"><a id="a7f1fc902563874dc2cfb0d987299767f"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7f1fc902563874dc2cfb0d987299767f">PIN_PC28N_CCL_IN5</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(92)</td></tr>
|
||
|
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<tr class="memdesc:a7f1fc902563874dc2cfb0d987299767f"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: IN5 on PC28 mux N. <br /></td></tr>
|
||
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<tr class="separator:a7f1fc902563874dc2cfb0d987299767f"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:ae323bea035d6a0c171c692c28761a3e5"><td class="memItemLeft" align="right" valign="top"><a id="ae323bea035d6a0c171c692c28761a3e5"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC28N_CCL_IN5</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
|
||
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<tr class="separator:ae323bea035d6a0c171c692c28761a3e5"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a170d235ecdd5dd63b5ef525a2bd78851"><td class="memItemLeft" align="right" valign="top"><a id="a170d235ecdd5dd63b5ef525a2bd78851"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC28N_CCL_IN5</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a7f1fc902563874dc2cfb0d987299767f">PIN_PC28N_CCL_IN5</a> << 16) | MUX_PC28N_CCL_IN5)</td></tr>
|
||
|
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<tr class="separator:a170d235ecdd5dd63b5ef525a2bd78851"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a4fad7fd94b49bb7ace1d923a1dfd117c"><td class="memItemLeft" align="right" valign="top"><a id="a4fad7fd94b49bb7ace1d923a1dfd117c"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC28N_CCL_IN5</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 28)</td></tr>
|
||
|
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<tr class="separator:a4fad7fd94b49bb7ace1d923a1dfd117c"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:a8b830511de49d9d970838acd37a2c813"><td class="memItemLeft" align="right" valign="top"><a id="a8b830511de49d9d970838acd37a2c813"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8b830511de49d9d970838acd37a2c813">PIN_PA22N_CCL_IN6</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(22)</td></tr>
|
||
|
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<tr class="memdesc:a8b830511de49d9d970838acd37a2c813"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: IN6 on PA22 mux N. <br /></td></tr>
|
||
|
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<tr class="separator:a8b830511de49d9d970838acd37a2c813"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a655a7100804c2a0ddbaeabad56329306"><td class="memItemLeft" align="right" valign="top"><a id="a655a7100804c2a0ddbaeabad56329306"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA22N_CCL_IN6</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
|
||
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<tr class="separator:a655a7100804c2a0ddbaeabad56329306"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a92f896c4091c0c5e6634f69a3c38b03c"><td class="memItemLeft" align="right" valign="top"><a id="a92f896c4091c0c5e6634f69a3c38b03c"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA22N_CCL_IN6</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a8b830511de49d9d970838acd37a2c813">PIN_PA22N_CCL_IN6</a> << 16) | MUX_PA22N_CCL_IN6)</td></tr>
|
||
|
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<tr class="separator:a92f896c4091c0c5e6634f69a3c38b03c"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:a12ae7d65d60bd1df4c48446409fada59"><td class="memItemLeft" align="right" valign="top"><a id="a12ae7d65d60bd1df4c48446409fada59"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA22N_CCL_IN6</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 22)</td></tr>
|
||
|
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<tr class="separator:a12ae7d65d60bd1df4c48446409fada59"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:a783d8f4923536ff311297369b3e632f4"><td class="memItemLeft" align="right" valign="top"><a id="a783d8f4923536ff311297369b3e632f4"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a783d8f4923536ff311297369b3e632f4">PIN_PB06N_CCL_IN6</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(38)</td></tr>
|
||
|
|
<tr class="memdesc:a783d8f4923536ff311297369b3e632f4"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: IN6 on PB06 mux N. <br /></td></tr>
|
||
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<tr class="separator:a783d8f4923536ff311297369b3e632f4"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a2ff2c906156794ab61ea457ceb6ed682"><td class="memItemLeft" align="right" valign="top"><a id="a2ff2c906156794ab61ea457ceb6ed682"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB06N_CCL_IN6</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
|
||
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<tr class="separator:a2ff2c906156794ab61ea457ceb6ed682"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a45dd0701d529049a46d6b31c0c9d2435"><td class="memItemLeft" align="right" valign="top"><a id="a45dd0701d529049a46d6b31c0c9d2435"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB06N_CCL_IN6</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a783d8f4923536ff311297369b3e632f4">PIN_PB06N_CCL_IN6</a> << 16) | MUX_PB06N_CCL_IN6)</td></tr>
|
||
|
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<tr class="separator:a45dd0701d529049a46d6b31c0c9d2435"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:afd862108da214b1a9d5e6e85b578ac57"><td class="memItemLeft" align="right" valign="top"><a id="afd862108da214b1a9d5e6e85b578ac57"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB06N_CCL_IN6</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 6)</td></tr>
|
||
|
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<tr class="separator:afd862108da214b1a9d5e6e85b578ac57"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:a4b6446e2cefb7c5e027e0a138f2c56af"><td class="memItemLeft" align="right" valign="top"><a id="a4b6446e2cefb7c5e027e0a138f2c56af"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4b6446e2cefb7c5e027e0a138f2c56af">PIN_PA23N_CCL_IN7</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(23)</td></tr>
|
||
|
|
<tr class="memdesc:a4b6446e2cefb7c5e027e0a138f2c56af"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: IN7 on PA23 mux N. <br /></td></tr>
|
||
|
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<tr class="separator:a4b6446e2cefb7c5e027e0a138f2c56af"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:ac7d379fcbdc533b9134b727daa5dfdf7"><td class="memItemLeft" align="right" valign="top"><a id="ac7d379fcbdc533b9134b727daa5dfdf7"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA23N_CCL_IN7</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
|
||
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<tr class="separator:ac7d379fcbdc533b9134b727daa5dfdf7"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:aaea2260c453dc98cffd422b4e9172ffb"><td class="memItemLeft" align="right" valign="top"><a id="aaea2260c453dc98cffd422b4e9172ffb"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA23N_CCL_IN7</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a4b6446e2cefb7c5e027e0a138f2c56af">PIN_PA23N_CCL_IN7</a> << 16) | MUX_PA23N_CCL_IN7)</td></tr>
|
||
|
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<tr class="separator:aaea2260c453dc98cffd422b4e9172ffb"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a9b2da131d3ee82eab2ff72e7c6e0b0e3"><td class="memItemLeft" align="right" valign="top"><a id="a9b2da131d3ee82eab2ff72e7c6e0b0e3"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA23N_CCL_IN7</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 23)</td></tr>
|
||
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<tr class="separator:a9b2da131d3ee82eab2ff72e7c6e0b0e3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adbf0080b72bf2877f4b3297fe85836a7"><td class="memItemLeft" align="right" valign="top"><a id="adbf0080b72bf2877f4b3297fe85836a7"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#adbf0080b72bf2877f4b3297fe85836a7">PIN_PB07N_CCL_IN7</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(39)</td></tr>
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||
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<tr class="memdesc:adbf0080b72bf2877f4b3297fe85836a7"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: IN7 on PB07 mux N. <br /></td></tr>
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<tr class="separator:adbf0080b72bf2877f4b3297fe85836a7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8b17a2dc8919161876a6a823e9f5fd82"><td class="memItemLeft" align="right" valign="top"><a id="a8b17a2dc8919161876a6a823e9f5fd82"></a>
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB07N_CCL_IN7</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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<tr class="separator:a8b17a2dc8919161876a6a823e9f5fd82"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac17308ebf9e0fd79d086e84738f967e6"><td class="memItemLeft" align="right" valign="top"><a id="ac17308ebf9e0fd79d086e84738f967e6"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB07N_CCL_IN7</b>   ((<a class="el" href="pio_2same54p20a_8h.html#adbf0080b72bf2877f4b3297fe85836a7">PIN_PB07N_CCL_IN7</a> << 16) | MUX_PB07N_CCL_IN7)</td></tr>
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<tr class="separator:ac17308ebf9e0fd79d086e84738f967e6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2503ae5bc1933c3d5b565da67f5c3346"><td class="memItemLeft" align="right" valign="top"><a id="a2503ae5bc1933c3d5b565da67f5c3346"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB07N_CCL_IN7</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 7)</td></tr>
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||
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<tr class="separator:a2503ae5bc1933c3d5b565da67f5c3346"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa71902621f48e409ca79bfbae325d1ac"><td class="memItemLeft" align="right" valign="top"><a id="aa71902621f48e409ca79bfbae325d1ac"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa71902621f48e409ca79bfbae325d1ac">PIN_PA24N_CCL_IN8</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(24)</td></tr>
|
||
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<tr class="memdesc:aa71902621f48e409ca79bfbae325d1ac"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: IN8 on PA24 mux N. <br /></td></tr>
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<tr class="separator:aa71902621f48e409ca79bfbae325d1ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a86b192f4b043774be6f06ab199bb1038"><td class="memItemLeft" align="right" valign="top"><a id="a86b192f4b043774be6f06ab199bb1038"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA24N_CCL_IN8</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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<tr class="separator:a86b192f4b043774be6f06ab199bb1038"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a11e8ad92b02c2fd76688664810bc5ad7"><td class="memItemLeft" align="right" valign="top"><a id="a11e8ad92b02c2fd76688664810bc5ad7"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA24N_CCL_IN8</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aa71902621f48e409ca79bfbae325d1ac">PIN_PA24N_CCL_IN8</a> << 16) | MUX_PA24N_CCL_IN8)</td></tr>
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<tr class="separator:a11e8ad92b02c2fd76688664810bc5ad7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3d7bbc94abc3f43976ce2bee5af53eb0"><td class="memItemLeft" align="right" valign="top"><a id="a3d7bbc94abc3f43976ce2bee5af53eb0"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA24N_CCL_IN8</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 24)</td></tr>
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||
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<tr class="separator:a3d7bbc94abc3f43976ce2bee5af53eb0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a19c266acf1544e888fc19f9a73fe9dd4"><td class="memItemLeft" align="right" valign="top"><a id="a19c266acf1544e888fc19f9a73fe9dd4"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a19c266acf1544e888fc19f9a73fe9dd4">PIN_PB08N_CCL_IN8</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(40)</td></tr>
|
||
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<tr class="memdesc:a19c266acf1544e888fc19f9a73fe9dd4"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: IN8 on PB08 mux N. <br /></td></tr>
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<tr class="separator:a19c266acf1544e888fc19f9a73fe9dd4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1b7c9aec030143c95fcb22bb60aa7188"><td class="memItemLeft" align="right" valign="top"><a id="a1b7c9aec030143c95fcb22bb60aa7188"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB08N_CCL_IN8</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
|
||
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<tr class="separator:a1b7c9aec030143c95fcb22bb60aa7188"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a3f219b19cc07687ba98e856b352039d2"><td class="memItemLeft" align="right" valign="top"><a id="a3f219b19cc07687ba98e856b352039d2"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB08N_CCL_IN8</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a19c266acf1544e888fc19f9a73fe9dd4">PIN_PB08N_CCL_IN8</a> << 16) | MUX_PB08N_CCL_IN8)</td></tr>
|
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<tr class="separator:a3f219b19cc07687ba98e856b352039d2"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a5500c485959bcab94ad32e724d25a144"><td class="memItemLeft" align="right" valign="top"><a id="a5500c485959bcab94ad32e724d25a144"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB08N_CCL_IN8</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 8)</td></tr>
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||
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<tr class="separator:a5500c485959bcab94ad32e724d25a144"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a7d6cc99ec8997e28bd7bcb464adc4c99"><td class="memItemLeft" align="right" valign="top"><a id="a7d6cc99ec8997e28bd7bcb464adc4c99"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7d6cc99ec8997e28bd7bcb464adc4c99">PIN_PB14N_CCL_IN9</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(46)</td></tr>
|
||
|
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<tr class="memdesc:a7d6cc99ec8997e28bd7bcb464adc4c99"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: IN9 on PB14 mux N. <br /></td></tr>
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||
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<tr class="separator:a7d6cc99ec8997e28bd7bcb464adc4c99"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a173502a5b73d59602ad7318d043a0080"><td class="memItemLeft" align="right" valign="top"><a id="a173502a5b73d59602ad7318d043a0080"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB14N_CCL_IN9</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
|
||
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<tr class="separator:a173502a5b73d59602ad7318d043a0080"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a36f8ad3c0c1124fc7ffecba78bdf56bf"><td class="memItemLeft" align="right" valign="top"><a id="a36f8ad3c0c1124fc7ffecba78bdf56bf"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB14N_CCL_IN9</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a7d6cc99ec8997e28bd7bcb464adc4c99">PIN_PB14N_CCL_IN9</a> << 16) | MUX_PB14N_CCL_IN9)</td></tr>
|
||
|
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<tr class="separator:a36f8ad3c0c1124fc7ffecba78bdf56bf"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:aea449e83531c18fb25557454965a9b6c"><td class="memItemLeft" align="right" valign="top"><a id="aea449e83531c18fb25557454965a9b6c"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB14N_CCL_IN9</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 14)</td></tr>
|
||
|
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<tr class="separator:aea449e83531c18fb25557454965a9b6c"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:acb93478906ebd008e9928c5b9b935e18"><td class="memItemLeft" align="right" valign="top"><a id="acb93478906ebd008e9928c5b9b935e18"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#acb93478906ebd008e9928c5b9b935e18">PIN_PC20N_CCL_IN9</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(84)</td></tr>
|
||
|
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<tr class="memdesc:acb93478906ebd008e9928c5b9b935e18"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: IN9 on PC20 mux N. <br /></td></tr>
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||
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<tr class="separator:acb93478906ebd008e9928c5b9b935e18"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:af6245db7b31c6d225c29547fa9b73c93"><td class="memItemLeft" align="right" valign="top"><a id="af6245db7b31c6d225c29547fa9b73c93"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC20N_CCL_IN9</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
|
||
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<tr class="separator:af6245db7b31c6d225c29547fa9b73c93"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a5f28fc77ed7741cdf650de11ce73fdd3"><td class="memItemLeft" align="right" valign="top"><a id="a5f28fc77ed7741cdf650de11ce73fdd3"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC20N_CCL_IN9</b>   ((<a class="el" href="pio_2same54p20a_8h.html#acb93478906ebd008e9928c5b9b935e18">PIN_PC20N_CCL_IN9</a> << 16) | MUX_PC20N_CCL_IN9)</td></tr>
|
||
|
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<tr class="separator:a5f28fc77ed7741cdf650de11ce73fdd3"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a70ef06dca9b14d91a190171322d498c7"><td class="memItemLeft" align="right" valign="top"><a id="a70ef06dca9b14d91a190171322d498c7"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC20N_CCL_IN9</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 20)</td></tr>
|
||
|
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<tr class="separator:a70ef06dca9b14d91a190171322d498c7"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a700bb325b3d756f29e71da236d0bf601"><td class="memItemLeft" align="right" valign="top"><a id="a700bb325b3d756f29e71da236d0bf601"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a700bb325b3d756f29e71da236d0bf601">PIN_PB15N_CCL_IN10</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(47)</td></tr>
|
||
|
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<tr class="memdesc:a700bb325b3d756f29e71da236d0bf601"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: IN10 on PB15 mux N. <br /></td></tr>
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<tr class="separator:a700bb325b3d756f29e71da236d0bf601"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:aee76032ffa88f62a8f6c2897fc4659bb"><td class="memItemLeft" align="right" valign="top"><a id="aee76032ffa88f62a8f6c2897fc4659bb"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB15N_CCL_IN10</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
|
||
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<tr class="separator:aee76032ffa88f62a8f6c2897fc4659bb"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a29d90f8c6fbef84eb7e6d6ad85b59a75"><td class="memItemLeft" align="right" valign="top"><a id="a29d90f8c6fbef84eb7e6d6ad85b59a75"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB15N_CCL_IN10</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a700bb325b3d756f29e71da236d0bf601">PIN_PB15N_CCL_IN10</a> << 16) | MUX_PB15N_CCL_IN10)</td></tr>
|
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<tr class="separator:a29d90f8c6fbef84eb7e6d6ad85b59a75"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a85788d9809c6d72a9e289cfa1d66c088"><td class="memItemLeft" align="right" valign="top"><a id="a85788d9809c6d72a9e289cfa1d66c088"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB15N_CCL_IN10</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 15)</td></tr>
|
||
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<tr class="separator:a85788d9809c6d72a9e289cfa1d66c088"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a932a786ccb928b78e5892ca25c985d5b"><td class="memItemLeft" align="right" valign="top"><a id="a932a786ccb928b78e5892ca25c985d5b"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a932a786ccb928b78e5892ca25c985d5b">PIN_PC21N_CCL_IN10</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(85)</td></tr>
|
||
|
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<tr class="memdesc:a932a786ccb928b78e5892ca25c985d5b"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: IN10 on PC21 mux N. <br /></td></tr>
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||
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<tr class="separator:a932a786ccb928b78e5892ca25c985d5b"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a1b9a6cf024362e6e652cc4bef7eab9d3"><td class="memItemLeft" align="right" valign="top"><a id="a1b9a6cf024362e6e652cc4bef7eab9d3"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC21N_CCL_IN10</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
|
||
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<tr class="separator:a1b9a6cf024362e6e652cc4bef7eab9d3"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a41b8e5bad22e0745986fffe67c5c22d7"><td class="memItemLeft" align="right" valign="top"><a id="a41b8e5bad22e0745986fffe67c5c22d7"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC21N_CCL_IN10</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a932a786ccb928b78e5892ca25c985d5b">PIN_PC21N_CCL_IN10</a> << 16) | MUX_PC21N_CCL_IN10)</td></tr>
|
||
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<tr class="separator:a41b8e5bad22e0745986fffe67c5c22d7"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a7d437c8f5699c3ca792730d217f78cf2"><td class="memItemLeft" align="right" valign="top"><a id="a7d437c8f5699c3ca792730d217f78cf2"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC21N_CCL_IN10</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 21)</td></tr>
|
||
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<tr class="separator:a7d437c8f5699c3ca792730d217f78cf2"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a57e976436dcca255984160c11f790587"><td class="memItemLeft" align="right" valign="top"><a id="a57e976436dcca255984160c11f790587"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a57e976436dcca255984160c11f790587">PIN_PB10N_CCL_IN11</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(42)</td></tr>
|
||
|
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<tr class="memdesc:a57e976436dcca255984160c11f790587"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: IN11 on PB10 mux N. <br /></td></tr>
|
||
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<tr class="separator:a57e976436dcca255984160c11f790587"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af4b5bac3e46107fc2037fcd2cd4c25b1"><td class="memItemLeft" align="right" valign="top"><a id="af4b5bac3e46107fc2037fcd2cd4c25b1"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB10N_CCL_IN11</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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<tr class="memitem:a134df348a8d3a3d130e6a4233bf340a0"><td class="memItemLeft" align="right" valign="top"><a id="a134df348a8d3a3d130e6a4233bf340a0"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB10N_CCL_IN11</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a57e976436dcca255984160c11f790587">PIN_PB10N_CCL_IN11</a> << 16) | MUX_PB10N_CCL_IN11)</td></tr>
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<tr class="separator:a134df348a8d3a3d130e6a4233bf340a0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac4fe375c2d078a1a57c7f54fde69dff2"><td class="memItemLeft" align="right" valign="top"><a id="ac4fe375c2d078a1a57c7f54fde69dff2"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB10N_CCL_IN11</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 10)</td></tr>
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<tr class="separator:ac4fe375c2d078a1a57c7f54fde69dff2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adffa67672dca7de317d99e378c565cc4"><td class="memItemLeft" align="right" valign="top"><a id="adffa67672dca7de317d99e378c565cc4"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#adffa67672dca7de317d99e378c565cc4">PIN_PB16N_CCL_IN11</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(48)</td></tr>
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<tr class="memdesc:adffa67672dca7de317d99e378c565cc4"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: IN11 on PB16 mux N. <br /></td></tr>
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<tr class="separator:adffa67672dca7de317d99e378c565cc4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab9c145415656b615f17f7a22e4e66bf3"><td class="memItemLeft" align="right" valign="top"><a id="ab9c145415656b615f17f7a22e4e66bf3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB16N_CCL_IN11</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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<tr class="separator:ab9c145415656b615f17f7a22e4e66bf3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae9d626ca45ac881d014d411afad9a2da"><td class="memItemLeft" align="right" valign="top"><a id="ae9d626ca45ac881d014d411afad9a2da"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB16N_CCL_IN11</b>   ((<a class="el" href="pio_2same54p20a_8h.html#adffa67672dca7de317d99e378c565cc4">PIN_PB16N_CCL_IN11</a> << 16) | MUX_PB16N_CCL_IN11)</td></tr>
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<tr class="separator:ae9d626ca45ac881d014d411afad9a2da"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afa1a645224388be06f775c797c1721f0"><td class="memItemLeft" align="right" valign="top"><a id="afa1a645224388be06f775c797c1721f0"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB16N_CCL_IN11</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 16)</td></tr>
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<tr class="separator:afa1a645224388be06f775c797c1721f0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad20d3d27162954c40d356c868fc7d3f1"><td class="memItemLeft" align="right" valign="top"><a id="ad20d3d27162954c40d356c868fc7d3f1"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad20d3d27162954c40d356c868fc7d3f1">PIN_PA07N_CCL_OUT0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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<tr class="memdesc:ad20d3d27162954c40d356c868fc7d3f1"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: OUT0 on PA07 mux N. <br /></td></tr>
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<tr class="separator:ad20d3d27162954c40d356c868fc7d3f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a20649f79e1e8eeb45992345940bda13f"><td class="memItemLeft" align="right" valign="top"><a id="a20649f79e1e8eeb45992345940bda13f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA07N_CCL_OUT0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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<tr class="separator:a20649f79e1e8eeb45992345940bda13f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa4fee25038e8314486e14320c4807aa5"><td class="memItemLeft" align="right" valign="top"><a id="aa4fee25038e8314486e14320c4807aa5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA07N_CCL_OUT0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ad20d3d27162954c40d356c868fc7d3f1">PIN_PA07N_CCL_OUT0</a> << 16) | MUX_PA07N_CCL_OUT0)</td></tr>
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<tr class="separator:aa4fee25038e8314486e14320c4807aa5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9e8d1b8e044317758238c64308043a80"><td class="memItemLeft" align="right" valign="top"><a id="a9e8d1b8e044317758238c64308043a80"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA07N_CCL_OUT0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 7)</td></tr>
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<tr class="separator:a9e8d1b8e044317758238c64308043a80"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aade9982add158f20548b2ce342abad88"><td class="memItemLeft" align="right" valign="top"><a id="aade9982add158f20548b2ce342abad88"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aade9982add158f20548b2ce342abad88">PIN_PA19N_CCL_OUT0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(19)</td></tr>
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<tr class="memdesc:aade9982add158f20548b2ce342abad88"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: OUT0 on PA19 mux N. <br /></td></tr>
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<tr class="separator:aade9982add158f20548b2ce342abad88"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aef2d3204a33ddffd2fe43c44d34fe097"><td class="memItemLeft" align="right" valign="top"><a id="aef2d3204a33ddffd2fe43c44d34fe097"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA19N_CCL_OUT0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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<tr class="separator:aef2d3204a33ddffd2fe43c44d34fe097"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7adc0424baf7e4ef8da77fec6da8e1ea"><td class="memItemLeft" align="right" valign="top"><a id="a7adc0424baf7e4ef8da77fec6da8e1ea"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA19N_CCL_OUT0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aade9982add158f20548b2ce342abad88">PIN_PA19N_CCL_OUT0</a> << 16) | MUX_PA19N_CCL_OUT0)</td></tr>
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<tr class="separator:a7adc0424baf7e4ef8da77fec6da8e1ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a059be4d5b99991269f3eec489a68c9f9"><td class="memItemLeft" align="right" valign="top"><a id="a059be4d5b99991269f3eec489a68c9f9"></a>
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA19N_CCL_OUT0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 19)</td></tr>
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<tr class="separator:a059be4d5b99991269f3eec489a68c9f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab1ea2a0cc5b2d3742ca72b7d5abfcc26"><td class="memItemLeft" align="right" valign="top"><a id="ab1ea2a0cc5b2d3742ca72b7d5abfcc26"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab1ea2a0cc5b2d3742ca72b7d5abfcc26">PIN_PB02N_CCL_OUT0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(34)</td></tr>
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||
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<tr class="memdesc:ab1ea2a0cc5b2d3742ca72b7d5abfcc26"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: OUT0 on PB02 mux N. <br /></td></tr>
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<tr class="separator:ab1ea2a0cc5b2d3742ca72b7d5abfcc26"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a004ca85185c17fd65e7098f72209f845"><td class="memItemLeft" align="right" valign="top"><a id="a004ca85185c17fd65e7098f72209f845"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB02N_CCL_OUT0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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<tr class="separator:a004ca85185c17fd65e7098f72209f845"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac66775745b2e9d56820cd7cf0983add0"><td class="memItemLeft" align="right" valign="top"><a id="ac66775745b2e9d56820cd7cf0983add0"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB02N_CCL_OUT0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ab1ea2a0cc5b2d3742ca72b7d5abfcc26">PIN_PB02N_CCL_OUT0</a> << 16) | MUX_PB02N_CCL_OUT0)</td></tr>
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<tr class="separator:ac66775745b2e9d56820cd7cf0983add0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6699ceffea09ca86c19dc0444d9db56e"><td class="memItemLeft" align="right" valign="top"><a id="a6699ceffea09ca86c19dc0444d9db56e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB02N_CCL_OUT0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 2)</td></tr>
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<tr class="separator:a6699ceffea09ca86c19dc0444d9db56e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1662f35acda7be5a74ee3bcf48e649be"><td class="memItemLeft" align="right" valign="top"><a id="a1662f35acda7be5a74ee3bcf48e649be"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1662f35acda7be5a74ee3bcf48e649be">PIN_PB23N_CCL_OUT0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(55)</td></tr>
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||
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<tr class="memdesc:a1662f35acda7be5a74ee3bcf48e649be"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: OUT0 on PB23 mux N. <br /></td></tr>
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<tr class="separator:a1662f35acda7be5a74ee3bcf48e649be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3e798bd838f1bed66b796ba53eb495ac"><td class="memItemLeft" align="right" valign="top"><a id="a3e798bd838f1bed66b796ba53eb495ac"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB23N_CCL_OUT0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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<tr class="separator:a3e798bd838f1bed66b796ba53eb495ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa7e2f1f69bb73783db8ee2cd111c1bba"><td class="memItemLeft" align="right" valign="top"><a id="aa7e2f1f69bb73783db8ee2cd111c1bba"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB23N_CCL_OUT0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a1662f35acda7be5a74ee3bcf48e649be">PIN_PB23N_CCL_OUT0</a> << 16) | MUX_PB23N_CCL_OUT0)</td></tr>
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<tr class="separator:aa7e2f1f69bb73783db8ee2cd111c1bba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a89283ca615e6ad78f5e8c6d9bdbf186d"><td class="memItemLeft" align="right" valign="top"><a id="a89283ca615e6ad78f5e8c6d9bdbf186d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB23N_CCL_OUT0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 23)</td></tr>
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||
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<tr class="separator:a89283ca615e6ad78f5e8c6d9bdbf186d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a929038a135f9dc48781e4312cea2ae7f"><td class="memItemLeft" align="right" valign="top"><a id="a929038a135f9dc48781e4312cea2ae7f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a929038a135f9dc48781e4312cea2ae7f">PIN_PA11N_CCL_OUT1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
|
||
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<tr class="memdesc:a929038a135f9dc48781e4312cea2ae7f"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: OUT1 on PA11 mux N. <br /></td></tr>
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<tr class="separator:a929038a135f9dc48781e4312cea2ae7f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4aff463fa61b8e78606f2338f658e9ce"><td class="memItemLeft" align="right" valign="top"><a id="a4aff463fa61b8e78606f2338f658e9ce"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA11N_CCL_OUT1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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<tr class="separator:a4aff463fa61b8e78606f2338f658e9ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af7a482938708c076656a217e3d64fa8f"><td class="memItemLeft" align="right" valign="top"><a id="af7a482938708c076656a217e3d64fa8f"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA11N_CCL_OUT1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a929038a135f9dc48781e4312cea2ae7f">PIN_PA11N_CCL_OUT1</a> << 16) | MUX_PA11N_CCL_OUT1)</td></tr>
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<tr class="separator:af7a482938708c076656a217e3d64fa8f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a368b70625ef82829ec067e23a0e2ccf7"><td class="memItemLeft" align="right" valign="top"><a id="a368b70625ef82829ec067e23a0e2ccf7"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA11N_CCL_OUT1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 11)</td></tr>
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<tr class="separator:a368b70625ef82829ec067e23a0e2ccf7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aeccac5005432ac3417358e9102fcc097"><td class="memItemLeft" align="right" valign="top"><a id="aeccac5005432ac3417358e9102fcc097"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aeccac5005432ac3417358e9102fcc097">PIN_PA31N_CCL_OUT1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(31)</td></tr>
|
||
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<tr class="memdesc:aeccac5005432ac3417358e9102fcc097"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: OUT1 on PA31 mux N. <br /></td></tr>
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<tr class="separator:aeccac5005432ac3417358e9102fcc097"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1988510da7b1098fe7fbff045d9aa138"><td class="memItemLeft" align="right" valign="top"><a id="a1988510da7b1098fe7fbff045d9aa138"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA31N_CCL_OUT1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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<tr class="separator:a1988510da7b1098fe7fbff045d9aa138"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a10439601767df7cb0153727a12b25272"><td class="memItemLeft" align="right" valign="top"><a id="a10439601767df7cb0153727a12b25272"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA31N_CCL_OUT1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aeccac5005432ac3417358e9102fcc097">PIN_PA31N_CCL_OUT1</a> << 16) | MUX_PA31N_CCL_OUT1)</td></tr>
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<tr class="memitem:a94350d7cd4acfba99b20cbfee8f6e4a6"><td class="memItemLeft" align="right" valign="top"><a id="a94350d7cd4acfba99b20cbfee8f6e4a6"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA31N_CCL_OUT1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 31)</td></tr>
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<tr class="separator:a94350d7cd4acfba99b20cbfee8f6e4a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af660ed9079305934dd6792f8980c4445"><td class="memItemLeft" align="right" valign="top"><a id="af660ed9079305934dd6792f8980c4445"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af660ed9079305934dd6792f8980c4445">PIN_PB11N_CCL_OUT1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(43)</td></tr>
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<tr class="memdesc:af660ed9079305934dd6792f8980c4445"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: OUT1 on PB11 mux N. <br /></td></tr>
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<tr class="separator:af660ed9079305934dd6792f8980c4445"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:add67837421256de5e6aed483a0767704"><td class="memItemLeft" align="right" valign="top"><a id="add67837421256de5e6aed483a0767704"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB11N_CCL_OUT1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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<tr class="separator:add67837421256de5e6aed483a0767704"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad2a096d21bed21599ec846b32f6e1a4f"><td class="memItemLeft" align="right" valign="top"><a id="ad2a096d21bed21599ec846b32f6e1a4f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB11N_CCL_OUT1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#af660ed9079305934dd6792f8980c4445">PIN_PB11N_CCL_OUT1</a> << 16) | MUX_PB11N_CCL_OUT1)</td></tr>
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<tr class="separator:ad2a096d21bed21599ec846b32f6e1a4f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a641ed137155ef97574863e657d4171b1"><td class="memItemLeft" align="right" valign="top"><a id="a641ed137155ef97574863e657d4171b1"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB11N_CCL_OUT1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 11)</td></tr>
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<tr class="separator:a641ed137155ef97574863e657d4171b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3065540517f9d77ce9c1246641adee78"><td class="memItemLeft" align="right" valign="top"><a id="a3065540517f9d77ce9c1246641adee78"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3065540517f9d77ce9c1246641adee78">PIN_PA25N_CCL_OUT2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(25)</td></tr>
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<tr class="memdesc:a3065540517f9d77ce9c1246641adee78"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: OUT2 on PA25 mux N. <br /></td></tr>
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<tr class="separator:a3065540517f9d77ce9c1246641adee78"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aae6099fa783e68f150c2b108700f39c4"><td class="memItemLeft" align="right" valign="top"><a id="aae6099fa783e68f150c2b108700f39c4"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA25N_CCL_OUT2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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<tr class="separator:aae6099fa783e68f150c2b108700f39c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af1d04b1a1f9de6cc4cca599655656501"><td class="memItemLeft" align="right" valign="top"><a id="af1d04b1a1f9de6cc4cca599655656501"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA25N_CCL_OUT2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a3065540517f9d77ce9c1246641adee78">PIN_PA25N_CCL_OUT2</a> << 16) | MUX_PA25N_CCL_OUT2)</td></tr>
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<tr class="separator:af1d04b1a1f9de6cc4cca599655656501"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a99f788cd2d9c8765e9da71fa2c40ee72"><td class="memItemLeft" align="right" valign="top"><a id="a99f788cd2d9c8765e9da71fa2c40ee72"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA25N_CCL_OUT2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 25)</td></tr>
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<tr class="separator:a99f788cd2d9c8765e9da71fa2c40ee72"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adc546271aa4df02baa2d6c6ebf21a469"><td class="memItemLeft" align="right" valign="top"><a id="adc546271aa4df02baa2d6c6ebf21a469"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#adc546271aa4df02baa2d6c6ebf21a469">PIN_PB09N_CCL_OUT2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(41)</td></tr>
|
||
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<tr class="memdesc:adc546271aa4df02baa2d6c6ebf21a469"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: OUT2 on PB09 mux N. <br /></td></tr>
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<tr class="separator:adc546271aa4df02baa2d6c6ebf21a469"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acf38ec79cc600dbe768b4bc8ac0a3de5"><td class="memItemLeft" align="right" valign="top"><a id="acf38ec79cc600dbe768b4bc8ac0a3de5"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB09N_CCL_OUT2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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<tr class="separator:acf38ec79cc600dbe768b4bc8ac0a3de5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a026ff46738d9eeee2dfbf415f2a08ca0"><td class="memItemLeft" align="right" valign="top"><a id="a026ff46738d9eeee2dfbf415f2a08ca0"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB09N_CCL_OUT2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#adc546271aa4df02baa2d6c6ebf21a469">PIN_PB09N_CCL_OUT2</a> << 16) | MUX_PB09N_CCL_OUT2)</td></tr>
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<tr class="separator:a026ff46738d9eeee2dfbf415f2a08ca0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afe69f3f0ba60da11e26956d31103d309"><td class="memItemLeft" align="right" valign="top"><a id="afe69f3f0ba60da11e26956d31103d309"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB09N_CCL_OUT2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 9)</td></tr>
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<tr class="separator:afe69f3f0ba60da11e26956d31103d309"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5d7e30b30f819cffa135a1577ff524b8"><td class="memItemLeft" align="right" valign="top"><a id="a5d7e30b30f819cffa135a1577ff524b8"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5d7e30b30f819cffa135a1577ff524b8">PIN_PB17N_CCL_OUT3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(49)</td></tr>
|
||
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<tr class="memdesc:a5d7e30b30f819cffa135a1577ff524b8"><td class="mdescLeft"> </td><td class="mdescRight">CCL signal: OUT3 on PB17 mux N. <br /></td></tr>
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<tr class="separator:a5d7e30b30f819cffa135a1577ff524b8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a47a69f49589106c6beabb1d33528caa9"><td class="memItemLeft" align="right" valign="top"><a id="a47a69f49589106c6beabb1d33528caa9"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB17N_CCL_OUT3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
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<tr class="separator:a47a69f49589106c6beabb1d33528caa9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae711f718bb1c47c5db4d6779b6bd1cfc"><td class="memItemLeft" align="right" valign="top"><a id="ae711f718bb1c47c5db4d6779b6bd1cfc"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB17N_CCL_OUT3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a5d7e30b30f819cffa135a1577ff524b8">PIN_PB17N_CCL_OUT3</a> << 16) | MUX_PB17N_CCL_OUT3)</td></tr>
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<tr class="separator:ae711f718bb1c47c5db4d6779b6bd1cfc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3b31bb0bfbd0e05202fdd44b97646c60"><td class="memItemLeft" align="right" valign="top"><a id="a3b31bb0bfbd0e05202fdd44b97646c60"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB17N_CCL_OUT3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 17)</td></tr>
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<tr class="separator:a3b31bb0bfbd0e05202fdd44b97646c60"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac17fd817a95b4a91465d6ca092c56c70"><td class="memItemLeft" align="right" valign="top"><a id="ac17fd817a95b4a91465d6ca092c56c70"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac17fd817a95b4a91465d6ca092c56c70">PIN_PA13D_SERCOM4_PAD0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
|
||
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<tr class="memdesc:ac17fd817a95b4a91465d6ca092c56c70"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM4 signal: PAD0 on PA13 mux D. <br /></td></tr>
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<tr class="separator:ac17fd817a95b4a91465d6ca092c56c70"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af0a326bb26ae760e135808e263a1615e"><td class="memItemLeft" align="right" valign="top"><a id="af0a326bb26ae760e135808e263a1615e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA13D_SERCOM4_PAD0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="separator:af0a326bb26ae760e135808e263a1615e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adff5e6f55683a2aafa1d80c85e2f51b3"><td class="memItemLeft" align="right" valign="top"><a id="adff5e6f55683a2aafa1d80c85e2f51b3"></a>
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA13D_SERCOM4_PAD0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ac17fd817a95b4a91465d6ca092c56c70">PIN_PA13D_SERCOM4_PAD0</a> << 16) | MUX_PA13D_SERCOM4_PAD0)</td></tr>
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<tr class="separator:adff5e6f55683a2aafa1d80c85e2f51b3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a14a3093749d3c24f22e4afc62baa2fcc"><td class="memItemLeft" align="right" valign="top"><a id="a14a3093749d3c24f22e4afc62baa2fcc"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA13D_SERCOM4_PAD0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 13)</td></tr>
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||
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<tr class="separator:a14a3093749d3c24f22e4afc62baa2fcc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a00d36c9207483de0ce5012e4cacf2c61"><td class="memItemLeft" align="right" valign="top"><a id="a00d36c9207483de0ce5012e4cacf2c61"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a00d36c9207483de0ce5012e4cacf2c61">PIN_PB08D_SERCOM4_PAD0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(40)</td></tr>
|
||
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<tr class="memdesc:a00d36c9207483de0ce5012e4cacf2c61"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM4 signal: PAD0 on PB08 mux D. <br /></td></tr>
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<tr class="separator:a00d36c9207483de0ce5012e4cacf2c61"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aba973e8ed3dad33e55c2bce24f3e6aef"><td class="memItemLeft" align="right" valign="top"><a id="aba973e8ed3dad33e55c2bce24f3e6aef"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB08D_SERCOM4_PAD0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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||
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<tr class="separator:aba973e8ed3dad33e55c2bce24f3e6aef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a81d7f6a3bbb876480a5fcbc369019a8e"><td class="memItemLeft" align="right" valign="top"><a id="a81d7f6a3bbb876480a5fcbc369019a8e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB08D_SERCOM4_PAD0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a00d36c9207483de0ce5012e4cacf2c61">PIN_PB08D_SERCOM4_PAD0</a> << 16) | MUX_PB08D_SERCOM4_PAD0)</td></tr>
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<tr class="separator:a81d7f6a3bbb876480a5fcbc369019a8e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6246524113827282ee0dbb4d128e6ddf"><td class="memItemLeft" align="right" valign="top"><a id="a6246524113827282ee0dbb4d128e6ddf"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB08D_SERCOM4_PAD0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 8)</td></tr>
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||
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<tr class="separator:a6246524113827282ee0dbb4d128e6ddf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3943d5aae1022310555f13af84222558"><td class="memItemLeft" align="right" valign="top"><a id="a3943d5aae1022310555f13af84222558"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3943d5aae1022310555f13af84222558">PIN_PB12C_SERCOM4_PAD0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(44)</td></tr>
|
||
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<tr class="memdesc:a3943d5aae1022310555f13af84222558"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM4 signal: PAD0 on PB12 mux C. <br /></td></tr>
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||
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<tr class="separator:a3943d5aae1022310555f13af84222558"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a43ac93191fd3e8037c7be20e3d261ec1"><td class="memItemLeft" align="right" valign="top"><a id="a43ac93191fd3e8037c7be20e3d261ec1"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB12C_SERCOM4_PAD0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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||
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<tr class="separator:a43ac93191fd3e8037c7be20e3d261ec1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9d189ddf3a65a9ce8806f271b64ff0cd"><td class="memItemLeft" align="right" valign="top"><a id="a9d189ddf3a65a9ce8806f271b64ff0cd"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB12C_SERCOM4_PAD0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a3943d5aae1022310555f13af84222558">PIN_PB12C_SERCOM4_PAD0</a> << 16) | MUX_PB12C_SERCOM4_PAD0)</td></tr>
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<tr class="separator:a9d189ddf3a65a9ce8806f271b64ff0cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a02d9c0963ef890e007ee16663db74034"><td class="memItemLeft" align="right" valign="top"><a id="a02d9c0963ef890e007ee16663db74034"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB12C_SERCOM4_PAD0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 12)</td></tr>
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<tr class="separator:a02d9c0963ef890e007ee16663db74034"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a191299504058ede84452ce4eebb11fa7"><td class="memItemLeft" align="right" valign="top"><a id="a191299504058ede84452ce4eebb11fa7"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a191299504058ede84452ce4eebb11fa7">PIN_PA12D_SERCOM4_PAD1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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<tr class="memdesc:a191299504058ede84452ce4eebb11fa7"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM4 signal: PAD1 on PA12 mux D. <br /></td></tr>
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<tr class="separator:a191299504058ede84452ce4eebb11fa7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:add5098b6d8c4c388f1d4133fab6177b5"><td class="memItemLeft" align="right" valign="top"><a id="add5098b6d8c4c388f1d4133fab6177b5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA12D_SERCOM4_PAD1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="separator:add5098b6d8c4c388f1d4133fab6177b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af7dc6f2d932bab81f8ad572737e54674"><td class="memItemLeft" align="right" valign="top"><a id="af7dc6f2d932bab81f8ad572737e54674"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA12D_SERCOM4_PAD1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a191299504058ede84452ce4eebb11fa7">PIN_PA12D_SERCOM4_PAD1</a> << 16) | MUX_PA12D_SERCOM4_PAD1)</td></tr>
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<tr class="separator:af7dc6f2d932bab81f8ad572737e54674"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa5358024ca069606857e32e692c3ee95"><td class="memItemLeft" align="right" valign="top"><a id="aa5358024ca069606857e32e692c3ee95"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA12D_SERCOM4_PAD1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 12)</td></tr>
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<tr class="separator:aa5358024ca069606857e32e692c3ee95"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a731ba4400fdcde718248eb560959d4b9"><td class="memItemLeft" align="right" valign="top"><a id="a731ba4400fdcde718248eb560959d4b9"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a731ba4400fdcde718248eb560959d4b9">PIN_PB09D_SERCOM4_PAD1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(41)</td></tr>
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||
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<tr class="memdesc:a731ba4400fdcde718248eb560959d4b9"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM4 signal: PAD1 on PB09 mux D. <br /></td></tr>
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<tr class="separator:a731ba4400fdcde718248eb560959d4b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aedde5e43092e3885721f10c201171588"><td class="memItemLeft" align="right" valign="top"><a id="aedde5e43092e3885721f10c201171588"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB09D_SERCOM4_PAD1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="separator:aedde5e43092e3885721f10c201171588"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aacee0dd5c58a1e999c4a73119ce6d465"><td class="memItemLeft" align="right" valign="top"><a id="aacee0dd5c58a1e999c4a73119ce6d465"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB09D_SERCOM4_PAD1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a731ba4400fdcde718248eb560959d4b9">PIN_PB09D_SERCOM4_PAD1</a> << 16) | MUX_PB09D_SERCOM4_PAD1)</td></tr>
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<tr class="separator:aacee0dd5c58a1e999c4a73119ce6d465"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0212a41abb931ad8ec604d567ea63595"><td class="memItemLeft" align="right" valign="top"><a id="a0212a41abb931ad8ec604d567ea63595"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB09D_SERCOM4_PAD1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 9)</td></tr>
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<tr class="separator:a0212a41abb931ad8ec604d567ea63595"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2587d8ece4ca92375cef72a5d46621ef"><td class="memItemLeft" align="right" valign="top"><a id="a2587d8ece4ca92375cef72a5d46621ef"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2587d8ece4ca92375cef72a5d46621ef">PIN_PB13C_SERCOM4_PAD1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(45)</td></tr>
|
||
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<tr class="memdesc:a2587d8ece4ca92375cef72a5d46621ef"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM4 signal: PAD1 on PB13 mux C. <br /></td></tr>
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<tr class="separator:a2587d8ece4ca92375cef72a5d46621ef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3a25dae02df5cdc7c16a33bf076d24f2"><td class="memItemLeft" align="right" valign="top"><a id="a3a25dae02df5cdc7c16a33bf076d24f2"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB13C_SERCOM4_PAD1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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<tr class="separator:a3a25dae02df5cdc7c16a33bf076d24f2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa2da90ad4d270e094e4787d0038258df"><td class="memItemLeft" align="right" valign="top"><a id="aa2da90ad4d270e094e4787d0038258df"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB13C_SERCOM4_PAD1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a2587d8ece4ca92375cef72a5d46621ef">PIN_PB13C_SERCOM4_PAD1</a> << 16) | MUX_PB13C_SERCOM4_PAD1)</td></tr>
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<tr class="separator:aa2da90ad4d270e094e4787d0038258df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0c06cc44afa910d09ec0158dfaea68c6"><td class="memItemLeft" align="right" valign="top"><a id="a0c06cc44afa910d09ec0158dfaea68c6"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB13C_SERCOM4_PAD1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 13)</td></tr>
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||
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<tr class="separator:a0c06cc44afa910d09ec0158dfaea68c6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1ceb3030544fbf98f84a5941172cb9a8"><td class="memItemLeft" align="right" valign="top"><a id="a1ceb3030544fbf98f84a5941172cb9a8"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1ceb3030544fbf98f84a5941172cb9a8">PIN_PA14D_SERCOM4_PAD2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
|
||
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<tr class="memdesc:a1ceb3030544fbf98f84a5941172cb9a8"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM4 signal: PAD2 on PA14 mux D. <br /></td></tr>
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<tr class="separator:a1ceb3030544fbf98f84a5941172cb9a8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4220e5a1fba40364f62d9fe776a64be1"><td class="memItemLeft" align="right" valign="top"><a id="a4220e5a1fba40364f62d9fe776a64be1"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA14D_SERCOM4_PAD2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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||
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<tr class="separator:a4220e5a1fba40364f62d9fe776a64be1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab53a04f9fca6e5f8875d2c89708f3cac"><td class="memItemLeft" align="right" valign="top"><a id="ab53a04f9fca6e5f8875d2c89708f3cac"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA14D_SERCOM4_PAD2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a1ceb3030544fbf98f84a5941172cb9a8">PIN_PA14D_SERCOM4_PAD2</a> << 16) | MUX_PA14D_SERCOM4_PAD2)</td></tr>
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<tr class="separator:ab53a04f9fca6e5f8875d2c89708f3cac"><td class="memSeparator" colspan="2"> </td></tr>
|
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<tr class="memitem:a25c4cd7f43209f7cb30adad2dbf9db25"><td class="memItemLeft" align="right" valign="top"><a id="a25c4cd7f43209f7cb30adad2dbf9db25"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA14D_SERCOM4_PAD2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 14)</td></tr>
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||
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<tr class="separator:a25c4cd7f43209f7cb30adad2dbf9db25"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abef8943e52365d8a67b831f23e66a7e5"><td class="memItemLeft" align="right" valign="top"><a id="abef8943e52365d8a67b831f23e66a7e5"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#abef8943e52365d8a67b831f23e66a7e5">PIN_PB10D_SERCOM4_PAD2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(42)</td></tr>
|
||
|
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<tr class="memdesc:abef8943e52365d8a67b831f23e66a7e5"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM4 signal: PAD2 on PB10 mux D. <br /></td></tr>
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||
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<tr class="separator:abef8943e52365d8a67b831f23e66a7e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad43dc9547fb380e2efb9380a8e73e5cf"><td class="memItemLeft" align="right" valign="top"><a id="ad43dc9547fb380e2efb9380a8e73e5cf"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB10D_SERCOM4_PAD2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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||
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<tr class="separator:ad43dc9547fb380e2efb9380a8e73e5cf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a53d5142f66d9424585852a343ed0b204"><td class="memItemLeft" align="right" valign="top"><a id="a53d5142f66d9424585852a343ed0b204"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB10D_SERCOM4_PAD2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#abef8943e52365d8a67b831f23e66a7e5">PIN_PB10D_SERCOM4_PAD2</a> << 16) | MUX_PB10D_SERCOM4_PAD2)</td></tr>
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<tr class="separator:a53d5142f66d9424585852a343ed0b204"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5220fc0f005cd9b7eff354d60d432730"><td class="memItemLeft" align="right" valign="top"><a id="a5220fc0f005cd9b7eff354d60d432730"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB10D_SERCOM4_PAD2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 10)</td></tr>
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||
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<tr class="separator:a5220fc0f005cd9b7eff354d60d432730"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab22cc54f3de871416b0aa14707f24d63"><td class="memItemLeft" align="right" valign="top"><a id="ab22cc54f3de871416b0aa14707f24d63"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab22cc54f3de871416b0aa14707f24d63">PIN_PB14C_SERCOM4_PAD2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(46)</td></tr>
|
||
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<tr class="memdesc:ab22cc54f3de871416b0aa14707f24d63"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM4 signal: PAD2 on PB14 mux C. <br /></td></tr>
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<tr class="separator:ab22cc54f3de871416b0aa14707f24d63"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5ed53922979090e949110d48d89f0de6"><td class="memItemLeft" align="right" valign="top"><a id="a5ed53922979090e949110d48d89f0de6"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB14C_SERCOM4_PAD2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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||
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<tr class="separator:a5ed53922979090e949110d48d89f0de6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac6fbf29e2a4d6c600a1aa8b2e87c366f"><td class="memItemLeft" align="right" valign="top"><a id="ac6fbf29e2a4d6c600a1aa8b2e87c366f"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB14C_SERCOM4_PAD2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ab22cc54f3de871416b0aa14707f24d63">PIN_PB14C_SERCOM4_PAD2</a> << 16) | MUX_PB14C_SERCOM4_PAD2)</td></tr>
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<tr class="separator:ac6fbf29e2a4d6c600a1aa8b2e87c366f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af22e013686b51e0e9ddf15d4ffc4522f"><td class="memItemLeft" align="right" valign="top"><a id="af22e013686b51e0e9ddf15d4ffc4522f"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB14C_SERCOM4_PAD2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 14)</td></tr>
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||
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<tr class="separator:af22e013686b51e0e9ddf15d4ffc4522f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aaeffcbb860a8c25bd2675e6a726bb74e"><td class="memItemLeft" align="right" valign="top"><a id="aaeffcbb860a8c25bd2675e6a726bb74e"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aaeffcbb860a8c25bd2675e6a726bb74e">PIN_PB11D_SERCOM4_PAD3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(43)</td></tr>
|
||
|
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<tr class="memdesc:aaeffcbb860a8c25bd2675e6a726bb74e"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM4 signal: PAD3 on PB11 mux D. <br /></td></tr>
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<tr class="separator:aaeffcbb860a8c25bd2675e6a726bb74e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:addb957112cd412ed42d844689758240b"><td class="memItemLeft" align="right" valign="top"><a id="addb957112cd412ed42d844689758240b"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB11D_SERCOM4_PAD3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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||
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<tr class="separator:addb957112cd412ed42d844689758240b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a944d81810295acdef84b694e06282dde"><td class="memItemLeft" align="right" valign="top"><a id="a944d81810295acdef84b694e06282dde"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB11D_SERCOM4_PAD3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aaeffcbb860a8c25bd2675e6a726bb74e">PIN_PB11D_SERCOM4_PAD3</a> << 16) | MUX_PB11D_SERCOM4_PAD3)</td></tr>
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<tr class="separator:a944d81810295acdef84b694e06282dde"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab596f550bbf3d2de454d2f66c8e8eaa1"><td class="memItemLeft" align="right" valign="top"><a id="ab596f550bbf3d2de454d2f66c8e8eaa1"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB11D_SERCOM4_PAD3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 11)</td></tr>
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<tr class="separator:ab596f550bbf3d2de454d2f66c8e8eaa1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af75797a9c76ee2bc7584bf135abd3e89"><td class="memItemLeft" align="right" valign="top"><a id="af75797a9c76ee2bc7584bf135abd3e89"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af75797a9c76ee2bc7584bf135abd3e89">PIN_PA15D_SERCOM4_PAD3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(15)</td></tr>
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<tr class="memdesc:af75797a9c76ee2bc7584bf135abd3e89"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM4 signal: PAD3 on PA15 mux D. <br /></td></tr>
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<tr class="memitem:a35bcf8dbbe36952b34b4d7ab15254bb0"><td class="memItemLeft" align="right" valign="top"><a id="a35bcf8dbbe36952b34b4d7ab15254bb0"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA15D_SERCOM4_PAD3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="separator:a35bcf8dbbe36952b34b4d7ab15254bb0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afd13c9c09cddd46c952baaef0bfef47d"><td class="memItemLeft" align="right" valign="top"><a id="afd13c9c09cddd46c952baaef0bfef47d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA15D_SERCOM4_PAD3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#af75797a9c76ee2bc7584bf135abd3e89">PIN_PA15D_SERCOM4_PAD3</a> << 16) | MUX_PA15D_SERCOM4_PAD3)</td></tr>
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<tr class="separator:afd13c9c09cddd46c952baaef0bfef47d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a352ff8e51d1992b7c00ab62031f23d4e"><td class="memItemLeft" align="right" valign="top"><a id="a352ff8e51d1992b7c00ab62031f23d4e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA15D_SERCOM4_PAD3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 15)</td></tr>
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<tr class="separator:a352ff8e51d1992b7c00ab62031f23d4e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae419108a03b25c2afae73f0f9997f5be"><td class="memItemLeft" align="right" valign="top"><a id="ae419108a03b25c2afae73f0f9997f5be"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae419108a03b25c2afae73f0f9997f5be">PIN_PB15C_SERCOM4_PAD3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(47)</td></tr>
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||
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<tr class="memdesc:ae419108a03b25c2afae73f0f9997f5be"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM4 signal: PAD3 on PB15 mux C. <br /></td></tr>
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<tr class="separator:ae419108a03b25c2afae73f0f9997f5be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a907448047f1c3340bbad930174a77fae"><td class="memItemLeft" align="right" valign="top"><a id="a907448047f1c3340bbad930174a77fae"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB15C_SERCOM4_PAD3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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<tr class="separator:a907448047f1c3340bbad930174a77fae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a09cc848aed48ebbcc6d6402d9f0034b1"><td class="memItemLeft" align="right" valign="top"><a id="a09cc848aed48ebbcc6d6402d9f0034b1"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB15C_SERCOM4_PAD3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ae419108a03b25c2afae73f0f9997f5be">PIN_PB15C_SERCOM4_PAD3</a> << 16) | MUX_PB15C_SERCOM4_PAD3)</td></tr>
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<tr class="separator:a09cc848aed48ebbcc6d6402d9f0034b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afe04f5cfac0fdd0835db7e9f385e094c"><td class="memItemLeft" align="right" valign="top"><a id="afe04f5cfac0fdd0835db7e9f385e094c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB15C_SERCOM4_PAD3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 15)</td></tr>
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<tr class="separator:afe04f5cfac0fdd0835db7e9f385e094c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6a66aa24e1c1ce5389755efda32fa6d6"><td class="memItemLeft" align="right" valign="top"><a id="a6a66aa24e1c1ce5389755efda32fa6d6"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6a66aa24e1c1ce5389755efda32fa6d6">PIN_PA23D_SERCOM5_PAD0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(23)</td></tr>
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||
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<tr class="memdesc:a6a66aa24e1c1ce5389755efda32fa6d6"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM5 signal: PAD0 on PA23 mux D. <br /></td></tr>
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<tr class="separator:a6a66aa24e1c1ce5389755efda32fa6d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9149a6f2a82fa9b8bed8d66abf456025"><td class="memItemLeft" align="right" valign="top"><a id="a9149a6f2a82fa9b8bed8d66abf456025"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA23D_SERCOM5_PAD0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="separator:a9149a6f2a82fa9b8bed8d66abf456025"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a11936f6e83243d1bb0468ca9a0c8a2d4"><td class="memItemLeft" align="right" valign="top"><a id="a11936f6e83243d1bb0468ca9a0c8a2d4"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA23D_SERCOM5_PAD0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a6a66aa24e1c1ce5389755efda32fa6d6">PIN_PA23D_SERCOM5_PAD0</a> << 16) | MUX_PA23D_SERCOM5_PAD0)</td></tr>
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<tr class="separator:a11936f6e83243d1bb0468ca9a0c8a2d4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a54be72b19b1221d9aa6625abfc69f451"><td class="memItemLeft" align="right" valign="top"><a id="a54be72b19b1221d9aa6625abfc69f451"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA23D_SERCOM5_PAD0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 23)</td></tr>
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<tr class="separator:a54be72b19b1221d9aa6625abfc69f451"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af69d1d9d5528bdd41985a4d50557bbca"><td class="memItemLeft" align="right" valign="top"><a id="af69d1d9d5528bdd41985a4d50557bbca"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af69d1d9d5528bdd41985a4d50557bbca">PIN_PB02D_SERCOM5_PAD0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(34)</td></tr>
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||
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<tr class="memdesc:af69d1d9d5528bdd41985a4d50557bbca"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM5 signal: PAD0 on PB02 mux D. <br /></td></tr>
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<tr class="separator:af69d1d9d5528bdd41985a4d50557bbca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adee65190dbf27de604220e5316aa589c"><td class="memItemLeft" align="right" valign="top"><a id="adee65190dbf27de604220e5316aa589c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB02D_SERCOM5_PAD0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="separator:adee65190dbf27de604220e5316aa589c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acb86784f9ba0b2892be7619033c3ccd0"><td class="memItemLeft" align="right" valign="top"><a id="acb86784f9ba0b2892be7619033c3ccd0"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB02D_SERCOM5_PAD0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#af69d1d9d5528bdd41985a4d50557bbca">PIN_PB02D_SERCOM5_PAD0</a> << 16) | MUX_PB02D_SERCOM5_PAD0)</td></tr>
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<tr class="separator:acb86784f9ba0b2892be7619033c3ccd0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac9ea6a47b32e086ba4b9aac6436b7859"><td class="memItemLeft" align="right" valign="top"><a id="ac9ea6a47b32e086ba4b9aac6436b7859"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB02D_SERCOM5_PAD0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 2)</td></tr>
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||
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<tr class="separator:ac9ea6a47b32e086ba4b9aac6436b7859"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a89bd93933c5de9c9838a9826b87aa904"><td class="memItemLeft" align="right" valign="top"><a id="a89bd93933c5de9c9838a9826b87aa904"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a89bd93933c5de9c9838a9826b87aa904">PIN_PB31D_SERCOM5_PAD0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(63)</td></tr>
|
||
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<tr class="memdesc:a89bd93933c5de9c9838a9826b87aa904"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM5 signal: PAD0 on PB31 mux D. <br /></td></tr>
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<tr class="separator:a89bd93933c5de9c9838a9826b87aa904"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa45ad8ea6df5f39699cf4f3745174a2f"><td class="memItemLeft" align="right" valign="top"><a id="aa45ad8ea6df5f39699cf4f3745174a2f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB31D_SERCOM5_PAD0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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||
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<tr class="separator:aa45ad8ea6df5f39699cf4f3745174a2f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aea3c168da9672e43c8b87973ee6e7b23"><td class="memItemLeft" align="right" valign="top"><a id="aea3c168da9672e43c8b87973ee6e7b23"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB31D_SERCOM5_PAD0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a89bd93933c5de9c9838a9826b87aa904">PIN_PB31D_SERCOM5_PAD0</a> << 16) | MUX_PB31D_SERCOM5_PAD0)</td></tr>
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<tr class="separator:aea3c168da9672e43c8b87973ee6e7b23"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad6eca80db43e8376586475b4e6cb19f6"><td class="memItemLeft" align="right" valign="top"><a id="ad6eca80db43e8376586475b4e6cb19f6"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB31D_SERCOM5_PAD0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 31)</td></tr>
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<tr class="separator:ad6eca80db43e8376586475b4e6cb19f6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8e6af1b0167518136dcd1048721e4b6a"><td class="memItemLeft" align="right" valign="top"><a id="a8e6af1b0167518136dcd1048721e4b6a"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8e6af1b0167518136dcd1048721e4b6a">PIN_PB16C_SERCOM5_PAD0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(48)</td></tr>
|
||
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<tr class="memdesc:a8e6af1b0167518136dcd1048721e4b6a"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM5 signal: PAD0 on PB16 mux C. <br /></td></tr>
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<tr class="separator:a8e6af1b0167518136dcd1048721e4b6a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a65001ca304731147303bd2f249ac5f1d"><td class="memItemLeft" align="right" valign="top"><a id="a65001ca304731147303bd2f249ac5f1d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB16C_SERCOM5_PAD0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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<tr class="separator:a65001ca304731147303bd2f249ac5f1d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aeae967081710a10f32df07c0c02b3d7b"><td class="memItemLeft" align="right" valign="top"><a id="aeae967081710a10f32df07c0c02b3d7b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB16C_SERCOM5_PAD0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a8e6af1b0167518136dcd1048721e4b6a">PIN_PB16C_SERCOM5_PAD0</a> << 16) | MUX_PB16C_SERCOM5_PAD0)</td></tr>
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<tr class="separator:aeae967081710a10f32df07c0c02b3d7b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7493799e2707daeca2007f9088e4a78f"><td class="memItemLeft" align="right" valign="top"><a id="a7493799e2707daeca2007f9088e4a78f"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB16C_SERCOM5_PAD0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 16)</td></tr>
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<tr class="separator:a7493799e2707daeca2007f9088e4a78f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a36cf7aac3bab2634d92473bf3ca624e0"><td class="memItemLeft" align="right" valign="top"><a id="a36cf7aac3bab2634d92473bf3ca624e0"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a36cf7aac3bab2634d92473bf3ca624e0">PIN_PA22D_SERCOM5_PAD1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(22)</td></tr>
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||
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<tr class="memdesc:a36cf7aac3bab2634d92473bf3ca624e0"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM5 signal: PAD1 on PA22 mux D. <br /></td></tr>
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<tr class="separator:a36cf7aac3bab2634d92473bf3ca624e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a962ec2767fc68e963f716a489eb706e9"><td class="memItemLeft" align="right" valign="top"><a id="a962ec2767fc68e963f716a489eb706e9"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA22D_SERCOM5_PAD1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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||
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<tr class="separator:a962ec2767fc68e963f716a489eb706e9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a96fe57a857e75d4a6ccd8b4263403d9c"><td class="memItemLeft" align="right" valign="top"><a id="a96fe57a857e75d4a6ccd8b4263403d9c"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA22D_SERCOM5_PAD1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a36cf7aac3bab2634d92473bf3ca624e0">PIN_PA22D_SERCOM5_PAD1</a> << 16) | MUX_PA22D_SERCOM5_PAD1)</td></tr>
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<tr class="separator:a96fe57a857e75d4a6ccd8b4263403d9c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a28854a808d27a694404421decbfe6a9f"><td class="memItemLeft" align="right" valign="top"><a id="a28854a808d27a694404421decbfe6a9f"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA22D_SERCOM5_PAD1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 22)</td></tr>
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||
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<tr class="separator:a28854a808d27a694404421decbfe6a9f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac737d7b2418abd8d9f66e0a5bb32c86e"><td class="memItemLeft" align="right" valign="top"><a id="ac737d7b2418abd8d9f66e0a5bb32c86e"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac737d7b2418abd8d9f66e0a5bb32c86e">PIN_PB03D_SERCOM5_PAD1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(35)</td></tr>
|
||
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<tr class="memdesc:ac737d7b2418abd8d9f66e0a5bb32c86e"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM5 signal: PAD1 on PB03 mux D. <br /></td></tr>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB03D_SERCOM5_PAD1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="memitem:a095f1791d4906a03088b579bda062a79"><td class="memItemLeft" align="right" valign="top"><a id="a095f1791d4906a03088b579bda062a79"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB03D_SERCOM5_PAD1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ac737d7b2418abd8d9f66e0a5bb32c86e">PIN_PB03D_SERCOM5_PAD1</a> << 16) | MUX_PB03D_SERCOM5_PAD1)</td></tr>
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<tr class="memitem:a5570240b5f1baa24354e3d3fa49d8f36"><td class="memItemLeft" align="right" valign="top"><a id="a5570240b5f1baa24354e3d3fa49d8f36"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB03D_SERCOM5_PAD1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 3)</td></tr>
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<tr class="memitem:a0c40598a613b940aad3079642c102a46"><td class="memItemLeft" align="right" valign="top"><a id="a0c40598a613b940aad3079642c102a46"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0c40598a613b940aad3079642c102a46">PIN_PB30D_SERCOM5_PAD1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(62)</td></tr>
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<tr class="memdesc:a0c40598a613b940aad3079642c102a46"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM5 signal: PAD1 on PB30 mux D. <br /></td></tr>
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<tr class="memitem:a232940bbad8eb189a3faf69a724ec736"><td class="memItemLeft" align="right" valign="top"><a id="a232940bbad8eb189a3faf69a724ec736"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB30D_SERCOM5_PAD1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="memitem:a40b622ed65a74b510330b550b4197833"><td class="memItemLeft" align="right" valign="top"><a id="a40b622ed65a74b510330b550b4197833"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB30D_SERCOM5_PAD1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a0c40598a613b940aad3079642c102a46">PIN_PB30D_SERCOM5_PAD1</a> << 16) | MUX_PB30D_SERCOM5_PAD1)</td></tr>
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<tr class="memitem:a3008cc7380ffc728c4e03c2e9820f43c"><td class="memItemLeft" align="right" valign="top"><a id="a3008cc7380ffc728c4e03c2e9820f43c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB30D_SERCOM5_PAD1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 30)</td></tr>
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<tr class="separator:a3008cc7380ffc728c4e03c2e9820f43c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac57849d68459dbd1da81ab7ea173df27"><td class="memItemLeft" align="right" valign="top"><a id="ac57849d68459dbd1da81ab7ea173df27"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac57849d68459dbd1da81ab7ea173df27">PIN_PB17C_SERCOM5_PAD1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(49)</td></tr>
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<tr class="memdesc:ac57849d68459dbd1da81ab7ea173df27"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM5 signal: PAD1 on PB17 mux C. <br /></td></tr>
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<tr class="separator:ac57849d68459dbd1da81ab7ea173df27"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6e52a38cbecc4ab8164312e7ed085dd3"><td class="memItemLeft" align="right" valign="top"><a id="a6e52a38cbecc4ab8164312e7ed085dd3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB17C_SERCOM5_PAD1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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<tr class="separator:a6e52a38cbecc4ab8164312e7ed085dd3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a52d21c6ab3b1e29a665171528f5fd287"><td class="memItemLeft" align="right" valign="top"><a id="a52d21c6ab3b1e29a665171528f5fd287"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB17C_SERCOM5_PAD1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ac57849d68459dbd1da81ab7ea173df27">PIN_PB17C_SERCOM5_PAD1</a> << 16) | MUX_PB17C_SERCOM5_PAD1)</td></tr>
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<tr class="separator:a52d21c6ab3b1e29a665171528f5fd287"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a45050f43910c30b95364f915fe4910c6"><td class="memItemLeft" align="right" valign="top"><a id="a45050f43910c30b95364f915fe4910c6"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB17C_SERCOM5_PAD1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 17)</td></tr>
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<tr class="separator:a45050f43910c30b95364f915fe4910c6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9b038b75caa4528984846d96e597f3ad"><td class="memItemLeft" align="right" valign="top"><a id="a9b038b75caa4528984846d96e597f3ad"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a9b038b75caa4528984846d96e597f3ad">PIN_PA24D_SERCOM5_PAD2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(24)</td></tr>
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<tr class="memdesc:a9b038b75caa4528984846d96e597f3ad"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM5 signal: PAD2 on PA24 mux D. <br /></td></tr>
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<tr class="separator:a9b038b75caa4528984846d96e597f3ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a781674be2d836ed7b5c21d558f395487"><td class="memItemLeft" align="right" valign="top"><a id="a781674be2d836ed7b5c21d558f395487"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA24D_SERCOM5_PAD2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="separator:a781674be2d836ed7b5c21d558f395487"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a56a1d57a7a6c002b8933f2ca1e357dbd"><td class="memItemLeft" align="right" valign="top"><a id="a56a1d57a7a6c002b8933f2ca1e357dbd"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA24D_SERCOM5_PAD2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a9b038b75caa4528984846d96e597f3ad">PIN_PA24D_SERCOM5_PAD2</a> << 16) | MUX_PA24D_SERCOM5_PAD2)</td></tr>
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<tr class="separator:a56a1d57a7a6c002b8933f2ca1e357dbd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0de20b2358e171e3ccaa8a7ee10fcc70"><td class="memItemLeft" align="right" valign="top"><a id="a0de20b2358e171e3ccaa8a7ee10fcc70"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA24D_SERCOM5_PAD2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 24)</td></tr>
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<tr class="separator:a0de20b2358e171e3ccaa8a7ee10fcc70"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a18549908e5cbd012a1e2f5fd05bd6eb8"><td class="memItemLeft" align="right" valign="top"><a id="a18549908e5cbd012a1e2f5fd05bd6eb8"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a18549908e5cbd012a1e2f5fd05bd6eb8">PIN_PB00D_SERCOM5_PAD2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(32)</td></tr>
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<tr class="memdesc:a18549908e5cbd012a1e2f5fd05bd6eb8"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM5 signal: PAD2 on PB00 mux D. <br /></td></tr>
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<tr class="separator:a18549908e5cbd012a1e2f5fd05bd6eb8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae6964cace97f4dc9c0fdfa05abf497ee"><td class="memItemLeft" align="right" valign="top"><a id="ae6964cace97f4dc9c0fdfa05abf497ee"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB00D_SERCOM5_PAD2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="separator:ae6964cace97f4dc9c0fdfa05abf497ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae87106cf53d6b7adf0454158498371e1"><td class="memItemLeft" align="right" valign="top"><a id="ae87106cf53d6b7adf0454158498371e1"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB00D_SERCOM5_PAD2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a18549908e5cbd012a1e2f5fd05bd6eb8">PIN_PB00D_SERCOM5_PAD2</a> << 16) | MUX_PB00D_SERCOM5_PAD2)</td></tr>
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<tr class="separator:ae87106cf53d6b7adf0454158498371e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac686431495a788db17bf5ae9f3ff8b1e"><td class="memItemLeft" align="right" valign="top"><a id="ac686431495a788db17bf5ae9f3ff8b1e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB00D_SERCOM5_PAD2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 0)</td></tr>
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<tr class="separator:ac686431495a788db17bf5ae9f3ff8b1e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aff8763497dcca10009b2d7b42f65e066"><td class="memItemLeft" align="right" valign="top"><a id="aff8763497dcca10009b2d7b42f65e066"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aff8763497dcca10009b2d7b42f65e066">PIN_PB22D_SERCOM5_PAD2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(54)</td></tr>
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<tr class="memdesc:aff8763497dcca10009b2d7b42f65e066"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM5 signal: PAD2 on PB22 mux D. <br /></td></tr>
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<tr class="separator:aff8763497dcca10009b2d7b42f65e066"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad06ee3599543f69f0de8904bdc2598a6"><td class="memItemLeft" align="right" valign="top"><a id="ad06ee3599543f69f0de8904bdc2598a6"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB22D_SERCOM5_PAD2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="separator:ad06ee3599543f69f0de8904bdc2598a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a50be2bec24a1ecdce31937a77ab5d09f"><td class="memItemLeft" align="right" valign="top"><a id="a50be2bec24a1ecdce31937a77ab5d09f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB22D_SERCOM5_PAD2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aff8763497dcca10009b2d7b42f65e066">PIN_PB22D_SERCOM5_PAD2</a> << 16) | MUX_PB22D_SERCOM5_PAD2)</td></tr>
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<tr class="separator:a50be2bec24a1ecdce31937a77ab5d09f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3f6b4e7e467e1eb6621a82c33895c6b3"><td class="memItemLeft" align="right" valign="top"><a id="a3f6b4e7e467e1eb6621a82c33895c6b3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB22D_SERCOM5_PAD2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 22)</td></tr>
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<tr class="separator:a3f6b4e7e467e1eb6621a82c33895c6b3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aeaebb673d7ad82b8d5199a3dbbe820d3"><td class="memItemLeft" align="right" valign="top"><a id="aeaebb673d7ad82b8d5199a3dbbe820d3"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aeaebb673d7ad82b8d5199a3dbbe820d3">PIN_PA20C_SERCOM5_PAD2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(20)</td></tr>
|
||
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<tr class="memdesc:aeaebb673d7ad82b8d5199a3dbbe820d3"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM5 signal: PAD2 on PA20 mux C. <br /></td></tr>
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<tr class="separator:aeaebb673d7ad82b8d5199a3dbbe820d3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a719c09e38e9db3e6023ef4acf4c62a49"><td class="memItemLeft" align="right" valign="top"><a id="a719c09e38e9db3e6023ef4acf4c62a49"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA20C_SERCOM5_PAD2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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<tr class="separator:a719c09e38e9db3e6023ef4acf4c62a49"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae1a3c4a59296101baf929b0296ff612c"><td class="memItemLeft" align="right" valign="top"><a id="ae1a3c4a59296101baf929b0296ff612c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA20C_SERCOM5_PAD2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aeaebb673d7ad82b8d5199a3dbbe820d3">PIN_PA20C_SERCOM5_PAD2</a> << 16) | MUX_PA20C_SERCOM5_PAD2)</td></tr>
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<tr class="separator:ae1a3c4a59296101baf929b0296ff612c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a11926927d430da8293b08fcc69a96f17"><td class="memItemLeft" align="right" valign="top"><a id="a11926927d430da8293b08fcc69a96f17"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA20C_SERCOM5_PAD2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 20)</td></tr>
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<tr class="separator:a11926927d430da8293b08fcc69a96f17"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab3c960528e3aa1c5065abd0514df2f0f"><td class="memItemLeft" align="right" valign="top"><a id="ab3c960528e3aa1c5065abd0514df2f0f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab3c960528e3aa1c5065abd0514df2f0f">PIN_PB18C_SERCOM5_PAD2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(50)</td></tr>
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||
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<tr class="memdesc:ab3c960528e3aa1c5065abd0514df2f0f"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM5 signal: PAD2 on PB18 mux C. <br /></td></tr>
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<tr class="separator:ab3c960528e3aa1c5065abd0514df2f0f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5d70923451c625ff5e5a8ab5e2c4e932"><td class="memItemLeft" align="right" valign="top"><a id="a5d70923451c625ff5e5a8ab5e2c4e932"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB18C_SERCOM5_PAD2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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||
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<tr class="memitem:a0ed9483815a7a4d1368ad629cd3f1022"><td class="memItemLeft" align="right" valign="top"><a id="a0ed9483815a7a4d1368ad629cd3f1022"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB18C_SERCOM5_PAD2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ab3c960528e3aa1c5065abd0514df2f0f">PIN_PB18C_SERCOM5_PAD2</a> << 16) | MUX_PB18C_SERCOM5_PAD2)</td></tr>
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<tr class="memitem:a123d9f907b7b794bf9fbb7421d205566"><td class="memItemLeft" align="right" valign="top"><a id="a123d9f907b7b794bf9fbb7421d205566"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB18C_SERCOM5_PAD2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 18)</td></tr>
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<tr class="separator:a123d9f907b7b794bf9fbb7421d205566"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa8cca3dc8884d7066c6dbd183fc417e5"><td class="memItemLeft" align="right" valign="top"><a id="aa8cca3dc8884d7066c6dbd183fc417e5"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa8cca3dc8884d7066c6dbd183fc417e5">PIN_PA25D_SERCOM5_PAD3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(25)</td></tr>
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||
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<tr class="memdesc:aa8cca3dc8884d7066c6dbd183fc417e5"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM5 signal: PAD3 on PA25 mux D. <br /></td></tr>
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<tr class="separator:aa8cca3dc8884d7066c6dbd183fc417e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a063d76a83d6c9d99fe08d7fce8bddb3b"><td class="memItemLeft" align="right" valign="top"><a id="a063d76a83d6c9d99fe08d7fce8bddb3b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA25D_SERCOM5_PAD3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="separator:a063d76a83d6c9d99fe08d7fce8bddb3b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae8f975060a37cccbe3d306fb05c920a3"><td class="memItemLeft" align="right" valign="top"><a id="ae8f975060a37cccbe3d306fb05c920a3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA25D_SERCOM5_PAD3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aa8cca3dc8884d7066c6dbd183fc417e5">PIN_PA25D_SERCOM5_PAD3</a> << 16) | MUX_PA25D_SERCOM5_PAD3)</td></tr>
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<tr class="separator:ae8f975060a37cccbe3d306fb05c920a3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afb1a2b274bc1a2d1d98f1676e949f04f"><td class="memItemLeft" align="right" valign="top"><a id="afb1a2b274bc1a2d1d98f1676e949f04f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA25D_SERCOM5_PAD3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 25)</td></tr>
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||
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<tr class="separator:afb1a2b274bc1a2d1d98f1676e949f04f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af0bbf7659e338b4d68a5751d12fa6483"><td class="memItemLeft" align="right" valign="top"><a id="af0bbf7659e338b4d68a5751d12fa6483"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af0bbf7659e338b4d68a5751d12fa6483">PIN_PB01D_SERCOM5_PAD3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(33)</td></tr>
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||
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<tr class="memdesc:af0bbf7659e338b4d68a5751d12fa6483"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM5 signal: PAD3 on PB01 mux D. <br /></td></tr>
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<tr class="separator:af0bbf7659e338b4d68a5751d12fa6483"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a410b93d03bfb7ebd58ac6382765de314"><td class="memItemLeft" align="right" valign="top"><a id="a410b93d03bfb7ebd58ac6382765de314"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB01D_SERCOM5_PAD3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="separator:a410b93d03bfb7ebd58ac6382765de314"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af27c4cfe484afc10bd70da0fc631dc53"><td class="memItemLeft" align="right" valign="top"><a id="af27c4cfe484afc10bd70da0fc631dc53"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB01D_SERCOM5_PAD3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#af0bbf7659e338b4d68a5751d12fa6483">PIN_PB01D_SERCOM5_PAD3</a> << 16) | MUX_PB01D_SERCOM5_PAD3)</td></tr>
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<tr class="separator:af27c4cfe484afc10bd70da0fc631dc53"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa82290cf25b70388a72dbd7f3346318a"><td class="memItemLeft" align="right" valign="top"><a id="aa82290cf25b70388a72dbd7f3346318a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB01D_SERCOM5_PAD3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 1)</td></tr>
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<tr class="separator:aa82290cf25b70388a72dbd7f3346318a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a80814067d3f472cc8398917ad9c0131a"><td class="memItemLeft" align="right" valign="top"><a id="a80814067d3f472cc8398917ad9c0131a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a80814067d3f472cc8398917ad9c0131a">PIN_PB23D_SERCOM5_PAD3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(55)</td></tr>
|
||
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<tr class="memdesc:a80814067d3f472cc8398917ad9c0131a"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM5 signal: PAD3 on PB23 mux D. <br /></td></tr>
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||
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<tr class="separator:a80814067d3f472cc8398917ad9c0131a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6e60e812594717a2736f849076ae5cd3"><td class="memItemLeft" align="right" valign="top"><a id="a6e60e812594717a2736f849076ae5cd3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB23D_SERCOM5_PAD3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="separator:a6e60e812594717a2736f849076ae5cd3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a55272a225c5d8830c891785a6e06c3f4"><td class="memItemLeft" align="right" valign="top"><a id="a55272a225c5d8830c891785a6e06c3f4"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB23D_SERCOM5_PAD3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a80814067d3f472cc8398917ad9c0131a">PIN_PB23D_SERCOM5_PAD3</a> << 16) | MUX_PB23D_SERCOM5_PAD3)</td></tr>
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<tr class="separator:a55272a225c5d8830c891785a6e06c3f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4acc20685c69ce1871f331a19e53e531"><td class="memItemLeft" align="right" valign="top"><a id="a4acc20685c69ce1871f331a19e53e531"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB23D_SERCOM5_PAD3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 23)</td></tr>
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||
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<tr class="separator:a4acc20685c69ce1871f331a19e53e531"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aae41f3cd9fbb8c529a608996f9840a13"><td class="memItemLeft" align="right" valign="top"><a id="aae41f3cd9fbb8c529a608996f9840a13"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aae41f3cd9fbb8c529a608996f9840a13">PIN_PA21C_SERCOM5_PAD3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(21)</td></tr>
|
||
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<tr class="memdesc:aae41f3cd9fbb8c529a608996f9840a13"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM5 signal: PAD3 on PA21 mux C. <br /></td></tr>
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<tr class="separator:aae41f3cd9fbb8c529a608996f9840a13"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae8c1fb906054a4f4d4a1fbd4789dc306"><td class="memItemLeft" align="right" valign="top"><a id="ae8c1fb906054a4f4d4a1fbd4789dc306"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA21C_SERCOM5_PAD3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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||
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<tr class="separator:ae8c1fb906054a4f4d4a1fbd4789dc306"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7807f0bc1d0ace6bd63d2b4464ed4e3e"><td class="memItemLeft" align="right" valign="top"><a id="a7807f0bc1d0ace6bd63d2b4464ed4e3e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA21C_SERCOM5_PAD3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aae41f3cd9fbb8c529a608996f9840a13">PIN_PA21C_SERCOM5_PAD3</a> << 16) | MUX_PA21C_SERCOM5_PAD3)</td></tr>
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<tr class="separator:a7807f0bc1d0ace6bd63d2b4464ed4e3e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a084e2871d8dabd52fe19e8058bd9f7d4"><td class="memItemLeft" align="right" valign="top"><a id="a084e2871d8dabd52fe19e8058bd9f7d4"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA21C_SERCOM5_PAD3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 21)</td></tr>
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||
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<tr class="separator:a084e2871d8dabd52fe19e8058bd9f7d4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adb385009a35fac5fa0c5f45ae64708df"><td class="memItemLeft" align="right" valign="top"><a id="adb385009a35fac5fa0c5f45ae64708df"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#adb385009a35fac5fa0c5f45ae64708df">PIN_PB19C_SERCOM5_PAD3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(51)</td></tr>
|
||
|
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<tr class="memdesc:adb385009a35fac5fa0c5f45ae64708df"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM5 signal: PAD3 on PB19 mux C. <br /></td></tr>
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<tr class="separator:adb385009a35fac5fa0c5f45ae64708df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a26a64ad774b3074888b0e67bc6a8033f"><td class="memItemLeft" align="right" valign="top"><a id="a26a64ad774b3074888b0e67bc6a8033f"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB19C_SERCOM5_PAD3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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||
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<tr class="separator:a26a64ad774b3074888b0e67bc6a8033f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac612fb0b41ba5e8a8e67317f2e35f683"><td class="memItemLeft" align="right" valign="top"><a id="ac612fb0b41ba5e8a8e67317f2e35f683"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB19C_SERCOM5_PAD3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#adb385009a35fac5fa0c5f45ae64708df">PIN_PB19C_SERCOM5_PAD3</a> << 16) | MUX_PB19C_SERCOM5_PAD3)</td></tr>
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<tr class="separator:ac612fb0b41ba5e8a8e67317f2e35f683"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a79c52081a324f1f0f183f8865a2fbc91"><td class="memItemLeft" align="right" valign="top"><a id="a79c52081a324f1f0f183f8865a2fbc91"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB19C_SERCOM5_PAD3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 19)</td></tr>
|
||
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<tr class="separator:a79c52081a324f1f0f183f8865a2fbc91"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:add09905d2ccada956af8cca7fd172732"><td class="memItemLeft" align="right" valign="top"><a id="add09905d2ccada956af8cca7fd172732"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#add09905d2ccada956af8cca7fd172732">PIN_PC13D_SERCOM6_PAD0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(77)</td></tr>
|
||
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<tr class="memdesc:add09905d2ccada956af8cca7fd172732"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM6 signal: PAD0 on PC13 mux D. <br /></td></tr>
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||
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<tr class="separator:add09905d2ccada956af8cca7fd172732"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9682a75d0826e7feea90476322375dda"><td class="memItemLeft" align="right" valign="top"><a id="a9682a75d0826e7feea90476322375dda"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC13D_SERCOM6_PAD0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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||
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<tr class="separator:a9682a75d0826e7feea90476322375dda"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad7aae76502c41344c04a06790bffd13e"><td class="memItemLeft" align="right" valign="top"><a id="ad7aae76502c41344c04a06790bffd13e"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC13D_SERCOM6_PAD0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#add09905d2ccada956af8cca7fd172732">PIN_PC13D_SERCOM6_PAD0</a> << 16) | MUX_PC13D_SERCOM6_PAD0)</td></tr>
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<tr class="separator:ad7aae76502c41344c04a06790bffd13e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a587d2b1799deb2328b413291da311d75"><td class="memItemLeft" align="right" valign="top"><a id="a587d2b1799deb2328b413291da311d75"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC13D_SERCOM6_PAD0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 13)</td></tr>
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||
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<tr class="separator:a587d2b1799deb2328b413291da311d75"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a6f0654016b08bb056b7e8aa5ce30898d"><td class="memItemLeft" align="right" valign="top"><a id="a6f0654016b08bb056b7e8aa5ce30898d"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6f0654016b08bb056b7e8aa5ce30898d">PIN_PC16C_SERCOM6_PAD0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(80)</td></tr>
|
||
|
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<tr class="memdesc:a6f0654016b08bb056b7e8aa5ce30898d"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM6 signal: PAD0 on PC16 mux C. <br /></td></tr>
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||
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<tr class="separator:a6f0654016b08bb056b7e8aa5ce30898d"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a8de337ebcc6156a2884b6426ae6cc1d0"><td class="memItemLeft" align="right" valign="top"><a id="a8de337ebcc6156a2884b6426ae6cc1d0"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC16C_SERCOM6_PAD0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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||
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<tr class="separator:a8de337ebcc6156a2884b6426ae6cc1d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aff93a40585a45701793b8f87a7576f07"><td class="memItemLeft" align="right" valign="top"><a id="aff93a40585a45701793b8f87a7576f07"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC16C_SERCOM6_PAD0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a6f0654016b08bb056b7e8aa5ce30898d">PIN_PC16C_SERCOM6_PAD0</a> << 16) | MUX_PC16C_SERCOM6_PAD0)</td></tr>
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<tr class="separator:aff93a40585a45701793b8f87a7576f07"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a02d55483f8ec8ab2db4c3b9f189a46bf"><td class="memItemLeft" align="right" valign="top"><a id="a02d55483f8ec8ab2db4c3b9f189a46bf"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC16C_SERCOM6_PAD0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 16)</td></tr>
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<tr class="separator:a02d55483f8ec8ab2db4c3b9f189a46bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9d35c0504131f2769abe7f184ec151e2"><td class="memItemLeft" align="right" valign="top"><a id="a9d35c0504131f2769abe7f184ec151e2"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a9d35c0504131f2769abe7f184ec151e2">PIN_PC12D_SERCOM6_PAD1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(76)</td></tr>
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||
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<tr class="memdesc:a9d35c0504131f2769abe7f184ec151e2"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM6 signal: PAD1 on PC12 mux D. <br /></td></tr>
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<tr class="separator:a9d35c0504131f2769abe7f184ec151e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4eb4442e1f741fb8c111e909e14ef268"><td class="memItemLeft" align="right" valign="top"><a id="a4eb4442e1f741fb8c111e909e14ef268"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC12D_SERCOM6_PAD1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="separator:a4eb4442e1f741fb8c111e909e14ef268"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:addafd9c03bba688ff22340c096ea922e"><td class="memItemLeft" align="right" valign="top"><a id="addafd9c03bba688ff22340c096ea922e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC12D_SERCOM6_PAD1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a9d35c0504131f2769abe7f184ec151e2">PIN_PC12D_SERCOM6_PAD1</a> << 16) | MUX_PC12D_SERCOM6_PAD1)</td></tr>
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<tr class="separator:addafd9c03bba688ff22340c096ea922e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acef6ac5a85ddbfea164caebe94780d9a"><td class="memItemLeft" align="right" valign="top"><a id="acef6ac5a85ddbfea164caebe94780d9a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC12D_SERCOM6_PAD1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 12)</td></tr>
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||
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<tr class="separator:acef6ac5a85ddbfea164caebe94780d9a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad36b5a7e806584fb77ccd3727c63e199"><td class="memItemLeft" align="right" valign="top"><a id="ad36b5a7e806584fb77ccd3727c63e199"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad36b5a7e806584fb77ccd3727c63e199">PIN_PC05C_SERCOM6_PAD1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(69)</td></tr>
|
||
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<tr class="memdesc:ad36b5a7e806584fb77ccd3727c63e199"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM6 signal: PAD1 on PC05 mux C. <br /></td></tr>
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<tr class="separator:ad36b5a7e806584fb77ccd3727c63e199"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9207f465f03b480f9f1afe63c87dafe8"><td class="memItemLeft" align="right" valign="top"><a id="a9207f465f03b480f9f1afe63c87dafe8"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC05C_SERCOM6_PAD1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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||
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<tr class="separator:a9207f465f03b480f9f1afe63c87dafe8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aac28eacc7086e6acf1dbfb51876f5cca"><td class="memItemLeft" align="right" valign="top"><a id="aac28eacc7086e6acf1dbfb51876f5cca"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC05C_SERCOM6_PAD1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ad36b5a7e806584fb77ccd3727c63e199">PIN_PC05C_SERCOM6_PAD1</a> << 16) | MUX_PC05C_SERCOM6_PAD1)</td></tr>
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<tr class="separator:aac28eacc7086e6acf1dbfb51876f5cca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8a949e338c4268cc425926b621ceae15"><td class="memItemLeft" align="right" valign="top"><a id="a8a949e338c4268cc425926b621ceae15"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC05C_SERCOM6_PAD1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 5)</td></tr>
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||
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<tr class="separator:a8a949e338c4268cc425926b621ceae15"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a47adc4dc76282eec950bbb955334dc23"><td class="memItemLeft" align="right" valign="top"><a id="a47adc4dc76282eec950bbb955334dc23"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a47adc4dc76282eec950bbb955334dc23">PIN_PC17C_SERCOM6_PAD1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(81)</td></tr>
|
||
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<tr class="memdesc:a47adc4dc76282eec950bbb955334dc23"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM6 signal: PAD1 on PC17 mux C. <br /></td></tr>
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<tr class="separator:a47adc4dc76282eec950bbb955334dc23"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0976262e17b21e60e333b9293ab6e8cf"><td class="memItemLeft" align="right" valign="top"><a id="a0976262e17b21e60e333b9293ab6e8cf"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC17C_SERCOM6_PAD1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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||
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<tr class="separator:a0976262e17b21e60e333b9293ab6e8cf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad5e5348ede42d22abb1c72c0f1ea93d4"><td class="memItemLeft" align="right" valign="top"><a id="ad5e5348ede42d22abb1c72c0f1ea93d4"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC17C_SERCOM6_PAD1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a47adc4dc76282eec950bbb955334dc23">PIN_PC17C_SERCOM6_PAD1</a> << 16) | MUX_PC17C_SERCOM6_PAD1)</td></tr>
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<tr class="separator:ad5e5348ede42d22abb1c72c0f1ea93d4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4eeaaae57bdfc16b504777cda52524c8"><td class="memItemLeft" align="right" valign="top"><a id="a4eeaaae57bdfc16b504777cda52524c8"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC17C_SERCOM6_PAD1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 17)</td></tr>
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||
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<tr class="separator:a4eeaaae57bdfc16b504777cda52524c8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3d52138a024ab1a1aae99d512d77308b"><td class="memItemLeft" align="right" valign="top"><a id="a3d52138a024ab1a1aae99d512d77308b"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3d52138a024ab1a1aae99d512d77308b">PIN_PC14D_SERCOM6_PAD2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(78)</td></tr>
|
||
|
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<tr class="memdesc:a3d52138a024ab1a1aae99d512d77308b"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM6 signal: PAD2 on PC14 mux D. <br /></td></tr>
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||
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<tr class="separator:a3d52138a024ab1a1aae99d512d77308b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a710dd6416a25bf700513d98192d635ec"><td class="memItemLeft" align="right" valign="top"><a id="a710dd6416a25bf700513d98192d635ec"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC14D_SERCOM6_PAD2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
|
||
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<tr class="separator:a710dd6416a25bf700513d98192d635ec"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:ab3e0f51660fb115c8549d76e1676eaba"><td class="memItemLeft" align="right" valign="top"><a id="ab3e0f51660fb115c8549d76e1676eaba"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC14D_SERCOM6_PAD2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a3d52138a024ab1a1aae99d512d77308b">PIN_PC14D_SERCOM6_PAD2</a> << 16) | MUX_PC14D_SERCOM6_PAD2)</td></tr>
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<tr class="separator:ab3e0f51660fb115c8549d76e1676eaba"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a1cf72acd632be2ba8dcc8ac5d486e5e2"><td class="memItemLeft" align="right" valign="top"><a id="a1cf72acd632be2ba8dcc8ac5d486e5e2"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC14D_SERCOM6_PAD2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 14)</td></tr>
|
||
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<tr class="separator:a1cf72acd632be2ba8dcc8ac5d486e5e2"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:a70adfb0f739f5b4c0428cc3fad707fe2"><td class="memItemLeft" align="right" valign="top"><a id="a70adfb0f739f5b4c0428cc3fad707fe2"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a70adfb0f739f5b4c0428cc3fad707fe2">PIN_PC06C_SERCOM6_PAD2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(70)</td></tr>
|
||
|
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<tr class="memdesc:a70adfb0f739f5b4c0428cc3fad707fe2"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM6 signal: PAD2 on PC06 mux C. <br /></td></tr>
|
||
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<tr class="separator:a70adfb0f739f5b4c0428cc3fad707fe2"><td class="memSeparator" colspan="2"> </td></tr>
|
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<tr class="memitem:a5cb160fa5923cdf397729d5f212a9cf8"><td class="memItemLeft" align="right" valign="top"><a id="a5cb160fa5923cdf397729d5f212a9cf8"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC06C_SERCOM6_PAD2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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||
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<tr class="separator:a5cb160fa5923cdf397729d5f212a9cf8"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a81340ad1d8145c9bda408f8de63b6a63"><td class="memItemLeft" align="right" valign="top"><a id="a81340ad1d8145c9bda408f8de63b6a63"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC06C_SERCOM6_PAD2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a70adfb0f739f5b4c0428cc3fad707fe2">PIN_PC06C_SERCOM6_PAD2</a> << 16) | MUX_PC06C_SERCOM6_PAD2)</td></tr>
|
||
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<tr class="separator:a81340ad1d8145c9bda408f8de63b6a63"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a67f0ee6111858291c0cf48037362a1b6"><td class="memItemLeft" align="right" valign="top"><a id="a67f0ee6111858291c0cf48037362a1b6"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC06C_SERCOM6_PAD2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 6)</td></tr>
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||
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<tr class="separator:a67f0ee6111858291c0cf48037362a1b6"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:aabbf8386c6fc00ec4ae5b0e38ee77347"><td class="memItemLeft" align="right" valign="top"><a id="aabbf8386c6fc00ec4ae5b0e38ee77347"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aabbf8386c6fc00ec4ae5b0e38ee77347">PIN_PC10C_SERCOM6_PAD2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(74)</td></tr>
|
||
|
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<tr class="memdesc:aabbf8386c6fc00ec4ae5b0e38ee77347"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM6 signal: PAD2 on PC10 mux C. <br /></td></tr>
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||
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<tr class="separator:aabbf8386c6fc00ec4ae5b0e38ee77347"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a382757e7093fda6bec64d90cfb8ec5fb"><td class="memItemLeft" align="right" valign="top"><a id="a382757e7093fda6bec64d90cfb8ec5fb"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC10C_SERCOM6_PAD2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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||
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<tr class="separator:a382757e7093fda6bec64d90cfb8ec5fb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9890606ad486f558446ac47c9e2ce9fd"><td class="memItemLeft" align="right" valign="top"><a id="a9890606ad486f558446ac47c9e2ce9fd"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC10C_SERCOM6_PAD2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aabbf8386c6fc00ec4ae5b0e38ee77347">PIN_PC10C_SERCOM6_PAD2</a> << 16) | MUX_PC10C_SERCOM6_PAD2)</td></tr>
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||
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<tr class="separator:a9890606ad486f558446ac47c9e2ce9fd"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a3c7954133a73e20b5b39c1d6939f3907"><td class="memItemLeft" align="right" valign="top"><a id="a3c7954133a73e20b5b39c1d6939f3907"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC10C_SERCOM6_PAD2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 10)</td></tr>
|
||
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<tr class="separator:a3c7954133a73e20b5b39c1d6939f3907"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:afa584864df2456aa525ce49ab697f751"><td class="memItemLeft" align="right" valign="top"><a id="afa584864df2456aa525ce49ab697f751"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#afa584864df2456aa525ce49ab697f751">PIN_PC18C_SERCOM6_PAD2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(82)</td></tr>
|
||
|
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<tr class="memdesc:afa584864df2456aa525ce49ab697f751"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM6 signal: PAD2 on PC18 mux C. <br /></td></tr>
|
||
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<tr class="separator:afa584864df2456aa525ce49ab697f751"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:ad473027932083e110866d16a3318263f"><td class="memItemLeft" align="right" valign="top"><a id="ad473027932083e110866d16a3318263f"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC18C_SERCOM6_PAD2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
|
||
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<tr class="separator:ad473027932083e110866d16a3318263f"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a27c24d74e50bd5011c9eba0fe634938b"><td class="memItemLeft" align="right" valign="top"><a id="a27c24d74e50bd5011c9eba0fe634938b"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC18C_SERCOM6_PAD2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#afa584864df2456aa525ce49ab697f751">PIN_PC18C_SERCOM6_PAD2</a> << 16) | MUX_PC18C_SERCOM6_PAD2)</td></tr>
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<tr class="separator:a27c24d74e50bd5011c9eba0fe634938b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a95a83a65de268a2352c604a1372cec40"><td class="memItemLeft" align="right" valign="top"><a id="a95a83a65de268a2352c604a1372cec40"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC18C_SERCOM6_PAD2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 18)</td></tr>
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<tr class="separator:a95a83a65de268a2352c604a1372cec40"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a22792353d9edc0691c3075bdbf84331e"><td class="memItemLeft" align="right" valign="top"><a id="a22792353d9edc0691c3075bdbf84331e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a22792353d9edc0691c3075bdbf84331e">PIN_PC15D_SERCOM6_PAD3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(79)</td></tr>
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||
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<tr class="memdesc:a22792353d9edc0691c3075bdbf84331e"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM6 signal: PAD3 on PC15 mux D. <br /></td></tr>
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<tr class="separator:a22792353d9edc0691c3075bdbf84331e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2c4861d43fa2d03993b2227b282fc46f"><td class="memItemLeft" align="right" valign="top"><a id="a2c4861d43fa2d03993b2227b282fc46f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC15D_SERCOM6_PAD3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="separator:a2c4861d43fa2d03993b2227b282fc46f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:affea830c00153efe9cb765036279c024"><td class="memItemLeft" align="right" valign="top"><a id="affea830c00153efe9cb765036279c024"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC15D_SERCOM6_PAD3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a22792353d9edc0691c3075bdbf84331e">PIN_PC15D_SERCOM6_PAD3</a> << 16) | MUX_PC15D_SERCOM6_PAD3)</td></tr>
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<tr class="separator:affea830c00153efe9cb765036279c024"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae30a0c5750c51a2fc99896a2cbf1378e"><td class="memItemLeft" align="right" valign="top"><a id="ae30a0c5750c51a2fc99896a2cbf1378e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC15D_SERCOM6_PAD3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 15)</td></tr>
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||
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<tr class="separator:ae30a0c5750c51a2fc99896a2cbf1378e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5559dc4fa2bdf05f8265c08d828ff37a"><td class="memItemLeft" align="right" valign="top"><a id="a5559dc4fa2bdf05f8265c08d828ff37a"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5559dc4fa2bdf05f8265c08d828ff37a">PIN_PC07C_SERCOM6_PAD3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(71)</td></tr>
|
||
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<tr class="memdesc:a5559dc4fa2bdf05f8265c08d828ff37a"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM6 signal: PAD3 on PC07 mux C. <br /></td></tr>
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<tr class="separator:a5559dc4fa2bdf05f8265c08d828ff37a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac91cc2f3476a4bec67c140baaf1c7936"><td class="memItemLeft" align="right" valign="top"><a id="ac91cc2f3476a4bec67c140baaf1c7936"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC07C_SERCOM6_PAD3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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<tr class="separator:ac91cc2f3476a4bec67c140baaf1c7936"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af7a12acff7ff0d9fcddc79073f2d253a"><td class="memItemLeft" align="right" valign="top"><a id="af7a12acff7ff0d9fcddc79073f2d253a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC07C_SERCOM6_PAD3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a5559dc4fa2bdf05f8265c08d828ff37a">PIN_PC07C_SERCOM6_PAD3</a> << 16) | MUX_PC07C_SERCOM6_PAD3)</td></tr>
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<tr class="separator:af7a12acff7ff0d9fcddc79073f2d253a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3497422eaa5b115528a0ee4f58fb12d0"><td class="memItemLeft" align="right" valign="top"><a id="a3497422eaa5b115528a0ee4f58fb12d0"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC07C_SERCOM6_PAD3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 7)</td></tr>
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||
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<tr class="separator:a3497422eaa5b115528a0ee4f58fb12d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a703016701829ef29cdee31c325c510d1"><td class="memItemLeft" align="right" valign="top"><a id="a703016701829ef29cdee31c325c510d1"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a703016701829ef29cdee31c325c510d1">PIN_PC11C_SERCOM6_PAD3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(75)</td></tr>
|
||
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<tr class="memdesc:a703016701829ef29cdee31c325c510d1"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM6 signal: PAD3 on PC11 mux C. <br /></td></tr>
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||
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<tr class="separator:a703016701829ef29cdee31c325c510d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a460d199509cdfaf85f9fd236475f492c"><td class="memItemLeft" align="right" valign="top"><a id="a460d199509cdfaf85f9fd236475f492c"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC11C_SERCOM6_PAD3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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||
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<tr class="separator:a460d199509cdfaf85f9fd236475f492c"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a2963a4bc75464bcd8822ab7f14315a29"><td class="memItemLeft" align="right" valign="top"><a id="a2963a4bc75464bcd8822ab7f14315a29"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC11C_SERCOM6_PAD3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a703016701829ef29cdee31c325c510d1">PIN_PC11C_SERCOM6_PAD3</a> << 16) | MUX_PC11C_SERCOM6_PAD3)</td></tr>
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||
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<tr class="separator:a2963a4bc75464bcd8822ab7f14315a29"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a44c0a286416916ddbd46bbbf2cb2bfd4"><td class="memItemLeft" align="right" valign="top"><a id="a44c0a286416916ddbd46bbbf2cb2bfd4"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC11C_SERCOM6_PAD3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 11)</td></tr>
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||
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<tr class="separator:a44c0a286416916ddbd46bbbf2cb2bfd4"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:ae9c65aecc2c2ea4dc952682aace4d14e"><td class="memItemLeft" align="right" valign="top"><a id="ae9c65aecc2c2ea4dc952682aace4d14e"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae9c65aecc2c2ea4dc952682aace4d14e">PIN_PC19C_SERCOM6_PAD3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(83)</td></tr>
|
||
|
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<tr class="memdesc:ae9c65aecc2c2ea4dc952682aace4d14e"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM6 signal: PAD3 on PC19 mux C. <br /></td></tr>
|
||
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<tr class="separator:ae9c65aecc2c2ea4dc952682aace4d14e"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a21ea61f4ac7a5e2aaf1a058726f714ab"><td class="memItemLeft" align="right" valign="top"><a id="a21ea61f4ac7a5e2aaf1a058726f714ab"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC19C_SERCOM6_PAD3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
|
||
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<tr class="separator:a21ea61f4ac7a5e2aaf1a058726f714ab"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a35a4e8fa5c1d13c3677e5e39da12e416"><td class="memItemLeft" align="right" valign="top"><a id="a35a4e8fa5c1d13c3677e5e39da12e416"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC19C_SERCOM6_PAD3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ae9c65aecc2c2ea4dc952682aace4d14e">PIN_PC19C_SERCOM6_PAD3</a> << 16) | MUX_PC19C_SERCOM6_PAD3)</td></tr>
|
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<tr class="separator:a35a4e8fa5c1d13c3677e5e39da12e416"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:afba9326cc3b2678bcc16bc8a64a7a6c0"><td class="memItemLeft" align="right" valign="top"><a id="afba9326cc3b2678bcc16bc8a64a7a6c0"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC19C_SERCOM6_PAD3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 19)</td></tr>
|
||
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<tr class="separator:afba9326cc3b2678bcc16bc8a64a7a6c0"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a314a50f60a5a450e1bb306c1d67bfd40"><td class="memItemLeft" align="right" valign="top"><a id="a314a50f60a5a450e1bb306c1d67bfd40"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a314a50f60a5a450e1bb306c1d67bfd40">PIN_PB21D_SERCOM7_PAD0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(53)</td></tr>
|
||
|
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<tr class="memdesc:a314a50f60a5a450e1bb306c1d67bfd40"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM7 signal: PAD0 on PB21 mux D. <br /></td></tr>
|
||
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<tr class="separator:a314a50f60a5a450e1bb306c1d67bfd40"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a5de722616ea255f1601a961ea69a2c0e"><td class="memItemLeft" align="right" valign="top"><a id="a5de722616ea255f1601a961ea69a2c0e"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB21D_SERCOM7_PAD0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
|
||
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<tr class="separator:a5de722616ea255f1601a961ea69a2c0e"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a48157f66c6adf890999f22a610a2d476"><td class="memItemLeft" align="right" valign="top"><a id="a48157f66c6adf890999f22a610a2d476"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB21D_SERCOM7_PAD0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a314a50f60a5a450e1bb306c1d67bfd40">PIN_PB21D_SERCOM7_PAD0</a> << 16) | MUX_PB21D_SERCOM7_PAD0)</td></tr>
|
||
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<tr class="separator:a48157f66c6adf890999f22a610a2d476"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a3883d7a332b23af2a953d3c07fd4e4e4"><td class="memItemLeft" align="right" valign="top"><a id="a3883d7a332b23af2a953d3c07fd4e4e4"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB21D_SERCOM7_PAD0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 21)</td></tr>
|
||
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<tr class="separator:a3883d7a332b23af2a953d3c07fd4e4e4"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a31aea605cce72c75ac6a5634032cae16"><td class="memItemLeft" align="right" valign="top"><a id="a31aea605cce72c75ac6a5634032cae16"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a31aea605cce72c75ac6a5634032cae16">PIN_PB30C_SERCOM7_PAD0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(62)</td></tr>
|
||
|
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<tr class="memdesc:a31aea605cce72c75ac6a5634032cae16"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM7 signal: PAD0 on PB30 mux C. <br /></td></tr>
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||
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<tr class="separator:a31aea605cce72c75ac6a5634032cae16"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad0383c93b3293a70cc4d7f4992bf4dd2"><td class="memItemLeft" align="right" valign="top"><a id="ad0383c93b3293a70cc4d7f4992bf4dd2"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB30C_SERCOM7_PAD0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
|
||
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<tr class="separator:ad0383c93b3293a70cc4d7f4992bf4dd2"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:ae0534574326240d6ee26c2e00da7beb4"><td class="memItemLeft" align="right" valign="top"><a id="ae0534574326240d6ee26c2e00da7beb4"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB30C_SERCOM7_PAD0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a31aea605cce72c75ac6a5634032cae16">PIN_PB30C_SERCOM7_PAD0</a> << 16) | MUX_PB30C_SERCOM7_PAD0)</td></tr>
|
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<tr class="separator:ae0534574326240d6ee26c2e00da7beb4"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a83b5549ef0fd1f9f27a3db4a0458e77c"><td class="memItemLeft" align="right" valign="top"><a id="a83b5549ef0fd1f9f27a3db4a0458e77c"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB30C_SERCOM7_PAD0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 30)</td></tr>
|
||
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<tr class="separator:a83b5549ef0fd1f9f27a3db4a0458e77c"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a99f2657f578b26c2aa214b320a2629b4"><td class="memItemLeft" align="right" valign="top"><a id="a99f2657f578b26c2aa214b320a2629b4"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a99f2657f578b26c2aa214b320a2629b4">PIN_PC12C_SERCOM7_PAD0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(76)</td></tr>
|
||
|
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<tr class="memdesc:a99f2657f578b26c2aa214b320a2629b4"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM7 signal: PAD0 on PC12 mux C. <br /></td></tr>
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||
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<tr class="separator:a99f2657f578b26c2aa214b320a2629b4"><td class="memSeparator" colspan="2"> </td></tr>
|
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<tr class="memitem:a8a46be196776022dec8480b2a79d82a5"><td class="memItemLeft" align="right" valign="top"><a id="a8a46be196776022dec8480b2a79d82a5"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC12C_SERCOM7_PAD0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
|
||
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<tr class="separator:a8a46be196776022dec8480b2a79d82a5"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a5d2c70a6c238cb6bf8d651a98208f3fc"><td class="memItemLeft" align="right" valign="top"><a id="a5d2c70a6c238cb6bf8d651a98208f3fc"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC12C_SERCOM7_PAD0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a99f2657f578b26c2aa214b320a2629b4">PIN_PC12C_SERCOM7_PAD0</a> << 16) | MUX_PC12C_SERCOM7_PAD0)</td></tr>
|
||
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<tr class="separator:a5d2c70a6c238cb6bf8d651a98208f3fc"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:ad06a65966ed853590c080ef23cbf7cba"><td class="memItemLeft" align="right" valign="top"><a id="ad06a65966ed853590c080ef23cbf7cba"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC12C_SERCOM7_PAD0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 12)</td></tr>
|
||
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<tr class="separator:ad06a65966ed853590c080ef23cbf7cba"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a71d7e6904f7aa4687a6f46d44477fec8"><td class="memItemLeft" align="right" valign="top"><a id="a71d7e6904f7aa4687a6f46d44477fec8"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a71d7e6904f7aa4687a6f46d44477fec8">PIN_PB20D_SERCOM7_PAD1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(52)</td></tr>
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||
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<tr class="memdesc:a71d7e6904f7aa4687a6f46d44477fec8"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM7 signal: PAD1 on PB20 mux D. <br /></td></tr>
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<tr class="separator:a71d7e6904f7aa4687a6f46d44477fec8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad974d0dcf966bdc46b132b761ce0a9f9"><td class="memItemLeft" align="right" valign="top"><a id="ad974d0dcf966bdc46b132b761ce0a9f9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB20D_SERCOM7_PAD1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="separator:ad974d0dcf966bdc46b132b761ce0a9f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4454e98054a9b9dd7d6668ba6fb2a8b3"><td class="memItemLeft" align="right" valign="top"><a id="a4454e98054a9b9dd7d6668ba6fb2a8b3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB20D_SERCOM7_PAD1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a71d7e6904f7aa4687a6f46d44477fec8">PIN_PB20D_SERCOM7_PAD1</a> << 16) | MUX_PB20D_SERCOM7_PAD1)</td></tr>
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<tr class="separator:a4454e98054a9b9dd7d6668ba6fb2a8b3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad42738ea2662c86cb73fca09afa5ac61"><td class="memItemLeft" align="right" valign="top"><a id="ad42738ea2662c86cb73fca09afa5ac61"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB20D_SERCOM7_PAD1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 20)</td></tr>
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<tr class="separator:ad42738ea2662c86cb73fca09afa5ac61"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6dd84e1c95ed39e08526375c27e9b6f5"><td class="memItemLeft" align="right" valign="top"><a id="a6dd84e1c95ed39e08526375c27e9b6f5"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6dd84e1c95ed39e08526375c27e9b6f5">PIN_PB31C_SERCOM7_PAD1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(63)</td></tr>
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||
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<tr class="memdesc:a6dd84e1c95ed39e08526375c27e9b6f5"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM7 signal: PAD1 on PB31 mux C. <br /></td></tr>
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<tr class="separator:a6dd84e1c95ed39e08526375c27e9b6f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a948c89cf5bee74627d108ee016dda395"><td class="memItemLeft" align="right" valign="top"><a id="a948c89cf5bee74627d108ee016dda395"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB31C_SERCOM7_PAD1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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<tr class="separator:a948c89cf5bee74627d108ee016dda395"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad3a77e22c6dff4014d69c78bcd1adee2"><td class="memItemLeft" align="right" valign="top"><a id="ad3a77e22c6dff4014d69c78bcd1adee2"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB31C_SERCOM7_PAD1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a6dd84e1c95ed39e08526375c27e9b6f5">PIN_PB31C_SERCOM7_PAD1</a> << 16) | MUX_PB31C_SERCOM7_PAD1)</td></tr>
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<tr class="separator:ad3a77e22c6dff4014d69c78bcd1adee2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3ee56535b4d1d32a9a16b60e6a99b42f"><td class="memItemLeft" align="right" valign="top"><a id="a3ee56535b4d1d32a9a16b60e6a99b42f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB31C_SERCOM7_PAD1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 31)</td></tr>
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||
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<tr class="separator:a3ee56535b4d1d32a9a16b60e6a99b42f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:addbe554ac2caf90827680817593a6554"><td class="memItemLeft" align="right" valign="top"><a id="addbe554ac2caf90827680817593a6554"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#addbe554ac2caf90827680817593a6554">PIN_PC13C_SERCOM7_PAD1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(77)</td></tr>
|
||
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<tr class="memdesc:addbe554ac2caf90827680817593a6554"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM7 signal: PAD1 on PC13 mux C. <br /></td></tr>
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<tr class="separator:addbe554ac2caf90827680817593a6554"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6d56b69eb38d6b18e8601c0866795a3b"><td class="memItemLeft" align="right" valign="top"><a id="a6d56b69eb38d6b18e8601c0866795a3b"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC13C_SERCOM7_PAD1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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<tr class="separator:a6d56b69eb38d6b18e8601c0866795a3b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a91656940b43cfabb4be6bac556a9c33e"><td class="memItemLeft" align="right" valign="top"><a id="a91656940b43cfabb4be6bac556a9c33e"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC13C_SERCOM7_PAD1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#addbe554ac2caf90827680817593a6554">PIN_PC13C_SERCOM7_PAD1</a> << 16) | MUX_PC13C_SERCOM7_PAD1)</td></tr>
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<tr class="separator:a91656940b43cfabb4be6bac556a9c33e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac3fcad81eefa9a1f2a39995eca0ac4d4"><td class="memItemLeft" align="right" valign="top"><a id="ac3fcad81eefa9a1f2a39995eca0ac4d4"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC13C_SERCOM7_PAD1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 13)</td></tr>
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||
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<tr class="separator:ac3fcad81eefa9a1f2a39995eca0ac4d4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aca2dc7884a7f52b6a1fd5816846b37bb"><td class="memItemLeft" align="right" valign="top"><a id="aca2dc7884a7f52b6a1fd5816846b37bb"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aca2dc7884a7f52b6a1fd5816846b37bb">PIN_PB18D_SERCOM7_PAD2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(50)</td></tr>
|
||
|
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<tr class="memdesc:aca2dc7884a7f52b6a1fd5816846b37bb"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM7 signal: PAD2 on PB18 mux D. <br /></td></tr>
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||
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<tr class="separator:aca2dc7884a7f52b6a1fd5816846b37bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acaf915408e50c9aa126d8a551687faff"><td class="memItemLeft" align="right" valign="top"><a id="acaf915408e50c9aa126d8a551687faff"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB18D_SERCOM7_PAD2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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||
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<tr class="separator:acaf915408e50c9aa126d8a551687faff"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a02c8bb76a7f59b8c7f1aec9e17474699"><td class="memItemLeft" align="right" valign="top"><a id="a02c8bb76a7f59b8c7f1aec9e17474699"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB18D_SERCOM7_PAD2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aca2dc7884a7f52b6a1fd5816846b37bb">PIN_PB18D_SERCOM7_PAD2</a> << 16) | MUX_PB18D_SERCOM7_PAD2)</td></tr>
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<tr class="separator:a02c8bb76a7f59b8c7f1aec9e17474699"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a69683fb28d0a10a105e0208e1ae56a85"><td class="memItemLeft" align="right" valign="top"><a id="a69683fb28d0a10a105e0208e1ae56a85"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB18D_SERCOM7_PAD2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 18)</td></tr>
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||
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<tr class="separator:a69683fb28d0a10a105e0208e1ae56a85"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a12a0e719c774f873abe1b6479f6a3980"><td class="memItemLeft" align="right" valign="top"><a id="a12a0e719c774f873abe1b6479f6a3980"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a12a0e719c774f873abe1b6479f6a3980">PIN_PC10D_SERCOM7_PAD2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(74)</td></tr>
|
||
|
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<tr class="memdesc:a12a0e719c774f873abe1b6479f6a3980"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM7 signal: PAD2 on PC10 mux D. <br /></td></tr>
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||
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<tr class="separator:a12a0e719c774f873abe1b6479f6a3980"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a357fb78ec35eabea390005e9bbba2961"><td class="memItemLeft" align="right" valign="top"><a id="a357fb78ec35eabea390005e9bbba2961"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC10D_SERCOM7_PAD2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
|
||
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<tr class="separator:a357fb78ec35eabea390005e9bbba2961"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa0c49a30fb5ed7556b1164773d925244"><td class="memItemLeft" align="right" valign="top"><a id="aa0c49a30fb5ed7556b1164773d925244"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC10D_SERCOM7_PAD2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a12a0e719c774f873abe1b6479f6a3980">PIN_PC10D_SERCOM7_PAD2</a> << 16) | MUX_PC10D_SERCOM7_PAD2)</td></tr>
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<tr class="separator:aa0c49a30fb5ed7556b1164773d925244"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a89e34d6520bd2bd30dd296eea85d2f90"><td class="memItemLeft" align="right" valign="top"><a id="a89e34d6520bd2bd30dd296eea85d2f90"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC10D_SERCOM7_PAD2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 10)</td></tr>
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||
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<tr class="separator:a89e34d6520bd2bd30dd296eea85d2f90"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a497eb8d6c380a8ce96bf2e2b68a88895"><td class="memItemLeft" align="right" valign="top"><a id="a497eb8d6c380a8ce96bf2e2b68a88895"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a497eb8d6c380a8ce96bf2e2b68a88895">PIN_PC14C_SERCOM7_PAD2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(78)</td></tr>
|
||
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<tr class="memdesc:a497eb8d6c380a8ce96bf2e2b68a88895"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM7 signal: PAD2 on PC14 mux C. <br /></td></tr>
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||
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<tr class="separator:a497eb8d6c380a8ce96bf2e2b68a88895"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a38ed81f4cfbe3fc074ec5b0cce0f1ec5"><td class="memItemLeft" align="right" valign="top"><a id="a38ed81f4cfbe3fc074ec5b0cce0f1ec5"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC14C_SERCOM7_PAD2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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||
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<tr class="separator:a38ed81f4cfbe3fc074ec5b0cce0f1ec5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abfe61a417894be074b9feb9011fa5246"><td class="memItemLeft" align="right" valign="top"><a id="abfe61a417894be074b9feb9011fa5246"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC14C_SERCOM7_PAD2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a497eb8d6c380a8ce96bf2e2b68a88895">PIN_PC14C_SERCOM7_PAD2</a> << 16) | MUX_PC14C_SERCOM7_PAD2)</td></tr>
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<tr class="separator:abfe61a417894be074b9feb9011fa5246"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af4e8c3fc22bb95b50719bbd506409b7d"><td class="memItemLeft" align="right" valign="top"><a id="af4e8c3fc22bb95b50719bbd506409b7d"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC14C_SERCOM7_PAD2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 14)</td></tr>
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||
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<tr class="separator:af4e8c3fc22bb95b50719bbd506409b7d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a016b93cd689a15f8bca86b848da12cf5"><td class="memItemLeft" align="right" valign="top"><a id="a016b93cd689a15f8bca86b848da12cf5"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a016b93cd689a15f8bca86b848da12cf5">PIN_PA30C_SERCOM7_PAD2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(30)</td></tr>
|
||
|
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<tr class="memdesc:a016b93cd689a15f8bca86b848da12cf5"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM7 signal: PAD2 on PA30 mux C. <br /></td></tr>
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||
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<tr class="separator:a016b93cd689a15f8bca86b848da12cf5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6c30db65be1c9ece7f264c9fd66335d8"><td class="memItemLeft" align="right" valign="top"><a id="a6c30db65be1c9ece7f264c9fd66335d8"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA30C_SERCOM7_PAD2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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||
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<tr class="separator:a6c30db65be1c9ece7f264c9fd66335d8"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a923eb70a7ff97ab20dc507acf5eb1da5"><td class="memItemLeft" align="right" valign="top"><a id="a923eb70a7ff97ab20dc507acf5eb1da5"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA30C_SERCOM7_PAD2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a016b93cd689a15f8bca86b848da12cf5">PIN_PA30C_SERCOM7_PAD2</a> << 16) | MUX_PA30C_SERCOM7_PAD2)</td></tr>
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<tr class="separator:a923eb70a7ff97ab20dc507acf5eb1da5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7750e4fc0a642a5009f1e429974ef136"><td class="memItemLeft" align="right" valign="top"><a id="a7750e4fc0a642a5009f1e429974ef136"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA30C_SERCOM7_PAD2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 30)</td></tr>
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||
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<tr class="separator:a7750e4fc0a642a5009f1e429974ef136"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a59f36df94d518fb2b35179e75c03b340"><td class="memItemLeft" align="right" valign="top"><a id="a59f36df94d518fb2b35179e75c03b340"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a59f36df94d518fb2b35179e75c03b340">PIN_PB19D_SERCOM7_PAD3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(51)</td></tr>
|
||
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<tr class="memdesc:a59f36df94d518fb2b35179e75c03b340"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM7 signal: PAD3 on PB19 mux D. <br /></td></tr>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB19D_SERCOM7_PAD3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="memitem:a49386438f9f9409f933a154051651753"><td class="memItemLeft" align="right" valign="top"><a id="a49386438f9f9409f933a154051651753"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB19D_SERCOM7_PAD3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a59f36df94d518fb2b35179e75c03b340">PIN_PB19D_SERCOM7_PAD3</a> << 16) | MUX_PB19D_SERCOM7_PAD3)</td></tr>
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<tr class="memitem:a02d77db93dac5f5019e08068ddb45560"><td class="memItemLeft" align="right" valign="top"><a id="a02d77db93dac5f5019e08068ddb45560"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB19D_SERCOM7_PAD3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 19)</td></tr>
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<tr class="memitem:a9177b92af11ad6d206f1c9ac42c6eb23"><td class="memItemLeft" align="right" valign="top"><a id="a9177b92af11ad6d206f1c9ac42c6eb23"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a9177b92af11ad6d206f1c9ac42c6eb23">PIN_PC11D_SERCOM7_PAD3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(75)</td></tr>
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<tr class="memdesc:a9177b92af11ad6d206f1c9ac42c6eb23"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM7 signal: PAD3 on PC11 mux D. <br /></td></tr>
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<tr class="separator:a9177b92af11ad6d206f1c9ac42c6eb23"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0ad0be00f246c969f8ecd0fc0a820f6a"><td class="memItemLeft" align="right" valign="top"><a id="a0ad0be00f246c969f8ecd0fc0a820f6a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC11D_SERCOM7_PAD3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="separator:a0ad0be00f246c969f8ecd0fc0a820f6a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad5767c29fd1f3c077a8b98856ea7ecc4"><td class="memItemLeft" align="right" valign="top"><a id="ad5767c29fd1f3c077a8b98856ea7ecc4"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC11D_SERCOM7_PAD3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a9177b92af11ad6d206f1c9ac42c6eb23">PIN_PC11D_SERCOM7_PAD3</a> << 16) | MUX_PC11D_SERCOM7_PAD3)</td></tr>
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<tr class="separator:ad5767c29fd1f3c077a8b98856ea7ecc4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9ccce94a7787a3a80dae671045b513f2"><td class="memItemLeft" align="right" valign="top"><a id="a9ccce94a7787a3a80dae671045b513f2"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC11D_SERCOM7_PAD3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 11)</td></tr>
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<tr class="separator:a9ccce94a7787a3a80dae671045b513f2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9b9e4938d5438d890a9b7bffe681a2ce"><td class="memItemLeft" align="right" valign="top"><a id="a9b9e4938d5438d890a9b7bffe681a2ce"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a9b9e4938d5438d890a9b7bffe681a2ce">PIN_PC15C_SERCOM7_PAD3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(79)</td></tr>
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||
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<tr class="memdesc:a9b9e4938d5438d890a9b7bffe681a2ce"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM7 signal: PAD3 on PC15 mux C. <br /></td></tr>
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<tr class="separator:a9b9e4938d5438d890a9b7bffe681a2ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aab13516f8f64f128603bd50e7446bf93"><td class="memItemLeft" align="right" valign="top"><a id="aab13516f8f64f128603bd50e7446bf93"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC15C_SERCOM7_PAD3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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<tr class="separator:aab13516f8f64f128603bd50e7446bf93"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae41c99bfd67d1a311a3be3592d5d0037"><td class="memItemLeft" align="right" valign="top"><a id="ae41c99bfd67d1a311a3be3592d5d0037"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC15C_SERCOM7_PAD3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a9b9e4938d5438d890a9b7bffe681a2ce">PIN_PC15C_SERCOM7_PAD3</a> << 16) | MUX_PC15C_SERCOM7_PAD3)</td></tr>
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<tr class="memitem:a9ee6362595418bad7e404aad487f0c65"><td class="memItemLeft" align="right" valign="top"><a id="a9ee6362595418bad7e404aad487f0c65"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC15C_SERCOM7_PAD3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 15)</td></tr>
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<tr class="separator:a9ee6362595418bad7e404aad487f0c65"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a196a0ea737307d8b617352b5dd2503f6"><td class="memItemLeft" align="right" valign="top"><a id="a196a0ea737307d8b617352b5dd2503f6"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a196a0ea737307d8b617352b5dd2503f6">PIN_PA31C_SERCOM7_PAD3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(31)</td></tr>
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||
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<tr class="memdesc:a196a0ea737307d8b617352b5dd2503f6"><td class="mdescLeft"> </td><td class="mdescRight">SERCOM7 signal: PAD3 on PA31 mux C. <br /></td></tr>
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<tr class="separator:a196a0ea737307d8b617352b5dd2503f6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3ddcdc6d90eedf6978331223a69e6326"><td class="memItemLeft" align="right" valign="top"><a id="a3ddcdc6d90eedf6978331223a69e6326"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA31C_SERCOM7_PAD3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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<tr class="separator:a3ddcdc6d90eedf6978331223a69e6326"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa79686fa709c273f7ee9b7bf20542695"><td class="memItemLeft" align="right" valign="top"><a id="aa79686fa709c273f7ee9b7bf20542695"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA31C_SERCOM7_PAD3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a196a0ea737307d8b617352b5dd2503f6">PIN_PA31C_SERCOM7_PAD3</a> << 16) | MUX_PA31C_SERCOM7_PAD3)</td></tr>
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<tr class="separator:aa79686fa709c273f7ee9b7bf20542695"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a85db9e1b0f2443fb73b3c100930603ed"><td class="memItemLeft" align="right" valign="top"><a id="a85db9e1b0f2443fb73b3c100930603ed"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA31C_SERCOM7_PAD3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 31)</td></tr>
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<tr class="separator:a85db9e1b0f2443fb73b3c100930603ed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae988325384408db165a231fb1714dfb0"><td class="memItemLeft" align="right" valign="top"><a id="ae988325384408db165a231fb1714dfb0"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae988325384408db165a231fb1714dfb0">PIN_PB14F_TCC4_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(46)</td></tr>
|
||
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<tr class="memdesc:ae988325384408db165a231fb1714dfb0"><td class="mdescLeft"> </td><td class="mdescRight">TCC4 signal: WO0 on PB14 mux F. <br /></td></tr>
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<tr class="separator:ae988325384408db165a231fb1714dfb0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0df73af1a2948b267938b49befbd7c99"><td class="memItemLeft" align="right" valign="top"><a id="a0df73af1a2948b267938b49befbd7c99"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB14F_TCC4_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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<tr class="separator:a0df73af1a2948b267938b49befbd7c99"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8c520c799b595423f8090d0c645264e2"><td class="memItemLeft" align="right" valign="top"><a id="a8c520c799b595423f8090d0c645264e2"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB14F_TCC4_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ae988325384408db165a231fb1714dfb0">PIN_PB14F_TCC4_WO0</a> << 16) | MUX_PB14F_TCC4_WO0)</td></tr>
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<tr class="separator:a8c520c799b595423f8090d0c645264e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:add226e195cc3d43b92152754d6a70876"><td class="memItemLeft" align="right" valign="top"><a id="add226e195cc3d43b92152754d6a70876"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB14F_TCC4_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 14)</td></tr>
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<tr class="separator:add226e195cc3d43b92152754d6a70876"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3d90fbe7aea60b2600f58785ec219362"><td class="memItemLeft" align="right" valign="top"><a id="a3d90fbe7aea60b2600f58785ec219362"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3d90fbe7aea60b2600f58785ec219362">PIN_PB30F_TCC4_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(62)</td></tr>
|
||
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<tr class="memdesc:a3d90fbe7aea60b2600f58785ec219362"><td class="mdescLeft"> </td><td class="mdescRight">TCC4 signal: WO0 on PB30 mux F. <br /></td></tr>
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<tr class="separator:a3d90fbe7aea60b2600f58785ec219362"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a55e8d5c3e8e717c1d904e0b20358e612"><td class="memItemLeft" align="right" valign="top"><a id="a55e8d5c3e8e717c1d904e0b20358e612"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB30F_TCC4_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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<tr class="separator:a55e8d5c3e8e717c1d904e0b20358e612"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a78ac437158ccb4c92726abfb9d3062ad"><td class="memItemLeft" align="right" valign="top"><a id="a78ac437158ccb4c92726abfb9d3062ad"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB30F_TCC4_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a3d90fbe7aea60b2600f58785ec219362">PIN_PB30F_TCC4_WO0</a> << 16) | MUX_PB30F_TCC4_WO0)</td></tr>
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<tr class="separator:a78ac437158ccb4c92726abfb9d3062ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af5421e888ae9961e796af85fb99ab361"><td class="memItemLeft" align="right" valign="top"><a id="af5421e888ae9961e796af85fb99ab361"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB30F_TCC4_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 30)</td></tr>
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||
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<tr class="separator:af5421e888ae9961e796af85fb99ab361"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2defb6a1a5fce170627d89725dde4e33"><td class="memItemLeft" align="right" valign="top"><a id="a2defb6a1a5fce170627d89725dde4e33"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2defb6a1a5fce170627d89725dde4e33">PIN_PB15F_TCC4_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(47)</td></tr>
|
||
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<tr class="memdesc:a2defb6a1a5fce170627d89725dde4e33"><td class="mdescLeft"> </td><td class="mdescRight">TCC4 signal: WO1 on PB15 mux F. <br /></td></tr>
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<tr class="separator:a2defb6a1a5fce170627d89725dde4e33"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1e83953c1c28bb2ed9958d034505aacb"><td class="memItemLeft" align="right" valign="top"><a id="a1e83953c1c28bb2ed9958d034505aacb"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB15F_TCC4_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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||
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<tr class="separator:a1e83953c1c28bb2ed9958d034505aacb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af5b38b202308e408a6a8e797ac958315"><td class="memItemLeft" align="right" valign="top"><a id="af5b38b202308e408a6a8e797ac958315"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB15F_TCC4_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a2defb6a1a5fce170627d89725dde4e33">PIN_PB15F_TCC4_WO1</a> << 16) | MUX_PB15F_TCC4_WO1)</td></tr>
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<tr class="separator:af5b38b202308e408a6a8e797ac958315"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a81a113f2d5af593b3d5bd518b1d8a296"><td class="memItemLeft" align="right" valign="top"><a id="a81a113f2d5af593b3d5bd518b1d8a296"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB15F_TCC4_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 15)</td></tr>
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||
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<tr class="separator:a81a113f2d5af593b3d5bd518b1d8a296"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a45c558122b07ae69d598a702e9bcee37"><td class="memItemLeft" align="right" valign="top"><a id="a45c558122b07ae69d598a702e9bcee37"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a45c558122b07ae69d598a702e9bcee37">PIN_PB31F_TCC4_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(63)</td></tr>
|
||
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<tr class="memdesc:a45c558122b07ae69d598a702e9bcee37"><td class="mdescLeft"> </td><td class="mdescRight">TCC4 signal: WO1 on PB31 mux F. <br /></td></tr>
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<tr class="separator:a45c558122b07ae69d598a702e9bcee37"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7c5b0955b19621b507719c563c85c9ca"><td class="memItemLeft" align="right" valign="top"><a id="a7c5b0955b19621b507719c563c85c9ca"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB31F_TCC4_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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<tr class="separator:a7c5b0955b19621b507719c563c85c9ca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a64a48c733cb239d196eedc1a0048865b"><td class="memItemLeft" align="right" valign="top"><a id="a64a48c733cb239d196eedc1a0048865b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB31F_TCC4_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a45c558122b07ae69d598a702e9bcee37">PIN_PB31F_TCC4_WO1</a> << 16) | MUX_PB31F_TCC4_WO1)</td></tr>
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<tr class="memitem:a6f1f2beecb9a4a5a3b0f223172eea149"><td class="memItemLeft" align="right" valign="top"><a id="a6f1f2beecb9a4a5a3b0f223172eea149"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB31F_TCC4_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 31)</td></tr>
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<tr class="separator:a6f1f2beecb9a4a5a3b0f223172eea149"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a60153ed79d737b70bdb687ce107e9716"><td class="memItemLeft" align="right" valign="top"><a id="a60153ed79d737b70bdb687ce107e9716"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a60153ed79d737b70bdb687ce107e9716">PIN_PA30E_TC6_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(30)</td></tr>
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<tr class="memdesc:a60153ed79d737b70bdb687ce107e9716"><td class="mdescLeft"> </td><td class="mdescRight">TC6 signal: WO0 on PA30 mux E. <br /></td></tr>
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<tr class="separator:a60153ed79d737b70bdb687ce107e9716"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1bbd04b87565171442d10a9b52b70b8d"><td class="memItemLeft" align="right" valign="top"><a id="a1bbd04b87565171442d10a9b52b70b8d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA30E_TC6_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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<tr class="separator:a1bbd04b87565171442d10a9b52b70b8d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae7f05554daad55d6f400e16905a3e6dc"><td class="memItemLeft" align="right" valign="top"><a id="ae7f05554daad55d6f400e16905a3e6dc"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA30E_TC6_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a60153ed79d737b70bdb687ce107e9716">PIN_PA30E_TC6_WO0</a> << 16) | MUX_PA30E_TC6_WO0)</td></tr>
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<tr class="separator:ae7f05554daad55d6f400e16905a3e6dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0554c56333097e41a9beb59b4d1bfa5e"><td class="memItemLeft" align="right" valign="top"><a id="a0554c56333097e41a9beb59b4d1bfa5e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA30E_TC6_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 30)</td></tr>
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<tr class="separator:a0554c56333097e41a9beb59b4d1bfa5e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a89450ffd1e32e588e58d3a4c2f97d7b4"><td class="memItemLeft" align="right" valign="top"><a id="a89450ffd1e32e588e58d3a4c2f97d7b4"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a89450ffd1e32e588e58d3a4c2f97d7b4">PIN_PB02E_TC6_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(34)</td></tr>
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||
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<tr class="memdesc:a89450ffd1e32e588e58d3a4c2f97d7b4"><td class="mdescLeft"> </td><td class="mdescRight">TC6 signal: WO0 on PB02 mux E. <br /></td></tr>
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<tr class="separator:a89450ffd1e32e588e58d3a4c2f97d7b4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a335485d7f34d2e34ce5c00dc9bfb38eb"><td class="memItemLeft" align="right" valign="top"><a id="a335485d7f34d2e34ce5c00dc9bfb38eb"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB02E_TC6_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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<tr class="separator:a335485d7f34d2e34ce5c00dc9bfb38eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a51cfc2e2d80835238970f5d896a35dda"><td class="memItemLeft" align="right" valign="top"><a id="a51cfc2e2d80835238970f5d896a35dda"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB02E_TC6_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a89450ffd1e32e588e58d3a4c2f97d7b4">PIN_PB02E_TC6_WO0</a> << 16) | MUX_PB02E_TC6_WO0)</td></tr>
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<tr class="separator:a51cfc2e2d80835238970f5d896a35dda"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afb36e5d167d309a035b292338a7df814"><td class="memItemLeft" align="right" valign="top"><a id="afb36e5d167d309a035b292338a7df814"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB02E_TC6_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 2)</td></tr>
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||
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<tr class="separator:afb36e5d167d309a035b292338a7df814"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5e9fd9977e3bf3333aa0fe0590dc7ea7"><td class="memItemLeft" align="right" valign="top"><a id="a5e9fd9977e3bf3333aa0fe0590dc7ea7"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5e9fd9977e3bf3333aa0fe0590dc7ea7">PIN_PB16E_TC6_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(48)</td></tr>
|
||
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<tr class="memdesc:a5e9fd9977e3bf3333aa0fe0590dc7ea7"><td class="mdescLeft"> </td><td class="mdescRight">TC6 signal: WO0 on PB16 mux E. <br /></td></tr>
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<tr class="separator:a5e9fd9977e3bf3333aa0fe0590dc7ea7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac67224ac24e7ace8852c735123db9c63"><td class="memItemLeft" align="right" valign="top"><a id="ac67224ac24e7ace8852c735123db9c63"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB16E_TC6_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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||
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<tr class="separator:ac67224ac24e7ace8852c735123db9c63"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aaa09d12a70a1e266a776103dcc0c61da"><td class="memItemLeft" align="right" valign="top"><a id="aaa09d12a70a1e266a776103dcc0c61da"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB16E_TC6_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a5e9fd9977e3bf3333aa0fe0590dc7ea7">PIN_PB16E_TC6_WO0</a> << 16) | MUX_PB16E_TC6_WO0)</td></tr>
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<tr class="separator:aaa09d12a70a1e266a776103dcc0c61da"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a462e7927846a291fe6dc6b90ef2740db"><td class="memItemLeft" align="right" valign="top"><a id="a462e7927846a291fe6dc6b90ef2740db"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB16E_TC6_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 16)</td></tr>
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||
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<tr class="separator:a462e7927846a291fe6dc6b90ef2740db"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae1b6e38dcbfc35e131f6e63f3945b0eb"><td class="memItemLeft" align="right" valign="top"><a id="ae1b6e38dcbfc35e131f6e63f3945b0eb"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae1b6e38dcbfc35e131f6e63f3945b0eb">PIN_PA31E_TC6_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(31)</td></tr>
|
||
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<tr class="memdesc:ae1b6e38dcbfc35e131f6e63f3945b0eb"><td class="mdescLeft"> </td><td class="mdescRight">TC6 signal: WO1 on PA31 mux E. <br /></td></tr>
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<tr class="separator:ae1b6e38dcbfc35e131f6e63f3945b0eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4e8c55e2a90d2dfe4b0fa6a02ccb6c13"><td class="memItemLeft" align="right" valign="top"><a id="a4e8c55e2a90d2dfe4b0fa6a02ccb6c13"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA31E_TC6_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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||
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<tr class="separator:a4e8c55e2a90d2dfe4b0fa6a02ccb6c13"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1b6f0f70665a2ff2aa6197c93f71e8ea"><td class="memItemLeft" align="right" valign="top"><a id="a1b6f0f70665a2ff2aa6197c93f71e8ea"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA31E_TC6_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ae1b6e38dcbfc35e131f6e63f3945b0eb">PIN_PA31E_TC6_WO1</a> << 16) | MUX_PA31E_TC6_WO1)</td></tr>
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<tr class="separator:a1b6f0f70665a2ff2aa6197c93f71e8ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a028791f322693da48cf3008cba5fefbb"><td class="memItemLeft" align="right" valign="top"><a id="a028791f322693da48cf3008cba5fefbb"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA31E_TC6_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 31)</td></tr>
|
||
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<tr class="separator:a028791f322693da48cf3008cba5fefbb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a736f98c161da8fef1fb8087a188d243d"><td class="memItemLeft" align="right" valign="top"><a id="a736f98c161da8fef1fb8087a188d243d"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a736f98c161da8fef1fb8087a188d243d">PIN_PB03E_TC6_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(35)</td></tr>
|
||
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<tr class="memdesc:a736f98c161da8fef1fb8087a188d243d"><td class="mdescLeft"> </td><td class="mdescRight">TC6 signal: WO1 on PB03 mux E. <br /></td></tr>
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<tr class="separator:a736f98c161da8fef1fb8087a188d243d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac6e26e387280a981122aaafe807aafc4"><td class="memItemLeft" align="right" valign="top"><a id="ac6e26e387280a981122aaafe807aafc4"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB03E_TC6_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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||
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<tr class="separator:ac6e26e387280a981122aaafe807aafc4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a703285f8061e59e447973eb6547be57c"><td class="memItemLeft" align="right" valign="top"><a id="a703285f8061e59e447973eb6547be57c"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB03E_TC6_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a736f98c161da8fef1fb8087a188d243d">PIN_PB03E_TC6_WO1</a> << 16) | MUX_PB03E_TC6_WO1)</td></tr>
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<tr class="separator:a703285f8061e59e447973eb6547be57c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a696a0a6559329e5e904b6ad281ecd368"><td class="memItemLeft" align="right" valign="top"><a id="a696a0a6559329e5e904b6ad281ecd368"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB03E_TC6_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 3)</td></tr>
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||
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<tr class="separator:a696a0a6559329e5e904b6ad281ecd368"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8126fc0f4d180275a7e4c3aef91e2269"><td class="memItemLeft" align="right" valign="top"><a id="a8126fc0f4d180275a7e4c3aef91e2269"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8126fc0f4d180275a7e4c3aef91e2269">PIN_PB17E_TC6_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(49)</td></tr>
|
||
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<tr class="memdesc:a8126fc0f4d180275a7e4c3aef91e2269"><td class="mdescLeft"> </td><td class="mdescRight">TC6 signal: WO1 on PB17 mux E. <br /></td></tr>
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<tr class="separator:a8126fc0f4d180275a7e4c3aef91e2269"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a34fecf9635adf172b199a2b59de0a7dc"><td class="memItemLeft" align="right" valign="top"><a id="a34fecf9635adf172b199a2b59de0a7dc"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB17E_TC6_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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||
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<tr class="separator:a34fecf9635adf172b199a2b59de0a7dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8587df1c24e048ac56fba5ca6f250868"><td class="memItemLeft" align="right" valign="top"><a id="a8587df1c24e048ac56fba5ca6f250868"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB17E_TC6_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a8126fc0f4d180275a7e4c3aef91e2269">PIN_PB17E_TC6_WO1</a> << 16) | MUX_PB17E_TC6_WO1)</td></tr>
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<tr class="separator:a8587df1c24e048ac56fba5ca6f250868"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ace5ee076c0ab8e16600320f69a92c009"><td class="memItemLeft" align="right" valign="top"><a id="ace5ee076c0ab8e16600320f69a92c009"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB17E_TC6_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 17)</td></tr>
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||
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<tr class="separator:ace5ee076c0ab8e16600320f69a92c009"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5ed47c4c324e78f4d390de181498d172"><td class="memItemLeft" align="right" valign="top"><a id="a5ed47c4c324e78f4d390de181498d172"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5ed47c4c324e78f4d390de181498d172">PIN_PA20E_TC7_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(20)</td></tr>
|
||
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<tr class="memdesc:a5ed47c4c324e78f4d390de181498d172"><td class="mdescLeft"> </td><td class="mdescRight">TC7 signal: WO0 on PA20 mux E. <br /></td></tr>
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<tr class="separator:a5ed47c4c324e78f4d390de181498d172"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3efaad1fe644b3a0902717cc19ffb391"><td class="memItemLeft" align="right" valign="top"><a id="a3efaad1fe644b3a0902717cc19ffb391"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA20E_TC7_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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||
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<tr class="separator:a3efaad1fe644b3a0902717cc19ffb391"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afdaee8d6f05126c95b1634176186bd3d"><td class="memItemLeft" align="right" valign="top"><a id="afdaee8d6f05126c95b1634176186bd3d"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA20E_TC7_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a5ed47c4c324e78f4d390de181498d172">PIN_PA20E_TC7_WO0</a> << 16) | MUX_PA20E_TC7_WO0)</td></tr>
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<tr class="separator:afdaee8d6f05126c95b1634176186bd3d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3857476abb033022e33b0b4933a255f2"><td class="memItemLeft" align="right" valign="top"><a id="a3857476abb033022e33b0b4933a255f2"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA20E_TC7_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 20)</td></tr>
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<tr class="memitem:ae6ca0cdff6526b2875f7daa54c28c43b"><td class="memItemLeft" align="right" valign="top"><a id="ae6ca0cdff6526b2875f7daa54c28c43b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae6ca0cdff6526b2875f7daa54c28c43b">PIN_PB00E_TC7_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(32)</td></tr>
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<tr class="memdesc:ae6ca0cdff6526b2875f7daa54c28c43b"><td class="mdescLeft"> </td><td class="mdescRight">TC7 signal: WO0 on PB00 mux E. <br /></td></tr>
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<tr class="separator:ae6ca0cdff6526b2875f7daa54c28c43b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6300001689d0d134236b4f94d5da8a86"><td class="memItemLeft" align="right" valign="top"><a id="a6300001689d0d134236b4f94d5da8a86"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB00E_TC7_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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<tr class="separator:a6300001689d0d134236b4f94d5da8a86"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2d9d909e73f0334ecd61b27c5bbf8d0d"><td class="memItemLeft" align="right" valign="top"><a id="a2d9d909e73f0334ecd61b27c5bbf8d0d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB00E_TC7_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ae6ca0cdff6526b2875f7daa54c28c43b">PIN_PB00E_TC7_WO0</a> << 16) | MUX_PB00E_TC7_WO0)</td></tr>
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<tr class="separator:a2d9d909e73f0334ecd61b27c5bbf8d0d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae7f5dbf0eaba6c4bc2079d39e250ba5a"><td class="memItemLeft" align="right" valign="top"><a id="ae7f5dbf0eaba6c4bc2079d39e250ba5a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB00E_TC7_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 0)</td></tr>
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<tr class="separator:ae7f5dbf0eaba6c4bc2079d39e250ba5a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8b7186e321d915f19f227b0821d12a86"><td class="memItemLeft" align="right" valign="top"><a id="a8b7186e321d915f19f227b0821d12a86"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8b7186e321d915f19f227b0821d12a86">PIN_PB22E_TC7_WO0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(54)</td></tr>
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<tr class="memdesc:a8b7186e321d915f19f227b0821d12a86"><td class="mdescLeft"> </td><td class="mdescRight">TC7 signal: WO0 on PB22 mux E. <br /></td></tr>
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<tr class="separator:a8b7186e321d915f19f227b0821d12a86"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a28597f9087b9644b03a78cc27988363a"><td class="memItemLeft" align="right" valign="top"><a id="a28597f9087b9644b03a78cc27988363a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB22E_TC7_WO0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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<tr class="separator:a28597f9087b9644b03a78cc27988363a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a85e5de4def6ddecd5e92cb2dead57aa7"><td class="memItemLeft" align="right" valign="top"><a id="a85e5de4def6ddecd5e92cb2dead57aa7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB22E_TC7_WO0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a8b7186e321d915f19f227b0821d12a86">PIN_PB22E_TC7_WO0</a> << 16) | MUX_PB22E_TC7_WO0)</td></tr>
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<tr class="separator:a85e5de4def6ddecd5e92cb2dead57aa7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0771fce2d1afebcf0f48894390db2ac2"><td class="memItemLeft" align="right" valign="top"><a id="a0771fce2d1afebcf0f48894390db2ac2"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB22E_TC7_WO0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 22)</td></tr>
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<tr class="separator:a0771fce2d1afebcf0f48894390db2ac2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3d2eb46dffd583f9060dac1f53fa0efb"><td class="memItemLeft" align="right" valign="top"><a id="a3d2eb46dffd583f9060dac1f53fa0efb"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3d2eb46dffd583f9060dac1f53fa0efb">PIN_PA21E_TC7_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(21)</td></tr>
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||
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<tr class="memdesc:a3d2eb46dffd583f9060dac1f53fa0efb"><td class="mdescLeft"> </td><td class="mdescRight">TC7 signal: WO1 on PA21 mux E. <br /></td></tr>
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<tr class="separator:a3d2eb46dffd583f9060dac1f53fa0efb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4e748207dc108b74b726bd8c9c4a7a0d"><td class="memItemLeft" align="right" valign="top"><a id="a4e748207dc108b74b726bd8c9c4a7a0d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA21E_TC7_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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<tr class="separator:a4e748207dc108b74b726bd8c9c4a7a0d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1e873b5b90b80096de23da63bdeaedd5"><td class="memItemLeft" align="right" valign="top"><a id="a1e873b5b90b80096de23da63bdeaedd5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA21E_TC7_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a3d2eb46dffd583f9060dac1f53fa0efb">PIN_PA21E_TC7_WO1</a> << 16) | MUX_PA21E_TC7_WO1)</td></tr>
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<tr class="separator:a1e873b5b90b80096de23da63bdeaedd5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1ad21851eedb509f361db8fdc5216295"><td class="memItemLeft" align="right" valign="top"><a id="a1ad21851eedb509f361db8fdc5216295"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA21E_TC7_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 21)</td></tr>
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||
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<tr class="separator:a1ad21851eedb509f361db8fdc5216295"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a277b372d1c6db240f7c21f54e4c53a92"><td class="memItemLeft" align="right" valign="top"><a id="a277b372d1c6db240f7c21f54e4c53a92"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a277b372d1c6db240f7c21f54e4c53a92">PIN_PB01E_TC7_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(33)</td></tr>
|
||
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<tr class="memdesc:a277b372d1c6db240f7c21f54e4c53a92"><td class="mdescLeft"> </td><td class="mdescRight">TC7 signal: WO1 on PB01 mux E. <br /></td></tr>
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<tr class="separator:a277b372d1c6db240f7c21f54e4c53a92"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5227b2910571a20a5b54aebaa59aa95a"><td class="memItemLeft" align="right" valign="top"><a id="a5227b2910571a20a5b54aebaa59aa95a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB01E_TC7_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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<tr class="separator:a5227b2910571a20a5b54aebaa59aa95a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6371dce5ca2358986ec223997228e0f5"><td class="memItemLeft" align="right" valign="top"><a id="a6371dce5ca2358986ec223997228e0f5"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB01E_TC7_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a277b372d1c6db240f7c21f54e4c53a92">PIN_PB01E_TC7_WO1</a> << 16) | MUX_PB01E_TC7_WO1)</td></tr>
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<tr class="separator:a6371dce5ca2358986ec223997228e0f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af766f851b8486b219c39a2cf0122f2dc"><td class="memItemLeft" align="right" valign="top"><a id="af766f851b8486b219c39a2cf0122f2dc"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB01E_TC7_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 1)</td></tr>
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||
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<tr class="separator:af766f851b8486b219c39a2cf0122f2dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac37fae76336321409e8f41d1be7e6f13"><td class="memItemLeft" align="right" valign="top"><a id="ac37fae76336321409e8f41d1be7e6f13"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac37fae76336321409e8f41d1be7e6f13">PIN_PB23E_TC7_WO1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(55)</td></tr>
|
||
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<tr class="memdesc:ac37fae76336321409e8f41d1be7e6f13"><td class="mdescLeft"> </td><td class="mdescRight">TC7 signal: WO1 on PB23 mux E. <br /></td></tr>
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<tr class="separator:ac37fae76336321409e8f41d1be7e6f13"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a760513bc13de616bdafac56c359a11f1"><td class="memItemLeft" align="right" valign="top"><a id="a760513bc13de616bdafac56c359a11f1"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB23E_TC7_WO1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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<tr class="separator:a760513bc13de616bdafac56c359a11f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0848c36d16fe711d018547b26cb9a78a"><td class="memItemLeft" align="right" valign="top"><a id="a0848c36d16fe711d018547b26cb9a78a"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB23E_TC7_WO1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ac37fae76336321409e8f41d1be7e6f13">PIN_PB23E_TC7_WO1</a> << 16) | MUX_PB23E_TC7_WO1)</td></tr>
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<tr class="separator:a0848c36d16fe711d018547b26cb9a78a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a41587aaaab40a0052274e302d8770dfa"><td class="memItemLeft" align="right" valign="top"><a id="a41587aaaab40a0052274e302d8770dfa"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB23E_TC7_WO1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 23)</td></tr>
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<tr class="separator:a41587aaaab40a0052274e302d8770dfa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a55aa8756eecc8c65d6c95d39bbd66286"><td class="memItemLeft" align="right" valign="top"><a id="a55aa8756eecc8c65d6c95d39bbd66286"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a55aa8756eecc8c65d6c95d39bbd66286">PIN_PA02B_ADC0_AIN0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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||
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<tr class="memdesc:a55aa8756eecc8c65d6c95d39bbd66286"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: AIN0 on PA02 mux B. <br /></td></tr>
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<tr class="separator:a55aa8756eecc8c65d6c95d39bbd66286"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4ad4ee795e1cc4e063b96039106b034d"><td class="memItemLeft" align="right" valign="top"><a id="a4ad4ee795e1cc4e063b96039106b034d"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA02B_ADC0_AIN0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:a4ad4ee795e1cc4e063b96039106b034d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a06bad0f033e3da8bb57e544a1823c07e"><td class="memItemLeft" align="right" valign="top"><a id="a06bad0f033e3da8bb57e544a1823c07e"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA02B_ADC0_AIN0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a55aa8756eecc8c65d6c95d39bbd66286">PIN_PA02B_ADC0_AIN0</a> << 16) | MUX_PA02B_ADC0_AIN0)</td></tr>
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<tr class="separator:a06bad0f033e3da8bb57e544a1823c07e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afeb84ddf7a1b207a68ce8f8de2a6eb4c"><td class="memItemLeft" align="right" valign="top"><a id="afeb84ddf7a1b207a68ce8f8de2a6eb4c"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA02B_ADC0_AIN0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 2)</td></tr>
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||
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<tr class="separator:afeb84ddf7a1b207a68ce8f8de2a6eb4c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adb81a4cb3598f661d6c9fb07e3b4e5e0"><td class="memItemLeft" align="right" valign="top"><a id="adb81a4cb3598f661d6c9fb07e3b4e5e0"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#adb81a4cb3598f661d6c9fb07e3b4e5e0">PIN_PA03B_ADC0_AIN1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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||
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<tr class="memdesc:adb81a4cb3598f661d6c9fb07e3b4e5e0"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: AIN1 on PA03 mux B. <br /></td></tr>
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<tr class="separator:adb81a4cb3598f661d6c9fb07e3b4e5e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adfc69ec155a57b29922b660ce30b8584"><td class="memItemLeft" align="right" valign="top"><a id="adfc69ec155a57b29922b660ce30b8584"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA03B_ADC0_AIN1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:adfc69ec155a57b29922b660ce30b8584"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a89f1e1e80a939a121d064b9922fdf708"><td class="memItemLeft" align="right" valign="top"><a id="a89f1e1e80a939a121d064b9922fdf708"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA03B_ADC0_AIN1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#adb81a4cb3598f661d6c9fb07e3b4e5e0">PIN_PA03B_ADC0_AIN1</a> << 16) | MUX_PA03B_ADC0_AIN1)</td></tr>
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<tr class="separator:a89f1e1e80a939a121d064b9922fdf708"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acf8dd0be4be229abf3b5f764d83f58d3"><td class="memItemLeft" align="right" valign="top"><a id="acf8dd0be4be229abf3b5f764d83f58d3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA03B_ADC0_AIN1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 3)</td></tr>
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<tr class="separator:acf8dd0be4be229abf3b5f764d83f58d3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2ff39fa0925103b3cb98db8ecf0a395c"><td class="memItemLeft" align="right" valign="top"><a id="a2ff39fa0925103b3cb98db8ecf0a395c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2ff39fa0925103b3cb98db8ecf0a395c">PIN_PB08B_ADC0_AIN2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(40)</td></tr>
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<tr class="memdesc:a2ff39fa0925103b3cb98db8ecf0a395c"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: AIN2 on PB08 mux B. <br /></td></tr>
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<tr class="memitem:a59a9bb0df8bb0e8744b8a20f54dcbdf3"><td class="memItemLeft" align="right" valign="top"><a id="a59a9bb0df8bb0e8744b8a20f54dcbdf3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB08B_ADC0_AIN2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="memitem:a0104c372f052a96e1da54143ae97a48e"><td class="memItemLeft" align="right" valign="top"><a id="a0104c372f052a96e1da54143ae97a48e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB08B_ADC0_AIN2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a2ff39fa0925103b3cb98db8ecf0a395c">PIN_PB08B_ADC0_AIN2</a> << 16) | MUX_PB08B_ADC0_AIN2)</td></tr>
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<tr class="memitem:a1a672576589e1cfd930de43ca0af4793"><td class="memItemLeft" align="right" valign="top"><a id="a1a672576589e1cfd930de43ca0af4793"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB08B_ADC0_AIN2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 8)</td></tr>
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<tr class="separator:a1a672576589e1cfd930de43ca0af4793"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a344be42bc25dfe9da3a92e6be8e22388"><td class="memItemLeft" align="right" valign="top"><a id="a344be42bc25dfe9da3a92e6be8e22388"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a344be42bc25dfe9da3a92e6be8e22388">PIN_PB09B_ADC0_AIN3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(41)</td></tr>
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<tr class="memdesc:a344be42bc25dfe9da3a92e6be8e22388"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: AIN3 on PB09 mux B. <br /></td></tr>
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<tr class="separator:a344be42bc25dfe9da3a92e6be8e22388"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1825fb932f26ed68b0c6bfae6a0a47a8"><td class="memItemLeft" align="right" valign="top"><a id="a1825fb932f26ed68b0c6bfae6a0a47a8"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB09B_ADC0_AIN3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:a1825fb932f26ed68b0c6bfae6a0a47a8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a63a1083dc95b7da3e80245e1ef71e80e"><td class="memItemLeft" align="right" valign="top"><a id="a63a1083dc95b7da3e80245e1ef71e80e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB09B_ADC0_AIN3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a344be42bc25dfe9da3a92e6be8e22388">PIN_PB09B_ADC0_AIN3</a> << 16) | MUX_PB09B_ADC0_AIN3)</td></tr>
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<tr class="separator:a63a1083dc95b7da3e80245e1ef71e80e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5cbfd93c3c0b8103b3f7e1d721c41f16"><td class="memItemLeft" align="right" valign="top"><a id="a5cbfd93c3c0b8103b3f7e1d721c41f16"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB09B_ADC0_AIN3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 9)</td></tr>
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<tr class="separator:a5cbfd93c3c0b8103b3f7e1d721c41f16"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae7658465a04a6228aff76a710fbb9e70"><td class="memItemLeft" align="right" valign="top"><a id="ae7658465a04a6228aff76a710fbb9e70"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae7658465a04a6228aff76a710fbb9e70">PIN_PA04B_ADC0_AIN4</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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<tr class="memdesc:ae7658465a04a6228aff76a710fbb9e70"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: AIN4 on PA04 mux B. <br /></td></tr>
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<tr class="separator:ae7658465a04a6228aff76a710fbb9e70"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aea5268e43b82f6dd8703852d6f56d1b2"><td class="memItemLeft" align="right" valign="top"><a id="aea5268e43b82f6dd8703852d6f56d1b2"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA04B_ADC0_AIN4</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:aea5268e43b82f6dd8703852d6f56d1b2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4545df02f48ce828b2db84ca92cbcf15"><td class="memItemLeft" align="right" valign="top"><a id="a4545df02f48ce828b2db84ca92cbcf15"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA04B_ADC0_AIN4</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ae7658465a04a6228aff76a710fbb9e70">PIN_PA04B_ADC0_AIN4</a> << 16) | MUX_PA04B_ADC0_AIN4)</td></tr>
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<tr class="separator:a4545df02f48ce828b2db84ca92cbcf15"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a764cd1576ebeadb30f8ed60257a61373"><td class="memItemLeft" align="right" valign="top"><a id="a764cd1576ebeadb30f8ed60257a61373"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA04B_ADC0_AIN4</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 4)</td></tr>
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<tr class="separator:a764cd1576ebeadb30f8ed60257a61373"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab2e318da4ce6d2ddc1b402f1406b2d3b"><td class="memItemLeft" align="right" valign="top"><a id="ab2e318da4ce6d2ddc1b402f1406b2d3b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab2e318da4ce6d2ddc1b402f1406b2d3b">PIN_PA05B_ADC0_AIN5</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
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<tr class="memdesc:ab2e318da4ce6d2ddc1b402f1406b2d3b"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: AIN5 on PA05 mux B. <br /></td></tr>
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<tr class="separator:ab2e318da4ce6d2ddc1b402f1406b2d3b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a622a3b3d0985020d36ec9980dcefd021"><td class="memItemLeft" align="right" valign="top"><a id="a622a3b3d0985020d36ec9980dcefd021"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA05B_ADC0_AIN5</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:a622a3b3d0985020d36ec9980dcefd021"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a90b88df3679fa1733f70ff70a22c257d"><td class="memItemLeft" align="right" valign="top"><a id="a90b88df3679fa1733f70ff70a22c257d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA05B_ADC0_AIN5</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ab2e318da4ce6d2ddc1b402f1406b2d3b">PIN_PA05B_ADC0_AIN5</a> << 16) | MUX_PA05B_ADC0_AIN5)</td></tr>
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<tr class="separator:a90b88df3679fa1733f70ff70a22c257d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a239822ad55529f99b9f78ead1bfd9879"><td class="memItemLeft" align="right" valign="top"><a id="a239822ad55529f99b9f78ead1bfd9879"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA05B_ADC0_AIN5</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 5)</td></tr>
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<tr class="separator:a239822ad55529f99b9f78ead1bfd9879"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5778cab227620cfc715daa694db8288e"><td class="memItemLeft" align="right" valign="top"><a id="a5778cab227620cfc715daa694db8288e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5778cab227620cfc715daa694db8288e">PIN_PA06B_ADC0_AIN6</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
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<tr class="memdesc:a5778cab227620cfc715daa694db8288e"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: AIN6 on PA06 mux B. <br /></td></tr>
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<tr class="separator:a5778cab227620cfc715daa694db8288e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aac56ad79df5182814dc2963230a6a5e8"><td class="memItemLeft" align="right" valign="top"><a id="aac56ad79df5182814dc2963230a6a5e8"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA06B_ADC0_AIN6</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:aac56ad79df5182814dc2963230a6a5e8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1c53c8b65597bc1d3704a2226f5b30c9"><td class="memItemLeft" align="right" valign="top"><a id="a1c53c8b65597bc1d3704a2226f5b30c9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA06B_ADC0_AIN6</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a5778cab227620cfc715daa694db8288e">PIN_PA06B_ADC0_AIN6</a> << 16) | MUX_PA06B_ADC0_AIN6)</td></tr>
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<tr class="separator:a1c53c8b65597bc1d3704a2226f5b30c9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a753719ea00a35a6103aecd806b3077ab"><td class="memItemLeft" align="right" valign="top"><a id="a753719ea00a35a6103aecd806b3077ab"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA06B_ADC0_AIN6</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 6)</td></tr>
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<tr class="separator:a753719ea00a35a6103aecd806b3077ab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a501e38aef181b2f595a4ef613e8a98a2"><td class="memItemLeft" align="right" valign="top"><a id="a501e38aef181b2f595a4ef613e8a98a2"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a501e38aef181b2f595a4ef613e8a98a2">PIN_PA07B_ADC0_AIN7</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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<tr class="memdesc:a501e38aef181b2f595a4ef613e8a98a2"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: AIN7 on PA07 mux B. <br /></td></tr>
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<tr class="separator:a501e38aef181b2f595a4ef613e8a98a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6a24adec4ac50298f10dd63314653a51"><td class="memItemLeft" align="right" valign="top"><a id="a6a24adec4ac50298f10dd63314653a51"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA07B_ADC0_AIN7</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:a6a24adec4ac50298f10dd63314653a51"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad851f18a52e9bf92f32bd682fefa75ab"><td class="memItemLeft" align="right" valign="top"><a id="ad851f18a52e9bf92f32bd682fefa75ab"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA07B_ADC0_AIN7</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a501e38aef181b2f595a4ef613e8a98a2">PIN_PA07B_ADC0_AIN7</a> << 16) | MUX_PA07B_ADC0_AIN7)</td></tr>
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<tr class="separator:ad851f18a52e9bf92f32bd682fefa75ab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0bdf0515ee59b4f40da3102e2cb9aa0d"><td class="memItemLeft" align="right" valign="top"><a id="a0bdf0515ee59b4f40da3102e2cb9aa0d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA07B_ADC0_AIN7</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 7)</td></tr>
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<tr class="separator:a0bdf0515ee59b4f40da3102e2cb9aa0d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aceccfd85cf1a03db216038eb4e32fcf3"><td class="memItemLeft" align="right" valign="top"><a id="aceccfd85cf1a03db216038eb4e32fcf3"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aceccfd85cf1a03db216038eb4e32fcf3">PIN_PA08B_ADC0_AIN8</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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||
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<tr class="memdesc:aceccfd85cf1a03db216038eb4e32fcf3"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: AIN8 on PA08 mux B. <br /></td></tr>
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<tr class="separator:aceccfd85cf1a03db216038eb4e32fcf3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a890f342c2a924e1508599dc60d04c4b7"><td class="memItemLeft" align="right" valign="top"><a id="a890f342c2a924e1508599dc60d04c4b7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA08B_ADC0_AIN8</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:a890f342c2a924e1508599dc60d04c4b7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aed28e6cda2c9281e790aadb7d74659ff"><td class="memItemLeft" align="right" valign="top"><a id="aed28e6cda2c9281e790aadb7d74659ff"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA08B_ADC0_AIN8</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aceccfd85cf1a03db216038eb4e32fcf3">PIN_PA08B_ADC0_AIN8</a> << 16) | MUX_PA08B_ADC0_AIN8)</td></tr>
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<tr class="separator:aed28e6cda2c9281e790aadb7d74659ff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a75f078291dd7ea3904a2525583936d4a"><td class="memItemLeft" align="right" valign="top"><a id="a75f078291dd7ea3904a2525583936d4a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA08B_ADC0_AIN8</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 8)</td></tr>
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<tr class="separator:a75f078291dd7ea3904a2525583936d4a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1caa71383e0270741e1963c68e9e426f"><td class="memItemLeft" align="right" valign="top"><a id="a1caa71383e0270741e1963c68e9e426f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1caa71383e0270741e1963c68e9e426f">PIN_PA09B_ADC0_AIN9</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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||
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<tr class="memdesc:a1caa71383e0270741e1963c68e9e426f"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: AIN9 on PA09 mux B. <br /></td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA09B_ADC0_AIN9</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="memitem:a91a332fc189f31a36eda29fabb93e942"><td class="memItemLeft" align="right" valign="top"><a id="a91a332fc189f31a36eda29fabb93e942"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA09B_ADC0_AIN9</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a1caa71383e0270741e1963c68e9e426f">PIN_PA09B_ADC0_AIN9</a> << 16) | MUX_PA09B_ADC0_AIN9)</td></tr>
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<tr class="memitem:af1d61069d0283041527be84c3b1f3629"><td class="memItemLeft" align="right" valign="top"><a id="af1d61069d0283041527be84c3b1f3629"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA09B_ADC0_AIN9</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 9)</td></tr>
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<tr class="memitem:a3f73d5fad9e51355712d6d30b5ef60e9"><td class="memItemLeft" align="right" valign="top"><a id="a3f73d5fad9e51355712d6d30b5ef60e9"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3f73d5fad9e51355712d6d30b5ef60e9">PIN_PA10B_ADC0_AIN10</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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<tr class="memdesc:a3f73d5fad9e51355712d6d30b5ef60e9"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: AIN10 on PA10 mux B. <br /></td></tr>
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<tr class="memitem:adfb062887bb6f3180de570418146dc3b"><td class="memItemLeft" align="right" valign="top"><a id="adfb062887bb6f3180de570418146dc3b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA10B_ADC0_AIN10</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="memitem:a585d6bdc1521d9a04bd555fa6aa042e9"><td class="memItemLeft" align="right" valign="top"><a id="a585d6bdc1521d9a04bd555fa6aa042e9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA10B_ADC0_AIN10</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a3f73d5fad9e51355712d6d30b5ef60e9">PIN_PA10B_ADC0_AIN10</a> << 16) | MUX_PA10B_ADC0_AIN10)</td></tr>
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<tr class="memitem:a719a0bbaa89f2c8f8f6c05942a7b2a09"><td class="memItemLeft" align="right" valign="top"><a id="a719a0bbaa89f2c8f8f6c05942a7b2a09"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA10B_ADC0_AIN10</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 10)</td></tr>
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<tr class="separator:a719a0bbaa89f2c8f8f6c05942a7b2a09"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a22fb1aa44b045a1b736bbea7e4d76702"><td class="memItemLeft" align="right" valign="top"><a id="a22fb1aa44b045a1b736bbea7e4d76702"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a22fb1aa44b045a1b736bbea7e4d76702">PIN_PA11B_ADC0_AIN11</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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<tr class="memdesc:a22fb1aa44b045a1b736bbea7e4d76702"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: AIN11 on PA11 mux B. <br /></td></tr>
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<tr class="separator:a22fb1aa44b045a1b736bbea7e4d76702"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af4f04840e382ec422003680e26d69ede"><td class="memItemLeft" align="right" valign="top"><a id="af4f04840e382ec422003680e26d69ede"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA11B_ADC0_AIN11</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:af4f04840e382ec422003680e26d69ede"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7a94ff8d0bad9e18088c8bb1eeb7044e"><td class="memItemLeft" align="right" valign="top"><a id="a7a94ff8d0bad9e18088c8bb1eeb7044e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA11B_ADC0_AIN11</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a22fb1aa44b045a1b736bbea7e4d76702">PIN_PA11B_ADC0_AIN11</a> << 16) | MUX_PA11B_ADC0_AIN11)</td></tr>
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<tr class="separator:a7a94ff8d0bad9e18088c8bb1eeb7044e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acd9d0eadeb19dbd553f10d6c4844049e"><td class="memItemLeft" align="right" valign="top"><a id="acd9d0eadeb19dbd553f10d6c4844049e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA11B_ADC0_AIN11</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 11)</td></tr>
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<tr class="separator:acd9d0eadeb19dbd553f10d6c4844049e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad610d6f46c5904a343c4895e77ec2949"><td class="memItemLeft" align="right" valign="top"><a id="ad610d6f46c5904a343c4895e77ec2949"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad610d6f46c5904a343c4895e77ec2949">PIN_PB00B_ADC0_AIN12</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(32)</td></tr>
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<tr class="memdesc:ad610d6f46c5904a343c4895e77ec2949"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: AIN12 on PB00 mux B. <br /></td></tr>
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<tr class="separator:ad610d6f46c5904a343c4895e77ec2949"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae01bc45742359c25096b6d58fc667b27"><td class="memItemLeft" align="right" valign="top"><a id="ae01bc45742359c25096b6d58fc667b27"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB00B_ADC0_AIN12</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:ae01bc45742359c25096b6d58fc667b27"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aaf2a8b20abfffb5cfe80629a29af83a8"><td class="memItemLeft" align="right" valign="top"><a id="aaf2a8b20abfffb5cfe80629a29af83a8"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB00B_ADC0_AIN12</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ad610d6f46c5904a343c4895e77ec2949">PIN_PB00B_ADC0_AIN12</a> << 16) | MUX_PB00B_ADC0_AIN12)</td></tr>
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<tr class="separator:aaf2a8b20abfffb5cfe80629a29af83a8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aacf0bbb648d88472b9302b8406970f54"><td class="memItemLeft" align="right" valign="top"><a id="aacf0bbb648d88472b9302b8406970f54"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB00B_ADC0_AIN12</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 0)</td></tr>
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<tr class="separator:aacf0bbb648d88472b9302b8406970f54"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a82a0605e63164a955a0772cee1e8a704"><td class="memItemLeft" align="right" valign="top"><a id="a82a0605e63164a955a0772cee1e8a704"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a82a0605e63164a955a0772cee1e8a704">PIN_PB01B_ADC0_AIN13</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(33)</td></tr>
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<tr class="memdesc:a82a0605e63164a955a0772cee1e8a704"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: AIN13 on PB01 mux B. <br /></td></tr>
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<tr class="memitem:a94e2bf76041198c532f345be1e2136a8"><td class="memItemLeft" align="right" valign="top"><a id="a94e2bf76041198c532f345be1e2136a8"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB01B_ADC0_AIN13</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:a94e2bf76041198c532f345be1e2136a8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a002a04ffd95e91ae57477fc2f56ceb8b"><td class="memItemLeft" align="right" valign="top"><a id="a002a04ffd95e91ae57477fc2f56ceb8b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB01B_ADC0_AIN13</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a82a0605e63164a955a0772cee1e8a704">PIN_PB01B_ADC0_AIN13</a> << 16) | MUX_PB01B_ADC0_AIN13)</td></tr>
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<tr class="separator:a002a04ffd95e91ae57477fc2f56ceb8b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad7f429bb7770508134cb4ff7d8a78d02"><td class="memItemLeft" align="right" valign="top"><a id="ad7f429bb7770508134cb4ff7d8a78d02"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB01B_ADC0_AIN13</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 1)</td></tr>
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<tr class="separator:ad7f429bb7770508134cb4ff7d8a78d02"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a186f71c64030c54a707bbc042853cc55"><td class="memItemLeft" align="right" valign="top"><a id="a186f71c64030c54a707bbc042853cc55"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a186f71c64030c54a707bbc042853cc55">PIN_PB02B_ADC0_AIN14</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(34)</td></tr>
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<tr class="memdesc:a186f71c64030c54a707bbc042853cc55"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: AIN14 on PB02 mux B. <br /></td></tr>
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<tr class="separator:a186f71c64030c54a707bbc042853cc55"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa5df7881c3763b3ddb98d9897560c4d8"><td class="memItemLeft" align="right" valign="top"><a id="aa5df7881c3763b3ddb98d9897560c4d8"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB02B_ADC0_AIN14</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:aa5df7881c3763b3ddb98d9897560c4d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5424f706583a94f51e03ef07b368e2a9"><td class="memItemLeft" align="right" valign="top"><a id="a5424f706583a94f51e03ef07b368e2a9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB02B_ADC0_AIN14</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a186f71c64030c54a707bbc042853cc55">PIN_PB02B_ADC0_AIN14</a> << 16) | MUX_PB02B_ADC0_AIN14)</td></tr>
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<tr class="separator:a5424f706583a94f51e03ef07b368e2a9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a10d5f784a6574ebd5948f8e87f02f3dd"><td class="memItemLeft" align="right" valign="top"><a id="a10d5f784a6574ebd5948f8e87f02f3dd"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB02B_ADC0_AIN14</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 2)</td></tr>
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<tr class="separator:a10d5f784a6574ebd5948f8e87f02f3dd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0202f983c48cb8e31c11d7ef33dc9834"><td class="memItemLeft" align="right" valign="top"><a id="a0202f983c48cb8e31c11d7ef33dc9834"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0202f983c48cb8e31c11d7ef33dc9834">PIN_PB03B_ADC0_AIN15</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(35)</td></tr>
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<tr class="memdesc:a0202f983c48cb8e31c11d7ef33dc9834"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: AIN15 on PB03 mux B. <br /></td></tr>
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<tr class="separator:a0202f983c48cb8e31c11d7ef33dc9834"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aca6ddd8024b98b87db326d4c7379efbc"><td class="memItemLeft" align="right" valign="top"><a id="aca6ddd8024b98b87db326d4c7379efbc"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB03B_ADC0_AIN15</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:aca6ddd8024b98b87db326d4c7379efbc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a658d1467d108c526a8570e43390b38d6"><td class="memItemLeft" align="right" valign="top"><a id="a658d1467d108c526a8570e43390b38d6"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB03B_ADC0_AIN15</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a0202f983c48cb8e31c11d7ef33dc9834">PIN_PB03B_ADC0_AIN15</a> << 16) | MUX_PB03B_ADC0_AIN15)</td></tr>
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<tr class="separator:a658d1467d108c526a8570e43390b38d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a02bcb48779c42299cc15b1fa9d8554ce"><td class="memItemLeft" align="right" valign="top"><a id="a02bcb48779c42299cc15b1fa9d8554ce"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB03B_ADC0_AIN15</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 3)</td></tr>
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<tr class="separator:a02bcb48779c42299cc15b1fa9d8554ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1963fad1ea7cddab4e49b18e91b2845c"><td class="memItemLeft" align="right" valign="top"><a id="a1963fad1ea7cddab4e49b18e91b2845c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1963fad1ea7cddab4e49b18e91b2845c">PIN_PA03O_ADC0_DRV0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
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<tr class="memdesc:a1963fad1ea7cddab4e49b18e91b2845c"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: DRV0 on PA03 mux O. <br /></td></tr>
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<tr class="separator:a1963fad1ea7cddab4e49b18e91b2845c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3872f3f7215609e6713ca54057decb43"><td class="memItemLeft" align="right" valign="top"><a id="a3872f3f7215609e6713ca54057decb43"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA03O_ADC0_DRV0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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<tr class="separator:a3872f3f7215609e6713ca54057decb43"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a73e2c1e1deb6295b4d889e5919735389"><td class="memItemLeft" align="right" valign="top"><a id="a73e2c1e1deb6295b4d889e5919735389"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA03O_ADC0_DRV0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a1963fad1ea7cddab4e49b18e91b2845c">PIN_PA03O_ADC0_DRV0</a> << 16) | MUX_PA03O_ADC0_DRV0)</td></tr>
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<tr class="memitem:ad204447e6e524af5c05fd4e408a9dbb7"><td class="memItemLeft" align="right" valign="top"><a id="ad204447e6e524af5c05fd4e408a9dbb7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA03O_ADC0_DRV0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 3)</td></tr>
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<tr class="separator:ad204447e6e524af5c05fd4e408a9dbb7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae6a23d3195ef6cae571dbd18854ee478"><td class="memItemLeft" align="right" valign="top"><a id="ae6a23d3195ef6cae571dbd18854ee478"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae6a23d3195ef6cae571dbd18854ee478">PIN_PB08O_ADC0_DRV1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(40)</td></tr>
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<tr class="memdesc:ae6a23d3195ef6cae571dbd18854ee478"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: DRV1 on PB08 mux O. <br /></td></tr>
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<tr class="separator:ae6a23d3195ef6cae571dbd18854ee478"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acc83c0964aa55bc08592c59ecd671255"><td class="memItemLeft" align="right" valign="top"><a id="acc83c0964aa55bc08592c59ecd671255"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB08O_ADC0_DRV1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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<tr class="separator:acc83c0964aa55bc08592c59ecd671255"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa709dcacd4586d8b37d17576b8abdc8a"><td class="memItemLeft" align="right" valign="top"><a id="aa709dcacd4586d8b37d17576b8abdc8a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB08O_ADC0_DRV1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ae6a23d3195ef6cae571dbd18854ee478">PIN_PB08O_ADC0_DRV1</a> << 16) | MUX_PB08O_ADC0_DRV1)</td></tr>
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<tr class="separator:aa709dcacd4586d8b37d17576b8abdc8a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae17c1258165831db017bffc9abc1298d"><td class="memItemLeft" align="right" valign="top"><a id="ae17c1258165831db017bffc9abc1298d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB08O_ADC0_DRV1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 8)</td></tr>
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<tr class="separator:ae17c1258165831db017bffc9abc1298d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adbcae59b905267c17a16368c5e8a9d00"><td class="memItemLeft" align="right" valign="top"><a id="adbcae59b905267c17a16368c5e8a9d00"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#adbcae59b905267c17a16368c5e8a9d00">PIN_PB09O_ADC0_DRV2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(41)</td></tr>
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||
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<tr class="memdesc:adbcae59b905267c17a16368c5e8a9d00"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: DRV2 on PB09 mux O. <br /></td></tr>
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<tr class="separator:adbcae59b905267c17a16368c5e8a9d00"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5ed873ac141a7f79896d08ae2e79a636"><td class="memItemLeft" align="right" valign="top"><a id="a5ed873ac141a7f79896d08ae2e79a636"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB09O_ADC0_DRV2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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<tr class="separator:a5ed873ac141a7f79896d08ae2e79a636"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab98e45b90be01b30e93f475a2f3ba37b"><td class="memItemLeft" align="right" valign="top"><a id="ab98e45b90be01b30e93f475a2f3ba37b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB09O_ADC0_DRV2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#adbcae59b905267c17a16368c5e8a9d00">PIN_PB09O_ADC0_DRV2</a> << 16) | MUX_PB09O_ADC0_DRV2)</td></tr>
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<tr class="separator:ab98e45b90be01b30e93f475a2f3ba37b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af8b6d6be9ae4e9ea9f2da3550047f96b"><td class="memItemLeft" align="right" valign="top"><a id="af8b6d6be9ae4e9ea9f2da3550047f96b"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB09O_ADC0_DRV2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 9)</td></tr>
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<tr class="separator:af8b6d6be9ae4e9ea9f2da3550047f96b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa62a95d8db5ca1dbc9a85483b3027611"><td class="memItemLeft" align="right" valign="top"><a id="aa62a95d8db5ca1dbc9a85483b3027611"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa62a95d8db5ca1dbc9a85483b3027611">PIN_PA04O_ADC0_DRV3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
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<tr class="memdesc:aa62a95d8db5ca1dbc9a85483b3027611"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: DRV3 on PA04 mux O. <br /></td></tr>
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<tr class="separator:aa62a95d8db5ca1dbc9a85483b3027611"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a04302306c558608748a7ff22962a8d29"><td class="memItemLeft" align="right" valign="top"><a id="a04302306c558608748a7ff22962a8d29"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA04O_ADC0_DRV3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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<tr class="separator:a04302306c558608748a7ff22962a8d29"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a92434d667bd5920218149fb6c11a4045"><td class="memItemLeft" align="right" valign="top"><a id="a92434d667bd5920218149fb6c11a4045"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA04O_ADC0_DRV3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aa62a95d8db5ca1dbc9a85483b3027611">PIN_PA04O_ADC0_DRV3</a> << 16) | MUX_PA04O_ADC0_DRV3)</td></tr>
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<tr class="separator:a92434d667bd5920218149fb6c11a4045"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af15123a02946efc23117c05c78a8bc4e"><td class="memItemLeft" align="right" valign="top"><a id="af15123a02946efc23117c05c78a8bc4e"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA04O_ADC0_DRV3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 4)</td></tr>
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||
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<tr class="separator:af15123a02946efc23117c05c78a8bc4e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a40eeff97d976588dd0e28a948d512cae"><td class="memItemLeft" align="right" valign="top"><a id="a40eeff97d976588dd0e28a948d512cae"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a40eeff97d976588dd0e28a948d512cae">PIN_PA06O_ADC0_DRV4</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
|
||
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<tr class="memdesc:a40eeff97d976588dd0e28a948d512cae"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: DRV4 on PA06 mux O. <br /></td></tr>
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<tr class="separator:a40eeff97d976588dd0e28a948d512cae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a20033d1f4b41812705cf578dbd18a69f"><td class="memItemLeft" align="right" valign="top"><a id="a20033d1f4b41812705cf578dbd18a69f"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA06O_ADC0_DRV4</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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||
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<tr class="separator:a20033d1f4b41812705cf578dbd18a69f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a791810296af40a84fe0c702e59da4a72"><td class="memItemLeft" align="right" valign="top"><a id="a791810296af40a84fe0c702e59da4a72"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA06O_ADC0_DRV4</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a40eeff97d976588dd0e28a948d512cae">PIN_PA06O_ADC0_DRV4</a> << 16) | MUX_PA06O_ADC0_DRV4)</td></tr>
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<tr class="separator:a791810296af40a84fe0c702e59da4a72"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9745926797d7303edbee8c748a7cb0d8"><td class="memItemLeft" align="right" valign="top"><a id="a9745926797d7303edbee8c748a7cb0d8"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA06O_ADC0_DRV4</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 6)</td></tr>
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||
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<tr class="separator:a9745926797d7303edbee8c748a7cb0d8"><td class="memSeparator" colspan="2"> </td></tr>
|
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<tr class="memitem:ac04245040a82cd4257029dda90a8c9ec"><td class="memItemLeft" align="right" valign="top"><a id="ac04245040a82cd4257029dda90a8c9ec"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac04245040a82cd4257029dda90a8c9ec">PIN_PA07O_ADC0_DRV5</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
|
||
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<tr class="memdesc:ac04245040a82cd4257029dda90a8c9ec"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: DRV5 on PA07 mux O. <br /></td></tr>
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<tr class="separator:ac04245040a82cd4257029dda90a8c9ec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acb6ca7070d1e6d385645b1c5a90691fc"><td class="memItemLeft" align="right" valign="top"><a id="acb6ca7070d1e6d385645b1c5a90691fc"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA07O_ADC0_DRV5</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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||
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<tr class="separator:acb6ca7070d1e6d385645b1c5a90691fc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab71ca204970e1f76e6ed8423ba9e4805"><td class="memItemLeft" align="right" valign="top"><a id="ab71ca204970e1f76e6ed8423ba9e4805"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA07O_ADC0_DRV5</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ac04245040a82cd4257029dda90a8c9ec">PIN_PA07O_ADC0_DRV5</a> << 16) | MUX_PA07O_ADC0_DRV5)</td></tr>
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<tr class="separator:ab71ca204970e1f76e6ed8423ba9e4805"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afda479ca313bf0f76000eea801d0bbf8"><td class="memItemLeft" align="right" valign="top"><a id="afda479ca313bf0f76000eea801d0bbf8"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA07O_ADC0_DRV5</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 7)</td></tr>
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||
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<tr class="separator:afda479ca313bf0f76000eea801d0bbf8"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:aab74c1ba4559893c6bba93e0e2494f15"><td class="memItemLeft" align="right" valign="top"><a id="aab74c1ba4559893c6bba93e0e2494f15"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aab74c1ba4559893c6bba93e0e2494f15">PIN_PA08O_ADC0_DRV6</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
|
||
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<tr class="memdesc:aab74c1ba4559893c6bba93e0e2494f15"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: DRV6 on PA08 mux O. <br /></td></tr>
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<tr class="separator:aab74c1ba4559893c6bba93e0e2494f15"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5025c5d9041f29202e563bc445a2bf09"><td class="memItemLeft" align="right" valign="top"><a id="a5025c5d9041f29202e563bc445a2bf09"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA08O_ADC0_DRV6</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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<tr class="separator:a5025c5d9041f29202e563bc445a2bf09"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5b91fdaec3bf98b2073a7a9b6350deab"><td class="memItemLeft" align="right" valign="top"><a id="a5b91fdaec3bf98b2073a7a9b6350deab"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA08O_ADC0_DRV6</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aab74c1ba4559893c6bba93e0e2494f15">PIN_PA08O_ADC0_DRV6</a> << 16) | MUX_PA08O_ADC0_DRV6)</td></tr>
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<tr class="separator:a5b91fdaec3bf98b2073a7a9b6350deab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac8397fb4689643e7d2554807937a78f7"><td class="memItemLeft" align="right" valign="top"><a id="ac8397fb4689643e7d2554807937a78f7"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA08O_ADC0_DRV6</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 8)</td></tr>
|
||
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<tr class="separator:ac8397fb4689643e7d2554807937a78f7"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a6f0d54ffbea8dcf8806b72e40f98286b"><td class="memItemLeft" align="right" valign="top"><a id="a6f0d54ffbea8dcf8806b72e40f98286b"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6f0d54ffbea8dcf8806b72e40f98286b">PIN_PA09O_ADC0_DRV7</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
|
||
|
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<tr class="memdesc:a6f0d54ffbea8dcf8806b72e40f98286b"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: DRV7 on PA09 mux O. <br /></td></tr>
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<tr class="separator:a6f0d54ffbea8dcf8806b72e40f98286b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1f8aa420f1c7470f3300931dd0447f74"><td class="memItemLeft" align="right" valign="top"><a id="a1f8aa420f1c7470f3300931dd0447f74"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA09O_ADC0_DRV7</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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<tr class="separator:a1f8aa420f1c7470f3300931dd0447f74"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad1e9140be3b60674165fd1c74292e9fe"><td class="memItemLeft" align="right" valign="top"><a id="ad1e9140be3b60674165fd1c74292e9fe"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA09O_ADC0_DRV7</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a6f0d54ffbea8dcf8806b72e40f98286b">PIN_PA09O_ADC0_DRV7</a> << 16) | MUX_PA09O_ADC0_DRV7)</td></tr>
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<tr class="separator:ad1e9140be3b60674165fd1c74292e9fe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9462fac82620625ac71beec545c16356"><td class="memItemLeft" align="right" valign="top"><a id="a9462fac82620625ac71beec545c16356"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA09O_ADC0_DRV7</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 9)</td></tr>
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<tr class="separator:a9462fac82620625ac71beec545c16356"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa94b8eef3c555c383c4c707a0a289542"><td class="memItemLeft" align="right" valign="top"><a id="aa94b8eef3c555c383c4c707a0a289542"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa94b8eef3c555c383c4c707a0a289542">PIN_PA10O_ADC0_DRV8</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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<tr class="memdesc:aa94b8eef3c555c383c4c707a0a289542"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: DRV8 on PA10 mux O. <br /></td></tr>
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<tr class="separator:aa94b8eef3c555c383c4c707a0a289542"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adbdfb2b123e25cc3cb7d39a5c3416ad1"><td class="memItemLeft" align="right" valign="top"><a id="adbdfb2b123e25cc3cb7d39a5c3416ad1"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA10O_ADC0_DRV8</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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<tr class="separator:adbdfb2b123e25cc3cb7d39a5c3416ad1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a459dc2a6d823b1677e1857ee01826167"><td class="memItemLeft" align="right" valign="top"><a id="a459dc2a6d823b1677e1857ee01826167"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA10O_ADC0_DRV8</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aa94b8eef3c555c383c4c707a0a289542">PIN_PA10O_ADC0_DRV8</a> << 16) | MUX_PA10O_ADC0_DRV8)</td></tr>
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<tr class="separator:a459dc2a6d823b1677e1857ee01826167"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a22fbadd094d59b6bda84e9722b1b43dc"><td class="memItemLeft" align="right" valign="top"><a id="a22fbadd094d59b6bda84e9722b1b43dc"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA10O_ADC0_DRV8</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 10)</td></tr>
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<tr class="separator:a22fbadd094d59b6bda84e9722b1b43dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aaf6ac5bda3d9ed2febd75c023946c5a0"><td class="memItemLeft" align="right" valign="top"><a id="aaf6ac5bda3d9ed2febd75c023946c5a0"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aaf6ac5bda3d9ed2febd75c023946c5a0">PIN_PA11O_ADC0_DRV9</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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<tr class="memdesc:aaf6ac5bda3d9ed2febd75c023946c5a0"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: DRV9 on PA11 mux O. <br /></td></tr>
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<tr class="separator:aaf6ac5bda3d9ed2febd75c023946c5a0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8efba2cb839783bf84907d5aab1b969b"><td class="memItemLeft" align="right" valign="top"><a id="a8efba2cb839783bf84907d5aab1b969b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA11O_ADC0_DRV9</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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<tr class="separator:a8efba2cb839783bf84907d5aab1b969b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abe5b349338bd6e2ccfb333abb3b62787"><td class="memItemLeft" align="right" valign="top"><a id="abe5b349338bd6e2ccfb333abb3b62787"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA11O_ADC0_DRV9</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aaf6ac5bda3d9ed2febd75c023946c5a0">PIN_PA11O_ADC0_DRV9</a> << 16) | MUX_PA11O_ADC0_DRV9)</td></tr>
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<tr class="separator:abe5b349338bd6e2ccfb333abb3b62787"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a164bc1d44e82416086e8392c34fa3d3c"><td class="memItemLeft" align="right" valign="top"><a id="a164bc1d44e82416086e8392c34fa3d3c"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA11O_ADC0_DRV9</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 11)</td></tr>
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||
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<tr class="separator:a164bc1d44e82416086e8392c34fa3d3c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1f5f104ea785c9aecc1ed67dc7fd4c10"><td class="memItemLeft" align="right" valign="top"><a id="a1f5f104ea785c9aecc1ed67dc7fd4c10"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1f5f104ea785c9aecc1ed67dc7fd4c10">PIN_PA16O_ADC0_DRV10</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(16)</td></tr>
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||
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<tr class="memdesc:a1f5f104ea785c9aecc1ed67dc7fd4c10"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: DRV10 on PA16 mux O. <br /></td></tr>
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<tr class="separator:a1f5f104ea785c9aecc1ed67dc7fd4c10"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac8da5a86cc67a41563fab41974a57174"><td class="memItemLeft" align="right" valign="top"><a id="ac8da5a86cc67a41563fab41974a57174"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA16O_ADC0_DRV10</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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||
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<tr class="separator:ac8da5a86cc67a41563fab41974a57174"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6c876a11cee8e823a449b46222249117"><td class="memItemLeft" align="right" valign="top"><a id="a6c876a11cee8e823a449b46222249117"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA16O_ADC0_DRV10</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a1f5f104ea785c9aecc1ed67dc7fd4c10">PIN_PA16O_ADC0_DRV10</a> << 16) | MUX_PA16O_ADC0_DRV10)</td></tr>
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<tr class="separator:a6c876a11cee8e823a449b46222249117"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a41740b5d542af179ae8d88c66b32a223"><td class="memItemLeft" align="right" valign="top"><a id="a41740b5d542af179ae8d88c66b32a223"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA16O_ADC0_DRV10</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 16)</td></tr>
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||
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<tr class="separator:a41740b5d542af179ae8d88c66b32a223"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a29189eb1f11badca6dddd687f622efe9"><td class="memItemLeft" align="right" valign="top"><a id="a29189eb1f11badca6dddd687f622efe9"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a29189eb1f11badca6dddd687f622efe9">PIN_PA17O_ADC0_DRV11</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(17)</td></tr>
|
||
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<tr class="memdesc:a29189eb1f11badca6dddd687f622efe9"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: DRV11 on PA17 mux O. <br /></td></tr>
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<tr class="separator:a29189eb1f11badca6dddd687f622efe9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a44ba58aa16bede526c6ad912bed68c80"><td class="memItemLeft" align="right" valign="top"><a id="a44ba58aa16bede526c6ad912bed68c80"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA17O_ADC0_DRV11</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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||
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<tr class="separator:a44ba58aa16bede526c6ad912bed68c80"><td class="memSeparator" colspan="2"> </td></tr>
|
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<tr class="memitem:a19707ac8a8480732ea40d6cbc8cd19b3"><td class="memItemLeft" align="right" valign="top"><a id="a19707ac8a8480732ea40d6cbc8cd19b3"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA17O_ADC0_DRV11</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a29189eb1f11badca6dddd687f622efe9">PIN_PA17O_ADC0_DRV11</a> << 16) | MUX_PA17O_ADC0_DRV11)</td></tr>
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<tr class="separator:a19707ac8a8480732ea40d6cbc8cd19b3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1315ccf3dcdd8893ae6c002f74f9dc09"><td class="memItemLeft" align="right" valign="top"><a id="a1315ccf3dcdd8893ae6c002f74f9dc09"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA17O_ADC0_DRV11</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 17)</td></tr>
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||
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<tr class="separator:a1315ccf3dcdd8893ae6c002f74f9dc09"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac1724252c005911ccb381594f734ee50"><td class="memItemLeft" align="right" valign="top"><a id="ac1724252c005911ccb381594f734ee50"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac1724252c005911ccb381594f734ee50">PIN_PA18O_ADC0_DRV12</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(18)</td></tr>
|
||
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<tr class="memdesc:ac1724252c005911ccb381594f734ee50"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: DRV12 on PA18 mux O. <br /></td></tr>
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<tr class="separator:ac1724252c005911ccb381594f734ee50"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1684e52eb180407f29aca92565441c7c"><td class="memItemLeft" align="right" valign="top"><a id="a1684e52eb180407f29aca92565441c7c"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA18O_ADC0_DRV12</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
|
||
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<tr class="separator:a1684e52eb180407f29aca92565441c7c"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a4245f1bbb39cc001feb06ea8fdf2e59f"><td class="memItemLeft" align="right" valign="top"><a id="a4245f1bbb39cc001feb06ea8fdf2e59f"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA18O_ADC0_DRV12</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ac1724252c005911ccb381594f734ee50">PIN_PA18O_ADC0_DRV12</a> << 16) | MUX_PA18O_ADC0_DRV12)</td></tr>
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<tr class="separator:a4245f1bbb39cc001feb06ea8fdf2e59f"><td class="memSeparator" colspan="2"> </td></tr>
|
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<tr class="memitem:a67854d1f35a88ca190a3a9dda9224d98"><td class="memItemLeft" align="right" valign="top"><a id="a67854d1f35a88ca190a3a9dda9224d98"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA18O_ADC0_DRV12</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 18)</td></tr>
|
||
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<tr class="separator:a67854d1f35a88ca190a3a9dda9224d98"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a75580c9e71023e1877a9001b79d0c9e0"><td class="memItemLeft" align="right" valign="top"><a id="a75580c9e71023e1877a9001b79d0c9e0"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a75580c9e71023e1877a9001b79d0c9e0">PIN_PA19O_ADC0_DRV13</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(19)</td></tr>
|
||
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<tr class="memdesc:a75580c9e71023e1877a9001b79d0c9e0"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: DRV13 on PA19 mux O. <br /></td></tr>
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<tr class="separator:a75580c9e71023e1877a9001b79d0c9e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0f47aad11cd818ac75f1d0ffa240b273"><td class="memItemLeft" align="right" valign="top"><a id="a0f47aad11cd818ac75f1d0ffa240b273"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA19O_ADC0_DRV13</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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||
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<tr class="separator:a0f47aad11cd818ac75f1d0ffa240b273"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a48a29d84b7cfe0fff3c8d0c9c6303a51"><td class="memItemLeft" align="right" valign="top"><a id="a48a29d84b7cfe0fff3c8d0c9c6303a51"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA19O_ADC0_DRV13</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a75580c9e71023e1877a9001b79d0c9e0">PIN_PA19O_ADC0_DRV13</a> << 16) | MUX_PA19O_ADC0_DRV13)</td></tr>
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<tr class="separator:a48a29d84b7cfe0fff3c8d0c9c6303a51"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a79ebd89592966e482794b09a09e076fb"><td class="memItemLeft" align="right" valign="top"><a id="a79ebd89592966e482794b09a09e076fb"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA19O_ADC0_DRV13</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 19)</td></tr>
|
||
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<tr class="separator:a79ebd89592966e482794b09a09e076fb"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a7811ba2c988651c2c61e02459573e823"><td class="memItemLeft" align="right" valign="top"><a id="a7811ba2c988651c2c61e02459573e823"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7811ba2c988651c2c61e02459573e823">PIN_PA20O_ADC0_DRV14</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(20)</td></tr>
|
||
|
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<tr class="memdesc:a7811ba2c988651c2c61e02459573e823"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: DRV14 on PA20 mux O. <br /></td></tr>
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<tr class="separator:a7811ba2c988651c2c61e02459573e823"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a03795bb715ca2643915a35f786baefa2"><td class="memItemLeft" align="right" valign="top"><a id="a03795bb715ca2643915a35f786baefa2"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA20O_ADC0_DRV14</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
|
||
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<tr class="separator:a03795bb715ca2643915a35f786baefa2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a946d4714df8955d01de20ce3c59985e8"><td class="memItemLeft" align="right" valign="top"><a id="a946d4714df8955d01de20ce3c59985e8"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA20O_ADC0_DRV14</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a7811ba2c988651c2c61e02459573e823">PIN_PA20O_ADC0_DRV14</a> << 16) | MUX_PA20O_ADC0_DRV14)</td></tr>
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<tr class="separator:a946d4714df8955d01de20ce3c59985e8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6a7e9c0e3937adea630ef95283c083e5"><td class="memItemLeft" align="right" valign="top"><a id="a6a7e9c0e3937adea630ef95283c083e5"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA20O_ADC0_DRV14</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 20)</td></tr>
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||
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<tr class="separator:a6a7e9c0e3937adea630ef95283c083e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a604d2edd25dc85915500a377d47d333d"><td class="memItemLeft" align="right" valign="top"><a id="a604d2edd25dc85915500a377d47d333d"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a604d2edd25dc85915500a377d47d333d">PIN_PA21O_ADC0_DRV15</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(21)</td></tr>
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<tr class="memdesc:a604d2edd25dc85915500a377d47d333d"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: DRV15 on PA21 mux O. <br /></td></tr>
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<tr class="memitem:a717b79e395ebe95056175ec567b690da"><td class="memItemLeft" align="right" valign="top"><a id="a717b79e395ebe95056175ec567b690da"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA21O_ADC0_DRV15</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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<tr class="separator:a717b79e395ebe95056175ec567b690da"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a69576ed7a076d1732f321f2ef79c4ba0"><td class="memItemLeft" align="right" valign="top"><a id="a69576ed7a076d1732f321f2ef79c4ba0"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA21O_ADC0_DRV15</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a604d2edd25dc85915500a377d47d333d">PIN_PA21O_ADC0_DRV15</a> << 16) | MUX_PA21O_ADC0_DRV15)</td></tr>
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<tr class="memitem:a3b9cfc957b2501eff584e465e82319f4"><td class="memItemLeft" align="right" valign="top"><a id="a3b9cfc957b2501eff584e465e82319f4"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA21O_ADC0_DRV15</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 21)</td></tr>
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<tr class="separator:a3b9cfc957b2501eff584e465e82319f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a454401ca6ea915995237970ce8b5bf4e"><td class="memItemLeft" align="right" valign="top"><a id="a454401ca6ea915995237970ce8b5bf4e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a454401ca6ea915995237970ce8b5bf4e">PIN_PA22O_ADC0_DRV16</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(22)</td></tr>
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<tr class="memdesc:a454401ca6ea915995237970ce8b5bf4e"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: DRV16 on PA22 mux O. <br /></td></tr>
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<tr class="separator:a454401ca6ea915995237970ce8b5bf4e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3e4cc40aa4cabe6cfca6f4c69711cc36"><td class="memItemLeft" align="right" valign="top"><a id="a3e4cc40aa4cabe6cfca6f4c69711cc36"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA22O_ADC0_DRV16</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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<tr class="separator:a3e4cc40aa4cabe6cfca6f4c69711cc36"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac5fb98f56d8c4b8c3c41c904ddf844aa"><td class="memItemLeft" align="right" valign="top"><a id="ac5fb98f56d8c4b8c3c41c904ddf844aa"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA22O_ADC0_DRV16</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a454401ca6ea915995237970ce8b5bf4e">PIN_PA22O_ADC0_DRV16</a> << 16) | MUX_PA22O_ADC0_DRV16)</td></tr>
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<tr class="separator:ac5fb98f56d8c4b8c3c41c904ddf844aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aca90a4ac2f3064278ddaecfd5d183c8e"><td class="memItemLeft" align="right" valign="top"><a id="aca90a4ac2f3064278ddaecfd5d183c8e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA22O_ADC0_DRV16</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 22)</td></tr>
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<tr class="separator:aca90a4ac2f3064278ddaecfd5d183c8e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab3f18155f6cac61bb44e45c1a766761f"><td class="memItemLeft" align="right" valign="top"><a id="ab3f18155f6cac61bb44e45c1a766761f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab3f18155f6cac61bb44e45c1a766761f">PIN_PA23O_ADC0_DRV17</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(23)</td></tr>
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<tr class="memdesc:ab3f18155f6cac61bb44e45c1a766761f"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: DRV17 on PA23 mux O. <br /></td></tr>
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<tr class="separator:ab3f18155f6cac61bb44e45c1a766761f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2bbe5f9dc0e4396b595913dcc76bb1d7"><td class="memItemLeft" align="right" valign="top"><a id="a2bbe5f9dc0e4396b595913dcc76bb1d7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA23O_ADC0_DRV17</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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<tr class="separator:a2bbe5f9dc0e4396b595913dcc76bb1d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a670d578dc37539e17bd47dbea6518b5e"><td class="memItemLeft" align="right" valign="top"><a id="a670d578dc37539e17bd47dbea6518b5e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA23O_ADC0_DRV17</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ab3f18155f6cac61bb44e45c1a766761f">PIN_PA23O_ADC0_DRV17</a> << 16) | MUX_PA23O_ADC0_DRV17)</td></tr>
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<tr class="separator:a670d578dc37539e17bd47dbea6518b5e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ade6d103c27d622dd56be8230ff9c5351"><td class="memItemLeft" align="right" valign="top"><a id="ade6d103c27d622dd56be8230ff9c5351"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA23O_ADC0_DRV17</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 23)</td></tr>
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<tr class="separator:ade6d103c27d622dd56be8230ff9c5351"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af73bd9f6eb5a0b8539fcd6e2c047bfa1"><td class="memItemLeft" align="right" valign="top"><a id="af73bd9f6eb5a0b8539fcd6e2c047bfa1"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af73bd9f6eb5a0b8539fcd6e2c047bfa1">PIN_PA27O_ADC0_DRV18</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(27)</td></tr>
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<tr class="memdesc:af73bd9f6eb5a0b8539fcd6e2c047bfa1"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: DRV18 on PA27 mux O. <br /></td></tr>
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<tr class="separator:af73bd9f6eb5a0b8539fcd6e2c047bfa1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a90ad226b00961b7427a7392c40d93880"><td class="memItemLeft" align="right" valign="top"><a id="a90ad226b00961b7427a7392c40d93880"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA27O_ADC0_DRV18</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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<tr class="separator:a90ad226b00961b7427a7392c40d93880"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae4949dd66d04c47e75fb41057a2b2439"><td class="memItemLeft" align="right" valign="top"><a id="ae4949dd66d04c47e75fb41057a2b2439"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA27O_ADC0_DRV18</b>   ((<a class="el" href="pio_2same54p20a_8h.html#af73bd9f6eb5a0b8539fcd6e2c047bfa1">PIN_PA27O_ADC0_DRV18</a> << 16) | MUX_PA27O_ADC0_DRV18)</td></tr>
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<tr class="separator:ae4949dd66d04c47e75fb41057a2b2439"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa11a0bdc01926b7d50bade4b2b995475"><td class="memItemLeft" align="right" valign="top"><a id="aa11a0bdc01926b7d50bade4b2b995475"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA27O_ADC0_DRV18</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 27)</td></tr>
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<tr class="separator:aa11a0bdc01926b7d50bade4b2b995475"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5b13862d74d69776c6422082dce6ce9c"><td class="memItemLeft" align="right" valign="top"><a id="a5b13862d74d69776c6422082dce6ce9c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5b13862d74d69776c6422082dce6ce9c">PIN_PA30O_ADC0_DRV19</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(30)</td></tr>
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<tr class="memdesc:a5b13862d74d69776c6422082dce6ce9c"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: DRV19 on PA30 mux O. <br /></td></tr>
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<tr class="separator:a5b13862d74d69776c6422082dce6ce9c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a869216ab4f1eaf04928646112bc4753e"><td class="memItemLeft" align="right" valign="top"><a id="a869216ab4f1eaf04928646112bc4753e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA30O_ADC0_DRV19</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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<tr class="separator:a869216ab4f1eaf04928646112bc4753e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a05b72c42c832dbe5ada9a9176859fccd"><td class="memItemLeft" align="right" valign="top"><a id="a05b72c42c832dbe5ada9a9176859fccd"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA30O_ADC0_DRV19</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a5b13862d74d69776c6422082dce6ce9c">PIN_PA30O_ADC0_DRV19</a> << 16) | MUX_PA30O_ADC0_DRV19)</td></tr>
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<tr class="separator:a05b72c42c832dbe5ada9a9176859fccd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4bc4a62f47de28b9fb9f55865feb9200"><td class="memItemLeft" align="right" valign="top"><a id="a4bc4a62f47de28b9fb9f55865feb9200"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA30O_ADC0_DRV19</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 30)</td></tr>
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<tr class="separator:a4bc4a62f47de28b9fb9f55865feb9200"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a003cc1eff4fd259c0decd329a64b99ad"><td class="memItemLeft" align="right" valign="top"><a id="a003cc1eff4fd259c0decd329a64b99ad"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a003cc1eff4fd259c0decd329a64b99ad">PIN_PB02O_ADC0_DRV20</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(34)</td></tr>
|
||
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<tr class="memdesc:a003cc1eff4fd259c0decd329a64b99ad"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: DRV20 on PB02 mux O. <br /></td></tr>
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<tr class="separator:a003cc1eff4fd259c0decd329a64b99ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adc68f4c2c3013a2983d1b2854ce7e6c7"><td class="memItemLeft" align="right" valign="top"><a id="adc68f4c2c3013a2983d1b2854ce7e6c7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB02O_ADC0_DRV20</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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<tr class="separator:adc68f4c2c3013a2983d1b2854ce7e6c7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8e69591bd850c647f34ed96fb79ca350"><td class="memItemLeft" align="right" valign="top"><a id="a8e69591bd850c647f34ed96fb79ca350"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB02O_ADC0_DRV20</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a003cc1eff4fd259c0decd329a64b99ad">PIN_PB02O_ADC0_DRV20</a> << 16) | MUX_PB02O_ADC0_DRV20)</td></tr>
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<tr class="separator:a8e69591bd850c647f34ed96fb79ca350"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7cfcad90cd6dbe44941a7362ed648ce3"><td class="memItemLeft" align="right" valign="top"><a id="a7cfcad90cd6dbe44941a7362ed648ce3"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB02O_ADC0_DRV20</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 2)</td></tr>
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<tr class="separator:a7cfcad90cd6dbe44941a7362ed648ce3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afe7c72552e6d62e43b4a343e71631a33"><td class="memItemLeft" align="right" valign="top"><a id="afe7c72552e6d62e43b4a343e71631a33"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#afe7c72552e6d62e43b4a343e71631a33">PIN_PB03O_ADC0_DRV21</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(35)</td></tr>
|
||
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<tr class="memdesc:afe7c72552e6d62e43b4a343e71631a33"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: DRV21 on PB03 mux O. <br /></td></tr>
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<tr class="separator:afe7c72552e6d62e43b4a343e71631a33"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab0797bc76bb265ac3a98018f58f2c77d"><td class="memItemLeft" align="right" valign="top"><a id="ab0797bc76bb265ac3a98018f58f2c77d"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB03O_ADC0_DRV21</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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<tr class="separator:ab0797bc76bb265ac3a98018f58f2c77d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aad381530da744b1d5c9ba334ae8766c2"><td class="memItemLeft" align="right" valign="top"><a id="aad381530da744b1d5c9ba334ae8766c2"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB03O_ADC0_DRV21</b>   ((<a class="el" href="pio_2same54p20a_8h.html#afe7c72552e6d62e43b4a343e71631a33">PIN_PB03O_ADC0_DRV21</a> << 16) | MUX_PB03O_ADC0_DRV21)</td></tr>
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<tr class="separator:aad381530da744b1d5c9ba334ae8766c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a39322a4145ad94b5c51a4ad9f7057a38"><td class="memItemLeft" align="right" valign="top"><a id="a39322a4145ad94b5c51a4ad9f7057a38"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB03O_ADC0_DRV21</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 3)</td></tr>
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<tr class="separator:a39322a4145ad94b5c51a4ad9f7057a38"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ace86b0a3ba39a57a320132cb794dbcd8"><td class="memItemLeft" align="right" valign="top"><a id="ace86b0a3ba39a57a320132cb794dbcd8"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ace86b0a3ba39a57a320132cb794dbcd8">PIN_PB04O_ADC0_DRV22</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(36)</td></tr>
|
||
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<tr class="memdesc:ace86b0a3ba39a57a320132cb794dbcd8"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: DRV22 on PB04 mux O. <br /></td></tr>
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<tr class="separator:ace86b0a3ba39a57a320132cb794dbcd8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a491e2f729bfb4063964609d165a45426"><td class="memItemLeft" align="right" valign="top"><a id="a491e2f729bfb4063964609d165a45426"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB04O_ADC0_DRV22</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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<tr class="memitem:aee464968517d062e48a729dc7ed40698"><td class="memItemLeft" align="right" valign="top"><a id="aee464968517d062e48a729dc7ed40698"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB04O_ADC0_DRV22</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ace86b0a3ba39a57a320132cb794dbcd8">PIN_PB04O_ADC0_DRV22</a> << 16) | MUX_PB04O_ADC0_DRV22)</td></tr>
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<tr class="memitem:ae6ccfd86043f40d3aa0e2a55510cba81"><td class="memItemLeft" align="right" valign="top"><a id="ae6ccfd86043f40d3aa0e2a55510cba81"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB04O_ADC0_DRV22</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 4)</td></tr>
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<tr class="separator:ae6ccfd86043f40d3aa0e2a55510cba81"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abb812dd33cb215819b02fde8dc83e2b3"><td class="memItemLeft" align="right" valign="top"><a id="abb812dd33cb215819b02fde8dc83e2b3"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#abb812dd33cb215819b02fde8dc83e2b3">PIN_PB05O_ADC0_DRV23</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(37)</td></tr>
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<tr class="memdesc:abb812dd33cb215819b02fde8dc83e2b3"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: DRV23 on PB05 mux O. <br /></td></tr>
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<tr class="separator:abb812dd33cb215819b02fde8dc83e2b3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a91caddaaed77e07fe813ad1c38c5ee77"><td class="memItemLeft" align="right" valign="top"><a id="a91caddaaed77e07fe813ad1c38c5ee77"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB05O_ADC0_DRV23</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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<tr class="separator:a91caddaaed77e07fe813ad1c38c5ee77"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0d0b5131dca0de0326141c9bad9951ca"><td class="memItemLeft" align="right" valign="top"><a id="a0d0b5131dca0de0326141c9bad9951ca"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB05O_ADC0_DRV23</b>   ((<a class="el" href="pio_2same54p20a_8h.html#abb812dd33cb215819b02fde8dc83e2b3">PIN_PB05O_ADC0_DRV23</a> << 16) | MUX_PB05O_ADC0_DRV23)</td></tr>
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<tr class="separator:a0d0b5131dca0de0326141c9bad9951ca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a00f1dfbf3c38d9faa9ade2b9b71112ad"><td class="memItemLeft" align="right" valign="top"><a id="a00f1dfbf3c38d9faa9ade2b9b71112ad"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB05O_ADC0_DRV23</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 5)</td></tr>
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<tr class="separator:a00f1dfbf3c38d9faa9ade2b9b71112ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aee8e93606402ce8538ff388f59a4d8a1"><td class="memItemLeft" align="right" valign="top"><a id="aee8e93606402ce8538ff388f59a4d8a1"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aee8e93606402ce8538ff388f59a4d8a1">PIN_PB06O_ADC0_DRV24</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(38)</td></tr>
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||
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<tr class="memdesc:aee8e93606402ce8538ff388f59a4d8a1"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: DRV24 on PB06 mux O. <br /></td></tr>
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<tr class="separator:aee8e93606402ce8538ff388f59a4d8a1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa78ac60c4ed178d0f0c7cf52bd269d3a"><td class="memItemLeft" align="right" valign="top"><a id="aa78ac60c4ed178d0f0c7cf52bd269d3a"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB06O_ADC0_DRV24</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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<tr class="separator:aa78ac60c4ed178d0f0c7cf52bd269d3a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a67e476a0b74cba274baa451ce488ad95"><td class="memItemLeft" align="right" valign="top"><a id="a67e476a0b74cba274baa451ce488ad95"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB06O_ADC0_DRV24</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aee8e93606402ce8538ff388f59a4d8a1">PIN_PB06O_ADC0_DRV24</a> << 16) | MUX_PB06O_ADC0_DRV24)</td></tr>
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<tr class="separator:a67e476a0b74cba274baa451ce488ad95"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae27f56d7987bd7347be467ffae1dc3ff"><td class="memItemLeft" align="right" valign="top"><a id="ae27f56d7987bd7347be467ffae1dc3ff"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB06O_ADC0_DRV24</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 6)</td></tr>
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<tr class="separator:ae27f56d7987bd7347be467ffae1dc3ff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa04c82374f3c204429c9bdd25727ffd3"><td class="memItemLeft" align="right" valign="top"><a id="aa04c82374f3c204429c9bdd25727ffd3"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa04c82374f3c204429c9bdd25727ffd3">PIN_PB07O_ADC0_DRV25</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(39)</td></tr>
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||
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<tr class="memdesc:aa04c82374f3c204429c9bdd25727ffd3"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: DRV25 on PB07 mux O. <br /></td></tr>
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<tr class="separator:aa04c82374f3c204429c9bdd25727ffd3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abf7ea0c604753de3dbf65daf3339889a"><td class="memItemLeft" align="right" valign="top"><a id="abf7ea0c604753de3dbf65daf3339889a"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB07O_ADC0_DRV25</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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<tr class="separator:abf7ea0c604753de3dbf65daf3339889a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afb5c414cbe9e3dbfb10a02f9ee04acfa"><td class="memItemLeft" align="right" valign="top"><a id="afb5c414cbe9e3dbfb10a02f9ee04acfa"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB07O_ADC0_DRV25</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aa04c82374f3c204429c9bdd25727ffd3">PIN_PB07O_ADC0_DRV25</a> << 16) | MUX_PB07O_ADC0_DRV25)</td></tr>
|
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<tr class="separator:afb5c414cbe9e3dbfb10a02f9ee04acfa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad3185c756d8fd425b7c164e327233234"><td class="memItemLeft" align="right" valign="top"><a id="ad3185c756d8fd425b7c164e327233234"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB07O_ADC0_DRV25</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 7)</td></tr>
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||
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<tr class="separator:ad3185c756d8fd425b7c164e327233234"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac13236776ef13bbb246a38db5fcedcbe"><td class="memItemLeft" align="right" valign="top"><a id="ac13236776ef13bbb246a38db5fcedcbe"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac13236776ef13bbb246a38db5fcedcbe">PIN_PB12O_ADC0_DRV26</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(44)</td></tr>
|
||
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<tr class="memdesc:ac13236776ef13bbb246a38db5fcedcbe"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: DRV26 on PB12 mux O. <br /></td></tr>
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<tr class="separator:ac13236776ef13bbb246a38db5fcedcbe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4f375b32e3c9cdd0e2ddc16b4a9874c4"><td class="memItemLeft" align="right" valign="top"><a id="a4f375b32e3c9cdd0e2ddc16b4a9874c4"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB12O_ADC0_DRV26</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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||
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<tr class="separator:a4f375b32e3c9cdd0e2ddc16b4a9874c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0b851a08d0552cfe5226c3f4edb9a221"><td class="memItemLeft" align="right" valign="top"><a id="a0b851a08d0552cfe5226c3f4edb9a221"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB12O_ADC0_DRV26</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ac13236776ef13bbb246a38db5fcedcbe">PIN_PB12O_ADC0_DRV26</a> << 16) | MUX_PB12O_ADC0_DRV26)</td></tr>
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<tr class="separator:a0b851a08d0552cfe5226c3f4edb9a221"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afa17b6aaacd61dedb6d43e90f56bb0c4"><td class="memItemLeft" align="right" valign="top"><a id="afa17b6aaacd61dedb6d43e90f56bb0c4"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB12O_ADC0_DRV26</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 12)</td></tr>
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||
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<tr class="separator:afa17b6aaacd61dedb6d43e90f56bb0c4"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a538d061641af63c05beca44057cb89d4"><td class="memItemLeft" align="right" valign="top"><a id="a538d061641af63c05beca44057cb89d4"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a538d061641af63c05beca44057cb89d4">PIN_PB13O_ADC0_DRV27</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(45)</td></tr>
|
||
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<tr class="memdesc:a538d061641af63c05beca44057cb89d4"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: DRV27 on PB13 mux O. <br /></td></tr>
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<tr class="separator:a538d061641af63c05beca44057cb89d4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad23e3d2f3da03aa5b2f38525b3bdbb1c"><td class="memItemLeft" align="right" valign="top"><a id="ad23e3d2f3da03aa5b2f38525b3bdbb1c"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB13O_ADC0_DRV27</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
|
||
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<tr class="separator:ad23e3d2f3da03aa5b2f38525b3bdbb1c"><td class="memSeparator" colspan="2"> </td></tr>
|
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<tr class="memitem:a66fc9a9c4e1ec9e5eec3dc508d7e4ffb"><td class="memItemLeft" align="right" valign="top"><a id="a66fc9a9c4e1ec9e5eec3dc508d7e4ffb"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB13O_ADC0_DRV27</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a538d061641af63c05beca44057cb89d4">PIN_PB13O_ADC0_DRV27</a> << 16) | MUX_PB13O_ADC0_DRV27)</td></tr>
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||
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<tr class="separator:a66fc9a9c4e1ec9e5eec3dc508d7e4ffb"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a5f9489298fa2608db97267a1dc763514"><td class="memItemLeft" align="right" valign="top"><a id="a5f9489298fa2608db97267a1dc763514"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB13O_ADC0_DRV27</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 13)</td></tr>
|
||
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<tr class="separator:a5f9489298fa2608db97267a1dc763514"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:ac16647a2f03a27eaaf9c342ea72a12eb"><td class="memItemLeft" align="right" valign="top"><a id="ac16647a2f03a27eaaf9c342ea72a12eb"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac16647a2f03a27eaaf9c342ea72a12eb">PIN_PB14O_ADC0_DRV28</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(46)</td></tr>
|
||
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<tr class="memdesc:ac16647a2f03a27eaaf9c342ea72a12eb"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: DRV28 on PB14 mux O. <br /></td></tr>
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<tr class="separator:ac16647a2f03a27eaaf9c342ea72a12eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abc7e741ab2b45e8d9e75771cd93ac02c"><td class="memItemLeft" align="right" valign="top"><a id="abc7e741ab2b45e8d9e75771cd93ac02c"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB14O_ADC0_DRV28</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
|
||
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<tr class="separator:abc7e741ab2b45e8d9e75771cd93ac02c"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a2010b8051f968f66678efceb23fe7880"><td class="memItemLeft" align="right" valign="top"><a id="a2010b8051f968f66678efceb23fe7880"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB14O_ADC0_DRV28</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ac16647a2f03a27eaaf9c342ea72a12eb">PIN_PB14O_ADC0_DRV28</a> << 16) | MUX_PB14O_ADC0_DRV28)</td></tr>
|
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<tr class="separator:a2010b8051f968f66678efceb23fe7880"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a980f078ef80ee7e62a9dac2e54ad622d"><td class="memItemLeft" align="right" valign="top"><a id="a980f078ef80ee7e62a9dac2e54ad622d"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB14O_ADC0_DRV28</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 14)</td></tr>
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||
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<tr class="separator:a980f078ef80ee7e62a9dac2e54ad622d"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:aec373d14aee3d7a0ee120db4062b96fd"><td class="memItemLeft" align="right" valign="top"><a id="aec373d14aee3d7a0ee120db4062b96fd"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aec373d14aee3d7a0ee120db4062b96fd">PIN_PB15O_ADC0_DRV29</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(47)</td></tr>
|
||
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<tr class="memdesc:aec373d14aee3d7a0ee120db4062b96fd"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: DRV29 on PB15 mux O. <br /></td></tr>
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<tr class="separator:aec373d14aee3d7a0ee120db4062b96fd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6f59e5d599a64e0933f5c4f69f141c7e"><td class="memItemLeft" align="right" valign="top"><a id="a6f59e5d599a64e0933f5c4f69f141c7e"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB15O_ADC0_DRV29</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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||
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<tr class="separator:a6f59e5d599a64e0933f5c4f69f141c7e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab8c2529955874577f46c897f46d0b15c"><td class="memItemLeft" align="right" valign="top"><a id="ab8c2529955874577f46c897f46d0b15c"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB15O_ADC0_DRV29</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aec373d14aee3d7a0ee120db4062b96fd">PIN_PB15O_ADC0_DRV29</a> << 16) | MUX_PB15O_ADC0_DRV29)</td></tr>
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<tr class="separator:ab8c2529955874577f46c897f46d0b15c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a57ef8bb1a70680bd05a256a363e5855d"><td class="memItemLeft" align="right" valign="top"><a id="a57ef8bb1a70680bd05a256a363e5855d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB15O_ADC0_DRV29</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 15)</td></tr>
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<tr class="separator:a57ef8bb1a70680bd05a256a363e5855d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5e747c2a7f8e247f3240ac56ed01b801"><td class="memItemLeft" align="right" valign="top"><a id="a5e747c2a7f8e247f3240ac56ed01b801"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5e747c2a7f8e247f3240ac56ed01b801">PIN_PB00O_ADC0_DRV30</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(32)</td></tr>
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||
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<tr class="memdesc:a5e747c2a7f8e247f3240ac56ed01b801"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: DRV30 on PB00 mux O. <br /></td></tr>
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<tr class="separator:a5e747c2a7f8e247f3240ac56ed01b801"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aac01298138f22bc551ec26ab90b9db4c"><td class="memItemLeft" align="right" valign="top"><a id="aac01298138f22bc551ec26ab90b9db4c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB00O_ADC0_DRV30</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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<tr class="separator:aac01298138f22bc551ec26ab90b9db4c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5695940bfbf60f48f2b2a3deb88a3625"><td class="memItemLeft" align="right" valign="top"><a id="a5695940bfbf60f48f2b2a3deb88a3625"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB00O_ADC0_DRV30</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a5e747c2a7f8e247f3240ac56ed01b801">PIN_PB00O_ADC0_DRV30</a> << 16) | MUX_PB00O_ADC0_DRV30)</td></tr>
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<tr class="separator:a5695940bfbf60f48f2b2a3deb88a3625"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6ab23770c4698967fac8350007fcec1c"><td class="memItemLeft" align="right" valign="top"><a id="a6ab23770c4698967fac8350007fcec1c"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB00O_ADC0_DRV30</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 0)</td></tr>
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||
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<tr class="separator:a6ab23770c4698967fac8350007fcec1c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae6cedeb179e669ab479adef553134390"><td class="memItemLeft" align="right" valign="top"><a id="ae6cedeb179e669ab479adef553134390"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae6cedeb179e669ab479adef553134390">PIN_PB01O_ADC0_DRV31</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(33)</td></tr>
|
||
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<tr class="memdesc:ae6cedeb179e669ab479adef553134390"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: DRV31 on PB01 mux O. <br /></td></tr>
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<tr class="separator:ae6cedeb179e669ab479adef553134390"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae3a5ee78af32e04e2a3d85977911d394"><td class="memItemLeft" align="right" valign="top"><a id="ae3a5ee78af32e04e2a3d85977911d394"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB01O_ADC0_DRV31</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
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||
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<tr class="separator:ae3a5ee78af32e04e2a3d85977911d394"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab34c59a98f2dfcfbabf3ae59d60c2505"><td class="memItemLeft" align="right" valign="top"><a id="ab34c59a98f2dfcfbabf3ae59d60c2505"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB01O_ADC0_DRV31</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ae6cedeb179e669ab479adef553134390">PIN_PB01O_ADC0_DRV31</a> << 16) | MUX_PB01O_ADC0_DRV31)</td></tr>
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<tr class="separator:ab34c59a98f2dfcfbabf3ae59d60c2505"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9def61ac4af5a652e20712bee0ef9b04"><td class="memItemLeft" align="right" valign="top"><a id="a9def61ac4af5a652e20712bee0ef9b04"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB01O_ADC0_DRV31</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 1)</td></tr>
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||
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<tr class="separator:a9def61ac4af5a652e20712bee0ef9b04"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a784c2f54be152ea6835656c403756a47"><td class="memItemLeft" align="right" valign="top"><a id="a784c2f54be152ea6835656c403756a47"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a784c2f54be152ea6835656c403756a47">PIN_PA03B_ADC0_PTCXY0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(3)</td></tr>
|
||
|
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<tr class="memdesc:a784c2f54be152ea6835656c403756a47"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: PTCXY0 on PA03 mux B. <br /></td></tr>
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<tr class="separator:a784c2f54be152ea6835656c403756a47"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a7b72dfcf63ecef389a221063c6a61037"><td class="memItemLeft" align="right" valign="top"><a id="a7b72dfcf63ecef389a221063c6a61037"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA03B_ADC0_PTCXY0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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||
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<tr class="separator:a7b72dfcf63ecef389a221063c6a61037"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:af49be4adea65fe31358dc8db181311b0"><td class="memItemLeft" align="right" valign="top"><a id="af49be4adea65fe31358dc8db181311b0"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA03B_ADC0_PTCXY0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a784c2f54be152ea6835656c403756a47">PIN_PA03B_ADC0_PTCXY0</a> << 16) | MUX_PA03B_ADC0_PTCXY0)</td></tr>
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||
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<tr class="separator:af49be4adea65fe31358dc8db181311b0"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a9eb251baccd313a4fd45c6549e18b7e6"><td class="memItemLeft" align="right" valign="top"><a id="a9eb251baccd313a4fd45c6549e18b7e6"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA03B_ADC0_PTCXY0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 3)</td></tr>
|
||
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<tr class="separator:a9eb251baccd313a4fd45c6549e18b7e6"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a67e29c1596d2fd8c9eecefaf9c786496"><td class="memItemLeft" align="right" valign="top"><a id="a67e29c1596d2fd8c9eecefaf9c786496"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a67e29c1596d2fd8c9eecefaf9c786496">PIN_PB08B_ADC0_PTCXY1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(40)</td></tr>
|
||
|
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<tr class="memdesc:a67e29c1596d2fd8c9eecefaf9c786496"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: PTCXY1 on PB08 mux B. <br /></td></tr>
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||
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<tr class="separator:a67e29c1596d2fd8c9eecefaf9c786496"><td class="memSeparator" colspan="2"> </td></tr>
|
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<tr class="memitem:ac3e55b5ee07cc8a757087935a734dc5e"><td class="memItemLeft" align="right" valign="top"><a id="ac3e55b5ee07cc8a757087935a734dc5e"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB08B_ADC0_PTCXY1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
|
||
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<tr class="separator:ac3e55b5ee07cc8a757087935a734dc5e"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a23b2b8cdd7ef16465678a22b94bdc73d"><td class="memItemLeft" align="right" valign="top"><a id="a23b2b8cdd7ef16465678a22b94bdc73d"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB08B_ADC0_PTCXY1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a67e29c1596d2fd8c9eecefaf9c786496">PIN_PB08B_ADC0_PTCXY1</a> << 16) | MUX_PB08B_ADC0_PTCXY1)</td></tr>
|
||
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<tr class="separator:a23b2b8cdd7ef16465678a22b94bdc73d"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:aa87d549ac2a8c03b29719edd2aa5ec53"><td class="memItemLeft" align="right" valign="top"><a id="aa87d549ac2a8c03b29719edd2aa5ec53"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB08B_ADC0_PTCXY1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 8)</td></tr>
|
||
|
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<tr class="separator:aa87d549ac2a8c03b29719edd2aa5ec53"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a25fdcc3c5288cdf0bc5d486851570c77"><td class="memItemLeft" align="right" valign="top"><a id="a25fdcc3c5288cdf0bc5d486851570c77"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a25fdcc3c5288cdf0bc5d486851570c77">PIN_PB09B_ADC0_PTCXY2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(41)</td></tr>
|
||
|
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<tr class="memdesc:a25fdcc3c5288cdf0bc5d486851570c77"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: PTCXY2 on PB09 mux B. <br /></td></tr>
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||
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<tr class="separator:a25fdcc3c5288cdf0bc5d486851570c77"><td class="memSeparator" colspan="2"> </td></tr>
|
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<tr class="memitem:a05337afb5263dd878351168cdd7f2b21"><td class="memItemLeft" align="right" valign="top"><a id="a05337afb5263dd878351168cdd7f2b21"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB09B_ADC0_PTCXY2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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||
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<tr class="separator:a05337afb5263dd878351168cdd7f2b21"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:af6e0598d228a6d5d8addfb97d0a952bf"><td class="memItemLeft" align="right" valign="top"><a id="af6e0598d228a6d5d8addfb97d0a952bf"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB09B_ADC0_PTCXY2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a25fdcc3c5288cdf0bc5d486851570c77">PIN_PB09B_ADC0_PTCXY2</a> << 16) | MUX_PB09B_ADC0_PTCXY2)</td></tr>
|
||
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<tr class="separator:af6e0598d228a6d5d8addfb97d0a952bf"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a88f63bcb8dfbb0555432dbf4f58d6a5e"><td class="memItemLeft" align="right" valign="top"><a id="a88f63bcb8dfbb0555432dbf4f58d6a5e"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB09B_ADC0_PTCXY2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 9)</td></tr>
|
||
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<tr class="separator:a88f63bcb8dfbb0555432dbf4f58d6a5e"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:ac1a6b19dbcb239d4355bf74722462899"><td class="memItemLeft" align="right" valign="top"><a id="ac1a6b19dbcb239d4355bf74722462899"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac1a6b19dbcb239d4355bf74722462899">PIN_PA04B_ADC0_PTCXY3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(4)</td></tr>
|
||
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<tr class="memdesc:ac1a6b19dbcb239d4355bf74722462899"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: PTCXY3 on PA04 mux B. <br /></td></tr>
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<tr class="separator:ac1a6b19dbcb239d4355bf74722462899"><td class="memSeparator" colspan="2"> </td></tr>
|
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<tr class="memitem:a256e622de8c88d61d5b70b91e1f9b34e"><td class="memItemLeft" align="right" valign="top"><a id="a256e622de8c88d61d5b70b91e1f9b34e"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA04B_ADC0_PTCXY3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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||
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<tr class="separator:a256e622de8c88d61d5b70b91e1f9b34e"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a9c0dfaf5e86b0f4fc9653d2be22a6099"><td class="memItemLeft" align="right" valign="top"><a id="a9c0dfaf5e86b0f4fc9653d2be22a6099"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA04B_ADC0_PTCXY3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ac1a6b19dbcb239d4355bf74722462899">PIN_PA04B_ADC0_PTCXY3</a> << 16) | MUX_PA04B_ADC0_PTCXY3)</td></tr>
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<tr class="separator:a9c0dfaf5e86b0f4fc9653d2be22a6099"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a767cdb4652b14abea01a1774abe5a0e9"><td class="memItemLeft" align="right" valign="top"><a id="a767cdb4652b14abea01a1774abe5a0e9"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA04B_ADC0_PTCXY3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 4)</td></tr>
|
||
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<tr class="separator:a767cdb4652b14abea01a1774abe5a0e9"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:abb0ae97ab16dc80fc57a8a4d33108244"><td class="memItemLeft" align="right" valign="top"><a id="abb0ae97ab16dc80fc57a8a4d33108244"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#abb0ae97ab16dc80fc57a8a4d33108244">PIN_PA06B_ADC0_PTCXY4</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
|
||
|
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<tr class="memdesc:abb0ae97ab16dc80fc57a8a4d33108244"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: PTCXY4 on PA06 mux B. <br /></td></tr>
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||
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<tr class="separator:abb0ae97ab16dc80fc57a8a4d33108244"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3228fad78199f63dac96da9f518f4d4a"><td class="memItemLeft" align="right" valign="top"><a id="a3228fad78199f63dac96da9f518f4d4a"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA06B_ADC0_PTCXY4</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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||
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<tr class="separator:a3228fad78199f63dac96da9f518f4d4a"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:ae0b480f98c1989f3c36fa4a8b9dd7395"><td class="memItemLeft" align="right" valign="top"><a id="ae0b480f98c1989f3c36fa4a8b9dd7395"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA06B_ADC0_PTCXY4</b>   ((<a class="el" href="pio_2same54p20a_8h.html#abb0ae97ab16dc80fc57a8a4d33108244">PIN_PA06B_ADC0_PTCXY4</a> << 16) | MUX_PA06B_ADC0_PTCXY4)</td></tr>
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<tr class="separator:ae0b480f98c1989f3c36fa4a8b9dd7395"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a8464e3f9f86d559416ed73e545400144"><td class="memItemLeft" align="right" valign="top"><a id="a8464e3f9f86d559416ed73e545400144"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA06B_ADC0_PTCXY4</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 6)</td></tr>
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||
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<tr class="separator:a8464e3f9f86d559416ed73e545400144"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a574c51a79a4c98847c325639af7b6547"><td class="memItemLeft" align="right" valign="top"><a id="a574c51a79a4c98847c325639af7b6547"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a574c51a79a4c98847c325639af7b6547">PIN_PA07B_ADC0_PTCXY5</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
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<tr class="memdesc:a574c51a79a4c98847c325639af7b6547"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: PTCXY5 on PA07 mux B. <br /></td></tr>
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<tr class="separator:a574c51a79a4c98847c325639af7b6547"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a816f255848a7d68f78900c25768b405e"><td class="memItemLeft" align="right" valign="top"><a id="a816f255848a7d68f78900c25768b405e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA07B_ADC0_PTCXY5</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:a816f255848a7d68f78900c25768b405e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2149cffa1b8863570411b1245ca04cc8"><td class="memItemLeft" align="right" valign="top"><a id="a2149cffa1b8863570411b1245ca04cc8"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA07B_ADC0_PTCXY5</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a574c51a79a4c98847c325639af7b6547">PIN_PA07B_ADC0_PTCXY5</a> << 16) | MUX_PA07B_ADC0_PTCXY5)</td></tr>
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<tr class="separator:a2149cffa1b8863570411b1245ca04cc8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5e81a55d44a354c2bc913f4ecdad46d6"><td class="memItemLeft" align="right" valign="top"><a id="a5e81a55d44a354c2bc913f4ecdad46d6"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA07B_ADC0_PTCXY5</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 7)</td></tr>
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<tr class="separator:a5e81a55d44a354c2bc913f4ecdad46d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7dea306e5d584db7e6b7c442268579e5"><td class="memItemLeft" align="right" valign="top"><a id="a7dea306e5d584db7e6b7c442268579e5"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7dea306e5d584db7e6b7c442268579e5">PIN_PA08B_ADC0_PTCXY6</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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||
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<tr class="memdesc:a7dea306e5d584db7e6b7c442268579e5"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: PTCXY6 on PA08 mux B. <br /></td></tr>
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<tr class="separator:a7dea306e5d584db7e6b7c442268579e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a94a051a56a786fd20c4c708c02cbfa8b"><td class="memItemLeft" align="right" valign="top"><a id="a94a051a56a786fd20c4c708c02cbfa8b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA08B_ADC0_PTCXY6</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:a94a051a56a786fd20c4c708c02cbfa8b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a76728d4fe4f7fd2a93866ff543fead31"><td class="memItemLeft" align="right" valign="top"><a id="a76728d4fe4f7fd2a93866ff543fead31"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA08B_ADC0_PTCXY6</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a7dea306e5d584db7e6b7c442268579e5">PIN_PA08B_ADC0_PTCXY6</a> << 16) | MUX_PA08B_ADC0_PTCXY6)</td></tr>
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<tr class="separator:a76728d4fe4f7fd2a93866ff543fead31"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5af383b38c8858034aae978c55d281ce"><td class="memItemLeft" align="right" valign="top"><a id="a5af383b38c8858034aae978c55d281ce"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA08B_ADC0_PTCXY6</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 8)</td></tr>
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<tr class="separator:a5af383b38c8858034aae978c55d281ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7c252bf52c87d70ef10d33cec58cedb1"><td class="memItemLeft" align="right" valign="top"><a id="a7c252bf52c87d70ef10d33cec58cedb1"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7c252bf52c87d70ef10d33cec58cedb1">PIN_PA09B_ADC0_PTCXY7</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
|
||
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<tr class="memdesc:a7c252bf52c87d70ef10d33cec58cedb1"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: PTCXY7 on PA09 mux B. <br /></td></tr>
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<tr class="separator:a7c252bf52c87d70ef10d33cec58cedb1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5defd9294726f0d6bdd3fbfaac348fe4"><td class="memItemLeft" align="right" valign="top"><a id="a5defd9294726f0d6bdd3fbfaac348fe4"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA09B_ADC0_PTCXY7</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:a5defd9294726f0d6bdd3fbfaac348fe4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a03c99192d930308d20591b2997ace4dc"><td class="memItemLeft" align="right" valign="top"><a id="a03c99192d930308d20591b2997ace4dc"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA09B_ADC0_PTCXY7</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a7c252bf52c87d70ef10d33cec58cedb1">PIN_PA09B_ADC0_PTCXY7</a> << 16) | MUX_PA09B_ADC0_PTCXY7)</td></tr>
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<tr class="separator:a03c99192d930308d20591b2997ace4dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a92fff8bd218b65958df6b98c2afdc142"><td class="memItemLeft" align="right" valign="top"><a id="a92fff8bd218b65958df6b98c2afdc142"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA09B_ADC0_PTCXY7</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 9)</td></tr>
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<tr class="separator:a92fff8bd218b65958df6b98c2afdc142"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa05ebecf74dc0f686d5785e096fb01cf"><td class="memItemLeft" align="right" valign="top"><a id="aa05ebecf74dc0f686d5785e096fb01cf"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa05ebecf74dc0f686d5785e096fb01cf">PIN_PA10B_ADC0_PTCXY8</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
|
||
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<tr class="memdesc:aa05ebecf74dc0f686d5785e096fb01cf"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: PTCXY8 on PA10 mux B. <br /></td></tr>
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<tr class="separator:aa05ebecf74dc0f686d5785e096fb01cf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aff1d7cbd9950b6798d68fa82c02898f4"><td class="memItemLeft" align="right" valign="top"><a id="aff1d7cbd9950b6798d68fa82c02898f4"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA10B_ADC0_PTCXY8</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:aff1d7cbd9950b6798d68fa82c02898f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7e97eee788b8c361fd0d7d9710e6587c"><td class="memItemLeft" align="right" valign="top"><a id="a7e97eee788b8c361fd0d7d9710e6587c"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA10B_ADC0_PTCXY8</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aa05ebecf74dc0f686d5785e096fb01cf">PIN_PA10B_ADC0_PTCXY8</a> << 16) | MUX_PA10B_ADC0_PTCXY8)</td></tr>
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<tr class="separator:a7e97eee788b8c361fd0d7d9710e6587c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5c3e316db17985d92225848e7e1308b0"><td class="memItemLeft" align="right" valign="top"><a id="a5c3e316db17985d92225848e7e1308b0"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA10B_ADC0_PTCXY8</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 10)</td></tr>
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||
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<tr class="separator:a5c3e316db17985d92225848e7e1308b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a29e2445c680dd2b0983e8fb37db913a3"><td class="memItemLeft" align="right" valign="top"><a id="a29e2445c680dd2b0983e8fb37db913a3"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a29e2445c680dd2b0983e8fb37db913a3">PIN_PA11B_ADC0_PTCXY9</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
|
||
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<tr class="memdesc:a29e2445c680dd2b0983e8fb37db913a3"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: PTCXY9 on PA11 mux B. <br /></td></tr>
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<tr class="separator:a29e2445c680dd2b0983e8fb37db913a3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6387fea32b9c9d3262bdbaf14f8d8815"><td class="memItemLeft" align="right" valign="top"><a id="a6387fea32b9c9d3262bdbaf14f8d8815"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA11B_ADC0_PTCXY9</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:a6387fea32b9c9d3262bdbaf14f8d8815"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1d27405ab7fba0ca61c1d5e3cfe5561c"><td class="memItemLeft" align="right" valign="top"><a id="a1d27405ab7fba0ca61c1d5e3cfe5561c"></a>
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA11B_ADC0_PTCXY9</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a29e2445c680dd2b0983e8fb37db913a3">PIN_PA11B_ADC0_PTCXY9</a> << 16) | MUX_PA11B_ADC0_PTCXY9)</td></tr>
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<tr class="separator:a1d27405ab7fba0ca61c1d5e3cfe5561c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab5e1a7434b36b0700dca6a9b72a51d70"><td class="memItemLeft" align="right" valign="top"><a id="ab5e1a7434b36b0700dca6a9b72a51d70"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA11B_ADC0_PTCXY9</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 11)</td></tr>
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||
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<tr class="separator:ab5e1a7434b36b0700dca6a9b72a51d70"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae46ab53aa73b234bb352838bc2001053"><td class="memItemLeft" align="right" valign="top"><a id="ae46ab53aa73b234bb352838bc2001053"></a>
|
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae46ab53aa73b234bb352838bc2001053">PIN_PA16B_ADC0_PTCXY10</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(16)</td></tr>
|
||
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<tr class="memdesc:ae46ab53aa73b234bb352838bc2001053"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: PTCXY10 on PA16 mux B. <br /></td></tr>
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<tr class="separator:ae46ab53aa73b234bb352838bc2001053"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4115c1327cd6cf512b2addda8abb1af6"><td class="memItemLeft" align="right" valign="top"><a id="a4115c1327cd6cf512b2addda8abb1af6"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA16B_ADC0_PTCXY10</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:a4115c1327cd6cf512b2addda8abb1af6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa15c8eca2a838926b1204fd8fd34ebd5"><td class="memItemLeft" align="right" valign="top"><a id="aa15c8eca2a838926b1204fd8fd34ebd5"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA16B_ADC0_PTCXY10</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ae46ab53aa73b234bb352838bc2001053">PIN_PA16B_ADC0_PTCXY10</a> << 16) | MUX_PA16B_ADC0_PTCXY10)</td></tr>
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<tr class="separator:aa15c8eca2a838926b1204fd8fd34ebd5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5ed7d69b20e1d562dd5b26220da98122"><td class="memItemLeft" align="right" valign="top"><a id="a5ed7d69b20e1d562dd5b26220da98122"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA16B_ADC0_PTCXY10</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 16)</td></tr>
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<tr class="separator:a5ed7d69b20e1d562dd5b26220da98122"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a85397e94bd7137771f4cd4f97e174139"><td class="memItemLeft" align="right" valign="top"><a id="a85397e94bd7137771f4cd4f97e174139"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a85397e94bd7137771f4cd4f97e174139">PIN_PA17B_ADC0_PTCXY11</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(17)</td></tr>
|
||
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<tr class="memdesc:a85397e94bd7137771f4cd4f97e174139"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: PTCXY11 on PA17 mux B. <br /></td></tr>
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<tr class="separator:a85397e94bd7137771f4cd4f97e174139"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a566674d56575e3c0cb6803336a751597"><td class="memItemLeft" align="right" valign="top"><a id="a566674d56575e3c0cb6803336a751597"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA17B_ADC0_PTCXY11</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:a566674d56575e3c0cb6803336a751597"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3c70bb5eede774b9d6d6e8a0c779ffec"><td class="memItemLeft" align="right" valign="top"><a id="a3c70bb5eede774b9d6d6e8a0c779ffec"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA17B_ADC0_PTCXY11</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a85397e94bd7137771f4cd4f97e174139">PIN_PA17B_ADC0_PTCXY11</a> << 16) | MUX_PA17B_ADC0_PTCXY11)</td></tr>
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<tr class="separator:a3c70bb5eede774b9d6d6e8a0c779ffec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9f02cfafbd53b656241a273da66ef269"><td class="memItemLeft" align="right" valign="top"><a id="a9f02cfafbd53b656241a273da66ef269"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA17B_ADC0_PTCXY11</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 17)</td></tr>
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||
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<tr class="separator:a9f02cfafbd53b656241a273da66ef269"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0b8a683d2b87230fe559ad1e302ed97e"><td class="memItemLeft" align="right" valign="top"><a id="a0b8a683d2b87230fe559ad1e302ed97e"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0b8a683d2b87230fe559ad1e302ed97e">PIN_PA18B_ADC0_PTCXY12</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(18)</td></tr>
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<tr class="memdesc:a0b8a683d2b87230fe559ad1e302ed97e"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: PTCXY12 on PA18 mux B. <br /></td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA18B_ADC0_PTCXY12</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="memitem:afb13ae9c7ff8e8bafd2a606090bc4a93"><td class="memItemLeft" align="right" valign="top"><a id="afb13ae9c7ff8e8bafd2a606090bc4a93"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA18B_ADC0_PTCXY12</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a0b8a683d2b87230fe559ad1e302ed97e">PIN_PA18B_ADC0_PTCXY12</a> << 16) | MUX_PA18B_ADC0_PTCXY12)</td></tr>
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<tr class="memitem:a4d0b5d8aefd67aafd345f0dc5afff52a"><td class="memItemLeft" align="right" valign="top"><a id="a4d0b5d8aefd67aafd345f0dc5afff52a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA18B_ADC0_PTCXY12</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 18)</td></tr>
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<tr class="separator:a4d0b5d8aefd67aafd345f0dc5afff52a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a480711f3291436de332bb57cc164620a"><td class="memItemLeft" align="right" valign="top"><a id="a480711f3291436de332bb57cc164620a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a480711f3291436de332bb57cc164620a">PIN_PA19B_ADC0_PTCXY13</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(19)</td></tr>
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<tr class="memdesc:a480711f3291436de332bb57cc164620a"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: PTCXY13 on PA19 mux B. <br /></td></tr>
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<tr class="separator:a480711f3291436de332bb57cc164620a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9cfc0aa8117116643d078e8daa5fb395"><td class="memItemLeft" align="right" valign="top"><a id="a9cfc0aa8117116643d078e8daa5fb395"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA19B_ADC0_PTCXY13</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:a9cfc0aa8117116643d078e8daa5fb395"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aba10e85eaf7a6ffe56c79e465c66510e"><td class="memItemLeft" align="right" valign="top"><a id="aba10e85eaf7a6ffe56c79e465c66510e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA19B_ADC0_PTCXY13</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a480711f3291436de332bb57cc164620a">PIN_PA19B_ADC0_PTCXY13</a> << 16) | MUX_PA19B_ADC0_PTCXY13)</td></tr>
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<tr class="memitem:a89882257b63d7524ac65be0c046dbf75"><td class="memItemLeft" align="right" valign="top"><a id="a89882257b63d7524ac65be0c046dbf75"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA19B_ADC0_PTCXY13</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 19)</td></tr>
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<tr class="separator:a89882257b63d7524ac65be0c046dbf75"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a31706dfe73b7a197d56c975ea9bd11f1"><td class="memItemLeft" align="right" valign="top"><a id="a31706dfe73b7a197d56c975ea9bd11f1"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a31706dfe73b7a197d56c975ea9bd11f1">PIN_PA20B_ADC0_PTCXY14</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(20)</td></tr>
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<tr class="memdesc:a31706dfe73b7a197d56c975ea9bd11f1"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: PTCXY14 on PA20 mux B. <br /></td></tr>
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<tr class="separator:a31706dfe73b7a197d56c975ea9bd11f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a98920881e490f616cdb9ceb5927e62db"><td class="memItemLeft" align="right" valign="top"><a id="a98920881e490f616cdb9ceb5927e62db"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA20B_ADC0_PTCXY14</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:a98920881e490f616cdb9ceb5927e62db"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a81c0ff2fe2a5396d8af41f141a1f9d0a"><td class="memItemLeft" align="right" valign="top"><a id="a81c0ff2fe2a5396d8af41f141a1f9d0a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA20B_ADC0_PTCXY14</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a31706dfe73b7a197d56c975ea9bd11f1">PIN_PA20B_ADC0_PTCXY14</a> << 16) | MUX_PA20B_ADC0_PTCXY14)</td></tr>
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<tr class="separator:a81c0ff2fe2a5396d8af41f141a1f9d0a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a85ba0f60481026411cfc36d6defbca1b"><td class="memItemLeft" align="right" valign="top"><a id="a85ba0f60481026411cfc36d6defbca1b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA20B_ADC0_PTCXY14</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 20)</td></tr>
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<tr class="separator:a85ba0f60481026411cfc36d6defbca1b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad8ae9144243e006000d0d4f0fbf804ba"><td class="memItemLeft" align="right" valign="top"><a id="ad8ae9144243e006000d0d4f0fbf804ba"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad8ae9144243e006000d0d4f0fbf804ba">PIN_PA21B_ADC0_PTCXY15</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(21)</td></tr>
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<tr class="memdesc:ad8ae9144243e006000d0d4f0fbf804ba"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: PTCXY15 on PA21 mux B. <br /></td></tr>
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<tr class="separator:ad8ae9144243e006000d0d4f0fbf804ba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aca85f2843b721228fac86b6ca5c43342"><td class="memItemLeft" align="right" valign="top"><a id="aca85f2843b721228fac86b6ca5c43342"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA21B_ADC0_PTCXY15</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:aca85f2843b721228fac86b6ca5c43342"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab50a8f89a00cd066c75665df9e708ccb"><td class="memItemLeft" align="right" valign="top"><a id="ab50a8f89a00cd066c75665df9e708ccb"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA21B_ADC0_PTCXY15</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ad8ae9144243e006000d0d4f0fbf804ba">PIN_PA21B_ADC0_PTCXY15</a> << 16) | MUX_PA21B_ADC0_PTCXY15)</td></tr>
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<tr class="separator:ab50a8f89a00cd066c75665df9e708ccb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a208093ceae6d8017d6bf0d9376df80ec"><td class="memItemLeft" align="right" valign="top"><a id="a208093ceae6d8017d6bf0d9376df80ec"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA21B_ADC0_PTCXY15</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 21)</td></tr>
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<tr class="separator:a208093ceae6d8017d6bf0d9376df80ec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af46d4c957b46480fde3e582606cd3d8c"><td class="memItemLeft" align="right" valign="top"><a id="af46d4c957b46480fde3e582606cd3d8c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af46d4c957b46480fde3e582606cd3d8c">PIN_PA22B_ADC0_PTCXY16</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(22)</td></tr>
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<tr class="memdesc:af46d4c957b46480fde3e582606cd3d8c"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: PTCXY16 on PA22 mux B. <br /></td></tr>
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<tr class="separator:af46d4c957b46480fde3e582606cd3d8c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a05ed93d147d334abce320d2fb6ad48ab"><td class="memItemLeft" align="right" valign="top"><a id="a05ed93d147d334abce320d2fb6ad48ab"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA22B_ADC0_PTCXY16</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:a05ed93d147d334abce320d2fb6ad48ab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa79d46be9c028e2a9e9d614d94f6c066"><td class="memItemLeft" align="right" valign="top"><a id="aa79d46be9c028e2a9e9d614d94f6c066"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA22B_ADC0_PTCXY16</b>   ((<a class="el" href="pio_2same54p20a_8h.html#af46d4c957b46480fde3e582606cd3d8c">PIN_PA22B_ADC0_PTCXY16</a> << 16) | MUX_PA22B_ADC0_PTCXY16)</td></tr>
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<tr class="separator:aa79d46be9c028e2a9e9d614d94f6c066"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a265b1c969ab5db6a4c7144e1f502994d"><td class="memItemLeft" align="right" valign="top"><a id="a265b1c969ab5db6a4c7144e1f502994d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA22B_ADC0_PTCXY16</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 22)</td></tr>
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<tr class="separator:a265b1c969ab5db6a4c7144e1f502994d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aaca514230fcf8e3d142ba3839243035a"><td class="memItemLeft" align="right" valign="top"><a id="aaca514230fcf8e3d142ba3839243035a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aaca514230fcf8e3d142ba3839243035a">PIN_PA23B_ADC0_PTCXY17</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(23)</td></tr>
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<tr class="memdesc:aaca514230fcf8e3d142ba3839243035a"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: PTCXY17 on PA23 mux B. <br /></td></tr>
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<tr class="separator:aaca514230fcf8e3d142ba3839243035a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7066366f4e8c1ece87bac8b5fc811537"><td class="memItemLeft" align="right" valign="top"><a id="a7066366f4e8c1ece87bac8b5fc811537"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA23B_ADC0_PTCXY17</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:a7066366f4e8c1ece87bac8b5fc811537"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7a86d11c418be585315c45b46b2a20a8"><td class="memItemLeft" align="right" valign="top"><a id="a7a86d11c418be585315c45b46b2a20a8"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA23B_ADC0_PTCXY17</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aaca514230fcf8e3d142ba3839243035a">PIN_PA23B_ADC0_PTCXY17</a> << 16) | MUX_PA23B_ADC0_PTCXY17)</td></tr>
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<tr class="separator:a7a86d11c418be585315c45b46b2a20a8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a32db2c6604a9c6a26fa0610ad99f0d0b"><td class="memItemLeft" align="right" valign="top"><a id="a32db2c6604a9c6a26fa0610ad99f0d0b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA23B_ADC0_PTCXY17</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 23)</td></tr>
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<tr class="separator:a32db2c6604a9c6a26fa0610ad99f0d0b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1f6699fd0d3a7877e4609a81c3c47b9a"><td class="memItemLeft" align="right" valign="top"><a id="a1f6699fd0d3a7877e4609a81c3c47b9a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1f6699fd0d3a7877e4609a81c3c47b9a">PIN_PA27B_ADC0_PTCXY18</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(27)</td></tr>
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<tr class="memdesc:a1f6699fd0d3a7877e4609a81c3c47b9a"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: PTCXY18 on PA27 mux B. <br /></td></tr>
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<tr class="separator:a1f6699fd0d3a7877e4609a81c3c47b9a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adbaa665294409f6b8ef453beb9a3f53c"><td class="memItemLeft" align="right" valign="top"><a id="adbaa665294409f6b8ef453beb9a3f53c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA27B_ADC0_PTCXY18</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:adbaa665294409f6b8ef453beb9a3f53c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa8c7178b9218cf7d207dbff049de8c5b"><td class="memItemLeft" align="right" valign="top"><a id="aa8c7178b9218cf7d207dbff049de8c5b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA27B_ADC0_PTCXY18</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a1f6699fd0d3a7877e4609a81c3c47b9a">PIN_PA27B_ADC0_PTCXY18</a> << 16) | MUX_PA27B_ADC0_PTCXY18)</td></tr>
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<tr class="separator:aa8c7178b9218cf7d207dbff049de8c5b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a991dc9a8547d5532bc86f45116b8cbfd"><td class="memItemLeft" align="right" valign="top"><a id="a991dc9a8547d5532bc86f45116b8cbfd"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA27B_ADC0_PTCXY18</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 27)</td></tr>
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<tr class="separator:a991dc9a8547d5532bc86f45116b8cbfd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6df4f427fa92417aae87a181a8c3db30"><td class="memItemLeft" align="right" valign="top"><a id="a6df4f427fa92417aae87a181a8c3db30"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6df4f427fa92417aae87a181a8c3db30">PIN_PA30B_ADC0_PTCXY19</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(30)</td></tr>
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<tr class="memdesc:a6df4f427fa92417aae87a181a8c3db30"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: PTCXY19 on PA30 mux B. <br /></td></tr>
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<tr class="separator:a6df4f427fa92417aae87a181a8c3db30"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4452c2bf4290ee7c3b0fe4a1e9a358fe"><td class="memItemLeft" align="right" valign="top"><a id="a4452c2bf4290ee7c3b0fe4a1e9a358fe"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA30B_ADC0_PTCXY19</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:a4452c2bf4290ee7c3b0fe4a1e9a358fe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a23a9060bf99b5f0abb51ff34444564ae"><td class="memItemLeft" align="right" valign="top"><a id="a23a9060bf99b5f0abb51ff34444564ae"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA30B_ADC0_PTCXY19</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a6df4f427fa92417aae87a181a8c3db30">PIN_PA30B_ADC0_PTCXY19</a> << 16) | MUX_PA30B_ADC0_PTCXY19)</td></tr>
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<tr class="memitem:abf4bf807ba0db6f09b25ec34e04daffb"><td class="memItemLeft" align="right" valign="top"><a id="abf4bf807ba0db6f09b25ec34e04daffb"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA30B_ADC0_PTCXY19</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 30)</td></tr>
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<tr class="separator:abf4bf807ba0db6f09b25ec34e04daffb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a04c6898ae2c640f37b602d6ac3fec204"><td class="memItemLeft" align="right" valign="top"><a id="a04c6898ae2c640f37b602d6ac3fec204"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a04c6898ae2c640f37b602d6ac3fec204">PIN_PB02B_ADC0_PTCXY20</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(34)</td></tr>
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<tr class="memdesc:a04c6898ae2c640f37b602d6ac3fec204"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: PTCXY20 on PB02 mux B. <br /></td></tr>
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<tr class="separator:a04c6898ae2c640f37b602d6ac3fec204"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac17c0fb41d82c749d8c85df35631410a"><td class="memItemLeft" align="right" valign="top"><a id="ac17c0fb41d82c749d8c85df35631410a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB02B_ADC0_PTCXY20</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:ac17c0fb41d82c749d8c85df35631410a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:add84440961344878710e41b72b7b7aae"><td class="memItemLeft" align="right" valign="top"><a id="add84440961344878710e41b72b7b7aae"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB02B_ADC0_PTCXY20</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a04c6898ae2c640f37b602d6ac3fec204">PIN_PB02B_ADC0_PTCXY20</a> << 16) | MUX_PB02B_ADC0_PTCXY20)</td></tr>
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<tr class="separator:add84440961344878710e41b72b7b7aae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aecbf4debe7f71268f4861e3961d34d8b"><td class="memItemLeft" align="right" valign="top"><a id="aecbf4debe7f71268f4861e3961d34d8b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB02B_ADC0_PTCXY20</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 2)</td></tr>
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<tr class="separator:aecbf4debe7f71268f4861e3961d34d8b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5f42c846bd1c11dd378d68faa5ffea98"><td class="memItemLeft" align="right" valign="top"><a id="a5f42c846bd1c11dd378d68faa5ffea98"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5f42c846bd1c11dd378d68faa5ffea98">PIN_PB03B_ADC0_PTCXY21</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(35)</td></tr>
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<tr class="memdesc:a5f42c846bd1c11dd378d68faa5ffea98"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: PTCXY21 on PB03 mux B. <br /></td></tr>
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<tr class="separator:a5f42c846bd1c11dd378d68faa5ffea98"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac730daf30cfa9c935bc409ff57df3589"><td class="memItemLeft" align="right" valign="top"><a id="ac730daf30cfa9c935bc409ff57df3589"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB03B_ADC0_PTCXY21</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:ac730daf30cfa9c935bc409ff57df3589"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af8b3405ec45d256d6ff76e2c114d575f"><td class="memItemLeft" align="right" valign="top"><a id="af8b3405ec45d256d6ff76e2c114d575f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB03B_ADC0_PTCXY21</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a5f42c846bd1c11dd378d68faa5ffea98">PIN_PB03B_ADC0_PTCXY21</a> << 16) | MUX_PB03B_ADC0_PTCXY21)</td></tr>
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<tr class="separator:af8b3405ec45d256d6ff76e2c114d575f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad26866adb71e61ee9eeb02692c18fc52"><td class="memItemLeft" align="right" valign="top"><a id="ad26866adb71e61ee9eeb02692c18fc52"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB03B_ADC0_PTCXY21</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 3)</td></tr>
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<tr class="separator:ad26866adb71e61ee9eeb02692c18fc52"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab8dd8d6d0715a21d207405416a343d91"><td class="memItemLeft" align="right" valign="top"><a id="ab8dd8d6d0715a21d207405416a343d91"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab8dd8d6d0715a21d207405416a343d91">PIN_PB04B_ADC0_PTCXY22</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(36)</td></tr>
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<tr class="memdesc:ab8dd8d6d0715a21d207405416a343d91"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: PTCXY22 on PB04 mux B. <br /></td></tr>
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<tr class="separator:ab8dd8d6d0715a21d207405416a343d91"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afc23870abfcedc9e888fe06abd34cf51"><td class="memItemLeft" align="right" valign="top"><a id="afc23870abfcedc9e888fe06abd34cf51"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB04B_ADC0_PTCXY22</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:afc23870abfcedc9e888fe06abd34cf51"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acb23e8cb522eeb2c8b7e232e56e73283"><td class="memItemLeft" align="right" valign="top"><a id="acb23e8cb522eeb2c8b7e232e56e73283"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB04B_ADC0_PTCXY22</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ab8dd8d6d0715a21d207405416a343d91">PIN_PB04B_ADC0_PTCXY22</a> << 16) | MUX_PB04B_ADC0_PTCXY22)</td></tr>
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<tr class="separator:acb23e8cb522eeb2c8b7e232e56e73283"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad4e33d5e88192a58428b28caae30b107"><td class="memItemLeft" align="right" valign="top"><a id="ad4e33d5e88192a58428b28caae30b107"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB04B_ADC0_PTCXY22</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 4)</td></tr>
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<tr class="separator:ad4e33d5e88192a58428b28caae30b107"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6b2aff4fdf703d401fcff33c1ec239b5"><td class="memItemLeft" align="right" valign="top"><a id="a6b2aff4fdf703d401fcff33c1ec239b5"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6b2aff4fdf703d401fcff33c1ec239b5">PIN_PB05B_ADC0_PTCXY23</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(37)</td></tr>
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<tr class="memdesc:a6b2aff4fdf703d401fcff33c1ec239b5"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: PTCXY23 on PB05 mux B. <br /></td></tr>
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<tr class="separator:a6b2aff4fdf703d401fcff33c1ec239b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab5258619219f326690f2c03cedea950b"><td class="memItemLeft" align="right" valign="top"><a id="ab5258619219f326690f2c03cedea950b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB05B_ADC0_PTCXY23</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:ab5258619219f326690f2c03cedea950b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1bbe43e2fb9a188927e8e2433bee7a9a"><td class="memItemLeft" align="right" valign="top"><a id="a1bbe43e2fb9a188927e8e2433bee7a9a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB05B_ADC0_PTCXY23</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a6b2aff4fdf703d401fcff33c1ec239b5">PIN_PB05B_ADC0_PTCXY23</a> << 16) | MUX_PB05B_ADC0_PTCXY23)</td></tr>
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<tr class="separator:a1bbe43e2fb9a188927e8e2433bee7a9a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3b8e2e6147450d9b76b03d086369b738"><td class="memItemLeft" align="right" valign="top"><a id="a3b8e2e6147450d9b76b03d086369b738"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB05B_ADC0_PTCXY23</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 5)</td></tr>
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<tr class="separator:a3b8e2e6147450d9b76b03d086369b738"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a61f6309b1993c6351c1306aeaeb4ee04"><td class="memItemLeft" align="right" valign="top"><a id="a61f6309b1993c6351c1306aeaeb4ee04"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a61f6309b1993c6351c1306aeaeb4ee04">PIN_PB06B_ADC0_PTCXY24</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(38)</td></tr>
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<tr class="memdesc:a61f6309b1993c6351c1306aeaeb4ee04"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: PTCXY24 on PB06 mux B. <br /></td></tr>
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<tr class="separator:a61f6309b1993c6351c1306aeaeb4ee04"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa896a02b716e0096e1e15b5dc499411a"><td class="memItemLeft" align="right" valign="top"><a id="aa896a02b716e0096e1e15b5dc499411a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB06B_ADC0_PTCXY24</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:aa896a02b716e0096e1e15b5dc499411a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a872c8dbb9e23229137ca14a076be9188"><td class="memItemLeft" align="right" valign="top"><a id="a872c8dbb9e23229137ca14a076be9188"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB06B_ADC0_PTCXY24</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a61f6309b1993c6351c1306aeaeb4ee04">PIN_PB06B_ADC0_PTCXY24</a> << 16) | MUX_PB06B_ADC0_PTCXY24)</td></tr>
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<tr class="separator:a872c8dbb9e23229137ca14a076be9188"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aafa322f9f8cf122bd91bc51e6f8051d5"><td class="memItemLeft" align="right" valign="top"><a id="aafa322f9f8cf122bd91bc51e6f8051d5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB06B_ADC0_PTCXY24</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 6)</td></tr>
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<tr class="separator:aafa322f9f8cf122bd91bc51e6f8051d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab6efc8ac261269eaae59e9ecbd2d23d2"><td class="memItemLeft" align="right" valign="top"><a id="ab6efc8ac261269eaae59e9ecbd2d23d2"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab6efc8ac261269eaae59e9ecbd2d23d2">PIN_PB07B_ADC0_PTCXY25</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(39)</td></tr>
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||
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<tr class="memdesc:ab6efc8ac261269eaae59e9ecbd2d23d2"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: PTCXY25 on PB07 mux B. <br /></td></tr>
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<tr class="separator:ab6efc8ac261269eaae59e9ecbd2d23d2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aea3042451cd2c97a5d2e64aebd22b372"><td class="memItemLeft" align="right" valign="top"><a id="aea3042451cd2c97a5d2e64aebd22b372"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB07B_ADC0_PTCXY25</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:aea3042451cd2c97a5d2e64aebd22b372"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5feed826ea0de8278c245eb85d4c656b"><td class="memItemLeft" align="right" valign="top"><a id="a5feed826ea0de8278c245eb85d4c656b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB07B_ADC0_PTCXY25</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ab6efc8ac261269eaae59e9ecbd2d23d2">PIN_PB07B_ADC0_PTCXY25</a> << 16) | MUX_PB07B_ADC0_PTCXY25)</td></tr>
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<tr class="separator:a5feed826ea0de8278c245eb85d4c656b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8b9372a2772766ae42eaa4039c7aded1"><td class="memItemLeft" align="right" valign="top"><a id="a8b9372a2772766ae42eaa4039c7aded1"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB07B_ADC0_PTCXY25</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 7)</td></tr>
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<tr class="separator:a8b9372a2772766ae42eaa4039c7aded1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3cd5e2958db2decefe237ea16f7ef880"><td class="memItemLeft" align="right" valign="top"><a id="a3cd5e2958db2decefe237ea16f7ef880"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3cd5e2958db2decefe237ea16f7ef880">PIN_PB12B_ADC0_PTCXY26</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(44)</td></tr>
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<tr class="memdesc:a3cd5e2958db2decefe237ea16f7ef880"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: PTCXY26 on PB12 mux B. <br /></td></tr>
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<tr class="separator:a3cd5e2958db2decefe237ea16f7ef880"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4c83507f4dc5f7d0bdfc02afea1d31f9"><td class="memItemLeft" align="right" valign="top"><a id="a4c83507f4dc5f7d0bdfc02afea1d31f9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB12B_ADC0_PTCXY26</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:a4c83507f4dc5f7d0bdfc02afea1d31f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2098af2d2c60ddc3056445a8106c3d01"><td class="memItemLeft" align="right" valign="top"><a id="a2098af2d2c60ddc3056445a8106c3d01"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB12B_ADC0_PTCXY26</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a3cd5e2958db2decefe237ea16f7ef880">PIN_PB12B_ADC0_PTCXY26</a> << 16) | MUX_PB12B_ADC0_PTCXY26)</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB12B_ADC0_PTCXY26</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 12)</td></tr>
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<tr class="separator:affac42350b2700004badb5a8e9a01435"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9f2d7f3bda7f2ef4d6eb7be44c9f9216"><td class="memItemLeft" align="right" valign="top"><a id="a9f2d7f3bda7f2ef4d6eb7be44c9f9216"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a9f2d7f3bda7f2ef4d6eb7be44c9f9216">PIN_PB13B_ADC0_PTCXY27</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(45)</td></tr>
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<tr class="memdesc:a9f2d7f3bda7f2ef4d6eb7be44c9f9216"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: PTCXY27 on PB13 mux B. <br /></td></tr>
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<tr class="memitem:aa8bd958dbaae831c53853d1d1af697f2"><td class="memItemLeft" align="right" valign="top"><a id="aa8bd958dbaae831c53853d1d1af697f2"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB13B_ADC0_PTCXY27</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:aa8bd958dbaae831c53853d1d1af697f2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afb2120b07d6694c4aa38d6c79aab5bde"><td class="memItemLeft" align="right" valign="top"><a id="afb2120b07d6694c4aa38d6c79aab5bde"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB13B_ADC0_PTCXY27</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a9f2d7f3bda7f2ef4d6eb7be44c9f9216">PIN_PB13B_ADC0_PTCXY27</a> << 16) | MUX_PB13B_ADC0_PTCXY27)</td></tr>
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<tr class="separator:afb2120b07d6694c4aa38d6c79aab5bde"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a384557d94a1bb0cc8d17fa44ec268bf0"><td class="memItemLeft" align="right" valign="top"><a id="a384557d94a1bb0cc8d17fa44ec268bf0"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB13B_ADC0_PTCXY27</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 13)</td></tr>
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<tr class="separator:a384557d94a1bb0cc8d17fa44ec268bf0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0bf30bc3602ed48035eaab5e8134992b"><td class="memItemLeft" align="right" valign="top"><a id="a0bf30bc3602ed48035eaab5e8134992b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0bf30bc3602ed48035eaab5e8134992b">PIN_PB14B_ADC0_PTCXY28</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(46)</td></tr>
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<tr class="memdesc:a0bf30bc3602ed48035eaab5e8134992b"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: PTCXY28 on PB14 mux B. <br /></td></tr>
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<tr class="separator:a0bf30bc3602ed48035eaab5e8134992b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7a79b18858eb41b4d34de2213763431e"><td class="memItemLeft" align="right" valign="top"><a id="a7a79b18858eb41b4d34de2213763431e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB14B_ADC0_PTCXY28</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:a7a79b18858eb41b4d34de2213763431e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae2920ace30bc93f0c107a659433e0aec"><td class="memItemLeft" align="right" valign="top"><a id="ae2920ace30bc93f0c107a659433e0aec"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB14B_ADC0_PTCXY28</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a0bf30bc3602ed48035eaab5e8134992b">PIN_PB14B_ADC0_PTCXY28</a> << 16) | MUX_PB14B_ADC0_PTCXY28)</td></tr>
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<tr class="separator:ae2920ace30bc93f0c107a659433e0aec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae0f6e71b695cd904ed9bbdf5452f4d96"><td class="memItemLeft" align="right" valign="top"><a id="ae0f6e71b695cd904ed9bbdf5452f4d96"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB14B_ADC0_PTCXY28</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 14)</td></tr>
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<tr class="separator:ae0f6e71b695cd904ed9bbdf5452f4d96"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af7fb8c70fc1c62e36b00829de2dd4b10"><td class="memItemLeft" align="right" valign="top"><a id="af7fb8c70fc1c62e36b00829de2dd4b10"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af7fb8c70fc1c62e36b00829de2dd4b10">PIN_PB15B_ADC0_PTCXY29</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(47)</td></tr>
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<tr class="memdesc:af7fb8c70fc1c62e36b00829de2dd4b10"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: PTCXY29 on PB15 mux B. <br /></td></tr>
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<tr class="separator:af7fb8c70fc1c62e36b00829de2dd4b10"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aeee8c4ff192ce3c7ec7ae24f048ce893"><td class="memItemLeft" align="right" valign="top"><a id="aeee8c4ff192ce3c7ec7ae24f048ce893"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB15B_ADC0_PTCXY29</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:aeee8c4ff192ce3c7ec7ae24f048ce893"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adbbbf8c595534180cb69cc04cd322993"><td class="memItemLeft" align="right" valign="top"><a id="adbbbf8c595534180cb69cc04cd322993"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB15B_ADC0_PTCXY29</b>   ((<a class="el" href="pio_2same54p20a_8h.html#af7fb8c70fc1c62e36b00829de2dd4b10">PIN_PB15B_ADC0_PTCXY29</a> << 16) | MUX_PB15B_ADC0_PTCXY29)</td></tr>
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<tr class="separator:adbbbf8c595534180cb69cc04cd322993"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a994c0223ef33768f05ef525c45771cc9"><td class="memItemLeft" align="right" valign="top"><a id="a994c0223ef33768f05ef525c45771cc9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB15B_ADC0_PTCXY29</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 15)</td></tr>
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<tr class="separator:a994c0223ef33768f05ef525c45771cc9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a07ee9e0fae09a010e759e04175036b14"><td class="memItemLeft" align="right" valign="top"><a id="a07ee9e0fae09a010e759e04175036b14"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a07ee9e0fae09a010e759e04175036b14">PIN_PB00B_ADC0_PTCXY30</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(32)</td></tr>
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<tr class="memdesc:a07ee9e0fae09a010e759e04175036b14"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: PTCXY30 on PB00 mux B. <br /></td></tr>
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<tr class="separator:a07ee9e0fae09a010e759e04175036b14"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5a0f2db35f2cae58b89c9ff9cbba774b"><td class="memItemLeft" align="right" valign="top"><a id="a5a0f2db35f2cae58b89c9ff9cbba774b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB00B_ADC0_PTCXY30</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:a5a0f2db35f2cae58b89c9ff9cbba774b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a485c4d6a330d39270acd7f7f16e9201f"><td class="memItemLeft" align="right" valign="top"><a id="a485c4d6a330d39270acd7f7f16e9201f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB00B_ADC0_PTCXY30</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a07ee9e0fae09a010e759e04175036b14">PIN_PB00B_ADC0_PTCXY30</a> << 16) | MUX_PB00B_ADC0_PTCXY30)</td></tr>
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<tr class="separator:a485c4d6a330d39270acd7f7f16e9201f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9b7f8ea389b1bc0286577fa072fd6315"><td class="memItemLeft" align="right" valign="top"><a id="a9b7f8ea389b1bc0286577fa072fd6315"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB00B_ADC0_PTCXY30</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 0)</td></tr>
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<tr class="separator:a9b7f8ea389b1bc0286577fa072fd6315"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4b8994039f5b7fb8144c30db8671ee6e"><td class="memItemLeft" align="right" valign="top"><a id="a4b8994039f5b7fb8144c30db8671ee6e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4b8994039f5b7fb8144c30db8671ee6e">PIN_PB01B_ADC0_PTCXY31</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(33)</td></tr>
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<tr class="memdesc:a4b8994039f5b7fb8144c30db8671ee6e"><td class="mdescLeft"> </td><td class="mdescRight">ADC0 signal: PTCXY31 on PB01 mux B. <br /></td></tr>
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<tr class="separator:a4b8994039f5b7fb8144c30db8671ee6e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a74eaa4ffc0db3dee8a44b0a718ad2b3e"><td class="memItemLeft" align="right" valign="top"><a id="a74eaa4ffc0db3dee8a44b0a718ad2b3e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB01B_ADC0_PTCXY31</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:a74eaa4ffc0db3dee8a44b0a718ad2b3e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3a55610dfc0a0ff184f9d478130bb47a"><td class="memItemLeft" align="right" valign="top"><a id="a3a55610dfc0a0ff184f9d478130bb47a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB01B_ADC0_PTCXY31</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a4b8994039f5b7fb8144c30db8671ee6e">PIN_PB01B_ADC0_PTCXY31</a> << 16) | MUX_PB01B_ADC0_PTCXY31)</td></tr>
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<tr class="separator:a3a55610dfc0a0ff184f9d478130bb47a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a129dca5b78ea29f5a73cc3a44fc3d3e6"><td class="memItemLeft" align="right" valign="top"><a id="a129dca5b78ea29f5a73cc3a44fc3d3e6"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB01B_ADC0_PTCXY31</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 1)</td></tr>
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<tr class="separator:a129dca5b78ea29f5a73cc3a44fc3d3e6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab4aea2d25f14f53d40dc26ccd47d18d1"><td class="memItemLeft" align="right" valign="top"><a id="ab4aea2d25f14f53d40dc26ccd47d18d1"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab4aea2d25f14f53d40dc26ccd47d18d1">PIN_PB08B_ADC1_AIN0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(40)</td></tr>
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<tr class="memdesc:ab4aea2d25f14f53d40dc26ccd47d18d1"><td class="mdescLeft"> </td><td class="mdescRight">ADC1 signal: AIN0 on PB08 mux B. <br /></td></tr>
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<tr class="separator:ab4aea2d25f14f53d40dc26ccd47d18d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7cee2be89259fee5acbc8909b299d456"><td class="memItemLeft" align="right" valign="top"><a id="a7cee2be89259fee5acbc8909b299d456"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB08B_ADC1_AIN0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:a7cee2be89259fee5acbc8909b299d456"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad7fae47cf6b7f677bbbf1bcff5f4dfc7"><td class="memItemLeft" align="right" valign="top"><a id="ad7fae47cf6b7f677bbbf1bcff5f4dfc7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB08B_ADC1_AIN0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ab4aea2d25f14f53d40dc26ccd47d18d1">PIN_PB08B_ADC1_AIN0</a> << 16) | MUX_PB08B_ADC1_AIN0)</td></tr>
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<tr class="separator:ad7fae47cf6b7f677bbbf1bcff5f4dfc7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a94cc32f4fb821e4b76cc405db36affad"><td class="memItemLeft" align="right" valign="top"><a id="a94cc32f4fb821e4b76cc405db36affad"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB08B_ADC1_AIN0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 8)</td></tr>
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<tr class="separator:a94cc32f4fb821e4b76cc405db36affad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5a03b2710c270e14264403dad4e6d861"><td class="memItemLeft" align="right" valign="top"><a id="a5a03b2710c270e14264403dad4e6d861"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5a03b2710c270e14264403dad4e6d861">PIN_PB09B_ADC1_AIN1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(41)</td></tr>
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<tr class="memdesc:a5a03b2710c270e14264403dad4e6d861"><td class="mdescLeft"> </td><td class="mdescRight">ADC1 signal: AIN1 on PB09 mux B. <br /></td></tr>
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<tr class="separator:a5a03b2710c270e14264403dad4e6d861"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a185ae0f409663fd20cefd1ec1dd2b3c5"><td class="memItemLeft" align="right" valign="top"><a id="a185ae0f409663fd20cefd1ec1dd2b3c5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB09B_ADC1_AIN1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:a185ae0f409663fd20cefd1ec1dd2b3c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a330d713d252b0cb29e9aae862087477e"><td class="memItemLeft" align="right" valign="top"><a id="a330d713d252b0cb29e9aae862087477e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB09B_ADC1_AIN1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a5a03b2710c270e14264403dad4e6d861">PIN_PB09B_ADC1_AIN1</a> << 16) | MUX_PB09B_ADC1_AIN1)</td></tr>
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<tr class="separator:a330d713d252b0cb29e9aae862087477e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6586a4692ec82dcf81bc0862b614f0a1"><td class="memItemLeft" align="right" valign="top"><a id="a6586a4692ec82dcf81bc0862b614f0a1"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB09B_ADC1_AIN1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 9)</td></tr>
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<tr class="memitem:af9e6229b9dbee3c7bacdad90f30cc5cf"><td class="memItemLeft" align="right" valign="top"><a id="af9e6229b9dbee3c7bacdad90f30cc5cf"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af9e6229b9dbee3c7bacdad90f30cc5cf">PIN_PA08B_ADC1_AIN2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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<tr class="memdesc:af9e6229b9dbee3c7bacdad90f30cc5cf"><td class="mdescLeft"> </td><td class="mdescRight">ADC1 signal: AIN2 on PA08 mux B. <br /></td></tr>
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<tr class="memitem:a23770da58a99cf3555f9469c883d4ab5"><td class="memItemLeft" align="right" valign="top"><a id="a23770da58a99cf3555f9469c883d4ab5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA08B_ADC1_AIN2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:a23770da58a99cf3555f9469c883d4ab5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adcb7948be522be9778b27c36c4d5bd60"><td class="memItemLeft" align="right" valign="top"><a id="adcb7948be522be9778b27c36c4d5bd60"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA08B_ADC1_AIN2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#af9e6229b9dbee3c7bacdad90f30cc5cf">PIN_PA08B_ADC1_AIN2</a> << 16) | MUX_PA08B_ADC1_AIN2)</td></tr>
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<tr class="memitem:a9746f713919b8733c2099d56c073e1f7"><td class="memItemLeft" align="right" valign="top"><a id="a9746f713919b8733c2099d56c073e1f7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA08B_ADC1_AIN2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 8)</td></tr>
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<tr class="separator:a9746f713919b8733c2099d56c073e1f7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa345bdaaa58db83ba6928685882ff7e9"><td class="memItemLeft" align="right" valign="top"><a id="aa345bdaaa58db83ba6928685882ff7e9"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa345bdaaa58db83ba6928685882ff7e9">PIN_PA09B_ADC1_AIN3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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<tr class="memdesc:aa345bdaaa58db83ba6928685882ff7e9"><td class="mdescLeft"> </td><td class="mdescRight">ADC1 signal: AIN3 on PA09 mux B. <br /></td></tr>
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<tr class="separator:aa345bdaaa58db83ba6928685882ff7e9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a65aa6514f0ef5ec529dc827aab48a571"><td class="memItemLeft" align="right" valign="top"><a id="a65aa6514f0ef5ec529dc827aab48a571"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA09B_ADC1_AIN3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:a65aa6514f0ef5ec529dc827aab48a571"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa1ab6a35d94b51ae4921078ff1092b6a"><td class="memItemLeft" align="right" valign="top"><a id="aa1ab6a35d94b51ae4921078ff1092b6a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA09B_ADC1_AIN3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aa345bdaaa58db83ba6928685882ff7e9">PIN_PA09B_ADC1_AIN3</a> << 16) | MUX_PA09B_ADC1_AIN3)</td></tr>
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<tr class="separator:aa1ab6a35d94b51ae4921078ff1092b6a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aae31a3c9d0165d7a75ca23984c318a72"><td class="memItemLeft" align="right" valign="top"><a id="aae31a3c9d0165d7a75ca23984c318a72"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA09B_ADC1_AIN3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 9)</td></tr>
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<tr class="separator:aae31a3c9d0165d7a75ca23984c318a72"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0a2f519ba1691dec19faaf4b2b47ecfd"><td class="memItemLeft" align="right" valign="top"><a id="a0a2f519ba1691dec19faaf4b2b47ecfd"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0a2f519ba1691dec19faaf4b2b47ecfd">PIN_PC02B_ADC1_AIN4</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(66)</td></tr>
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<tr class="memdesc:a0a2f519ba1691dec19faaf4b2b47ecfd"><td class="mdescLeft"> </td><td class="mdescRight">ADC1 signal: AIN4 on PC02 mux B. <br /></td></tr>
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<tr class="separator:a0a2f519ba1691dec19faaf4b2b47ecfd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adcc6773e656c3070d4bc1cff91c537f2"><td class="memItemLeft" align="right" valign="top"><a id="adcc6773e656c3070d4bc1cff91c537f2"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC02B_ADC1_AIN4</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:adcc6773e656c3070d4bc1cff91c537f2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2425e517bd41a905175153bcfe8b63c6"><td class="memItemLeft" align="right" valign="top"><a id="a2425e517bd41a905175153bcfe8b63c6"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC02B_ADC1_AIN4</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a0a2f519ba1691dec19faaf4b2b47ecfd">PIN_PC02B_ADC1_AIN4</a> << 16) | MUX_PC02B_ADC1_AIN4)</td></tr>
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<tr class="separator:a2425e517bd41a905175153bcfe8b63c6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac31f8253ae13cd74c1118960d9229e03"><td class="memItemLeft" align="right" valign="top"><a id="ac31f8253ae13cd74c1118960d9229e03"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC02B_ADC1_AIN4</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 2)</td></tr>
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<tr class="separator:ac31f8253ae13cd74c1118960d9229e03"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae1e1bbe3dd622f37e981e9abd52fcb5d"><td class="memItemLeft" align="right" valign="top"><a id="ae1e1bbe3dd622f37e981e9abd52fcb5d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae1e1bbe3dd622f37e981e9abd52fcb5d">PIN_PC03B_ADC1_AIN5</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(67)</td></tr>
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||
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<tr class="memdesc:ae1e1bbe3dd622f37e981e9abd52fcb5d"><td class="mdescLeft"> </td><td class="mdescRight">ADC1 signal: AIN5 on PC03 mux B. <br /></td></tr>
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<tr class="separator:ae1e1bbe3dd622f37e981e9abd52fcb5d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9737090040b57777a2115db200532a24"><td class="memItemLeft" align="right" valign="top"><a id="a9737090040b57777a2115db200532a24"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC03B_ADC1_AIN5</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:a9737090040b57777a2115db200532a24"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7942b5c456cbfe71aca12adde4a10ee3"><td class="memItemLeft" align="right" valign="top"><a id="a7942b5c456cbfe71aca12adde4a10ee3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC03B_ADC1_AIN5</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ae1e1bbe3dd622f37e981e9abd52fcb5d">PIN_PC03B_ADC1_AIN5</a> << 16) | MUX_PC03B_ADC1_AIN5)</td></tr>
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<tr class="separator:a7942b5c456cbfe71aca12adde4a10ee3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa93cbb0719bb301889e1bea44b819fbb"><td class="memItemLeft" align="right" valign="top"><a id="aa93cbb0719bb301889e1bea44b819fbb"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC03B_ADC1_AIN5</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 3)</td></tr>
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<tr class="separator:aa93cbb0719bb301889e1bea44b819fbb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2e48c0a61d69ac34ed9b34f2bdf7c2a5"><td class="memItemLeft" align="right" valign="top"><a id="a2e48c0a61d69ac34ed9b34f2bdf7c2a5"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2e48c0a61d69ac34ed9b34f2bdf7c2a5">PIN_PB04B_ADC1_AIN6</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(36)</td></tr>
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||
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<tr class="memdesc:a2e48c0a61d69ac34ed9b34f2bdf7c2a5"><td class="mdescLeft"> </td><td class="mdescRight">ADC1 signal: AIN6 on PB04 mux B. <br /></td></tr>
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<tr class="separator:a2e48c0a61d69ac34ed9b34f2bdf7c2a5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a92d4abf51480a2c8845792a47d22f64b"><td class="memItemLeft" align="right" valign="top"><a id="a92d4abf51480a2c8845792a47d22f64b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB04B_ADC1_AIN6</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:a92d4abf51480a2c8845792a47d22f64b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad683e877effdb87f19aacdaec9809ac9"><td class="memItemLeft" align="right" valign="top"><a id="ad683e877effdb87f19aacdaec9809ac9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB04B_ADC1_AIN6</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a2e48c0a61d69ac34ed9b34f2bdf7c2a5">PIN_PB04B_ADC1_AIN6</a> << 16) | MUX_PB04B_ADC1_AIN6)</td></tr>
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<tr class="separator:ad683e877effdb87f19aacdaec9809ac9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:add52eb057e12f2fb873112ae14f80106"><td class="memItemLeft" align="right" valign="top"><a id="add52eb057e12f2fb873112ae14f80106"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB04B_ADC1_AIN6</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 4)</td></tr>
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<tr class="separator:add52eb057e12f2fb873112ae14f80106"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4d03ecccf6afc8a55f4ded17218adc9a"><td class="memItemLeft" align="right" valign="top"><a id="a4d03ecccf6afc8a55f4ded17218adc9a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4d03ecccf6afc8a55f4ded17218adc9a">PIN_PB05B_ADC1_AIN7</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(37)</td></tr>
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||
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<tr class="memdesc:a4d03ecccf6afc8a55f4ded17218adc9a"><td class="mdescLeft"> </td><td class="mdescRight">ADC1 signal: AIN7 on PB05 mux B. <br /></td></tr>
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<tr class="separator:a4d03ecccf6afc8a55f4ded17218adc9a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac813239edd1358796e1b1dd2cbb5e5bd"><td class="memItemLeft" align="right" valign="top"><a id="ac813239edd1358796e1b1dd2cbb5e5bd"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB05B_ADC1_AIN7</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:ac813239edd1358796e1b1dd2cbb5e5bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac85e529f9e5377c629f27df4c605e4e4"><td class="memItemLeft" align="right" valign="top"><a id="ac85e529f9e5377c629f27df4c605e4e4"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB05B_ADC1_AIN7</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a4d03ecccf6afc8a55f4ded17218adc9a">PIN_PB05B_ADC1_AIN7</a> << 16) | MUX_PB05B_ADC1_AIN7)</td></tr>
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<tr class="separator:ac85e529f9e5377c629f27df4c605e4e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad054a804cff158383127bea6ea469e1f"><td class="memItemLeft" align="right" valign="top"><a id="ad054a804cff158383127bea6ea469e1f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB05B_ADC1_AIN7</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 5)</td></tr>
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||
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<tr class="separator:ad054a804cff158383127bea6ea469e1f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a870dd9e9de79013b71c884f30062abba"><td class="memItemLeft" align="right" valign="top"><a id="a870dd9e9de79013b71c884f30062abba"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a870dd9e9de79013b71c884f30062abba">PIN_PB06B_ADC1_AIN8</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(38)</td></tr>
|
||
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<tr class="memdesc:a870dd9e9de79013b71c884f30062abba"><td class="mdescLeft"> </td><td class="mdescRight">ADC1 signal: AIN8 on PB06 mux B. <br /></td></tr>
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<tr class="separator:a870dd9e9de79013b71c884f30062abba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab19c4067bffed04b08722c49cd0c58c1"><td class="memItemLeft" align="right" valign="top"><a id="ab19c4067bffed04b08722c49cd0c58c1"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB06B_ADC1_AIN8</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:ab19c4067bffed04b08722c49cd0c58c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab77b33ffd45a8e03c3df37a78b4ef86a"><td class="memItemLeft" align="right" valign="top"><a id="ab77b33ffd45a8e03c3df37a78b4ef86a"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB06B_ADC1_AIN8</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a870dd9e9de79013b71c884f30062abba">PIN_PB06B_ADC1_AIN8</a> << 16) | MUX_PB06B_ADC1_AIN8)</td></tr>
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<tr class="separator:ab77b33ffd45a8e03c3df37a78b4ef86a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4924f6dc47262d954eae270ec61f2582"><td class="memItemLeft" align="right" valign="top"><a id="a4924f6dc47262d954eae270ec61f2582"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB06B_ADC1_AIN8</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 6)</td></tr>
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<tr class="separator:a4924f6dc47262d954eae270ec61f2582"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3b4e96995c22871c4335e70c008b11b3"><td class="memItemLeft" align="right" valign="top"><a id="a3b4e96995c22871c4335e70c008b11b3"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a3b4e96995c22871c4335e70c008b11b3">PIN_PB07B_ADC1_AIN9</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(39)</td></tr>
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<tr class="memdesc:a3b4e96995c22871c4335e70c008b11b3"><td class="mdescLeft"> </td><td class="mdescRight">ADC1 signal: AIN9 on PB07 mux B. <br /></td></tr>
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<tr class="memitem:aa880396cff2bb79aca6224de2482e039"><td class="memItemLeft" align="right" valign="top"><a id="aa880396cff2bb79aca6224de2482e039"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB07B_ADC1_AIN9</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:aa880396cff2bb79aca6224de2482e039"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5b0da4b3b3528cfdcb06677e322562fa"><td class="memItemLeft" align="right" valign="top"><a id="a5b0da4b3b3528cfdcb06677e322562fa"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB07B_ADC1_AIN9</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a3b4e96995c22871c4335e70c008b11b3">PIN_PB07B_ADC1_AIN9</a> << 16) | MUX_PB07B_ADC1_AIN9)</td></tr>
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<tr class="separator:a5b0da4b3b3528cfdcb06677e322562fa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2e8cbd678b132f5ac63ff77380958434"><td class="memItemLeft" align="right" valign="top"><a id="a2e8cbd678b132f5ac63ff77380958434"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB07B_ADC1_AIN9</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 7)</td></tr>
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<tr class="separator:a2e8cbd678b132f5ac63ff77380958434"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac287c4b9c3d4a192e62adb7f7d61308a"><td class="memItemLeft" align="right" valign="top"><a id="ac287c4b9c3d4a192e62adb7f7d61308a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac287c4b9c3d4a192e62adb7f7d61308a">PIN_PC00B_ADC1_AIN10</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(64)</td></tr>
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<tr class="memdesc:ac287c4b9c3d4a192e62adb7f7d61308a"><td class="mdescLeft"> </td><td class="mdescRight">ADC1 signal: AIN10 on PC00 mux B. <br /></td></tr>
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<tr class="separator:ac287c4b9c3d4a192e62adb7f7d61308a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af6367e515a5a930796d806e6c8797847"><td class="memItemLeft" align="right" valign="top"><a id="af6367e515a5a930796d806e6c8797847"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC00B_ADC1_AIN10</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:af6367e515a5a930796d806e6c8797847"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a843ab08c8b31e2a66425f13acad65e43"><td class="memItemLeft" align="right" valign="top"><a id="a843ab08c8b31e2a66425f13acad65e43"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC00B_ADC1_AIN10</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ac287c4b9c3d4a192e62adb7f7d61308a">PIN_PC00B_ADC1_AIN10</a> << 16) | MUX_PC00B_ADC1_AIN10)</td></tr>
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<tr class="separator:a843ab08c8b31e2a66425f13acad65e43"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad3e173441f319878caf6e5132944a6d5"><td class="memItemLeft" align="right" valign="top"><a id="ad3e173441f319878caf6e5132944a6d5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC00B_ADC1_AIN10</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 0)</td></tr>
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<tr class="separator:ad3e173441f319878caf6e5132944a6d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7e06599af49b239b423962d006539735"><td class="memItemLeft" align="right" valign="top"><a id="a7e06599af49b239b423962d006539735"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7e06599af49b239b423962d006539735">PIN_PC01B_ADC1_AIN11</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(65)</td></tr>
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<tr class="memdesc:a7e06599af49b239b423962d006539735"><td class="mdescLeft"> </td><td class="mdescRight">ADC1 signal: AIN11 on PC01 mux B. <br /></td></tr>
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<tr class="separator:a7e06599af49b239b423962d006539735"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a22e725a9007fcd8ca0432102e7440e7d"><td class="memItemLeft" align="right" valign="top"><a id="a22e725a9007fcd8ca0432102e7440e7d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC01B_ADC1_AIN11</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:a22e725a9007fcd8ca0432102e7440e7d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7a0d5139150cf2b363c50eadbcdd28ef"><td class="memItemLeft" align="right" valign="top"><a id="a7a0d5139150cf2b363c50eadbcdd28ef"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC01B_ADC1_AIN11</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a7e06599af49b239b423962d006539735">PIN_PC01B_ADC1_AIN11</a> << 16) | MUX_PC01B_ADC1_AIN11)</td></tr>
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<tr class="separator:a7a0d5139150cf2b363c50eadbcdd28ef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a15b92cd944bdbbdcd0dc2372cc666b4c"><td class="memItemLeft" align="right" valign="top"><a id="a15b92cd944bdbbdcd0dc2372cc666b4c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC01B_ADC1_AIN11</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 1)</td></tr>
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<tr class="separator:a15b92cd944bdbbdcd0dc2372cc666b4c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab5911f08cdb90b1f7879415264025446"><td class="memItemLeft" align="right" valign="top"><a id="ab5911f08cdb90b1f7879415264025446"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab5911f08cdb90b1f7879415264025446">PIN_PA02B_DAC_VOUT0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(2)</td></tr>
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<tr class="memdesc:ab5911f08cdb90b1f7879415264025446"><td class="mdescLeft"> </td><td class="mdescRight">DAC signal: VOUT0 on PA02 mux B. <br /></td></tr>
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<tr class="separator:ab5911f08cdb90b1f7879415264025446"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a46ec5090d324b4145d4040a85bf90adc"><td class="memItemLeft" align="right" valign="top"><a id="a46ec5090d324b4145d4040a85bf90adc"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA02B_DAC_VOUT0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:a46ec5090d324b4145d4040a85bf90adc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5bb356ee40525f4b3140e837eb32b821"><td class="memItemLeft" align="right" valign="top"><a id="a5bb356ee40525f4b3140e837eb32b821"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA02B_DAC_VOUT0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ab5911f08cdb90b1f7879415264025446">PIN_PA02B_DAC_VOUT0</a> << 16) | MUX_PA02B_DAC_VOUT0)</td></tr>
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<tr class="separator:a5bb356ee40525f4b3140e837eb32b821"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a60093b96f40cd9d381bd19c40afcd325"><td class="memItemLeft" align="right" valign="top"><a id="a60093b96f40cd9d381bd19c40afcd325"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA02B_DAC_VOUT0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 2)</td></tr>
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<tr class="separator:a60093b96f40cd9d381bd19c40afcd325"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a01411a15324989201b2c5de18969e07b"><td class="memItemLeft" align="right" valign="top"><a id="a01411a15324989201b2c5de18969e07b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a01411a15324989201b2c5de18969e07b">PIN_PA05B_DAC_VOUT1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(5)</td></tr>
|
||
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<tr class="memdesc:a01411a15324989201b2c5de18969e07b"><td class="mdescLeft"> </td><td class="mdescRight">DAC signal: VOUT1 on PA05 mux B. <br /></td></tr>
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<tr class="separator:a01411a15324989201b2c5de18969e07b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9ee5b32439bb67f0484aafb7529c5722"><td class="memItemLeft" align="right" valign="top"><a id="a9ee5b32439bb67f0484aafb7529c5722"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA05B_DAC_VOUT1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(1)</td></tr>
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<tr class="separator:a9ee5b32439bb67f0484aafb7529c5722"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab737c25ca971e678d68794da747006d3"><td class="memItemLeft" align="right" valign="top"><a id="ab737c25ca971e678d68794da747006d3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA05B_DAC_VOUT1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a01411a15324989201b2c5de18969e07b">PIN_PA05B_DAC_VOUT1</a> << 16) | MUX_PA05B_DAC_VOUT1)</td></tr>
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<tr class="separator:ab737c25ca971e678d68794da747006d3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4d2b39a2a6925ac0fae96f2eef079efa"><td class="memItemLeft" align="right" valign="top"><a id="a4d2b39a2a6925ac0fae96f2eef079efa"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA05B_DAC_VOUT1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 5)</td></tr>
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<tr class="separator:a4d2b39a2a6925ac0fae96f2eef079efa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad57f1dfcecdd92fdc301a0b7c076313a"><td class="memItemLeft" align="right" valign="top"><a id="ad57f1dfcecdd92fdc301a0b7c076313a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad57f1dfcecdd92fdc301a0b7c076313a">PIN_PA09J_I2S_FS0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
|
||
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<tr class="memdesc:ad57f1dfcecdd92fdc301a0b7c076313a"><td class="mdescLeft"> </td><td class="mdescRight">I2S signal: FS0 on PA09 mux J. <br /></td></tr>
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<tr class="separator:ad57f1dfcecdd92fdc301a0b7c076313a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a23d896ce9a1e06febdbb98b27fd3a7c8"><td class="memItemLeft" align="right" valign="top"><a id="a23d896ce9a1e06febdbb98b27fd3a7c8"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA09J_I2S_FS0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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<tr class="separator:a23d896ce9a1e06febdbb98b27fd3a7c8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a92c9cd6f480472aed142ccd6e1939795"><td class="memItemLeft" align="right" valign="top"><a id="a92c9cd6f480472aed142ccd6e1939795"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA09J_I2S_FS0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ad57f1dfcecdd92fdc301a0b7c076313a">PIN_PA09J_I2S_FS0</a> << 16) | MUX_PA09J_I2S_FS0)</td></tr>
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<tr class="separator:a92c9cd6f480472aed142ccd6e1939795"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a903a4c85dbf7dbdd44441c14db7aab00"><td class="memItemLeft" align="right" valign="top"><a id="a903a4c85dbf7dbdd44441c14db7aab00"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA09J_I2S_FS0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 9)</td></tr>
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<tr class="separator:a903a4c85dbf7dbdd44441c14db7aab00"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2e59889980df747b588d166ff0901abe"><td class="memItemLeft" align="right" valign="top"><a id="a2e59889980df747b588d166ff0901abe"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2e59889980df747b588d166ff0901abe">PIN_PA20J_I2S_FS0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(20)</td></tr>
|
||
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<tr class="memdesc:a2e59889980df747b588d166ff0901abe"><td class="mdescLeft"> </td><td class="mdescRight">I2S signal: FS0 on PA20 mux J. <br /></td></tr>
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<tr class="separator:a2e59889980df747b588d166ff0901abe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a96a14b43fbd8f56f8f371b89db32de8d"><td class="memItemLeft" align="right" valign="top"><a id="a96a14b43fbd8f56f8f371b89db32de8d"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA20J_I2S_FS0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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<tr class="separator:a96a14b43fbd8f56f8f371b89db32de8d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0daac4aea0084334f5061562a22b6c0a"><td class="memItemLeft" align="right" valign="top"><a id="a0daac4aea0084334f5061562a22b6c0a"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA20J_I2S_FS0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a2e59889980df747b588d166ff0901abe">PIN_PA20J_I2S_FS0</a> << 16) | MUX_PA20J_I2S_FS0)</td></tr>
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<tr class="separator:a0daac4aea0084334f5061562a22b6c0a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a453a0fdf46a8cf6cae52fa13442a0d74"><td class="memItemLeft" align="right" valign="top"><a id="a453a0fdf46a8cf6cae52fa13442a0d74"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA20J_I2S_FS0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 20)</td></tr>
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<tr class="separator:a453a0fdf46a8cf6cae52fa13442a0d74"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a70dece10118a43cc55302df35b37ad63"><td class="memItemLeft" align="right" valign="top"><a id="a70dece10118a43cc55302df35b37ad63"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a70dece10118a43cc55302df35b37ad63">PIN_PA23J_I2S_FS1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(23)</td></tr>
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||
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<tr class="memdesc:a70dece10118a43cc55302df35b37ad63"><td class="mdescLeft"> </td><td class="mdescRight">I2S signal: FS1 on PA23 mux J. <br /></td></tr>
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<tr class="separator:a70dece10118a43cc55302df35b37ad63"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae9b04bf35b1c8c91eff3f68cef4d9882"><td class="memItemLeft" align="right" valign="top"><a id="ae9b04bf35b1c8c91eff3f68cef4d9882"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA23J_I2S_FS1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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<tr class="separator:ae9b04bf35b1c8c91eff3f68cef4d9882"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aef96fe988a97e4d3939dc38c40efd91a"><td class="memItemLeft" align="right" valign="top"><a id="aef96fe988a97e4d3939dc38c40efd91a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA23J_I2S_FS1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a70dece10118a43cc55302df35b37ad63">PIN_PA23J_I2S_FS1</a> << 16) | MUX_PA23J_I2S_FS1)</td></tr>
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<tr class="separator:aef96fe988a97e4d3939dc38c40efd91a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a47f95c2700b0a2d201d4580d23d59082"><td class="memItemLeft" align="right" valign="top"><a id="a47f95c2700b0a2d201d4580d23d59082"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA23J_I2S_FS1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 23)</td></tr>
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<tr class="separator:a47f95c2700b0a2d201d4580d23d59082"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a68d2992f731b20c19f0ae740157d5213"><td class="memItemLeft" align="right" valign="top"><a id="a68d2992f731b20c19f0ae740157d5213"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a68d2992f731b20c19f0ae740157d5213">PIN_PB11J_I2S_FS1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(43)</td></tr>
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<tr class="memdesc:a68d2992f731b20c19f0ae740157d5213"><td class="mdescLeft"> </td><td class="mdescRight">I2S signal: FS1 on PB11 mux J. <br /></td></tr>
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<tr class="separator:a68d2992f731b20c19f0ae740157d5213"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9757c46458377a46bdcae0bc7a288eb8"><td class="memItemLeft" align="right" valign="top"><a id="a9757c46458377a46bdcae0bc7a288eb8"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB11J_I2S_FS1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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<tr class="separator:a9757c46458377a46bdcae0bc7a288eb8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a272ff486619fcd4c682db21fea441186"><td class="memItemLeft" align="right" valign="top"><a id="a272ff486619fcd4c682db21fea441186"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB11J_I2S_FS1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a68d2992f731b20c19f0ae740157d5213">PIN_PB11J_I2S_FS1</a> << 16) | MUX_PB11J_I2S_FS1)</td></tr>
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<tr class="separator:a272ff486619fcd4c682db21fea441186"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac1ad24861aa7fa184fa5eea5dc5c2ac9"><td class="memItemLeft" align="right" valign="top"><a id="ac1ad24861aa7fa184fa5eea5dc5c2ac9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB11J_I2S_FS1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 11)</td></tr>
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<tr class="separator:ac1ad24861aa7fa184fa5eea5dc5c2ac9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abdb786683728918a543efeb2c12023cc"><td class="memItemLeft" align="right" valign="top"><a id="abdb786683728918a543efeb2c12023cc"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#abdb786683728918a543efeb2c12023cc">PIN_PA08J_I2S_MCK0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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||
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<tr class="memdesc:abdb786683728918a543efeb2c12023cc"><td class="mdescLeft"> </td><td class="mdescRight">I2S signal: MCK0 on PA08 mux J. <br /></td></tr>
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<tr class="separator:abdb786683728918a543efeb2c12023cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4c50f5f4a35d40df06174fe7b719be97"><td class="memItemLeft" align="right" valign="top"><a id="a4c50f5f4a35d40df06174fe7b719be97"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA08J_I2S_MCK0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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<tr class="separator:a4c50f5f4a35d40df06174fe7b719be97"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3b0ddea3965a93fcf852bcd1aee961a9"><td class="memItemLeft" align="right" valign="top"><a id="a3b0ddea3965a93fcf852bcd1aee961a9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA08J_I2S_MCK0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#abdb786683728918a543efeb2c12023cc">PIN_PA08J_I2S_MCK0</a> << 16) | MUX_PA08J_I2S_MCK0)</td></tr>
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<tr class="separator:a3b0ddea3965a93fcf852bcd1aee961a9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a545691457897ea1944e031750b3fb6b4"><td class="memItemLeft" align="right" valign="top"><a id="a545691457897ea1944e031750b3fb6b4"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA08J_I2S_MCK0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 8)</td></tr>
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<tr class="separator:a545691457897ea1944e031750b3fb6b4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a375c1c34361038e192c89561d6541957"><td class="memItemLeft" align="right" valign="top"><a id="a375c1c34361038e192c89561d6541957"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a375c1c34361038e192c89561d6541957">PIN_PB17J_I2S_MCK0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(49)</td></tr>
|
||
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<tr class="memdesc:a375c1c34361038e192c89561d6541957"><td class="mdescLeft"> </td><td class="mdescRight">I2S signal: MCK0 on PB17 mux J. <br /></td></tr>
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<tr class="separator:a375c1c34361038e192c89561d6541957"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aba6d58e262c78b7e8ec6301ac471cc0c"><td class="memItemLeft" align="right" valign="top"><a id="aba6d58e262c78b7e8ec6301ac471cc0c"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB17J_I2S_MCK0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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||
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<tr class="separator:aba6d58e262c78b7e8ec6301ac471cc0c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af38569ebcfd7f2d6954294c6dfafdfb9"><td class="memItemLeft" align="right" valign="top"><a id="af38569ebcfd7f2d6954294c6dfafdfb9"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB17J_I2S_MCK0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a375c1c34361038e192c89561d6541957">PIN_PB17J_I2S_MCK0</a> << 16) | MUX_PB17J_I2S_MCK0)</td></tr>
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<tr class="separator:af38569ebcfd7f2d6954294c6dfafdfb9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad03729ce4a66d0d6b59dc9f54bd846d7"><td class="memItemLeft" align="right" valign="top"><a id="ad03729ce4a66d0d6b59dc9f54bd846d7"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB17J_I2S_MCK0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 17)</td></tr>
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||
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<tr class="separator:ad03729ce4a66d0d6b59dc9f54bd846d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4d12818153babaa8ee70733398df2b4d"><td class="memItemLeft" align="right" valign="top"><a id="a4d12818153babaa8ee70733398df2b4d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4d12818153babaa8ee70733398df2b4d">PIN_PB13J_I2S_MCK1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(45)</td></tr>
|
||
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<tr class="memdesc:a4d12818153babaa8ee70733398df2b4d"><td class="mdescLeft"> </td><td class="mdescRight">I2S signal: MCK1 on PB13 mux J. <br /></td></tr>
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<tr class="separator:a4d12818153babaa8ee70733398df2b4d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0a0303a01b4f3272f7754f8732a59426"><td class="memItemLeft" align="right" valign="top"><a id="a0a0303a01b4f3272f7754f8732a59426"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB13J_I2S_MCK1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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||
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<tr class="separator:a0a0303a01b4f3272f7754f8732a59426"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4c4561f9fe3f9a282234dbf9358cc46e"><td class="memItemLeft" align="right" valign="top"><a id="a4c4561f9fe3f9a282234dbf9358cc46e"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB13J_I2S_MCK1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a4d12818153babaa8ee70733398df2b4d">PIN_PB13J_I2S_MCK1</a> << 16) | MUX_PB13J_I2S_MCK1)</td></tr>
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<tr class="separator:a4c4561f9fe3f9a282234dbf9358cc46e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a554cc20ac808e6ad317b2b9f062ede94"><td class="memItemLeft" align="right" valign="top"><a id="a554cc20ac808e6ad317b2b9f062ede94"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB13J_I2S_MCK1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 13)</td></tr>
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<tr class="separator:a554cc20ac808e6ad317b2b9f062ede94"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9cdbd4d3cfc40b7d10d7e6c584bc8ca1"><td class="memItemLeft" align="right" valign="top"><a id="a9cdbd4d3cfc40b7d10d7e6c584bc8ca1"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a9cdbd4d3cfc40b7d10d7e6c584bc8ca1">PIN_PA10J_I2S_SCK0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
|
||
|
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<tr class="memdesc:a9cdbd4d3cfc40b7d10d7e6c584bc8ca1"><td class="mdescLeft"> </td><td class="mdescRight">I2S signal: SCK0 on PA10 mux J. <br /></td></tr>
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<tr class="separator:a9cdbd4d3cfc40b7d10d7e6c584bc8ca1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a85eb93722172572f5a406b33e6cbdd34"><td class="memItemLeft" align="right" valign="top"><a id="a85eb93722172572f5a406b33e6cbdd34"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA10J_I2S_SCK0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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||
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<tr class="separator:a85eb93722172572f5a406b33e6cbdd34"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4739c48d133971dbcdba636322193a7b"><td class="memItemLeft" align="right" valign="top"><a id="a4739c48d133971dbcdba636322193a7b"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA10J_I2S_SCK0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a9cdbd4d3cfc40b7d10d7e6c584bc8ca1">PIN_PA10J_I2S_SCK0</a> << 16) | MUX_PA10J_I2S_SCK0)</td></tr>
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<tr class="separator:a4739c48d133971dbcdba636322193a7b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1144eceb63c2270dc15286d69f5eec52"><td class="memItemLeft" align="right" valign="top"><a id="a1144eceb63c2270dc15286d69f5eec52"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA10J_I2S_SCK0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 10)</td></tr>
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||
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<tr class="separator:a1144eceb63c2270dc15286d69f5eec52"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aace264fd0a10582361b0388268bad25f"><td class="memItemLeft" align="right" valign="top"><a id="aace264fd0a10582361b0388268bad25f"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aace264fd0a10582361b0388268bad25f">PIN_PB16J_I2S_SCK0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(48)</td></tr>
|
||
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<tr class="memdesc:aace264fd0a10582361b0388268bad25f"><td class="mdescLeft"> </td><td class="mdescRight">I2S signal: SCK0 on PB16 mux J. <br /></td></tr>
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<tr class="separator:aace264fd0a10582361b0388268bad25f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8830fd2d3df73ac5b3f18ca6e2c98cf4"><td class="memItemLeft" align="right" valign="top"><a id="a8830fd2d3df73ac5b3f18ca6e2c98cf4"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB16J_I2S_SCK0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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||
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<tr class="separator:a8830fd2d3df73ac5b3f18ca6e2c98cf4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a23b2484e1d4bf22b8a287a733dd2bbcd"><td class="memItemLeft" align="right" valign="top"><a id="a23b2484e1d4bf22b8a287a733dd2bbcd"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB16J_I2S_SCK0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aace264fd0a10582361b0388268bad25f">PIN_PB16J_I2S_SCK0</a> << 16) | MUX_PB16J_I2S_SCK0)</td></tr>
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<tr class="separator:a23b2484e1d4bf22b8a287a733dd2bbcd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aad0141083a7b40a61ed4e6ec79989fe7"><td class="memItemLeft" align="right" valign="top"><a id="aad0141083a7b40a61ed4e6ec79989fe7"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB16J_I2S_SCK0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 16)</td></tr>
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||
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<tr class="separator:aad0141083a7b40a61ed4e6ec79989fe7"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:aab56848fdaf7f85c3eebb0b045610486"><td class="memItemLeft" align="right" valign="top"><a id="aab56848fdaf7f85c3eebb0b045610486"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aab56848fdaf7f85c3eebb0b045610486">PIN_PB12J_I2S_SCK1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(44)</td></tr>
|
||
|
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<tr class="memdesc:aab56848fdaf7f85c3eebb0b045610486"><td class="mdescLeft"> </td><td class="mdescRight">I2S signal: SCK1 on PB12 mux J. <br /></td></tr>
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<tr class="separator:aab56848fdaf7f85c3eebb0b045610486"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af3a858f182495958333e129cf2e25e28"><td class="memItemLeft" align="right" valign="top"><a id="af3a858f182495958333e129cf2e25e28"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB12J_I2S_SCK1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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||
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<tr class="separator:af3a858f182495958333e129cf2e25e28"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:ad1e28e121073a79632774cbf3c582e9a"><td class="memItemLeft" align="right" valign="top"><a id="ad1e28e121073a79632774cbf3c582e9a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB12J_I2S_SCK1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aab56848fdaf7f85c3eebb0b045610486">PIN_PB12J_I2S_SCK1</a> << 16) | MUX_PB12J_I2S_SCK1)</td></tr>
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<tr class="memitem:ae33d68f977903f0a79c319e48c257be3"><td class="memItemLeft" align="right" valign="top"><a id="ae33d68f977903f0a79c319e48c257be3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB12J_I2S_SCK1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 12)</td></tr>
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<tr class="separator:ae33d68f977903f0a79c319e48c257be3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2c545bc1954b16d4aeb60999133d9b99"><td class="memItemLeft" align="right" valign="top"><a id="a2c545bc1954b16d4aeb60999133d9b99"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2c545bc1954b16d4aeb60999133d9b99">PIN_PA22J_I2S_SDI</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(22)</td></tr>
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<tr class="memdesc:a2c545bc1954b16d4aeb60999133d9b99"><td class="mdescLeft"> </td><td class="mdescRight">I2S signal: SDI on PA22 mux J. <br /></td></tr>
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<tr class="separator:a2c545bc1954b16d4aeb60999133d9b99"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a24f624b381e1ff45acf2d70516a15d82"><td class="memItemLeft" align="right" valign="top"><a id="a24f624b381e1ff45acf2d70516a15d82"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA22J_I2S_SDI</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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<tr class="separator:a24f624b381e1ff45acf2d70516a15d82"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af8f39f6e8e9d57773102c2e2530f80a0"><td class="memItemLeft" align="right" valign="top"><a id="af8f39f6e8e9d57773102c2e2530f80a0"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA22J_I2S_SDI</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a2c545bc1954b16d4aeb60999133d9b99">PIN_PA22J_I2S_SDI</a> << 16) | MUX_PA22J_I2S_SDI)</td></tr>
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<tr class="separator:af8f39f6e8e9d57773102c2e2530f80a0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a33d32afffccd4f756a9b142d38995a05"><td class="memItemLeft" align="right" valign="top"><a id="a33d32afffccd4f756a9b142d38995a05"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA22J_I2S_SDI</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 22)</td></tr>
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<tr class="separator:a33d32afffccd4f756a9b142d38995a05"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a69b0fa5e8f8cc71567a13d2d6311fc16"><td class="memItemLeft" align="right" valign="top"><a id="a69b0fa5e8f8cc71567a13d2d6311fc16"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a69b0fa5e8f8cc71567a13d2d6311fc16">PIN_PB10J_I2S_SDI</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(42)</td></tr>
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<tr class="memdesc:a69b0fa5e8f8cc71567a13d2d6311fc16"><td class="mdescLeft"> </td><td class="mdescRight">I2S signal: SDI on PB10 mux J. <br /></td></tr>
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<tr class="separator:a69b0fa5e8f8cc71567a13d2d6311fc16"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa1cf96a09446d80f728d0016cb1c0acc"><td class="memItemLeft" align="right" valign="top"><a id="aa1cf96a09446d80f728d0016cb1c0acc"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB10J_I2S_SDI</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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<tr class="separator:aa1cf96a09446d80f728d0016cb1c0acc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a455a02384a542a3be722cd70621f8d94"><td class="memItemLeft" align="right" valign="top"><a id="a455a02384a542a3be722cd70621f8d94"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB10J_I2S_SDI</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a69b0fa5e8f8cc71567a13d2d6311fc16">PIN_PB10J_I2S_SDI</a> << 16) | MUX_PB10J_I2S_SDI)</td></tr>
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<tr class="separator:a455a02384a542a3be722cd70621f8d94"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2816e0f148fab51f887dab3c0f3f17a2"><td class="memItemLeft" align="right" valign="top"><a id="a2816e0f148fab51f887dab3c0f3f17a2"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB10J_I2S_SDI</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 10)</td></tr>
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||
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<tr class="separator:a2816e0f148fab51f887dab3c0f3f17a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7f7b2b73be9dad6b4dad521f9c315523"><td class="memItemLeft" align="right" valign="top"><a id="a7f7b2b73be9dad6b4dad521f9c315523"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7f7b2b73be9dad6b4dad521f9c315523">PIN_PA11J_I2S_SDO</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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||
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<tr class="memdesc:a7f7b2b73be9dad6b4dad521f9c315523"><td class="mdescLeft"> </td><td class="mdescRight">I2S signal: SDO on PA11 mux J. <br /></td></tr>
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<tr class="separator:a7f7b2b73be9dad6b4dad521f9c315523"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a48ccce89abda0e1909d1bdd223127b8a"><td class="memItemLeft" align="right" valign="top"><a id="a48ccce89abda0e1909d1bdd223127b8a"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA11J_I2S_SDO</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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<tr class="separator:a48ccce89abda0e1909d1bdd223127b8a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a254e6c34d0b6e35f43bc19622d55aaa2"><td class="memItemLeft" align="right" valign="top"><a id="a254e6c34d0b6e35f43bc19622d55aaa2"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA11J_I2S_SDO</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a7f7b2b73be9dad6b4dad521f9c315523">PIN_PA11J_I2S_SDO</a> << 16) | MUX_PA11J_I2S_SDO)</td></tr>
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<tr class="separator:a254e6c34d0b6e35f43bc19622d55aaa2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aff80164a97db5e2c92a99a488f22c95b"><td class="memItemLeft" align="right" valign="top"><a id="aff80164a97db5e2c92a99a488f22c95b"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA11J_I2S_SDO</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 11)</td></tr>
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||
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<tr class="separator:aff80164a97db5e2c92a99a488f22c95b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abbec72d29abc239aa2239b373bd15572"><td class="memItemLeft" align="right" valign="top"><a id="abbec72d29abc239aa2239b373bd15572"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#abbec72d29abc239aa2239b373bd15572">PIN_PA21J_I2S_SDO</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(21)</td></tr>
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||
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<tr class="memdesc:abbec72d29abc239aa2239b373bd15572"><td class="mdescLeft"> </td><td class="mdescRight">I2S signal: SDO on PA21 mux J. <br /></td></tr>
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<tr class="separator:abbec72d29abc239aa2239b373bd15572"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a72a338218d95853444ef8b6abfcc745e"><td class="memItemLeft" align="right" valign="top"><a id="a72a338218d95853444ef8b6abfcc745e"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA21J_I2S_SDO</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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||
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<tr class="separator:a72a338218d95853444ef8b6abfcc745e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac8269e493d9592bd2bc262b3be9ed7dc"><td class="memItemLeft" align="right" valign="top"><a id="ac8269e493d9592bd2bc262b3be9ed7dc"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA21J_I2S_SDO</b>   ((<a class="el" href="pio_2same54p20a_8h.html#abbec72d29abc239aa2239b373bd15572">PIN_PA21J_I2S_SDO</a> << 16) | MUX_PA21J_I2S_SDO)</td></tr>
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<tr class="separator:ac8269e493d9592bd2bc262b3be9ed7dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0f4cb105585a788624f1d4b927a1d078"><td class="memItemLeft" align="right" valign="top"><a id="a0f4cb105585a788624f1d4b927a1d078"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA21J_I2S_SDO</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 21)</td></tr>
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||
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<tr class="separator:a0f4cb105585a788624f1d4b927a1d078"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a411bd3e7690b568fa356436eca829b79"><td class="memItemLeft" align="right" valign="top"><a id="a411bd3e7690b568fa356436eca829b79"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a411bd3e7690b568fa356436eca829b79">PIN_PA14K_PCC_CLK</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(14)</td></tr>
|
||
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<tr class="memdesc:a411bd3e7690b568fa356436eca829b79"><td class="mdescLeft"> </td><td class="mdescRight">PCC signal: CLK on PA14 mux K. <br /></td></tr>
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<tr class="separator:a411bd3e7690b568fa356436eca829b79"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae10b8abd4d59606296fa5f7d9fd0b8fd"><td class="memItemLeft" align="right" valign="top"><a id="ae10b8abd4d59606296fa5f7d9fd0b8fd"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA14K_PCC_CLK</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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<tr class="separator:ae10b8abd4d59606296fa5f7d9fd0b8fd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a04e70dde26219320db4a595e83a12305"><td class="memItemLeft" align="right" valign="top"><a id="a04e70dde26219320db4a595e83a12305"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA14K_PCC_CLK</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a411bd3e7690b568fa356436eca829b79">PIN_PA14K_PCC_CLK</a> << 16) | MUX_PA14K_PCC_CLK)</td></tr>
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<tr class="separator:a04e70dde26219320db4a595e83a12305"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a47ef5f5c209acaa6801fb8215cb75975"><td class="memItemLeft" align="right" valign="top"><a id="a47ef5f5c209acaa6801fb8215cb75975"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA14K_PCC_CLK</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 14)</td></tr>
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<tr class="separator:a47ef5f5c209acaa6801fb8215cb75975"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6b3fb5e2876d9e9ec3655e3d55ae23a8"><td class="memItemLeft" align="right" valign="top"><a id="a6b3fb5e2876d9e9ec3655e3d55ae23a8"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6b3fb5e2876d9e9ec3655e3d55ae23a8">PIN_PA16K_PCC_DATA0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(16)</td></tr>
|
||
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<tr class="memdesc:a6b3fb5e2876d9e9ec3655e3d55ae23a8"><td class="mdescLeft"> </td><td class="mdescRight">PCC signal: DATA0 on PA16 mux K. <br /></td></tr>
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||
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<tr class="separator:a6b3fb5e2876d9e9ec3655e3d55ae23a8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad51010adf25e2f46d68d7e37cbca22a4"><td class="memItemLeft" align="right" valign="top"><a id="ad51010adf25e2f46d68d7e37cbca22a4"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA16K_PCC_DATA0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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||
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<tr class="separator:ad51010adf25e2f46d68d7e37cbca22a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ade03cae1329beeb7bb92295d39083d70"><td class="memItemLeft" align="right" valign="top"><a id="ade03cae1329beeb7bb92295d39083d70"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA16K_PCC_DATA0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a6b3fb5e2876d9e9ec3655e3d55ae23a8">PIN_PA16K_PCC_DATA0</a> << 16) | MUX_PA16K_PCC_DATA0)</td></tr>
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<tr class="separator:ade03cae1329beeb7bb92295d39083d70"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab2f7ae61acc8b0cf658a5c54d9ff1b42"><td class="memItemLeft" align="right" valign="top"><a id="ab2f7ae61acc8b0cf658a5c54d9ff1b42"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA16K_PCC_DATA0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 16)</td></tr>
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||
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<tr class="separator:ab2f7ae61acc8b0cf658a5c54d9ff1b42"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1aad4374898a1652ca028abdabff42d1"><td class="memItemLeft" align="right" valign="top"><a id="a1aad4374898a1652ca028abdabff42d1"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1aad4374898a1652ca028abdabff42d1">PIN_PA17K_PCC_DATA1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(17)</td></tr>
|
||
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<tr class="memdesc:a1aad4374898a1652ca028abdabff42d1"><td class="mdescLeft"> </td><td class="mdescRight">PCC signal: DATA1 on PA17 mux K. <br /></td></tr>
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||
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<tr class="separator:a1aad4374898a1652ca028abdabff42d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a858fb6a37b4922cd0938284d10f87e2a"><td class="memItemLeft" align="right" valign="top"><a id="a858fb6a37b4922cd0938284d10f87e2a"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA17K_PCC_DATA1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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||
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<tr class="separator:a858fb6a37b4922cd0938284d10f87e2a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afd92385e16d96ca702e7a1918c2152af"><td class="memItemLeft" align="right" valign="top"><a id="afd92385e16d96ca702e7a1918c2152af"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA17K_PCC_DATA1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a1aad4374898a1652ca028abdabff42d1">PIN_PA17K_PCC_DATA1</a> << 16) | MUX_PA17K_PCC_DATA1)</td></tr>
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<tr class="separator:afd92385e16d96ca702e7a1918c2152af"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a638df51a03b25e12b3b44d7210f63fb1"><td class="memItemLeft" align="right" valign="top"><a id="a638df51a03b25e12b3b44d7210f63fb1"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA17K_PCC_DATA1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 17)</td></tr>
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||
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<tr class="separator:a638df51a03b25e12b3b44d7210f63fb1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a579c6c8bc97df0de75f0ca3bd31af7fd"><td class="memItemLeft" align="right" valign="top"><a id="a579c6c8bc97df0de75f0ca3bd31af7fd"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a579c6c8bc97df0de75f0ca3bd31af7fd">PIN_PA18K_PCC_DATA2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(18)</td></tr>
|
||
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<tr class="memdesc:a579c6c8bc97df0de75f0ca3bd31af7fd"><td class="mdescLeft"> </td><td class="mdescRight">PCC signal: DATA2 on PA18 mux K. <br /></td></tr>
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||
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<tr class="separator:a579c6c8bc97df0de75f0ca3bd31af7fd"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a96950874b68479ff6da7dea1c29c68cf"><td class="memItemLeft" align="right" valign="top"><a id="a96950874b68479ff6da7dea1c29c68cf"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA18K_PCC_DATA2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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||
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<tr class="separator:a96950874b68479ff6da7dea1c29c68cf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af8533f9d4df3f9e4a336f75cb0f3ee13"><td class="memItemLeft" align="right" valign="top"><a id="af8533f9d4df3f9e4a336f75cb0f3ee13"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA18K_PCC_DATA2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a579c6c8bc97df0de75f0ca3bd31af7fd">PIN_PA18K_PCC_DATA2</a> << 16) | MUX_PA18K_PCC_DATA2)</td></tr>
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||
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<tr class="separator:af8533f9d4df3f9e4a336f75cb0f3ee13"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:acabcbdbefd41873e5d86d3284e5dd052"><td class="memItemLeft" align="right" valign="top"><a id="acabcbdbefd41873e5d86d3284e5dd052"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA18K_PCC_DATA2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 18)</td></tr>
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||
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<tr class="separator:acabcbdbefd41873e5d86d3284e5dd052"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a159ef1fbea04782bcb324845399db83a"><td class="memItemLeft" align="right" valign="top"><a id="a159ef1fbea04782bcb324845399db83a"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a159ef1fbea04782bcb324845399db83a">PIN_PA19K_PCC_DATA3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(19)</td></tr>
|
||
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<tr class="memdesc:a159ef1fbea04782bcb324845399db83a"><td class="mdescLeft"> </td><td class="mdescRight">PCC signal: DATA3 on PA19 mux K. <br /></td></tr>
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||
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<tr class="separator:a159ef1fbea04782bcb324845399db83a"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a3a23bfa1a8314b957e4f7dc34300ecfe"><td class="memItemLeft" align="right" valign="top"><a id="a3a23bfa1a8314b957e4f7dc34300ecfe"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA19K_PCC_DATA3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
|
||
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<tr class="separator:a3a23bfa1a8314b957e4f7dc34300ecfe"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:a741fc2d416e0102bf18d7206acb01ae2"><td class="memItemLeft" align="right" valign="top"><a id="a741fc2d416e0102bf18d7206acb01ae2"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA19K_PCC_DATA3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a159ef1fbea04782bcb324845399db83a">PIN_PA19K_PCC_DATA3</a> << 16) | MUX_PA19K_PCC_DATA3)</td></tr>
|
||
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<tr class="separator:a741fc2d416e0102bf18d7206acb01ae2"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:ac665053b9c01208924ffdb0f0a36b04e"><td class="memItemLeft" align="right" valign="top"><a id="ac665053b9c01208924ffdb0f0a36b04e"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA19K_PCC_DATA3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 19)</td></tr>
|
||
|
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<tr class="separator:ac665053b9c01208924ffdb0f0a36b04e"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:ac928db310ac25bb5b4db52e595ba49a4"><td class="memItemLeft" align="right" valign="top"><a id="ac928db310ac25bb5b4db52e595ba49a4"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac928db310ac25bb5b4db52e595ba49a4">PIN_PA20K_PCC_DATA4</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(20)</td></tr>
|
||
|
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<tr class="memdesc:ac928db310ac25bb5b4db52e595ba49a4"><td class="mdescLeft"> </td><td class="mdescRight">PCC signal: DATA4 on PA20 mux K. <br /></td></tr>
|
||
|
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<tr class="separator:ac928db310ac25bb5b4db52e595ba49a4"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:aef5b522747ccec1a1b95858042247d61"><td class="memItemLeft" align="right" valign="top"><a id="aef5b522747ccec1a1b95858042247d61"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA20K_PCC_DATA4</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
|
||
|
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<tr class="separator:aef5b522747ccec1a1b95858042247d61"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:aebb6ee09bc69f6e6daa56aa324b4804c"><td class="memItemLeft" align="right" valign="top"><a id="aebb6ee09bc69f6e6daa56aa324b4804c"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA20K_PCC_DATA4</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ac928db310ac25bb5b4db52e595ba49a4">PIN_PA20K_PCC_DATA4</a> << 16) | MUX_PA20K_PCC_DATA4)</td></tr>
|
||
|
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<tr class="separator:aebb6ee09bc69f6e6daa56aa324b4804c"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:aee283201b14291d50c7d7c6cdbbfe6ad"><td class="memItemLeft" align="right" valign="top"><a id="aee283201b14291d50c7d7c6cdbbfe6ad"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA20K_PCC_DATA4</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 20)</td></tr>
|
||
|
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<tr class="separator:aee283201b14291d50c7d7c6cdbbfe6ad"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:a0c422e9182101dd4c2cb6a1cefd89b59"><td class="memItemLeft" align="right" valign="top"><a id="a0c422e9182101dd4c2cb6a1cefd89b59"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a0c422e9182101dd4c2cb6a1cefd89b59">PIN_PA21K_PCC_DATA5</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(21)</td></tr>
|
||
|
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<tr class="memdesc:a0c422e9182101dd4c2cb6a1cefd89b59"><td class="mdescLeft"> </td><td class="mdescRight">PCC signal: DATA5 on PA21 mux K. <br /></td></tr>
|
||
|
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<tr class="separator:a0c422e9182101dd4c2cb6a1cefd89b59"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:ae5ec056d119545cb50e692261e981b9a"><td class="memItemLeft" align="right" valign="top"><a id="ae5ec056d119545cb50e692261e981b9a"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA21K_PCC_DATA5</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
|
||
|
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<tr class="separator:ae5ec056d119545cb50e692261e981b9a"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:a902c5748fcbf4f85df249ed64c1c8c1c"><td class="memItemLeft" align="right" valign="top"><a id="a902c5748fcbf4f85df249ed64c1c8c1c"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA21K_PCC_DATA5</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a0c422e9182101dd4c2cb6a1cefd89b59">PIN_PA21K_PCC_DATA5</a> << 16) | MUX_PA21K_PCC_DATA5)</td></tr>
|
||
|
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<tr class="separator:a902c5748fcbf4f85df249ed64c1c8c1c"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:a5d5d7442fa517e6483c57e1ec95494a6"><td class="memItemLeft" align="right" valign="top"><a id="a5d5d7442fa517e6483c57e1ec95494a6"></a>
|
||
|
|
#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA21K_PCC_DATA5</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 21)</td></tr>
|
||
|
|
<tr class="separator:a5d5d7442fa517e6483c57e1ec95494a6"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:ab259822602b60999587ffd97ce517ef3"><td class="memItemLeft" align="right" valign="top"><a id="ab259822602b60999587ffd97ce517ef3"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ab259822602b60999587ffd97ce517ef3">PIN_PA22K_PCC_DATA6</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(22)</td></tr>
|
||
|
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<tr class="memdesc:ab259822602b60999587ffd97ce517ef3"><td class="mdescLeft"> </td><td class="mdescRight">PCC signal: DATA6 on PA22 mux K. <br /></td></tr>
|
||
|
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<tr class="separator:ab259822602b60999587ffd97ce517ef3"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:a5b987af0771f5f01c46d7dbced40c2bd"><td class="memItemLeft" align="right" valign="top"><a id="a5b987af0771f5f01c46d7dbced40c2bd"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA22K_PCC_DATA6</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
|
||
|
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<tr class="separator:a5b987af0771f5f01c46d7dbced40c2bd"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:a65c39e3964064ff21dc9813ae9892bce"><td class="memItemLeft" align="right" valign="top"><a id="a65c39e3964064ff21dc9813ae9892bce"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA22K_PCC_DATA6</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ab259822602b60999587ffd97ce517ef3">PIN_PA22K_PCC_DATA6</a> << 16) | MUX_PA22K_PCC_DATA6)</td></tr>
|
||
|
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<tr class="separator:a65c39e3964064ff21dc9813ae9892bce"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:a1b9fb845825a802e475a2d20b43c3fc4"><td class="memItemLeft" align="right" valign="top"><a id="a1b9fb845825a802e475a2d20b43c3fc4"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA22K_PCC_DATA6</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 22)</td></tr>
|
||
|
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<tr class="separator:a1b9fb845825a802e475a2d20b43c3fc4"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
|
<tr class="memitem:acc6782550f27bce322f863060115b087"><td class="memItemLeft" align="right" valign="top"><a id="acc6782550f27bce322f863060115b087"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#acc6782550f27bce322f863060115b087">PIN_PA23K_PCC_DATA7</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(23)</td></tr>
|
||
|
|
<tr class="memdesc:acc6782550f27bce322f863060115b087"><td class="mdescLeft"> </td><td class="mdescRight">PCC signal: DATA7 on PA23 mux K. <br /></td></tr>
|
||
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<tr class="separator:acc6782550f27bce322f863060115b087"><td class="memSeparator" colspan="2"> </td></tr>
|
||
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<tr class="memitem:aa41b10be911fd79bbdd2c33ed7a200eb"><td class="memItemLeft" align="right" valign="top"><a id="aa41b10be911fd79bbdd2c33ed7a200eb"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA23K_PCC_DATA7</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
|
||
|
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<tr class="separator:aa41b10be911fd79bbdd2c33ed7a200eb"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:a66db1423c06f9e658d392e647266a555"><td class="memItemLeft" align="right" valign="top"><a id="a66db1423c06f9e658d392e647266a555"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA23K_PCC_DATA7</b>   ((<a class="el" href="pio_2same54p20a_8h.html#acc6782550f27bce322f863060115b087">PIN_PA23K_PCC_DATA7</a> << 16) | MUX_PA23K_PCC_DATA7)</td></tr>
|
||
|
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<tr class="separator:a66db1423c06f9e658d392e647266a555"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:a515c027df3315d1c310b0cf55012222f"><td class="memItemLeft" align="right" valign="top"><a id="a515c027df3315d1c310b0cf55012222f"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA23K_PCC_DATA7</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 23)</td></tr>
|
||
|
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<tr class="separator:a515c027df3315d1c310b0cf55012222f"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:ad5c99a74d773dc0d73987345fa1c8282"><td class="memItemLeft" align="right" valign="top"><a id="ad5c99a74d773dc0d73987345fa1c8282"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad5c99a74d773dc0d73987345fa1c8282">PIN_PB14K_PCC_DATA8</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(46)</td></tr>
|
||
|
|
<tr class="memdesc:ad5c99a74d773dc0d73987345fa1c8282"><td class="mdescLeft"> </td><td class="mdescRight">PCC signal: DATA8 on PB14 mux K. <br /></td></tr>
|
||
|
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<tr class="separator:ad5c99a74d773dc0d73987345fa1c8282"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:ab23d9050756d7e56c6eca2bc91936e90"><td class="memItemLeft" align="right" valign="top"><a id="ab23d9050756d7e56c6eca2bc91936e90"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB14K_PCC_DATA8</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
|
||
|
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<tr class="separator:ab23d9050756d7e56c6eca2bc91936e90"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:ab0f86312fa0686bd7d14260ec2afacba"><td class="memItemLeft" align="right" valign="top"><a id="ab0f86312fa0686bd7d14260ec2afacba"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB14K_PCC_DATA8</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ad5c99a74d773dc0d73987345fa1c8282">PIN_PB14K_PCC_DATA8</a> << 16) | MUX_PB14K_PCC_DATA8)</td></tr>
|
||
|
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<tr class="separator:ab0f86312fa0686bd7d14260ec2afacba"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:aa3964b500a9f109a46fec95fa4fa0063"><td class="memItemLeft" align="right" valign="top"><a id="aa3964b500a9f109a46fec95fa4fa0063"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB14K_PCC_DATA8</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 14)</td></tr>
|
||
|
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<tr class="separator:aa3964b500a9f109a46fec95fa4fa0063"><td class="memSeparator" colspan="2"> </td></tr>
|
||
|
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<tr class="memitem:a4d7e10c6674b55cdd8411414052b25ea"><td class="memItemLeft" align="right" valign="top"><a id="a4d7e10c6674b55cdd8411414052b25ea"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4d7e10c6674b55cdd8411414052b25ea">PIN_PB15K_PCC_DATA9</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(47)</td></tr>
|
||
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<tr class="memdesc:a4d7e10c6674b55cdd8411414052b25ea"><td class="mdescLeft"> </td><td class="mdescRight">PCC signal: DATA9 on PB15 mux K. <br /></td></tr>
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<tr class="memitem:a95b2baf04d0617acedf6372a9cf221f3"><td class="memItemLeft" align="right" valign="top"><a id="a95b2baf04d0617acedf6372a9cf221f3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB15K_PCC_DATA9</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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<tr class="separator:a95b2baf04d0617acedf6372a9cf221f3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4147505707f3d369b7c4a107e26fb512"><td class="memItemLeft" align="right" valign="top"><a id="a4147505707f3d369b7c4a107e26fb512"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB15K_PCC_DATA9</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a4d7e10c6674b55cdd8411414052b25ea">PIN_PB15K_PCC_DATA9</a> << 16) | MUX_PB15K_PCC_DATA9)</td></tr>
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<tr class="separator:a4147505707f3d369b7c4a107e26fb512"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a57ff2f5276ddf91f90e154245361b0aa"><td class="memItemLeft" align="right" valign="top"><a id="a57ff2f5276ddf91f90e154245361b0aa"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB15K_PCC_DATA9</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 15)</td></tr>
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<tr class="separator:a57ff2f5276ddf91f90e154245361b0aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aec4f0401174d813adcab3dda8ef685c1"><td class="memItemLeft" align="right" valign="top"><a id="aec4f0401174d813adcab3dda8ef685c1"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aec4f0401174d813adcab3dda8ef685c1">PIN_PC12K_PCC_DATA10</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(76)</td></tr>
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<tr class="memdesc:aec4f0401174d813adcab3dda8ef685c1"><td class="mdescLeft"> </td><td class="mdescRight">PCC signal: DATA10 on PC12 mux K. <br /></td></tr>
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<tr class="separator:aec4f0401174d813adcab3dda8ef685c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acb400aca398c2afb05ef368ca8d653e2"><td class="memItemLeft" align="right" valign="top"><a id="acb400aca398c2afb05ef368ca8d653e2"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC12K_PCC_DATA10</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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<tr class="separator:acb400aca398c2afb05ef368ca8d653e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af3f6727ee621c808edad5c650f13ceae"><td class="memItemLeft" align="right" valign="top"><a id="af3f6727ee621c808edad5c650f13ceae"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC12K_PCC_DATA10</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aec4f0401174d813adcab3dda8ef685c1">PIN_PC12K_PCC_DATA10</a> << 16) | MUX_PC12K_PCC_DATA10)</td></tr>
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<tr class="separator:af3f6727ee621c808edad5c650f13ceae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8903982f12a478f91530cea520688b80"><td class="memItemLeft" align="right" valign="top"><a id="a8903982f12a478f91530cea520688b80"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC12K_PCC_DATA10</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 12)</td></tr>
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<tr class="separator:a8903982f12a478f91530cea520688b80"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2f6caf0b091dbd3fd30382de37a358db"><td class="memItemLeft" align="right" valign="top"><a id="a2f6caf0b091dbd3fd30382de37a358db"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2f6caf0b091dbd3fd30382de37a358db">PIN_PC13K_PCC_DATA11</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(77)</td></tr>
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<tr class="memdesc:a2f6caf0b091dbd3fd30382de37a358db"><td class="mdescLeft"> </td><td class="mdescRight">PCC signal: DATA11 on PC13 mux K. <br /></td></tr>
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<tr class="separator:a2f6caf0b091dbd3fd30382de37a358db"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a22c1de69db9844686745ddb441f7d522"><td class="memItemLeft" align="right" valign="top"><a id="a22c1de69db9844686745ddb441f7d522"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC13K_PCC_DATA11</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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<tr class="separator:a22c1de69db9844686745ddb441f7d522"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a23c654ce1571208819fd0df2abb32abc"><td class="memItemLeft" align="right" valign="top"><a id="a23c654ce1571208819fd0df2abb32abc"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC13K_PCC_DATA11</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a2f6caf0b091dbd3fd30382de37a358db">PIN_PC13K_PCC_DATA11</a> << 16) | MUX_PC13K_PCC_DATA11)</td></tr>
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<tr class="separator:a23c654ce1571208819fd0df2abb32abc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae81cf2399b5e1f775ab7dbb5ab63875e"><td class="memItemLeft" align="right" valign="top"><a id="ae81cf2399b5e1f775ab7dbb5ab63875e"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC13K_PCC_DATA11</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 13)</td></tr>
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||
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<tr class="separator:ae81cf2399b5e1f775ab7dbb5ab63875e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af1a1cbcbc27cf4cc19ab9270be0166b6"><td class="memItemLeft" align="right" valign="top"><a id="af1a1cbcbc27cf4cc19ab9270be0166b6"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af1a1cbcbc27cf4cc19ab9270be0166b6">PIN_PC14K_PCC_DATA12</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(78)</td></tr>
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||
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<tr class="memdesc:af1a1cbcbc27cf4cc19ab9270be0166b6"><td class="mdescLeft"> </td><td class="mdescRight">PCC signal: DATA12 on PC14 mux K. <br /></td></tr>
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<tr class="separator:af1a1cbcbc27cf4cc19ab9270be0166b6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1273b53a9929e67ce3e799fd058728d7"><td class="memItemLeft" align="right" valign="top"><a id="a1273b53a9929e67ce3e799fd058728d7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC14K_PCC_DATA12</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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<tr class="separator:a1273b53a9929e67ce3e799fd058728d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a09021cc6602e1bd8da05bd4c364371ec"><td class="memItemLeft" align="right" valign="top"><a id="a09021cc6602e1bd8da05bd4c364371ec"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC14K_PCC_DATA12</b>   ((<a class="el" href="pio_2same54p20a_8h.html#af1a1cbcbc27cf4cc19ab9270be0166b6">PIN_PC14K_PCC_DATA12</a> << 16) | MUX_PC14K_PCC_DATA12)</td></tr>
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<tr class="separator:a09021cc6602e1bd8da05bd4c364371ec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4dba7853c189eda51953980d47782dbd"><td class="memItemLeft" align="right" valign="top"><a id="a4dba7853c189eda51953980d47782dbd"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC14K_PCC_DATA12</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 14)</td></tr>
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||
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<tr class="separator:a4dba7853c189eda51953980d47782dbd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a82788e2bb85284b088010dc69d7974fd"><td class="memItemLeft" align="right" valign="top"><a id="a82788e2bb85284b088010dc69d7974fd"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a82788e2bb85284b088010dc69d7974fd">PIN_PC15K_PCC_DATA13</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(79)</td></tr>
|
||
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<tr class="memdesc:a82788e2bb85284b088010dc69d7974fd"><td class="mdescLeft"> </td><td class="mdescRight">PCC signal: DATA13 on PC15 mux K. <br /></td></tr>
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<tr class="separator:a82788e2bb85284b088010dc69d7974fd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a88d616b21019ee48c9f70e53ac1105a7"><td class="memItemLeft" align="right" valign="top"><a id="a88d616b21019ee48c9f70e53ac1105a7"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC15K_PCC_DATA13</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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<tr class="separator:a88d616b21019ee48c9f70e53ac1105a7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afbbb77ab63c00df2723ee258b0149dda"><td class="memItemLeft" align="right" valign="top"><a id="afbbb77ab63c00df2723ee258b0149dda"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC15K_PCC_DATA13</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a82788e2bb85284b088010dc69d7974fd">PIN_PC15K_PCC_DATA13</a> << 16) | MUX_PC15K_PCC_DATA13)</td></tr>
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<tr class="separator:afbbb77ab63c00df2723ee258b0149dda"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6552b1dab6f62d557007fd3758c53b5f"><td class="memItemLeft" align="right" valign="top"><a id="a6552b1dab6f62d557007fd3758c53b5f"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC15K_PCC_DATA13</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 15)</td></tr>
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||
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<tr class="separator:a6552b1dab6f62d557007fd3758c53b5f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a95f4299c5d7e1752b1d3f64a2ddd8431"><td class="memItemLeft" align="right" valign="top"><a id="a95f4299c5d7e1752b1d3f64a2ddd8431"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a95f4299c5d7e1752b1d3f64a2ddd8431">PIN_PA12K_PCC_DEN1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
|
||
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<tr class="memdesc:a95f4299c5d7e1752b1d3f64a2ddd8431"><td class="mdescLeft"> </td><td class="mdescRight">PCC signal: DEN1 on PA12 mux K. <br /></td></tr>
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<tr class="separator:a95f4299c5d7e1752b1d3f64a2ddd8431"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa8ba31e6e5386b162d0eaf6606e95e58"><td class="memItemLeft" align="right" valign="top"><a id="aa8ba31e6e5386b162d0eaf6606e95e58"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA12K_PCC_DEN1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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<tr class="separator:aa8ba31e6e5386b162d0eaf6606e95e58"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5925c456f274be7d28ea1ecf4683cbce"><td class="memItemLeft" align="right" valign="top"><a id="a5925c456f274be7d28ea1ecf4683cbce"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA12K_PCC_DEN1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a95f4299c5d7e1752b1d3f64a2ddd8431">PIN_PA12K_PCC_DEN1</a> << 16) | MUX_PA12K_PCC_DEN1)</td></tr>
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<tr class="separator:a5925c456f274be7d28ea1ecf4683cbce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a83d8e92a66d4ea8db473230078687048"><td class="memItemLeft" align="right" valign="top"><a id="a83d8e92a66d4ea8db473230078687048"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA12K_PCC_DEN1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 12)</td></tr>
|
||
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<tr class="separator:a83d8e92a66d4ea8db473230078687048"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad65fb1b287ea3b11963e946d4e014984"><td class="memItemLeft" align="right" valign="top"><a id="ad65fb1b287ea3b11963e946d4e014984"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad65fb1b287ea3b11963e946d4e014984">PIN_PA13K_PCC_DEN2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
|
||
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<tr class="memdesc:ad65fb1b287ea3b11963e946d4e014984"><td class="mdescLeft"> </td><td class="mdescRight">PCC signal: DEN2 on PA13 mux K. <br /></td></tr>
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||
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<tr class="separator:ad65fb1b287ea3b11963e946d4e014984"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a38c67ff483edf7d4a1a79d3973ac5497"><td class="memItemLeft" align="right" valign="top"><a id="a38c67ff483edf7d4a1a79d3973ac5497"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA13K_PCC_DEN2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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||
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<tr class="separator:a38c67ff483edf7d4a1a79d3973ac5497"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a67896af2fb1a8c36b4b402fe006feda1"><td class="memItemLeft" align="right" valign="top"><a id="a67896af2fb1a8c36b4b402fe006feda1"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA13K_PCC_DEN2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ad65fb1b287ea3b11963e946d4e014984">PIN_PA13K_PCC_DEN2</a> << 16) | MUX_PA13K_PCC_DEN2)</td></tr>
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<tr class="separator:a67896af2fb1a8c36b4b402fe006feda1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a610a855d8cfff6f377399b2590de7d40"><td class="memItemLeft" align="right" valign="top"><a id="a610a855d8cfff6f377399b2590de7d40"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA13K_PCC_DEN2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 13)</td></tr>
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||
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<tr class="separator:a610a855d8cfff6f377399b2590de7d40"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a7eba67b3fa722743acdea76e2ef27d7a"><td class="memItemLeft" align="right" valign="top"><a id="a7eba67b3fa722743acdea76e2ef27d7a"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a7eba67b3fa722743acdea76e2ef27d7a">PIN_PA06I_SDHC0_SDCD</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(6)</td></tr>
|
||
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<tr class="memdesc:a7eba67b3fa722743acdea76e2ef27d7a"><td class="mdescLeft"> </td><td class="mdescRight">SDHC0 signal: SDCD on PA06 mux I. <br /></td></tr>
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||
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<tr class="separator:a7eba67b3fa722743acdea76e2ef27d7a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8e0c9f1bd7bf65dc4613c078711e70b6"><td class="memItemLeft" align="right" valign="top"><a id="a8e0c9f1bd7bf65dc4613c078711e70b6"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA06I_SDHC0_SDCD</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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||
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<tr class="separator:a8e0c9f1bd7bf65dc4613c078711e70b6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afdfb7f84d383d8f175645a99d77223b7"><td class="memItemLeft" align="right" valign="top"><a id="afdfb7f84d383d8f175645a99d77223b7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA06I_SDHC0_SDCD</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a7eba67b3fa722743acdea76e2ef27d7a">PIN_PA06I_SDHC0_SDCD</a> << 16) | MUX_PA06I_SDHC0_SDCD)</td></tr>
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<tr class="memitem:a7c9d37a04bf55130a1ea241f1a1f9f1b"><td class="memItemLeft" align="right" valign="top"><a id="a7c9d37a04bf55130a1ea241f1a1f9f1b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA06I_SDHC0_SDCD</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 6)</td></tr>
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<tr class="memitem:a1652b1b085a562bc8917a81143f0c524"><td class="memItemLeft" align="right" valign="top"><a id="a1652b1b085a562bc8917a81143f0c524"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1652b1b085a562bc8917a81143f0c524">PIN_PA12I_SDHC0_SDCD</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(12)</td></tr>
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<tr class="memdesc:a1652b1b085a562bc8917a81143f0c524"><td class="mdescLeft"> </td><td class="mdescRight">SDHC0 signal: SDCD on PA12 mux I. <br /></td></tr>
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<tr class="memitem:aff2a3321eb387116b7c347da8e122aff"><td class="memItemLeft" align="right" valign="top"><a id="aff2a3321eb387116b7c347da8e122aff"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA12I_SDHC0_SDCD</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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<tr class="memitem:aef7e37386682a3a4f3e474bc9916d28e"><td class="memItemLeft" align="right" valign="top"><a id="aef7e37386682a3a4f3e474bc9916d28e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA12I_SDHC0_SDCD</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a1652b1b085a562bc8917a81143f0c524">PIN_PA12I_SDHC0_SDCD</a> << 16) | MUX_PA12I_SDHC0_SDCD)</td></tr>
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<tr class="memitem:ac42aed4f620ecc3b775e7b7605ac4cb8"><td class="memItemLeft" align="right" valign="top"><a id="ac42aed4f620ecc3b775e7b7605ac4cb8"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA12I_SDHC0_SDCD</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 12)</td></tr>
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<tr class="separator:ac42aed4f620ecc3b775e7b7605ac4cb8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6334c9da7c0ecbe7010cd8ed67000f0a"><td class="memItemLeft" align="right" valign="top"><a id="a6334c9da7c0ecbe7010cd8ed67000f0a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6334c9da7c0ecbe7010cd8ed67000f0a">PIN_PB12I_SDHC0_SDCD</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(44)</td></tr>
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<tr class="memdesc:a6334c9da7c0ecbe7010cd8ed67000f0a"><td class="mdescLeft"> </td><td class="mdescRight">SDHC0 signal: SDCD on PB12 mux I. <br /></td></tr>
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<tr class="memitem:ac16dc69a55e7cd6f4e610deaa90ed2f6"><td class="memItemLeft" align="right" valign="top"><a id="ac16dc69a55e7cd6f4e610deaa90ed2f6"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB12I_SDHC0_SDCD</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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<tr class="separator:ac16dc69a55e7cd6f4e610deaa90ed2f6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adbb28571cbc11915651a08b8df0ae05f"><td class="memItemLeft" align="right" valign="top"><a id="adbb28571cbc11915651a08b8df0ae05f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB12I_SDHC0_SDCD</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a6334c9da7c0ecbe7010cd8ed67000f0a">PIN_PB12I_SDHC0_SDCD</a> << 16) | MUX_PB12I_SDHC0_SDCD)</td></tr>
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<tr class="memitem:a6dd1384fbecf5744b227cbccc5615586"><td class="memItemLeft" align="right" valign="top"><a id="a6dd1384fbecf5744b227cbccc5615586"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB12I_SDHC0_SDCD</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 12)</td></tr>
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<tr class="separator:a6dd1384fbecf5744b227cbccc5615586"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:accbfc26f95777ee4c8ea1dc6d97ef61a"><td class="memItemLeft" align="right" valign="top"><a id="accbfc26f95777ee4c8ea1dc6d97ef61a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#accbfc26f95777ee4c8ea1dc6d97ef61a">PIN_PC06I_SDHC0_SDCD</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(70)</td></tr>
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<tr class="memdesc:accbfc26f95777ee4c8ea1dc6d97ef61a"><td class="mdescLeft"> </td><td class="mdescRight">SDHC0 signal: SDCD on PC06 mux I. <br /></td></tr>
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<tr class="separator:accbfc26f95777ee4c8ea1dc6d97ef61a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a36c5bae4f4769d3eb8f41bc2e30d1470"><td class="memItemLeft" align="right" valign="top"><a id="a36c5bae4f4769d3eb8f41bc2e30d1470"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC06I_SDHC0_SDCD</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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<tr class="separator:a36c5bae4f4769d3eb8f41bc2e30d1470"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3dcb8a23114aa3cafd8e860d73018722"><td class="memItemLeft" align="right" valign="top"><a id="a3dcb8a23114aa3cafd8e860d73018722"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC06I_SDHC0_SDCD</b>   ((<a class="el" href="pio_2same54p20a_8h.html#accbfc26f95777ee4c8ea1dc6d97ef61a">PIN_PC06I_SDHC0_SDCD</a> << 16) | MUX_PC06I_SDHC0_SDCD)</td></tr>
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<tr class="separator:a3dcb8a23114aa3cafd8e860d73018722"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abfe985ccf79f1d13dad12eb080dc5649"><td class="memItemLeft" align="right" valign="top"><a id="abfe985ccf79f1d13dad12eb080dc5649"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC06I_SDHC0_SDCD</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 6)</td></tr>
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<tr class="separator:abfe985ccf79f1d13dad12eb080dc5649"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2e1cf132f6526c8da6bf172b8c04accb"><td class="memItemLeft" align="right" valign="top"><a id="a2e1cf132f6526c8da6bf172b8c04accb"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2e1cf132f6526c8da6bf172b8c04accb">PIN_PB11I_SDHC0_SDCK</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(43)</td></tr>
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<tr class="memdesc:a2e1cf132f6526c8da6bf172b8c04accb"><td class="mdescLeft"> </td><td class="mdescRight">SDHC0 signal: SDCK on PB11 mux I. <br /></td></tr>
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<tr class="separator:a2e1cf132f6526c8da6bf172b8c04accb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af3a0a68ee6a1b6c891d81609803f5300"><td class="memItemLeft" align="right" valign="top"><a id="af3a0a68ee6a1b6c891d81609803f5300"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB11I_SDHC0_SDCK</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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<tr class="separator:af3a0a68ee6a1b6c891d81609803f5300"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6bbbedbdf131be3400bdc671ca78489b"><td class="memItemLeft" align="right" valign="top"><a id="a6bbbedbdf131be3400bdc671ca78489b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB11I_SDHC0_SDCK</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a2e1cf132f6526c8da6bf172b8c04accb">PIN_PB11I_SDHC0_SDCK</a> << 16) | MUX_PB11I_SDHC0_SDCK)</td></tr>
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<tr class="memitem:a32654b2764e0a5b196ca8b7c8b8d1992"><td class="memItemLeft" align="right" valign="top"><a id="a32654b2764e0a5b196ca8b7c8b8d1992"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB11I_SDHC0_SDCK</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 11)</td></tr>
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<tr class="separator:a32654b2764e0a5b196ca8b7c8b8d1992"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5ce89ff16c8a387ed61286c08b560d2a"><td class="memItemLeft" align="right" valign="top"><a id="a5ce89ff16c8a387ed61286c08b560d2a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a5ce89ff16c8a387ed61286c08b560d2a">PIN_PA08I_SDHC0_SDCMD</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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<tr class="memdesc:a5ce89ff16c8a387ed61286c08b560d2a"><td class="mdescLeft"> </td><td class="mdescRight">SDHC0 signal: SDCMD on PA08 mux I. <br /></td></tr>
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<tr class="separator:a5ce89ff16c8a387ed61286c08b560d2a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa0c40fdf6eb5193cb0cef7fd66480dc2"><td class="memItemLeft" align="right" valign="top"><a id="aa0c40fdf6eb5193cb0cef7fd66480dc2"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA08I_SDHC0_SDCMD</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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<tr class="separator:aa0c40fdf6eb5193cb0cef7fd66480dc2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aeadf8c5343d606dd1ebaac603d7b92b7"><td class="memItemLeft" align="right" valign="top"><a id="aeadf8c5343d606dd1ebaac603d7b92b7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA08I_SDHC0_SDCMD</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a5ce89ff16c8a387ed61286c08b560d2a">PIN_PA08I_SDHC0_SDCMD</a> << 16) | MUX_PA08I_SDHC0_SDCMD)</td></tr>
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<tr class="separator:aeadf8c5343d606dd1ebaac603d7b92b7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab4d20e667a3fd6a071fdcf7ccb396e2e"><td class="memItemLeft" align="right" valign="top"><a id="ab4d20e667a3fd6a071fdcf7ccb396e2e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA08I_SDHC0_SDCMD</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 8)</td></tr>
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<tr class="separator:ab4d20e667a3fd6a071fdcf7ccb396e2e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a94b8bf2870b540c7230c5cbb19d57802"><td class="memItemLeft" align="right" valign="top"><a id="a94b8bf2870b540c7230c5cbb19d57802"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a94b8bf2870b540c7230c5cbb19d57802">PIN_PA09I_SDHC0_SDDAT0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(9)</td></tr>
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||
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<tr class="memdesc:a94b8bf2870b540c7230c5cbb19d57802"><td class="mdescLeft"> </td><td class="mdescRight">SDHC0 signal: SDDAT0 on PA09 mux I. <br /></td></tr>
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<tr class="separator:a94b8bf2870b540c7230c5cbb19d57802"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad1bd2254d1ac05a912064761aaa3bff3"><td class="memItemLeft" align="right" valign="top"><a id="ad1bd2254d1ac05a912064761aaa3bff3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA09I_SDHC0_SDDAT0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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<tr class="separator:ad1bd2254d1ac05a912064761aaa3bff3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab79d1a8e061a8f58a9405ad024d20664"><td class="memItemLeft" align="right" valign="top"><a id="ab79d1a8e061a8f58a9405ad024d20664"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA09I_SDHC0_SDDAT0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a94b8bf2870b540c7230c5cbb19d57802">PIN_PA09I_SDHC0_SDDAT0</a> << 16) | MUX_PA09I_SDHC0_SDDAT0)</td></tr>
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<tr class="separator:ab79d1a8e061a8f58a9405ad024d20664"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5e1cf00bdb6c98761053f388713ee2a6"><td class="memItemLeft" align="right" valign="top"><a id="a5e1cf00bdb6c98761053f388713ee2a6"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA09I_SDHC0_SDDAT0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 9)</td></tr>
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<tr class="separator:a5e1cf00bdb6c98761053f388713ee2a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae8ab21367573b32ffbb51adc89e5214c"><td class="memItemLeft" align="right" valign="top"><a id="ae8ab21367573b32ffbb51adc89e5214c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae8ab21367573b32ffbb51adc89e5214c">PIN_PA10I_SDHC0_SDDAT1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(10)</td></tr>
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||
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<tr class="memdesc:ae8ab21367573b32ffbb51adc89e5214c"><td class="mdescLeft"> </td><td class="mdescRight">SDHC0 signal: SDDAT1 on PA10 mux I. <br /></td></tr>
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<tr class="separator:ae8ab21367573b32ffbb51adc89e5214c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a05f0ad66845c1a4a11c5f27d7d9f7635"><td class="memItemLeft" align="right" valign="top"><a id="a05f0ad66845c1a4a11c5f27d7d9f7635"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA10I_SDHC0_SDDAT1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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||
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<tr class="separator:a05f0ad66845c1a4a11c5f27d7d9f7635"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af4602f85d792010cea8a02f194e05ec1"><td class="memItemLeft" align="right" valign="top"><a id="af4602f85d792010cea8a02f194e05ec1"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA10I_SDHC0_SDDAT1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ae8ab21367573b32ffbb51adc89e5214c">PIN_PA10I_SDHC0_SDDAT1</a> << 16) | MUX_PA10I_SDHC0_SDDAT1)</td></tr>
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<tr class="memitem:ab7f33a75ea249d60ea6e66914569c1f9"><td class="memItemLeft" align="right" valign="top"><a id="ab7f33a75ea249d60ea6e66914569c1f9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA10I_SDHC0_SDDAT1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 10)</td></tr>
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<tr class="separator:ab7f33a75ea249d60ea6e66914569c1f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac33e3a21859731b4f762debccf27eb3b"><td class="memItemLeft" align="right" valign="top"><a id="ac33e3a21859731b4f762debccf27eb3b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ac33e3a21859731b4f762debccf27eb3b">PIN_PA11I_SDHC0_SDDAT2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(11)</td></tr>
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<tr class="memdesc:ac33e3a21859731b4f762debccf27eb3b"><td class="mdescLeft"> </td><td class="mdescRight">SDHC0 signal: SDDAT2 on PA11 mux I. <br /></td></tr>
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<tr class="separator:ac33e3a21859731b4f762debccf27eb3b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a572bc7e162ad3c0d5417541392f52ba2"><td class="memItemLeft" align="right" valign="top"><a id="a572bc7e162ad3c0d5417541392f52ba2"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA11I_SDHC0_SDDAT2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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<tr class="separator:a572bc7e162ad3c0d5417541392f52ba2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a19774ef3da1e38f03881fa35e181404b"><td class="memItemLeft" align="right" valign="top"><a id="a19774ef3da1e38f03881fa35e181404b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA11I_SDHC0_SDDAT2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ac33e3a21859731b4f762debccf27eb3b">PIN_PA11I_SDHC0_SDDAT2</a> << 16) | MUX_PA11I_SDHC0_SDDAT2)</td></tr>
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<tr class="separator:a19774ef3da1e38f03881fa35e181404b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aab245554b3581f40f0e85de986b83ace"><td class="memItemLeft" align="right" valign="top"><a id="aab245554b3581f40f0e85de986b83ace"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA11I_SDHC0_SDDAT2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 11)</td></tr>
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<tr class="separator:aab245554b3581f40f0e85de986b83ace"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8b7b4025892d03890865b8f66bfc1ed6"><td class="memItemLeft" align="right" valign="top"><a id="a8b7b4025892d03890865b8f66bfc1ed6"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8b7b4025892d03890865b8f66bfc1ed6">PIN_PB10I_SDHC0_SDDAT3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(42)</td></tr>
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||
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<tr class="memdesc:a8b7b4025892d03890865b8f66bfc1ed6"><td class="mdescLeft"> </td><td class="mdescRight">SDHC0 signal: SDDAT3 on PB10 mux I. <br /></td></tr>
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<tr class="separator:a8b7b4025892d03890865b8f66bfc1ed6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a40328e7da3f76b7c4e4026692cd6bbd5"><td class="memItemLeft" align="right" valign="top"><a id="a40328e7da3f76b7c4e4026692cd6bbd5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB10I_SDHC0_SDDAT3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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<tr class="separator:a40328e7da3f76b7c4e4026692cd6bbd5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acb62b72067e7f1a13da611bd5bfa7ad1"><td class="memItemLeft" align="right" valign="top"><a id="acb62b72067e7f1a13da611bd5bfa7ad1"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB10I_SDHC0_SDDAT3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a8b7b4025892d03890865b8f66bfc1ed6">PIN_PB10I_SDHC0_SDDAT3</a> << 16) | MUX_PB10I_SDHC0_SDDAT3)</td></tr>
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<tr class="separator:acb62b72067e7f1a13da611bd5bfa7ad1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9b4951c06626e2d3af18572274299eb8"><td class="memItemLeft" align="right" valign="top"><a id="a9b4951c06626e2d3af18572274299eb8"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB10I_SDHC0_SDDAT3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 10)</td></tr>
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<tr class="separator:a9b4951c06626e2d3af18572274299eb8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4c18ee0a78cc6c00542cd0bcb85c55c0"><td class="memItemLeft" align="right" valign="top"><a id="a4c18ee0a78cc6c00542cd0bcb85c55c0"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a4c18ee0a78cc6c00542cd0bcb85c55c0">PIN_PA07I_SDHC0_SDWP</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(7)</td></tr>
|
||
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<tr class="memdesc:a4c18ee0a78cc6c00542cd0bcb85c55c0"><td class="mdescLeft"> </td><td class="mdescRight">SDHC0 signal: SDWP on PA07 mux I. <br /></td></tr>
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<tr class="separator:a4c18ee0a78cc6c00542cd0bcb85c55c0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abec1d2f7a6223f2b7793173b663639ad"><td class="memItemLeft" align="right" valign="top"><a id="abec1d2f7a6223f2b7793173b663639ad"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA07I_SDHC0_SDWP</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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||
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<tr class="separator:abec1d2f7a6223f2b7793173b663639ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aaf2f051a9cbcc388f19da89123cc980e"><td class="memItemLeft" align="right" valign="top"><a id="aaf2f051a9cbcc388f19da89123cc980e"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA07I_SDHC0_SDWP</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a4c18ee0a78cc6c00542cd0bcb85c55c0">PIN_PA07I_SDHC0_SDWP</a> << 16) | MUX_PA07I_SDHC0_SDWP)</td></tr>
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<tr class="separator:aaf2f051a9cbcc388f19da89123cc980e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac809b65d182e87d442db44cefd7a6ade"><td class="memItemLeft" align="right" valign="top"><a id="ac809b65d182e87d442db44cefd7a6ade"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA07I_SDHC0_SDWP</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 7)</td></tr>
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||
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<tr class="separator:ac809b65d182e87d442db44cefd7a6ade"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aeb8b6ff5f0910a82ee11942744761bb1"><td class="memItemLeft" align="right" valign="top"><a id="aeb8b6ff5f0910a82ee11942744761bb1"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aeb8b6ff5f0910a82ee11942744761bb1">PIN_PA13I_SDHC0_SDWP</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(13)</td></tr>
|
||
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<tr class="memdesc:aeb8b6ff5f0910a82ee11942744761bb1"><td class="mdescLeft"> </td><td class="mdescRight">SDHC0 signal: SDWP on PA13 mux I. <br /></td></tr>
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||
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<tr class="separator:aeb8b6ff5f0910a82ee11942744761bb1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8b202ab61610034dd1e4a09382e89288"><td class="memItemLeft" align="right" valign="top"><a id="a8b202ab61610034dd1e4a09382e89288"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA13I_SDHC0_SDWP</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
|
||
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<tr class="separator:a8b202ab61610034dd1e4a09382e89288"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae1f55fdbbefa64e524c9ba344ca45696"><td class="memItemLeft" align="right" valign="top"><a id="ae1f55fdbbefa64e524c9ba344ca45696"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA13I_SDHC0_SDWP</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aeb8b6ff5f0910a82ee11942744761bb1">PIN_PA13I_SDHC0_SDWP</a> << 16) | MUX_PA13I_SDHC0_SDWP)</td></tr>
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<tr class="separator:ae1f55fdbbefa64e524c9ba344ca45696"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a762d8fda41c07604b90769c53478f9c3"><td class="memItemLeft" align="right" valign="top"><a id="a762d8fda41c07604b90769c53478f9c3"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA13I_SDHC0_SDWP</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 13)</td></tr>
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||
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<tr class="separator:a762d8fda41c07604b90769c53478f9c3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae23c3fa2b7ace661c286468f5be6a168"><td class="memItemLeft" align="right" valign="top"><a id="ae23c3fa2b7ace661c286468f5be6a168"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ae23c3fa2b7ace661c286468f5be6a168">PIN_PB13I_SDHC0_SDWP</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(45)</td></tr>
|
||
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<tr class="memdesc:ae23c3fa2b7ace661c286468f5be6a168"><td class="mdescLeft"> </td><td class="mdescRight">SDHC0 signal: SDWP on PB13 mux I. <br /></td></tr>
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<tr class="separator:ae23c3fa2b7ace661c286468f5be6a168"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0884bd15e3e1e34882079e6e1e31aa31"><td class="memItemLeft" align="right" valign="top"><a id="a0884bd15e3e1e34882079e6e1e31aa31"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB13I_SDHC0_SDWP</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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||
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<tr class="separator:a0884bd15e3e1e34882079e6e1e31aa31"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a648d6f01d98be024d07115ad87e4fedc"><td class="memItemLeft" align="right" valign="top"><a id="a648d6f01d98be024d07115ad87e4fedc"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB13I_SDHC0_SDWP</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ae23c3fa2b7ace661c286468f5be6a168">PIN_PB13I_SDHC0_SDWP</a> << 16) | MUX_PB13I_SDHC0_SDWP)</td></tr>
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<tr class="separator:a648d6f01d98be024d07115ad87e4fedc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2d22e364910d969c840c67bb5136abac"><td class="memItemLeft" align="right" valign="top"><a id="a2d22e364910d969c840c67bb5136abac"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB13I_SDHC0_SDWP</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 13)</td></tr>
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||
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<tr class="separator:a2d22e364910d969c840c67bb5136abac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a25ca4efebdef34b3f4b89f9856d7fcdf"><td class="memItemLeft" align="right" valign="top"><a id="a25ca4efebdef34b3f4b89f9856d7fcdf"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a25ca4efebdef34b3f4b89f9856d7fcdf">PIN_PC07I_SDHC0_SDWP</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(71)</td></tr>
|
||
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<tr class="memdesc:a25ca4efebdef34b3f4b89f9856d7fcdf"><td class="mdescLeft"> </td><td class="mdescRight">SDHC0 signal: SDWP on PC07 mux I. <br /></td></tr>
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<tr class="separator:a25ca4efebdef34b3f4b89f9856d7fcdf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab84ec35ec056cd23f0cae6fe4d6b0e80"><td class="memItemLeft" align="right" valign="top"><a id="ab84ec35ec056cd23f0cae6fe4d6b0e80"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC07I_SDHC0_SDWP</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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||
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<tr class="separator:ab84ec35ec056cd23f0cae6fe4d6b0e80"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a4f28624331e0b90bb55556df42c6db63"><td class="memItemLeft" align="right" valign="top"><a id="a4f28624331e0b90bb55556df42c6db63"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC07I_SDHC0_SDWP</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a25ca4efebdef34b3f4b89f9856d7fcdf">PIN_PC07I_SDHC0_SDWP</a> << 16) | MUX_PC07I_SDHC0_SDWP)</td></tr>
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<tr class="separator:a4f28624331e0b90bb55556df42c6db63"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3f1b2d93ae3a6d58f44221d70dfa7279"><td class="memItemLeft" align="right" valign="top"><a id="a3f1b2d93ae3a6d58f44221d70dfa7279"></a>
|
||
|
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC07I_SDHC0_SDWP</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 7)</td></tr>
|
||
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<tr class="separator:a3f1b2d93ae3a6d58f44221d70dfa7279"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:af7f8904dab20bffa1f795c139f278090"><td class="memItemLeft" align="right" valign="top"><a id="af7f8904dab20bffa1f795c139f278090"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#af7f8904dab20bffa1f795c139f278090">PIN_PB16I_SDHC1_SDCD</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(48)</td></tr>
|
||
|
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<tr class="memdesc:af7f8904dab20bffa1f795c139f278090"><td class="mdescLeft"> </td><td class="mdescRight">SDHC1 signal: SDCD on PB16 mux I. <br /></td></tr>
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||
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<tr class="separator:af7f8904dab20bffa1f795c139f278090"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:a4afc66e7b1776ef37712061f90cc45a4"><td class="memItemLeft" align="right" valign="top"><a id="a4afc66e7b1776ef37712061f90cc45a4"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB16I_SDHC1_SDCD</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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||
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<tr class="separator:a4afc66e7b1776ef37712061f90cc45a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aae803511103917e1e03d04bc51aa70b0"><td class="memItemLeft" align="right" valign="top"><a id="aae803511103917e1e03d04bc51aa70b0"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB16I_SDHC1_SDCD</b>   ((<a class="el" href="pio_2same54p20a_8h.html#af7f8904dab20bffa1f795c139f278090">PIN_PB16I_SDHC1_SDCD</a> << 16) | MUX_PB16I_SDHC1_SDCD)</td></tr>
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<tr class="separator:aae803511103917e1e03d04bc51aa70b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aedb93a0611bc6420f637f706d494a4cc"><td class="memItemLeft" align="right" valign="top"><a id="aedb93a0611bc6420f637f706d494a4cc"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB16I_SDHC1_SDCD</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 16)</td></tr>
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<tr class="memitem:a8460a60ab02c33b04a2860ac8c23c8eb"><td class="memItemLeft" align="right" valign="top"><a id="a8460a60ab02c33b04a2860ac8c23c8eb"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a8460a60ab02c33b04a2860ac8c23c8eb">PIN_PC20I_SDHC1_SDCD</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(84)</td></tr>
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||
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<tr class="memdesc:a8460a60ab02c33b04a2860ac8c23c8eb"><td class="mdescLeft"> </td><td class="mdescRight">SDHC1 signal: SDCD on PC20 mux I. <br /></td></tr>
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<tr class="separator:a8460a60ab02c33b04a2860ac8c23c8eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aebcae9d7c0fc6f0f9b6a9aa910d37451"><td class="memItemLeft" align="right" valign="top"><a id="aebcae9d7c0fc6f0f9b6a9aa910d37451"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC20I_SDHC1_SDCD</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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<tr class="separator:aebcae9d7c0fc6f0f9b6a9aa910d37451"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a36009d5e65915e0e7712f1e172ae50ff"><td class="memItemLeft" align="right" valign="top"><a id="a36009d5e65915e0e7712f1e172ae50ff"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC20I_SDHC1_SDCD</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a8460a60ab02c33b04a2860ac8c23c8eb">PIN_PC20I_SDHC1_SDCD</a> << 16) | MUX_PC20I_SDHC1_SDCD)</td></tr>
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<tr class="separator:a36009d5e65915e0e7712f1e172ae50ff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae1977456368e48ea59ab0550dd65d078"><td class="memItemLeft" align="right" valign="top"><a id="ae1977456368e48ea59ab0550dd65d078"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC20I_SDHC1_SDCD</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 20)</td></tr>
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<tr class="separator:ae1977456368e48ea59ab0550dd65d078"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a70332e65e672013ce468ce28f4630f13"><td class="memItemLeft" align="right" valign="top"><a id="a70332e65e672013ce468ce28f4630f13"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a70332e65e672013ce468ce28f4630f13">PIN_PA21I_SDHC1_SDCK</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(21)</td></tr>
|
||
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<tr class="memdesc:a70332e65e672013ce468ce28f4630f13"><td class="mdescLeft"> </td><td class="mdescRight">SDHC1 signal: SDCK on PA21 mux I. <br /></td></tr>
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<tr class="separator:a70332e65e672013ce468ce28f4630f13"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a19bc1f553d3d1619e4064b6b90c52700"><td class="memItemLeft" align="right" valign="top"><a id="a19bc1f553d3d1619e4064b6b90c52700"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA21I_SDHC1_SDCK</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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<tr class="separator:a19bc1f553d3d1619e4064b6b90c52700"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a39588033af1138774fd010cc7c7d22e2"><td class="memItemLeft" align="right" valign="top"><a id="a39588033af1138774fd010cc7c7d22e2"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA21I_SDHC1_SDCK</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a70332e65e672013ce468ce28f4630f13">PIN_PA21I_SDHC1_SDCK</a> << 16) | MUX_PA21I_SDHC1_SDCK)</td></tr>
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<tr class="separator:a39588033af1138774fd010cc7c7d22e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9ba940d336ed93498df4880f1e8710d9"><td class="memItemLeft" align="right" valign="top"><a id="a9ba940d336ed93498df4880f1e8710d9"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA21I_SDHC1_SDCK</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 21)</td></tr>
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||
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<tr class="separator:a9ba940d336ed93498df4880f1e8710d9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6a1fd480bd8adde686c3725e1123a0f4"><td class="memItemLeft" align="right" valign="top"><a id="a6a1fd480bd8adde686c3725e1123a0f4"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a6a1fd480bd8adde686c3725e1123a0f4">PIN_PA20I_SDHC1_SDCMD</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(20)</td></tr>
|
||
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<tr class="memdesc:a6a1fd480bd8adde686c3725e1123a0f4"><td class="mdescLeft"> </td><td class="mdescRight">SDHC1 signal: SDCMD on PA20 mux I. <br /></td></tr>
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<tr class="separator:a6a1fd480bd8adde686c3725e1123a0f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2c27767c0ada33442b7c8190964d8a83"><td class="memItemLeft" align="right" valign="top"><a id="a2c27767c0ada33442b7c8190964d8a83"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PA20I_SDHC1_SDCMD</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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<tr class="separator:a2c27767c0ada33442b7c8190964d8a83"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a997f0c11bd78f257034db2a0a198f52e"><td class="memItemLeft" align="right" valign="top"><a id="a997f0c11bd78f257034db2a0a198f52e"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PA20I_SDHC1_SDCMD</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a6a1fd480bd8adde686c3725e1123a0f4">PIN_PA20I_SDHC1_SDCMD</a> << 16) | MUX_PA20I_SDHC1_SDCMD)</td></tr>
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<tr class="separator:a997f0c11bd78f257034db2a0a198f52e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4164d56c752b73dee15e5d7659121565"><td class="memItemLeft" align="right" valign="top"><a id="a4164d56c752b73dee15e5d7659121565"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PA20I_SDHC1_SDCMD</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 20)</td></tr>
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||
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<tr class="separator:a4164d56c752b73dee15e5d7659121565"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2902ffa452bb5c02771369f1d2730828"><td class="memItemLeft" align="right" valign="top"><a id="a2902ffa452bb5c02771369f1d2730828"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a2902ffa452bb5c02771369f1d2730828">PIN_PB18I_SDHC1_SDDAT0</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(50)</td></tr>
|
||
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<tr class="memdesc:a2902ffa452bb5c02771369f1d2730828"><td class="mdescLeft"> </td><td class="mdescRight">SDHC1 signal: SDDAT0 on PB18 mux I. <br /></td></tr>
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<tr class="separator:a2902ffa452bb5c02771369f1d2730828"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abf7989057c284db398d9e1a554357432"><td class="memItemLeft" align="right" valign="top"><a id="abf7989057c284db398d9e1a554357432"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB18I_SDHC1_SDDAT0</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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||
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<tr class="separator:abf7989057c284db398d9e1a554357432"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0d537c3c4319c7584227e2e1999a0066"><td class="memItemLeft" align="right" valign="top"><a id="a0d537c3c4319c7584227e2e1999a0066"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB18I_SDHC1_SDDAT0</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a2902ffa452bb5c02771369f1d2730828">PIN_PB18I_SDHC1_SDDAT0</a> << 16) | MUX_PB18I_SDHC1_SDDAT0)</td></tr>
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<tr class="separator:a0d537c3c4319c7584227e2e1999a0066"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae6e2e94d2b4e4a0d97ef9b3c952a58b0"><td class="memItemLeft" align="right" valign="top"><a id="ae6e2e94d2b4e4a0d97ef9b3c952a58b0"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB18I_SDHC1_SDDAT0</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 18)</td></tr>
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||
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<tr class="separator:ae6e2e94d2b4e4a0d97ef9b3c952a58b0"><td class="memSeparator" colspan="2"> </td></tr>
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||
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<tr class="memitem:aa096f5ec84f5c11fa5d23a9499c7d7cc"><td class="memItemLeft" align="right" valign="top"><a id="aa096f5ec84f5c11fa5d23a9499c7d7cc"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#aa096f5ec84f5c11fa5d23a9499c7d7cc">PIN_PB19I_SDHC1_SDDAT1</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(51)</td></tr>
|
||
|
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<tr class="memdesc:aa096f5ec84f5c11fa5d23a9499c7d7cc"><td class="mdescLeft"> </td><td class="mdescRight">SDHC1 signal: SDDAT1 on PB19 mux I. <br /></td></tr>
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<tr class="separator:aa096f5ec84f5c11fa5d23a9499c7d7cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aec50720b1ab9cd0c7a85df6a77a6174d"><td class="memItemLeft" align="right" valign="top"><a id="aec50720b1ab9cd0c7a85df6a77a6174d"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB19I_SDHC1_SDDAT1</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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||
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<tr class="separator:aec50720b1ab9cd0c7a85df6a77a6174d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aaba66e2dccde7cc58e8630cd3e6fab11"><td class="memItemLeft" align="right" valign="top"><a id="aaba66e2dccde7cc58e8630cd3e6fab11"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB19I_SDHC1_SDDAT1</b>   ((<a class="el" href="pio_2same54p20a_8h.html#aa096f5ec84f5c11fa5d23a9499c7d7cc">PIN_PB19I_SDHC1_SDDAT1</a> << 16) | MUX_PB19I_SDHC1_SDDAT1)</td></tr>
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<tr class="separator:aaba66e2dccde7cc58e8630cd3e6fab11"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4dbffeeaa0fa0991dda2932d760a12fb"><td class="memItemLeft" align="right" valign="top"><a id="a4dbffeeaa0fa0991dda2932d760a12fb"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB19I_SDHC1_SDDAT1</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 19)</td></tr>
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||
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<tr class="separator:a4dbffeeaa0fa0991dda2932d760a12fb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad3017802d2f20dd1450cc1f59516b09a"><td class="memItemLeft" align="right" valign="top"><a id="ad3017802d2f20dd1450cc1f59516b09a"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#ad3017802d2f20dd1450cc1f59516b09a">PIN_PB20I_SDHC1_SDDAT2</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(52)</td></tr>
|
||
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<tr class="memdesc:ad3017802d2f20dd1450cc1f59516b09a"><td class="mdescLeft"> </td><td class="mdescRight">SDHC1 signal: SDDAT2 on PB20 mux I. <br /></td></tr>
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<tr class="separator:ad3017802d2f20dd1450cc1f59516b09a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad58ee6699d0a0dccad76c486ba581027"><td class="memItemLeft" align="right" valign="top"><a id="ad58ee6699d0a0dccad76c486ba581027"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB20I_SDHC1_SDDAT2</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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||
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<tr class="separator:ad58ee6699d0a0dccad76c486ba581027"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a342e7017592d42eef42a1962d1e72199"><td class="memItemLeft" align="right" valign="top"><a id="a342e7017592d42eef42a1962d1e72199"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB20I_SDHC1_SDDAT2</b>   ((<a class="el" href="pio_2same54p20a_8h.html#ad3017802d2f20dd1450cc1f59516b09a">PIN_PB20I_SDHC1_SDDAT2</a> << 16) | MUX_PB20I_SDHC1_SDDAT2)</td></tr>
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<tr class="separator:a342e7017592d42eef42a1962d1e72199"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a388fdb854b206bfd83235aa050682ddd"><td class="memItemLeft" align="right" valign="top"><a id="a388fdb854b206bfd83235aa050682ddd"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB20I_SDHC1_SDDAT2</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 20)</td></tr>
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||
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<tr class="separator:a388fdb854b206bfd83235aa050682ddd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afa203efc0446dfae5ae9f1f6317e7cbf"><td class="memItemLeft" align="right" valign="top"><a id="afa203efc0446dfae5ae9f1f6317e7cbf"></a>
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||
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#afa203efc0446dfae5ae9f1f6317e7cbf">PIN_PB21I_SDHC1_SDDAT3</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(53)</td></tr>
|
||
|
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<tr class="memdesc:afa203efc0446dfae5ae9f1f6317e7cbf"><td class="mdescLeft"> </td><td class="mdescRight">SDHC1 signal: SDDAT3 on PB21 mux I. <br /></td></tr>
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<tr class="separator:afa203efc0446dfae5ae9f1f6317e7cbf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab8a38bae76b135ed772bf80bfbbd5734"><td class="memItemLeft" align="right" valign="top"><a id="ab8a38bae76b135ed772bf80bfbbd5734"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB21I_SDHC1_SDDAT3</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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||
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<tr class="separator:ab8a38bae76b135ed772bf80bfbbd5734"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9cc95d97b8b690cff84bd21ff758a449"><td class="memItemLeft" align="right" valign="top"><a id="a9cc95d97b8b690cff84bd21ff758a449"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB21I_SDHC1_SDDAT3</b>   ((<a class="el" href="pio_2same54p20a_8h.html#afa203efc0446dfae5ae9f1f6317e7cbf">PIN_PB21I_SDHC1_SDDAT3</a> << 16) | MUX_PB21I_SDHC1_SDDAT3)</td></tr>
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<tr class="separator:a9cc95d97b8b690cff84bd21ff758a449"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ada709fe8f97701ea505d38b4a00c0ab0"><td class="memItemLeft" align="right" valign="top"><a id="ada709fe8f97701ea505d38b4a00c0ab0"></a>
|
||
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB21I_SDHC1_SDDAT3</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 21)</td></tr>
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||
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<tr class="separator:ada709fe8f97701ea505d38b4a00c0ab0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1ca123636104f6a92cacf8cde3bd768d"><td class="memItemLeft" align="right" valign="top"><a id="a1ca123636104f6a92cacf8cde3bd768d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a1ca123636104f6a92cacf8cde3bd768d">PIN_PB17I_SDHC1_SDWP</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(49)</td></tr>
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<tr class="memdesc:a1ca123636104f6a92cacf8cde3bd768d"><td class="mdescLeft"> </td><td class="mdescRight">SDHC1 signal: SDWP on PB17 mux I. <br /></td></tr>
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<tr class="separator:a1ca123636104f6a92cacf8cde3bd768d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac73915d8e189e4aa3a1adabdeceba03a"><td class="memItemLeft" align="right" valign="top"><a id="ac73915d8e189e4aa3a1adabdeceba03a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PB17I_SDHC1_SDWP</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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<tr class="separator:ac73915d8e189e4aa3a1adabdeceba03a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5bb8f23d0b25cfa530ca70aeba3af81b"><td class="memItemLeft" align="right" valign="top"><a id="a5bb8f23d0b25cfa530ca70aeba3af81b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PB17I_SDHC1_SDWP</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a1ca123636104f6a92cacf8cde3bd768d">PIN_PB17I_SDHC1_SDWP</a> << 16) | MUX_PB17I_SDHC1_SDWP)</td></tr>
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<tr class="separator:a5bb8f23d0b25cfa530ca70aeba3af81b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:accebe52247ffb536c0e2ecca1cc58170"><td class="memItemLeft" align="right" valign="top"><a id="accebe52247ffb536c0e2ecca1cc58170"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PB17I_SDHC1_SDWP</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 17)</td></tr>
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<tr class="separator:accebe52247ffb536c0e2ecca1cc58170"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a077cc951218cd28cf6b68a7877a8b111"><td class="memItemLeft" align="right" valign="top"><a id="a077cc951218cd28cf6b68a7877a8b111"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="pio_2same54n20a_8h.html#a077cc951218cd28cf6b68a7877a8b111">PIN_PC21I_SDHC1_SDWP</a>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(85)</td></tr>
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<tr class="memdesc:a077cc951218cd28cf6b68a7877a8b111"><td class="mdescLeft"> </td><td class="mdescRight">SDHC1 signal: SDWP on PC21 mux I. <br /></td></tr>
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<tr class="separator:a077cc951218cd28cf6b68a7877a8b111"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a45b9c50e801f41a3388f99db2d5dd017"><td class="memItemLeft" align="right" valign="top"><a id="a45b9c50e801f41a3388f99db2d5dd017"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MUX_PC21I_SDHC1_SDWP</b>   <a class="el" href="same54p20a_8h.html#abb0ab0fd09ef35746cd37013d15cd731">_L_</a>(8)</td></tr>
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<tr class="separator:a45b9c50e801f41a3388f99db2d5dd017"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a39672a88127e4d620840447ffff4dca1"><td class="memItemLeft" align="right" valign="top"><a id="a39672a88127e4d620840447ffff4dca1"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PINMUX_PC21I_SDHC1_SDWP</b>   ((<a class="el" href="pio_2same54p20a_8h.html#a077cc951218cd28cf6b68a7877a8b111">PIN_PC21I_SDHC1_SDWP</a> << 16) | MUX_PC21I_SDHC1_SDWP)</td></tr>
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<tr class="separator:a39672a88127e4d620840447ffff4dca1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6827840c2be0a7bd29722aa1e426a96f"><td class="memItemLeft" align="right" valign="top"><a id="a6827840c2be0a7bd29722aa1e426a96f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PORT_PC21I_SDHC1_SDWP</b>   (<a class="el" href="same54p20a_8h.html#ad2451e287402b297a2a0687b6a2e38c3">_UL_</a>(1) << 21)</td></tr>
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<tr class="separator:a6827840c2be0a7bd29722aa1e426a96f"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>Peripheral I/O description for SAME54N20A. </p>
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<p>Copyright (c) 2019 Microchip Technology Inc.</p>
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<p>\asf_license_start </p>
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<p class="definition">Definition in file <a class="el" href="pio_2same54n20a_8h_source.html">same54n20a.h</a>.</p>
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Generated by <a href="http://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.8.20
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</small></address>
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