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266 lines
32 KiB
HTML
266 lines
32 KiB
HTML
4 years ago
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<title>SAME54P20A Test Project: /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/ramecc.h File Reference</title>
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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_2bb2e10400507f879251f0324a0a8c7c.html">component</a></li> </ul>
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<div class="summary">
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<a href="#nested-classes">Data Structures</a> |
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<a href="#define-members">Macros</a> </div>
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<div class="headertitle">
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<div class="title">ramecc.h File Reference</div> </div>
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<div class="contents">
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<p>Component description for RAMECC.
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<a href="#details">More...</a></p>
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<p><a href="component_2ramecc_8h_source.html">Go to the source code of this file.</a></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
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Data Structures</h2></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionRAMECC__INTENCLR__Type.html">RAMECC_INTENCLR_Type</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionRAMECC__INTENSET__Type.html">RAMECC_INTENSET_Type</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionRAMECC__INTFLAG__Type.html">RAMECC_INTFLAG_Type</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionRAMECC__STATUS__Type.html">RAMECC_STATUS_Type</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionRAMECC__ERRADDR__Type.html">RAMECC_ERRADDR_Type</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionRAMECC__DBGCTRL__Type.html">RAMECC_DBGCTRL_Type</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structRamecc.html">Ramecc</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">RAMECC hardware registers. <a href="structRamecc.html#details">More...</a><br /></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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Macros</h2></td></tr>
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<tr class="memitem:ab5aa64fc8b05def9b4e76c4c09fd503d"><td class="memItemLeft" align="right" valign="top"><a id="ab5aa64fc8b05def9b4e76c4c09fd503d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>RAMECC_U2268</b></td></tr>
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<tr class="separator:ab5aa64fc8b05def9b4e76c4c09fd503d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab77cf9955d2bef7495d195c22b95b741"><td class="memItemLeft" align="right" valign="top"><a id="ab77cf9955d2bef7495d195c22b95b741"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>REV_RAMECC</b>   0x100</td></tr>
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<tr class="separator:ab77cf9955d2bef7495d195c22b95b741"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6ecdeaa86842a9b5a0a99abede67f384"><td class="memItemLeft" align="right" valign="top"><a id="a6ecdeaa86842a9b5a0a99abede67f384"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2ramecc_8h.html#a6ecdeaa86842a9b5a0a99abede67f384">RAMECC_INTENCLR_OFFSET</a>   0x0</td></tr>
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<tr class="memdesc:a6ecdeaa86842a9b5a0a99abede67f384"><td class="mdescLeft"> </td><td class="mdescRight">(RAMECC_INTENCLR offset) Interrupt Enable Clear <br /></td></tr>
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<tr class="separator:a6ecdeaa86842a9b5a0a99abede67f384"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af905d7a6bc86a37d0e957904ae1c1847"><td class="memItemLeft" align="right" valign="top"><a id="af905d7a6bc86a37d0e957904ae1c1847"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2ramecc_8h.html#af905d7a6bc86a37d0e957904ae1c1847">RAMECC_INTENCLR_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00)</td></tr>
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<tr class="memdesc:af905d7a6bc86a37d0e957904ae1c1847"><td class="mdescLeft"> </td><td class="mdescRight">(RAMECC_INTENCLR reset_value) Interrupt Enable Clear <br /></td></tr>
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<tr class="separator:af905d7a6bc86a37d0e957904ae1c1847"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad78892cf766a2ceea0c07e82236954ea"><td class="memItemLeft" align="right" valign="top"><a id="ad78892cf766a2ceea0c07e82236954ea"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2ramecc_8h.html#ad78892cf766a2ceea0c07e82236954ea">RAMECC_INTENCLR_SINGLEE_Pos</a>   0</td></tr>
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<tr class="memdesc:ad78892cf766a2ceea0c07e82236954ea"><td class="mdescLeft"> </td><td class="mdescRight">(RAMECC_INTENCLR) Single Bit ECC Error Interrupt Enable Clear <br /></td></tr>
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<tr class="separator:ad78892cf766a2ceea0c07e82236954ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a90679f8cb106537b5eb24cdeda4cee9f"><td class="memItemLeft" align="right" valign="top"><a id="a90679f8cb106537b5eb24cdeda4cee9f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>RAMECC_INTENCLR_SINGLEE</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2ramecc_8h.html#ad78892cf766a2ceea0c07e82236954ea">RAMECC_INTENCLR_SINGLEE_Pos</a>)</td></tr>
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<tr class="separator:a90679f8cb106537b5eb24cdeda4cee9f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa8f8f8016d8b11f20868660762d61636"><td class="memItemLeft" align="right" valign="top"><a id="aa8f8f8016d8b11f20868660762d61636"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2ramecc_8h.html#aa8f8f8016d8b11f20868660762d61636">RAMECC_INTENCLR_DUALE_Pos</a>   1</td></tr>
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<tr class="memdesc:aa8f8f8016d8b11f20868660762d61636"><td class="mdescLeft"> </td><td class="mdescRight">(RAMECC_INTENCLR) Dual Bit ECC Error Interrupt Enable Clear <br /></td></tr>
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<tr class="separator:aa8f8f8016d8b11f20868660762d61636"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ace8121e51c0fb6dd7d492c418980cb64"><td class="memItemLeft" align="right" valign="top"><a id="ace8121e51c0fb6dd7d492c418980cb64"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>RAMECC_INTENCLR_DUALE</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2ramecc_8h.html#aa8f8f8016d8b11f20868660762d61636">RAMECC_INTENCLR_DUALE_Pos</a>)</td></tr>
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<tr class="separator:ace8121e51c0fb6dd7d492c418980cb64"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac2d16480713fd62c82cd54b94d894ea1"><td class="memItemLeft" align="right" valign="top"><a id="ac2d16480713fd62c82cd54b94d894ea1"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2ramecc_8h.html#ac2d16480713fd62c82cd54b94d894ea1">RAMECC_INTENCLR_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x03)</td></tr>
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<tr class="memdesc:ac2d16480713fd62c82cd54b94d894ea1"><td class="mdescLeft"> </td><td class="mdescRight">(RAMECC_INTENCLR) MASK Register <br /></td></tr>
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<tr class="separator:ac2d16480713fd62c82cd54b94d894ea1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac428cc201847ef38fdfccb09d43dfd05"><td class="memItemLeft" align="right" valign="top"><a id="ac428cc201847ef38fdfccb09d43dfd05"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2ramecc_8h.html#ac428cc201847ef38fdfccb09d43dfd05">RAMECC_INTENSET_OFFSET</a>   0x1</td></tr>
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<tr class="memdesc:ac428cc201847ef38fdfccb09d43dfd05"><td class="mdescLeft"> </td><td class="mdescRight">(RAMECC_INTENSET offset) Interrupt Enable Set <br /></td></tr>
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<tr class="separator:ac428cc201847ef38fdfccb09d43dfd05"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1d0eda60a8a741fb277a5762c66f6664"><td class="memItemLeft" align="right" valign="top"><a id="a1d0eda60a8a741fb277a5762c66f6664"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2ramecc_8h.html#a1d0eda60a8a741fb277a5762c66f6664">RAMECC_INTENSET_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00)</td></tr>
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<tr class="memdesc:a1d0eda60a8a741fb277a5762c66f6664"><td class="mdescLeft"> </td><td class="mdescRight">(RAMECC_INTENSET reset_value) Interrupt Enable Set <br /></td></tr>
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<tr class="separator:a1d0eda60a8a741fb277a5762c66f6664"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3f7d235551f4e8b801aa723b1dfd9d50"><td class="memItemLeft" align="right" valign="top"><a id="a3f7d235551f4e8b801aa723b1dfd9d50"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2ramecc_8h.html#a3f7d235551f4e8b801aa723b1dfd9d50">RAMECC_INTENSET_SINGLEE_Pos</a>   0</td></tr>
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<tr class="memdesc:a3f7d235551f4e8b801aa723b1dfd9d50"><td class="mdescLeft"> </td><td class="mdescRight">(RAMECC_INTENSET) Single Bit ECC Error Interrupt Enable Set <br /></td></tr>
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<tr class="separator:a3f7d235551f4e8b801aa723b1dfd9d50"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a09989326bf0501e3ef6046b1ea2a4164"><td class="memItemLeft" align="right" valign="top"><a id="a09989326bf0501e3ef6046b1ea2a4164"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>RAMECC_INTENSET_SINGLEE</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2ramecc_8h.html#a3f7d235551f4e8b801aa723b1dfd9d50">RAMECC_INTENSET_SINGLEE_Pos</a>)</td></tr>
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<tr class="separator:a09989326bf0501e3ef6046b1ea2a4164"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a540bd256680ad5cc67e90d3d05ff3888"><td class="memItemLeft" align="right" valign="top"><a id="a540bd256680ad5cc67e90d3d05ff3888"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2ramecc_8h.html#a540bd256680ad5cc67e90d3d05ff3888">RAMECC_INTENSET_DUALE_Pos</a>   1</td></tr>
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<tr class="memdesc:a540bd256680ad5cc67e90d3d05ff3888"><td class="mdescLeft"> </td><td class="mdescRight">(RAMECC_INTENSET) Dual Bit ECC Error Interrupt Enable Set <br /></td></tr>
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<tr class="separator:a540bd256680ad5cc67e90d3d05ff3888"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a81d0a54ba563fa6b6e9cfd5ba8d27424"><td class="memItemLeft" align="right" valign="top"><a id="a81d0a54ba563fa6b6e9cfd5ba8d27424"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>RAMECC_INTENSET_DUALE</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2ramecc_8h.html#a540bd256680ad5cc67e90d3d05ff3888">RAMECC_INTENSET_DUALE_Pos</a>)</td></tr>
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<tr class="separator:a81d0a54ba563fa6b6e9cfd5ba8d27424"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afce3a73643801607c3b2953710448281"><td class="memItemLeft" align="right" valign="top"><a id="afce3a73643801607c3b2953710448281"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2ramecc_8h.html#afce3a73643801607c3b2953710448281">RAMECC_INTENSET_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x03)</td></tr>
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<tr class="memdesc:afce3a73643801607c3b2953710448281"><td class="mdescLeft"> </td><td class="mdescRight">(RAMECC_INTENSET) MASK Register <br /></td></tr>
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<tr class="memitem:a97ba817ff23664a405979a16c296adb5"><td class="memItemLeft" align="right" valign="top"><a id="a97ba817ff23664a405979a16c296adb5"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2ramecc_8h.html#a97ba817ff23664a405979a16c296adb5">RAMECC_INTFLAG_OFFSET</a>   0x2</td></tr>
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<tr class="memdesc:a97ba817ff23664a405979a16c296adb5"><td class="mdescLeft"> </td><td class="mdescRight">(RAMECC_INTFLAG offset) Interrupt Flag <br /></td></tr>
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<tr class="memitem:a75316aa5bf2764aef9342ab9e97102ce"><td class="memItemLeft" align="right" valign="top"><a id="a75316aa5bf2764aef9342ab9e97102ce"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2ramecc_8h.html#a75316aa5bf2764aef9342ab9e97102ce">RAMECC_INTFLAG_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00)</td></tr>
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<tr class="memdesc:a75316aa5bf2764aef9342ab9e97102ce"><td class="mdescLeft"> </td><td class="mdescRight">(RAMECC_INTFLAG reset_value) Interrupt Flag <br /></td></tr>
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<tr class="memitem:a670716fa90c43dec438166271e62b842"><td class="memItemLeft" align="right" valign="top"><a id="a670716fa90c43dec438166271e62b842"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2ramecc_8h.html#a670716fa90c43dec438166271e62b842">RAMECC_INTFLAG_SINGLEE_Pos</a>   0</td></tr>
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<tr class="memdesc:a670716fa90c43dec438166271e62b842"><td class="mdescLeft"> </td><td class="mdescRight">(RAMECC_INTFLAG) Single Bit ECC Error Interrupt <br /></td></tr>
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<tr class="memitem:a0d243c9d57fce652f7946e30ea6ca8cb"><td class="memItemLeft" align="right" valign="top"><a id="a0d243c9d57fce652f7946e30ea6ca8cb"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>RAMECC_INTFLAG_SINGLEE</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2ramecc_8h.html#a670716fa90c43dec438166271e62b842">RAMECC_INTFLAG_SINGLEE_Pos</a>)</td></tr>
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<tr class="memitem:aa3e61ae09b527a9e0ab2a4621aa20959"><td class="memItemLeft" align="right" valign="top"><a id="aa3e61ae09b527a9e0ab2a4621aa20959"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2ramecc_8h.html#aa3e61ae09b527a9e0ab2a4621aa20959">RAMECC_INTFLAG_DUALE_Pos</a>   1</td></tr>
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<tr class="memdesc:aa3e61ae09b527a9e0ab2a4621aa20959"><td class="mdescLeft"> </td><td class="mdescRight">(RAMECC_INTFLAG) Dual Bit ECC Error Interrupt <br /></td></tr>
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<tr class="memitem:a431c638a6d0736dd997a1e3654e10914"><td class="memItemLeft" align="right" valign="top"><a id="a431c638a6d0736dd997a1e3654e10914"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>RAMECC_INTFLAG_DUALE</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2ramecc_8h.html#aa3e61ae09b527a9e0ab2a4621aa20959">RAMECC_INTFLAG_DUALE_Pos</a>)</td></tr>
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<tr class="memitem:a53cbb484920b486324488c1e6e04fcba"><td class="memItemLeft" align="right" valign="top"><a id="a53cbb484920b486324488c1e6e04fcba"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2ramecc_8h.html#a53cbb484920b486324488c1e6e04fcba">RAMECC_INTFLAG_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x03)</td></tr>
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<tr class="memdesc:a53cbb484920b486324488c1e6e04fcba"><td class="mdescLeft"> </td><td class="mdescRight">(RAMECC_INTFLAG) MASK Register <br /></td></tr>
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<tr class="separator:a53cbb484920b486324488c1e6e04fcba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a92482bf7dca87d60e43bff04febe1726"><td class="memItemLeft" align="right" valign="top"><a id="a92482bf7dca87d60e43bff04febe1726"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2ramecc_8h.html#a92482bf7dca87d60e43bff04febe1726">RAMECC_STATUS_OFFSET</a>   0x3</td></tr>
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<tr class="memdesc:a92482bf7dca87d60e43bff04febe1726"><td class="mdescLeft"> </td><td class="mdescRight">(RAMECC_STATUS offset) Status <br /></td></tr>
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<tr class="memitem:ade15049c636df2ad5882e1b6798b8799"><td class="memItemLeft" align="right" valign="top"><a id="ade15049c636df2ad5882e1b6798b8799"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2ramecc_8h.html#ade15049c636df2ad5882e1b6798b8799">RAMECC_STATUS_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00)</td></tr>
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<tr class="memdesc:ade15049c636df2ad5882e1b6798b8799"><td class="mdescLeft"> </td><td class="mdescRight">(RAMECC_STATUS reset_value) Status <br /></td></tr>
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<tr class="memitem:aad3526dd29623bdf0b6b017385ce8cee"><td class="memItemLeft" align="right" valign="top"><a id="aad3526dd29623bdf0b6b017385ce8cee"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2ramecc_8h.html#aad3526dd29623bdf0b6b017385ce8cee">RAMECC_STATUS_ECCDIS_Pos</a>   0</td></tr>
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<tr class="memdesc:aad3526dd29623bdf0b6b017385ce8cee"><td class="mdescLeft"> </td><td class="mdescRight">(RAMECC_STATUS) ECC Disable <br /></td></tr>
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<tr class="memitem:a41038d3d999d0a9343dece190af34918"><td class="memItemLeft" align="right" valign="top"><a id="a41038d3d999d0a9343dece190af34918"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>RAMECC_STATUS_ECCDIS</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2ramecc_8h.html#aad3526dd29623bdf0b6b017385ce8cee">RAMECC_STATUS_ECCDIS_Pos</a>)</td></tr>
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<tr class="separator:a41038d3d999d0a9343dece190af34918"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7744be01916c51171405466f2f5e77fa"><td class="memItemLeft" align="right" valign="top"><a id="a7744be01916c51171405466f2f5e77fa"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2ramecc_8h.html#a7744be01916c51171405466f2f5e77fa">RAMECC_STATUS_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x01)</td></tr>
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<tr class="memdesc:a7744be01916c51171405466f2f5e77fa"><td class="mdescLeft"> </td><td class="mdescRight">(RAMECC_STATUS) MASK Register <br /></td></tr>
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<tr class="separator:a7744be01916c51171405466f2f5e77fa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae1210dedbd55a1583bebd5ee8870d5dc"><td class="memItemLeft" align="right" valign="top"><a id="ae1210dedbd55a1583bebd5ee8870d5dc"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2ramecc_8h.html#ae1210dedbd55a1583bebd5ee8870d5dc">RAMECC_ERRADDR_OFFSET</a>   0x4</td></tr>
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<tr class="memdesc:ae1210dedbd55a1583bebd5ee8870d5dc"><td class="mdescLeft"> </td><td class="mdescRight">(RAMECC_ERRADDR offset) Error Address <br /></td></tr>
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<tr class="separator:ae1210dedbd55a1583bebd5ee8870d5dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a421c81f0ceb471869a0dad27520761bb"><td class="memItemLeft" align="right" valign="top"><a id="a421c81f0ceb471869a0dad27520761bb"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2ramecc_8h.html#a421c81f0ceb471869a0dad27520761bb">RAMECC_ERRADDR_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000000)</td></tr>
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<tr class="memdesc:a421c81f0ceb471869a0dad27520761bb"><td class="mdescLeft"> </td><td class="mdescRight">(RAMECC_ERRADDR reset_value) Error Address <br /></td></tr>
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<tr class="memitem:aa78357b85c2bc9531d87c2a7ffb94490"><td class="memItemLeft" align="right" valign="top"><a id="aa78357b85c2bc9531d87c2a7ffb94490"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2ramecc_8h.html#aa78357b85c2bc9531d87c2a7ffb94490">RAMECC_ERRADDR_ERRADDR_Pos</a>   0</td></tr>
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<tr class="memdesc:aa78357b85c2bc9531d87c2a7ffb94490"><td class="mdescLeft"> </td><td class="mdescRight">(RAMECC_ERRADDR) Error Address <br /></td></tr>
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<tr class="separator:aa78357b85c2bc9531d87c2a7ffb94490"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa17c78bfd950b3302dc61fc1ed40298f"><td class="memItemLeft" align="right" valign="top"><a id="aa17c78bfd950b3302dc61fc1ed40298f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>RAMECC_ERRADDR_ERRADDR_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1FFFF) << <a class="el" href="component_2ramecc_8h.html#aa78357b85c2bc9531d87c2a7ffb94490">RAMECC_ERRADDR_ERRADDR_Pos</a>)</td></tr>
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<tr class="separator:aa17c78bfd950b3302dc61fc1ed40298f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af6b990ef677cd1b5dee15a1bd2f4d3ac"><td class="memItemLeft" align="right" valign="top"><a id="af6b990ef677cd1b5dee15a1bd2f4d3ac"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>RAMECC_ERRADDR_ERRADDR</b>(value)   (RAMECC_ERRADDR_ERRADDR_Msk & ((value) << <a class="el" href="component_2ramecc_8h.html#aa78357b85c2bc9531d87c2a7ffb94490">RAMECC_ERRADDR_ERRADDR_Pos</a>))</td></tr>
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<tr class="separator:af6b990ef677cd1b5dee15a1bd2f4d3ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abd318720c748f4880ae7db2f304f48ed"><td class="memItemLeft" align="right" valign="top"><a id="abd318720c748f4880ae7db2f304f48ed"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2ramecc_8h.html#abd318720c748f4880ae7db2f304f48ed">RAMECC_ERRADDR_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x0001FFFF)</td></tr>
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<tr class="memdesc:abd318720c748f4880ae7db2f304f48ed"><td class="mdescLeft"> </td><td class="mdescRight">(RAMECC_ERRADDR) MASK Register <br /></td></tr>
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<tr class="separator:abd318720c748f4880ae7db2f304f48ed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a95f3d6ef123e45e0583164ae6ac03544"><td class="memItemLeft" align="right" valign="top"><a id="a95f3d6ef123e45e0583164ae6ac03544"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2ramecc_8h.html#a95f3d6ef123e45e0583164ae6ac03544">RAMECC_DBGCTRL_OFFSET</a>   0xF</td></tr>
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<tr class="memdesc:a95f3d6ef123e45e0583164ae6ac03544"><td class="mdescLeft"> </td><td class="mdescRight">(RAMECC_DBGCTRL offset) Debug Control <br /></td></tr>
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<tr class="separator:a95f3d6ef123e45e0583164ae6ac03544"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aed80d19f1724acee50967a8212ee2b1c"><td class="memItemLeft" align="right" valign="top"><a id="aed80d19f1724acee50967a8212ee2b1c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2ramecc_8h.html#aed80d19f1724acee50967a8212ee2b1c">RAMECC_DBGCTRL_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00)</td></tr>
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<tr class="memdesc:aed80d19f1724acee50967a8212ee2b1c"><td class="mdescLeft"> </td><td class="mdescRight">(RAMECC_DBGCTRL reset_value) Debug Control <br /></td></tr>
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<tr class="separator:aed80d19f1724acee50967a8212ee2b1c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa5972c5e97ddb80048f2a045f8789b96"><td class="memItemLeft" align="right" valign="top"><a id="aa5972c5e97ddb80048f2a045f8789b96"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2ramecc_8h.html#aa5972c5e97ddb80048f2a045f8789b96">RAMECC_DBGCTRL_ECCDIS_Pos</a>   0</td></tr>
|
||
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<tr class="memdesc:aa5972c5e97ddb80048f2a045f8789b96"><td class="mdescLeft"> </td><td class="mdescRight">(RAMECC_DBGCTRL) ECC Disable <br /></td></tr>
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<tr class="separator:aa5972c5e97ddb80048f2a045f8789b96"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0d7824df36089e00d0732fa53f6b2f82"><td class="memItemLeft" align="right" valign="top"><a id="a0d7824df36089e00d0732fa53f6b2f82"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>RAMECC_DBGCTRL_ECCDIS</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2ramecc_8h.html#aa5972c5e97ddb80048f2a045f8789b96">RAMECC_DBGCTRL_ECCDIS_Pos</a>)</td></tr>
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<tr class="separator:a0d7824df36089e00d0732fa53f6b2f82"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad80a79467c2c1661d1a7dc3d03376fd8"><td class="memItemLeft" align="right" valign="top"><a id="ad80a79467c2c1661d1a7dc3d03376fd8"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2ramecc_8h.html#ad80a79467c2c1661d1a7dc3d03376fd8">RAMECC_DBGCTRL_ECCELOG_Pos</a>   1</td></tr>
|
||
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<tr class="memdesc:ad80a79467c2c1661d1a7dc3d03376fd8"><td class="mdescLeft"> </td><td class="mdescRight">(RAMECC_DBGCTRL) ECC Error Log <br /></td></tr>
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<tr class="separator:ad80a79467c2c1661d1a7dc3d03376fd8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7ebf185ba186c8449716457f6e5fb339"><td class="memItemLeft" align="right" valign="top"><a id="a7ebf185ba186c8449716457f6e5fb339"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>RAMECC_DBGCTRL_ECCELOG</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2ramecc_8h.html#ad80a79467c2c1661d1a7dc3d03376fd8">RAMECC_DBGCTRL_ECCELOG_Pos</a>)</td></tr>
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<tr class="separator:a7ebf185ba186c8449716457f6e5fb339"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1b3536513c7d5d946dc77a753c0bf2fb"><td class="memItemLeft" align="right" valign="top"><a id="a1b3536513c7d5d946dc77a753c0bf2fb"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2ramecc_8h.html#a1b3536513c7d5d946dc77a753c0bf2fb">RAMECC_DBGCTRL_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x03)</td></tr>
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<tr class="memdesc:a1b3536513c7d5d946dc77a753c0bf2fb"><td class="mdescLeft"> </td><td class="mdescRight">(RAMECC_DBGCTRL) MASK Register <br /></td></tr>
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<tr class="separator:a1b3536513c7d5d946dc77a753c0bf2fb"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>Component description for RAMECC. </p>
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<p>Copyright (c) 2019 Microchip Technology Inc.</p>
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<p>\asf_license_start </p>
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<p class="definition">Definition in file <a class="el" href="component_2ramecc_8h_source.html">ramecc.h</a>.</p>
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