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61 lines
2.1 KiB
C
61 lines
2.1 KiB
C
4 years ago
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#ifndef _HDI_SAM_D2X_H_
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#define _HDI_SAM_D2X_H_
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#include "hal_arm.h"
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if !(defined(__ASSEMBLY__))
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#ifndef __cplusplus
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typedef volatile const uint32_t RoReg; // Read only 32-bit register (volatile const unsigned int)
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typedef volatile const uint16_t RoReg16; // Read only 16-bit register (volatile const unsigned int)
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typedef volatile const uint8_t RoReg8; // Read only 8-bit register (volatile const unsigned int)
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#else
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typedef volatile uint32_t RoReg; // Read only 32-bit register (volatile const unsigned int)
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typedef volatile uint16_t RoReg16; // Read only 16-bit register (volatile const unsigned int)
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typedef volatile uint8_t RoReg8; // Read only 8-bit register (volatile const unsigned int)
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#endif
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typedef volatile uint32_t WoReg; // Write only 32-bit register (volatile unsigned int)
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typedef volatile uint16_t WoReg16; // Write only 16-bit register (volatile unsigned int)
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typedef volatile uint16_t WoReg8; // Write only 8-bit register (volatile unsigned int)
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typedef volatile uint32_t RwReg; // Write only 32-bit register (volatile unsigned int)
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typedef volatile uint16_t RwReg16; // Write only 16-bit register (volatile unsigned int)
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typedef volatile uint8_t RwReg8; // Write only 8-bit register (volatile unsigned int)
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#define CAST(type, value) ((type*)(value))
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#define REG_ACCESS(type, address) (*(type*)(address))
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#else
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#define CAST(type, value) (value)
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#define REG_ACCESS(type, address) (address)
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#endif
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typedef enum IRQn
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{
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// Cortex-M0+ Processor Exception Numbers
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NonMaskableInt_IRQn = -14,
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HardFault_IRQn = -13,
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SVCall_IRQn = -5,
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PendSV_IRQn = -2,
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SysTick_IRQn = -1,
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// samd21j18a specific interrupt numbers
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PM_IRQn = 0,
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SYSCTRL_IRQn = 1,
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WDT_IRQn = 2,
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RTC_IRQn = 3,
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EIC_IRQn = 4,
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NVMCTRL_IRQn = 5,
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DMAC_IRQn = 6,
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USB_IRQn = 7,
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EVSYS_IRQ = 8,
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SERCOM0_IRQn = 9,
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SERCOM1_IRQn = 10,
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SERCOM2_IRQn = 11,
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SERCOM3_IRQn = 12,
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SERCOM4_IRQn = 13,
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SERCOM5_IRQn = 14
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}IRQn_Type;
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#ifdef __cplusplus
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}
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#endif
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#endif
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