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282 lines
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4 years ago
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<title>DEC Alpha Options - Using the GNU Compiler Collection (GCC)</title>
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<meta name="description" content="Using the GNU Compiler Collection (GCC)">
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<link title="Top" rel="start" href="index.html#Top">
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<link rel="up" href="Submodel-Options.html#Submodel-Options" title="Submodel Options">
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<link rel="prev" href="Darwin-Options.html#Darwin-Options" title="Darwin Options">
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<link rel="next" href="FR30-Options.html#FR30-Options" title="FR30 Options">
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Copyright (C) 1988-2015 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.3 or
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any later version published by the Free Software Foundation; with the
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Invariant Sections being ``Funding Free Software'', the Front-Cover
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(see below). A copy of the license is included in the section entitled
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(a) The FSF's Front-Cover Text is:
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A GNU Manual
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(b) The FSF's Back-Cover Text is:
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</head>
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<body>
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<div class="node">
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<a name="DEC-Alpha-Options"></a>
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<p>
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Next: <a rel="next" accesskey="n" href="FR30-Options.html#FR30-Options">FR30 Options</a>,
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Previous: <a rel="previous" accesskey="p" href="Darwin-Options.html#Darwin-Options">Darwin Options</a>,
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Up: <a rel="up" accesskey="u" href="Submodel-Options.html#Submodel-Options">Submodel Options</a>
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<hr>
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</div>
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<h4 class="subsection">3.17.11 DEC Alpha Options</h4>
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<p>These ‘<samp><span class="samp">-m</span></samp>’ options are defined for the DEC Alpha implementations:
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<dl>
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<dt><code>-mno-soft-float</code><dt><code>-msoft-float</code><dd><a name="index-mno_002dsoft_002dfloat-1603"></a><a name="index-msoft_002dfloat-1604"></a>Use (do not use) the hardware floating-point instructions for
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floating-point operations. When <samp><span class="option">-msoft-float</span></samp> is specified,
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functions in <samp><span class="file">libgcc.a</span></samp> are used to perform floating-point
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operations. Unless they are replaced by routines that emulate the
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floating-point operations, or compiled in such a way as to call such
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emulations routines, these routines issue floating-point
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operations. If you are compiling for an Alpha without floating-point
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operations, you must ensure that the library is built so as not to call
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them.
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<p>Note that Alpha implementations without floating-point operations are
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required to have floating-point registers.
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<br><dt><code>-mfp-reg</code><dt><code>-mno-fp-regs</code><dd><a name="index-mfp_002dreg-1605"></a><a name="index-mno_002dfp_002dregs-1606"></a>Generate code that uses (does not use) the floating-point register set.
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<samp><span class="option">-mno-fp-regs</span></samp> implies <samp><span class="option">-msoft-float</span></samp>. If the floating-point
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register set is not used, floating-point operands are passed in integer
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registers as if they were integers and floating-point results are passed
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in <code>$0</code> instead of <code>$f0</code>. This is a non-standard calling sequence,
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so any function with a floating-point argument or return value called by code
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compiled with <samp><span class="option">-mno-fp-regs</span></samp> must also be compiled with that
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option.
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<p>A typical use of this option is building a kernel that does not use,
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and hence need not save and restore, any floating-point registers.
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<br><dt><code>-mieee</code><dd><a name="index-mieee-1607"></a>The Alpha architecture implements floating-point hardware optimized for
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maximum performance. It is mostly compliant with the IEEE floating-point
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standard. However, for full compliance, software assistance is
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required. This option generates code fully IEEE-compliant code
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<em>except</em> that the <var>inexact-flag</var> is not maintained (see below).
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If this option is turned on, the preprocessor macro <code>_IEEE_FP</code> is
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defined during compilation. The resulting code is less efficient but is
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able to correctly support denormalized numbers and exceptional IEEE
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values such as not-a-number and plus/minus infinity. Other Alpha
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compilers call this option <samp><span class="option">-ieee_with_no_inexact</span></samp>.
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<br><dt><code>-mieee-with-inexact</code><dd><a name="index-mieee_002dwith_002dinexact-1608"></a>This is like <samp><span class="option">-mieee</span></samp> except the generated code also maintains
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the IEEE <var>inexact-flag</var>. Turning on this option causes the
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generated code to implement fully-compliant IEEE math. In addition to
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<code>_IEEE_FP</code>, <code>_IEEE_FP_EXACT</code> is defined as a preprocessor
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macro. On some Alpha implementations the resulting code may execute
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significantly slower than the code generated by default. Since there is
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very little code that depends on the <var>inexact-flag</var>, you should
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normally not specify this option. Other Alpha compilers call this
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option <samp><span class="option">-ieee_with_inexact</span></samp>.
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<br><dt><code>-mfp-trap-mode=</code><var>trap-mode</var><dd><a name="index-mfp_002dtrap_002dmode-1609"></a>This option controls what floating-point related traps are enabled.
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Other Alpha compilers call this option <samp><span class="option">-fptm </span><var>trap-mode</var></samp>.
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The trap mode can be set to one of four values:
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<dl>
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<dt>‘<samp><span class="samp">n</span></samp>’<dd>This is the default (normal) setting. The only traps that are enabled
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are the ones that cannot be disabled in software (e.g., division by zero
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trap).
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<br><dt>‘<samp><span class="samp">u</span></samp>’<dd>In addition to the traps enabled by ‘<samp><span class="samp">n</span></samp>’, underflow traps are enabled
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as well.
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<br><dt>‘<samp><span class="samp">su</span></samp>’<dd>Like ‘<samp><span class="samp">u</span></samp>’, but the instructions are marked to be safe for software
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completion (see Alpha architecture manual for details).
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<br><dt>‘<samp><span class="samp">sui</span></samp>’<dd>Like ‘<samp><span class="samp">su</span></samp>’, but inexact traps are enabled as well.
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</dl>
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<br><dt><code>-mfp-rounding-mode=</code><var>rounding-mode</var><dd><a name="index-mfp_002drounding_002dmode-1610"></a>Selects the IEEE rounding mode. Other Alpha compilers call this option
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<samp><span class="option">-fprm </span><var>rounding-mode</var></samp>. The <var>rounding-mode</var> can be one
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of:
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<dl>
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<dt>‘<samp><span class="samp">n</span></samp>’<dd>Normal IEEE rounding mode. Floating-point numbers are rounded towards
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the nearest machine number or towards the even machine number in case
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of a tie.
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<br><dt>‘<samp><span class="samp">m</span></samp>’<dd>Round towards minus infinity.
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<br><dt>‘<samp><span class="samp">c</span></samp>’<dd>Chopped rounding mode. Floating-point numbers are rounded towards zero.
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<br><dt>‘<samp><span class="samp">d</span></samp>’<dd>Dynamic rounding mode. A field in the floating-point control register
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(<var>fpcr</var>, see Alpha architecture reference manual) controls the
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rounding mode in effect. The C library initializes this register for
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rounding towards plus infinity. Thus, unless your program modifies the
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<var>fpcr</var>, ‘<samp><span class="samp">d</span></samp>’ corresponds to round towards plus infinity.
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</dl>
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<br><dt><code>-mtrap-precision=</code><var>trap-precision</var><dd><a name="index-mtrap_002dprecision-1611"></a>In the Alpha architecture, floating-point traps are imprecise. This
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means without software assistance it is impossible to recover from a
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floating trap and program execution normally needs to be terminated.
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GCC can generate code that can assist operating system trap handlers
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in determining the exact location that caused a floating-point trap.
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Depending on the requirements of an application, different levels of
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precisions can be selected:
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<dl>
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<dt>‘<samp><span class="samp">p</span></samp>’<dd>Program precision. This option is the default and means a trap handler
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can only identify which program caused a floating-point exception.
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<br><dt>‘<samp><span class="samp">f</span></samp>’<dd>Function precision. The trap handler can determine the function that
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caused a floating-point exception.
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<br><dt>‘<samp><span class="samp">i</span></samp>’<dd>Instruction precision. The trap handler can determine the exact
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instruction that caused a floating-point exception.
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</dl>
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<p>Other Alpha compilers provide the equivalent options called
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<samp><span class="option">-scope_safe</span></samp> and <samp><span class="option">-resumption_safe</span></samp>.
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<br><dt><code>-mieee-conformant</code><dd><a name="index-mieee_002dconformant-1612"></a>This option marks the generated code as IEEE conformant. You must not
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use this option unless you also specify <samp><span class="option">-mtrap-precision=i</span></samp> and either
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<samp><span class="option">-mfp-trap-mode=su</span></samp> or <samp><span class="option">-mfp-trap-mode=sui</span></samp>. Its only effect
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is to emit the line ‘<samp><span class="samp">.eflag 48</span></samp>’ in the function prologue of the
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generated assembly file.
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<br><dt><code>-mbuild-constants</code><dd><a name="index-mbuild_002dconstants-1613"></a>Normally GCC examines a 32- or 64-bit integer constant to
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see if it can construct it from smaller constants in two or three
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instructions. If it cannot, it outputs the constant as a literal and
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generates code to load it from the data segment at run time.
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<p>Use this option to require GCC to construct <em>all</em> integer constants
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using code, even if it takes more instructions (the maximum is six).
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<p>You typically use this option to build a shared library dynamic
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loader. Itself a shared library, it must relocate itself in memory
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before it can find the variables and constants in its own data segment.
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<br><dt><code>-mbwx</code><dt><code>-mno-bwx</code><dt><code>-mcix</code><dt><code>-mno-cix</code><dt><code>-mfix</code><dt><code>-mno-fix</code><dt><code>-mmax</code><dt><code>-mno-max</code><dd><a name="index-mbwx-1614"></a><a name="index-mno_002dbwx-1615"></a><a name="index-mcix-1616"></a><a name="index-mno_002dcix-1617"></a><a name="index-mfix-1618"></a><a name="index-mno_002dfix-1619"></a><a name="index-mmax-1620"></a><a name="index-mno_002dmax-1621"></a>Indicate whether GCC should generate code to use the optional BWX,
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CIX, FIX and MAX instruction sets. The default is to use the instruction
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sets supported by the CPU type specified via <samp><span class="option">-mcpu=</span></samp> option or that
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of the CPU on which GCC was built if none is specified.
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<br><dt><code>-mfloat-vax</code><dt><code>-mfloat-ieee</code><dd><a name="index-mfloat_002dvax-1622"></a><a name="index-mfloat_002dieee-1623"></a>Generate code that uses (does not use) VAX F and G floating-point
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arithmetic instead of IEEE single and double precision.
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<br><dt><code>-mexplicit-relocs</code><dt><code>-mno-explicit-relocs</code><dd><a name="index-mexplicit_002drelocs-1624"></a><a name="index-mno_002dexplicit_002drelocs-1625"></a>Older Alpha assemblers provided no way to generate symbol relocations
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except via assembler macros. Use of these macros does not allow
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optimal instruction scheduling. GNU binutils as of version 2.12
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supports a new syntax that allows the compiler to explicitly mark
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which relocations should apply to which instructions. This option
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is mostly useful for debugging, as GCC detects the capabilities of
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the assembler when it is built and sets the default accordingly.
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<br><dt><code>-msmall-data</code><dt><code>-mlarge-data</code><dd><a name="index-msmall_002ddata-1626"></a><a name="index-mlarge_002ddata-1627"></a>When <samp><span class="option">-mexplicit-relocs</span></samp> is in effect, static data is
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accessed via <dfn>gp-relative</dfn> relocations. When <samp><span class="option">-msmall-data</span></samp>
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is used, objects 8 bytes long or smaller are placed in a <dfn>small data area</dfn>
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(the <code>.sdata</code> and <code>.sbss</code> sections) and are accessed via
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16-bit relocations off of the <code>$gp</code> register. This limits the
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size of the small data area to 64KB, but allows the variables to be
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directly accessed via a single instruction.
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<p>The default is <samp><span class="option">-mlarge-data</span></samp>. With this option the data area
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is limited to just below 2GB. Programs that require more than 2GB of
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data must use <code>malloc</code> or <code>mmap</code> to allocate the data in the
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heap instead of in the program's data segment.
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<p>When generating code for shared libraries, <samp><span class="option">-fpic</span></samp> implies
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<samp><span class="option">-msmall-data</span></samp> and <samp><span class="option">-fPIC</span></samp> implies <samp><span class="option">-mlarge-data</span></samp>.
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<br><dt><code>-msmall-text</code><dt><code>-mlarge-text</code><dd><a name="index-msmall_002dtext-1628"></a><a name="index-mlarge_002dtext-1629"></a>When <samp><span class="option">-msmall-text</span></samp> is used, the compiler assumes that the
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code of the entire program (or shared library) fits in 4MB, and is
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thus reachable with a branch instruction. When <samp><span class="option">-msmall-data</span></samp>
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is used, the compiler can assume that all local symbols share the
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same <code>$gp</code> value, and thus reduce the number of instructions
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required for a function call from 4 to 1.
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<p>The default is <samp><span class="option">-mlarge-text</span></samp>.
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<br><dt><code>-mcpu=</code><var>cpu_type</var><dd><a name="index-mcpu-1630"></a>Set the instruction set and instruction scheduling parameters for
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machine type <var>cpu_type</var>. You can specify either the ‘<samp><span class="samp">EV</span></samp>’
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style name or the corresponding chip number. GCC supports scheduling
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parameters for the EV4, EV5 and EV6 family of processors and
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chooses the default values for the instruction set from the processor
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you specify. If you do not specify a processor type, GCC defaults
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to the processor on which the compiler was built.
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<p>Supported values for <var>cpu_type</var> are
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<dl>
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<dt>‘<samp><span class="samp">ev4</span></samp>’<dt>‘<samp><span class="samp">ev45</span></samp>’<dt>‘<samp><span class="samp">21064</span></samp>’<dd>Schedules as an EV4 and has no instruction set extensions.
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<br><dt>‘<samp><span class="samp">ev5</span></samp>’<dt>‘<samp><span class="samp">21164</span></samp>’<dd>Schedules as an EV5 and has no instruction set extensions.
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<br><dt>‘<samp><span class="samp">ev56</span></samp>’<dt>‘<samp><span class="samp">21164a</span></samp>’<dd>Schedules as an EV5 and supports the BWX extension.
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<br><dt>‘<samp><span class="samp">pca56</span></samp>’<dt>‘<samp><span class="samp">21164pc</span></samp>’<dt>‘<samp><span class="samp">21164PC</span></samp>’<dd>Schedules as an EV5 and supports the BWX and MAX extensions.
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<br><dt>‘<samp><span class="samp">ev6</span></samp>’<dt>‘<samp><span class="samp">21264</span></samp>’<dd>Schedules as an EV6 and supports the BWX, FIX, and MAX extensions.
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<br><dt>‘<samp><span class="samp">ev67</span></samp>’<dt>‘<samp><span class="samp">21264a</span></samp>’<dd>Schedules as an EV6 and supports the BWX, CIX, FIX, and MAX extensions.
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</dl>
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<p>Native toolchains also support the value ‘<samp><span class="samp">native</span></samp>’,
|
||
|
|
which selects the best architecture option for the host processor.
|
||
|
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<samp><span class="option">-mcpu=native</span></samp> has no effect if GCC does not recognize
|
||
|
|
the processor.
|
||
|
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|
||
|
|
<br><dt><code>-mtune=</code><var>cpu_type</var><dd><a name="index-mtune-1631"></a>Set only the instruction scheduling parameters for machine type
|
||
|
|
<var>cpu_type</var>. The instruction set is not changed.
|
||
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|
||
|
|
<p>Native toolchains also support the value ‘<samp><span class="samp">native</span></samp>’,
|
||
|
|
which selects the best architecture option for the host processor.
|
||
|
|
<samp><span class="option">-mtune=native</span></samp> has no effect if GCC does not recognize
|
||
|
|
the processor.
|
||
|
|
|
||
|
|
<br><dt><code>-mmemory-latency=</code><var>time</var><dd><a name="index-mmemory_002dlatency-1632"></a>Sets the latency the scheduler should assume for typical memory
|
||
|
|
references as seen by the application. This number is highly
|
||
|
|
dependent on the memory access patterns used by the application
|
||
|
|
and the size of the external cache on the machine.
|
||
|
|
|
||
|
|
<p>Valid options for <var>time</var> are
|
||
|
|
|
||
|
|
<dl>
|
||
|
|
<dt>‘<samp><var>number</var></samp>’<dd>A decimal number representing clock cycles.
|
||
|
|
|
||
|
|
<br><dt>‘<samp><span class="samp">L1</span></samp>’<dt>‘<samp><span class="samp">L2</span></samp>’<dt>‘<samp><span class="samp">L3</span></samp>’<dt>‘<samp><span class="samp">main</span></samp>’<dd>The compiler contains estimates of the number of clock cycles for
|
||
|
|
“typical” EV4 & EV5 hardware for the Level 1, 2 & 3 caches
|
||
|
|
(also called Dcache, Scache, and Bcache), as well as to main memory.
|
||
|
|
Note that L3 is only valid for EV5.
|
||
|
|
|
||
|
|
</dl>
|
||
|
|
</dl>
|
||
|
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|
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|
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</body></html>
|
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