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176 lines
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176 lines
11 KiB
HTML
4 years ago
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<head>
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<title>AArch64 Options - Using the GNU Compiler Collection (GCC)</title>
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<meta name="description" content="Using the GNU Compiler Collection (GCC)">
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<link title="Top" rel="start" href="index.html#Top">
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<link rel="up" href="Submodel-Options.html#Submodel-Options" title="Submodel Options">
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<link rel="next" href="Adapteva-Epiphany-Options.html#Adapteva-Epiphany-Options" title="Adapteva Epiphany Options">
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Copyright (C) 1988-2015 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.3 or
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Invariant Sections being ``Funding Free Software'', the Front-Cover
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(a) The FSF's Front-Cover Text is:
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A GNU Manual
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</head>
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<body>
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<div class="node">
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<a name="AArch64-Options"></a>
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<p>
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Next: <a rel="next" accesskey="n" href="Adapteva-Epiphany-Options.html#Adapteva-Epiphany-Options">Adapteva Epiphany Options</a>,
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Up: <a rel="up" accesskey="u" href="Submodel-Options.html#Submodel-Options">Submodel Options</a>
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<hr>
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</div>
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<h4 class="subsection">3.17.1 AArch64 Options</h4>
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<p><a name="index-AArch64-Options-1269"></a>
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These options are defined for AArch64 implementations:
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<dl>
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<dt><code>-mabi=</code><var>name</var><dd><a name="index-mabi-1270"></a>Generate code for the specified data model. Permissible values
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are ‘<samp><span class="samp">ilp32</span></samp>’ for SysV-like data model where int, long int and pointer
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are 32-bit, and ‘<samp><span class="samp">lp64</span></samp>’ for SysV-like data model where int is 32-bit,
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but long int and pointer are 64-bit.
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<p>The default depends on the specific target configuration. Note that
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the LP64 and ILP32 ABIs are not link-compatible; you must compile your
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entire program with the same ABI, and link with a compatible set of libraries.
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<br><dt><code>-mbig-endian</code><dd><a name="index-mbig_002dendian-1271"></a>Generate big-endian code. This is the default when GCC is configured for an
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‘<samp><span class="samp">aarch64_be-*-*</span></samp>’ target.
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<br><dt><code>-mgeneral-regs-only</code><dd><a name="index-mgeneral_002dregs_002donly-1272"></a>Generate code which uses only the general registers.
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<br><dt><code>-mlittle-endian</code><dd><a name="index-mlittle_002dendian-1273"></a>Generate little-endian code. This is the default when GCC is configured for an
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‘<samp><span class="samp">aarch64-*-*</span></samp>’ but not an ‘<samp><span class="samp">aarch64_be-*-*</span></samp>’ target.
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<br><dt><code>-mcmodel=tiny</code><dd><a name="index-mcmodel_003dtiny-1274"></a>Generate code for the tiny code model. The program and its statically defined
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symbols must be within 1GB of each other. Pointers are 64 bits. Programs can
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be statically or dynamically linked. This model is not fully implemented and
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mostly treated as ‘<samp><span class="samp">small</span></samp>’.
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<br><dt><code>-mcmodel=small</code><dd><a name="index-mcmodel_003dsmall-1275"></a>Generate code for the small code model. The program and its statically defined
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symbols must be within 4GB of each other. Pointers are 64 bits. Programs can
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be statically or dynamically linked. This is the default code model.
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<br><dt><code>-mcmodel=large</code><dd><a name="index-mcmodel_003dlarge-1276"></a>Generate code for the large code model. This makes no assumptions about
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addresses and sizes of sections. Pointers are 64 bits. Programs can be
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statically linked only.
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<br><dt><code>-mstrict-align</code><dd><a name="index-mstrict_002dalign-1277"></a>Do not assume that unaligned memory references are handled by the system.
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<br><dt><code>-momit-leaf-frame-pointer</code><dt><code>-mno-omit-leaf-frame-pointer</code><dd><a name="index-momit_002dleaf_002dframe_002dpointer-1278"></a><a name="index-mno_002domit_002dleaf_002dframe_002dpointer-1279"></a>Omit or keep the frame pointer in leaf functions. The former behaviour is the
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default.
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<br><dt><code>-mtls-dialect=desc</code><dd><a name="index-mtls_002ddialect_003ddesc-1280"></a>Use TLS descriptors as the thread-local storage mechanism for dynamic accesses
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of TLS variables. This is the default.
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<br><dt><code>-mtls-dialect=traditional</code><dd><a name="index-mtls_002ddialect_003dtraditional-1281"></a>Use traditional TLS as the thread-local storage mechanism for dynamic accesses
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of TLS variables.
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<br><dt><code>-mfix-cortex-a53-835769</code><dt><code>-mno-fix-cortex-a53-835769</code><dd><a name="index-mfix_002dcortex_002da53_002d835769-1282"></a><a name="index-mno_002dfix_002dcortex_002da53_002d835769-1283"></a>Enable or disable the workaround for the ARM Cortex-A53 erratum number 835769.
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This involves inserting a NOP instruction between memory instructions and
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64-bit integer multiply-accumulate instructions.
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<br><dt><code>-mfix-cortex-a53-843419</code><dt><code>-mno-fix-cortex-a53-843419</code><dd><a name="index-mfix_002dcortex_002da53_002d843419-1284"></a><a name="index-mno_002dfix_002dcortex_002da53_002d843419-1285"></a>Enable or disable the workaround for the ARM Cortex-A53 erratum number 843419.
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This erratum workaround is made at link time and this will only pass the
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corresponding flag to the linker.
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<br><dt><code>-march=</code><var>name</var><dd><a name="index-march-1286"></a>Specify the name of the target architecture, optionally suffixed by one or
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more feature modifiers. This option has the form
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<samp><span class="option">-march=</span><var>arch</var><span class="option">{+[no]</span><var>feature</var><span class="option">}*</span></samp>, where the
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only permissible value for <var>arch</var> is ‘<samp><span class="samp">armv8-a</span></samp>’. The permissible
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values for <var>feature</var> are documented in the sub-section below.
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<p>Where conflicting feature modifiers are specified, the right-most feature is
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used.
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<p>GCC uses this name to determine what kind of instructions it can emit when
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generating assembly code.
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<p>Where <samp><span class="option">-march</span></samp> is specified without either of <samp><span class="option">-mtune</span></samp>
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or <samp><span class="option">-mcpu</span></samp> also being specified, the code is tuned to perform
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well across a range of target processors implementing the target
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architecture.
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<br><dt><code>-mtune=</code><var>name</var><dd><a name="index-mtune-1287"></a>Specify the name of the target processor for which GCC should tune the
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performance of the code. Permissible values for this option are:
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‘<samp><span class="samp">generic</span></samp>’, ‘<samp><span class="samp">cortex-a53</span></samp>’, ‘<samp><span class="samp">cortex-a57</span></samp>’, ‘<samp><span class="samp">cortex-a72</span></samp>’,
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‘<samp><span class="samp">exynos-m1</span></samp>’, ‘<samp><span class="samp">thunderx</span></samp>’, ‘<samp><span class="samp">xgene1</span></samp>’.
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<p>Additionally, this option can specify that GCC should tune the performance
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of the code for a big.LITTLE system. Permissible values for this
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option are: ‘<samp><span class="samp">cortex-a57.cortex-a53</span></samp>’, ‘<samp><span class="samp">cortex-a72.cortex-a53</span></samp>’.
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<p>Where none of <samp><span class="option">-mtune=</span></samp>, <samp><span class="option">-mcpu=</span></samp> or <samp><span class="option">-march=</span></samp>
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are specified, the code is tuned to perform well across a range
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of target processors.
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<p>This option cannot be suffixed by feature modifiers.
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<br><dt><code>-mcpu=</code><var>name</var><dd><a name="index-mcpu-1288"></a>Specify the name of the target processor, optionally suffixed by one or more
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feature modifiers. This option has the form
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<samp><span class="option">-mcpu=</span><var>cpu</var><span class="option">{+[no]</span><var>feature</var><span class="option">}*</span></samp>, where the
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permissible values for <var>cpu</var> are the same as those available for
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<samp><span class="option">-mtune</span></samp>.
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<p>The permissible values for <var>feature</var> are documented in the sub-section
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below.
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<p>Where conflicting feature modifiers are specified, the right-most feature is
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used.
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<p>GCC uses this name to determine what kind of instructions it can emit when
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generating assembly code (as if by <samp><span class="option">-march</span></samp>) and to determine
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the target processor for which to tune for performance (as if
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by <samp><span class="option">-mtune</span></samp>). Where this option is used in conjunction
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with <samp><span class="option">-march</span></samp> or <samp><span class="option">-mtune</span></samp>, those options take precedence
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over the appropriate part of this option.
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</dl>
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<h5 class="subsubsection">3.17.1.1 <samp><span class="option">-march</span></samp> and <samp><span class="option">-mcpu</span></samp> Feature Modifiers</h5>
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<p><a name="index-g_t_0040option_007b_002dmarch_007d-feature-modifiers-1289"></a><a name="index-g_t_0040option_007b_002dmcpu_007d-feature-modifiers-1290"></a>Feature modifiers used with <samp><span class="option">-march</span></samp> and <samp><span class="option">-mcpu</span></samp> can be one
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the following:
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<dl>
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<dt>‘<samp><span class="samp">crc</span></samp>’<dd>Enable CRC extension.
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<br><dt>‘<samp><span class="samp">crypto</span></samp>’<dd>Enable Crypto extension. This implies Advanced SIMD is enabled.
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<br><dt>‘<samp><span class="samp">fp</span></samp>’<dd>Enable floating-point instructions.
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<br><dt>‘<samp><span class="samp">simd</span></samp>’<dd>Enable Advanced SIMD instructions. This implies floating-point instructions
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are enabled. This is the default for all current possible values for options
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<samp><span class="option">-march</span></samp> and <samp><span class="option">-mcpu=</span></samp>.
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</dl>
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</body></html>
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