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102 lines
4.7 KiB
HTML
102 lines
4.7 KiB
HTML
4 years ago
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<html lang="en">
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<title>ARM Opcodes - Using as</title>
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<meta name="description" content="Using as">
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<meta name="generator" content="makeinfo 4.13">
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<link title="Top" rel="start" href="index.html#Top">
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<link rel="up" href="ARM_002dDependent.html#ARM_002dDependent" title="ARM-Dependent">
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<link rel="prev" href="ARM-Directives.html#ARM-Directives" title="ARM Directives">
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<link rel="next" href="ARM-Mapping-Symbols.html#ARM-Mapping-Symbols" title="ARM Mapping Symbols">
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<link href="http://www.gnu.org/software/texinfo/" rel="generator-home" title="Texinfo Homepage">
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<!--
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This file documents the GNU Assembler "as".
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Copyright (C) 1991-2015 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.3
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or any later version published by the Free Software Foundation;
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with no Invariant Sections, with no Front-Cover Texts, and with no
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Back-Cover Texts. A copy of the license is included in the
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section entitled ``GNU Free Documentation License''.
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--></style>
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</head>
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<body>
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<div class="node">
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<a name="ARM-Opcodes"></a>
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<p>
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Next: <a rel="next" accesskey="n" href="ARM-Mapping-Symbols.html#ARM-Mapping-Symbols">ARM Mapping Symbols</a>,
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Previous: <a rel="previous" accesskey="p" href="ARM-Directives.html#ARM-Directives">ARM Directives</a>,
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Up: <a rel="up" accesskey="u" href="ARM_002dDependent.html#ARM_002dDependent">ARM-Dependent</a>
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<hr>
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</div>
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<h4 class="subsection">9.4.5 Opcodes</h4>
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<p><a name="index-ARM-opcodes-773"></a><a name="index-opcodes-for-ARM-774"></a><code>as</code> implements all the standard ARM opcodes. It also
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implements several pseudo opcodes, including several synthetic load
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instructions.
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<a name="index-g_t_0040code_007bNOP_007d-pseudo-op_002c-ARM-775"></a>
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<dl><dt><code>NOP</code><dd>
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<pre class="smallexample"> nop
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</pre>
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<p>This pseudo op will always evaluate to a legal ARM instruction that does
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nothing. Currently it will evaluate to MOV r0, r0.
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<p><a name="index-g_t_0040code_007bLDR-reg_002c_003d_003clabel_003e_007d-pseudo-op_002c-ARM-776"></a><br><dt><code>LDR</code><dd>
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<pre class="smallexample"> ldr <register> , = <expression>
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</pre>
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<p>If expression evaluates to a numeric constant then a MOV or MVN
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instruction will be used in place of the LDR instruction, if the
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constant can be generated by either of these instructions. Otherwise
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the constant will be placed into the nearest literal pool (if it not
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already there) and a PC relative LDR instruction will be generated.
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<p><a name="index-g_t_0040code_007bADR-reg_002c_003clabel_003e_007d-pseudo-op_002c-ARM-777"></a><br><dt><code>ADR</code><dd>
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<pre class="smallexample"> adr <register> <label>
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</pre>
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<p>This instruction will load the address of <var>label</var> into the indicated
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register. The instruction will evaluate to a PC relative ADD or SUB
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instruction depending upon where the label is located. If the label is
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out of range, or if it is not defined in the same file (and section) as
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the ADR instruction, then an error will be generated. This instruction
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will not make use of the literal pool.
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<p><a name="index-g_t_0040code_007bADRL-reg_002c_003clabel_003e_007d-pseudo-op_002c-ARM-778"></a><br><dt><code>ADRL</code><dd>
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<pre class="smallexample"> adrl <register> <label>
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</pre>
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<p>This instruction will load the address of <var>label</var> into the indicated
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register. The instruction will evaluate to one or two PC relative ADD
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or SUB instructions depending upon where the label is located. If a
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second instruction is not needed a NOP instruction will be generated in
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its place, so that this instruction is always 8 bytes long.
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<p>If the label is out of range, or if it is not defined in the same file
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(and section) as the ADRL instruction, then an error will be generated.
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This instruction will not make use of the literal pool.
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</dl>
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<p>For information on the ARM or Thumb instruction sets, see <cite>ARM
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Software Development Toolkit Reference Manual</cite>, Advanced RISC Machines
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Ltd.
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</body></html>
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