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145 lines
8.9 KiB
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4 years ago
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<title>M32R-Opts - Using as</title>
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<link title="Top" rel="start" href="index.html#Top">
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<link rel="up" href="M32R_002dDependent.html#M32R_002dDependent" title="M32R-Dependent">
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<link rel="next" href="M32R_002dDirectives.html#M32R_002dDirectives" title="M32R-Directives">
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<link href="http://www.gnu.org/software/texinfo/" rel="generator-home" title="Texinfo Homepage">
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<!--
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This file documents the GNU Assembler "as".
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Copyright (C) 1991-2015 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.3
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or any later version published by the Free Software Foundation;
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with no Invariant Sections, with no Front-Cover Texts, and with no
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Back-Cover Texts. A copy of the license is included in the
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section entitled ``GNU Free Documentation License''.
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</head>
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<body>
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<div class="node">
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<a name="M32R-Opts"></a>
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<a name="M32R_002dOpts"></a>
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<p>
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Next: <a rel="next" accesskey="n" href="M32R_002dDirectives.html#M32R_002dDirectives">M32R-Directives</a>,
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Up: <a rel="up" accesskey="u" href="M32R_002dDependent.html#M32R_002dDependent">M32R-Dependent</a>
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<hr>
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</div>
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<h4 class="subsection">9.22.1 M32R Options</h4>
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<p><a name="index-options_002c-M32R-1284"></a><a name="index-M32R-options-1285"></a>
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The Renease M32R version of <code>as</code> has a few machine
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dependent options:
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<dl>
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<dt><code>-m32rx</code><dd><a name="index-g_t_0040samp_007b_002dm32rx_007d-option_002c-M32RX-1286"></a><a name="index-architecture-options_002c-M32RX-1287"></a><a name="index-M32R-architecture-options-1288"></a><code>as</code> can assemble code for several different members of the
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Renesas M32R family. Normally the default is to assemble code for
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the M32R microprocessor. This option may be used to change the default
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to the M32RX microprocessor, which adds some more instructions to the
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basic M32R instruction set, and some additional parameters to some of
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the original instructions.
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<br><dt><code>-m32r2</code><dd><a name="index-g_t_0040samp_007b_002dm32rx_007d-option_002c-M32R2-1289"></a><a name="index-architecture-options_002c-M32R2-1290"></a><a name="index-M32R-architecture-options-1291"></a>This option changes the target processor to the M32R2
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microprocessor.
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<br><dt><code>-m32r</code><dd><a name="index-g_t_0040samp_007b_002dm32r_007d-option_002c-M32R-1292"></a><a name="index-architecture-options_002c-M32R-1293"></a><a name="index-M32R-architecture-options-1294"></a>This option can be used to restore the assembler's default behaviour of
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assembling for the M32R microprocessor. This can be useful if the
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default has been changed by a previous command line option.
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<br><dt><code>-little</code><dd><a name="index-g_t_0040code_007b_002dlittle_007d-option_002c-M32R-1295"></a>This option tells the assembler to produce little-endian code and
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data. The default is dependent upon how the toolchain was
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configured.
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<br><dt><code>-EL</code><dd><a name="index-g_t_0040code_007b_002dEL_007d-option_002c-M32R-1296"></a>This is a synonym for <em>-little</em>.
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<br><dt><code>-big</code><dd><a name="index-g_t_0040code_007b_002dbig_007d-option_002c-M32R-1297"></a>This option tells the assembler to produce big-endian code and
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data.
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<br><dt><code>-EB</code><dd><a name="index-g_t_0040code_007b_002dEB_007d-option_002c-M32R-1298"></a>This is a synonum for <em>-big</em>.
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<br><dt><code>-KPIC</code><dd><a name="index-g_t_0040code_007b_002dKPIC_007d-option_002c-M32R-1299"></a><a name="index-PIC-code-generation-for-M32R-1300"></a>This option specifies that the output of the assembler should be
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marked as position-independent code (PIC).
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<br><dt><code>-parallel</code><dd><a name="index-g_t_0040code_007b_002dparallel_007d-option_002c-M32RX-1301"></a>This option tells the assembler to attempts to combine two sequential
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instructions into a single, parallel instruction, where it is legal to
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do so.
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<br><dt><code>-no-parallel</code><dd><a name="index-g_t_0040code_007b_002dno_002dparallel_007d-option_002c-M32RX-1302"></a>This option disables a previously enabled <em>-parallel</em> option.
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<br><dt><code>-no-bitinst</code><dd><a name="index-g_t_0040samp_007b_002dno_002dbitinst_007d_002c-M32R2-1303"></a>This option disables the support for the extended bit-field
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instructions provided by the M32R2. If this support needs to be
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re-enabled the <em>-bitinst</em> switch can be used to restore it.
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<br><dt><code>-O</code><dd><a name="index-g_t_0040code_007b_002dO_007d-option_002c-M32RX-1304"></a>This option tells the assembler to attempt to optimize the
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instructions that it produces. This includes filling delay slots and
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converting sequential instructions into parallel ones. This option
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implies <em>-parallel</em>.
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<br><dt><code>-warn-explicit-parallel-conflicts</code><dd><a name="index-g_t_0040samp_007b_002dwarn_002dexplicit_002dparallel_002dconflicts_007d-option_002c-M32RX-1305"></a>Instructs <code>as</code> to produce warning messages when
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questionable parallel instructions are encountered. This option is
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enabled by default, but <code>gcc</code> disables it when it invokes
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<code>as</code> directly. Questionable instructions are those whose
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behaviour would be different if they were executed sequentially. For
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example the code fragment ‘<samp><span class="samp">mv r1, r2 || mv r3, r1</span></samp>’ produces a
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different result from ‘<samp><span class="samp">mv r1, r2 \n mv r3, r1</span></samp>’ since the former
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moves r1 into r3 and then r2 into r1, whereas the later moves r2 into r1
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and r3.
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<br><dt><code>-Wp</code><dd><a name="index-g_t_0040samp_007b_002dWp_007d-option_002c-M32RX-1306"></a>This is a shorter synonym for the <em>-warn-explicit-parallel-conflicts</em>
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option.
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<br><dt><code>-no-warn-explicit-parallel-conflicts</code><dd><a name="index-g_t_0040samp_007b_002dno_002dwarn_002dexplicit_002dparallel_002dconflicts_007d-option_002c-M32RX-1307"></a>Instructs <code>as</code> not to produce warning messages when
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questionable parallel instructions are encountered.
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<br><dt><code>-Wnp</code><dd><a name="index-g_t_0040samp_007b_002dWnp_007d-option_002c-M32RX-1308"></a>This is a shorter synonym for the <em>-no-warn-explicit-parallel-conflicts</em>
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option.
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<br><dt><code>-ignore-parallel-conflicts</code><dd><a name="index-g_t_0040samp_007b_002dignore_002dparallel_002dconflicts_007d-option_002c-M32RX-1309"></a>This option tells the assembler's to stop checking parallel
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instructions for constraint violations. This ability is provided for
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hardware vendors testing chip designs and should not be used under
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normal circumstances.
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<br><dt><code>-no-ignore-parallel-conflicts</code><dd><a name="index-g_t_0040samp_007b_002dno_002dignore_002dparallel_002dconflicts_007d-option_002c-M32RX-1310"></a>This option restores the assembler's default behaviour of checking
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parallel instructions to detect constraint violations.
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<br><dt><code>-Ip</code><dd><a name="index-g_t_0040samp_007b_002dIp_007d-option_002c-M32RX-1311"></a>This is a shorter synonym for the <em>-ignore-parallel-conflicts</em>
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option.
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<br><dt><code>-nIp</code><dd><a name="index-g_t_0040samp_007b_002dnIp_007d-option_002c-M32RX-1312"></a>This is a shorter synonym for the <em>-no-ignore-parallel-conflicts</em>
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option.
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<br><dt><code>-warn-unmatched-high</code><dd><a name="index-g_t_0040samp_007b_002dwarn_002dunmatched_002dhigh_007d-option_002c-M32R-1313"></a>This option tells the assembler to produce a warning message if a
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<code>.high</code> pseudo op is encountered without a matching <code>.low</code>
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pseudo op. The presence of such an unmatched pseudo op usually
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indicates a programming error.
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<br><dt><code>-no-warn-unmatched-high</code><dd><a name="index-g_t_0040samp_007b_002dno_002dwarn_002dunmatched_002dhigh_007d-option_002c-M32R-1314"></a>Disables a previously enabled <em>-warn-unmatched-high</em> option.
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<br><dt><code>-Wuh</code><dd><a name="index-g_t_0040samp_007b_002dWuh_007d-option_002c-M32RX-1315"></a>This is a shorter synonym for the <em>-warn-unmatched-high</em> option.
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<br><dt><code>-Wnuh</code><dd><a name="index-g_t_0040samp_007b_002dWnuh_007d-option_002c-M32RX-1316"></a>This is a shorter synonym for the <em>-no-warn-unmatched-high</em> option.
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</dl>
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</body></html>
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