ePenguin-Software-Framework/toolchains/avr/man/man3/avr_interrupts.3

.TH "<avr/interrupt.h>: Interrupts" 3 "24 Jun 2019" "Version 2.0.0" "avr-libc" \" -*- nroff -*-
.ad l
.nh
.SH NAME
<avr/interrupt.h>: Interrupts \- 
.SS "Global manipulation of the interrupt flag"
 The global interrupt flag is maintained in the I bit of the status register (SREG).
.PP
Handling interrupts frequently requires attention regarding atomic access to objects that could be altered by code running within an interrupt context, see <\fButil/atomic.h\fP>.
.PP
Frequently, interrupts are being disabled for periods of time in order to perform certain operations without being disturbed; see \fBProblems with reordering code\fP for things to be taken into account with respect to compiler optimizations. 
.in +1c
.ti -1c
.RI "#define \fBsei\fP()"
.br
.ti -1c
.RI "#define \fBcli\fP()"
.br
.in -1c
.SS "Macros for writing interrupt handler functions"
 
.in +1c
.ti -1c
.RI "#define \fBISR\fP(vector, attributes)"
.br
.ti -1c
.RI "#define \fBSIGNAL\fP(vector)"
.br
.ti -1c
.RI "#define \fBEMPTY_INTERRUPT\fP(vector)"
.br
.ti -1c
.RI "#define \fBISR_ALIAS\fP(vector, target_vector)"
.br
.ti -1c
.RI "#define \fBreti\fP()"
.br
.ti -1c
.RI "#define \fBBADISR_vect\fP"
.br
.in -1c
.SS "ISR attributes"
 
.in +1c
.ti -1c
.RI "#define \fBISR_BLOCK\fP"
.br
.ti -1c
.RI "#define \fBISR_NOBLOCK\fP"
.br
.ti -1c
.RI "#define \fBISR_NAKED\fP"
.br
.ti -1c
.RI "#define \fBISR_ALIASOF\fP(target_vector)"
.br
.in -1c
.SH "Detailed Description"
.PP 
\fBNote:\fP
.RS 4
This discussion of interrupts was originally taken from Rich Neswold's document. See \fBAcknowledgments\fP.
.RE
.PP
.SS "Introduction to avr-libc's interrupt handling"
.PP
It's nearly impossible to find compilers that agree on how to handle interrupt code. Since the C language tries to stay away from machine dependent details, each compiler writer is forced to design their method of support.
.PP
In the AVR-GCC environment, the vector table is predefined to point to interrupt routines with predetermined names. By using the appropriate name, your routine will be called when the corresponding interrupt occurs. The device library provides a set of default interrupt routines, which will get used if you don't define your own.
.PP
Patching into the vector table is only one part of the problem. The compiler uses, by convention, a set of registers when it's normally executing compiler-generated code. It's important that these registers, as well as the status register, get saved and restored. The extra code needed to do this is enabled by tagging the interrupt function with \fC__attribute__((signal))\fP.
.PP
These details seem to make interrupt routines a little messy, but all these details are handled by the Interrupt API. An interrupt routine is defined with \fBISR()\fP. This macro register and mark the routine as an interrupt handler for the specified peripheral. The following is an example definition of a handler for the ADC interrupt.
.PP
.PP
.nf
#include <avr/interrupt.h>

ISR(ADC_vect)
{
    // user code here
}
.fi
.PP
.PP
Refer to the chapter explaining \fBassembler programming\fP for an explanation about interrupt routines written solely in assembler language.
.PP
.SS "Catch-all interrupt vector"
.PP
If an unexpected interrupt occurs (interrupt is enabled and no handler is installed, which usually indicates a bug), then the default action is to reset the device by jumping to the reset vector. You can override this by supplying a function named \fCBADISR_vect\fP which should be defined with \fBISR()\fP as such. (The name BADISR_vect is actually an alias for __vector_default. The latter must be used inside assembly code in case <\fBavr/interrupt.h\fP> is not included.)
.PP
.PP
.nf
#include <avr/interrupt.h>

ISR(BADISR_vect)
{
    // user code here
}
.fi
.PP
.PP
.SS "Nested interrupts"
.PP
The AVR hardware clears the global interrupt flag in SREG before entering an interrupt vector. Thus, normally interrupts will remain disabled inside the handler until the handler exits, where the RETI instruction (that is emitted by the compiler as part of the normal function epilogue for an interrupt handler) will eventually re-enable further interrupts. For that reason, interrupt handlers normally do not nest. For most interrupt handlers, this is the desired behaviour, for some it is even required in order to prevent infinitely recursive interrupts (like UART interrupts, or level-triggered external interrupts). In rare circumstances though it might be desired to re-enable the global interrupt flag as early as possible in the interrupt handler, in order to not defer any other interrupt more than absolutely needed. This could be done using an \fBsei()\fP instruction right at the beginning of the interrupt handler, but this still leaves few instructions inside the compiler-generated function prologue to run with global interrupts disabled. The compiler can be instructed to insert an SEI instruction right at the beginning of an interrupt handler by declaring the handler the following way:
.PP
 
.PP
.nf
ISR(XXX_vect, ISR_NOBLOCK)
{
  ...
}

.fi
.PP
.PP
where \fCXXX_vect\fP is the name of a valid interrupt vector for the MCU type in question, as explained below.
.PP
.SS "Two vectors sharing the same code"
.PP
In some circumstances, the actions to be taken upon two different interrupts might be completely identical so a single implementation for the ISR would suffice. For example, pin-change interrupts arriving from two different ports could logically signal an event that is independent from the actual port (and thus interrupt vector) where it happened. Sharing interrupt vector code can be accomplished using the \fBISR_ALIASOF()\fP attribute to the ISR macro:
.PP
.PP
.nf
ISR(PCINT0_vect)
{
  ...
  // Code to handle the event.
}

ISR(PCINT1_vect, ISR_ALIASOF(PCINT0_vect));
.fi
.PP
.PP
\fBNote:\fP
.RS 4
There is no body to the aliased ISR.
.RE
.PP
Note that the \fBISR_ALIASOF()\fP feature requires GCC 4.2 or above (or a patched version of GCC 4.1.x). See the documentation of the \fBISR_ALIAS()\fP macro for an implementation which is less elegant but could be applied to all compiler versions.
.PP
.SS "Empty interrupt service routines"
.PP
In rare circumstances, in interrupt vector does not need any code to be implemented at all. The vector must be declared anyway, so when the interrupt triggers it won't execute the BADISR_vect code (which by default restarts the application).
.PP
This could for example be the case for interrupts that are solely enabled for the purpose of getting the controller out of \fBsleep_mode()\fP.
.PP
A handler for such an interrupt vector can be declared using the \fBEMPTY_INTERRUPT()\fP macro:
.PP
.PP
.nf
EMPTY_INTERRUPT(ADC_vect);
.fi
.PP
.PP
\fBNote:\fP
.RS 4
There is no body to this macro.
.RE
.PP
.SS "Manually defined ISRs"
.PP
In some circumstances, the compiler-generated prologue and epilogue of the ISR might not be optimal for the job, and a manually defined ISR could be considered particularly to speedup the interrupt handling.
.PP
One solution to this could be to implement the entire ISR as manual assembly code in a separate (assembly) file. See \fBCombining C and assembly source files\fP for an example of how to implement it that way.
.PP
Another solution is to still implement the ISR in C language but take over the compiler's job of generating the prologue and epilogue. This can be done using the ISR_NAKED attribute to the \fBISR()\fP macro. Note that the compiler does not generate \fIanything\fP as prologue or epilogue, so the final \fBreti()\fP must be provided by the actual implementation. SREG must be manually saved if the ISR code modifies it, and the compiler-implied assumption of \fC__zero_reg__\fP always being 0 could be wrong (e. g. when interrupting right after of a MUL instruction).
.PP
.PP
.nf
ISR(TIMER1_OVF_vect, ISR_NAKED)
{
  PORTB |= _BV(0);  // results in SBI which does not affect SREG
  reti();
}
.fi
.PP
.PP
.SS "Choosing the vector: Interrupt vector names"
.PP
The interrupt is chosen by supplying one of the symbols in following table.
.PP
There are currently two different styles present for naming the vectors. One form uses names starting with \fCSIG_\fP, followed by a relatively verbose but arbitrarily chosen name describing the interrupt vector. This has been the only available style in avr-libc up to version 1.2.x.
.PP
Starting with avr-libc version 1.4.0, a second style of interrupt vector names has been added, where a short phrase for the vector description is followed by \fC_vect\fP. The short phrase matches the vector name as described in the datasheet of the respective device (and in Atmel's XML files), with spaces replaced by an underscore and other non-alphanumeric characters dropped. Using the suffix \fC_vect\fP is intented to improve portability to other C compilers available for the AVR that use a similar naming convention.
.PP
The historical naming style might become deprecated in a future release, so it is not recommended for new projects.
.PP
\fBNote:\fP
.RS 4
The \fBISR()\fP macro cannot really spell-check the argument passed to them. Thus, by misspelling one of the names below in a call to \fBISR()\fP, a function will be created that, while possibly being usable as an interrupt function, is not actually wired into the interrupt vector table. The compiler will generate a warning if it detects a suspiciously looking name of a \fBISR()\fP function (i.e. one that after macro replacement does not start with '__vector_').
.RE
.PP
  \fBVector name\fP \fBOld vector name\fP \fBDescription\fP \fBApplicable for device\fP 
.PP
ADC_vect SIG_ADC ADC Conversion Complete AT90S2333, AT90S4433, AT90S4434, AT90S8535, AT90PWM216, AT90PWM2B, AT90PWM316, AT90PWM3B, AT90PWM3, AT90PWM2, AT90PWM1, AT90CAN128, AT90CAN32, AT90CAN64, ATmega103, ATmega128, ATmega1284P, ATmega16, ATmega163, ATmega165, ATmega165P, ATmega168P, ATmega169, ATmega169P, ATmega32, ATmega323, ATmega325, ATmega3250, ATmega3250P, ATmega328P, ATmega329, ATmega3290, ATmega3290P, ATmega48P, ATmega64, ATmega645, ATmega6450, ATmega649, ATmega6490, ATmega8, ATmega8535, ATmega88P, ATmega168, ATmega48, ATmega88, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega324P, ATmega164P, ATmega644P, ATmega644, ATtiny13, ATtiny15, ATtiny26, ATtiny43U, ATtiny48, ATtiny24, ATtiny44, ATtiny84, ATtiny45, ATtiny25, ATtiny85, ATtiny261, ATtiny461, ATtiny861, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646  ANALOG_COMP_0_vect SIG_COMPARATOR0 Analog Comparator 0 AT90PWM3, AT90PWM2, AT90PWM1  ANALOG_COMP_1_vect SIG_COMPARATOR1 Analog Comparator 1 AT90PWM3, AT90PWM2, AT90PWM1  ANALOG_COMP_2_vect SIG_COMPARATOR2 Analog Comparator 2 AT90PWM3, AT90PWM2, AT90PWM1  ANALOG_COMP_vect SIG_COMPARATOR Analog Comparator AT90CAN128, AT90CAN32, AT90CAN64, ATmega103, ATmega128, ATmega1284P, ATmega165, ATmega165P, ATmega168P, ATmega169, ATmega169P, ATmega325, ATmega3250, ATmega3250P, ATmega328P, ATmega329, ATmega3290, ATmega3290P, ATmega48P, ATmega64, ATmega645, ATmega6450, ATmega649, ATmega6490, ATmega88P, ATmega168, ATmega48, ATmega88, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega324P, ATmega164P, ATmega644P, ATmega644, AT90USB162, AT90USB82, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646  ANA_COMP_vect SIG_COMPARATOR Analog Comparator AT90S1200, AT90S2313, AT90S2333, AT90S4414, AT90S4433, AT90S4434, AT90S8515, AT90S8535, ATmega16, ATmega161, ATmega162, ATmega163, ATmega32, ATmega323, ATmega8, ATmega8515, ATmega8535, ATtiny11, ATtiny12, ATtiny13, ATtiny15, ATtiny2313, ATtiny26, ATtiny28, ATtiny43U, ATtiny48, ATtiny24, ATtiny44, ATtiny84, ATtiny45, ATtiny25, ATtiny85, ATtiny261, ATtiny461, ATtiny861  CANIT_vect SIG_CAN_INTERRUPT1 CAN Transfer Complete or Error AT90CAN128, AT90CAN32, AT90CAN64  EEPROM_READY_vect SIG_EEPROM_READY, SIG_EE_READY ATtiny2313  EE_RDY_vect SIG_EEPROM_READY EEPROM Ready AT90S2333, AT90S4433, AT90S4434, AT90S8535, ATmega16, ATmega161, ATmega162, ATmega163, ATmega32, ATmega323, ATmega8, ATmega8515, ATmega8535, ATtiny12, ATtiny13, ATtiny15, ATtiny26, ATtiny43U, ATtiny48, ATtiny24, ATtiny44, ATtiny84, ATtiny45, ATtiny25, ATtiny85, ATtiny261, ATtiny461, ATtiny861  EE_READY_vect SIG_EEPROM_READY EEPROM Ready AT90PWM3, AT90PWM2, AT90PWM1, AT90CAN128, AT90CAN32, AT90CAN64, ATmega103, ATmega128, ATmega1284P, ATmega165, ATmega165P, ATmega168P, ATmega169, ATmega169P, ATmega325, ATmega3250, ATmega3250P, ATmega328P, ATmega329, ATmega3290, ATmega3290P, ATmega32HVB, ATmega406, ATmega48P, ATmega64, ATmega645, ATmega6450, ATmega649, ATmega6490, ATmega88P, ATmega168, ATmega48, ATmega88, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega324P, ATmega164P, ATmega644P, ATmega644, ATmega16HVA, AT90USB162, AT90USB82, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646  EXT_INT0_vect SIG_INTERRUPT0 External Interrupt Request 0 ATtiny24, ATtiny44, ATtiny84  INT0_vect SIG_INTERRUPT0 External Interrupt 0 AT90S1200, AT90S2313, AT90S2323, AT90S2333, AT90S2343, AT90S4414, AT90S4433, AT90S4434, AT90S8515, AT90S8535, AT90PWM216, AT90PWM2B, AT90PWM316, AT90PWM3B, AT90PWM3, AT90PWM2, AT90PWM1, AT90CAN128, AT90CAN32, AT90CAN64, ATmega103, ATmega128, ATmega1284P, ATmega16, ATmega161, ATmega162, ATmega163, ATmega165, ATmega165P, ATmega168P, ATmega169, ATmega169P, ATmega32, ATmega323, ATmega325, ATmega3250, ATmega3250P, ATmega328P, ATmega329, ATmega3290, ATmega3290P, ATmega32HVB, ATmega406, ATmega48P, ATmega64, ATmega645, ATmega6450, ATmega649, ATmega6490, ATmega8, ATmega8515, ATmega8535, ATmega88P, ATmega168, ATmega48, ATmega88, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega324P, ATmega164P, ATmega644P, ATmega644, ATmega16HVA, ATtiny11, ATtiny12, ATtiny13, ATtiny15, ATtiny
.SH "Define Documentation"
.PP 
.SS "#define BADISR_vect".PP
.nf
 #include <avr/interrupt.h> 
.fi
.PP
.PP
This is a vector which is aliased to __vector_default, the vector executed when an ISR fires with no accompanying ISR handler. This may be used along with the \fBISR()\fP macro to create a catch-all for undefined but used ISRs for debugging purposes. 
.SS "#define cli()"Disables all interrupts by clearing the global interrupt mask. This function actually compiles into a single line of assembly, so there is no function call overhead. However, the macro also implies a \fImemory barrier\fP which can cause additional loss of optimization.
.PP
In order to implement atomic access to multi-byte objects, consider using the macros from <\fButil/atomic.h\fP>, rather than implementing them manually with \fBcli()\fP and \fBsei()\fP. 
.SS "#define EMPTY_INTERRUPT(vector)"Defines an empty interrupt handler function. This will not generate any prolog or epilog code and will only return from the ISR. Do not define a function body as this will define it for you. Example: 
.PP
.nf
 EMPTY_INTERRUPT(ADC_vect);

.fi
.PP
 
.SS "#define ISR(vector, attributes)"Introduces an interrupt handler function (interrupt service routine) that runs with global interrupts initially disabled by default with no attributes specified.
.PP
The attributes are optional and alter the behaviour and resultant generated code of the interrupt routine. Multiple attributes may be used for a single function, with a space seperating each attribute.
.PP
Valid attributes are ISR_BLOCK, ISR_NOBLOCK, ISR_NAKED and \fBISR_ALIASOF(vect)\fP.
.PP
\fCvector\fP must be one of the interrupt vector names that are valid for the particular MCU type. 
.SS "#define ISR_ALIAS(vector, target_vector)"Aliases a given vector to another one in the same manner as the ISR_ALIASOF attribute for the \fBISR()\fP macro. Unlike the ISR_ALIASOF attribute macro however, this is compatible for all versions of GCC rather than just GCC version 4.2 onwards.
.PP
\fBNote:\fP
.RS 4
This macro creates a trampoline function for the aliased macro. This will result in a two cycle penalty for the aliased vector compared to the ISR the vector is aliased to, due to the JMP/RJMP opcode used.
.RE
.PP
\fBDeprecated\fP
.RS 4
For new code, the use of ISR(..., ISR_ALIASOF(...)) is recommended.
.RE
.PP
Example: 
.PP
.nf
    ISR(INT0_vect)
    {
        PORTB = 42;
    }

    ISR_ALIAS(INT1_vect, INT0_vect);

.fi
.PP
 
.SS "#define ISR_ALIASOF(target_vector)"The ISR is linked to another ISR, specified by the vect parameter. This is compatible with GCC 4.2 and greater only.
.PP
Use this attribute in the attributes parameter of the ISR macro. 
.SS "#define ISR_BLOCK"Identical to an ISR with no attributes specified. Global interrupts are initially disabled by the AVR hardware when entering the ISR, without the compiler modifying this state.
.PP
Use this attribute in the attributes parameter of the ISR macro. 
.SS "#define ISR_NAKED"ISR is created with no prologue or epilogue code. The user code is responsible for preservation of the machine state including the SREG register, as well as placing a \fBreti()\fP at the end of the interrupt routine.
.PP
Use this attribute in the attributes parameter of the ISR macro. 
.SS "#define ISR_NOBLOCK"ISR runs with global interrupts initially enabled. The interrupt enable flag is activated by the compiler as early as possible within the ISR to ensure minimal processing delay for nested interrupts.
.PP
This may be used to create nested ISRs, however care should be taken to avoid stack overflows, or to avoid infinitely entering the ISR for those cases where the AVR hardware does not clear the respective interrupt flag before entering the ISR.
.PP
Use this attribute in the attributes parameter of the ISR macro. 
.SS "#define reti()"Returns from an interrupt routine, enabling global interrupts. This should be the last command executed before leaving an ISR defined with the ISR_NAKED attribute.
.PP
This macro actually compiles into a single line of assembly, so there is no function call overhead. 
.SS "#define sei()"Enables interrupts by setting the global interrupt mask. This function actually compiles into a single line of assembly, so there is no function call overhead. However, the macro also implies a \fImemory barrier\fP which can cause additional loss of optimization.
.PP
In order to implement atomic access to multi-byte objects, consider using the macros from <\fButil/atomic.h\fP>, rather than implementing them manually with \fBcli()\fP and \fBsei()\fP. 
.SS "#define SIGNAL(vector)"Introduces an interrupt handler function that runs with global interrupts initially disabled.
.PP
This is the same as the ISR macro without optional attributes. 
.PP
\fBDeprecated\fP
.RS 4
Do not use \fBSIGNAL()\fP in new code. Use \fBISR()\fP instead. 
.RE
.PP

.SH "Author"
.PP 
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