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1726 lines
79 KiB
HTML
4 years ago
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<html lang="en">
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<head>
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<title>Machine Constraints - GNU Compiler Collection (GCC) Internals</title>
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<meta http-equiv="Content-Type" content="text/html">
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<meta name="description" content="GNU Compiler Collection (GCC) Internals">
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<meta name="generator" content="makeinfo 4.13">
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<link title="Top" rel="start" href="index.html#Top">
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<link rel="up" href="Constraints.html#Constraints" title="Constraints">
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<link rel="prev" href="Modifiers.html#Modifiers" title="Modifiers">
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<link rel="next" href="Disable-Insn-Alternatives.html#Disable-Insn-Alternatives" title="Disable Insn Alternatives">
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<link href="http://www.gnu.org/software/texinfo/" rel="generator-home" title="Texinfo Homepage">
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<!--
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Copyright (C) 1988-2015 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.3 or
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any later version published by the Free Software Foundation; with the
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Invariant Sections being ``Funding Free Software'', the Front-Cover
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Texts being (a) (see below), and with the Back-Cover Texts being (b)
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(see below). A copy of the license is included in the section entitled
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``GNU Free Documentation License''.
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(a) The FSF's Front-Cover Text is:
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A GNU Manual
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(b) The FSF's Back-Cover Text is:
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You have freedom to copy and modify this GNU Manual, like GNU
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software. Copies published by the Free Software Foundation raise
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funds for GNU development.-->
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--></style>
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</head>
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<body>
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<div class="node">
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<a name="Machine-Constraints"></a>
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<p>
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Next: <a rel="next" accesskey="n" href="Disable-Insn-Alternatives.html#Disable-Insn-Alternatives">Disable Insn Alternatives</a>,
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Previous: <a rel="previous" accesskey="p" href="Modifiers.html#Modifiers">Modifiers</a>,
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Up: <a rel="up" accesskey="u" href="Constraints.html#Constraints">Constraints</a>
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<hr>
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</div>
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<h4 class="subsection">16.8.5 Constraints for Particular Machines</h4>
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<p><a name="index-machine-specific-constraints-3362"></a><a name="index-constraints_002c-machine-specific-3363"></a>
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Whenever possible, you should use the general-purpose constraint letters
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in <code>asm</code> arguments, since they will convey meaning more readily to
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people reading your code. Failing that, use the constraint letters
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that usually have very similar meanings across architectures. The most
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commonly used constraints are ‘<samp><span class="samp">m</span></samp>’ and ‘<samp><span class="samp">r</span></samp>’ (for memory and
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general-purpose registers respectively; see <a href="Simple-Constraints.html#Simple-Constraints">Simple Constraints</a>), and
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‘<samp><span class="samp">I</span></samp>’, usually the letter indicating the most common
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immediate-constant format.
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<p>Each architecture defines additional constraints. These constraints
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are used by the compiler itself for instruction generation, as well as
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for <code>asm</code> statements; therefore, some of the constraints are not
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particularly useful for <code>asm</code>. Here is a summary of some of the
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machine-dependent constraints available on some particular machines;
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it includes both constraints that are useful for <code>asm</code> and
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constraints that aren't. The compiler source file mentioned in the
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table heading for each architecture is the definitive reference for
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the meanings of that architecture's constraints.
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<!-- Please keep this table alphabetized by target! -->
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<dl>
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<dt><em>AArch64 family—</em><samp><span class="file">config/aarch64/constraints.md</span></samp><dd>
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<dl>
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<dt><code>k</code><dd>The stack pointer register (<code>SP</code>)
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<br><dt><code>w</code><dd>Floating point or SIMD vector register
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<br><dt><code>I</code><dd>Integer constant that is valid as an immediate operand in an <code>ADD</code>
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instruction
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<br><dt><code>J</code><dd>Integer constant that is valid as an immediate operand in a <code>SUB</code>
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instruction (once negated)
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<br><dt><code>K</code><dd>Integer constant that can be used with a 32-bit logical instruction
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<br><dt><code>L</code><dd>Integer constant that can be used with a 64-bit logical instruction
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<br><dt><code>M</code><dd>Integer constant that is valid as an immediate operand in a 32-bit <code>MOV</code>
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pseudo instruction. The <code>MOV</code> may be assembled to one of several different
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machine instructions depending on the value
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<br><dt><code>N</code><dd>Integer constant that is valid as an immediate operand in a 64-bit <code>MOV</code>
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pseudo instruction
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<br><dt><code>S</code><dd>An absolute symbolic address or a label reference
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<br><dt><code>Y</code><dd>Floating point constant zero
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<br><dt><code>Z</code><dd>Integer constant zero
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<br><dt><code>Ush</code><dd>The high part (bits 12 and upwards) of the pc-relative address of a symbol
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within 4GB of the instruction
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<br><dt><code>Q</code><dd>A memory address which uses a single base register with no offset
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<br><dt><code>Ump</code><dd>A memory address suitable for a load/store pair instruction in SI, DI, SF and
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DF modes
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</dl>
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<br><dt><em>ARC —</em><samp><span class="file">config/arc/constraints.md</span></samp><dd>
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<dl>
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<dt><code>q</code><dd>Registers usable in ARCompact 16-bit instructions: <code>r0</code>-<code>r3</code>,
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<code>r12</code>-<code>r15</code>. This constraint can only match when the <samp><span class="option">-mq</span></samp>
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option is in effect.
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<br><dt><code>e</code><dd>Registers usable as base-regs of memory addresses in ARCompact 16-bit memory
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instructions: <code>r0</code>-<code>r3</code>, <code>r12</code>-<code>r15</code>, <code>sp</code>.
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This constraint can only match when the <samp><span class="option">-mq</span></samp>
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option is in effect.
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<br><dt><code>D</code><dd>ARC FPX (dpfp) 64-bit registers. <code>D0</code>, <code>D1</code>.
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<br><dt><code>I</code><dd>A signed 12-bit integer constant.
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<br><dt><code>Cal</code><dd>constant for arithmetic/logical operations. This might be any constant
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that can be put into a long immediate by the assmbler or linker without
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involving a PIC relocation.
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<br><dt><code>K</code><dd>A 3-bit unsigned integer constant.
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<br><dt><code>L</code><dd>A 6-bit unsigned integer constant.
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<br><dt><code>CnL</code><dd>One's complement of a 6-bit unsigned integer constant.
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<br><dt><code>CmL</code><dd>Two's complement of a 6-bit unsigned integer constant.
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<br><dt><code>M</code><dd>A 5-bit unsigned integer constant.
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<br><dt><code>O</code><dd>A 7-bit unsigned integer constant.
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<br><dt><code>P</code><dd>A 8-bit unsigned integer constant.
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<br><dt><code>H</code><dd>Any const_double value.
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</dl>
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<br><dt><em>ARM family—</em><samp><span class="file">config/arm/constraints.md</span></samp><dd>
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<dl>
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<dt><code>h</code><dd>In Thumb state, the core registers <code>r8</code>-<code>r15</code>.
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<br><dt><code>k</code><dd>The stack pointer register.
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<br><dt><code>l</code><dd>In Thumb State the core registers <code>r0</code>-<code>r7</code>. In ARM state this
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is an alias for the <code>r</code> constraint.
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<br><dt><code>t</code><dd>VFP floating-point registers <code>s0</code>-<code>s31</code>. Used for 32 bit values.
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<br><dt><code>w</code><dd>VFP floating-point registers <code>d0</code>-<code>d31</code> and the appropriate
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subset <code>d0</code>-<code>d15</code> based on command line options.
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Used for 64 bit values only. Not valid for Thumb1.
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<br><dt><code>y</code><dd>The iWMMX co-processor registers.
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<br><dt><code>z</code><dd>The iWMMX GR registers.
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<br><dt><code>G</code><dd>The floating-point constant 0.0
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<br><dt><code>I</code><dd>Integer that is valid as an immediate operand in a data processing
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instruction. That is, an integer in the range 0 to 255 rotated by a
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multiple of 2
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<br><dt><code>J</code><dd>Integer in the range −4095 to 4095
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<br><dt><code>K</code><dd>Integer that satisfies constraint ‘<samp><span class="samp">I</span></samp>’ when inverted (ones complement)
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<br><dt><code>L</code><dd>Integer that satisfies constraint ‘<samp><span class="samp">I</span></samp>’ when negated (twos complement)
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<br><dt><code>M</code><dd>Integer in the range 0 to 32
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<br><dt><code>Q</code><dd>A memory reference where the exact address is in a single register
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(`‘<samp><span class="samp">m</span></samp>’' is preferable for <code>asm</code> statements)
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<br><dt><code>R</code><dd>An item in the constant pool
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<br><dt><code>S</code><dd>A symbol in the text segment of the current file
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<br><dt><code>Uv</code><dd>A memory reference suitable for VFP load/store insns (reg+constant offset)
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<br><dt><code>Uy</code><dd>A memory reference suitable for iWMMXt load/store instructions.
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<br><dt><code>Uq</code><dd>A memory reference suitable for the ARMv4 ldrsb instruction.
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</dl>
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<br><dt><em>AVR family—</em><samp><span class="file">config/avr/constraints.md</span></samp><dd>
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<dl>
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<dt><code>l</code><dd>Registers from r0 to r15
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<br><dt><code>a</code><dd>Registers from r16 to r23
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<br><dt><code>d</code><dd>Registers from r16 to r31
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<br><dt><code>w</code><dd>Registers from r24 to r31. These registers can be used in ‘<samp><span class="samp">adiw</span></samp>’ command
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<br><dt><code>e</code><dd>Pointer register (r26–r31)
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<br><dt><code>b</code><dd>Base pointer register (r28–r31)
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<br><dt><code>q</code><dd>Stack pointer register (SPH:SPL)
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<br><dt><code>t</code><dd>Temporary register r0
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<br><dt><code>x</code><dd>Register pair X (r27:r26)
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<br><dt><code>y</code><dd>Register pair Y (r29:r28)
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<br><dt><code>z</code><dd>Register pair Z (r31:r30)
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<br><dt><code>I</code><dd>Constant greater than −1, less than 64
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<br><dt><code>J</code><dd>Constant greater than −64, less than 1
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<br><dt><code>K</code><dd>Constant integer 2
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<br><dt><code>L</code><dd>Constant integer 0
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<br><dt><code>M</code><dd>Constant that fits in 8 bits
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<br><dt><code>N</code><dd>Constant integer −1
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<br><dt><code>O</code><dd>Constant integer 8, 16, or 24
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<br><dt><code>P</code><dd>Constant integer 1
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<br><dt><code>G</code><dd>A floating point constant 0.0
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<br><dt><code>Q</code><dd>A memory address based on Y or Z pointer with displacement.
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</dl>
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<br><dt><em>Blackfin family—</em><samp><span class="file">config/bfin/constraints.md</span></samp><dd>
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<dl>
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<dt><code>a</code><dd>P register
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<br><dt><code>d</code><dd>D register
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<br><dt><code>z</code><dd>A call clobbered P register.
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<br><dt><code>q</code><var>n</var><dd>A single register. If <var>n</var> is in the range 0 to 7, the corresponding D
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register. If it is <code>A</code>, then the register P0.
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<br><dt><code>D</code><dd>Even-numbered D register
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<br><dt><code>W</code><dd>Odd-numbered D register
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<br><dt><code>e</code><dd>Accumulator register.
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<br><dt><code>A</code><dd>Even-numbered accumulator register.
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<br><dt><code>B</code><dd>Odd-numbered accumulator register.
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<br><dt><code>b</code><dd>I register
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<br><dt><code>v</code><dd>B register
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<br><dt><code>f</code><dd>M register
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<br><dt><code>c</code><dd>Registers used for circular buffering, i.e. I, B, or L registers.
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<br><dt><code>C</code><dd>The CC register.
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<br><dt><code>t</code><dd>LT0 or LT1.
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<br><dt><code>k</code><dd>LC0 or LC1.
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<br><dt><code>u</code><dd>LB0 or LB1.
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<br><dt><code>x</code><dd>Any D, P, B, M, I or L register.
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<br><dt><code>y</code><dd>Additional registers typically used only in prologues and epilogues: RETS,
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RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP.
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<br><dt><code>w</code><dd>Any register except accumulators or CC.
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<br><dt><code>Ksh</code><dd>Signed 16 bit integer (in the range −32768 to 32767)
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<br><dt><code>Kuh</code><dd>Unsigned 16 bit integer (in the range 0 to 65535)
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<br><dt><code>Ks7</code><dd>Signed 7 bit integer (in the range −64 to 63)
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<br><dt><code>Ku7</code><dd>Unsigned 7 bit integer (in the range 0 to 127)
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<br><dt><code>Ku5</code><dd>Unsigned 5 bit integer (in the range 0 to 31)
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<br><dt><code>Ks4</code><dd>Signed 4 bit integer (in the range −8 to 7)
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<br><dt><code>Ks3</code><dd>Signed 3 bit integer (in the range −3 to 4)
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<br><dt><code>Ku3</code><dd>Unsigned 3 bit integer (in the range 0 to 7)
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<br><dt><code>P</code><var>n</var><dd>Constant <var>n</var>, where <var>n</var> is a single-digit constant in the range 0 to 4.
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<br><dt><code>PA</code><dd>An integer equal to one of the MACFLAG_XXX constants that is suitable for
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use with either accumulator.
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|
||
|
|
<br><dt><code>PB</code><dd>An integer equal to one of the MACFLAG_XXX constants that is suitable for
|
||
|
|
use only with accumulator A1.
|
||
|
|
|
||
|
|
<br><dt><code>M1</code><dd>Constant 255.
|
||
|
|
|
||
|
|
<br><dt><code>M2</code><dd>Constant 65535.
|
||
|
|
|
||
|
|
<br><dt><code>J</code><dd>An integer constant with exactly a single bit set.
|
||
|
|
|
||
|
|
<br><dt><code>L</code><dd>An integer constant with all bits set except exactly one.
|
||
|
|
|
||
|
|
<br><dt><code>H</code>
|
||
|
|
<br><dt><code>Q</code><dd>Any SYMBOL_REF.
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<br><dt><em>CR16 Architecture—</em><samp><span class="file">config/cr16/cr16.h</span></samp><dd>
|
||
|
|
<dl>
|
||
|
|
<dt><code>b</code><dd>Registers from r0 to r14 (registers without stack pointer)
|
||
|
|
|
||
|
|
<br><dt><code>t</code><dd>Register from r0 to r11 (all 16-bit registers)
|
||
|
|
|
||
|
|
<br><dt><code>p</code><dd>Register from r12 to r15 (all 32-bit registers)
|
||
|
|
|
||
|
|
<br><dt><code>I</code><dd>Signed constant that fits in 4 bits
|
||
|
|
|
||
|
|
<br><dt><code>J</code><dd>Signed constant that fits in 5 bits
|
||
|
|
|
||
|
|
<br><dt><code>K</code><dd>Signed constant that fits in 6 bits
|
||
|
|
|
||
|
|
<br><dt><code>L</code><dd>Unsigned constant that fits in 4 bits
|
||
|
|
|
||
|
|
<br><dt><code>M</code><dd>Signed constant that fits in 32 bits
|
||
|
|
|
||
|
|
<br><dt><code>N</code><dd>Check for 64 bits wide constants for add/sub instructions
|
||
|
|
|
||
|
|
<br><dt><code>G</code><dd>Floating point constant that is legal for store immediate
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<br><dt><em>Epiphany—</em><samp><span class="file">config/epiphany/constraints.md</span></samp><dd>
|
||
|
|
<dl>
|
||
|
|
<dt><code>U16</code><dd>An unsigned 16-bit constant.
|
||
|
|
|
||
|
|
<br><dt><code>K</code><dd>An unsigned 5-bit constant.
|
||
|
|
|
||
|
|
<br><dt><code>L</code><dd>A signed 11-bit constant.
|
||
|
|
|
||
|
|
<br><dt><code>Cm1</code><dd>A signed 11-bit constant added to −1.
|
||
|
|
Can only match when the <samp><span class="option">-m1reg-</span><var>reg</var></samp> option is active.
|
||
|
|
|
||
|
|
<br><dt><code>Cl1</code><dd>Left-shift of −1, i.e., a bit mask with a block of leading ones, the rest
|
||
|
|
being a block of trailing zeroes.
|
||
|
|
Can only match when the <samp><span class="option">-m1reg-</span><var>reg</var></samp> option is active.
|
||
|
|
|
||
|
|
<br><dt><code>Cr1</code><dd>Right-shift of −1, i.e., a bit mask with a trailing block of ones, the
|
||
|
|
rest being zeroes. Or to put it another way, one less than a power of two.
|
||
|
|
Can only match when the <samp><span class="option">-m1reg-</span><var>reg</var></samp> option is active.
|
||
|
|
|
||
|
|
<br><dt><code>Cal</code><dd>Constant for arithmetic/logical operations.
|
||
|
|
This is like <code>i</code>, except that for position independent code,
|
||
|
|
no symbols / expressions needing relocations are allowed.
|
||
|
|
|
||
|
|
<br><dt><code>Csy</code><dd>Symbolic constant for call/jump instruction.
|
||
|
|
|
||
|
|
<br><dt><code>Rcs</code><dd>The register class usable in short insns. This is a register class
|
||
|
|
constraint, and can thus drive register allocation.
|
||
|
|
This constraint won't match unless <samp><span class="option">-mprefer-short-insn-regs</span></samp> is
|
||
|
|
in effect.
|
||
|
|
|
||
|
|
<br><dt><code>Rsc</code><dd>The the register class of registers that can be used to hold a
|
||
|
|
sibcall call address. I.e., a caller-saved register.
|
||
|
|
|
||
|
|
<br><dt><code>Rct</code><dd>Core control register class.
|
||
|
|
|
||
|
|
<br><dt><code>Rgs</code><dd>The register group usable in short insns.
|
||
|
|
This constraint does not use a register class, so that it only
|
||
|
|
passively matches suitable registers, and doesn't drive register allocation.
|
||
|
|
|
||
|
|
<br><dt><code>Car</code><dd>Constant suitable for the addsi3_r pattern. This is a valid offset
|
||
|
|
For byte, halfword, or word addressing.
|
||
|
|
|
||
|
|
<br><dt><code>Rra</code><dd>Matches the return address if it can be replaced with the link register.
|
||
|
|
|
||
|
|
<br><dt><code>Rcc</code><dd>Matches the integer condition code register.
|
||
|
|
|
||
|
|
<br><dt><code>Sra</code><dd>Matches the return address if it is in a stack slot.
|
||
|
|
|
||
|
|
<br><dt><code>Cfm</code><dd>Matches control register values to switch fp mode, which are encapsulated in
|
||
|
|
<code>UNSPEC_FP_MODE</code>.
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<br><dt><em>FRV—</em><samp><span class="file">config/frv/frv.h</span></samp><dd>
|
||
|
|
<dl>
|
||
|
|
<dt><code>a</code><dd>Register in the class <code>ACC_REGS</code> (<code>acc0</code> to <code>acc7</code>).
|
||
|
|
|
||
|
|
<br><dt><code>b</code><dd>Register in the class <code>EVEN_ACC_REGS</code> (<code>acc0</code> to <code>acc7</code>).
|
||
|
|
|
||
|
|
<br><dt><code>c</code><dd>Register in the class <code>CC_REGS</code> (<code>fcc0</code> to <code>fcc3</code> and
|
||
|
|
<code>icc0</code> to <code>icc3</code>).
|
||
|
|
|
||
|
|
<br><dt><code>d</code><dd>Register in the class <code>GPR_REGS</code> (<code>gr0</code> to <code>gr63</code>).
|
||
|
|
|
||
|
|
<br><dt><code>e</code><dd>Register in the class <code>EVEN_REGS</code> (<code>gr0</code> to <code>gr63</code>).
|
||
|
|
Odd registers are excluded not in the class but through the use of a machine
|
||
|
|
mode larger than 4 bytes.
|
||
|
|
|
||
|
|
<br><dt><code>f</code><dd>Register in the class <code>FPR_REGS</code> (<code>fr0</code> to <code>fr63</code>).
|
||
|
|
|
||
|
|
<br><dt><code>h</code><dd>Register in the class <code>FEVEN_REGS</code> (<code>fr0</code> to <code>fr63</code>).
|
||
|
|
Odd registers are excluded not in the class but through the use of a machine
|
||
|
|
mode larger than 4 bytes.
|
||
|
|
|
||
|
|
<br><dt><code>l</code><dd>Register in the class <code>LR_REG</code> (the <code>lr</code> register).
|
||
|
|
|
||
|
|
<br><dt><code>q</code><dd>Register in the class <code>QUAD_REGS</code> (<code>gr2</code> to <code>gr63</code>).
|
||
|
|
Register numbers not divisible by 4 are excluded not in the class but through
|
||
|
|
the use of a machine mode larger than 8 bytes.
|
||
|
|
|
||
|
|
<br><dt><code>t</code><dd>Register in the class <code>ICC_REGS</code> (<code>icc0</code> to <code>icc3</code>).
|
||
|
|
|
||
|
|
<br><dt><code>u</code><dd>Register in the class <code>FCC_REGS</code> (<code>fcc0</code> to <code>fcc3</code>).
|
||
|
|
|
||
|
|
<br><dt><code>v</code><dd>Register in the class <code>ICR_REGS</code> (<code>cc4</code> to <code>cc7</code>).
|
||
|
|
|
||
|
|
<br><dt><code>w</code><dd>Register in the class <code>FCR_REGS</code> (<code>cc0</code> to <code>cc3</code>).
|
||
|
|
|
||
|
|
<br><dt><code>x</code><dd>Register in the class <code>QUAD_FPR_REGS</code> (<code>fr0</code> to <code>fr63</code>).
|
||
|
|
Register numbers not divisible by 4 are excluded not in the class but through
|
||
|
|
the use of a machine mode larger than 8 bytes.
|
||
|
|
|
||
|
|
<br><dt><code>z</code><dd>Register in the class <code>SPR_REGS</code> (<code>lcr</code> and <code>lr</code>).
|
||
|
|
|
||
|
|
<br><dt><code>A</code><dd>Register in the class <code>QUAD_ACC_REGS</code> (<code>acc0</code> to <code>acc7</code>).
|
||
|
|
|
||
|
|
<br><dt><code>B</code><dd>Register in the class <code>ACCG_REGS</code> (<code>accg0</code> to <code>accg7</code>).
|
||
|
|
|
||
|
|
<br><dt><code>C</code><dd>Register in the class <code>CR_REGS</code> (<code>cc0</code> to <code>cc7</code>).
|
||
|
|
|
||
|
|
<br><dt><code>G</code><dd>Floating point constant zero
|
||
|
|
|
||
|
|
<br><dt><code>I</code><dd>6-bit signed integer constant
|
||
|
|
|
||
|
|
<br><dt><code>J</code><dd>10-bit signed integer constant
|
||
|
|
|
||
|
|
<br><dt><code>L</code><dd>16-bit signed integer constant
|
||
|
|
|
||
|
|
<br><dt><code>M</code><dd>16-bit unsigned integer constant
|
||
|
|
|
||
|
|
<br><dt><code>N</code><dd>12-bit signed integer constant that is negative—i.e. in the
|
||
|
|
range of −2048 to −1
|
||
|
|
|
||
|
|
<br><dt><code>O</code><dd>Constant zero
|
||
|
|
|
||
|
|
<br><dt><code>P</code><dd>12-bit signed integer constant that is greater than zero—i.e. in the
|
||
|
|
range of 1 to 2047.
|
||
|
|
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<br><dt><em>Hewlett-Packard PA-RISC—</em><samp><span class="file">config/pa/pa.h</span></samp><dd>
|
||
|
|
<dl>
|
||
|
|
<dt><code>a</code><dd>General register 1
|
||
|
|
|
||
|
|
<br><dt><code>f</code><dd>Floating point register
|
||
|
|
|
||
|
|
<br><dt><code>q</code><dd>Shift amount register
|
||
|
|
|
||
|
|
<br><dt><code>x</code><dd>Floating point register (deprecated)
|
||
|
|
|
||
|
|
<br><dt><code>y</code><dd>Upper floating point register (32-bit), floating point register (64-bit)
|
||
|
|
|
||
|
|
<br><dt><code>Z</code><dd>Any register
|
||
|
|
|
||
|
|
<br><dt><code>I</code><dd>Signed 11-bit integer constant
|
||
|
|
|
||
|
|
<br><dt><code>J</code><dd>Signed 14-bit integer constant
|
||
|
|
|
||
|
|
<br><dt><code>K</code><dd>Integer constant that can be deposited with a <code>zdepi</code> instruction
|
||
|
|
|
||
|
|
<br><dt><code>L</code><dd>Signed 5-bit integer constant
|
||
|
|
|
||
|
|
<br><dt><code>M</code><dd>Integer constant 0
|
||
|
|
|
||
|
|
<br><dt><code>N</code><dd>Integer constant that can be loaded with a <code>ldil</code> instruction
|
||
|
|
|
||
|
|
<br><dt><code>O</code><dd>Integer constant whose value plus one is a power of 2
|
||
|
|
|
||
|
|
<br><dt><code>P</code><dd>Integer constant that can be used for <code>and</code> operations in <code>depi</code>
|
||
|
|
and <code>extru</code> instructions
|
||
|
|
|
||
|
|
<br><dt><code>S</code><dd>Integer constant 31
|
||
|
|
|
||
|
|
<br><dt><code>U</code><dd>Integer constant 63
|
||
|
|
|
||
|
|
<br><dt><code>G</code><dd>Floating-point constant 0.0
|
||
|
|
|
||
|
|
<br><dt><code>A</code><dd>A <code>lo_sum</code> data-linkage-table memory operand
|
||
|
|
|
||
|
|
<br><dt><code>Q</code><dd>A memory operand that can be used as the destination operand of an
|
||
|
|
integer store instruction
|
||
|
|
|
||
|
|
<br><dt><code>R</code><dd>A scaled or unscaled indexed memory operand
|
||
|
|
|
||
|
|
<br><dt><code>T</code><dd>A memory operand for floating-point loads and stores
|
||
|
|
|
||
|
|
<br><dt><code>W</code><dd>A register indirect memory operand
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<br><dt><em>Intel IA-64—</em><samp><span class="file">config/ia64/ia64.h</span></samp><dd>
|
||
|
|
<dl>
|
||
|
|
<dt><code>a</code><dd>General register <code>r0</code> to <code>r3</code> for <code>addl</code> instruction
|
||
|
|
|
||
|
|
<br><dt><code>b</code><dd>Branch register
|
||
|
|
|
||
|
|
<br><dt><code>c</code><dd>Predicate register (‘<samp><span class="samp">c</span></samp>’ as in “conditional”)
|
||
|
|
|
||
|
|
<br><dt><code>d</code><dd>Application register residing in M-unit
|
||
|
|
|
||
|
|
<br><dt><code>e</code><dd>Application register residing in I-unit
|
||
|
|
|
||
|
|
<br><dt><code>f</code><dd>Floating-point register
|
||
|
|
|
||
|
|
<br><dt><code>m</code><dd>Memory operand. If used together with ‘<samp><span class="samp"><</span></samp>’ or ‘<samp><span class="samp">></span></samp>’,
|
||
|
|
the operand can have postincrement and postdecrement which
|
||
|
|
require printing with ‘<samp><span class="samp">%Pn</span></samp>’ on IA-64.
|
||
|
|
|
||
|
|
<br><dt><code>G</code><dd>Floating-point constant 0.0 or 1.0
|
||
|
|
|
||
|
|
<br><dt><code>I</code><dd>14-bit signed integer constant
|
||
|
|
|
||
|
|
<br><dt><code>J</code><dd>22-bit signed integer constant
|
||
|
|
|
||
|
|
<br><dt><code>K</code><dd>8-bit signed integer constant for logical instructions
|
||
|
|
|
||
|
|
<br><dt><code>L</code><dd>8-bit adjusted signed integer constant for compare pseudo-ops
|
||
|
|
|
||
|
|
<br><dt><code>M</code><dd>6-bit unsigned integer constant for shift counts
|
||
|
|
|
||
|
|
<br><dt><code>N</code><dd>9-bit signed integer constant for load and store postincrements
|
||
|
|
|
||
|
|
<br><dt><code>O</code><dd>The constant zero
|
||
|
|
|
||
|
|
<br><dt><code>P</code><dd>0 or −1 for <code>dep</code> instruction
|
||
|
|
|
||
|
|
<br><dt><code>Q</code><dd>Non-volatile memory for floating-point loads and stores
|
||
|
|
|
||
|
|
<br><dt><code>R</code><dd>Integer constant in the range 1 to 4 for <code>shladd</code> instruction
|
||
|
|
|
||
|
|
<br><dt><code>S</code><dd>Memory operand except postincrement and postdecrement. This is
|
||
|
|
now roughly the same as ‘<samp><span class="samp">m</span></samp>’ when not used together with ‘<samp><span class="samp"><</span></samp>’
|
||
|
|
or ‘<samp><span class="samp">></span></samp>’.
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<br><dt><em>M32C—</em><samp><span class="file">config/m32c/m32c.c</span></samp><dd>
|
||
|
|
<dl>
|
||
|
|
<dt><code>Rsp</code><dt><code>Rfb</code><dt><code>Rsb</code><dd>‘<samp><span class="samp">$sp</span></samp>’, ‘<samp><span class="samp">$fb</span></samp>’, ‘<samp><span class="samp">$sb</span></samp>’.
|
||
|
|
|
||
|
|
<br><dt><code>Rcr</code><dd>Any control register, when they're 16 bits wide (nothing if control
|
||
|
|
registers are 24 bits wide)
|
||
|
|
|
||
|
|
<br><dt><code>Rcl</code><dd>Any control register, when they're 24 bits wide.
|
||
|
|
|
||
|
|
<br><dt><code>R0w</code><dt><code>R1w</code><dt><code>R2w</code><dt><code>R3w</code><dd>$r0, $r1, $r2, $r3.
|
||
|
|
|
||
|
|
<br><dt><code>R02</code><dd>$r0 or $r2, or $r2r0 for 32 bit values.
|
||
|
|
|
||
|
|
<br><dt><code>R13</code><dd>$r1 or $r3, or $r3r1 for 32 bit values.
|
||
|
|
|
||
|
|
<br><dt><code>Rdi</code><dd>A register that can hold a 64 bit value.
|
||
|
|
|
||
|
|
<br><dt><code>Rhl</code><dd>$r0 or $r1 (registers with addressable high/low bytes)
|
||
|
|
|
||
|
|
<br><dt><code>R23</code><dd>$r2 or $r3
|
||
|
|
|
||
|
|
<br><dt><code>Raa</code><dd>Address registers
|
||
|
|
|
||
|
|
<br><dt><code>Raw</code><dd>Address registers when they're 16 bits wide.
|
||
|
|
|
||
|
|
<br><dt><code>Ral</code><dd>Address registers when they're 24 bits wide.
|
||
|
|
|
||
|
|
<br><dt><code>Rqi</code><dd>Registers that can hold QI values.
|
||
|
|
|
||
|
|
<br><dt><code>Rad</code><dd>Registers that can be used with displacements ($a0, $a1, $sb).
|
||
|
|
|
||
|
|
<br><dt><code>Rsi</code><dd>Registers that can hold 32 bit values.
|
||
|
|
|
||
|
|
<br><dt><code>Rhi</code><dd>Registers that can hold 16 bit values.
|
||
|
|
|
||
|
|
<br><dt><code>Rhc</code><dd>Registers chat can hold 16 bit values, including all control
|
||
|
|
registers.
|
||
|
|
|
||
|
|
<br><dt><code>Rra</code><dd>$r0 through R1, plus $a0 and $a1.
|
||
|
|
|
||
|
|
<br><dt><code>Rfl</code><dd>The flags register.
|
||
|
|
|
||
|
|
<br><dt><code>Rmm</code><dd>The memory-based pseudo-registers $mem0 through $mem15.
|
||
|
|
|
||
|
|
<br><dt><code>Rpi</code><dd>Registers that can hold pointers (16 bit registers for r8c, m16c; 24
|
||
|
|
bit registers for m32cm, m32c).
|
||
|
|
|
||
|
|
<br><dt><code>Rpa</code><dd>Matches multiple registers in a PARALLEL to form a larger register.
|
||
|
|
Used to match function return values.
|
||
|
|
|
||
|
|
<br><dt><code>Is3</code><dd>−8 <small class="dots">...</small> 7
|
||
|
|
|
||
|
|
<br><dt><code>IS1</code><dd>−128 <small class="dots">...</small> 127
|
||
|
|
|
||
|
|
<br><dt><code>IS2</code><dd>−32768 <small class="dots">...</small> 32767
|
||
|
|
|
||
|
|
<br><dt><code>IU2</code><dd>0 <small class="dots">...</small> 65535
|
||
|
|
|
||
|
|
<br><dt><code>In4</code><dd>−8 <small class="dots">...</small> −1 or 1 <small class="dots">...</small> 8
|
||
|
|
|
||
|
|
<br><dt><code>In5</code><dd>−16 <small class="dots">...</small> −1 or 1 <small class="dots">...</small> 16
|
||
|
|
|
||
|
|
<br><dt><code>In6</code><dd>−32 <small class="dots">...</small> −1 or 1 <small class="dots">...</small> 32
|
||
|
|
|
||
|
|
<br><dt><code>IM2</code><dd>−65536 <small class="dots">...</small> −1
|
||
|
|
|
||
|
|
<br><dt><code>Ilb</code><dd>An 8 bit value with exactly one bit set.
|
||
|
|
|
||
|
|
<br><dt><code>Ilw</code><dd>A 16 bit value with exactly one bit set.
|
||
|
|
|
||
|
|
<br><dt><code>Sd</code><dd>The common src/dest memory addressing modes.
|
||
|
|
|
||
|
|
<br><dt><code>Sa</code><dd>Memory addressed using $a0 or $a1.
|
||
|
|
|
||
|
|
<br><dt><code>Si</code><dd>Memory addressed with immediate addresses.
|
||
|
|
|
||
|
|
<br><dt><code>Ss</code><dd>Memory addressed using the stack pointer ($sp).
|
||
|
|
|
||
|
|
<br><dt><code>Sf</code><dd>Memory addressed using the frame base register ($fb).
|
||
|
|
|
||
|
|
<br><dt><code>Ss</code><dd>Memory addressed using the small base register ($sb).
|
||
|
|
|
||
|
|
<br><dt><code>S1</code><dd>$r1h
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<br><dt><em>MeP—</em><samp><span class="file">config/mep/constraints.md</span></samp><dd>
|
||
|
|
<dl>
|
||
|
|
<dt><code>a</code><dd>The $sp register.
|
||
|
|
|
||
|
|
<br><dt><code>b</code><dd>The $tp register.
|
||
|
|
|
||
|
|
<br><dt><code>c</code><dd>Any control register.
|
||
|
|
|
||
|
|
<br><dt><code>d</code><dd>Either the $hi or the $lo register.
|
||
|
|
|
||
|
|
<br><dt><code>em</code><dd>Coprocessor registers that can be directly loaded ($c0-$c15).
|
||
|
|
|
||
|
|
<br><dt><code>ex</code><dd>Coprocessor registers that can be moved to each other.
|
||
|
|
|
||
|
|
<br><dt><code>er</code><dd>Coprocessor registers that can be moved to core registers.
|
||
|
|
|
||
|
|
<br><dt><code>h</code><dd>The $hi register.
|
||
|
|
|
||
|
|
<br><dt><code>j</code><dd>The $rpc register.
|
||
|
|
|
||
|
|
<br><dt><code>l</code><dd>The $lo register.
|
||
|
|
|
||
|
|
<br><dt><code>t</code><dd>Registers which can be used in $tp-relative addressing.
|
||
|
|
|
||
|
|
<br><dt><code>v</code><dd>The $gp register.
|
||
|
|
|
||
|
|
<br><dt><code>x</code><dd>The coprocessor registers.
|
||
|
|
|
||
|
|
<br><dt><code>y</code><dd>The coprocessor control registers.
|
||
|
|
|
||
|
|
<br><dt><code>z</code><dd>The $0 register.
|
||
|
|
|
||
|
|
<br><dt><code>A</code><dd>User-defined register set A.
|
||
|
|
|
||
|
|
<br><dt><code>B</code><dd>User-defined register set B.
|
||
|
|
|
||
|
|
<br><dt><code>C</code><dd>User-defined register set C.
|
||
|
|
|
||
|
|
<br><dt><code>D</code><dd>User-defined register set D.
|
||
|
|
|
||
|
|
<br><dt><code>I</code><dd>Offsets for $gp-rel addressing.
|
||
|
|
|
||
|
|
<br><dt><code>J</code><dd>Constants that can be used directly with boolean insns.
|
||
|
|
|
||
|
|
<br><dt><code>K</code><dd>Constants that can be moved directly to registers.
|
||
|
|
|
||
|
|
<br><dt><code>L</code><dd>Small constants that can be added to registers.
|
||
|
|
|
||
|
|
<br><dt><code>M</code><dd>Long shift counts.
|
||
|
|
|
||
|
|
<br><dt><code>N</code><dd>Small constants that can be compared to registers.
|
||
|
|
|
||
|
|
<br><dt><code>O</code><dd>Constants that can be loaded into the top half of registers.
|
||
|
|
|
||
|
|
<br><dt><code>S</code><dd>Signed 8-bit immediates.
|
||
|
|
|
||
|
|
<br><dt><code>T</code><dd>Symbols encoded for $tp-rel or $gp-rel addressing.
|
||
|
|
|
||
|
|
<br><dt><code>U</code><dd>Non-constant addresses for loading/saving coprocessor registers.
|
||
|
|
|
||
|
|
<br><dt><code>W</code><dd>The top half of a symbol's value.
|
||
|
|
|
||
|
|
<br><dt><code>Y</code><dd>A register indirect address without offset.
|
||
|
|
|
||
|
|
<br><dt><code>Z</code><dd>Symbolic references to the control bus.
|
||
|
|
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<br><dt><em>MicroBlaze—</em><samp><span class="file">config/microblaze/constraints.md</span></samp><dd>
|
||
|
|
<dl>
|
||
|
|
<dt><code>d</code><dd>A general register (<code>r0</code> to <code>r31</code>).
|
||
|
|
|
||
|
|
<br><dt><code>z</code><dd>A status register (<code>rmsr</code>, <code>$fcc1</code> to <code>$fcc7</code>).
|
||
|
|
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<br><dt><em>MIPS—</em><samp><span class="file">config/mips/constraints.md</span></samp><dd>
|
||
|
|
<dl>
|
||
|
|
<dt><code>d</code><dd>An address register. This is equivalent to <code>r</code> unless
|
||
|
|
generating MIPS16 code.
|
||
|
|
|
||
|
|
<br><dt><code>f</code><dd>A floating-point register (if available).
|
||
|
|
|
||
|
|
<br><dt><code>h</code><dd>Formerly the <code>hi</code> register. This constraint is no longer supported.
|
||
|
|
|
||
|
|
<br><dt><code>l</code><dd>The <code>lo</code> register. Use this register to store values that are
|
||
|
|
no bigger than a word.
|
||
|
|
|
||
|
|
<br><dt><code>x</code><dd>The concatenated <code>hi</code> and <code>lo</code> registers. Use this register
|
||
|
|
to store doubleword values.
|
||
|
|
|
||
|
|
<br><dt><code>c</code><dd>A register suitable for use in an indirect jump. This will always be
|
||
|
|
<code>$25</code> for <samp><span class="option">-mabicalls</span></samp>.
|
||
|
|
|
||
|
|
<br><dt><code>v</code><dd>Register <code>$3</code>. Do not use this constraint in new code;
|
||
|
|
it is retained only for compatibility with glibc.
|
||
|
|
|
||
|
|
<br><dt><code>y</code><dd>Equivalent to <code>r</code>; retained for backwards compatibility.
|
||
|
|
|
||
|
|
<br><dt><code>z</code><dd>A floating-point condition code register.
|
||
|
|
|
||
|
|
<br><dt><code>I</code><dd>A signed 16-bit constant (for arithmetic instructions).
|
||
|
|
|
||
|
|
<br><dt><code>J</code><dd>Integer zero.
|
||
|
|
|
||
|
|
<br><dt><code>K</code><dd>An unsigned 16-bit constant (for logic instructions).
|
||
|
|
|
||
|
|
<br><dt><code>L</code><dd>A signed 32-bit constant in which the lower 16 bits are zero.
|
||
|
|
Such constants can be loaded using <code>lui</code>.
|
||
|
|
|
||
|
|
<br><dt><code>M</code><dd>A constant that cannot be loaded using <code>lui</code>, <code>addiu</code>
|
||
|
|
or <code>ori</code>.
|
||
|
|
|
||
|
|
<br><dt><code>N</code><dd>A constant in the range −65535 to −1 (inclusive).
|
||
|
|
|
||
|
|
<br><dt><code>O</code><dd>A signed 15-bit constant.
|
||
|
|
|
||
|
|
<br><dt><code>P</code><dd>A constant in the range 1 to 65535 (inclusive).
|
||
|
|
|
||
|
|
<br><dt><code>G</code><dd>Floating-point zero.
|
||
|
|
|
||
|
|
<br><dt><code>R</code><dd>An address that can be used in a non-macro load or store.
|
||
|
|
|
||
|
|
<br><dt><code>ZC</code><dd>A memory operand whose address is formed by a base register and offset
|
||
|
|
that is suitable for use in instructions with the same addressing mode
|
||
|
|
as <code>ll</code> and <code>sc</code>.
|
||
|
|
|
||
|
|
<br><dt><code>ZD</code><dd>An address suitable for a <code>prefetch</code> instruction, or for any other
|
||
|
|
instruction with the same addressing mode as <code>prefetch</code>.
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<br><dt><em>Motorola 680x0—</em><samp><span class="file">config/m68k/constraints.md</span></samp><dd>
|
||
|
|
<dl>
|
||
|
|
<dt><code>a</code><dd>Address register
|
||
|
|
|
||
|
|
<br><dt><code>d</code><dd>Data register
|
||
|
|
|
||
|
|
<br><dt><code>f</code><dd>68881 floating-point register, if available
|
||
|
|
|
||
|
|
<br><dt><code>I</code><dd>Integer in the range 1 to 8
|
||
|
|
|
||
|
|
<br><dt><code>J</code><dd>16-bit signed number
|
||
|
|
|
||
|
|
<br><dt><code>K</code><dd>Signed number whose magnitude is greater than 0x80
|
||
|
|
|
||
|
|
<br><dt><code>L</code><dd>Integer in the range −8 to −1
|
||
|
|
|
||
|
|
<br><dt><code>M</code><dd>Signed number whose magnitude is greater than 0x100
|
||
|
|
|
||
|
|
<br><dt><code>N</code><dd>Range 24 to 31, rotatert:SI 8 to 1 expressed as rotate
|
||
|
|
|
||
|
|
<br><dt><code>O</code><dd>16 (for rotate using swap)
|
||
|
|
|
||
|
|
<br><dt><code>P</code><dd>Range 8 to 15, rotatert:HI 8 to 1 expressed as rotate
|
||
|
|
|
||
|
|
<br><dt><code>R</code><dd>Numbers that mov3q can handle
|
||
|
|
|
||
|
|
<br><dt><code>G</code><dd>Floating point constant that is not a 68881 constant
|
||
|
|
|
||
|
|
<br><dt><code>S</code><dd>Operands that satisfy 'm' when -mpcrel is in effect
|
||
|
|
|
||
|
|
<br><dt><code>T</code><dd>Operands that satisfy 's' when -mpcrel is not in effect
|
||
|
|
|
||
|
|
<br><dt><code>Q</code><dd>Address register indirect addressing mode
|
||
|
|
|
||
|
|
<br><dt><code>U</code><dd>Register offset addressing
|
||
|
|
|
||
|
|
<br><dt><code>W</code><dd>const_call_operand
|
||
|
|
|
||
|
|
<br><dt><code>Cs</code><dd>symbol_ref or const
|
||
|
|
|
||
|
|
<br><dt><code>Ci</code><dd>const_int
|
||
|
|
|
||
|
|
<br><dt><code>C0</code><dd>const_int 0
|
||
|
|
|
||
|
|
<br><dt><code>Cj</code><dd>Range of signed numbers that don't fit in 16 bits
|
||
|
|
|
||
|
|
<br><dt><code>Cmvq</code><dd>Integers valid for mvq
|
||
|
|
|
||
|
|
<br><dt><code>Capsw</code><dd>Integers valid for a moveq followed by a swap
|
||
|
|
|
||
|
|
<br><dt><code>Cmvz</code><dd>Integers valid for mvz
|
||
|
|
|
||
|
|
<br><dt><code>Cmvs</code><dd>Integers valid for mvs
|
||
|
|
|
||
|
|
<br><dt><code>Ap</code><dd>push_operand
|
||
|
|
|
||
|
|
<br><dt><code>Ac</code><dd>Non-register operands allowed in clr
|
||
|
|
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<br><dt><em>Moxie—</em><samp><span class="file">config/moxie/constraints.md</span></samp><dd>
|
||
|
|
<dl>
|
||
|
|
<dt><code>A</code><dd>An absolute address
|
||
|
|
|
||
|
|
<br><dt><code>B</code><dd>An offset address
|
||
|
|
|
||
|
|
<br><dt><code>W</code><dd>A register indirect memory operand
|
||
|
|
|
||
|
|
<br><dt><code>I</code><dd>A constant in the range of 0 to 255.
|
||
|
|
|
||
|
|
<br><dt><code>N</code><dd>A constant in the range of 0 to −255.
|
||
|
|
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<br><dt><em>MSP430–</em><samp><span class="file">config/msp430/constraints.md</span></samp><dd>
|
||
|
|
<dl>
|
||
|
|
<dt><code>R12</code><dd>Register R12.
|
||
|
|
|
||
|
|
<br><dt><code>R13</code><dd>Register R13.
|
||
|
|
|
||
|
|
<br><dt><code>K</code><dd>Integer constant 1.
|
||
|
|
|
||
|
|
<br><dt><code>L</code><dd>Integer constant -1^20..1^19.
|
||
|
|
|
||
|
|
<br><dt><code>M</code><dd>Integer constant 1-4.
|
||
|
|
|
||
|
|
<br><dt><code>Ya</code><dd>Memory references which do not require an extended MOVX instruction.
|
||
|
|
|
||
|
|
<br><dt><code>Yl</code><dd>Memory reference, labels only.
|
||
|
|
|
||
|
|
<br><dt><code>Ys</code><dd>Memory reference, stack only.
|
||
|
|
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<br><dt><em>NDS32—</em><samp><span class="file">config/nds32/constraints.md</span></samp><dd>
|
||
|
|
<dl>
|
||
|
|
<dt><code>w</code><dd>LOW register class $r0 to $r7 constraint for V3/V3M ISA.
|
||
|
|
<br><dt><code>l</code><dd>LOW register class $r0 to $r7.
|
||
|
|
<br><dt><code>d</code><dd>MIDDLE register class $r0 to $r11, $r16 to $r19.
|
||
|
|
<br><dt><code>h</code><dd>HIGH register class $r12 to $r14, $r20 to $r31.
|
||
|
|
<br><dt><code>t</code><dd>Temporary assist register $ta (i.e. $r15).
|
||
|
|
<br><dt><code>k</code><dd>Stack register $sp.
|
||
|
|
<br><dt><code>Iu03</code><dd>Unsigned immediate 3-bit value.
|
||
|
|
<br><dt><code>In03</code><dd>Negative immediate 3-bit value in the range of −7–0.
|
||
|
|
<br><dt><code>Iu04</code><dd>Unsigned immediate 4-bit value.
|
||
|
|
<br><dt><code>Is05</code><dd>Signed immediate 5-bit value.
|
||
|
|
<br><dt><code>Iu05</code><dd>Unsigned immediate 5-bit value.
|
||
|
|
<br><dt><code>In05</code><dd>Negative immediate 5-bit value in the range of −31–0.
|
||
|
|
<br><dt><code>Ip05</code><dd>Unsigned immediate 5-bit value for movpi45 instruction with range 16–47.
|
||
|
|
<br><dt><code>Iu06</code><dd>Unsigned immediate 6-bit value constraint for addri36.sp instruction.
|
||
|
|
<br><dt><code>Iu08</code><dd>Unsigned immediate 8-bit value.
|
||
|
|
<br><dt><code>Iu09</code><dd>Unsigned immediate 9-bit value.
|
||
|
|
<br><dt><code>Is10</code><dd>Signed immediate 10-bit value.
|
||
|
|
<br><dt><code>Is11</code><dd>Signed immediate 11-bit value.
|
||
|
|
<br><dt><code>Is15</code><dd>Signed immediate 15-bit value.
|
||
|
|
<br><dt><code>Iu15</code><dd>Unsigned immediate 15-bit value.
|
||
|
|
<br><dt><code>Ic15</code><dd>A constant which is not in the range of imm15u but ok for bclr instruction.
|
||
|
|
<br><dt><code>Ie15</code><dd>A constant which is not in the range of imm15u but ok for bset instruction.
|
||
|
|
<br><dt><code>It15</code><dd>A constant which is not in the range of imm15u but ok for btgl instruction.
|
||
|
|
<br><dt><code>Ii15</code><dd>A constant whose compliment value is in the range of imm15u
|
||
|
|
and ok for bitci instruction.
|
||
|
|
<br><dt><code>Is16</code><dd>Signed immediate 16-bit value.
|
||
|
|
<br><dt><code>Is17</code><dd>Signed immediate 17-bit value.
|
||
|
|
<br><dt><code>Is19</code><dd>Signed immediate 19-bit value.
|
||
|
|
<br><dt><code>Is20</code><dd>Signed immediate 20-bit value.
|
||
|
|
<br><dt><code>Ihig</code><dd>The immediate value that can be simply set high 20-bit.
|
||
|
|
<br><dt><code>Izeb</code><dd>The immediate value 0xff.
|
||
|
|
<br><dt><code>Izeh</code><dd>The immediate value 0xffff.
|
||
|
|
<br><dt><code>Ixls</code><dd>The immediate value 0x01.
|
||
|
|
<br><dt><code>Ix11</code><dd>The immediate value 0x7ff.
|
||
|
|
<br><dt><code>Ibms</code><dd>The immediate value with power of 2.
|
||
|
|
<br><dt><code>Ifex</code><dd>The immediate value with power of 2 minus 1.
|
||
|
|
<br><dt><code>U33</code><dd>Memory constraint for 333 format.
|
||
|
|
<br><dt><code>U45</code><dd>Memory constraint for 45 format.
|
||
|
|
<br><dt><code>U37</code><dd>Memory constraint for 37 format.
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<br><dt><em>Nios II family—</em><samp><span class="file">config/nios2/constraints.md</span></samp><dd>
|
||
|
|
<dl>
|
||
|
|
<dt><code>I</code><dd>Integer that is valid as an immediate operand in an
|
||
|
|
instruction taking a signed 16-bit number. Range
|
||
|
|
−32768 to 32767.
|
||
|
|
|
||
|
|
<br><dt><code>J</code><dd>Integer that is valid as an immediate operand in an
|
||
|
|
instruction taking an unsigned 16-bit number. Range
|
||
|
|
0 to 65535.
|
||
|
|
|
||
|
|
<br><dt><code>K</code><dd>Integer that is valid as an immediate operand in an
|
||
|
|
instruction taking only the upper 16-bits of a
|
||
|
|
32-bit number. Range 32-bit numbers with the lower
|
||
|
|
16-bits being 0.
|
||
|
|
|
||
|
|
<br><dt><code>L</code><dd>Integer that is valid as an immediate operand for a
|
||
|
|
shift instruction. Range 0 to 31.
|
||
|
|
|
||
|
|
<br><dt><code>M</code><dd>Integer that is valid as an immediate operand for
|
||
|
|
only the value 0. Can be used in conjunction with
|
||
|
|
the format modifier <code>z</code> to use <code>r0</code>
|
||
|
|
instead of <code>0</code> in the assembly output.
|
||
|
|
|
||
|
|
<br><dt><code>N</code><dd>Integer that is valid as an immediate operand for
|
||
|
|
a custom instruction opcode. Range 0 to 255.
|
||
|
|
|
||
|
|
<br><dt><code>S</code><dd>Matches immediates which are addresses in the small
|
||
|
|
data section and therefore can be added to <code>gp</code>
|
||
|
|
as a 16-bit immediate to re-create their 32-bit value.
|
||
|
|
|
||
|
|
<br><dt><code>T</code><dd>A <code>const</code> wrapped <code>UNSPEC</code> expression,
|
||
|
|
representing a supported PIC or TLS relocation.
|
||
|
|
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<br><dt><em>PDP-11—</em><samp><span class="file">config/pdp11/constraints.md</span></samp><dd>
|
||
|
|
<dl>
|
||
|
|
<dt><code>a</code><dd>Floating point registers AC0 through AC3. These can be loaded from/to
|
||
|
|
memory with a single instruction.
|
||
|
|
|
||
|
|
<br><dt><code>d</code><dd>Odd numbered general registers (R1, R3, R5). These are used for
|
||
|
|
16-bit multiply operations.
|
||
|
|
|
||
|
|
<br><dt><code>f</code><dd>Any of the floating point registers (AC0 through AC5).
|
||
|
|
|
||
|
|
<br><dt><code>G</code><dd>Floating point constant 0.
|
||
|
|
|
||
|
|
<br><dt><code>I</code><dd>An integer constant that fits in 16 bits.
|
||
|
|
|
||
|
|
<br><dt><code>J</code><dd>An integer constant whose low order 16 bits are zero.
|
||
|
|
|
||
|
|
<br><dt><code>K</code><dd>An integer constant that does not meet the constraints for codes
|
||
|
|
‘<samp><span class="samp">I</span></samp>’ or ‘<samp><span class="samp">J</span></samp>’.
|
||
|
|
|
||
|
|
<br><dt><code>L</code><dd>The integer constant 1.
|
||
|
|
|
||
|
|
<br><dt><code>M</code><dd>The integer constant −1.
|
||
|
|
|
||
|
|
<br><dt><code>N</code><dd>The integer constant 0.
|
||
|
|
|
||
|
|
<br><dt><code>O</code><dd>Integer constants −4 through −1 and 1 through 4; shifts by these
|
||
|
|
amounts are handled as multiple single-bit shifts rather than a single
|
||
|
|
variable-length shift.
|
||
|
|
|
||
|
|
<br><dt><code>Q</code><dd>A memory reference which requires an additional word (address or
|
||
|
|
offset) after the opcode.
|
||
|
|
|
||
|
|
<br><dt><code>R</code><dd>A memory reference that is encoded within the opcode.
|
||
|
|
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<br><dt><em>PowerPC and IBM RS6000—</em><samp><span class="file">config/rs6000/constraints.md</span></samp><dd>
|
||
|
|
<dl>
|
||
|
|
<dt><code>b</code><dd>Address base register
|
||
|
|
|
||
|
|
<br><dt><code>d</code><dd>Floating point register (containing 64-bit value)
|
||
|
|
|
||
|
|
<br><dt><code>f</code><dd>Floating point register (containing 32-bit value)
|
||
|
|
|
||
|
|
<br><dt><code>v</code><dd>Altivec vector register
|
||
|
|
|
||
|
|
<br><dt><code>wa</code><dd>Any VSX register if the -mvsx option was used or NO_REGS.
|
||
|
|
|
||
|
|
<p>When using any of the register constraints (<code>wa</code>, <code>wd</code>,
|
||
|
|
<code>wf</code>, <code>wg</code>, <code>wh</code>, <code>wi</code>, <code>wj</code>, <code>wk</code>,
|
||
|
|
<code>wl</code>, <code>wm</code>, <code>ws</code>, <code>wt</code>, <code>wu</code>, <code>wv</code>,
|
||
|
|
<code>ww</code>, or <code>wy</code>) that take VSX registers, you must use
|
||
|
|
<code>%x<n></code> in the template so that the correct register is used.
|
||
|
|
Otherwise the register number output in the assembly file will be
|
||
|
|
incorrect if an Altivec register is an operand of a VSX instruction
|
||
|
|
that expects VSX register numbering.
|
||
|
|
|
||
|
|
<pre class="smallexample"> asm ("xvadddp %x0,%x1,%x2" : "=wa" (v1) : "wa" (v2), "wa" (v3));
|
||
|
|
</pre>
|
||
|
|
<p>is correct, but:
|
||
|
|
|
||
|
|
<pre class="smallexample"> asm ("xvadddp %0,%1,%2" : "=wa" (v1) : "wa" (v2), "wa" (v3));
|
||
|
|
</pre>
|
||
|
|
<p>is not correct.
|
||
|
|
|
||
|
|
<br><dt><code>wd</code><dd>VSX vector register to hold vector double data or NO_REGS.
|
||
|
|
|
||
|
|
<br><dt><code>wf</code><dd>VSX vector register to hold vector float data or NO_REGS.
|
||
|
|
|
||
|
|
<br><dt><code>wg</code><dd>If <samp><span class="option">-mmfpgpr</span></samp> was used, a floating point register or NO_REGS.
|
||
|
|
|
||
|
|
<br><dt><code>wh</code><dd>Floating point register if direct moves are available, or NO_REGS.
|
||
|
|
|
||
|
|
<br><dt><code>wi</code><dd>FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.
|
||
|
|
|
||
|
|
<br><dt><code>wj</code><dd>FP or VSX register to hold 64-bit integers for direct moves or NO_REGS.
|
||
|
|
|
||
|
|
<br><dt><code>wk</code><dd>FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.
|
||
|
|
|
||
|
|
<br><dt><code>wl</code><dd>Floating point register if the LFIWAX instruction is enabled or NO_REGS.
|
||
|
|
|
||
|
|
<br><dt><code>wm</code><dd>VSX register if direct move instructions are enabled, or NO_REGS.
|
||
|
|
|
||
|
|
<br><dt><code>wn</code><dd>No register (NO_REGS).
|
||
|
|
|
||
|
|
<br><dt><code>wr</code><dd>General purpose register if 64-bit instructions are enabled or NO_REGS.
|
||
|
|
|
||
|
|
<br><dt><code>ws</code><dd>VSX vector register to hold scalar double values or NO_REGS.
|
||
|
|
|
||
|
|
<br><dt><code>wt</code><dd>VSX vector register to hold 128 bit integer or NO_REGS.
|
||
|
|
|
||
|
|
<br><dt><code>wu</code><dd>Altivec register to use for float/32-bit int loads/stores or NO_REGS.
|
||
|
|
|
||
|
|
<br><dt><code>wv</code><dd>Altivec register to use for double loads/stores or NO_REGS.
|
||
|
|
|
||
|
|
<br><dt><code>ww</code><dd>FP or VSX register to perform float operations under <samp><span class="option">-mvsx</span></samp> or NO_REGS.
|
||
|
|
|
||
|
|
<br><dt><code>wx</code><dd>Floating point register if the STFIWX instruction is enabled or NO_REGS.
|
||
|
|
|
||
|
|
<br><dt><code>wy</code><dd>FP or VSX register to perform ISA 2.07 float ops or NO_REGS.
|
||
|
|
|
||
|
|
<br><dt><code>wz</code><dd>Floating point register if the LFIWZX instruction is enabled or NO_REGS.
|
||
|
|
|
||
|
|
<br><dt><code>wD</code><dd>Int constant that is the element number of the 64-bit scalar in a vector.
|
||
|
|
|
||
|
|
<br><dt><code>wQ</code><dd>A memory address that will work with the <code>lq</code> and <code>stq</code>
|
||
|
|
instructions.
|
||
|
|
|
||
|
|
<br><dt><code>h</code><dd>‘<samp><span class="samp">MQ</span></samp>’, ‘<samp><span class="samp">CTR</span></samp>’, or ‘<samp><span class="samp">LINK</span></samp>’ register
|
||
|
|
|
||
|
|
<br><dt><code>q</code><dd>‘<samp><span class="samp">MQ</span></samp>’ register
|
||
|
|
|
||
|
|
<br><dt><code>c</code><dd>‘<samp><span class="samp">CTR</span></samp>’ register
|
||
|
|
|
||
|
|
<br><dt><code>l</code><dd>‘<samp><span class="samp">LINK</span></samp>’ register
|
||
|
|
|
||
|
|
<br><dt><code>x</code><dd>‘<samp><span class="samp">CR</span></samp>’ register (condition register) number 0
|
||
|
|
|
||
|
|
<br><dt><code>y</code><dd>‘<samp><span class="samp">CR</span></samp>’ register (condition register)
|
||
|
|
|
||
|
|
<br><dt><code>z</code><dd>‘<samp><span class="samp">XER[CA]</span></samp>’ carry bit (part of the XER register)
|
||
|
|
|
||
|
|
<br><dt><code>I</code><dd>Signed 16-bit constant
|
||
|
|
|
||
|
|
<br><dt><code>J</code><dd>Unsigned 16-bit constant shifted left 16 bits (use ‘<samp><span class="samp">L</span></samp>’ instead for
|
||
|
|
<code>SImode</code> constants)
|
||
|
|
|
||
|
|
<br><dt><code>K</code><dd>Unsigned 16-bit constant
|
||
|
|
|
||
|
|
<br><dt><code>L</code><dd>Signed 16-bit constant shifted left 16 bits
|
||
|
|
|
||
|
|
<br><dt><code>M</code><dd>Constant larger than 31
|
||
|
|
|
||
|
|
<br><dt><code>N</code><dd>Exact power of 2
|
||
|
|
|
||
|
|
<br><dt><code>O</code><dd>Zero
|
||
|
|
|
||
|
|
<br><dt><code>P</code><dd>Constant whose negation is a signed 16-bit constant
|
||
|
|
|
||
|
|
<br><dt><code>G</code><dd>Floating point constant that can be loaded into a register with one
|
||
|
|
instruction per word
|
||
|
|
|
||
|
|
<br><dt><code>H</code><dd>Integer/Floating point constant that can be loaded into a register using
|
||
|
|
three instructions
|
||
|
|
|
||
|
|
<br><dt><code>m</code><dd>Memory operand.
|
||
|
|
Normally, <code>m</code> does not allow addresses that update the base register.
|
||
|
|
If ‘<samp><span class="samp"><</span></samp>’ or ‘<samp><span class="samp">></span></samp>’ constraint is also used, they are allowed and
|
||
|
|
therefore on PowerPC targets in that case it is only safe
|
||
|
|
to use ‘<samp><span class="samp">m<></span></samp>’ in an <code>asm</code> statement if that <code>asm</code> statement
|
||
|
|
accesses the operand exactly once. The <code>asm</code> statement must also
|
||
|
|
use ‘<samp><span class="samp">%U</span><var><opno></var></samp>’ as a placeholder for the “update” flag in the
|
||
|
|
corresponding load or store instruction. For example:
|
||
|
|
|
||
|
|
<pre class="smallexample"> asm ("st%U0 %1,%0" : "=m<>" (mem) : "r" (val));
|
||
|
|
</pre>
|
||
|
|
<p>is correct but:
|
||
|
|
|
||
|
|
<pre class="smallexample"> asm ("st %1,%0" : "=m<>" (mem) : "r" (val));
|
||
|
|
</pre>
|
||
|
|
<p>is not.
|
||
|
|
|
||
|
|
<br><dt><code>es</code><dd>A “stable” memory operand; that is, one which does not include any
|
||
|
|
automodification of the base register. This used to be useful when
|
||
|
|
‘<samp><span class="samp">m</span></samp>’ allowed automodification of the base register, but as those are now only
|
||
|
|
allowed when ‘<samp><span class="samp"><</span></samp>’ or ‘<samp><span class="samp">></span></samp>’ is used, ‘<samp><span class="samp">es</span></samp>’ is basically the same
|
||
|
|
as ‘<samp><span class="samp">m</span></samp>’ without ‘<samp><span class="samp"><</span></samp>’ and ‘<samp><span class="samp">></span></samp>’.
|
||
|
|
|
||
|
|
<br><dt><code>Q</code><dd>Memory operand that is an offset from a register (it is usually better
|
||
|
|
to use ‘<samp><span class="samp">m</span></samp>’ or ‘<samp><span class="samp">es</span></samp>’ in <code>asm</code> statements)
|
||
|
|
|
||
|
|
<br><dt><code>Z</code><dd>Memory operand that is an indexed or indirect from a register (it is
|
||
|
|
usually better to use ‘<samp><span class="samp">m</span></samp>’ or ‘<samp><span class="samp">es</span></samp>’ in <code>asm</code> statements)
|
||
|
|
|
||
|
|
<br><dt><code>R</code><dd>AIX TOC entry
|
||
|
|
|
||
|
|
<br><dt><code>a</code><dd>Address operand that is an indexed or indirect from a register (‘<samp><span class="samp">p</span></samp>’ is
|
||
|
|
preferable for <code>asm</code> statements)
|
||
|
|
|
||
|
|
<br><dt><code>S</code><dd>Constant suitable as a 64-bit mask operand
|
||
|
|
|
||
|
|
<br><dt><code>T</code><dd>Constant suitable as a 32-bit mask operand
|
||
|
|
|
||
|
|
<br><dt><code>U</code><dd>System V Release 4 small data area reference
|
||
|
|
|
||
|
|
<br><dt><code>t</code><dd>AND masks that can be performed by two rldic{l, r} instructions
|
||
|
|
|
||
|
|
<br><dt><code>W</code><dd>Vector constant that does not require memory
|
||
|
|
|
||
|
|
<br><dt><code>j</code><dd>Vector constant that is all zeros.
|
||
|
|
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<br><dt><em>RL78—</em><samp><span class="file">config/rl78/constraints.md</span></samp><dd>
|
||
|
|
<dl>
|
||
|
|
<dt><code>Int3</code><dd>An integer constant in the range 1 <small class="dots">...</small> 7.
|
||
|
|
<br><dt><code>Int8</code><dd>An integer constant in the range 0 <small class="dots">...</small> 255.
|
||
|
|
<br><dt><code>J</code><dd>An integer constant in the range −255 <small class="dots">...</small> 0
|
||
|
|
<br><dt><code>K</code><dd>The integer constant 1.
|
||
|
|
<br><dt><code>L</code><dd>The integer constant -1.
|
||
|
|
<br><dt><code>M</code><dd>The integer constant 0.
|
||
|
|
<br><dt><code>N</code><dd>The integer constant 2.
|
||
|
|
<br><dt><code>O</code><dd>The integer constant -2.
|
||
|
|
<br><dt><code>P</code><dd>An integer constant in the range 1 <small class="dots">...</small> 15.
|
||
|
|
<br><dt><code>Qbi</code><dd>The built-in compare types–eq, ne, gtu, ltu, geu, and leu.
|
||
|
|
<br><dt><code>Qsc</code><dd>The synthetic compare types–gt, lt, ge, and le.
|
||
|
|
<br><dt><code>Wab</code><dd>A memory reference with an absolute address.
|
||
|
|
<br><dt><code>Wbc</code><dd>A memory reference using <code>BC</code> as a base register, with an optional offset.
|
||
|
|
<br><dt><code>Wca</code><dd>A memory reference using <code>AX</code>, <code>BC</code>, <code>DE</code>, or <code>HL</code> for the address, for calls.
|
||
|
|
<br><dt><code>Wcv</code><dd>A memory reference using any 16-bit register pair for the address, for calls.
|
||
|
|
<br><dt><code>Wd2</code><dd>A memory reference using <code>DE</code> as a base register, with an optional offset.
|
||
|
|
<br><dt><code>Wde</code><dd>A memory reference using <code>DE</code> as a base register, without any offset.
|
||
|
|
<br><dt><code>Wfr</code><dd>Any memory reference to an address in the far address space.
|
||
|
|
<br><dt><code>Wh1</code><dd>A memory reference using <code>HL</code> as a base register, with an optional one-byte offset.
|
||
|
|
<br><dt><code>Whb</code><dd>A memory reference using <code>HL</code> as a base register, with <code>B</code> or <code>C</code> as the index register.
|
||
|
|
<br><dt><code>Whl</code><dd>A memory reference using <code>HL</code> as a base register, without any offset.
|
||
|
|
<br><dt><code>Ws1</code><dd>A memory reference using <code>SP</code> as a base register, with an optional one-byte offset.
|
||
|
|
<br><dt><code>Y</code><dd>Any memory reference to an address in the near address space.
|
||
|
|
<br><dt><code>A</code><dd>The <code>AX</code> register.
|
||
|
|
<br><dt><code>B</code><dd>The <code>BC</code> register.
|
||
|
|
<br><dt><code>D</code><dd>The <code>DE</code> register.
|
||
|
|
<br><dt><code>R</code><dd><code>A</code> through <code>L</code> registers.
|
||
|
|
<br><dt><code>S</code><dd>The <code>SP</code> register.
|
||
|
|
<br><dt><code>T</code><dd>The <code>HL</code> register.
|
||
|
|
<br><dt><code>Z08W</code><dd>The 16-bit <code>R8</code> register.
|
||
|
|
<br><dt><code>Z10W</code><dd>The 16-bit <code>R10</code> register.
|
||
|
|
<br><dt><code>Zint</code><dd>The registers reserved for interrupts (<code>R24</code> to <code>R31</code>).
|
||
|
|
<br><dt><code>a</code><dd>The <code>A</code> register.
|
||
|
|
<br><dt><code>b</code><dd>The <code>B</code> register.
|
||
|
|
<br><dt><code>c</code><dd>The <code>C</code> register.
|
||
|
|
<br><dt><code>d</code><dd>The <code>D</code> register.
|
||
|
|
<br><dt><code>e</code><dd>The <code>E</code> register.
|
||
|
|
<br><dt><code>h</code><dd>The <code>H</code> register.
|
||
|
|
<br><dt><code>l</code><dd>The <code>L</code> register.
|
||
|
|
<br><dt><code>v</code><dd>The virtual registers.
|
||
|
|
<br><dt><code>w</code><dd>The <code>PSW</code> register.
|
||
|
|
<br><dt><code>x</code><dd>The <code>X</code> register.
|
||
|
|
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<br><dt><em>RX—</em><samp><span class="file">config/rx/constraints.md</span></samp><dd>
|
||
|
|
<dl>
|
||
|
|
<dt><code>Q</code><dd>An address which does not involve register indirect addressing or
|
||
|
|
pre/post increment/decrement addressing.
|
||
|
|
|
||
|
|
<br><dt><code>Symbol</code><dd>A symbol reference.
|
||
|
|
|
||
|
|
<br><dt><code>Int08</code><dd>A constant in the range −256 to 255, inclusive.
|
||
|
|
|
||
|
|
<br><dt><code>Sint08</code><dd>A constant in the range −128 to 127, inclusive.
|
||
|
|
|
||
|
|
<br><dt><code>Sint16</code><dd>A constant in the range −32768 to 32767, inclusive.
|
||
|
|
|
||
|
|
<br><dt><code>Sint24</code><dd>A constant in the range −8388608 to 8388607, inclusive.
|
||
|
|
|
||
|
|
<br><dt><code>Uint04</code><dd>A constant in the range 0 to 15, inclusive.
|
||
|
|
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<br><dt><em>S/390 and zSeries—</em><samp><span class="file">config/s390/s390.h</span></samp><dd>
|
||
|
|
<dl>
|
||
|
|
<dt><code>a</code><dd>Address register (general purpose register except r0)
|
||
|
|
|
||
|
|
<br><dt><code>c</code><dd>Condition code register
|
||
|
|
|
||
|
|
<br><dt><code>d</code><dd>Data register (arbitrary general purpose register)
|
||
|
|
|
||
|
|
<br><dt><code>f</code><dd>Floating-point register
|
||
|
|
|
||
|
|
<br><dt><code>I</code><dd>Unsigned 8-bit constant (0–255)
|
||
|
|
|
||
|
|
<br><dt><code>J</code><dd>Unsigned 12-bit constant (0–4095)
|
||
|
|
|
||
|
|
<br><dt><code>K</code><dd>Signed 16-bit constant (−32768–32767)
|
||
|
|
|
||
|
|
<br><dt><code>L</code><dd>Value appropriate as displacement.
|
||
|
|
<dl>
|
||
|
|
<dt><code>(0..4095)</code><dd>for short displacement
|
||
|
|
<br><dt><code>(−524288..524287)</code><dd>for long displacement
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<br><dt><code>M</code><dd>Constant integer with a value of 0x7fffffff.
|
||
|
|
|
||
|
|
<br><dt><code>N</code><dd>Multiple letter constraint followed by 4 parameter letters.
|
||
|
|
<dl>
|
||
|
|
<dt><code>0..9:</code><dd>number of the part counting from most to least significant
|
||
|
|
<br><dt><code>H,Q:</code><dd>mode of the part
|
||
|
|
<br><dt><code>D,S,H:</code><dd>mode of the containing operand
|
||
|
|
<br><dt><code>0,F:</code><dd>value of the other parts (F—all bits set)
|
||
|
|
</dl>
|
||
|
|
The constraint matches if the specified part of a constant
|
||
|
|
has a value different from its other parts.
|
||
|
|
|
||
|
|
<br><dt><code>Q</code><dd>Memory reference without index register and with short displacement.
|
||
|
|
|
||
|
|
<br><dt><code>R</code><dd>Memory reference with index register and short displacement.
|
||
|
|
|
||
|
|
<br><dt><code>S</code><dd>Memory reference without index register but with long displacement.
|
||
|
|
|
||
|
|
<br><dt><code>T</code><dd>Memory reference with index register and long displacement.
|
||
|
|
|
||
|
|
<br><dt><code>U</code><dd>Pointer with short displacement.
|
||
|
|
|
||
|
|
<br><dt><code>W</code><dd>Pointer with long displacement.
|
||
|
|
|
||
|
|
<br><dt><code>Y</code><dd>Shift count operand.
|
||
|
|
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<br><dt><em>SPARC—</em><samp><span class="file">config/sparc/sparc.h</span></samp><dd>
|
||
|
|
<dl>
|
||
|
|
<dt><code>f</code><dd>Floating-point register on the SPARC-V8 architecture and
|
||
|
|
lower floating-point register on the SPARC-V9 architecture.
|
||
|
|
|
||
|
|
<br><dt><code>e</code><dd>Floating-point register. It is equivalent to ‘<samp><span class="samp">f</span></samp>’ on the
|
||
|
|
SPARC-V8 architecture and contains both lower and upper
|
||
|
|
floating-point registers on the SPARC-V9 architecture.
|
||
|
|
|
||
|
|
<br><dt><code>c</code><dd>Floating-point condition code register.
|
||
|
|
|
||
|
|
<br><dt><code>d</code><dd>Lower floating-point register. It is only valid on the SPARC-V9
|
||
|
|
architecture when the Visual Instruction Set is available.
|
||
|
|
|
||
|
|
<br><dt><code>b</code><dd>Floating-point register. It is only valid on the SPARC-V9 architecture
|
||
|
|
when the Visual Instruction Set is available.
|
||
|
|
|
||
|
|
<br><dt><code>h</code><dd>64-bit global or out register for the SPARC-V8+ architecture.
|
||
|
|
|
||
|
|
<br><dt><code>C</code><dd>The constant all-ones, for floating-point.
|
||
|
|
|
||
|
|
<br><dt><code>A</code><dd>Signed 5-bit constant
|
||
|
|
|
||
|
|
<br><dt><code>D</code><dd>A vector constant
|
||
|
|
|
||
|
|
<br><dt><code>I</code><dd>Signed 13-bit constant
|
||
|
|
|
||
|
|
<br><dt><code>J</code><dd>Zero
|
||
|
|
|
||
|
|
<br><dt><code>K</code><dd>32-bit constant with the low 12 bits clear (a constant that can be
|
||
|
|
loaded with the <code>sethi</code> instruction)
|
||
|
|
|
||
|
|
<br><dt><code>L</code><dd>A constant in the range supported by <code>movcc</code> instructions (11-bit
|
||
|
|
signed immediate)
|
||
|
|
|
||
|
|
<br><dt><code>M</code><dd>A constant in the range supported by <code>movrcc</code> instructions (10-bit
|
||
|
|
signed immediate)
|
||
|
|
|
||
|
|
<br><dt><code>N</code><dd>Same as ‘<samp><span class="samp">K</span></samp>’, except that it verifies that bits that are not in the
|
||
|
|
lower 32-bit range are all zero. Must be used instead of ‘<samp><span class="samp">K</span></samp>’ for
|
||
|
|
modes wider than <code>SImode</code>
|
||
|
|
|
||
|
|
<br><dt><code>O</code><dd>The constant 4096
|
||
|
|
|
||
|
|
<br><dt><code>G</code><dd>Floating-point zero
|
||
|
|
|
||
|
|
<br><dt><code>H</code><dd>Signed 13-bit constant, sign-extended to 32 or 64 bits
|
||
|
|
|
||
|
|
<br><dt><code>P</code><dd>The constant -1
|
||
|
|
|
||
|
|
<br><dt><code>Q</code><dd>Floating-point constant whose integral representation can
|
||
|
|
be moved into an integer register using a single sethi
|
||
|
|
instruction
|
||
|
|
|
||
|
|
<br><dt><code>R</code><dd>Floating-point constant whose integral representation can
|
||
|
|
be moved into an integer register using a single mov
|
||
|
|
instruction
|
||
|
|
|
||
|
|
<br><dt><code>S</code><dd>Floating-point constant whose integral representation can
|
||
|
|
be moved into an integer register using a high/lo_sum
|
||
|
|
instruction sequence
|
||
|
|
|
||
|
|
<br><dt><code>T</code><dd>Memory address aligned to an 8-byte boundary
|
||
|
|
|
||
|
|
<br><dt><code>U</code><dd>Even register
|
||
|
|
|
||
|
|
<br><dt><code>W</code><dd>Memory address for ‘<samp><span class="samp">e</span></samp>’ constraint registers
|
||
|
|
|
||
|
|
<br><dt><code>w</code><dd>Memory address with only a base register
|
||
|
|
|
||
|
|
<br><dt><code>Y</code><dd>Vector zero
|
||
|
|
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<br><dt><em>SPU—</em><samp><span class="file">config/spu/spu.h</span></samp><dd>
|
||
|
|
<dl>
|
||
|
|
<dt><code>a</code><dd>An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value.
|
||
|
|
|
||
|
|
<br><dt><code>c</code><dd>An immediate for and/xor/or instructions. const_int is treated as a 64 bit value.
|
||
|
|
|
||
|
|
<br><dt><code>d</code><dd>An immediate for the <code>iohl</code> instruction. const_int is treated as a 64 bit value.
|
||
|
|
|
||
|
|
<br><dt><code>f</code><dd>An immediate which can be loaded with <code>fsmbi</code>.
|
||
|
|
|
||
|
|
<br><dt><code>A</code><dd>An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value.
|
||
|
|
|
||
|
|
<br><dt><code>B</code><dd>An immediate for most arithmetic instructions. const_int is treated as a 32 bit value.
|
||
|
|
|
||
|
|
<br><dt><code>C</code><dd>An immediate for and/xor/or instructions. const_int is treated as a 32 bit value.
|
||
|
|
|
||
|
|
<br><dt><code>D</code><dd>An immediate for the <code>iohl</code> instruction. const_int is treated as a 32 bit value.
|
||
|
|
|
||
|
|
<br><dt><code>I</code><dd>A constant in the range [−64, 63] for shift/rotate instructions.
|
||
|
|
|
||
|
|
<br><dt><code>J</code><dd>An unsigned 7-bit constant for conversion/nop/channel instructions.
|
||
|
|
|
||
|
|
<br><dt><code>K</code><dd>A signed 10-bit constant for most arithmetic instructions.
|
||
|
|
|
||
|
|
<br><dt><code>M</code><dd>A signed 16 bit immediate for <code>stop</code>.
|
||
|
|
|
||
|
|
<br><dt><code>N</code><dd>An unsigned 16-bit constant for <code>iohl</code> and <code>fsmbi</code>.
|
||
|
|
|
||
|
|
<br><dt><code>O</code><dd>An unsigned 7-bit constant whose 3 least significant bits are 0.
|
||
|
|
|
||
|
|
<br><dt><code>P</code><dd>An unsigned 3-bit constant for 16-byte rotates and shifts
|
||
|
|
|
||
|
|
<br><dt><code>R</code><dd>Call operand, reg, for indirect calls
|
||
|
|
|
||
|
|
<br><dt><code>S</code><dd>Call operand, symbol, for relative calls.
|
||
|
|
|
||
|
|
<br><dt><code>T</code><dd>Call operand, const_int, for absolute calls.
|
||
|
|
|
||
|
|
<br><dt><code>U</code><dd>An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit.
|
||
|
|
|
||
|
|
<br><dt><code>W</code><dd>An immediate for shift and rotate instructions. const_int is treated as a 32 bit value.
|
||
|
|
|
||
|
|
<br><dt><code>Y</code><dd>An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit.
|
||
|
|
|
||
|
|
<br><dt><code>Z</code><dd>An immediate for the <code>iohl</code> instruction. const_int is sign extended to 128 bit.
|
||
|
|
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<br><dt><em>TI C6X family—</em><samp><span class="file">config/c6x/constraints.md</span></samp><dd>
|
||
|
|
<dl>
|
||
|
|
<dt><code>a</code><dd>Register file A (A0–A31).
|
||
|
|
|
||
|
|
<br><dt><code>b</code><dd>Register file B (B0–B31).
|
||
|
|
|
||
|
|
<br><dt><code>A</code><dd>Predicate registers in register file A (A0–A2 on C64X and
|
||
|
|
higher, A1 and A2 otherwise).
|
||
|
|
|
||
|
|
<br><dt><code>B</code><dd>Predicate registers in register file B (B0–B2).
|
||
|
|
|
||
|
|
<br><dt><code>C</code><dd>A call-used register in register file B (B0–B9, B16–B31).
|
||
|
|
|
||
|
|
<br><dt><code>Da</code><dd>Register file A, excluding predicate registers (A3–A31,
|
||
|
|
plus A0 if not C64X or higher).
|
||
|
|
|
||
|
|
<br><dt><code>Db</code><dd>Register file B, excluding predicate registers (B3–B31).
|
||
|
|
|
||
|
|
<br><dt><code>Iu4</code><dd>Integer constant in the range 0 <small class="dots">...</small> 15.
|
||
|
|
|
||
|
|
<br><dt><code>Iu5</code><dd>Integer constant in the range 0 <small class="dots">...</small> 31.
|
||
|
|
|
||
|
|
<br><dt><code>In5</code><dd>Integer constant in the range −31 <small class="dots">...</small> 0.
|
||
|
|
|
||
|
|
<br><dt><code>Is5</code><dd>Integer constant in the range −16 <small class="dots">...</small> 15.
|
||
|
|
|
||
|
|
<br><dt><code>I5x</code><dd>Integer constant that can be the operand of an ADDA or a SUBA insn.
|
||
|
|
|
||
|
|
<br><dt><code>IuB</code><dd>Integer constant in the range 0 <small class="dots">...</small> 65535.
|
||
|
|
|
||
|
|
<br><dt><code>IsB</code><dd>Integer constant in the range −32768 <small class="dots">...</small> 32767.
|
||
|
|
|
||
|
|
<br><dt><code>IsC</code><dd>Integer constant in the range -2^20 <small class="dots">...</small> 2^20 - 1.
|
||
|
|
|
||
|
|
<br><dt><code>Jc</code><dd>Integer constant that is a valid mask for the clr instruction.
|
||
|
|
|
||
|
|
<br><dt><code>Js</code><dd>Integer constant that is a valid mask for the set instruction.
|
||
|
|
|
||
|
|
<br><dt><code>Q</code><dd>Memory location with A base register.
|
||
|
|
|
||
|
|
<br><dt><code>R</code><dd>Memory location with B base register.
|
||
|
|
|
||
|
|
<br><dt><code>S0</code><dd>On C64x+ targets, a GP-relative small data reference.
|
||
|
|
|
||
|
|
<br><dt><code>S1</code><dd>Any kind of <code>SYMBOL_REF</code>, for use in a call address.
|
||
|
|
|
||
|
|
<br><dt><code>Si</code><dd>Any kind of immediate operand, unless it matches the S0 constraint.
|
||
|
|
|
||
|
|
<br><dt><code>T</code><dd>Memory location with B base register, but not using a long offset.
|
||
|
|
|
||
|
|
<br><dt><code>W</code><dd>A memory operand with an address that can't be used in an unaligned access.
|
||
|
|
|
||
|
|
<br><dt><code>Z</code><dd>Register B14 (aka DP).
|
||
|
|
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<br><dt><em>TILE-Gx—</em><samp><span class="file">config/tilegx/constraints.md</span></samp><dd>
|
||
|
|
<dl>
|
||
|
|
<dt><code>R00</code><dt><code>R01</code><dt><code>R02</code><dt><code>R03</code><dt><code>R04</code><dt><code>R05</code><dt><code>R06</code><dt><code>R07</code><dt><code>R08</code><dt><code>R09</code><dt><code>R10</code><dd>Each of these represents a register constraint for an individual
|
||
|
|
register, from r0 to r10.
|
||
|
|
|
||
|
|
<br><dt><code>I</code><dd>Signed 8-bit integer constant.
|
||
|
|
|
||
|
|
<br><dt><code>J</code><dd>Signed 16-bit integer constant.
|
||
|
|
|
||
|
|
<br><dt><code>K</code><dd>Unsigned 16-bit integer constant.
|
||
|
|
|
||
|
|
<br><dt><code>L</code><dd>Integer constant that fits in one signed byte when incremented by one
|
||
|
|
(−129 <small class="dots">...</small> 126).
|
||
|
|
|
||
|
|
<br><dt><code>m</code><dd>Memory operand. If used together with ‘<samp><span class="samp"><</span></samp>’ or ‘<samp><span class="samp">></span></samp>’, the
|
||
|
|
operand can have postincrement which requires printing with ‘<samp><span class="samp">%In</span></samp>’
|
||
|
|
and ‘<samp><span class="samp">%in</span></samp>’ on TILE-Gx. For example:
|
||
|
|
|
||
|
|
<pre class="smallexample"> asm ("st_add %I0,%1,%i0" : "=m<>" (*mem) : "r" (val));
|
||
|
|
</pre>
|
||
|
|
<br><dt><code>M</code><dd>A bit mask suitable for the BFINS instruction.
|
||
|
|
|
||
|
|
<br><dt><code>N</code><dd>Integer constant that is a byte tiled out eight times.
|
||
|
|
|
||
|
|
<br><dt><code>O</code><dd>The integer zero constant.
|
||
|
|
|
||
|
|
<br><dt><code>P</code><dd>Integer constant that is a sign-extended byte tiled out as four shorts.
|
||
|
|
|
||
|
|
<br><dt><code>Q</code><dd>Integer constant that fits in one signed byte when incremented
|
||
|
|
(−129 <small class="dots">...</small> 126), but excluding -1.
|
||
|
|
|
||
|
|
<br><dt><code>S</code><dd>Integer constant that has all 1 bits consecutive and starting at bit 0.
|
||
|
|
|
||
|
|
<br><dt><code>T</code><dd>A 16-bit fragment of a got, tls, or pc-relative reference.
|
||
|
|
|
||
|
|
<br><dt><code>U</code><dd>Memory operand except postincrement. This is roughly the same as
|
||
|
|
‘<samp><span class="samp">m</span></samp>’ when not used together with ‘<samp><span class="samp"><</span></samp>’ or ‘<samp><span class="samp">></span></samp>’.
|
||
|
|
|
||
|
|
<br><dt><code>W</code><dd>An 8-element vector constant with identical elements.
|
||
|
|
|
||
|
|
<br><dt><code>Y</code><dd>A 4-element vector constant with identical elements.
|
||
|
|
|
||
|
|
<br><dt><code>Z0</code><dd>The integer constant 0xffffffff.
|
||
|
|
|
||
|
|
<br><dt><code>Z1</code><dd>The integer constant 0xffffffff00000000.
|
||
|
|
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<br><dt><em>TILEPro—</em><samp><span class="file">config/tilepro/constraints.md</span></samp><dd>
|
||
|
|
<dl>
|
||
|
|
<dt><code>R00</code><dt><code>R01</code><dt><code>R02</code><dt><code>R03</code><dt><code>R04</code><dt><code>R05</code><dt><code>R06</code><dt><code>R07</code><dt><code>R08</code><dt><code>R09</code><dt><code>R10</code><dd>Each of these represents a register constraint for an individual
|
||
|
|
register, from r0 to r10.
|
||
|
|
|
||
|
|
<br><dt><code>I</code><dd>Signed 8-bit integer constant.
|
||
|
|
|
||
|
|
<br><dt><code>J</code><dd>Signed 16-bit integer constant.
|
||
|
|
|
||
|
|
<br><dt><code>K</code><dd>Nonzero integer constant with low 16 bits zero.
|
||
|
|
|
||
|
|
<br><dt><code>L</code><dd>Integer constant that fits in one signed byte when incremented by one
|
||
|
|
(−129 <small class="dots">...</small> 126).
|
||
|
|
|
||
|
|
<br><dt><code>m</code><dd>Memory operand. If used together with ‘<samp><span class="samp"><</span></samp>’ or ‘<samp><span class="samp">></span></samp>’, the
|
||
|
|
operand can have postincrement which requires printing with ‘<samp><span class="samp">%In</span></samp>’
|
||
|
|
and ‘<samp><span class="samp">%in</span></samp>’ on TILEPro. For example:
|
||
|
|
|
||
|
|
<pre class="smallexample"> asm ("swadd %I0,%1,%i0" : "=m<>" (mem) : "r" (val));
|
||
|
|
</pre>
|
||
|
|
<br><dt><code>M</code><dd>A bit mask suitable for the MM instruction.
|
||
|
|
|
||
|
|
<br><dt><code>N</code><dd>Integer constant that is a byte tiled out four times.
|
||
|
|
|
||
|
|
<br><dt><code>O</code><dd>The integer zero constant.
|
||
|
|
|
||
|
|
<br><dt><code>P</code><dd>Integer constant that is a sign-extended byte tiled out as two shorts.
|
||
|
|
|
||
|
|
<br><dt><code>Q</code><dd>Integer constant that fits in one signed byte when incremented
|
||
|
|
(−129 <small class="dots">...</small> 126), but excluding -1.
|
||
|
|
|
||
|
|
<br><dt><code>T</code><dd>A symbolic operand, or a 16-bit fragment of a got, tls, or pc-relative
|
||
|
|
reference.
|
||
|
|
|
||
|
|
<br><dt><code>U</code><dd>Memory operand except postincrement. This is roughly the same as
|
||
|
|
‘<samp><span class="samp">m</span></samp>’ when not used together with ‘<samp><span class="samp"><</span></samp>’ or ‘<samp><span class="samp">></span></samp>’.
|
||
|
|
|
||
|
|
<br><dt><code>W</code><dd>A 4-element vector constant with identical elements.
|
||
|
|
|
||
|
|
<br><dt><code>Y</code><dd>A 2-element vector constant with identical elements.
|
||
|
|
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<br><dt><em>Visium—</em><samp><span class="file">config/visium/constraints.md</span></samp><dd>
|
||
|
|
<dl>
|
||
|
|
<dt><code>b</code><dd>EAM register <code>mdb</code>
|
||
|
|
|
||
|
|
<br><dt><code>c</code><dd>EAM register <code>mdc</code>
|
||
|
|
|
||
|
|
<br><dt><code>f</code><dd>Floating point register
|
||
|
|
|
||
|
|
<br><dt><code>k</code><dd>Register for sibcall optimization
|
||
|
|
|
||
|
|
<br><dt><code>l</code><dd>General register, but not <code>r29</code>, <code>r30</code> and <code>r31</code>
|
||
|
|
|
||
|
|
<br><dt><code>t</code><dd>Register <code>r1</code>
|
||
|
|
|
||
|
|
<br><dt><code>u</code><dd>Register <code>r2</code>
|
||
|
|
|
||
|
|
<br><dt><code>v</code><dd>Register <code>r3</code>
|
||
|
|
|
||
|
|
<br><dt><code>G</code><dd>Floating-point constant 0.0
|
||
|
|
|
||
|
|
<br><dt><code>J</code><dd>Integer constant in the range 0 .. 65535 (16-bit immediate)
|
||
|
|
|
||
|
|
<br><dt><code>K</code><dd>Integer constant in the range 1 .. 31 (5-bit immediate)
|
||
|
|
|
||
|
|
<br><dt><code>L</code><dd>Integer constant in the range −65535 .. −1 (16-bit negative immediate)
|
||
|
|
|
||
|
|
<br><dt><code>M</code><dd>Integer constant −1
|
||
|
|
|
||
|
|
<br><dt><code>O</code><dd>Integer constant 0
|
||
|
|
|
||
|
|
<br><dt><code>P</code><dd>Integer constant 32
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<br><dt><em>x86 family—</em><samp><span class="file">config/i386/constraints.md</span></samp><dd>
|
||
|
|
<dl>
|
||
|
|
<dt><code>R</code><dd>Legacy register—the eight integer registers available on all
|
||
|
|
i386 processors (<code>a</code>, <code>b</code>, <code>c</code>, <code>d</code>,
|
||
|
|
<code>si</code>, <code>di</code>, <code>bp</code>, <code>sp</code>).
|
||
|
|
|
||
|
|
<br><dt><code>q</code><dd>Any register accessible as <var>r</var><code>l</code>. In 32-bit mode, <code>a</code>,
|
||
|
|
<code>b</code>, <code>c</code>, and <code>d</code>; in 64-bit mode, any integer register.
|
||
|
|
|
||
|
|
<br><dt><code>Q</code><dd>Any register accessible as <var>r</var><code>h</code>: <code>a</code>, <code>b</code>,
|
||
|
|
<code>c</code>, and <code>d</code>.
|
||
|
|
|
||
|
|
<br><dt><code>l</code><dd>Any register that can be used as the index in a base+index memory
|
||
|
|
access: that is, any general register except the stack pointer.
|
||
|
|
|
||
|
|
<br><dt><code>a</code><dd>The <code>a</code> register.
|
||
|
|
|
||
|
|
<br><dt><code>b</code><dd>The <code>b</code> register.
|
||
|
|
|
||
|
|
<br><dt><code>c</code><dd>The <code>c</code> register.
|
||
|
|
|
||
|
|
<br><dt><code>d</code><dd>The <code>d</code> register.
|
||
|
|
|
||
|
|
<br><dt><code>S</code><dd>The <code>si</code> register.
|
||
|
|
|
||
|
|
<br><dt><code>D</code><dd>The <code>di</code> register.
|
||
|
|
|
||
|
|
<br><dt><code>A</code><dd>The <code>a</code> and <code>d</code> registers. This class is used for instructions
|
||
|
|
that return double word results in the <code>ax:dx</code> register pair. Single
|
||
|
|
word values will be allocated either in <code>ax</code> or <code>dx</code>.
|
||
|
|
For example on i386 the following implements <code>rdtsc</code>:
|
||
|
|
|
||
|
|
<pre class="smallexample"> unsigned long long rdtsc (void)
|
||
|
|
{
|
||
|
|
unsigned long long tick;
|
||
|
|
__asm__ __volatile__("rdtsc":"=A"(tick));
|
||
|
|
return tick;
|
||
|
|
}
|
||
|
|
</pre>
|
||
|
|
<p>This is not correct on x86-64 as it would allocate tick in either <code>ax</code>
|
||
|
|
or <code>dx</code>. You have to use the following variant instead:
|
||
|
|
|
||
|
|
<pre class="smallexample"> unsigned long long rdtsc (void)
|
||
|
|
{
|
||
|
|
unsigned int tickl, tickh;
|
||
|
|
__asm__ __volatile__("rdtsc":"=a"(tickl),"=d"(tickh));
|
||
|
|
return ((unsigned long long)tickh << 32)|tickl;
|
||
|
|
}
|
||
|
|
</pre>
|
||
|
|
<br><dt><code>f</code><dd>Any 80387 floating-point (stack) register.
|
||
|
|
|
||
|
|
<br><dt><code>t</code><dd>Top of 80387 floating-point stack (<code>%st(0)</code>).
|
||
|
|
|
||
|
|
<br><dt><code>u</code><dd>Second from top of 80387 floating-point stack (<code>%st(1)</code>).
|
||
|
|
|
||
|
|
<br><dt><code>y</code><dd>Any MMX register.
|
||
|
|
|
||
|
|
<br><dt><code>x</code><dd>Any SSE register.
|
||
|
|
|
||
|
|
<br><dt><code>Yz</code><dd>First SSE register (<code>%xmm0</code>).
|
||
|
|
|
||
|
|
<br><dt><code>Y2</code><dd>Any SSE register, when SSE2 is enabled.
|
||
|
|
|
||
|
|
<br><dt><code>Yi</code><dd>Any SSE register, when SSE2 and inter-unit moves are enabled.
|
||
|
|
|
||
|
|
<br><dt><code>Ym</code><dd>Any MMX register, when inter-unit moves are enabled.
|
||
|
|
|
||
|
|
<br><dt><code>I</code><dd>Integer constant in the range 0 <small class="dots">...</small> 31, for 32-bit shifts.
|
||
|
|
|
||
|
|
<br><dt><code>J</code><dd>Integer constant in the range 0 <small class="dots">...</small> 63, for 64-bit shifts.
|
||
|
|
|
||
|
|
<br><dt><code>K</code><dd>Signed 8-bit integer constant.
|
||
|
|
|
||
|
|
<br><dt><code>L</code><dd><code>0xFF</code> or <code>0xFFFF</code>, for andsi as a zero-extending move.
|
||
|
|
|
||
|
|
<br><dt><code>M</code><dd>0, 1, 2, or 3 (shifts for the <code>lea</code> instruction).
|
||
|
|
|
||
|
|
<br><dt><code>N</code><dd>Unsigned 8-bit integer constant (for <code>in</code> and <code>out</code>
|
||
|
|
instructions).
|
||
|
|
|
||
|
|
<br><dt><code>O</code><dd>Integer constant in the range 0 <small class="dots">...</small> 127, for 128-bit shifts.
|
||
|
|
|
||
|
|
<br><dt><code>G</code><dd>Standard 80387 floating point constant.
|
||
|
|
|
||
|
|
<br><dt><code>C</code><dd>SSE constant zero operand.
|
||
|
|
|
||
|
|
<br><dt><code>e</code><dd>32-bit signed integer constant, or a symbolic reference known
|
||
|
|
to fit that range (for immediate operands in sign-extending x86-64
|
||
|
|
instructions).
|
||
|
|
|
||
|
|
<br><dt><code>Z</code><dd>32-bit unsigned integer constant, or a symbolic reference known
|
||
|
|
to fit that range (for immediate operands in zero-extending x86-64
|
||
|
|
instructions).
|
||
|
|
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<br><dt><em>Xstormy16—</em><samp><span class="file">config/stormy16/stormy16.h</span></samp><dd>
|
||
|
|
<dl>
|
||
|
|
<dt><code>a</code><dd>Register r0.
|
||
|
|
|
||
|
|
<br><dt><code>b</code><dd>Register r1.
|
||
|
|
|
||
|
|
<br><dt><code>c</code><dd>Register r2.
|
||
|
|
|
||
|
|
<br><dt><code>d</code><dd>Register r8.
|
||
|
|
|
||
|
|
<br><dt><code>e</code><dd>Registers r0 through r7.
|
||
|
|
|
||
|
|
<br><dt><code>t</code><dd>Registers r0 and r1.
|
||
|
|
|
||
|
|
<br><dt><code>y</code><dd>The carry register.
|
||
|
|
|
||
|
|
<br><dt><code>z</code><dd>Registers r8 and r9.
|
||
|
|
|
||
|
|
<br><dt><code>I</code><dd>A constant between 0 and 3 inclusive.
|
||
|
|
|
||
|
|
<br><dt><code>J</code><dd>A constant that has exactly one bit set.
|
||
|
|
|
||
|
|
<br><dt><code>K</code><dd>A constant that has exactly one bit clear.
|
||
|
|
|
||
|
|
<br><dt><code>L</code><dd>A constant between 0 and 255 inclusive.
|
||
|
|
|
||
|
|
<br><dt><code>M</code><dd>A constant between −255 and 0 inclusive.
|
||
|
|
|
||
|
|
<br><dt><code>N</code><dd>A constant between −3 and 0 inclusive.
|
||
|
|
|
||
|
|
<br><dt><code>O</code><dd>A constant between 1 and 4 inclusive.
|
||
|
|
|
||
|
|
<br><dt><code>P</code><dd>A constant between −4 and −1 inclusive.
|
||
|
|
|
||
|
|
<br><dt><code>Q</code><dd>A memory reference that is a stack push.
|
||
|
|
|
||
|
|
<br><dt><code>R</code><dd>A memory reference that is a stack pop.
|
||
|
|
|
||
|
|
<br><dt><code>S</code><dd>A memory reference that refers to a constant address of known value.
|
||
|
|
|
||
|
|
<br><dt><code>T</code><dd>The register indicated by Rx (not implemented yet).
|
||
|
|
|
||
|
|
<br><dt><code>U</code><dd>A constant that is not between 2 and 15 inclusive.
|
||
|
|
|
||
|
|
<br><dt><code>Z</code><dd>The constant 0.
|
||
|
|
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<br><dt><em>Xtensa—</em><samp><span class="file">config/xtensa/constraints.md</span></samp><dd>
|
||
|
|
<dl>
|
||
|
|
<dt><code>a</code><dd>General-purpose 32-bit register
|
||
|
|
|
||
|
|
<br><dt><code>b</code><dd>One-bit boolean register
|
||
|
|
|
||
|
|
<br><dt><code>A</code><dd>MAC16 40-bit accumulator register
|
||
|
|
|
||
|
|
<br><dt><code>I</code><dd>Signed 12-bit integer constant, for use in MOVI instructions
|
||
|
|
|
||
|
|
<br><dt><code>J</code><dd>Signed 8-bit integer constant, for use in ADDI instructions
|
||
|
|
|
||
|
|
<br><dt><code>K</code><dd>Integer constant valid for BccI instructions
|
||
|
|
|
||
|
|
<br><dt><code>L</code><dd>Unsigned constant valid for BccUI instructions
|
||
|
|
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
</body></html>
|
||
|
|
|