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170 lines
15 KiB
C
170 lines
15 KiB
C
4 years ago
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/**
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* \brief Component description for PCC
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*
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* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
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*
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* Subject to your compliance with these terms, you may use Microchip software and any derivatives
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* exclusively with Microchip products. It is your responsibility to comply with third party license
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* terms applicable to your use of third party software (including open source software) that may
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* accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
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* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
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* FITNESS FOR A PARTICULAR PURPOSE.
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*
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* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
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* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
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* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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*/
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/* file generated from device description version 2020-03-12T17:27:04Z */
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#ifndef _SAME54_PCC_COMPONENT_H_
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#define _SAME54_PCC_COMPONENT_H_
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/* ************************************************************************** */
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/* SOFTWARE API DEFINITION FOR PCC */
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/* ************************************************************************** */
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/* -------- PCC_MR : (PCC Offset: 0x00) (R/W 32) Mode Register -------- */
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#define PCC_MR_RESETVALUE _U_(0x00) /**< (PCC_MR) Mode Register Reset Value */
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#define PCC_MR_PCEN_Pos _U_(0) /**< (PCC_MR) Parallel Capture Enable Position */
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#define PCC_MR_PCEN_Msk (_U_(0x1) << PCC_MR_PCEN_Pos) /**< (PCC_MR) Parallel Capture Enable Mask */
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#define PCC_MR_PCEN(value) (PCC_MR_PCEN_Msk & ((value) << PCC_MR_PCEN_Pos))
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#define PCC_MR_DSIZE_Pos _U_(4) /**< (PCC_MR) Data size Position */
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#define PCC_MR_DSIZE_Msk (_U_(0x3) << PCC_MR_DSIZE_Pos) /**< (PCC_MR) Data size Mask */
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#define PCC_MR_DSIZE(value) (PCC_MR_DSIZE_Msk & ((value) << PCC_MR_DSIZE_Pos))
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#define PCC_MR_SCALE_Pos _U_(8) /**< (PCC_MR) Scale data Position */
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#define PCC_MR_SCALE_Msk (_U_(0x1) << PCC_MR_SCALE_Pos) /**< (PCC_MR) Scale data Mask */
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#define PCC_MR_SCALE(value) (PCC_MR_SCALE_Msk & ((value) << PCC_MR_SCALE_Pos))
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#define PCC_MR_ALWYS_Pos _U_(9) /**< (PCC_MR) Always Sampling Position */
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#define PCC_MR_ALWYS_Msk (_U_(0x1) << PCC_MR_ALWYS_Pos) /**< (PCC_MR) Always Sampling Mask */
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#define PCC_MR_ALWYS(value) (PCC_MR_ALWYS_Msk & ((value) << PCC_MR_ALWYS_Pos))
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#define PCC_MR_HALFS_Pos _U_(10) /**< (PCC_MR) Half Sampling Position */
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#define PCC_MR_HALFS_Msk (_U_(0x1) << PCC_MR_HALFS_Pos) /**< (PCC_MR) Half Sampling Mask */
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#define PCC_MR_HALFS(value) (PCC_MR_HALFS_Msk & ((value) << PCC_MR_HALFS_Pos))
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#define PCC_MR_FRSTS_Pos _U_(11) /**< (PCC_MR) First sample Position */
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#define PCC_MR_FRSTS_Msk (_U_(0x1) << PCC_MR_FRSTS_Pos) /**< (PCC_MR) First sample Mask */
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#define PCC_MR_FRSTS(value) (PCC_MR_FRSTS_Msk & ((value) << PCC_MR_FRSTS_Pos))
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#define PCC_MR_ISIZE_Pos _U_(16) /**< (PCC_MR) Input Data Size Position */
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#define PCC_MR_ISIZE_Msk (_U_(0x7) << PCC_MR_ISIZE_Pos) /**< (PCC_MR) Input Data Size Mask */
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#define PCC_MR_ISIZE(value) (PCC_MR_ISIZE_Msk & ((value) << PCC_MR_ISIZE_Pos))
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#define PCC_MR_CID_Pos _U_(30) /**< (PCC_MR) Clear If Disabled Position */
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#define PCC_MR_CID_Msk (_U_(0x3) << PCC_MR_CID_Pos) /**< (PCC_MR) Clear If Disabled Mask */
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#define PCC_MR_CID(value) (PCC_MR_CID_Msk & ((value) << PCC_MR_CID_Pos))
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#define PCC_MR_Msk _U_(0xC0070F31) /**< (PCC_MR) Register Mask */
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/* -------- PCC_IER : (PCC Offset: 0x04) ( /W 32) Interrupt Enable Register -------- */
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#define PCC_IER_RESETVALUE _U_(0x00) /**< (PCC_IER) Interrupt Enable Register Reset Value */
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#define PCC_IER_DRDY_Pos _U_(0) /**< (PCC_IER) Data Ready Interrupt Enable Position */
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#define PCC_IER_DRDY_Msk (_U_(0x1) << PCC_IER_DRDY_Pos) /**< (PCC_IER) Data Ready Interrupt Enable Mask */
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#define PCC_IER_DRDY(value) (PCC_IER_DRDY_Msk & ((value) << PCC_IER_DRDY_Pos))
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#define PCC_IER_OVRE_Pos _U_(1) /**< (PCC_IER) Overrun Error Interrupt Enable Position */
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#define PCC_IER_OVRE_Msk (_U_(0x1) << PCC_IER_OVRE_Pos) /**< (PCC_IER) Overrun Error Interrupt Enable Mask */
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#define PCC_IER_OVRE(value) (PCC_IER_OVRE_Msk & ((value) << PCC_IER_OVRE_Pos))
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#define PCC_IER_Msk _U_(0x00000003) /**< (PCC_IER) Register Mask */
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/* -------- PCC_IDR : (PCC Offset: 0x08) ( /W 32) Interrupt Disable Register -------- */
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#define PCC_IDR_RESETVALUE _U_(0x00) /**< (PCC_IDR) Interrupt Disable Register Reset Value */
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#define PCC_IDR_DRDY_Pos _U_(0) /**< (PCC_IDR) Data Ready Interrupt Disable Position */
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#define PCC_IDR_DRDY_Msk (_U_(0x1) << PCC_IDR_DRDY_Pos) /**< (PCC_IDR) Data Ready Interrupt Disable Mask */
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#define PCC_IDR_DRDY(value) (PCC_IDR_DRDY_Msk & ((value) << PCC_IDR_DRDY_Pos))
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#define PCC_IDR_OVRE_Pos _U_(1) /**< (PCC_IDR) Overrun Error Interrupt Disable Position */
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#define PCC_IDR_OVRE_Msk (_U_(0x1) << PCC_IDR_OVRE_Pos) /**< (PCC_IDR) Overrun Error Interrupt Disable Mask */
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#define PCC_IDR_OVRE(value) (PCC_IDR_OVRE_Msk & ((value) << PCC_IDR_OVRE_Pos))
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#define PCC_IDR_Msk _U_(0x00000003) /**< (PCC_IDR) Register Mask */
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/* -------- PCC_IMR : (PCC Offset: 0x0C) ( R/ 32) Interrupt Mask Register -------- */
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#define PCC_IMR_RESETVALUE _U_(0x00) /**< (PCC_IMR) Interrupt Mask Register Reset Value */
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#define PCC_IMR_DRDY_Pos _U_(0) /**< (PCC_IMR) Data Ready Interrupt Mask Position */
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#define PCC_IMR_DRDY_Msk (_U_(0x1) << PCC_IMR_DRDY_Pos) /**< (PCC_IMR) Data Ready Interrupt Mask Mask */
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#define PCC_IMR_DRDY(value) (PCC_IMR_DRDY_Msk & ((value) << PCC_IMR_DRDY_Pos))
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#define PCC_IMR_OVRE_Pos _U_(1) /**< (PCC_IMR) Overrun Error Interrupt Mask Position */
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#define PCC_IMR_OVRE_Msk (_U_(0x1) << PCC_IMR_OVRE_Pos) /**< (PCC_IMR) Overrun Error Interrupt Mask Mask */
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#define PCC_IMR_OVRE(value) (PCC_IMR_OVRE_Msk & ((value) << PCC_IMR_OVRE_Pos))
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#define PCC_IMR_Msk _U_(0x00000003) /**< (PCC_IMR) Register Mask */
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/* -------- PCC_ISR : (PCC Offset: 0x10) ( R/ 32) Interrupt Status Register -------- */
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#define PCC_ISR_RESETVALUE _U_(0x00) /**< (PCC_ISR) Interrupt Status Register Reset Value */
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#define PCC_ISR_DRDY_Pos _U_(0) /**< (PCC_ISR) Data Ready Interrupt Status Position */
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#define PCC_ISR_DRDY_Msk (_U_(0x1) << PCC_ISR_DRDY_Pos) /**< (PCC_ISR) Data Ready Interrupt Status Mask */
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#define PCC_ISR_DRDY(value) (PCC_ISR_DRDY_Msk & ((value) << PCC_ISR_DRDY_Pos))
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#define PCC_ISR_OVRE_Pos _U_(1) /**< (PCC_ISR) Overrun Error Interrupt Status Position */
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#define PCC_ISR_OVRE_Msk (_U_(0x1) << PCC_ISR_OVRE_Pos) /**< (PCC_ISR) Overrun Error Interrupt Status Mask */
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#define PCC_ISR_OVRE(value) (PCC_ISR_OVRE_Msk & ((value) << PCC_ISR_OVRE_Pos))
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#define PCC_ISR_Msk _U_(0x00000003) /**< (PCC_ISR) Register Mask */
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/* -------- PCC_RHR : (PCC Offset: 0x14) ( R/ 32) Reception Holding Register -------- */
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#define PCC_RHR_RESETVALUE _U_(0x00) /**< (PCC_RHR) Reception Holding Register Reset Value */
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#define PCC_RHR_RDATA_Pos _U_(0) /**< (PCC_RHR) Reception Data Position */
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#define PCC_RHR_RDATA_Msk (_U_(0xFFFFFFFF) << PCC_RHR_RDATA_Pos) /**< (PCC_RHR) Reception Data Mask */
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#define PCC_RHR_RDATA(value) (PCC_RHR_RDATA_Msk & ((value) << PCC_RHR_RDATA_Pos))
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#define PCC_RHR_Msk _U_(0xFFFFFFFF) /**< (PCC_RHR) Register Mask */
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/* -------- PCC_WPMR : (PCC Offset: 0xE0) (R/W 32) Write Protection Mode Register -------- */
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#define PCC_WPMR_RESETVALUE _U_(0x00) /**< (PCC_WPMR) Write Protection Mode Register Reset Value */
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#define PCC_WPMR_WPEN_Pos _U_(0) /**< (PCC_WPMR) Write Protection Enable Position */
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#define PCC_WPMR_WPEN_Msk (_U_(0x1) << PCC_WPMR_WPEN_Pos) /**< (PCC_WPMR) Write Protection Enable Mask */
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#define PCC_WPMR_WPEN(value) (PCC_WPMR_WPEN_Msk & ((value) << PCC_WPMR_WPEN_Pos))
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#define PCC_WPMR_WPKEY_Pos _U_(8) /**< (PCC_WPMR) Write Protection Key Position */
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#define PCC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << PCC_WPMR_WPKEY_Pos) /**< (PCC_WPMR) Write Protection Key Mask */
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#define PCC_WPMR_WPKEY(value) (PCC_WPMR_WPKEY_Msk & ((value) << PCC_WPMR_WPKEY_Pos))
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#define PCC_WPMR_Msk _U_(0xFFFFFF01) /**< (PCC_WPMR) Register Mask */
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/* -------- PCC_WPSR : (PCC Offset: 0xE4) ( R/ 32) Write Protection Status Register -------- */
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#define PCC_WPSR_RESETVALUE _U_(0x00) /**< (PCC_WPSR) Write Protection Status Register Reset Value */
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#define PCC_WPSR_WPVS_Pos _U_(0) /**< (PCC_WPSR) Write Protection Violation Source Position */
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#define PCC_WPSR_WPVS_Msk (_U_(0x1) << PCC_WPSR_WPVS_Pos) /**< (PCC_WPSR) Write Protection Violation Source Mask */
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#define PCC_WPSR_WPVS(value) (PCC_WPSR_WPVS_Msk & ((value) << PCC_WPSR_WPVS_Pos))
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#define PCC_WPSR_WPVSRC_Pos _U_(8) /**< (PCC_WPSR) Write Protection Violation Status Position */
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#define PCC_WPSR_WPVSRC_Msk (_U_(0xFFFF) << PCC_WPSR_WPVSRC_Pos) /**< (PCC_WPSR) Write Protection Violation Status Mask */
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#define PCC_WPSR_WPVSRC(value) (PCC_WPSR_WPVSRC_Msk & ((value) << PCC_WPSR_WPVSRC_Pos))
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#define PCC_WPSR_Msk _U_(0x00FFFF01) /**< (PCC_WPSR) Register Mask */
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/** \brief PCC register offsets definitions */
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#define PCC_MR_REG_OFST (0x00) /**< (PCC_MR) Mode Register Offset */
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#define PCC_IER_REG_OFST (0x04) /**< (PCC_IER) Interrupt Enable Register Offset */
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#define PCC_IDR_REG_OFST (0x08) /**< (PCC_IDR) Interrupt Disable Register Offset */
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#define PCC_IMR_REG_OFST (0x0C) /**< (PCC_IMR) Interrupt Mask Register Offset */
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#define PCC_ISR_REG_OFST (0x10) /**< (PCC_ISR) Interrupt Status Register Offset */
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#define PCC_RHR_REG_OFST (0x14) /**< (PCC_RHR) Reception Holding Register Offset */
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#define PCC_WPMR_REG_OFST (0xE0) /**< (PCC_WPMR) Write Protection Mode Register Offset */
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#define PCC_WPSR_REG_OFST (0xE4) /**< (PCC_WPSR) Write Protection Status Register Offset */
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#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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/** \brief PCC register API structure */
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typedef struct
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{ /* Parallel Capture Controller */
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__IO uint32_t PCC_MR; /**< Offset: 0x00 (R/W 32) Mode Register */
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__O uint32_t PCC_IER; /**< Offset: 0x04 ( /W 32) Interrupt Enable Register */
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__O uint32_t PCC_IDR; /**< Offset: 0x08 ( /W 32) Interrupt Disable Register */
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__I uint32_t PCC_IMR; /**< Offset: 0x0C (R/ 32) Interrupt Mask Register */
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__I uint32_t PCC_ISR; /**< Offset: 0x10 (R/ 32) Interrupt Status Register */
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__I uint32_t PCC_RHR; /**< Offset: 0x14 (R/ 32) Reception Holding Register */
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__I uint8_t Reserved1[0xC8];
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__IO uint32_t PCC_WPMR; /**< Offset: 0xE0 (R/W 32) Write Protection Mode Register */
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__I uint32_t PCC_WPSR; /**< Offset: 0xE4 (R/ 32) Write Protection Status Register */
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} pcc_registers_t;
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#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAME54_PCC_COMPONENT_H_ */
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