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277 lines
11 KiB
Plaintext
277 lines
11 KiB
Plaintext
4 years ago
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e54testdir.elf: file format elf32-littlearm
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .text 000003d0 00000000 00000000 00010000 2**2
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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1 .relocate 00000000 20000000 20000000 000103d0 2**0
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CONTENTS
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2 .bkupram 00000000 47000000 47000000 000103d0 2**0
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CONTENTS
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3 .qspi 00000000 04000000 04000000 000103d0 2**0
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CONTENTS
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4 .bss 0000001c 20000000 20000000 00020000 2**2
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ALLOC
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5 .stack 00010004 2000001c 2000001c 00020000 2**0
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ALLOC
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6 .ARM.attributes 0000002e 00000000 00000000 000103d0 2**0
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CONTENTS, READONLY
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7 .comment 0000001e 00000000 00000000 000103fe 2**0
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CONTENTS, READONLY
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8 .debug_info 00000d0a 00000000 00000000 0001041c 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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9 .debug_abbrev 00000200 00000000 00000000 00011126 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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10 .debug_aranges 00000048 00000000 00000000 00011326 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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11 .debug_ranges 00000028 00000000 00000000 0001136e 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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12 .debug_macro 00026037 00000000 00000000 00011396 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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13 .debug_line 00000cd8 00000000 00000000 000373cd 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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14 .debug_str 000f108b 00000000 00000000 000380a5 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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15 .debug_frame 000000cc 00000000 00000000 00129130 2**2
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CONTENTS, READONLY, DEBUGGING, OCTETS
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Disassembly of section .text:
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00000000 <exception_table>:
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0: 20 00 01 20 a9 02 00 00 a5 02 00 00 a5 02 00 00 .. ............
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10: a5 02 00 00 a5 02 00 00 a5 02 00 00 00 00 00 00 ................
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...
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2c: a5 02 00 00 a5 02 00 00 00 00 00 00 a5 02 00 00 ................
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3c: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................
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4c: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................
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5c: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................
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6c: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................
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7c: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................
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8c: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................
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9c: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................
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ac: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................
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bc: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................
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cc: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................
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dc: a5 02 00 00 a5 02 00 00 a5 02 00 00 00 00 00 00 ................
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...
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f4: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................
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104: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................
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114: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................
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124: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................
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134: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................
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144: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................
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154: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................
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164: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................
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174: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................
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184: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................
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194: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................
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1a4: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................
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1b4: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................
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1c4: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................
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1d4: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................
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1e4: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................
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1f4: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................
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204: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................
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214: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................
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224: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................
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234: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................
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244: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................
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254: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................
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00000264 <__do_global_dtors_aux>:
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264: b510 push {r4, lr}
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266: 4c05 ldr r4, [pc, #20] ; (27c <__do_global_dtors_aux+0x18>)
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268: 7823 ldrb r3, [r4, #0]
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26a: b933 cbnz r3, 27a <__do_global_dtors_aux+0x16>
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26c: 4b04 ldr r3, [pc, #16] ; (280 <__do_global_dtors_aux+0x1c>)
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26e: b113 cbz r3, 276 <__do_global_dtors_aux+0x12>
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270: 4804 ldr r0, [pc, #16] ; (284 <__do_global_dtors_aux+0x20>)
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272: f3af 8000 nop.w
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276: 2301 movs r3, #1
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278: 7023 strb r3, [r4, #0]
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27a: bd10 pop {r4, pc}
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27c: 20000000 .word 0x20000000
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280: 00000000 .word 0x00000000
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284: 000003d0 .word 0x000003d0
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00000288 <frame_dummy>:
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288: b508 push {r3, lr}
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28a: 4b03 ldr r3, [pc, #12] ; (298 <frame_dummy+0x10>)
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28c: b11b cbz r3, 296 <frame_dummy+0xe>
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28e: 4903 ldr r1, [pc, #12] ; (29c <frame_dummy+0x14>)
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290: 4803 ldr r0, [pc, #12] ; (2a0 <frame_dummy+0x18>)
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292: f3af 8000 nop.w
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296: bd08 pop {r3, pc}
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298: 00000000 .word 0x00000000
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29c: 20000004 .word 0x20000004
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2a0: 000003d0 .word 0x000003d0
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000002a4 <Dummy_Handler>:
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/**
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* \brief Default interrupt handler for unused IRQs.
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*/
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void Dummy_Handler(void)
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{
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while (1) {
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2a4: e7fe b.n 2a4 <Dummy_Handler>
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...
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000002a8 <Reset_Handler>:
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if (pSrc != pDest) {
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2a8: 4918 ldr r1, [pc, #96] ; (30c <Reset_Handler+0x64>)
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2aa: 4819 ldr r0, [pc, #100] ; (310 <Reset_Handler+0x68>)
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2ac: 4281 cmp r1, r0
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{
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2ae: b510 push {r4, lr}
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if (pSrc != pDest) {
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2b0: d00a beq.n 2c8 <Reset_Handler+0x20>
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*pDest++ = *pSrc++;
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2b2: 4b18 ldr r3, [pc, #96] ; (314 <Reset_Handler+0x6c>)
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2b4: 1cda adds r2, r3, #3
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2b6: 1a12 subs r2, r2, r0
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2b8: f022 0203 bic.w r2, r2, #3
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2bc: 1ec4 subs r4, r0, #3
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2be: 42a3 cmp r3, r4
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2c0: bf38 it cc
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2c2: 2200 movcc r2, #0
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2c4: 4b14 ldr r3, [pc, #80] ; (318 <Reset_Handler+0x70>)
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2c6: 4798 blx r3
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*pDest++ = 0;
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2c8: 4b14 ldr r3, [pc, #80] ; (31c <Reset_Handler+0x74>)
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2ca: 4815 ldr r0, [pc, #84] ; (320 <Reset_Handler+0x78>)
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2cc: 1cda adds r2, r3, #3
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2ce: 1a12 subs r2, r2, r0
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2d0: 1ec1 subs r1, r0, #3
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2d2: f022 0203 bic.w r2, r2, #3
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2d6: 4299 cmp r1, r3
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2d8: bf88 it hi
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2da: 2200 movhi r2, #0
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2dc: 4b11 ldr r3, [pc, #68] ; (324 <Reset_Handler+0x7c>)
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2de: 2100 movs r1, #0
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2e0: 4798 blx r3
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SCB->VTOR = ((uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk);
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2e2: 4a11 ldr r2, [pc, #68] ; (328 <Reset_Handler+0x80>)
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2e4: 4b11 ldr r3, [pc, #68] ; (32c <Reset_Handler+0x84>)
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2e6: f022 027f bic.w r2, r2, #127 ; 0x7f
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2ea: 609a str r2, [r3, #8]
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SCB->CPACR |= (0xFu << 20);
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2ec: f8d3 2088 ldr.w r2, [r3, #136] ; 0x88
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2f0: f442 0270 orr.w r2, r2, #15728640 ; 0xf00000
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2f4: f8c3 2088 str.w r2, [r3, #136] ; 0x88
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\details Acts as a special kind of Data Memory Barrier.
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It completes when all explicit memory accesses before this instruction complete.
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*/
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__STATIC_FORCEINLINE void __DSB(void)
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{
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__ASM volatile ("dsb 0xF":::"memory");
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2f8: f3bf 8f4f dsb sy
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__ASM volatile ("isb 0xF":::"memory");
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2fc: f3bf 8f6f isb sy
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__libc_init_array();
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300: 4b0b ldr r3, [pc, #44] ; (330 <Reset_Handler+0x88>)
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302: 4798 blx r3
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main();
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304: 4b0b ldr r3, [pc, #44] ; (334 <Reset_Handler+0x8c>)
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306: 4798 blx r3
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while (1)
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308: e7fe b.n 308 <Reset_Handler+0x60>
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30a: bf00 nop
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30c: 000003d0 .word 0x000003d0
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310: 20000000 .word 0x20000000
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314: 20000000 .word 0x20000000
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318: 00000385 .word 0x00000385
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31c: 2000001c .word 0x2000001c
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320: 20000000 .word 0x20000000
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324: 000003a1 .word 0x000003a1
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328: 00000000 .word 0x00000000
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32c: e000ed00 .word 0xe000ed00
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330: 0000033d .word 0x0000033d
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334: 00000339 .word 0x00000339
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00000338 <main>:
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int main()
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{
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for(;;)
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{
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asm volatile("nop");
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338: bf00 nop
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for(;;)
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33a: e7fd b.n 338 <main>
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0000033c <__libc_init_array>:
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33c: b570 push {r4, r5, r6, lr}
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33e: 4d0d ldr r5, [pc, #52] ; (374 <__libc_init_array+0x38>)
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340: 4c0d ldr r4, [pc, #52] ; (378 <__libc_init_array+0x3c>)
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342: 1b64 subs r4, r4, r5
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344: 10a4 asrs r4, r4, #2
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346: 2600 movs r6, #0
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348: 42a6 cmp r6, r4
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34a: d109 bne.n 360 <__libc_init_array+0x24>
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34c: 4d0b ldr r5, [pc, #44] ; (37c <__libc_init_array+0x40>)
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34e: 4c0c ldr r4, [pc, #48] ; (380 <__libc_init_array+0x44>)
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350: f000 f82e bl 3b0 <_init>
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354: 1b64 subs r4, r4, r5
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356: 10a4 asrs r4, r4, #2
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358: 2600 movs r6, #0
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35a: 42a6 cmp r6, r4
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35c: d105 bne.n 36a <__libc_init_array+0x2e>
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35e: bd70 pop {r4, r5, r6, pc}
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360: f855 3b04 ldr.w r3, [r5], #4
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364: 4798 blx r3
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366: 3601 adds r6, #1
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368: e7ee b.n 348 <__libc_init_array+0xc>
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36a: f855 3b04 ldr.w r3, [r5], #4
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36e: 4798 blx r3
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370: 3601 adds r6, #1
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372: e7f2 b.n 35a <__libc_init_array+0x1e>
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374: 000003bc .word 0x000003bc
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378: 000003bc .word 0x000003bc
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37c: 000003bc .word 0x000003bc
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380: 000003c0 .word 0x000003c0
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00000384 <memcpy>:
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384: 440a add r2, r1
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386: 4291 cmp r1, r2
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388: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
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38c: d100 bne.n 390 <memcpy+0xc>
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38e: 4770 bx lr
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390: b510 push {r4, lr}
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392: f811 4b01 ldrb.w r4, [r1], #1
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396: f803 4f01 strb.w r4, [r3, #1]!
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39a: 4291 cmp r1, r2
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39c: d1f9 bne.n 392 <memcpy+0xe>
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39e: bd10 pop {r4, pc}
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000003a0 <memset>:
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3a0: 4402 add r2, r0
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3a2: 4603 mov r3, r0
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3a4: 4293 cmp r3, r2
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3a6: d100 bne.n 3aa <memset+0xa>
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3a8: 4770 bx lr
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3aa: f803 1b01 strb.w r1, [r3], #1
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3ae: e7f9 b.n 3a4 <memset+0x4>
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000003b0 <_init>:
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3b0: b5f8 push {r3, r4, r5, r6, r7, lr}
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3b2: bf00 nop
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3b4: bcf8 pop {r3, r4, r5, r6, r7}
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3b6: bc08 pop {r3}
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3b8: 469e mov lr, r3
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3ba: 4770 bx lr
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000003bc <__frame_dummy_init_array_entry>:
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3bc: 0289 0000 ....
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000003c0 <_fini>:
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3c0: b5f8 push {r3, r4, r5, r6, r7, lr}
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3c2: bf00 nop
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3c4: bcf8 pop {r3, r4, r5, r6, r7}
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3c6: bc08 pop {r3}
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3c8: 469e mov lr, r3
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3ca: 4770 bx lr
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000003cc <__do_global_dtors_aux_fini_array_entry>:
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3cc: 0265 0000 e...
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