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641 lines
18 KiB
C
641 lines
18 KiB
C
/* Auto-generated config file hpl_oscctrl_config.h */
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#ifndef HPL_OSCCTRL_CONFIG_H
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#define HPL_OSCCTRL_CONFIG_H
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// <<< Use Configuration Wizard in Context Menu >>>
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// <e> External Multipurpose Crystal Oscillator Configuration
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// <i> Indicates whether configuration for XOSC0 is enabled or not
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// <id> enable_xosc0
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#ifndef CONF_XOSC0_CONFIG
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#define CONF_XOSC0_CONFIG 0
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#endif
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// <o> Frequency <8000000-48000000>
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// <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
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// <id> xosc0_frequency
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#ifndef CONF_XOSC_FREQUENCY
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#define CONF_XOSC0_FREQUENCY 12000000
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#endif
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// <h> External Multipurpose Crystal Oscillator Control
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// <q> Oscillator enable
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// <i> Indicates whether External Multipurpose Crystal Oscillator is enabled or not
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// <id> xosc0_arch_enable
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#ifndef CONF_XOSC0_ENABLE
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#define CONF_XOSC0_ENABLE 0
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#endif
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// <o> Start-Up Time
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// <0x0=>31us
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// <0x1=>61us
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// <0x2=>122us
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// <0x3=>244us
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// <0x4=>488us
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// <0x5=>977us
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// <0x6=>1953us
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// <0x7=>3906us
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// <0x8=>7813us
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// <0x9=>15625us
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// <0xA=>31250us
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// <0xB=>62500us
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// <0xC=>125000us
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// <0xD=>250000us
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// <0xE=>500000us
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// <0xF=>1000000us
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// <id> xosc0_arch_startup
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#ifndef CONF_XOSC0_STARTUP
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#define CONF_XOSC0_STARTUP 0
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#endif
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// <q> Clock Switch Back
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// <i> Indicates whether Clock Switch Back is enabled or not
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// <id> xosc0_arch_swben
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#ifndef CONF_XOSC0_SWBEN
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#define CONF_XOSC0_SWBEN 0
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#endif
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// <q> Clock Failure Detector
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// <i> Indicates whether Clock Failure Detector is enabled or not
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// <id> xosc0_arch_cfden
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#ifndef CONF_XOSC0_CFDEN
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#define CONF_XOSC0_CFDEN 0
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#endif
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// <q> Automatic Loop Control Enable
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// <i> Indicates whether Automatic Loop Control is enabled or not
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// <id> xosc0_arch_enalc
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#ifndef CONF_XOSC0_ENALC
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#define CONF_XOSC0_ENALC 0
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#endif
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// <q> Low Buffer Gain Enable
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// <i> Indicates whether Low Buffer Gain is enabled or not
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// <id> xosc0_arch_lowbufgain
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#ifndef CONF_XOSC0_LOWBUFGAIN
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#define CONF_XOSC0_LOWBUFGAIN 0
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#endif
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// <q> On Demand Control
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// <i> Indicates whether On Demand Control is enabled or not
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// <id> xosc0_arch_ondemand
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#ifndef CONF_XOSC0_ONDEMAND
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#define CONF_XOSC0_ONDEMAND 0
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#endif
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// <q> Run in Standby
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// <i> Indicates whether Run in Standby is enabled or not
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// <id> xosc0_arch_runstdby
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#ifndef CONF_XOSC0_RUNSTDBY
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#define CONF_XOSC0_RUNSTDBY 0
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#endif
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// <q> Crystal connected to XIN/XOUT Enable
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// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
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// <id> xosc0_arch_xtalen
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#ifndef CONF_XOSC0_XTALEN
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#define CONF_XOSC0_XTALEN 0
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#endif
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//</h>
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//</e>
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#if CONF_XOSC0_FREQUENCY >= 32000000
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#define CONF_XOSC0_CFDPRESC 0x0
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#define CONF_XOSC0_IMULT 0x7
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#define CONF_XOSC0_IPTAT 0x3
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#elif CONF_XOSC0_FREQUENCY >= 24000000
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#define CONF_XOSC0_CFDPRESC 0x1
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#define CONF_XOSC0_IMULT 0x6
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#define CONF_XOSC0_IPTAT 0x3
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#elif CONF_XOSC0_FREQUENCY >= 16000000
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#define CONF_XOSC0_CFDPRESC 0x2
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#define CONF_XOSC0_IMULT 0x5
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#define CONF_XOSC0_IPTAT 0x3
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#elif CONF_XOSC0_FREQUENCY >= 8000000
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#define CONF_XOSC0_CFDPRESC 0x3
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#define CONF_XOSC0_IMULT 0x4
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#define CONF_XOSC0_IPTAT 0x3
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#endif
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// <e> External Multipurpose Crystal Oscillator Configuration
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// <i> Indicates whether configuration for XOSC1 is enabled or not
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// <id> enable_xosc1
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#ifndef CONF_XOSC1_CONFIG
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#define CONF_XOSC1_CONFIG 0
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#endif
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// <o> Frequency <8000000-48000000>
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// <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
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// <id> xosc1_frequency
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#ifndef CONF_XOSC_FREQUENCY
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#define CONF_XOSC1_FREQUENCY 12000000
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#endif
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// <h> External Multipurpose Crystal Oscillator Control
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// <q> Oscillator enable
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// <i> Indicates whether External Multipurpose Crystal Oscillator is enabled or not
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// <id> xosc1_arch_enable
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#ifndef CONF_XOSC1_ENABLE
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#define CONF_XOSC1_ENABLE 0
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#endif
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// <o> Start-Up Time
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// <0x0=>31us
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// <0x1=>61us
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// <0x2=>122us
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// <0x3=>244us
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// <0x4=>488us
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// <0x5=>977us
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// <0x6=>1953us
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// <0x7=>3906us
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// <0x8=>7813us
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// <0x9=>15625us
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// <0xA=>31250us
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// <0xB=>62500us
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// <0xC=>125000us
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// <0xD=>250000us
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// <0xE=>500000us
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// <0xF=>1000000us
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// <id> xosc1_arch_startup
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#ifndef CONF_XOSC1_STARTUP
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#define CONF_XOSC1_STARTUP 0
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#endif
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// <q> Clock Switch Back
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// <i> Indicates whether Clock Switch Back is enabled or not
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// <id> xosc1_arch_swben
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#ifndef CONF_XOSC1_SWBEN
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#define CONF_XOSC1_SWBEN 0
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#endif
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// <q> Clock Failure Detector
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// <i> Indicates whether Clock Failure Detector is enabled or not
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// <id> xosc1_arch_cfden
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#ifndef CONF_XOSC1_CFDEN
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#define CONF_XOSC1_CFDEN 0
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#endif
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// <q> Automatic Loop Control Enable
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// <i> Indicates whether Automatic Loop Control is enabled or not
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// <id> xosc1_arch_enalc
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#ifndef CONF_XOSC1_ENALC
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#define CONF_XOSC1_ENALC 0
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#endif
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// <q> Low Buffer Gain Enable
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// <i> Indicates whether Low Buffer Gain is enabled or not
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// <id> xosc1_arch_lowbufgain
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#ifndef CONF_XOSC1_LOWBUFGAIN
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#define CONF_XOSC1_LOWBUFGAIN 0
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#endif
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// <q> On Demand Control
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// <i> Indicates whether On Demand Control is enabled or not
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// <id> xosc1_arch_ondemand
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#ifndef CONF_XOSC1_ONDEMAND
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#define CONF_XOSC1_ONDEMAND 0
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#endif
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// <q> Run in Standby
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// <i> Indicates whether Run in Standby is enabled or not
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// <id> xosc1_arch_runstdby
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#ifndef CONF_XOSC1_RUNSTDBY
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#define CONF_XOSC1_RUNSTDBY 0
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#endif
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// <q> Crystal connected to XIN/XOUT Enable
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// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
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// <id> xosc1_arch_xtalen
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#ifndef CONF_XOSC1_XTALEN
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#define CONF_XOSC1_XTALEN 1
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#endif
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//</h>
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//</e>
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#if CONF_XOSC1_FREQUENCY >= 32000000
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#define CONF_XOSC1_CFDPRESC 0x0
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#define CONF_XOSC1_IMULT 0x7
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#define CONF_XOSC1_IPTAT 0x3
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#elif CONF_XOSC1_FREQUENCY >= 24000000
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#define CONF_XOSC1_CFDPRESC 0x1
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#define CONF_XOSC1_IMULT 0x6
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#define CONF_XOSC1_IPTAT 0x3
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#elif CONF_XOSC1_FREQUENCY >= 16000000
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#define CONF_XOSC1_CFDPRESC 0x2
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#define CONF_XOSC1_IMULT 0x5
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#define CONF_XOSC1_IPTAT 0x3
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#elif CONF_XOSC1_FREQUENCY >= 8000000
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#define CONF_XOSC1_CFDPRESC 0x3
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#define CONF_XOSC1_IMULT 0x4
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#define CONF_XOSC1_IPTAT 0x3
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#endif
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// <e> DFLL Configuration
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// <i> Indicates whether configuration for DFLL is enabled or not
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// <id> enable_dfll
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#ifndef CONF_DFLL_CONFIG
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#define CONF_DFLL_CONFIG 0
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#endif
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// <y> Reference Clock Source
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// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
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// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
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// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
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// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
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// <i> Select the clock source
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// <id> dfll_ref_clock
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#ifndef CONF_DFLL_GCLK
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#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK3_Val
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#endif
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// <h> Digital Frequency Locked Loop Control
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// <q> DFLL Enable
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// <i> Indicates whether DFLL is enabled or not
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// <id> dfll_arch_enable
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#ifndef CONF_DFLL_ENABLE
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#define CONF_DFLL_ENABLE 0
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#endif
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// <q> On Demand Control
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// <i> Indicates whether On Demand Control is enabled or not
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// <id> dfll_arch_ondemand
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#ifndef CONF_DFLL_ONDEMAND
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#define CONF_DFLL_ONDEMAND 0
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#endif
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// <q> Run in Standby
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// <i> Indicates whether Run in Standby is enabled or not
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// <id> dfll_arch_runstdby
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#ifndef CONF_DFLL_RUNSTDBY
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#define CONF_DFLL_RUNSTDBY 0
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#endif
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// <q> USB Clock Recovery Mode
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// <i> Indicates whether USB Clock Recovery Mode is enabled or not
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// <id> dfll_arch_usbcrm
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#ifndef CONF_DFLL_USBCRM
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#define CONF_DFLL_USBCRM 0
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#endif
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// <q> Wait Lock
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// <i> Indicates whether Wait Lock is enabled or not
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// <id> dfll_arch_waitlock
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#ifndef CONF_DFLL_WAITLOCK
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#define CONF_DFLL_WAITLOCK 0
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#endif
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// <q> Bypass Coarse Lock
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// <i> Indicates whether Bypass Coarse Lock is enabled or not
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// <id> dfll_arch_bplckc
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#ifndef CONF_DFLL_BPLCKC
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#define CONF_DFLL_BPLCKC 0
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#endif
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// <q> Quick Lock Disable
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// <i> Indicates whether Quick Lock Disable is enabled or not
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// <id> dfll_arch_qldis
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#ifndef CONF_DFLL_QLDIS
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#define CONF_DFLL_QLDIS 0
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#endif
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// <q> Chill Cycle Disable
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// <i> Indicates whether Chill Cycle Disable is enabled or not
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// <id> dfll_arch_ccdis
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#ifndef CONF_DFLL_CCDIS
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#define CONF_DFLL_CCDIS 1
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#endif
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// <q> Lose Lock After Wake
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// <i> Indicates whether Lose Lock After Wake is enabled or not
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// <id> dfll_arch_llaw
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#ifndef CONF_DFLL_LLAW
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#define CONF_DFLL_LLAW 0
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#endif
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// <q> Stable DFLL Frequency
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// <i> Indicates whether Stable DFLL Frequency is enabled or not
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// <id> dfll_arch_stable
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#ifndef CONF_DFLL_STABLE
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#define CONF_DFLL_STABLE 0
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#endif
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// <o> Operating Mode Selection
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// <0=>Open Loop Mode
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// <1=>Closed Loop Mode
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// <id> dfll_mode
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#ifndef CONF_DFLL_MODE
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#define CONF_DFLL_MODE 0x1
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#endif
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// <o> Coarse Maximum Step <0x0-0x1F>
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// <id> dfll_arch_cstep
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#ifndef CONF_DFLL_CSTEP
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#define CONF_DFLL_CSTEP 0x1
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#endif
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// <o> Fine Maximum Step <0x0-0xFF>
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// <id> dfll_arch_fstep
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#ifndef CONF_DFLL_FSTEP
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#define CONF_DFLL_FSTEP 0x1
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#endif
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// <o> DFLL Multiply Factor <0x0-0xFFFF>
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// <id> dfll_mul
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#ifndef CONF_DFLL_MUL
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#define CONF_DFLL_MUL 0x5b9
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#endif
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// <e> DFLL Calibration Overwrite
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// <i> Indicates whether Overwrite Calibration value of DFLL
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// <id> dfll_arch_calibration
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#ifndef CONF_DFLL_OVERWRITE_CALIBRATION
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#define CONF_DFLL_OVERWRITE_CALIBRATION 0
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#endif
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// <o> Coarse Value <0x0-0x3F>
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// <id> dfll_arch_coarse
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#ifndef CONF_DFLL_COARSE
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#define CONF_DFLL_COARSE (0x1f / 4)
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#endif
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// <o> Fine Value <0x0-0xFF>
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// <id> dfll_arch_fine
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#ifndef CONF_DFLL_FINE
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#define CONF_DFLL_FINE (0x80)
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#endif
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//</e>
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//</h>
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//</e>
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// <e> FDPLL0 Configuration
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// <i> Indicates whether configuration for FDPLL0 is enabled or not
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// <id> enable_fdpll0
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#ifndef CONF_FDPLL0_CONFIG
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#define CONF_FDPLL0_CONFIG 1
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#endif
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// <y> Reference Clock Source
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// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
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// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
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// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
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// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
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// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
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// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
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// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
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// <i> Select the clock source.
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// <id> fdpll0_ref_clock
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#ifndef CONF_FDPLL0_GCLK
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#define CONF_FDPLL0_GCLK GCLK_GENCTRL_SRC_XOSC32K
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#endif
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// <h> Digital Phase Locked Loop Control
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// <q> Enable
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// <i> Indicates whether Digital Phase Locked Loop is enabled or not
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// <id> fdpll0_arch_enable
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#ifndef CONF_FDPLL0_ENABLE
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#define CONF_FDPLL0_ENABLE 1
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#endif
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// <q> On Demand Control
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// <i> Indicates whether On Demand Control is enabled or not
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// <id> fdpll0_arch_ondemand
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#ifndef CONF_FDPLL0_ONDEMAND
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#define CONF_FDPLL0_ONDEMAND 0
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#endif
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// <q> Run in Standby
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// <i> Indicates whether Run in Standby is enabled or not
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// <id> fdpll0_arch_runstdby
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#ifndef CONF_FDPLL0_RUNSTDBY
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#define CONF_FDPLL0_RUNSTDBY 0
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#endif
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// <o> Loop Divider Ratio Fractional Part <0x0-0x1F>
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// <i> Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
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// <id> fdpll0_ldrfrac
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#ifndef CONF_FDPLL0_LDRFRAC
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#define CONF_FDPLL0_LDRFRAC 0x1
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#endif
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// <o> Loop Divider Ratio Integer Part <0x0-0x1FFF>
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// <i> Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
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// <id> fdpll0_ldr
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#ifndef CONF_FDPLL0_LDR
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#define CONF_FDPLL0_LDR 0xe4d
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#endif
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// <o> Clock Divider <0x0-0x7FF>
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// <i> This Clock divider is only for XOSC clock input to DPLL
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// <id> fdpll0_clock_div
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#ifndef CONF_FDPLL0_DIV
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#define CONF_FDPLL0_DIV 0x0
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#endif
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// <q> DCO Filter Enable
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// <i> Indicates whether DCO Filter Enable is enabled or not
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// <id> fdpll0_arch_dcoen
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#ifndef CONF_FDPLL0_DCOEN
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#define CONF_FDPLL0_DCOEN 0
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#endif
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// <o> Sigma-Delta DCO Filter Selection <0x0-0x7>
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// <id> fdpll0_clock_dcofilter
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#ifndef CONF_FDPLL0_DCOFILTER
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#define CONF_FDPLL0_DCOFILTER 0x0
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#endif
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// <q> Lock Bypass
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// <i> Indicates whether Lock Bypass is enabled or not
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// <id> fdpll0_arch_lbypass
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#ifndef CONF_FDPLL0_LBYPASS
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#define CONF_FDPLL0_LBYPASS 1
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#endif
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// <o> Lock Time
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// <0x0=>No time-out, automatic lock
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// <0x4=>The Time-out if no lock within 800 us
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// <0x5=>The Time-out if no lock within 900 us
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// <0x6=>The Time-out if no lock within 1 ms
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// <0x7=>The Time-out if no lock within 11 ms
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// <id> fdpll0_arch_ltime
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#ifndef CONF_FDPLL0_LTIME
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#define CONF_FDPLL0_LTIME 0x0
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#endif
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// <o> Reference Clock Selection
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// <0x0=>GCLK clock reference
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// <0x1=>XOSC32K clock reference
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// <0x2=>XOSC0 clock reference
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// <0x3=>XOSC1 clock reference
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// <id> fdpll0_arch_refclk
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#ifndef CONF_FDPLL0_REFCLK
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#define CONF_FDPLL0_REFCLK 0x1
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#endif
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// <q> Wake Up Fast
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// <i> Indicates whether Wake Up Fast is enabled or not
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// <id> fdpll0_arch_wuf
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#ifndef CONF_FDPLL0_WUF
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#define CONF_FDPLL0_WUF 0
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#endif
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// <o> Proportional Integral Filter Selection <0x0-0xF>
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// <id> fdpll0_arch_filter
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#ifndef CONF_FDPLL0_FILTER
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#define CONF_FDPLL0_FILTER 0x0
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#endif
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//</h>
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//</e>
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// <e> FDPLL1 Configuration
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// <i> Indicates whether configuration for FDPLL1 is enabled or not
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// <id> enable_fdpll1
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#ifndef CONF_FDPLL1_CONFIG
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#define CONF_FDPLL1_CONFIG 0
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#endif
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// <y> Reference Clock Source
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// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
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// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
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// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
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// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
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// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
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// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
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// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
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// <i> Select the clock source.
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// <id> fdpll1_ref_clock
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#ifndef CONF_FDPLL1_GCLK
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#define CONF_FDPLL1_GCLK GCLK_GENCTRL_SRC_XOSC32K
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#endif
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// <h> Digital Phase Locked Loop Control
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// <q> Enable
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// <i> Indicates whether Digital Phase Locked Loop is enabled or not
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// <id> fdpll1_arch_enable
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#ifndef CONF_FDPLL1_ENABLE
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#define CONF_FDPLL1_ENABLE 0
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#endif
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// <q> On Demand Control
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// <i> Indicates whether On Demand Control is enabled or not
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// <id> fdpll1_arch_ondemand
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#ifndef CONF_FDPLL1_ONDEMAND
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#define CONF_FDPLL1_ONDEMAND 0
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#endif
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// <q> Run in Standby
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// <i> Indicates whether Run in Standby is enabled or not
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// <id> fdpll1_arch_runstdby
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#ifndef CONF_FDPLL1_RUNSTDBY
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#define CONF_FDPLL1_RUNSTDBY 0
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#endif
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// <o> Loop Divider Ratio Fractional Part <0x0-0x1F>
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// <i> Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
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// <id> fdpll1_ldrfrac
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#ifndef CONF_FDPLL1_LDRFRAC
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#define CONF_FDPLL1_LDRFRAC 0xd
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#endif
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// <o> Loop Divider Ratio Integer Part <0x0-0x1FFF>
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// <i> Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
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// <id> fdpll1_ldr
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#ifndef CONF_FDPLL1_LDR
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#define CONF_FDPLL1_LDR 0x5b7
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#endif
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// <o> Clock Divider <0x0-0x7FF>
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// <i> This Clock divider is only for XOSC clock input to DPLL
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// <id> fdpll1_clock_div
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#ifndef CONF_FDPLL1_DIV
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#define CONF_FDPLL1_DIV 0x0
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#endif
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// <q> DCO Filter Enable
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// <i> Indicates whether DCO Filter Enable is enabled or not
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// <id> fdpll1_arch_dcoen
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#ifndef CONF_FDPLL1_DCOEN
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#define CONF_FDPLL1_DCOEN 0
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#endif
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// <o> Sigma-Delta DCO Filter Selection <0x0-0x7>
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// <id> fdpll1_clock_dcofilter
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#ifndef CONF_FDPLL1_DCOFILTER
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#define CONF_FDPLL1_DCOFILTER 0x0
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#endif
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// <q> Lock Bypass
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// <i> Indicates whether Lock Bypass is enabled or not
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// <id> fdpll1_arch_lbypass
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#ifndef CONF_FDPLL1_LBYPASS
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#define CONF_FDPLL1_LBYPASS 0
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#endif
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// <o> Lock Time
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// <0x0=>No time-out, automatic lock
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// <0x4=>The Time-out if no lock within 800 us
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// <0x5=>The Time-out if no lock within 900 us
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// <0x6=>The Time-out if no lock within 1 ms
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// <0x7=>The Time-out if no lock within 11 ms
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// <id> fdpll1_arch_ltime
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#ifndef CONF_FDPLL1_LTIME
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#define CONF_FDPLL1_LTIME 0x0
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#endif
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// <o> Reference Clock Selection
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// <0x0=>GCLK clock reference
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// <0x1=>XOSC32K clock reference
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// <0x2=>XOSC0 clock reference
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// <0x3=>XOSC1 clock reference
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// <id> fdpll1_arch_refclk
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#ifndef CONF_FDPLL1_REFCLK
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#define CONF_FDPLL1_REFCLK 0x1
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#endif
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// <q> Wake Up Fast
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// <i> Indicates whether Wake Up Fast is enabled or not
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// <id> fdpll1_arch_wuf
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#ifndef CONF_FDPLL1_WUF
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#define CONF_FDPLL1_WUF 0
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#endif
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// <o> Proportional Integral Filter Selection <0x0-0xF>
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// <id> fdpll1_arch_filter
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#ifndef CONF_FDPLL1_FILTER
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#define CONF_FDPLL1_FILTER 0x0
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#endif
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//</h>
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//</e>
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// <<< end of configuration section >>>
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#endif // HPL_OSCCTRL_CONFIG_H
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