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105 lines
2.7 KiB
C
105 lines
2.7 KiB
C
/* Auto-generated config file hpl_mclk_config.h */
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#ifndef HPL_MCLK_CONFIG_H
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#define HPL_MCLK_CONFIG_H
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// <<< Use Configuration Wizard in Context Menu >>>
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#include <peripheral_clk_config.h>
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// <e> System Configuration
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// <i> Indicates whether configuration for system is enabled or not
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// <id> enable_cpu_clock
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#ifndef CONF_SYSTEM_CONFIG
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#define CONF_SYSTEM_CONFIG 1
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#endif
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// <h> Basic settings
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// <y> CPU Clock source
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// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <i> This defines the clock source for the CPU
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// <id> cpu_clock_source
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#ifndef CONF_CPU_SRC
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#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
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#endif
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// <y> CPU Clock Division Factor
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// <MCLK_CPUDIV_DIV_DIV1_Val"> 1
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// <MCLK_CPUDIV_DIV_DIV2_Val"> 2
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// <MCLK_CPUDIV_DIV_DIV4_Val"> 4
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// <MCLK_CPUDIV_DIV_DIV8_Val"> 8
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// <MCLK_CPUDIV_DIV_DIV16_Val"> 16
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// <MCLK_CPUDIV_DIV_DIV32_Val"> 32
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// <MCLK_CPUDIV_DIV_DIV64_Val"> 64
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// <MCLK_CPUDIV_DIV_DIV128_Val"> 128
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// <i> Prescalar for CPU clock
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// <id> cpu_div
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#ifndef CONF_MCLK_CPUDIV
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#define CONF_MCLK_CPUDIV MCLK_CPUDIV_DIV_DIV1_Val
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#endif
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// <y> Low Power Clock Division
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// <MCLK_LPDIV_LPDIV_DIV1_Val"> Divide by 1
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// <MCLK_LPDIV_LPDIV_DIV2_Val"> Divide by 2
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// <MCLK_LPDIV_LPDIV_DIV4_Val"> Divide by 4
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// <MCLK_LPDIV_LPDIV_DIV8_Val"> Divide by 8
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// <MCLK_LPDIV_LPDIV_DIV16_Val"> Divide by 16
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// <MCLK_LPDIV_LPDIV_DIV32_Val"> Divide by 32
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// <MCLK_LPDIV_LPDIV_DIV64_Val"> Divide by 64
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// <MCLK_LPDIV_LPDIV_DIV128_Val"> Divide by 128
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// <id> mclk_arch_lpdiv
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#ifndef CONF_MCLK_LPDIV
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#define CONF_MCLK_LPDIV MCLK_LPDIV_LPDIV_DIV4_Val
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#endif
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// <y> Backup Clock Division
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// <MCLK_BUPDIV_BUPDIV_DIV1_Val"> Divide by 1
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// <MCLK_BUPDIV_BUPDIV_DIV2_Val"> Divide by 2
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// <MCLK_BUPDIV_BUPDIV_DIV4_Val"> Divide by 4
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// <MCLK_BUPDIV_BUPDIV_DIV8_Val"> Divide by 8
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// <MCLK_BUPDIV_BUPDIV_DIV16_Val"> Divide by 16
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// <MCLK_BUPDIV_BUPDIV_DIV32_Val"> Divide by 32
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// <MCLK_BUPDIV_BUPDIV_DIV64_Val"> Divide by 64
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// <MCLK_BUPDIV_BUPDIV_DIV128_Val"> Divide by 128
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// <id> mclk_arch_bupdiv
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#ifndef CONF_MCLK_BUPDIV
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#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV8_Val
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#endif
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// <y> High-Speed Clock Division
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// <MCLK_HSDIV_DIV_DIV1_Val"> Divide by 1
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// <id> mclk_arch_hsdiv
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#ifndef CONF_MCLK_HSDIV
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#define CONF_MCLK_HSDIV MCLK_HSDIV_DIV_DIV1_Val
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#endif
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// </h>
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// <h> NVM Settings
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// <o> NVM Wait States
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// <i> These bits select the number of wait states for a read operation.
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// <0=> 0
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// <1=> 1
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// <2=> 2
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// <3=> 3
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// <4=> 4
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// <5=> 5
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// <6=> 6
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// <7=> 7
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// <8=> 8
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// <9=> 9
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// <10=> 10
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// <11=> 11
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// <12=> 12
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// <13=> 13
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// <14=> 14
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// <15=> 15
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// <id> nvm_wait_states
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#ifndef CONF_NVM_WAIT_STATE
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#define CONF_NVM_WAIT_STATE 5
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#endif
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// </h>
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// </e>
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// <<< end of configuration section >>>
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#endif // HPL_MCLK_CONFIG_H
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