diff --git a/AtmelStart.gpdsc b/AtmelStart.gpdsc
index 10a7009..2c309d2 100644
--- a/AtmelStart.gpdsc
+++ b/AtmelStart.gpdsc
@@ -42,14 +42,18 @@
       <description>Atmel Start Framework</description>
       <RTE_Components_h>#define ATMEL_START</RTE_Components_h>
       <files>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/calendar.rst"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/mci_sync.rst"/>
         <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/spi_master_sync.rst"/>
         <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/usart_sync.rst"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_atomic.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_cache.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_calendar.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_delay.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_gpio.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_init.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_io.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_mci_sync.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_sleep.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_spi_m_sync.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_cmcc.h"/>
@@ -63,6 +67,7 @@
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_s_sync.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_init.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_irq.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_mci_sync.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_ramecc.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_sleep.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi.h"/>
@@ -77,15 +82,18 @@
         <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_gpio.c"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_init.c"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_io.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_mci_sync.c"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_sleep.c"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/compiler.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/err_codes.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/events.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_assert.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_decrement_macro.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_event.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_increment_macro.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_list.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_recursion_macro.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_repeat_macro.h"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_assert.c"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_event.c"/>
@@ -130,6 +138,19 @@
         <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_trng_e54.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_usb_e54.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_wdt_e54.h"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="documentation/sd_mmc.rst"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="sd_mmc/sd_mmc.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="sd_mmc/sd_mmc.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="sd_mmc/sd_mmc_protocol.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="diskio/diskio.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="diskio/sdmmc_diskio.c"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="documentation/diskio_sdmmc.rst"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="documentation/fatfs.rst"/>
+        <file category="other" condition="ARMCC, GCC, IAR" name="fatfs/.clang-format"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="fatfs/src/ff.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="fatfs/src/ff.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="fatfs/src/ffconf.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="fatfs/src/integer.h"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="main.c"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="driver_init.c"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="driver_init.h"/>
@@ -137,6 +158,7 @@
         <file category="header" condition="ARMCC, GCC, IAR" name="examples/driver_examples.h"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="examples/driver_examples.c"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_usart_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_calendar.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_missing_features.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_reset.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_async.h"/>
@@ -144,8 +166,10 @@
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_sync.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_s_async.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_s_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_timer.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_async.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_sync.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_calendar.c"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_spi_m_sync.c"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_usart_sync.c"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/parts.h"/>
@@ -163,8 +187,17 @@
         <file category="header" condition="ARMCC, GCC, IAR" name="hpl/pm/hpl_pm_base.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hpl/port/hpl_gpio_base.h"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hpl/ramecc/hpl_ramecc.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/rtc/hpl_rtc.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/rtc/hpl_rtc_base.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/sdhc/hpl_sdhc.c"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hpl/sercom/hpl_sercom.c"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hpl/systick/hpl_systick.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="sd_mmc_start.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="sd_mmc_start.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="diskio_start.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="diskio_start.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="fatfs_main.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="fatfs_main.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="atmel_start.h"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="atmel_start.c"/>
         <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_cmcc_config.h"/>
@@ -174,9 +207,13 @@
         <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_osc32kctrl_config.h"/>
         <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_oscctrl_config.h"/>
         <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_port_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_rtc_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_sdhc_config.h"/>
         <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_sercom_config.h"/>
         <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_systick_config.h"/>
         <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/peripheral_clk_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/conf_sd_mmc.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="fatfs/src/conf_fatfs.h"/>
         <file category="include" condition="ARMCC, GCC, IAR" name=""/>
         <file category="include" condition="ARMCC, GCC, IAR" name="config"/>
         <file category="include" condition="ARMCC, GCC, IAR" name="examples"/>
@@ -192,10 +229,19 @@
         <file category="include" condition="ARMCC, GCC, IAR" name="hpl/pm"/>
         <file category="include" condition="ARMCC, GCC, IAR" name="hpl/port"/>
         <file category="include" condition="ARMCC, GCC, IAR" name="hpl/ramecc"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/rtc"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/sdhc"/>
         <file category="include" condition="ARMCC, GCC, IAR" name="hpl/sercom"/>
         <file category="include" condition="ARMCC, GCC, IAR" name="hpl/systick"/>
         <file category="include" condition="ARMCC, GCC, IAR" name="hri"/>
         <file category="include" condition="ARMCC, GCC, IAR" name=""/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="config"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="sd_mmc"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name=""/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="diskio"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name=""/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="fatfs/src"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name=""/>
       </files>
     </component>
   </components>
diff --git a/atmel_start.c b/atmel_start.c
index 79f252a..8f0ebc0 100644
--- a/atmel_start.c
+++ b/atmel_start.c
@@ -6,4 +6,6 @@
 void atmel_start_init(void)
 {
 	system_init();
+	sd_mmc_stack_init();
+	diskio_init();
 }
diff --git a/atmel_start.h b/atmel_start.h
index 0de62f5..4c05575 100644
--- a/atmel_start.h
+++ b/atmel_start.h
@@ -6,6 +6,8 @@ extern "C" {
 #endif
 
 #include "driver_init.h"
+#include "sd_mmc_start.h"
+#include "diskio_start.h"
 
 /**
  * Initializes MCU, drivers and middleware in the project
diff --git a/atmel_start_config.atstart b/atmel_start_config.atstart
index 5166c6d..776d97c 100644
--- a/atmel_start_config.atstart
+++ b/atmel_start_config.atstart
@@ -18,7 +18,72 @@ board:
   device: SAME54P20A-AU
 details: null
 application: null
-middlewares: {}
+middlewares:
+  SDMMC:
+    user_label: SDMMC
+    configuration:
+      conf_mmc_support: false
+      conf_sd_mmc_0_cd_detect_en: false
+      conf_sd_mmc_0_cd_detect_value: Low
+      conf_sd_mmc_0_enable: true
+      conf_sd_mmc_0_wp_detect_en: false
+      conf_sd_mmc_0_wp_detect_value: High
+      conf_sd_mmc_os_support: false
+      conf_sdio_support: true
+    definition: Atmel:SD_MMC:0.0.1::SD_MMC
+    functionality: SD/MMC_Access
+    api: SD-MMC:Lib:API
+    dependencies:
+      IO Bus: IO_BUS
+      Write Protect 0: null
+      Card Detect 0: null
+  DISK_IO:
+    user_label: DISK_IO
+    configuration: {}
+    definition: Atmel:DiskIO:1.0.0::SD_MMC
+    functionality: DISKIO
+    api: DiskIO:Storage-Abstractions:API
+    dependencies:
+      SDMMC: SDMMC
+  FATFS_0:
+    user_label: FATFS_0
+    configuration:
+      character_code_set: 0 - ANSI/OEM
+      character_encoding: UTF-8
+      code_page: Multilingual Latin 1 (OEM)
+      config_fs_timeout: 1000
+      f_mkfs_fs_enable: true
+      fast_seek_fs_enable: false
+      file_lock_enable: 0
+      file_share_count: 0
+      filtered_dir_enable: false
+      free_space_info_enable: false
+      lfn_feature: 0 - Disable LFN feature. _MAX_LFN and _LFN_UNICODE have no effect.
+      max_lfn_length: 255
+      max_sector_size: '512'
+      min_sector_size: '512'
+      minimisation_level: 0 - Full function
+      multiple_partition_enable: false
+      num_volumes: 5
+      read_only_fs_enable: false
+      reentrant_enable: false
+      relative_path_enable: 2 - f_getcwd() is available in addition to 1.
+      sectore_erase_enable: false
+      strfunc_fs_enable: false
+      string_volume_enable: false
+      synch_handler: HANDLE
+      time_stamp_enable: false
+      tiny_fs_enable: false
+      trim_feature_enable: false
+      use_forward_fs_enable: false
+      volume_label_enable: false
+      word_access_enable: false
+    definition: Atmel:FATFS:1.0.0::FAT_File_System
+    functionality: FATFS
+    api: FAT:File-System:API
+    dependencies:
+      Disk IO: DISK_IO
+      Calender Interface: CALENDER_INTERFACE
 drivers:
   CMCC:
     user_label: CMCC
@@ -582,7 +647,7 @@ drivers:
       $input_id: External Crystal Oscillator 8-48MHz (XOSC1)
       RESERVED_InputFreq: 12000000
       RESERVED_InputFreq_id: External Crystal Oscillator 8-48MHz (XOSC1)
-      _$freq_output_Generic clock generator 0: 48005120
+      _$freq_output_Generic clock generator 0: 119997440
       _$freq_output_Generic clock generator 1: 48005120
       _$freq_output_Generic clock generator 10: 12000000
       _$freq_output_Generic clock generator 11: 12000000
@@ -680,7 +745,7 @@ drivers:
       gclk_arch_gen_9_runstdby: false
       gclk_gen_0_div: 1
       gclk_gen_0_div_sel: false
-      gclk_gen_0_oscillator: Digital Frequency Locked Loop (DFLL48M)
+      gclk_gen_0_oscillator: Digital Phase Locked Loop (DPLL0)
       gclk_gen_10_div: 1
       gclk_gen_10_div_sel: false
       gclk_gen_10_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
@@ -724,18 +789,18 @@ drivers:
     functionality: System
     api: HAL:HPL:MCLK
     configuration:
-      $input: 48005120
+      $input: 119997440
       $input_id: Generic clock generator 0
-      RESERVED_InputFreq: 48005120
+      RESERVED_InputFreq: 119997440
       RESERVED_InputFreq_id: Generic clock generator 0
-      _$freq_output_CPU: 48005120
+      _$freq_output_CPU: 119997440
       cpu_clock_source: Generic clock generator 0
       cpu_div: '1'
       enable_cpu_clock: true
       mclk_arch_bupdiv: Divide by 8
       mclk_arch_hsdiv: Divide by 1
       mclk_arch_lpdiv: Divide by 4
-      nvm_wait_states: '0'
+      nvm_wait_states: '5'
     optional_signals: []
     variant: null
     clocks:
@@ -768,11 +833,11 @@ drivers:
       xosc32k_arch_cfdeo: false
       xosc32k_arch_cgm: Standard mode
       xosc32k_arch_en1k: false
-      xosc32k_arch_en32k: false
+      xosc32k_arch_en32k: true
       xosc32k_arch_enable: true
       xosc32k_arch_ondemand: true
       xosc32k_arch_runstdby: false
-      xosc32k_arch_startup: 62592us
+      xosc32k_arch_startup: 1000092us
       xosc32k_arch_swben: false
       xosc32k_arch_xtalen: true
     optional_signals: []
@@ -790,16 +855,16 @@ drivers:
       RESERVED_InputFreq: 32768
       RESERVED_InputFreq_id: 32kHz External Crystal Oscillator (XOSC32K)
       _$freq_output_Digital Frequency Locked Loop (DFLL48M): 48005120
-      _$freq_output_Digital Phase Locked Loop (DPLL0): 47985664
+      _$freq_output_Digital Phase Locked Loop (DPLL0): 119997440
       _$freq_output_Digital Phase Locked Loop (DPLL1): 47985664
-      _$freq_output_External Crystal Oscillator 8-48MHz (XOSC0): '12000000'
-      _$freq_output_External Crystal Oscillator 8-48MHz (XOSC1): '12000000'
+      _$freq_output_External Crystal Oscillator 8-48MHz (XOSC0): 12000000
+      _$freq_output_External Crystal Oscillator 8-48MHz (XOSC1): 12000000
       dfll_arch_bplckc: false
       dfll_arch_calibration: false
       dfll_arch_ccdis: true
       dfll_arch_coarse: 31
       dfll_arch_cstep: 1
-      dfll_arch_enable: true
+      dfll_arch_enable: false
       dfll_arch_fine: 128
       dfll_arch_fstep: 1
       dfll_arch_llaw: false
@@ -812,15 +877,15 @@ drivers:
       dfll_mode: Closed Loop Mode
       dfll_mul: 1465
       dfll_ref_clock: Generic clock generator 3
-      enable_dfll: true
-      enable_fdpll0: false
+      enable_dfll: false
+      enable_fdpll0: true
       enable_fdpll1: false
       enable_xosc0: false
       enable_xosc1: false
       fdpll0_arch_dcoen: false
-      fdpll0_arch_enable: false
+      fdpll0_arch_enable: true
       fdpll0_arch_filter: 0
-      fdpll0_arch_lbypass: false
+      fdpll0_arch_lbypass: true
       fdpll0_arch_ltime: No time-out, automatic lock
       fdpll0_arch_ondemand: false
       fdpll0_arch_refclk: XOSC32K clock reference
@@ -828,8 +893,8 @@ drivers:
       fdpll0_arch_wuf: false
       fdpll0_clock_dcofilter: 0
       fdpll0_clock_div: 0
-      fdpll0_ldr: 1463
-      fdpll0_ldrfrac: 13
+      fdpll0_ldr: 3661
+      fdpll0_ldrfrac: 1
       fdpll0_ref_clock: 32kHz External Crystal Oscillator (XOSC32K)
       fdpll1_arch_dcoen: false
       fdpll1_arch_enable: false
@@ -941,6 +1006,61 @@ drivers:
     variant: null
     clocks:
       domain_group: null
+  CALENDER_INTERFACE:
+    user_label: CALENDER_INTERFACE
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::RTC::driver_config_definition::Calendar::HAL:Driver:Calendar
+    functionality: Calendar
+    api: HAL:Driver:Calendar
+    configuration:
+      rtc_arch_init_reset: true
+      rtc_arch_prescaler: Peripheral clock divided by 1
+      rtc_cmpeo0: false
+      rtc_cmpeo1: false
+      rtc_event_control: false
+      rtc_ovfeo: false
+      rtc_pereo0: false
+      rtc_pereo1: false
+      rtc_pereo2: false
+      rtc_pereo3: false
+      rtc_pereo4: false
+      rtc_pereo5: false
+      rtc_pereo6: false
+      rtc_pereo7: false
+      rtc_tamper_active_layer_frequency_prescalar: DIV2 CLK_RTC_OUT is CLK_RTC /2
+      rtc_tamper_debounce_frequency_prescalar: DIV2 CLK_RTC_DEB is CLK_RTC /2
+      rtc_tamper_input_action_0: OFF(Disabled)
+      rtc_tamper_input_action_1: OFF(Disabled)
+      rtc_tamper_input_action_2: OFF(Disabled)
+      rtc_tamper_input_action_3: OFF(Disabled)
+      rtc_tamper_input_action_4: OFF(Disabled)
+      rtc_tampereo: false
+      rtc_tampevei: false
+      tamper_debounce_enable_0: false
+      tamper_debounce_enable_1: false
+      tamper_debounce_enable_2: false
+      tamper_debounce_enable_3: false
+      tamper_debounce_enable_4: false
+      tamper_input_0_settings: false
+      tamper_input_1_settings: false
+      tamper_input_2_settings: false
+      tamper_input_3_settings: false
+      tamper_input_4_settings: false
+      tamper_level_0: false
+      tamper_level_1: false
+      tamper_level_2: false
+      tamper_level_3: false
+      tamper_level_4: false
+    optional_signals: []
+    variant: null
+    clocks:
+      domain_group:
+        nodes:
+        - name: RTC
+          input: RTC source
+          external: false
+          external_frequency: 0
+        configuration:
+          rtc_clk_selection: RTC source
   USART_DBG:
     user_label: USART_DBG
     definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::SERCOM2::driver_config_definition::UART::HAL:Driver:USART.Sync
@@ -1034,6 +1154,49 @@ drivers:
         configuration:
           core_gclk_selection: Generic clock generator 0
           slow_gclk_selection: Generic clock generator 3
+  IO_BUS:
+    user_label: IO_BUS
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::SDHC0::driver_config_definition::MCI::HAL:Driver:MCI.Sync
+    functionality: MCI
+    api: HAL:Driver:MCI_Sync
+    configuration:
+      sdhc_clk_gsel: Divided Clock mode
+    optional_signals: []
+    variant:
+      specification: default
+      required_signals:
+      - name: SDHC0/SDCK
+        pad: PB11
+        label: SDCK
+      - name: SDHC0/SDCMD
+        pad: PA08
+        label: SDCMD
+      - name: SDHC0/SDDAT/0
+        pad: PA09
+        label: SDDAT/0
+      - name: SDHC0/SDDAT/1
+        pad: PA10
+        label: SDDAT/1
+      - name: SDHC0/SDDAT/2
+        pad: PA11
+        label: SDDAT/2
+      - name: SDHC0/SDDAT/3
+        pad: PB10
+        label: SDDAT/3
+    clocks:
+      domain_group:
+        nodes:
+        - name: SDHC
+          input: Generic clock generator 0
+          external: false
+          external_frequency: 0
+        - name: SDHC_Slow
+          input: Generic clock generator 0
+          external: false
+          external_frequency: 0
+        configuration:
+          sdhc_gclk_selection: Generic clock generator 0
+          sdhc_slow_gclk_selection: Generic clock generator 0
   DELAY_0:
     user_label: DELAY_0
     definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::SysTick::driver_config_definition::Delay::HAL:Driver:Delay
@@ -1046,6 +1209,42 @@ drivers:
     clocks:
       domain_group: null
 pads:
+  PA08:
+    name: PA08
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA08
+    mode: Advanced
+    user_label: PA08
+    configuration: null
+  PA09:
+    name: PA09
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA09
+    mode: Advanced
+    user_label: PA09
+    configuration: null
+  PA10:
+    name: PA10
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA10
+    mode: Advanced
+    user_label: PA10
+    configuration: null
+  PA11:
+    name: PA11
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA11
+    mode: Advanced
+    user_label: PA11
+    configuration: null
+  PB10:
+    name: PB10
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB10
+    mode: Advanced
+    user_label: PB10
+    configuration: null
+  PB11:
+    name: PB11
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB11
+    mode: Advanced
+    user_label: PB11
+    configuration: null
   PB24:
     name: PB24
     definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB24
diff --git a/atmel_start_pins.h b/atmel_start_pins.h
index 5d9e7d0..9ec5a4b 100644
--- a/atmel_start_pins.h
+++ b/atmel_start_pins.h
@@ -27,10 +27,24 @@
 #define GPIO_PIN_FUNCTION_M 12
 #define GPIO_PIN_FUNCTION_N 13
 
+#define PA04 GPIO(GPIO_PORTA, 4)
+#define PA08 GPIO(GPIO_PORTA, 8)
+#define PA09 GPIO(GPIO_PORTA, 9)
+#define PA10 GPIO(GPIO_PORTA, 10)
+#define PA11 GPIO(GPIO_PORTA, 11)
+#define PB10 GPIO(GPIO_PORTB, 10)
+#define PB11 GPIO(GPIO_PORTB, 11)
 #define PB24 GPIO(GPIO_PORTB, 24)
 #define PB25 GPIO(GPIO_PORTB, 25)
 #define PB26 GPIO(GPIO_PORTB, 26)
 #define PB27 GPIO(GPIO_PORTB, 27)
+#define PB28 GPIO(GPIO_PORTB, 28)
 #define PB29 GPIO(GPIO_PORTB, 29)
 
+#define SPI_CS PB28
+#define SPI_CS_PIN GPIO_PIN(SPI_CS)
+#define SPI_CS_PORT GPIO_PORT(SPI_CS)
+#define SPI_CD PA04
+
+
 #endif // ATMEL_START_PINS_H_INCLUDED
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new file mode 100644
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new file mode 100644
index 0000000..0179df2
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diff --git a/build/.cache/clangd/index/wdt.h.11E3B822DD1F2D31.idx b/build/.cache/clangd/index/wdt.h.11E3B822DD1F2D31.idx
new file mode 100644
index 0000000..6ce4cc6
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diff --git a/build/.cache/clangd/index/wdt.h.A87736EA973BA415.idx b/build/.cache/clangd/index/wdt.h.A87736EA973BA415.idx
new file mode 100644
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diff --git a/build/.gdb_history b/build/.gdb_history
new file mode 100644
index 0000000..048ca87
--- /dev/null
+++ b/build/.gdb_history
@@ -0,0 +1,170 @@
+q
+break main
+r
+n
+n
+n
+n
+q
+break main
+r
+n
+n
+n
+n
+c
+r
+n
+n
+n
+n
+c
+q
+break main.c:28
+r
+c
+r
+c
+q
+break main.c:29
+r
+c
+q
+break main.c:96
+r
+q
+break main.c:97
+r
+c
+q
+break main.c:92
+r
+c
+q
+break main
+r
+info break
+q
+q
+att 1
+q
+tar ext /dev/ttyACM0
+mon s
+mon s
+att 1
+load spi_sd_mmc_lib.elf 
+b main
+r
+r
+info b
+break main.c:12
+file spi_sd_mmc_lib.elf 
+break main.c:12
+r
+s
+s
+s
+finish
+finish
+q
+attach 13022
+q
+load
+q
+tar ext /dev/ttyACM0
+mon s
+mon s
+mon swdp_scan
+mon swdp_scan
+mon swdp_scan
+q
+tar ext /dev/ttyACM0
+mon s
+qq
+q
+mon s
+q
+q
+q
+set pagination off
+set logging file gdb.txt
+set logging redirect on
+set logging on
+tar ext /dev/ttyACM0
+blackmagic
+load
+mon s
+mon s
+tar ext /dev/ttyACM1
+q
+q
+q
+q
+q
+q
+q
+q
+q
+mon s
+status
+help
+q
+q
+q
+q
+break main
+r
+q
+q
+q
+mon s
+tar ext /dev/ttyACM0
+mon s
+mon
+q
+target extended-remote /dev/ttyACM0
+reset
+help
+mon s
+att 1
+q
+target extended-remote /dev/ttyACM1
+target extended-remote /dev/ttyACM0
+target extended-remote /dev/ttyACM0
+q
+tar ext /dev/ttyACM0
+mon s
+s
+det 1
+detach 1
+detach
+mon s
+mon s
+mon s
+q
+q
+tar ext /dev/ttyACM0
+mon s
+q
+target extended-remote /dev/ttyACM0
+attach 1
+b main
+file spi_sd_mmc_lib.elf 
+b main
+del 2
+load
+r
+detach
+q
+target extended-remote /dev/ttyACM0
+monitor reset
+reset
+help 
+help monitor
+target extended-remote /dev/ttyACM0
+mon s
+attach 1
+monitor reset
+r
+q
+q
diff --git a/build/.gitignore b/build/.gitignore
deleted file mode 100644
index 96d5d16..0000000
--- a/build/.gitignore
+++ /dev/null
@@ -1,13 +0,0 @@
-*
-
-!gcc
-!gcc/same54p20a_flash.ld
-!gcc/same54p20a_sram.ld
-!gcc/startup_same54.c
-!scripts
-!scripts/openocd.cfg
-!scripts/push.gdb
-!scripts/debug.gdb
-!.gitignore
-!system_same54.c
-!Makefile
diff --git a/build/Makefile b/build/Makefile
index 19d7024..135b430 100644
--- a/build/Makefile
+++ b/build/Makefile
@@ -30,22 +30,27 @@ endif
 # List the subdirectories for creating object files
 SUB_DIRS +=  \
  \
-hpl/pm \
-build \
-hpl/osc32kctrl \
 hpl/ramecc \
+sd_mmc \
+examples \
+hpl/systick \
+hpl/oscctrl \
+hpl/sdhc \
+fatfs/src \
+hpl/osc32kctrl \
 hpl/dmac \
 hal/src \
-hpl/mclk \
-hpl/systick \
 hal/utils/src \
-hpl/sercom \
-examples \
+diskio \
+hpl/rtc \
+build \
+hpl/pm \
+hpl/cmcc \
 hpl/gclk \
-hpl/oscctrl \
 build/gcc \
+hpl/mclk \
+hpl/sercom \
 hpl/core \
-hpl/cmcc \
 shared \
 shared/devices \
 shared/drivers \
@@ -55,69 +60,91 @@ shared/util
 OBJS +=  \
 hal/src/hal_io.o \
 hpl/systick/hpl_systick.o \
+hal/src/hal_calendar.o \
+sd_mmc_start.o \
+fatfs_main.o \
 hpl/core/hpl_core_m4.o \
+hal/src/hal_cache.o \
 hal/utils/src/utils_syscalls.o \
+sd_mmc/sd_mmc.o \
+sd_mmc/sd_mmc_spi.o \
 hal/src/hal_spi_m_sync.o \
-build/system_same54.o \
+hal/src/hal_mci_sync.o \
 hal/src/hal_delay.o \
 hpl/pm/hpl_pm.o \
 hpl/core/hpl_init.o \
 hpl/gclk/hpl_gclk.o \
 hal/utils/src/utils_list.o \
 hal/utils/src/utils_assert.o \
-hpl/dmac/hpl_dmac.o \
 hpl/oscctrl/hpl_oscctrl.o \
+hpl/sdhc/hpl_sdhc.o \
 hal/src/hal_usart_sync.o \
 hpl/mclk/hpl_mclk.o \
 hpl/ramecc/hpl_ramecc.o \
 hal/src/hal_init.o \
+diskio_start.o \
 build/gcc/startup_same54.o \
 main.o \
 hpl/osc32kctrl/hpl_osc32kctrl.o \
+diskio/sdmmc_diskio.o \
+hpl/rtc/hpl_rtc.o \
 examples/driver_examples.o \
 driver_init.o \
 hpl/sercom/hpl_sercom.o \
+hal/src/hal_atomic.o \
 hal/src/hal_gpio.o \
 hal/utils/src/utils_event.o \
 hal/src/hal_sleep.o \
-hal/src/hal_cache.o \
-hpl/cmcc/hpl_cmcc.o \
+hpl/dmac/hpl_dmac.o \
+build/system_same54.o \
 atmel_start.o \
-hal/src/hal_atomic.o \
+fatfs/src/ff.o \
+hpl/cmcc/hpl_cmcc.o \
 shared/util/pdebug.o
 
 OBJS_AS_ARGS +=  \
 "hal/src/hal_io.o" \
 "hpl/systick/hpl_systick.o" \
+"hal/src/hal_calendar.o" \
+"sd_mmc_start.o" \
+"fatfs_main.o" \
 "hpl/core/hpl_core_m4.o" \
+"hal/src/hal_cache.o" \
 "hal/utils/src/utils_syscalls.o" \
+"sd_mmc/sd_mmc.o" \
+"sd_mmc/sd_mmc_spi.o" \
 "hal/src/hal_spi_m_sync.o" \
-"build/system_same54.o" \
+"hal/src/hal_mci_sync.o" \
 "hal/src/hal_delay.o" \
 "hpl/pm/hpl_pm.o" \
 "hpl/core/hpl_init.o" \
 "hpl/gclk/hpl_gclk.o" \
 "hal/utils/src/utils_list.o" \
 "hal/utils/src/utils_assert.o" \
-"hpl/dmac/hpl_dmac.o" \
 "hpl/oscctrl/hpl_oscctrl.o" \
+"hpl/sdhc/hpl_sdhc.o" \
 "hal/src/hal_usart_sync.o" \
 "hpl/mclk/hpl_mclk.o" \
 "hpl/ramecc/hpl_ramecc.o" \
 "hal/src/hal_init.o" \
+"diskio_start.o" \
 "build/gcc/startup_same54.o" \
 "main.o" \
 "hpl/osc32kctrl/hpl_osc32kctrl.o" \
+"diskio/sdmmc_diskio.o" \
+"hpl/rtc/hpl_rtc.o" \
 "examples/driver_examples.o" \
 "driver_init.o" \
 "hpl/sercom/hpl_sercom.o" \
+"hal/src/hal_atomic.o" \
 "hal/src/hal_gpio.o" \
 "hal/utils/src/utils_event.o" \
 "hal/src/hal_sleep.o" \
-"hal/src/hal_cache.o" \
-"hpl/cmcc/hpl_cmcc.o" \
+"hpl/dmac/hpl_dmac.o" \
+"build/system_same54.o" \
 "atmel_start.o" \
-"hal/src/hal_atomic.o" \
+"fatfs/src/ff.o" \
+"hpl/cmcc/hpl_cmcc.o" \
 "shared/util/pdebug.o"
 
 
@@ -138,10 +165,19 @@ DIR_INCLUDES +=  \
 -I"../hpl/pm" \
 -I"../hpl/port" \
 -I"../hpl/ramecc" \
+-I"../hpl/rtc" \
+-I"../hpl/sdhc" \
 -I"../hpl/sercom" \
 -I"../hpl/systick" \
 -I"../hri" \
 -I"../" \
+-I"../config" \
+-I"../sd_mmc" \
+-I"../" \
+-I"../diskio" \
+-I"../" \
+-I"../fatfs/src" \
+-I"../" \
 -I"../CMSIS/Core/Include" \
 -I"../include" \
 -I"../shared" \
@@ -153,22 +189,30 @@ DIR_INCLUDES +=  \
 DEPS := $(OBJS:%.o=%.d)
 
 DEPS_AS_ARGS +=  \
+"hal/src/hal_calendar.d" \
 "hal/utils/src/utils_event.d" \
 "hal/src/hal_io.d" \
 "hpl/ramecc/hpl_ramecc.d" \
 "hpl/systick/hpl_systick.d" \
 "hpl/core/hpl_core_m4.d" \
+"fatfs_main.d" \
 "hal/utils/src/utils_syscalls.d" \
+"sd_mmc_start.d" \
+"sd_mmc/sd_mmc.d" \
+"sd_mmc/sd_mmc_spi.d" \
+"hal/src/hal_mci_sync.d" \
 "hal/src/hal_spi_m_sync.d" \
 "hal/utils/src/utils_list.d" \
 "hpl/cmcc/hpl_cmcc.d" \
 "hpl/dmac/hpl_dmac.d" \
 "hal/utils/src/utils_assert.d" \
+"hpl/sdhc/hpl_sdhc.d" \
 "hal/src/hal_delay.d" \
 "hpl/core/hpl_init.d" \
 "hpl/pm/hpl_pm.d" \
 "hpl/gclk/hpl_gclk.d" \
 "build/gcc/startup_same54.d" \
+"diskio_start.d" \
 "hal/src/hal_init.d" \
 "hal/src/hal_usart_sync.d" \
 "hpl/mclk/hpl_mclk.d" \
@@ -176,11 +220,14 @@ DEPS_AS_ARGS +=  \
 "hpl/osc32kctrl/hpl_osc32kctrl.d" \
 "main.d" \
 "examples/driver_examples.d" \
+"hpl/rtc/hpl_rtc.d" \
+"diskio/sdmmc_diskio.d" \
 "hal/src/hal_cache.d" \
 "hal/src/hal_sleep.d" \
 "hpl/sercom/hpl_sercom.d" \
 "hal/src/hal_gpio.d" \
 "hal/src/hal_atomic.d" \
+"fatfs/src/ff.d" \
 "hpl/oscctrl/hpl_oscctrl.d" \
 "build/system_same54.d" \
 "atmel_start.d" \
@@ -270,12 +317,12 @@ clean:
         $(OUTPUT_FILE_NAME).lss $(OUTPUT_FILE_NAME).eep $(OUTPUT_FILE_NAME).map \
         $(OUTPUT_FILE_NAME).srec
 debug: $(OUTPUT_FILE_NAME).elf
-	@$(QUOTE)arm-none-eabi-gdb$(QUOTE) $(OUTPUT_FILE_NAME).elf -x scripts/debug.gdb
+	@$(QUOTE)${ESF_DIR}/toolchains/arm-none-eabi-toolchain/bin/arm-none-eabi-gdb-py$(QUOTE) $(OUTPUT_FILE_NAME).elf -x scripts/debug.gdb
 
 push: $(OUTPUT_FILE_NAME).elf
 	@echo $(QUOTE)$(QUOTE)
 	@echo $(QUOTE)Uploading $(OUTPUT_FILE_NAME).elf...$(QUOTE)
-	@$(QUOTE)arm-none-eabi-gdb$(QUOTE) $(OUTPUT_FILE_NAME).elf -x scripts/push.gdb >/dev/null
+	@$(QUOTE)${ESF_DIR}/toolchains/arm-none-eabi-toolchain/bin/arm-none-eabi-gdb-py$(QUOTE) $(OUTPUT_FILE_NAME).elf -x scripts/push.gdb
 	@echo $(QUOTE)$(QUOTE)$(OUTPUT_FILE_NAME).elf$(QUOTE) uploaded!$(QUOTE)
 	@$(QUOTE)arm-none-eabi-size$(QUOTE) $(QUOTE)$(OUTPUT_FILE_NAME).elf$(QUOTE)
 
diff --git a/build/atmel_start.d b/build/atmel_start.d
new file mode 100644
index 0000000..898bc67
--- /dev/null
+++ b/build/atmel_start.d
@@ -0,0 +1,334 @@
+atmel_start.d atmel_start.o: ../atmel_start.c ../atmel_start.h \
+ ../driver_init.h ../atmel_start_pins.h ../hal/include/hal_gpio.h \
+ ../hal/include/hpl_gpio.h ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h ../hpl/port/hpl_gpio_base.h \
+ ../hal/utils/include/utils_assert.h ../config/hpl_port_config.h \
+ ../hal/include/hal_delay.h ../hal/include/hpl_irq.h \
+ ../hal/include/hpl_reset.h ../hal/include/hpl_sleep.h \
+ ../hal/include/hal_init.h ../hal/include/hpl_init.h \
+ ../hal/include/hal_io.h ../hal/include/hal_sleep.h \
+ ../hal/include/hal_calendar.h ../hal/include/hpl_calendar.h \
+ ../hal/utils/include/utils_list.h ../hal/include/hpl_irq.h \
+ ../hal/include/hal_usart_sync.h ../hal/include/hal_io.h \
+ ../hal/include/hpl_usart_sync.h ../hal/include/hpl_usart.h \
+ ../hal/include/hal_spi_m_sync.h ../hal/include/hpl_spi_m_sync.h \
+ ../hal/include/hpl_spi.h ../hal/utils/include/utils.h \
+ ../hal/include/hpl_spi_sync.h ../hal/include/hal_mci_sync.h \
+ ../hal/include/hpl_mci_sync.h ../sd_mmc_start.h \
+ /usr/arm-none-eabi/include/stdio.h /usr/arm-none-eabi/include/_ansi.h \
+ /usr/arm-none-eabi/include/newlib.h \
+ /usr/arm-none-eabi/include/sys/config.h \
+ /usr/arm-none-eabi/include/machine/ieeefp.h \
+ /usr/arm-none-eabi/include/sys/cdefs.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdarg.h \
+ /usr/arm-none-eabi/include/sys/reent.h \
+ /usr/arm-none-eabi/include/_ansi.h \
+ /usr/arm-none-eabi/include/sys/_types.h \
+ /usr/arm-none-eabi/include/machine/_types.h \
+ /usr/arm-none-eabi/include/sys/lock.h \
+ /usr/arm-none-eabi/include/sys/types.h \
+ /usr/arm-none-eabi/include/machine/endian.h \
+ /usr/arm-none-eabi/include/machine/_endian.h \
+ /usr/arm-none-eabi/include/sys/select.h \
+ /usr/arm-none-eabi/include/sys/_sigset.h \
+ /usr/arm-none-eabi/include/sys/_timeval.h \
+ /usr/arm-none-eabi/include/sys/timespec.h \
+ /usr/arm-none-eabi/include/sys/_timespec.h \
+ /usr/arm-none-eabi/include/sys/_pthreadtypes.h \
+ /usr/arm-none-eabi/include/sys/sched.h \
+ /usr/arm-none-eabi/include/machine/types.h \
+ /usr/arm-none-eabi/include/sys/stdio.h ../diskio_start.h
+../atmel_start.h:
+../driver_init.h:
+../atmel_start_pins.h:
+../hal/include/hal_gpio.h:
+../hal/include/hpl_gpio.h:
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
+../hpl/port/hpl_gpio_base.h:
+../hal/utils/include/utils_assert.h:
+../config/hpl_port_config.h:
+../hal/include/hal_delay.h:
+../hal/include/hpl_irq.h:
+../hal/include/hpl_reset.h:
+../hal/include/hpl_sleep.h:
+../hal/include/hal_init.h:
+../hal/include/hpl_init.h:
+../hal/include/hal_io.h:
+../hal/include/hal_sleep.h:
+../hal/include/hal_calendar.h:
+../hal/include/hpl_calendar.h:
+../hal/utils/include/utils_list.h:
+../hal/include/hpl_irq.h:
+../hal/include/hal_usart_sync.h:
+../hal/include/hal_io.h:
+../hal/include/hpl_usart_sync.h:
+../hal/include/hpl_usart.h:
+../hal/include/hal_spi_m_sync.h:
+../hal/include/hpl_spi_m_sync.h:
+../hal/include/hpl_spi.h:
+../hal/utils/include/utils.h:
+../hal/include/hpl_spi_sync.h:
+../hal/include/hal_mci_sync.h:
+../hal/include/hpl_mci_sync.h:
+../sd_mmc_start.h:
+/usr/arm-none-eabi/include/stdio.h:
+/usr/arm-none-eabi/include/_ansi.h:
+/usr/arm-none-eabi/include/newlib.h:
+/usr/arm-none-eabi/include/sys/config.h:
+/usr/arm-none-eabi/include/machine/ieeefp.h:
+/usr/arm-none-eabi/include/sys/cdefs.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdarg.h:
+/usr/arm-none-eabi/include/sys/reent.h:
+/usr/arm-none-eabi/include/_ansi.h:
+/usr/arm-none-eabi/include/sys/_types.h:
+/usr/arm-none-eabi/include/machine/_types.h:
+/usr/arm-none-eabi/include/sys/lock.h:
+/usr/arm-none-eabi/include/sys/types.h:
+/usr/arm-none-eabi/include/machine/endian.h:
+/usr/arm-none-eabi/include/machine/_endian.h:
+/usr/arm-none-eabi/include/sys/select.h:
+/usr/arm-none-eabi/include/sys/_sigset.h:
+/usr/arm-none-eabi/include/sys/_timeval.h:
+/usr/arm-none-eabi/include/sys/timespec.h:
+/usr/arm-none-eabi/include/sys/_timespec.h:
+/usr/arm-none-eabi/include/sys/_pthreadtypes.h:
+/usr/arm-none-eabi/include/sys/sched.h:
+/usr/arm-none-eabi/include/machine/types.h:
+/usr/arm-none-eabi/include/sys/stdio.h:
+../diskio_start.h:
diff --git a/build/atmel_start.o b/build/atmel_start.o
new file mode 100644
index 0000000..e5425a0
Binary files /dev/null and b/build/atmel_start.o differ
diff --git a/build/build/gcc/startup_same54.d b/build/build/gcc/startup_same54.d
new file mode 100644
index 0000000..b757c09
--- /dev/null
+++ b/build/build/gcc/startup_same54.d
@@ -0,0 +1,177 @@
+build/gcc/startup_same54.d build/gcc/startup_same54.o: \
+ ../build/gcc/startup_same54.c ../include/same54.h \
+ ../include/same54p20a.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h
+../include/same54.h:
+../include/same54p20a.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
diff --git a/build/build/gcc/startup_same54.o b/build/build/gcc/startup_same54.o
new file mode 100644
index 0000000..b3b17b7
Binary files /dev/null and b/build/build/gcc/startup_same54.o differ
diff --git a/build/build/system_same54.d b/build/build/system_same54.d
new file mode 100644
index 0000000..4a0f8cd
--- /dev/null
+++ b/build/build/system_same54.d
@@ -0,0 +1,176 @@
+build/system_same54.d build/system_same54.o: ../build/system_same54.c \
+ ../include/same54.h ../include/same54p20a.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h
+../include/same54.h:
+../include/same54p20a.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
diff --git a/build/build/system_same54.o b/build/build/system_same54.o
new file mode 100644
index 0000000..2b3162e
Binary files /dev/null and b/build/build/system_same54.o differ
diff --git a/build/compile_commands.json b/build/compile_commands.json
new file mode 100644
index 0000000..e9f9333
--- /dev/null
+++ b/build/compile_commands.json
@@ -0,0 +1,2625 @@
+[
+  {
+    "arguments": [
+      "/usr/bin/arm-none-eabi-gcc",
+      "-x",
+      "c",
+      "-mthumb",
+      "-DDEBUG",
+      "-Os",
+      "-ffunction-sections",
+      "-mlong-calls",
+      "-g3",
+      "-Wall",
+      "-c",
+      "-std=gnu99",
+      "-D__SAME54P20A__",
+      "-mcpu=cortex-m4",
+      "-mfloat-abi=softfp",
+      "-mfpu=fpv4-sp-d16",
+      "-I../",
+      "-I../config",
+      "-I../examples",
+      "-I../hal/include",
+      "-I../hal/utils/include",
+      "-I../hpl/cmcc",
+      "-I../hpl/core",
+      "-I../hpl/dmac",
+      "-I../hpl/gclk",
+      "-I../hpl/mclk",
+      "-I../hpl/osc32kctrl",
+      "-I../hpl/oscctrl",
+      "-I../hpl/pm",
+      "-I../hpl/port",
+      "-I../hpl/ramecc",
+      "-I../hpl/rtc",
+      "-I../hpl/sdhc",
+      "-I../hpl/sercom",
+      "-I../hpl/systick",
+      "-I../hri",
+      "-I../",
+      "-I../config",
+      "-I../sd_mmc",
+      "-I../",
+      "-I../diskio",
+      "-I../",
+      "-I../fatfs/src",
+      "-I../",
+      "-I../CMSIS/Core/Include",
+      "-I../include",
+      "-I../shared",
+      "-I../shared/drivers",
+      "-I../shared/devices",
+      "-I../shared/util",
+      "-MThal/src/hal_calendar.o",
+      "-o",
+      "hal/src/hal_calendar.o",
+      "../hal/src/hal_calendar.c"
+    ],
+    "directory": "/storage/Shared/Documents/Projects/spi_sd_mmc_lib/build",
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+      "-I../sd_mmc",
+      "-I../",
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+      "-I../sd_mmc",
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+  },
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+      "-MThal/utils/src/utils_syscalls.o",
+      "-o",
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+  },
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+      "-I../hpl/sdhc",
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+      "-o",
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+  },
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+      "-I../shared/devices",
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+      "-MThal/src/hal_spi_m_sync.o",
+      "-o",
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+  },
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+      "-MThal/src/hal_mci_sync.o",
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+      "-I../hpl/rtc",
+      "-I../hpl/sdhc",
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+      "-I../",
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+      "-I../sd_mmc",
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+      "-I../fatfs/src",
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+      "-I../include",
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+      "-MThpl/gclk/hpl_gclk.o",
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+  },
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+      "-MThal/utils/src/utils_list.o",
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+      "-MThal/utils/src/utils_assert.o",
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+  },
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+  },
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+      "-I../include",
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+      "-I../shared/devices",
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+  },
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+  },
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+      "-mthumb",
+      "-DDEBUG",
+      "-Os",
+      "-ffunction-sections",
+      "-mlong-calls",
+      "-g3",
+      "-Wall",
+      "-c",
+      "-std=gnu99",
+      "-D__SAME54P20A__",
+      "-mcpu=cortex-m4",
+      "-mfloat-abi=softfp",
+      "-mfpu=fpv4-sp-d16",
+      "-I../",
+      "-I../config",
+      "-I../examples",
+      "-I../hal/include",
+      "-I../hal/utils/include",
+      "-I../hpl/cmcc",
+      "-I../hpl/core",
+      "-I../hpl/dmac",
+      "-I../hpl/gclk",
+      "-I../hpl/mclk",
+      "-I../hpl/osc32kctrl",
+      "-I../hpl/oscctrl",
+      "-I../hpl/pm",
+      "-I../hpl/port",
+      "-I../hpl/ramecc",
+      "-I../hpl/rtc",
+      "-I../hpl/sdhc",
+      "-I../hpl/sercom",
+      "-I../hpl/systick",
+      "-I../hri",
+      "-I../",
+      "-I../config",
+      "-I../sd_mmc",
+      "-I../",
+      "-I../diskio",
+      "-I../",
+      "-I../fatfs/src",
+      "-I../",
+      "-I../CMSIS/Core/Include",
+      "-I../include",
+      "-I../shared",
+      "-I../shared/drivers",
+      "-I../shared/devices",
+      "-I../shared/util",
+      "-MThal/src/hal_gpio.o",
+      "-o",
+      "hal/src/hal_gpio.o",
+      "../hal/src/hal_gpio.c"
+    ],
+    "directory": "/storage/Shared/Documents/Projects/spi_sd_mmc_lib/build",
+    "file": "/storage/Shared/Documents/Projects/spi_sd_mmc_lib/build/../hal/src/hal_gpio.c",
+    "output": "/storage/Shared/Documents/Projects/spi_sd_mmc_lib/build/hal/src/hal_gpio.o"
+  },
+  {
+    "arguments": [
+      "/usr/bin/arm-none-eabi-gcc",
+      "-x",
+      "c",
+      "-mthumb",
+      "-DDEBUG",
+      "-Os",
+      "-ffunction-sections",
+      "-mlong-calls",
+      "-g3",
+      "-Wall",
+      "-c",
+      "-std=gnu99",
+      "-D__SAME54P20A__",
+      "-mcpu=cortex-m4",
+      "-mfloat-abi=softfp",
+      "-mfpu=fpv4-sp-d16",
+      "-I../",
+      "-I../config",
+      "-I../examples",
+      "-I../hal/include",
+      "-I../hal/utils/include",
+      "-I../hpl/cmcc",
+      "-I../hpl/core",
+      "-I../hpl/dmac",
+      "-I../hpl/gclk",
+      "-I../hpl/mclk",
+      "-I../hpl/osc32kctrl",
+      "-I../hpl/oscctrl",
+      "-I../hpl/pm",
+      "-I../hpl/port",
+      "-I../hpl/ramecc",
+      "-I../hpl/rtc",
+      "-I../hpl/sdhc",
+      "-I../hpl/sercom",
+      "-I../hpl/systick",
+      "-I../hri",
+      "-I../",
+      "-I../config",
+      "-I../sd_mmc",
+      "-I../",
+      "-I../diskio",
+      "-I../",
+      "-I../fatfs/src",
+      "-I../",
+      "-I../CMSIS/Core/Include",
+      "-I../include",
+      "-I../shared",
+      "-I../shared/drivers",
+      "-I../shared/devices",
+      "-I../shared/util",
+      "-MThal/utils/src/utils_event.o",
+      "-o",
+      "hal/utils/src/utils_event.o",
+      "../hal/utils/src/utils_event.c"
+    ],
+    "directory": "/storage/Shared/Documents/Projects/spi_sd_mmc_lib/build",
+    "file": "/storage/Shared/Documents/Projects/spi_sd_mmc_lib/build/../hal/utils/src/utils_event.c",
+    "output": "/storage/Shared/Documents/Projects/spi_sd_mmc_lib/build/hal/utils/src/utils_event.o"
+  },
+  {
+    "arguments": [
+      "/usr/bin/arm-none-eabi-gcc",
+      "-x",
+      "c",
+      "-mthumb",
+      "-DDEBUG",
+      "-Os",
+      "-ffunction-sections",
+      "-mlong-calls",
+      "-g3",
+      "-Wall",
+      "-c",
+      "-std=gnu99",
+      "-D__SAME54P20A__",
+      "-mcpu=cortex-m4",
+      "-mfloat-abi=softfp",
+      "-mfpu=fpv4-sp-d16",
+      "-I../",
+      "-I../config",
+      "-I../examples",
+      "-I../hal/include",
+      "-I../hal/utils/include",
+      "-I../hpl/cmcc",
+      "-I../hpl/core",
+      "-I../hpl/dmac",
+      "-I../hpl/gclk",
+      "-I../hpl/mclk",
+      "-I../hpl/osc32kctrl",
+      "-I../hpl/oscctrl",
+      "-I../hpl/pm",
+      "-I../hpl/port",
+      "-I../hpl/ramecc",
+      "-I../hpl/rtc",
+      "-I../hpl/sdhc",
+      "-I../hpl/sercom",
+      "-I../hpl/systick",
+      "-I../hri",
+      "-I../",
+      "-I../config",
+      "-I../sd_mmc",
+      "-I../",
+      "-I../diskio",
+      "-I../",
+      "-I../fatfs/src",
+      "-I../",
+      "-I../CMSIS/Core/Include",
+      "-I../include",
+      "-I../shared",
+      "-I../shared/drivers",
+      "-I../shared/devices",
+      "-I../shared/util",
+      "-MThal/src/hal_sleep.o",
+      "-o",
+      "hal/src/hal_sleep.o",
+      "../hal/src/hal_sleep.c"
+    ],
+    "directory": "/storage/Shared/Documents/Projects/spi_sd_mmc_lib/build",
+    "file": "/storage/Shared/Documents/Projects/spi_sd_mmc_lib/build/../hal/src/hal_sleep.c",
+    "output": "/storage/Shared/Documents/Projects/spi_sd_mmc_lib/build/hal/src/hal_sleep.o"
+  },
+  {
+    "arguments": [
+      "/usr/bin/arm-none-eabi-gcc",
+      "-x",
+      "c",
+      "-mthumb",
+      "-DDEBUG",
+      "-Os",
+      "-ffunction-sections",
+      "-mlong-calls",
+      "-g3",
+      "-Wall",
+      "-c",
+      "-std=gnu99",
+      "-D__SAME54P20A__",
+      "-mcpu=cortex-m4",
+      "-mfloat-abi=softfp",
+      "-mfpu=fpv4-sp-d16",
+      "-I../",
+      "-I../config",
+      "-I../examples",
+      "-I../hal/include",
+      "-I../hal/utils/include",
+      "-I../hpl/cmcc",
+      "-I../hpl/core",
+      "-I../hpl/dmac",
+      "-I../hpl/gclk",
+      "-I../hpl/mclk",
+      "-I../hpl/osc32kctrl",
+      "-I../hpl/oscctrl",
+      "-I../hpl/pm",
+      "-I../hpl/port",
+      "-I../hpl/ramecc",
+      "-I../hpl/rtc",
+      "-I../hpl/sdhc",
+      "-I../hpl/sercom",
+      "-I../hpl/systick",
+      "-I../hri",
+      "-I../",
+      "-I../config",
+      "-I../sd_mmc",
+      "-I../",
+      "-I../diskio",
+      "-I../",
+      "-I../fatfs/src",
+      "-I../",
+      "-I../CMSIS/Core/Include",
+      "-I../include",
+      "-I../shared",
+      "-I../shared/drivers",
+      "-I../shared/devices",
+      "-I../shared/util",
+      "-MThpl/dmac/hpl_dmac.o",
+      "-o",
+      "hpl/dmac/hpl_dmac.o",
+      "../hpl/dmac/hpl_dmac.c"
+    ],
+    "directory": "/storage/Shared/Documents/Projects/spi_sd_mmc_lib/build",
+    "file": "/storage/Shared/Documents/Projects/spi_sd_mmc_lib/build/../hpl/dmac/hpl_dmac.c",
+    "output": "/storage/Shared/Documents/Projects/spi_sd_mmc_lib/build/hpl/dmac/hpl_dmac.o"
+  },
+  {
+    "arguments": [
+      "/usr/bin/arm-none-eabi-gcc",
+      "-x",
+      "c",
+      "-mthumb",
+      "-DDEBUG",
+      "-Os",
+      "-ffunction-sections",
+      "-mlong-calls",
+      "-g3",
+      "-Wall",
+      "-c",
+      "-std=gnu99",
+      "-D__SAME54P20A__",
+      "-mcpu=cortex-m4",
+      "-mfloat-abi=softfp",
+      "-mfpu=fpv4-sp-d16",
+      "-I../",
+      "-I../config",
+      "-I../examples",
+      "-I../hal/include",
+      "-I../hal/utils/include",
+      "-I../hpl/cmcc",
+      "-I../hpl/core",
+      "-I../hpl/dmac",
+      "-I../hpl/gclk",
+      "-I../hpl/mclk",
+      "-I../hpl/osc32kctrl",
+      "-I../hpl/oscctrl",
+      "-I../hpl/pm",
+      "-I../hpl/port",
+      "-I../hpl/ramecc",
+      "-I../hpl/rtc",
+      "-I../hpl/sdhc",
+      "-I../hpl/sercom",
+      "-I../hpl/systick",
+      "-I../hri",
+      "-I../",
+      "-I../config",
+      "-I../sd_mmc",
+      "-I../",
+      "-I../diskio",
+      "-I../",
+      "-I../fatfs/src",
+      "-I../",
+      "-I../CMSIS/Core/Include",
+      "-I../include",
+      "-I../shared",
+      "-I../shared/drivers",
+      "-I../shared/devices",
+      "-I../shared/util",
+      "-MTbuild/system_same54.o",
+      "-o",
+      "build/system_same54.o",
+      "../build/system_same54.c"
+    ],
+    "directory": "/storage/Shared/Documents/Projects/spi_sd_mmc_lib/build",
+    "file": "/storage/Shared/Documents/Projects/spi_sd_mmc_lib/build/../build/system_same54.c",
+    "output": "/storage/Shared/Documents/Projects/spi_sd_mmc_lib/build/build/system_same54.o"
+  },
+  {
+    "arguments": [
+      "/usr/bin/arm-none-eabi-gcc",
+      "-x",
+      "c",
+      "-mthumb",
+      "-DDEBUG",
+      "-Os",
+      "-ffunction-sections",
+      "-mlong-calls",
+      "-g3",
+      "-Wall",
+      "-c",
+      "-std=gnu99",
+      "-D__SAME54P20A__",
+      "-mcpu=cortex-m4",
+      "-mfloat-abi=softfp",
+      "-mfpu=fpv4-sp-d16",
+      "-I../",
+      "-I../config",
+      "-I../examples",
+      "-I../hal/include",
+      "-I../hal/utils/include",
+      "-I../hpl/cmcc",
+      "-I../hpl/core",
+      "-I../hpl/dmac",
+      "-I../hpl/gclk",
+      "-I../hpl/mclk",
+      "-I../hpl/osc32kctrl",
+      "-I../hpl/oscctrl",
+      "-I../hpl/pm",
+      "-I../hpl/port",
+      "-I../hpl/ramecc",
+      "-I../hpl/rtc",
+      "-I../hpl/sdhc",
+      "-I../hpl/sercom",
+      "-I../hpl/systick",
+      "-I../hri",
+      "-I../",
+      "-I../config",
+      "-I../sd_mmc",
+      "-I../",
+      "-I../diskio",
+      "-I../",
+      "-I../fatfs/src",
+      "-I../",
+      "-I../CMSIS/Core/Include",
+      "-I../include",
+      "-I../shared",
+      "-I../shared/drivers",
+      "-I../shared/devices",
+      "-I../shared/util",
+      "-MTatmel_start.o",
+      "-o",
+      "atmel_start.o",
+      "../atmel_start.c"
+    ],
+    "directory": "/storage/Shared/Documents/Projects/spi_sd_mmc_lib/build",
+    "file": "/storage/Shared/Documents/Projects/spi_sd_mmc_lib/build/../atmel_start.c",
+    "output": "/storage/Shared/Documents/Projects/spi_sd_mmc_lib/build/atmel_start.o"
+  },
+  {
+    "arguments": [
+      "/usr/bin/arm-none-eabi-gcc",
+      "-x",
+      "c",
+      "-mthumb",
+      "-DDEBUG",
+      "-Os",
+      "-ffunction-sections",
+      "-mlong-calls",
+      "-g3",
+      "-Wall",
+      "-c",
+      "-std=gnu99",
+      "-D__SAME54P20A__",
+      "-mcpu=cortex-m4",
+      "-mfloat-abi=softfp",
+      "-mfpu=fpv4-sp-d16",
+      "-I../",
+      "-I../config",
+      "-I../examples",
+      "-I../hal/include",
+      "-I../hal/utils/include",
+      "-I../hpl/cmcc",
+      "-I../hpl/core",
+      "-I../hpl/dmac",
+      "-I../hpl/gclk",
+      "-I../hpl/mclk",
+      "-I../hpl/osc32kctrl",
+      "-I../hpl/oscctrl",
+      "-I../hpl/pm",
+      "-I../hpl/port",
+      "-I../hpl/ramecc",
+      "-I../hpl/rtc",
+      "-I../hpl/sdhc",
+      "-I../hpl/sercom",
+      "-I../hpl/systick",
+      "-I../hri",
+      "-I../",
+      "-I../config",
+      "-I../sd_mmc",
+      "-I../",
+      "-I../diskio",
+      "-I../",
+      "-I../fatfs/src",
+      "-I../",
+      "-I../CMSIS/Core/Include",
+      "-I../include",
+      "-I../shared",
+      "-I../shared/drivers",
+      "-I../shared/devices",
+      "-I../shared/util",
+      "-MTfatfs/src/ff.o",
+      "-o",
+      "fatfs/src/ff.o",
+      "../fatfs/src/ff.c"
+    ],
+    "directory": "/storage/Shared/Documents/Projects/spi_sd_mmc_lib/build",
+    "file": "/storage/Shared/Documents/Projects/spi_sd_mmc_lib/build/../fatfs/src/ff.c",
+    "output": "/storage/Shared/Documents/Projects/spi_sd_mmc_lib/build/fatfs/src/ff.o"
+  },
+  {
+    "arguments": [
+      "/usr/bin/arm-none-eabi-gcc",
+      "-x",
+      "c",
+      "-mthumb",
+      "-DDEBUG",
+      "-Os",
+      "-ffunction-sections",
+      "-mlong-calls",
+      "-g3",
+      "-Wall",
+      "-c",
+      "-std=gnu99",
+      "-D__SAME54P20A__",
+      "-mcpu=cortex-m4",
+      "-mfloat-abi=softfp",
+      "-mfpu=fpv4-sp-d16",
+      "-I../",
+      "-I../config",
+      "-I../examples",
+      "-I../hal/include",
+      "-I../hal/utils/include",
+      "-I../hpl/cmcc",
+      "-I../hpl/core",
+      "-I../hpl/dmac",
+      "-I../hpl/gclk",
+      "-I../hpl/mclk",
+      "-I../hpl/osc32kctrl",
+      "-I../hpl/oscctrl",
+      "-I../hpl/pm",
+      "-I../hpl/port",
+      "-I../hpl/ramecc",
+      "-I../hpl/rtc",
+      "-I../hpl/sdhc",
+      "-I../hpl/sercom",
+      "-I../hpl/systick",
+      "-I../hri",
+      "-I../",
+      "-I../config",
+      "-I../sd_mmc",
+      "-I../",
+      "-I../diskio",
+      "-I../",
+      "-I../fatfs/src",
+      "-I../",
+      "-I../CMSIS/Core/Include",
+      "-I../include",
+      "-I../shared",
+      "-I../shared/drivers",
+      "-I../shared/devices",
+      "-I../shared/util",
+      "-MThpl/cmcc/hpl_cmcc.o",
+      "-o",
+      "hpl/cmcc/hpl_cmcc.o",
+      "../hpl/cmcc/hpl_cmcc.c"
+    ],
+    "directory": "/storage/Shared/Documents/Projects/spi_sd_mmc_lib/build",
+    "file": "/storage/Shared/Documents/Projects/spi_sd_mmc_lib/build/../hpl/cmcc/hpl_cmcc.c",
+    "output": "/storage/Shared/Documents/Projects/spi_sd_mmc_lib/build/hpl/cmcc/hpl_cmcc.o"
+  },
+  {
+    "arguments": [
+      "/usr/bin/arm-none-eabi-gcc",
+      "-x",
+      "c",
+      "-mthumb",
+      "-DDEBUG",
+      "-Os",
+      "-ffunction-sections",
+      "-mlong-calls",
+      "-g3",
+      "-Wall",
+      "-c",
+      "-std=gnu99",
+      "-D__SAME54P20A__",
+      "-mcpu=cortex-m4",
+      "-mfloat-abi=softfp",
+      "-mfpu=fpv4-sp-d16",
+      "-I../",
+      "-I../config",
+      "-I../examples",
+      "-I../hal/include",
+      "-I../hal/utils/include",
+      "-I../hpl/cmcc",
+      "-I../hpl/core",
+      "-I../hpl/dmac",
+      "-I../hpl/gclk",
+      "-I../hpl/mclk",
+      "-I../hpl/osc32kctrl",
+      "-I../hpl/oscctrl",
+      "-I../hpl/pm",
+      "-I../hpl/port",
+      "-I../hpl/ramecc",
+      "-I../hpl/rtc",
+      "-I../hpl/sdhc",
+      "-I../hpl/sercom",
+      "-I../hpl/systick",
+      "-I../hri",
+      "-I../",
+      "-I../config",
+      "-I../sd_mmc",
+      "-I../",
+      "-I../diskio",
+      "-I../",
+      "-I../fatfs/src",
+      "-I../",
+      "-I../CMSIS/Core/Include",
+      "-I../include",
+      "-I../shared",
+      "-I../shared/drivers",
+      "-I../shared/devices",
+      "-I../shared/util",
+      "-MTshared/util/pdebug.o",
+      "-o",
+      "shared/util/pdebug.o",
+      "../shared/util/pdebug.c"
+    ],
+    "directory": "/storage/Shared/Documents/Projects/spi_sd_mmc_lib/build",
+    "file": "/storage/Shared/Documents/Projects/spi_sd_mmc_lib/build/../shared/util/pdebug.c",
+    "output": "/storage/Shared/Documents/Projects/spi_sd_mmc_lib/build/shared/util/pdebug.o"
+  }
+]
diff --git a/build/diskio/sdmmc_diskio.d b/build/diskio/sdmmc_diskio.d
new file mode 100644
index 0000000..f75e1c0
--- /dev/null
+++ b/build/diskio/sdmmc_diskio.d
@@ -0,0 +1,245 @@
+diskio/sdmmc_diskio.d diskio/sdmmc_diskio.o: ../diskio/sdmmc_diskio.c \
+ ../sd_mmc/sd_mmc.h ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h ../config/conf_sd_mmc.h \
+ ../diskio/diskio.h ../hal/utils/include/err_codes.h
+../sd_mmc/sd_mmc.h:
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
+../config/conf_sd_mmc.h:
+../diskio/diskio.h:
+../hal/utils/include/err_codes.h:
diff --git a/build/diskio/sdmmc_diskio.o b/build/diskio/sdmmc_diskio.o
new file mode 100644
index 0000000..b1fa145
Binary files /dev/null and b/build/diskio/sdmmc_diskio.o differ
diff --git a/build/diskio_start.d b/build/diskio_start.d
new file mode 100644
index 0000000..a3cee5c
--- /dev/null
+++ b/build/diskio_start.d
@@ -0,0 +1,335 @@
+diskio_start.d diskio_start.o: ../diskio_start.c ../diskio_start.h \
+ ../atmel_start.h ../driver_init.h ../atmel_start_pins.h \
+ ../hal/include/hal_gpio.h ../hal/include/hpl_gpio.h \
+ ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h ../hpl/port/hpl_gpio_base.h \
+ ../hal/utils/include/utils_assert.h ../config/hpl_port_config.h \
+ ../hal/include/hal_delay.h ../hal/include/hpl_irq.h \
+ ../hal/include/hpl_reset.h ../hal/include/hpl_sleep.h \
+ ../hal/include/hal_init.h ../hal/include/hpl_init.h \
+ ../hal/include/hal_io.h ../hal/include/hal_sleep.h \
+ ../hal/include/hal_calendar.h ../hal/include/hpl_calendar.h \
+ ../hal/utils/include/utils_list.h ../hal/include/hpl_irq.h \
+ ../hal/include/hal_usart_sync.h ../hal/include/hal_io.h \
+ ../hal/include/hpl_usart_sync.h ../hal/include/hpl_usart.h \
+ ../hal/include/hal_spi_m_sync.h ../hal/include/hpl_spi_m_sync.h \
+ ../hal/include/hpl_spi.h ../hal/utils/include/utils.h \
+ ../hal/include/hpl_spi_sync.h ../hal/include/hal_mci_sync.h \
+ ../hal/include/hpl_mci_sync.h ../sd_mmc_start.h \
+ /usr/arm-none-eabi/include/stdio.h /usr/arm-none-eabi/include/_ansi.h \
+ /usr/arm-none-eabi/include/newlib.h \
+ /usr/arm-none-eabi/include/sys/config.h \
+ /usr/arm-none-eabi/include/machine/ieeefp.h \
+ /usr/arm-none-eabi/include/sys/cdefs.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdarg.h \
+ /usr/arm-none-eabi/include/sys/reent.h \
+ /usr/arm-none-eabi/include/_ansi.h \
+ /usr/arm-none-eabi/include/sys/_types.h \
+ /usr/arm-none-eabi/include/machine/_types.h \
+ /usr/arm-none-eabi/include/sys/lock.h \
+ /usr/arm-none-eabi/include/sys/types.h \
+ /usr/arm-none-eabi/include/machine/endian.h \
+ /usr/arm-none-eabi/include/machine/_endian.h \
+ /usr/arm-none-eabi/include/sys/select.h \
+ /usr/arm-none-eabi/include/sys/_sigset.h \
+ /usr/arm-none-eabi/include/sys/_timeval.h \
+ /usr/arm-none-eabi/include/sys/timespec.h \
+ /usr/arm-none-eabi/include/sys/_timespec.h \
+ /usr/arm-none-eabi/include/sys/_pthreadtypes.h \
+ /usr/arm-none-eabi/include/sys/sched.h \
+ /usr/arm-none-eabi/include/machine/types.h \
+ /usr/arm-none-eabi/include/sys/stdio.h
+../diskio_start.h:
+../atmel_start.h:
+../driver_init.h:
+../atmel_start_pins.h:
+../hal/include/hal_gpio.h:
+../hal/include/hpl_gpio.h:
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
+../hpl/port/hpl_gpio_base.h:
+../hal/utils/include/utils_assert.h:
+../config/hpl_port_config.h:
+../hal/include/hal_delay.h:
+../hal/include/hpl_irq.h:
+../hal/include/hpl_reset.h:
+../hal/include/hpl_sleep.h:
+../hal/include/hal_init.h:
+../hal/include/hpl_init.h:
+../hal/include/hal_io.h:
+../hal/include/hal_sleep.h:
+../hal/include/hal_calendar.h:
+../hal/include/hpl_calendar.h:
+../hal/utils/include/utils_list.h:
+../hal/include/hpl_irq.h:
+../hal/include/hal_usart_sync.h:
+../hal/include/hal_io.h:
+../hal/include/hpl_usart_sync.h:
+../hal/include/hpl_usart.h:
+../hal/include/hal_spi_m_sync.h:
+../hal/include/hpl_spi_m_sync.h:
+../hal/include/hpl_spi.h:
+../hal/utils/include/utils.h:
+../hal/include/hpl_spi_sync.h:
+../hal/include/hal_mci_sync.h:
+../hal/include/hpl_mci_sync.h:
+../sd_mmc_start.h:
+/usr/arm-none-eabi/include/stdio.h:
+/usr/arm-none-eabi/include/_ansi.h:
+/usr/arm-none-eabi/include/newlib.h:
+/usr/arm-none-eabi/include/sys/config.h:
+/usr/arm-none-eabi/include/machine/ieeefp.h:
+/usr/arm-none-eabi/include/sys/cdefs.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdarg.h:
+/usr/arm-none-eabi/include/sys/reent.h:
+/usr/arm-none-eabi/include/_ansi.h:
+/usr/arm-none-eabi/include/sys/_types.h:
+/usr/arm-none-eabi/include/machine/_types.h:
+/usr/arm-none-eabi/include/sys/lock.h:
+/usr/arm-none-eabi/include/sys/types.h:
+/usr/arm-none-eabi/include/machine/endian.h:
+/usr/arm-none-eabi/include/machine/_endian.h:
+/usr/arm-none-eabi/include/sys/select.h:
+/usr/arm-none-eabi/include/sys/_sigset.h:
+/usr/arm-none-eabi/include/sys/_timeval.h:
+/usr/arm-none-eabi/include/sys/timespec.h:
+/usr/arm-none-eabi/include/sys/_timespec.h:
+/usr/arm-none-eabi/include/sys/_pthreadtypes.h:
+/usr/arm-none-eabi/include/sys/sched.h:
+/usr/arm-none-eabi/include/machine/types.h:
+/usr/arm-none-eabi/include/sys/stdio.h:
diff --git a/build/diskio_start.o b/build/diskio_start.o
new file mode 100644
index 0000000..ab4b213
Binary files /dev/null and b/build/diskio_start.o differ
diff --git a/build/driver_init.d b/build/driver_init.d
new file mode 100644
index 0000000..8572763
--- /dev/null
+++ b/build/driver_init.d
@@ -0,0 +1,285 @@
+driver_init.d driver_init.o: ../driver_init.c ../driver_init.h \
+ ../atmel_start_pins.h ../hal/include/hal_gpio.h \
+ ../hal/include/hpl_gpio.h ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h ../hpl/port/hpl_gpio_base.h \
+ ../hal/utils/include/utils_assert.h ../config/hpl_port_config.h \
+ ../hal/include/hal_delay.h ../hal/include/hpl_irq.h \
+ ../hal/include/hpl_reset.h ../hal/include/hpl_sleep.h \
+ ../hal/include/hal_init.h ../hal/include/hpl_init.h \
+ ../hal/include/hal_io.h ../hal/include/hal_sleep.h \
+ ../hal/include/hal_calendar.h ../hal/include/hpl_calendar.h \
+ ../hal/utils/include/utils_list.h ../hal/include/hpl_irq.h \
+ ../hal/include/hal_usart_sync.h ../hal/include/hal_io.h \
+ ../hal/include/hpl_usart_sync.h ../hal/include/hpl_usart.h \
+ ../hal/include/hal_spi_m_sync.h ../hal/include/hpl_spi_m_sync.h \
+ ../hal/include/hpl_spi.h ../hal/utils/include/utils.h \
+ ../hal/include/hpl_spi_sync.h ../hal/include/hal_mci_sync.h \
+ ../hal/include/hpl_mci_sync.h ../config/peripheral_clk_config.h
+../driver_init.h:
+../atmel_start_pins.h:
+../hal/include/hal_gpio.h:
+../hal/include/hpl_gpio.h:
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
+../hpl/port/hpl_gpio_base.h:
+../hal/utils/include/utils_assert.h:
+../config/hpl_port_config.h:
+../hal/include/hal_delay.h:
+../hal/include/hpl_irq.h:
+../hal/include/hpl_reset.h:
+../hal/include/hpl_sleep.h:
+../hal/include/hal_init.h:
+../hal/include/hpl_init.h:
+../hal/include/hal_io.h:
+../hal/include/hal_sleep.h:
+../hal/include/hal_calendar.h:
+../hal/include/hpl_calendar.h:
+../hal/utils/include/utils_list.h:
+../hal/include/hpl_irq.h:
+../hal/include/hal_usart_sync.h:
+../hal/include/hal_io.h:
+../hal/include/hpl_usart_sync.h:
+../hal/include/hpl_usart.h:
+../hal/include/hal_spi_m_sync.h:
+../hal/include/hpl_spi_m_sync.h:
+../hal/include/hpl_spi.h:
+../hal/utils/include/utils.h:
+../hal/include/hpl_spi_sync.h:
+../hal/include/hal_mci_sync.h:
+../hal/include/hpl_mci_sync.h:
+../config/peripheral_clk_config.h:
diff --git a/build/driver_init.o b/build/driver_init.o
new file mode 100644
index 0000000..537ae4d
Binary files /dev/null and b/build/driver_init.o differ
diff --git a/build/examples/driver_examples.d b/build/examples/driver_examples.d
new file mode 100644
index 0000000..abcc584
--- /dev/null
+++ b/build/examples/driver_examples.d
@@ -0,0 +1,286 @@
+examples/driver_examples.d examples/driver_examples.o: \
+ ../examples/driver_examples.c ../examples/driver_examples.h \
+ ../driver_init.h ../atmel_start_pins.h ../hal/include/hal_gpio.h \
+ ../hal/include/hpl_gpio.h ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h ../hpl/port/hpl_gpio_base.h \
+ ../hal/utils/include/utils_assert.h ../config/hpl_port_config.h \
+ ../hal/include/hal_delay.h ../hal/include/hpl_irq.h \
+ ../hal/include/hpl_reset.h ../hal/include/hpl_sleep.h \
+ ../hal/include/hal_init.h ../hal/include/hpl_init.h \
+ ../hal/include/hal_io.h ../hal/include/hal_sleep.h \
+ ../hal/include/hal_calendar.h ../hal/include/hpl_calendar.h \
+ ../hal/utils/include/utils_list.h ../hal/include/hpl_irq.h \
+ ../hal/include/hal_usart_sync.h ../hal/include/hal_io.h \
+ ../hal/include/hpl_usart_sync.h ../hal/include/hpl_usart.h \
+ ../hal/include/hal_spi_m_sync.h ../hal/include/hpl_spi_m_sync.h \
+ ../hal/include/hpl_spi.h ../hal/utils/include/utils.h \
+ ../hal/include/hpl_spi_sync.h ../hal/include/hal_mci_sync.h \
+ ../hal/include/hpl_mci_sync.h
+../examples/driver_examples.h:
+../driver_init.h:
+../atmel_start_pins.h:
+../hal/include/hal_gpio.h:
+../hal/include/hpl_gpio.h:
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
+../hpl/port/hpl_gpio_base.h:
+../hal/utils/include/utils_assert.h:
+../config/hpl_port_config.h:
+../hal/include/hal_delay.h:
+../hal/include/hpl_irq.h:
+../hal/include/hpl_reset.h:
+../hal/include/hpl_sleep.h:
+../hal/include/hal_init.h:
+../hal/include/hpl_init.h:
+../hal/include/hal_io.h:
+../hal/include/hal_sleep.h:
+../hal/include/hal_calendar.h:
+../hal/include/hpl_calendar.h:
+../hal/utils/include/utils_list.h:
+../hal/include/hpl_irq.h:
+../hal/include/hal_usart_sync.h:
+../hal/include/hal_io.h:
+../hal/include/hpl_usart_sync.h:
+../hal/include/hpl_usart.h:
+../hal/include/hal_spi_m_sync.h:
+../hal/include/hpl_spi_m_sync.h:
+../hal/include/hpl_spi.h:
+../hal/utils/include/utils.h:
+../hal/include/hpl_spi_sync.h:
+../hal/include/hal_mci_sync.h:
+../hal/include/hpl_mci_sync.h:
diff --git a/build/examples/driver_examples.o b/build/examples/driver_examples.o
new file mode 100644
index 0000000..b9a8358
Binary files /dev/null and b/build/examples/driver_examples.o differ
diff --git a/build/fatfs/src/ff.d b/build/fatfs/src/ff.d
new file mode 100644
index 0000000..fb73401
--- /dev/null
+++ b/build/fatfs/src/ff.d
@@ -0,0 +1,23 @@
+fatfs/src/ff.d fatfs/src/ff.o: ../fatfs/src/ff.c ../fatfs/src/ff.h \
+ ../fatfs/src/ffconf.h ../fatfs/src/conf_fatfs.h ../fatfs/src/integer.h \
+ ../diskio/diskio.h /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ ../hal/utils/include/err_codes.h
+../fatfs/src/ff.h:
+../fatfs/src/ffconf.h:
+../fatfs/src/conf_fatfs.h:
+../fatfs/src/integer.h:
+../diskio/diskio.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+../hal/utils/include/err_codes.h:
diff --git a/build/fatfs/src/ff.o b/build/fatfs/src/ff.o
new file mode 100644
index 0000000..a6dfb44
Binary files /dev/null and b/build/fatfs/src/ff.o differ
diff --git a/build/fatfs_main.d b/build/fatfs_main.d
new file mode 100644
index 0000000..7a707ad
--- /dev/null
+++ b/build/fatfs_main.d
@@ -0,0 +1,350 @@
+fatfs_main.d fatfs_main.o: ../fatfs_main.c ../fatfs_main.h \
+ ../atmel_start.h ../driver_init.h ../atmel_start_pins.h \
+ ../hal/include/hal_gpio.h ../hal/include/hpl_gpio.h \
+ ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h ../hpl/port/hpl_gpio_base.h \
+ ../hal/utils/include/utils_assert.h ../config/hpl_port_config.h \
+ ../hal/include/hal_delay.h ../hal/include/hpl_irq.h \
+ ../hal/include/hpl_reset.h ../hal/include/hpl_sleep.h \
+ ../hal/include/hal_init.h ../hal/include/hpl_init.h \
+ ../hal/include/hal_io.h ../hal/include/hal_sleep.h \
+ ../hal/include/hal_calendar.h ../hal/include/hpl_calendar.h \
+ ../hal/utils/include/utils_list.h ../hal/include/hpl_irq.h \
+ ../hal/include/hal_usart_sync.h ../hal/include/hal_io.h \
+ ../hal/include/hpl_usart_sync.h ../hal/include/hpl_usart.h \
+ ../hal/include/hal_spi_m_sync.h ../hal/include/hpl_spi_m_sync.h \
+ ../hal/include/hpl_spi.h ../hal/utils/include/utils.h \
+ ../hal/include/hpl_spi_sync.h ../hal/include/hal_mci_sync.h \
+ ../hal/include/hpl_mci_sync.h ../sd_mmc_start.h \
+ /usr/arm-none-eabi/include/stdio.h /usr/arm-none-eabi/include/_ansi.h \
+ /usr/arm-none-eabi/include/newlib.h \
+ /usr/arm-none-eabi/include/sys/config.h \
+ /usr/arm-none-eabi/include/machine/ieeefp.h \
+ /usr/arm-none-eabi/include/sys/cdefs.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdarg.h \
+ /usr/arm-none-eabi/include/sys/reent.h \
+ /usr/arm-none-eabi/include/_ansi.h \
+ /usr/arm-none-eabi/include/sys/_types.h \
+ /usr/arm-none-eabi/include/machine/_types.h \
+ /usr/arm-none-eabi/include/sys/lock.h \
+ /usr/arm-none-eabi/include/sys/types.h \
+ /usr/arm-none-eabi/include/machine/endian.h \
+ /usr/arm-none-eabi/include/machine/_endian.h \
+ /usr/arm-none-eabi/include/sys/select.h \
+ /usr/arm-none-eabi/include/sys/_sigset.h \
+ /usr/arm-none-eabi/include/sys/_timeval.h \
+ /usr/arm-none-eabi/include/sys/timespec.h \
+ /usr/arm-none-eabi/include/sys/_timespec.h \
+ /usr/arm-none-eabi/include/sys/_pthreadtypes.h \
+ /usr/arm-none-eabi/include/sys/sched.h \
+ /usr/arm-none-eabi/include/machine/types.h \
+ /usr/arm-none-eabi/include/sys/stdio.h ../diskio_start.h \
+ ../atmel_start.h /usr/arm-none-eabi/include/string.h \
+ /usr/arm-none-eabi/include/sys/_locale.h \
+ /usr/arm-none-eabi/include/strings.h \
+ /usr/arm-none-eabi/include/sys/string.h ../fatfs/src/ff.h \
+ ../fatfs/src/ffconf.h ../fatfs/src/conf_fatfs.h ../fatfs/src/integer.h
+../fatfs_main.h:
+../atmel_start.h:
+../driver_init.h:
+../atmel_start_pins.h:
+../hal/include/hal_gpio.h:
+../hal/include/hpl_gpio.h:
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
+../hpl/port/hpl_gpio_base.h:
+../hal/utils/include/utils_assert.h:
+../config/hpl_port_config.h:
+../hal/include/hal_delay.h:
+../hal/include/hpl_irq.h:
+../hal/include/hpl_reset.h:
+../hal/include/hpl_sleep.h:
+../hal/include/hal_init.h:
+../hal/include/hpl_init.h:
+../hal/include/hal_io.h:
+../hal/include/hal_sleep.h:
+../hal/include/hal_calendar.h:
+../hal/include/hpl_calendar.h:
+../hal/utils/include/utils_list.h:
+../hal/include/hpl_irq.h:
+../hal/include/hal_usart_sync.h:
+../hal/include/hal_io.h:
+../hal/include/hpl_usart_sync.h:
+../hal/include/hpl_usart.h:
+../hal/include/hal_spi_m_sync.h:
+../hal/include/hpl_spi_m_sync.h:
+../hal/include/hpl_spi.h:
+../hal/utils/include/utils.h:
+../hal/include/hpl_spi_sync.h:
+../hal/include/hal_mci_sync.h:
+../hal/include/hpl_mci_sync.h:
+../sd_mmc_start.h:
+/usr/arm-none-eabi/include/stdio.h:
+/usr/arm-none-eabi/include/_ansi.h:
+/usr/arm-none-eabi/include/newlib.h:
+/usr/arm-none-eabi/include/sys/config.h:
+/usr/arm-none-eabi/include/machine/ieeefp.h:
+/usr/arm-none-eabi/include/sys/cdefs.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdarg.h:
+/usr/arm-none-eabi/include/sys/reent.h:
+/usr/arm-none-eabi/include/_ansi.h:
+/usr/arm-none-eabi/include/sys/_types.h:
+/usr/arm-none-eabi/include/machine/_types.h:
+/usr/arm-none-eabi/include/sys/lock.h:
+/usr/arm-none-eabi/include/sys/types.h:
+/usr/arm-none-eabi/include/machine/endian.h:
+/usr/arm-none-eabi/include/machine/_endian.h:
+/usr/arm-none-eabi/include/sys/select.h:
+/usr/arm-none-eabi/include/sys/_sigset.h:
+/usr/arm-none-eabi/include/sys/_timeval.h:
+/usr/arm-none-eabi/include/sys/timespec.h:
+/usr/arm-none-eabi/include/sys/_timespec.h:
+/usr/arm-none-eabi/include/sys/_pthreadtypes.h:
+/usr/arm-none-eabi/include/sys/sched.h:
+/usr/arm-none-eabi/include/machine/types.h:
+/usr/arm-none-eabi/include/sys/stdio.h:
+../diskio_start.h:
+../atmel_start.h:
+/usr/arm-none-eabi/include/string.h:
+/usr/arm-none-eabi/include/sys/_locale.h:
+/usr/arm-none-eabi/include/strings.h:
+/usr/arm-none-eabi/include/sys/string.h:
+../fatfs/src/ff.h:
+../fatfs/src/ffconf.h:
+../fatfs/src/conf_fatfs.h:
+../fatfs/src/integer.h:
diff --git a/build/fatfs_main.o b/build/fatfs_main.o
new file mode 100644
index 0000000..a2d1532
Binary files /dev/null and b/build/fatfs_main.o differ
diff --git a/build/gdb.txt b/build/gdb.txt
new file mode 100644
index 0000000..b1f4836
--- /dev/null
+++ b/build/gdb.txt
@@ -0,0 +1,651 @@
+Quit
+─── Assembly ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+ 0x00000808  main+0  push    {r3, lr}
+ 0x0000080a  main+2  ldr    r3, [pc, #8]    ; (0x814 <main+12>)
+ 0x0000080c  main+4  blx    r3
+ 0x0000080e  main+6  ldr    r3, [pc, #8]    ; (0x818 <main+16>)
+ 0x00000810  main+8  blx    r3
+ 0x00000812  main+10 b.n    0x812 <main+10>
+ 0x00000814  main+12 lsrs    r5, r4, #30
+ 0x00000816  main+14 movs    r0, r0
+ 0x00000818  main+16 asrs    r5, r4, #32
+ 0x0000081a  main+18 movs    r0, r0
+─── Breakpoints ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── Expressions ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── History ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── Memory ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── Registers ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+     r0 0x00000000      r1 0x0000000a          r2 0x000000f1          r3 0x000005cd           r4 0x1ffffffd         r5 0x00000000
+     r6 0x000002a5      r7 0xa0000000          r8 0xf7e2f6ef          r9 0xffffff7d          r10 0xfff7e7cf        r11 0xbf9faffe
+    r12 0x0000000a      sp 0x20010158          lr 0x0000103d          pc 0x00000812         xpsr 0x61000000      fpscr 0x00000000
+    msp 0x20010158     psp 0xfff7df7c     primask 0x00           basepri 0x00          faultmask 0x00          control 0x00      
+─── Source ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+  2  #include "pdebug.h"
+  3  
+  4  int main(void)
+  5  {
+  6      /* Initializes MCU, drivers and middleware */
+  7      atmel_start_init();
+  8      pdebug_init();
+  9  
+ 10      /* Replace with your application code */
+ 11      while (1) {
+ 12      }
+ 13  }
+~
+~
+~
+~
+~
+~
+~
+~
+─── Stack ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+[0] from 0x00000812 in main+10 at ../main.c:12
+─── Threads ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+[1] id -1 from 0x00000812 in main+10 at ../main.c:12
+─── Variables ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+main () at ../main.c:12
+12		}
+A program is being debugged already.  Kill it? (y or n) [answered Y; input not from terminal]
+─── Assembly ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+ 0x00000552  _oscctrl_init_referenced_generators+34 ldr    r3, [pc, #16]    ; (0x564 <_oscctrl_init_referenced_generators+52>)
+ 0x00000554  _oscctrl_init_referenced_generators+36 ldr    r2, [r3, #64]    ; 0x40
+ 0x00000556  _oscctrl_init_referenced_generators+38 lsls    r1, r2, #31
+ 0x00000558  _oscctrl_init_referenced_generators+40 bmi.n    0x560 <_oscctrl_init_referenced_generators+48>
+ 0x0000055a  _oscctrl_init_referenced_generators+42 ldr    r2, [r3, #64]    ; 0x40
+ 0x0000055c  _oscctrl_init_referenced_generators+44 lsls    r2, r2, #30
+ 0x0000055e  _oscctrl_init_referenced_generators+46 bpl.n    0x554 <_oscctrl_init_referenced_generators+36>
+ 0x00000560  _oscctrl_init_referenced_generators+48 bx    lr
+ 0x00000562  _oscctrl_init_referenced_generators+50 nop
+ 0x00000564  _oscctrl_init_referenced_generators+52 asrs    r0, r0, #32
+─── Breakpoints ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── Expressions ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── History ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── Memory ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── Registers ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+     r0 0x00000000      r1 0x00000000          r2 0x00000000          r3 0x40001000           r4 0x1ffffffd         r5 0x00000000
+     r6 0x000002a5      r7 0xa0000000          r8 0xf7e2f6ef          r9 0xffffff7d          r10 0xfff7e7cf        r11 0xbf9faffe
+    r12 0x0000000a      sp 0x20010140          lr 0x000004cb          pc 0x0000055c         xpsr 0x41000000      fpscr 0x00000000
+    msp 0x20010140     psp 0xfff7df7c     primask 0x00           basepri 0x00          faultmask 0x00          control 0x00      
+─── Source ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+ 914  }
+ 915  
+ 916  static inline bool hri_oscctrl_get_DPLLSTATUS_LOCK_bit(const void *const hw, uint8_t submodule_index)
+ 917  {
+ 918      return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK)
+ 919             >> OSCCTRL_DPLLSTATUS_LOCK_Pos;
+ 920  }
+ 921  
+ 922  static inline bool hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(const void *const hw, uint8_t submodule_index)
+ 923  {
+ 924      return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY)
+ 925             >> OSCCTRL_DPLLSTATUS_CLKRDY_Pos;
+ 926  }
+ 927  
+ 928  static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_get_DPLLSTATUS_reg(const void *const hw, uint8_t submodule_index,
+ 929                                                                            hri_oscctrl_dpllstatus_reg_t mask)
+ 930  {
+ 931      uint32_t tmp;
+ 932      tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg;
+ 933      tmp &= mask;
+─── Stack ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+[0] from 0x0000055c in _oscctrl_init_referenced_generators+44 at ../hri/hri_oscctrl_e54.h:924
+[1] from 0x000004ca in _init_chip+30 at ../hpl/core/hpl_init.c:63
+[2] from 0x00000c16 in init_mcu+4 at ../hal/include/hal_init.h:58
+[3] from 0x00000c16 in system_init+6 at ../driver_init.c:407
+[4] from 0x00000faa in atmel_start_init+6 at ../atmel_start.c:8
+[5] from 0x0000080e in main+6 at ../main.c:7
+─── Threads ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+[1] id 0 from 0x0000055c in _oscctrl_init_referenced_generators+44 at ../hri/hri_oscctrl_e54.h:924
+─── Variables ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+0x0000055c in _oscctrl_init_referenced_generators () at ../hri/hri_oscctrl_e54.h:924
+924		return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY)
+Breakpoint 1 at 0x808: file ../main.c, line 7.
+Loading section .text, size 0x1bc0 lma 0x0
+Loading section .relocate, size 0x6c lma 0x1bc0
+Start address 0x0, load size 7212
+Transfer rate: 53 KB/sec, 801 bytes/write.
+─── Output/messages ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+Note: automatically using hardware breakpoints for read-only addresses.
+─── Assembly ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+~
+~
+~
+~
+~
+!0x00000808  main+0 push    {r3, lr}
+ 0x0000080a  main+2 ldr    r3, [pc, #8]    ; (0x814 <main+12>)
+ 0x0000080c  main+4 blx    r3
+ 0x0000080e  main+6 ldr    r3, [pc, #8]    ; (0x818 <main+16>)
+ 0x00000810  main+8 blx    r3
+─── Breakpoints ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+[1] break at 0x00000808 in ../main.c:7 for main hit 1 time
+─── Expressions ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── History ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── Memory ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── Registers ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+     r0 0x20000070      r1 0x00000000          r2 0x00f00000          r3 0x00000809           r4 0x1ffffffd         r5 0x00000000
+     r6 0x000002a5      r7 0xa0000000          r8 0xf7e2f6ef          r9 0xffffff7d          r10 0xfff7e7cf        r11 0xbf9faffe
+    r12 0x0000000a      sp 0x20010160          lr 0x000007d9          pc 0x00000808         xpsr 0x61000000      fpscr 0x00000000
+    msp 0x20010160     psp 0xfff7df7c     primask 0x00           basepri 0x00          faultmask 0x00          control 0x00      
+─── Source ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+~
+~
+~
+~
+  1  #include <atmel_start.h>
+  2  #include "pdebug.h"
+  3  
+  4  int main(void)
+  5  {
+  6      /* Initializes MCU, drivers and middleware */
+! 7      atmel_start_init();
+  8      pdebug_init();
+  9  
+ 10      /* Replace with your application code */
+ 11      while (1) {
+ 12      }
+ 13  }
+~
+~
+~
+─── Stack ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+[0] from 0x00000808 in main+0 at ../main.c:7
+─── Threads ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+[1] id -1 from 0x00000808 in main+0 at ../main.c:7
+─── Variables ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+
+Breakpoint 1, main () at ../main.c:7
+7		atmel_start_init();
+─── Assembly ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+ 0x00000808  main+0  push    {r3, lr}
+ 0x0000080a  main+2  ldr    r3, [pc, #8]    ; (0x814 <main+12>)
+ 0x0000080c  main+4  blx    r3
+ 0x0000080e  main+6  ldr    r3, [pc, #8]    ; (0x818 <main+16>)
+ 0x00000810  main+8  blx    r3
+ 0x00000812  main+10 b.n    0x812 <main+10>
+ 0x00000814  main+12 lsrs    r5, r4, #30
+ 0x00000816  main+14 movs    r0, r0
+ 0x00000818  main+16 asrs    r5, r4, #32
+ 0x0000081a  main+18 movs    r0, r0
+─── Breakpoints ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── Expressions ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── History ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── Memory ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── Registers ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+     r0 0x00000000      r1 0x0000000a          r2 0x000000f1          r3 0x000005cd           r4 0x1ffffffd         r5 0x00000000
+     r6 0x000002a5      r7 0xa0000000          r8 0xf7e2f6ef          r9 0xffffff7d          r10 0xfff7e7cf        r11 0xbf9faffe
+    r12 0x0000000a      sp 0x20010158          lr 0x0000103d          pc 0x00000812         xpsr 0x61000000      fpscr 0x00000000
+    msp 0x20010158     psp 0xfff7df7c     primask 0x00           basepri 0x00          faultmask 0x00          control 0x00      
+─── Source ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+  2  #include "pdebug.h"
+  3  
+  4  int main(void)
+  5  {
+  6      /* Initializes MCU, drivers and middleware */
+  7      atmel_start_init();
+  8      pdebug_init();
+  9  
+ 10      /* Replace with your application code */
+ 11      while (1) {
+ 12      }
+ 13  }
+~
+~
+~
+~
+~
+~
+~
+~
+─── Stack ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+[0] from 0x00000812 in main+10 at ../main.c:12
+─── Threads ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+[1] id -1 from 0x00000812 in main+10 at ../main.c:12
+─── Variables ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+main () at ../main.c:12
+12		}
+A program is being debugged already.  Kill it? (y or n) [answered Y; input not from terminal]
+─── Assembly ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+~
+~
+~
+~
+ 0x00000552  hri_oscctrl_get_DPLLSTATUS_LOCK_bit+0 ldr    r3, [pc, #16]    ; (0x564 <_oscctrl_init_referenced_generators+52>)
+ 0x00000554  hri_oscctrl_get_DPLLSTATUS_LOCK_bit+2 ldr    r2, [r3, #64]    ; 0x40
+~
+~
+~
+~
+─── Breakpoints ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── Expressions ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── History ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── Memory ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── Registers ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+     r0 0x00000000      r1 0x00000000          r2 0x00000000          r3 0x40001000           r4 0x1ffffffd         r5 0x00000000
+     r6 0x000002a5      r7 0xa0000000          r8 0xf7e2f6ef          r9 0xffffff7d          r10 0xfff7e7cf        r11 0xbf9faffe
+    r12 0x0000000a      sp 0x20010140          lr 0x000004cb          pc 0x00000554         xpsr 0x41000000      fpscr 0x00000000
+    msp 0x20010140     psp 0xfff7df7c     primask 0x00           basepri 0x00          faultmask 0x00          control 0x00      
+─── Source ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+ 908  }
+ 909  
+ 910  static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrl_read_DPLLSYNCBUSY_reg(const void *const hw,
+ 911                                                                                 uint8_t           submodule_index)
+ 912  {
+ 913      return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg;
+ 914  }
+ 915  
+ 916  static inline bool hri_oscctrl_get_DPLLSTATUS_LOCK_bit(const void *const hw, uint8_t submodule_index)
+ 917  {
+ 918      return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK)
+ 919             >> OSCCTRL_DPLLSTATUS_LOCK_Pos;
+ 920  }
+ 921  
+ 922  static inline bool hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(const void *const hw, uint8_t submodule_index)
+ 923  {
+ 924      return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY)
+ 925             >> OSCCTRL_DPLLSTATUS_CLKRDY_Pos;
+ 926  }
+ 927  
+─── Stack ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+[0] from 0x00000554 in hri_oscctrl_get_DPLLSTATUS_LOCK_bit+2 at ../hri/hri_oscctrl_e54.h:918
+[1] from 0x00000554 in _oscctrl_init_referenced_generators+36 at ../hpl/oscctrl/hpl_oscctrl.c:204
+[2] from 0x000004ca in _init_chip+30 at ../hpl/core/hpl_init.c:63
+[3] from 0x00000c16 in init_mcu+4 at ../hal/include/hal_init.h:58
+[4] from 0x00000c16 in system_init+6 at ../driver_init.c:407
+[5] from 0x00000faa in atmel_start_init+6 at ../atmel_start.c:8
+[6] from 0x0000080e in main+6 at ../main.c:7
+─── Threads ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+[1] id 0 from 0x00000554 in hri_oscctrl_get_DPLLSTATUS_LOCK_bit+2 at ../hri/hri_oscctrl_e54.h:918
+─── Variables ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+arg submodule_index = 0 '\000', hw = 0x40001000
+─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+hri_oscctrl_get_DPLLSTATUS_LOCK_bit (submodule_index=0 '\000', hw=0x40001000) at ../hri/hri_oscctrl_e54.h:918
+918		return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK)
+Breakpoint 1 at 0x808: file ../main.c, line 7.
+Loading section .text, size 0x1bc0 lma 0x0
+Loading section .relocate, size 0x6c lma 0x1bc0
+Start address 0x0, load size 7212
+Transfer rate: 54 KB/sec, 801 bytes/write.
+─── Output/messages ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+Note: automatically using hardware breakpoints for read-only addresses.
+─── Assembly ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+~
+~
+~
+~
+~
+!0x00000808  main+0 push    {r3, lr}
+ 0x0000080a  main+2 ldr    r3, [pc, #8]    ; (0x814 <main+12>)
+ 0x0000080c  main+4 blx    r3
+ 0x0000080e  main+6 ldr    r3, [pc, #8]    ; (0x818 <main+16>)
+ 0x00000810  main+8 blx    r3
+─── Breakpoints ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+[1] break at 0x00000808 in ../main.c:7 for main hit 1 time
+─── Expressions ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── History ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── Memory ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── Registers ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+     r0 0x20000070      r1 0x00000000          r2 0x00f00000          r3 0x00000809           r4 0x1ffffffd         r5 0x00000000
+     r6 0x000002a5      r7 0xa0000000          r8 0xf7e2f6ef          r9 0xffffff7d          r10 0xfff7e7cf        r11 0xbf9faffe
+    r12 0x0000000a      sp 0x20010160          lr 0x000007d9          pc 0x00000808         xpsr 0x61000000      fpscr 0x00000000
+    msp 0x20010160     psp 0xfff7df7c     primask 0x00           basepri 0x00          faultmask 0x00          control 0x00      
+─── Source ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+~
+~
+~
+~
+  1  #include <atmel_start.h>
+  2  #include "pdebug.h"
+  3  
+  4  int main(void)
+  5  {
+  6      /* Initializes MCU, drivers and middleware */
+! 7      atmel_start_init();
+  8      pdebug_init();
+  9  
+ 10      /* Replace with your application code */
+ 11      while (1) {
+ 12      }
+ 13  }
+~
+~
+~
+─── Stack ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+[0] from 0x00000808 in main+0 at ../main.c:7
+─── Threads ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+[1] id -1 from 0x00000808 in main+0 at ../main.c:7
+─── Variables ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+
+Breakpoint 1, main () at ../main.c:7
+7		atmel_start_init();
+─── Assembly ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+ 0x00000808  main+0  push    {r3, lr}
+ 0x0000080a  main+2  ldr    r3, [pc, #8]    ; (0x814 <main+12>)
+ 0x0000080c  main+4  blx    r3
+ 0x0000080e  main+6  ldr    r3, [pc, #8]    ; (0x818 <main+16>)
+ 0x00000810  main+8  blx    r3
+ 0x00000812  main+10 b.n    0x812 <main+10>
+ 0x00000814  main+12 lsrs    r5, r4, #30
+ 0x00000816  main+14 movs    r0, r0
+ 0x00000818  main+16 asrs    r5, r4, #32
+ 0x0000081a  main+18 movs    r0, r0
+─── Breakpoints ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── Expressions ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── History ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── Memory ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── Registers ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+     r0 0x00000000      r1 0x0000000a          r2 0x000000f1          r3 0x000005cd           r4 0x1ffffffd         r5 0x00000000
+     r6 0x000002a5      r7 0xa0000000          r8 0xf7e2f6ef          r9 0xffffff7d          r10 0xfff7e7cf        r11 0xbf9faffe
+    r12 0x0000000a      sp 0x20010158          lr 0x0000103d          pc 0x00000812         xpsr 0x61000000      fpscr 0x00000000
+    msp 0x20010158     psp 0xfff7df7c     primask 0x00           basepri 0x00          faultmask 0x00          control 0x00      
+─── Source ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+~
+~
+  1  #include <atmel_start.h>
+  2  #include "pdebug.h"
+  3  
+  4  int main(void)
+  5  {
+  6      /* Initializes MCU, drivers and middleware */
+  7      atmel_start_init();
+  8      pdebug_init();
+  9      printf("Hello world\n");
+ 10  
+ 11      /* Replace with your application code */
+ 12      while (1) {
+ 13      }
+ 14  }
+~
+~
+~
+~
+─── Stack ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+[0] from 0x00000812 in main+10 at ../main.c:9
+─── Threads ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+[1] id -1 from 0x00000812 in main+10 at ../main.c:9
+─── Variables ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+main () at ../main.c:9
+9		printf("Hello world\n");
+A program is being debugged already.  Kill it? (y or n) [answered Y; input not from terminal]
+─── Assembly ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+ 0x00000552  _oscctrl_init_referenced_generators+34 ldr    r3, [pc, #16]    ; (0x564 <_oscctrl_init_referenced_generators+52>)
+ 0x00000554  _oscctrl_init_referenced_generators+36 ldr    r2, [r3, #64]    ; 0x40
+ 0x00000556  _oscctrl_init_referenced_generators+38 lsls    r1, r2, #31
+ 0x00000558  _oscctrl_init_referenced_generators+40 bmi.n    0x560 <_oscctrl_init_referenced_generators+48>
+ 0x0000055a  _oscctrl_init_referenced_generators+42 ldr    r2, [r3, #64]    ; 0x40
+ 0x0000055c  _oscctrl_init_referenced_generators+44 lsls    r2, r2, #30
+ 0x0000055e  _oscctrl_init_referenced_generators+46 bpl.n    0x554 <_oscctrl_init_referenced_generators+36>
+ 0x00000560  _oscctrl_init_referenced_generators+48 bx    lr
+ 0x00000562  _oscctrl_init_referenced_generators+50 nop
+ 0x00000564  _oscctrl_init_referenced_generators+52 asrs    r0, r0, #32
+─── Breakpoints ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── Expressions ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── History ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── Memory ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── Registers ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+     r0 0x00000000      r1 0x00000000          r2 0x00000000          r3 0x40001000           r4 0x1ffffffd         r5 0x00000000
+     r6 0x000002a5      r7 0xa0000000          r8 0xf7e2f6ef          r9 0xffffff7d          r10 0xfff7e7cf        r11 0xbf9faffe
+    r12 0x0000000a      sp 0x20010140          lr 0x000004cb          pc 0x0000055c         xpsr 0x41000000      fpscr 0x00000000
+    msp 0x20010140     psp 0xfff7df7c     primask 0x00           basepri 0x00          faultmask 0x00          control 0x00      
+─── Source ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+ 914  }
+ 915  
+ 916  static inline bool hri_oscctrl_get_DPLLSTATUS_LOCK_bit(const void *const hw, uint8_t submodule_index)
+ 917  {
+ 918      return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK)
+ 919             >> OSCCTRL_DPLLSTATUS_LOCK_Pos;
+ 920  }
+ 921  
+ 922  static inline bool hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(const void *const hw, uint8_t submodule_index)
+ 923  {
+ 924      return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY)
+ 925             >> OSCCTRL_DPLLSTATUS_CLKRDY_Pos;
+ 926  }
+ 927  
+ 928  static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_get_DPLLSTATUS_reg(const void *const hw, uint8_t submodule_index,
+ 929                                                                            hri_oscctrl_dpllstatus_reg_t mask)
+ 930  {
+ 931      uint32_t tmp;
+ 932      tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg;
+ 933      tmp &= mask;
+─── Stack ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+[0] from 0x0000055c in _oscctrl_init_referenced_generators+44 at ../hri/hri_oscctrl_e54.h:924
+[1] from 0x000004ca in _init_chip+30 at ../hpl/core/hpl_init.c:63
+[2] from 0x00000c16 in delay_driver_init+6 at ../driver_init.c:402
+─── Threads ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+[1] id 0 from 0x0000055c in _oscctrl_init_referenced_generators+44 at ../hri/hri_oscctrl_e54.h:924
+─── Variables ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+0x0000055c in _oscctrl_init_referenced_generators () at ../hri/hri_oscctrl_e54.h:924
+924		return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY)
+Breakpoint 1 at 0x808: file ../main.c, line 7.
+Loading section .text, size 0x1bdc lma 0x0
+Loading section .relocate, size 0x6c lma 0x1bdc
+Start address 0x0, load size 7240
+Transfer rate: 53 KB/sec, 804 bytes/write.
+─── Output/messages ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+Note: automatically using hardware breakpoints for read-only addresses.
+─── Assembly ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+~
+~
+~
+~
+~
+!0x00000808  main+0 push    {r3, lr}
+ 0x0000080a  main+2 ldr    r3, [pc, #16]    ; (0x81c <main+20>)
+ 0x0000080c  main+4 blx    r3
+ 0x0000080e  main+6 ldr    r3, [pc, #16]    ; (0x820 <main+24>)
+ 0x00000810  main+8 blx    r3
+─── Breakpoints ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+[1] break at 0x00000808 in ../main.c:7 for main hit 1 time
+─── Expressions ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── History ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── Memory ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── Registers ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+     r0 0x20000070      r1 0x00000000          r2 0x00f00000          r3 0x00000809           r4 0x1ffffffd         r5 0x00000000
+     r6 0x000002a5      r7 0xa0000000          r8 0xf7e2f6ef          r9 0xffffff7d          r10 0xfff7e7cf        r11 0xbf9faffe
+    r12 0x0000000a      sp 0x20010160          lr 0x000007d9          pc 0x00000808         xpsr 0x61000000      fpscr 0x00000000
+    msp 0x20010160     psp 0xfff7df7c     primask 0x00           basepri 0x00          faultmask 0x00          control 0x00      
+─── Source ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+~
+~
+~
+~
+  1  #include <atmel_start.h>
+  2  #include "pdebug.h"
+  3  
+  4  int main(void)
+  5  {
+  6      /* Initializes MCU, drivers and middleware */
+! 7      atmel_start_init();
+  8      pdebug_init();
+  9      printf("Hello world\n");
+ 10  
+ 11      /* Replace with your application code */
+ 12      while (1) {
+ 13      }
+ 14  }
+~
+~
+─── Stack ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+[0] from 0x00000808 in main+0 at ../main.c:7
+─── Threads ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+[1] id -1 from 0x00000808 in main+0 at ../main.c:7
+─── Variables ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+
+Breakpoint 1, main () at ../main.c:7
+7		atmel_start_init();
+─── Assembly ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+~
+~
+~
+~
+ 0x00000816  mmc_spi_op_cond+0  blx    r3
+ 0x00000818  mmc_spi_op_cond+2  b.n    0x818 <sd_mmc_check+248>
+ 0x0000081a  mmc_spi_op_cond+4  nop
+ 0x0000081c  mmc_spi_op_cond+6  lsrs    r5, r6, #30
+ 0x0000081e  mmc_spi_op_cond+8  movs    r0, r0
+ 0x00000820  mmc_spi_op_cond+10 asrs    r5, r6, #32
+─── Breakpoints ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── Expressions ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── History ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── Memory ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── Registers ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+     r0 0x0000000c      r1 0x0000000a          r2 0x000000f1          r3 0x000005cd           r4 0x1ffffffd         r5 0x00000000
+     r6 0x000002a5      r7 0xa0000000          r8 0xf7e2f6ef          r9 0xffffff7d          r10 0xfff7e7cf        r11 0xbf9faffe
+    r12 0x0000000a      sp 0x20010158          lr 0x00000819          pc 0x00000818         xpsr 0x21000000      fpscr 0x00000000
+    msp 0x20010158     psp 0xfff7df7c     primask 0x00           basepri 0x00          faultmask 0x00          control 0x00      
+─── Source ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+ 432   * process, then it sets the SD/MMC card in transfer state.
+ 433   * At last, it will automaticly enable maximum bus width and transfer speed.
+ 434   *
+ 435   * \return true if success, otherwise false
+ 436   */
+ 437  static bool sd_mmc_spi_install_mmc(void)
+ 438  {
+ 439      uint8_t b_authorize_high_speed;
+ 440  
+ 441      // CMD0 - Reset all cards to idle state.
+ 442      if (!driver_send_cmd(sd_mmc_hal, SDMMC_SPI_CMD0_GO_IDLE_STATE, 0)) {
+ 443          return false;
+ 444      }
+ 445  
+ 446      if (!mmc_spi_op_cond()) {
+ 447          return false;
+ 448      }
+ 449  
+ 450      // Disable CRC check for SPI mode
+ 451      if (!driver_send_cmd(sd_mmc_hal, SDMMC_SPI_CMD59_CRC_ON_OFF, 0)) {
+─── Stack ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+[0] from 0x00000818 in mmc_spi_op_cond+2 at ../sd_mmc/sd_mmc.c:442
+[1] from 0x00000818 in sd_mmc_spi_install_mmc+20 at ../sd_mmc/sd_mmc.c:446
+[2] from 0x00000818 in sd_mmc_spi_card_init+220 at ../sd_mmc/sd_mmc.c:379
+[3] from 0x00000818 in sd_mmc_check+248 at ../sd_mmc/sd_mmc.c:1633
+[4] from 0xcf1f4f30
+─── Threads ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+[1] id -1 from 0x00000818 in mmc_spi_op_cond+2 at ../sd_mmc/sd_mmc.c:442
+─── Variables ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+loc retry = <optimized out>, resp = <optimized out>, __func__ = '\377' <repeats 16 times>, b_authorize_high_speed = <optimized out>, v2 = <optimized out>, sd_mmc_err = <optimized out>
+─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+0x00000818 in mmc_spi_op_cond () at ../sd_mmc/sd_mmc.c:442
+442		if (!driver_send_cmd(sd_mmc_hal, SDMMC_SPI_CMD0_GO_IDLE_STATE, 0)) {
+A program is being debugged already.  Kill it? (y or n) [answered Y; input not from terminal]
+─── Assembly ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+ 0x00000550  sd_mmc_select_slot+136 bmi.n    0x54c <sd_mmc_select_slot+132>
+ 0x00000552  sd_mmc_select_slot+138 ldr    r3, [pc, #16]    ; (0x564 <sd_mmc_select_slot+156>)
+ 0x00000554  sd_mmc_select_slot+140 ldr    r2, [r3, #64]    ; 0x40
+ 0x00000556  sd_mmc_select_slot+142 lsls    r1, r2, #31
+ 0x00000558  sd_mmc_select_slot+144 bmi.n    0x560 <sd_mmc_select_slot+152>
+ 0x0000055a  sd_mmc_select_slot+146 ldr    r2, [r3, #64]    ; 0x40
+ 0x0000055c  sd_mmc_select_slot+148 lsls    r2, r2, #30
+ 0x0000055e  sd_mmc_select_slot+150 bpl.n    0x554 <sd_mmc_select_slot+140>
+ 0x00000560  sd_mmc_select_slot+152 bx    lr
+ 0x00000562  sd_mmc_select_slot+154 nop
+─── Breakpoints ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── Expressions ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── History ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── Memory ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── Registers ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+     r0 0x00000000      r1 0x00000000          r2 0x00000000          r3 0x40001000           r4 0x1ffffffd         r5 0x00000000
+     r6 0x000002a5      r7 0xa0000000          r8 0xf7e2f6ef          r9 0xffffff7d          r10 0xfff7e7cf        r11 0xbf9faffe
+    r12 0x0000000a      sp 0x20010140          lr 0x000004cb          pc 0x0000055a         xpsr 0x41000000      fpscr 0x00000000
+    msp 0x20010140     psp 0xfff7df7c     primask 0x00           basepri 0x00          faultmask 0x00          control 0x00      
+─── Source ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+ 1303              /* Set 1-bit bus width and low clock for initialization */
+ 1304              sd_mmc_cards[slot].clock      = SDMMC_CLOCK_INIT;
+ 1305              sd_mmc_cards[slot].bus_width  = 1;
+ 1306              sd_mmc_cards[slot].high_speed = 0;
+ 1307          }
+ 1308          if (sd_mmc_cards[slot].state == SD_MMC_CARD_STATE_UNUSABLE) {
+ 1309              return SD_MMC_ERR_UNUSABLE;
+ 1310          }
+ 1311      } else {
+ 1312          /* No pin card detection, then always try to install it */
+ 1313          if ((sd_mmc_cards[slot].state == SD_MMC_CARD_STATE_NO_CARD)
+ 1314              || (sd_mmc_cards[slot].state == SD_MMC_CARD_STATE_UNUSABLE)) {
+ 1315              /* Card is not initialized */
+ 1316              sd_mmc_cards[slot].state = SD_MMC_CARD_STATE_INIT;
+ 1317              /* Set 1-bit bus width and low clock for initialization */
+ 1318              sd_mmc_cards[slot].clock      = SDMMC_CLOCK_INIT;
+ 1319              sd_mmc_cards[slot].bus_width  = 1;
+ 1320              sd_mmc_cards[slot].high_speed = 0;
+ 1321          }
+ 1322      }
+─── Stack ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+[0] from 0x0000055a in sd_mmc_select_slot+146 at ../sd_mmc/sd_mmc.c:1313
+[1] from 0x00000fba in spi_m_sync_start_read_block+46 at ../sd_mmc/sd_mmc_spi.c:179
+[2] from 0x2b3af61e
+─── Threads ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+[1] id 0 from 0x0000055a in sd_mmc_select_slot+146 at ../sd_mmc/sd_mmc.c:1313
+─── Variables ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+arg slot = <optimized out>
+─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+0x0000055a in sd_mmc_select_slot (slot=<optimized out>) at ../sd_mmc/sd_mmc.c:1313
+1313			if ((sd_mmc_cards[slot].state == SD_MMC_CARD_STATE_NO_CARD)
+Breakpoint 1 at 0x18e4: file ../main.c, line 8.
+Loading section .text, size 0x31c0 lma 0x0
+Loading section .relocate, size 0x6c lma 0x31c0
+Start address 0x0, load size 12844
+Transfer rate: 52 KB/sec, 856 bytes/write.
+─── Output/messages ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+Note: automatically using hardware breakpoints for read-only addresses.
+─── Assembly ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+~
+~
+~
+~
+~
+!0x000018e4  main+0 push    {r3, lr}
+ 0x000018e6  main+2 ldr    r3, [pc, #20]    ; (0x18fc <main+24>)
+ 0x000018e8  main+4 blx    r3
+ 0x000018ea  main+6 ldr    r3, [pc, #20]    ; (0x1900 <main+28>)
+ 0x000018ec  main+8 blx    r3
+─── Breakpoints ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+[1] break at 0x000018e4 in ../main.c:8 for main hit 1 time
+─── Expressions ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── History ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── Memory ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─── Registers ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+     r0 0x20000070      r1 0x00000000          r2 0x00f00000          r3 0x000018e5           r4 0x1ffffffd         r5 0x00000000
+     r6 0x000002a5      r7 0xa0000000          r8 0xf7e2f6ef          r9 0xffffff7d          r10 0xfff7e7cf        r11 0xbf9faffe
+    r12 0x0000000a      sp 0x20010368          lr 0x000018b5          pc 0x000018e4         xpsr 0x61000000      fpscr 0x00000000
+    msp 0x20010368     psp 0xfff7df7c     primask 0x00           basepri 0x00          faultmask 0x00          control 0x00      
+─── Source ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+~
+~
+~
+  1  #include <atmel_start.h>
+  2  #include "pdebug.h"
+  3  #include "sd_mmc_start.h"
+  4  
+  5  int main(void)
+  6  {
+  7      /* Initializes MCU, drivers and middleware */
+! 8      atmel_start_init();
+  9      pdebug_init();
+ 10      printf("Hello world\n");
+ 11  
+ 12      SDMMC_example();
+ 13      /* Replace with your application code */
+ 14      while (1) {
+ 15      }
+ 16  }
+~
+─── Stack ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+[0] from 0x000018e4 in main+0 at ../main.c:8
+─── Threads ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+[1] id -1 from 0x000018e4 in main+0 at ../main.c:8
+─── Variables ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
+
+Breakpoint 1, main () at ../main.c:8
+8		atmel_start_init();
diff --git a/build/hal/src/hal_atomic.d b/build/hal/src/hal_atomic.d
new file mode 100644
index 0000000..40e1db2
--- /dev/null
+++ b/build/hal/src/hal_atomic.d
@@ -0,0 +1,239 @@
+hal/src/hal_atomic.d hal/src/hal_atomic.o: ../hal/src/hal_atomic.c \
+ ../hal/include/hal_atomic.h ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hri/hri_adc_e54.h ../hri/hri_aes_e54.h \
+ ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h ../hri/hri_cmcc_e54.h \
+ ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h ../hri/hri_dsu_e54.h \
+ ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h ../hri/hri_freqm_e54.h \
+ ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h ../hri/hri_hmatrixb_e54.h \
+ ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h ../hri/hri_mclk_e54.h \
+ ../hri/hri_nvmctrl_e54.h ../hri/hri_osc32kctrl_e54.h \
+ ../hri/hri_oscctrl_e54.h ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h \
+ ../hri/hri_pdec_e54.h ../hri/hri_pm_e54.h ../hri/hri_port_e54.h \
+ ../hri/hri_qspi_e54.h ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h \
+ ../hri/hri_rtc_e54.h ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h \
+ ../hri/hri_supc_e54.h ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h \
+ ../hri/hri_trng_e54.h ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h
+../hal/include/hal_atomic.h:
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
diff --git a/build/hal/src/hal_atomic.o b/build/hal/src/hal_atomic.o
new file mode 100644
index 0000000..c35b450
Binary files /dev/null and b/build/hal/src/hal_atomic.o differ
diff --git a/build/hal/src/hal_cache.d b/build/hal/src/hal_cache.d
new file mode 100644
index 0000000..24d2667
--- /dev/null
+++ b/build/hal/src/hal_cache.d
@@ -0,0 +1,241 @@
+hal/src/hal_cache.d hal/src/hal_cache.o: ../hal/src/hal_cache.c \
+ ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h ../hal/include/hpl_cmcc.h
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
+../hal/include/hpl_cmcc.h:
diff --git a/build/hal/src/hal_cache.o b/build/hal/src/hal_cache.o
new file mode 100644
index 0000000..08970d7
Binary files /dev/null and b/build/hal/src/hal_cache.o differ
diff --git a/build/hal/src/hal_calendar.d b/build/hal/src/hal_calendar.d
new file mode 100644
index 0000000..02d8967
--- /dev/null
+++ b/build/hal/src/hal_calendar.d
@@ -0,0 +1,249 @@
+hal/src/hal_calendar.d hal/src/hal_calendar.o: ../hal/src/hal_calendar.c \
+ ../hal/include/hal_calendar.h ../hal/include/hpl_calendar.h \
+ ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h ../hal/utils/include/utils_list.h \
+ ../hal/include/hpl_irq.h ../hal/utils/include/utils.h \
+ ../hal/utils/include/utils_assert.h
+../hal/include/hal_calendar.h:
+../hal/include/hpl_calendar.h:
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
+../hal/utils/include/utils_list.h:
+../hal/include/hpl_irq.h:
+../hal/utils/include/utils.h:
+../hal/utils/include/utils_assert.h:
diff --git a/build/hal/src/hal_calendar.o b/build/hal/src/hal_calendar.o
new file mode 100644
index 0000000..58e92c8
Binary files /dev/null and b/build/hal/src/hal_calendar.o differ
diff --git a/build/hal/src/hal_delay.d b/build/hal/src/hal_delay.d
new file mode 100644
index 0000000..83c1dfd
--- /dev/null
+++ b/build/hal/src/hal_delay.d
@@ -0,0 +1,247 @@
+hal/src/hal_delay.d hal/src/hal_delay.o: ../hal/src/hal_delay.c \
+ ../hal/include/hpl_irq.h ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h ../hal/include/hpl_reset.h \
+ ../hal/include/hpl_sleep.h ../hal/include/hal_delay.h \
+ ../hal/include/hpl_delay.h
+../hal/include/hpl_irq.h:
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
+../hal/include/hpl_reset.h:
+../hal/include/hpl_sleep.h:
+../hal/include/hal_delay.h:
+../hal/include/hpl_delay.h:
diff --git a/build/hal/src/hal_delay.o b/build/hal/src/hal_delay.o
new file mode 100644
index 0000000..58dca25
Binary files /dev/null and b/build/hal/src/hal_delay.o differ
diff --git a/build/hal/src/hal_gpio.d b/build/hal/src/hal_gpio.d
new file mode 100644
index 0000000..be16d91
--- /dev/null
+++ b/build/hal/src/hal_gpio.d
@@ -0,0 +1,247 @@
+hal/src/hal_gpio.d hal/src/hal_gpio.o: ../hal/src/hal_gpio.c \
+ ../hal/include/hal_gpio.h ../hal/include/hpl_gpio.h \
+ ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h ../hpl/port/hpl_gpio_base.h \
+ ../hal/utils/include/utils_assert.h ../config/hpl_port_config.h
+../hal/include/hal_gpio.h:
+../hal/include/hpl_gpio.h:
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
+../hpl/port/hpl_gpio_base.h:
+../hal/utils/include/utils_assert.h:
+../config/hpl_port_config.h:
diff --git a/build/hal/src/hal_gpio.o b/build/hal/src/hal_gpio.o
new file mode 100644
index 0000000..ae1b24f
Binary files /dev/null and b/build/hal/src/hal_gpio.o differ
diff --git a/build/hal/src/hal_init.d b/build/hal/src/hal_init.d
new file mode 100644
index 0000000..44fa00c
--- /dev/null
+++ b/build/hal/src/hal_init.d
@@ -0,0 +1,243 @@
+hal/src/hal_init.d hal/src/hal_init.o: ../hal/src/hal_init.c \
+ ../hal/include/hal_init.h ../hal/include/hpl_init.h \
+ ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h
+../hal/include/hal_init.h:
+../hal/include/hpl_init.h:
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
diff --git a/build/hal/src/hal_init.o b/build/hal/src/hal_init.o
new file mode 100644
index 0000000..4a8e888
Binary files /dev/null and b/build/hal/src/hal_init.o differ
diff --git a/build/hal/src/hal_io.d b/build/hal/src/hal_io.d
new file mode 100644
index 0000000..24b3309
--- /dev/null
+++ b/build/hal/src/hal_io.d
@@ -0,0 +1,242 @@
+hal/src/hal_io.d hal/src/hal_io.o: ../hal/src/hal_io.c \
+ ../hal/include/hal_io.h ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h ../hal/utils/include/utils_assert.h
+../hal/include/hal_io.h:
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
+../hal/utils/include/utils_assert.h:
diff --git a/build/hal/src/hal_io.o b/build/hal/src/hal_io.o
new file mode 100644
index 0000000..f2f45bc
Binary files /dev/null and b/build/hal/src/hal_io.o differ
diff --git a/build/hal/src/hal_mci_sync.d b/build/hal/src/hal_mci_sync.d
new file mode 100644
index 0000000..19468a1
--- /dev/null
+++ b/build/hal/src/hal_mci_sync.d
@@ -0,0 +1,246 @@
+hal/src/hal_mci_sync.d hal/src/hal_mci_sync.o: ../hal/src/hal_mci_sync.c \
+ ../hal/include/hal_mci_sync.h ../hal/include/hpl_mci_sync.h \
+ ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h ../hal/utils/include/utils.h \
+ ../hal/utils/include/utils_assert.h
+../hal/include/hal_mci_sync.h:
+../hal/include/hpl_mci_sync.h:
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
+../hal/utils/include/utils.h:
+../hal/utils/include/utils_assert.h:
diff --git a/build/hal/src/hal_mci_sync.o b/build/hal/src/hal_mci_sync.o
new file mode 100644
index 0000000..9361665
Binary files /dev/null and b/build/hal/src/hal_mci_sync.o differ
diff --git a/build/hal/src/hal_sleep.d b/build/hal/src/hal_sleep.d
new file mode 100644
index 0000000..0271943
--- /dev/null
+++ b/build/hal/src/hal_sleep.d
@@ -0,0 +1,243 @@
+hal/src/hal_sleep.d hal/src/hal_sleep.o: ../hal/src/hal_sleep.c \
+ ../hal/include/hal_sleep.h ../hal/include/hpl_sleep.h \
+ ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h
+../hal/include/hal_sleep.h:
+../hal/include/hpl_sleep.h:
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
diff --git a/build/hal/src/hal_sleep.o b/build/hal/src/hal_sleep.o
new file mode 100644
index 0000000..128e9ca
Binary files /dev/null and b/build/hal/src/hal_sleep.o differ
diff --git a/build/hal/src/hal_spi_m_sync.d b/build/hal/src/hal_spi_m_sync.d
new file mode 100644
index 0000000..121f5b4
--- /dev/null
+++ b/build/hal/src/hal_spi_m_sync.d
@@ -0,0 +1,250 @@
+hal/src/hal_spi_m_sync.d hal/src/hal_spi_m_sync.o: \
+ ../hal/src/hal_spi_m_sync.c ../hal/include/hal_spi_m_sync.h \
+ ../hal/include/hal_io.h ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h ../hal/include/hpl_spi_m_sync.h \
+ ../hal/include/hpl_spi.h ../hal/utils/include/utils.h \
+ ../hal/include/hpl_spi_sync.h ../hal/utils/include/utils_assert.h
+../hal/include/hal_spi_m_sync.h:
+../hal/include/hal_io.h:
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
+../hal/include/hpl_spi_m_sync.h:
+../hal/include/hpl_spi.h:
+../hal/utils/include/utils.h:
+../hal/include/hpl_spi_sync.h:
+../hal/utils/include/utils_assert.h:
diff --git a/build/hal/src/hal_spi_m_sync.o b/build/hal/src/hal_spi_m_sync.o
new file mode 100644
index 0000000..8590afd
Binary files /dev/null and b/build/hal/src/hal_spi_m_sync.o differ
diff --git a/build/hal/src/hal_usart_sync.d b/build/hal/src/hal_usart_sync.d
new file mode 100644
index 0000000..2863ede
--- /dev/null
+++ b/build/hal/src/hal_usart_sync.d
@@ -0,0 +1,249 @@
+hal/src/hal_usart_sync.d hal/src/hal_usart_sync.o: \
+ ../hal/src/hal_usart_sync.c ../hal/include/hal_usart_sync.h \
+ ../hal/include/hal_io.h ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h ../hal/include/hpl_usart_sync.h \
+ ../hal/include/hpl_usart.h ../hal/utils/include/utils_assert.h \
+ ../hal/utils/include/utils.h
+../hal/include/hal_usart_sync.h:
+../hal/include/hal_io.h:
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
+../hal/include/hpl_usart_sync.h:
+../hal/include/hpl_usart.h:
+../hal/utils/include/utils_assert.h:
+../hal/utils/include/utils.h:
diff --git a/build/hal/src/hal_usart_sync.o b/build/hal/src/hal_usart_sync.o
new file mode 100644
index 0000000..0bfdbbc
Binary files /dev/null and b/build/hal/src/hal_usart_sync.o differ
diff --git a/build/hal/utils/src/utils_assert.d b/build/hal/utils/src/utils_assert.d
new file mode 100644
index 0000000..a40c04b
--- /dev/null
+++ b/build/hal/utils/src/utils_assert.d
@@ -0,0 +1,242 @@
+hal/utils/src/utils_assert.d hal/utils/src/utils_assert.o: \
+ ../hal/utils/src/utils_assert.c ../hal/utils/include/utils_assert.h \
+ ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h
+../hal/utils/include/utils_assert.h:
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
diff --git a/build/hal/utils/src/utils_assert.o b/build/hal/utils/src/utils_assert.o
new file mode 100644
index 0000000..96945a2
Binary files /dev/null and b/build/hal/utils/src/utils_assert.o differ
diff --git a/build/hal/utils/src/utils_event.d b/build/hal/utils/src/utils_event.d
new file mode 100644
index 0000000..e6f6766
--- /dev/null
+++ b/build/hal/utils/src/utils_event.d
@@ -0,0 +1,274 @@
+hal/utils/src/utils_event.d hal/utils/src/utils_event.o: \
+ ../hal/utils/src/utils_event.c ../hal/utils/include/utils_event.h \
+ ../hal/utils/include/utils.h ../hal/utils/include/utils_list.h \
+ ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h ../hal/utils/include/events.h \
+ ../hal/utils/include/utils_assert.h /usr/arm-none-eabi/include/string.h \
+ /usr/arm-none-eabi/include/_ansi.h /usr/arm-none-eabi/include/newlib.h \
+ /usr/arm-none-eabi/include/sys/config.h \
+ /usr/arm-none-eabi/include/machine/ieeefp.h \
+ /usr/arm-none-eabi/include/sys/reent.h \
+ /usr/arm-none-eabi/include/_ansi.h \
+ /usr/arm-none-eabi/include/sys/_types.h \
+ /usr/arm-none-eabi/include/machine/_types.h \
+ /usr/arm-none-eabi/include/sys/lock.h \
+ /usr/arm-none-eabi/include/sys/cdefs.h \
+ /usr/arm-none-eabi/include/sys/_locale.h \
+ /usr/arm-none-eabi/include/strings.h \
+ /usr/arm-none-eabi/include/sys/string.h
+../hal/utils/include/utils_event.h:
+../hal/utils/include/utils.h:
+../hal/utils/include/utils_list.h:
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
+../hal/utils/include/events.h:
+../hal/utils/include/utils_assert.h:
+/usr/arm-none-eabi/include/string.h:
+/usr/arm-none-eabi/include/_ansi.h:
+/usr/arm-none-eabi/include/newlib.h:
+/usr/arm-none-eabi/include/sys/config.h:
+/usr/arm-none-eabi/include/machine/ieeefp.h:
+/usr/arm-none-eabi/include/sys/reent.h:
+/usr/arm-none-eabi/include/_ansi.h:
+/usr/arm-none-eabi/include/sys/_types.h:
+/usr/arm-none-eabi/include/machine/_types.h:
+/usr/arm-none-eabi/include/sys/lock.h:
+/usr/arm-none-eabi/include/sys/cdefs.h:
+/usr/arm-none-eabi/include/sys/_locale.h:
+/usr/arm-none-eabi/include/strings.h:
+/usr/arm-none-eabi/include/sys/string.h:
diff --git a/build/hal/utils/src/utils_event.o b/build/hal/utils/src/utils_event.o
new file mode 100644
index 0000000..b6babba
Binary files /dev/null and b/build/hal/utils/src/utils_event.o differ
diff --git a/build/hal/utils/src/utils_list.d b/build/hal/utils/src/utils_list.d
new file mode 100644
index 0000000..5558c44
--- /dev/null
+++ b/build/hal/utils/src/utils_list.d
@@ -0,0 +1,243 @@
+hal/utils/src/utils_list.d hal/utils/src/utils_list.o: \
+ ../hal/utils/src/utils_list.c ../hal/utils/include/utils_list.h \
+ ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h ../hal/utils/include/utils_assert.h
+../hal/utils/include/utils_list.h:
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
+../hal/utils/include/utils_assert.h:
diff --git a/build/hal/utils/src/utils_list.o b/build/hal/utils/src/utils_list.o
new file mode 100644
index 0000000..1cb6810
Binary files /dev/null and b/build/hal/utils/src/utils_list.o differ
diff --git a/build/hal/utils/src/utils_syscalls.d b/build/hal/utils/src/utils_syscalls.d
new file mode 100644
index 0000000..3450794
--- /dev/null
+++ b/build/hal/utils/src/utils_syscalls.d
@@ -0,0 +1,65 @@
+hal/utils/src/utils_syscalls.d hal/utils/src/utils_syscalls.o: \
+ ../hal/utils/src/utils_syscalls.c /usr/arm-none-eabi/include/stdio.h \
+ /usr/arm-none-eabi/include/_ansi.h /usr/arm-none-eabi/include/newlib.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/config.h \
+ /usr/arm-none-eabi/include/machine/ieeefp.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/sys/cdefs.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdarg.h \
+ /usr/arm-none-eabi/include/sys/reent.h \
+ /usr/arm-none-eabi/include/_ansi.h \
+ /usr/arm-none-eabi/include/sys/_types.h \
+ /usr/arm-none-eabi/include/machine/_types.h \
+ /usr/arm-none-eabi/include/sys/lock.h \
+ /usr/arm-none-eabi/include/sys/types.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/arm-none-eabi/include/machine/endian.h \
+ /usr/arm-none-eabi/include/machine/_endian.h \
+ /usr/arm-none-eabi/include/sys/select.h \
+ /usr/arm-none-eabi/include/sys/_sigset.h \
+ /usr/arm-none-eabi/include/sys/_timeval.h \
+ /usr/arm-none-eabi/include/sys/timespec.h \
+ /usr/arm-none-eabi/include/sys/_timespec.h \
+ /usr/arm-none-eabi/include/sys/_pthreadtypes.h \
+ /usr/arm-none-eabi/include/sys/sched.h \
+ /usr/arm-none-eabi/include/machine/types.h \
+ /usr/arm-none-eabi/include/sys/stdio.h \
+ /usr/arm-none-eabi/include/sys/stat.h /usr/arm-none-eabi/include/time.h \
+ /usr/arm-none-eabi/include/machine/time.h \
+ /usr/arm-none-eabi/include/sys/_locale.h
+/usr/arm-none-eabi/include/stdio.h:
+/usr/arm-none-eabi/include/_ansi.h:
+/usr/arm-none-eabi/include/newlib.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/config.h:
+/usr/arm-none-eabi/include/machine/ieeefp.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/sys/cdefs.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdarg.h:
+/usr/arm-none-eabi/include/sys/reent.h:
+/usr/arm-none-eabi/include/_ansi.h:
+/usr/arm-none-eabi/include/sys/_types.h:
+/usr/arm-none-eabi/include/machine/_types.h:
+/usr/arm-none-eabi/include/sys/lock.h:
+/usr/arm-none-eabi/include/sys/types.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/arm-none-eabi/include/machine/endian.h:
+/usr/arm-none-eabi/include/machine/_endian.h:
+/usr/arm-none-eabi/include/sys/select.h:
+/usr/arm-none-eabi/include/sys/_sigset.h:
+/usr/arm-none-eabi/include/sys/_timeval.h:
+/usr/arm-none-eabi/include/sys/timespec.h:
+/usr/arm-none-eabi/include/sys/_timespec.h:
+/usr/arm-none-eabi/include/sys/_pthreadtypes.h:
+/usr/arm-none-eabi/include/sys/sched.h:
+/usr/arm-none-eabi/include/machine/types.h:
+/usr/arm-none-eabi/include/sys/stdio.h:
+/usr/arm-none-eabi/include/sys/stat.h:
+/usr/arm-none-eabi/include/time.h:
+/usr/arm-none-eabi/include/machine/time.h:
+/usr/arm-none-eabi/include/sys/_locale.h:
diff --git a/build/hal/utils/src/utils_syscalls.o b/build/hal/utils/src/utils_syscalls.o
new file mode 100644
index 0000000..395c16c
Binary files /dev/null and b/build/hal/utils/src/utils_syscalls.o differ
diff --git a/build/hpl/cmcc/hpl_cmcc.d b/build/hpl/cmcc/hpl_cmcc.d
new file mode 100644
index 0000000..6f38616
--- /dev/null
+++ b/build/hpl/cmcc/hpl_cmcc.d
@@ -0,0 +1,243 @@
+hpl/cmcc/hpl_cmcc.d hpl/cmcc/hpl_cmcc.o: ../hpl/cmcc/hpl_cmcc.c \
+ ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h ../hal/include/hpl_cmcc.h \
+ ../config/hpl_cmcc_config.h
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
+../hal/include/hpl_cmcc.h:
+../config/hpl_cmcc_config.h:
diff --git a/build/hpl/cmcc/hpl_cmcc.o b/build/hpl/cmcc/hpl_cmcc.o
new file mode 100644
index 0000000..0f9f395
Binary files /dev/null and b/build/hpl/cmcc/hpl_cmcc.o differ
diff --git a/build/hpl/core/hpl_core_m4.d b/build/hpl/core/hpl_core_m4.d
new file mode 100644
index 0000000..924c73e
--- /dev/null
+++ b/build/hpl/core/hpl_core_m4.d
@@ -0,0 +1,248 @@
+hpl/core/hpl_core_m4.d hpl/core/hpl_core_m4.o: ../hpl/core/hpl_core_m4.c \
+ ../hal/include/hpl_core.h ../hpl/core/hpl_core_port.h \
+ ../config/peripheral_clk_config.h ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h ../hal/include/hpl_irq.h \
+ ../hal/utils/include/utils.h ../hal/utils/include/utils_assert.h
+../hal/include/hpl_core.h:
+../hpl/core/hpl_core_port.h:
+../config/peripheral_clk_config.h:
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
+../hal/include/hpl_irq.h:
+../hal/utils/include/utils.h:
+../hal/utils/include/utils_assert.h:
diff --git a/build/hpl/core/hpl_core_m4.o b/build/hpl/core/hpl_core_m4.o
new file mode 100644
index 0000000..38338c5
Binary files /dev/null and b/build/hpl/core/hpl_core_m4.o differ
diff --git a/build/hpl/core/hpl_init.d b/build/hpl/core/hpl_init.d
new file mode 100644
index 0000000..c685281
--- /dev/null
+++ b/build/hpl/core/hpl_init.d
@@ -0,0 +1,260 @@
+hpl/core/hpl_init.d hpl/core/hpl_init.o: ../hpl/core/hpl_init.c \
+ ../hal/include/hpl_gpio.h ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h ../hpl/port/hpl_gpio_base.h \
+ ../hal/utils/include/utils_assert.h ../config/hpl_port_config.h \
+ ../hal/include/hpl_init.h ../hpl/gclk/hpl_gclk_base.h \
+ ../config/hpl_mclk_config.h ../config/peripheral_clk_config.h \
+ ../hal/include/hpl_dma.h ../hal/include/hpl_irq.h \
+ ../config/hpl_dmac_config.h ../config/hpl_cmcc_config.h \
+ ../hal/include/hal_cache.h ../hal/include/hpl_cmcc.h
+../hal/include/hpl_gpio.h:
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
+../hpl/port/hpl_gpio_base.h:
+../hal/utils/include/utils_assert.h:
+../config/hpl_port_config.h:
+../hal/include/hpl_init.h:
+../hpl/gclk/hpl_gclk_base.h:
+../config/hpl_mclk_config.h:
+../config/peripheral_clk_config.h:
+../hal/include/hpl_dma.h:
+../hal/include/hpl_irq.h:
+../config/hpl_dmac_config.h:
+../config/hpl_cmcc_config.h:
+../hal/include/hal_cache.h:
+../hal/include/hpl_cmcc.h:
diff --git a/build/hpl/core/hpl_init.o b/build/hpl/core/hpl_init.o
new file mode 100644
index 0000000..8e3f4cb
Binary files /dev/null and b/build/hpl/core/hpl_init.o differ
diff --git a/build/hpl/dmac/hpl_dmac.d b/build/hpl/dmac/hpl_dmac.d
new file mode 100644
index 0000000..dc2d0fb
--- /dev/null
+++ b/build/hpl/dmac/hpl_dmac.d
@@ -0,0 +1,250 @@
+hpl/dmac/hpl_dmac.d hpl/dmac/hpl_dmac.o: ../hpl/dmac/hpl_dmac.c \
+ ../hal/include/hpl_dma.h ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h ../hal/include/hpl_irq.h \
+ ../hal/utils/include/utils_assert.h ../hal/utils/include/utils.h \
+ ../config/hpl_dmac_config.h ../hal/utils/include/utils_repeat_macro.h \
+ ../hal/utils/include/utils_increment_macro.h
+../hal/include/hpl_dma.h:
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
+../hal/include/hpl_irq.h:
+../hal/utils/include/utils_assert.h:
+../hal/utils/include/utils.h:
+../config/hpl_dmac_config.h:
+../hal/utils/include/utils_repeat_macro.h:
+../hal/utils/include/utils_increment_macro.h:
diff --git a/build/hpl/dmac/hpl_dmac.o b/build/hpl/dmac/hpl_dmac.o
new file mode 100644
index 0000000..2f70c79
Binary files /dev/null and b/build/hpl/dmac/hpl_dmac.o differ
diff --git a/build/hpl/gclk/hpl_gclk.d b/build/hpl/gclk/hpl_gclk.d
new file mode 100644
index 0000000..a6b3259
--- /dev/null
+++ b/build/hpl/gclk/hpl_gclk.d
@@ -0,0 +1,244 @@
+hpl/gclk/hpl_gclk.d hpl/gclk/hpl_gclk.o: ../hpl/gclk/hpl_gclk.c \
+ ../config/hpl_gclk_config.h ../hal/include/hpl_init.h \
+ ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h ../hal/utils/include/utils_assert.h
+../config/hpl_gclk_config.h:
+../hal/include/hpl_init.h:
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
+../hal/utils/include/utils_assert.h:
diff --git a/build/hpl/gclk/hpl_gclk.o b/build/hpl/gclk/hpl_gclk.o
new file mode 100644
index 0000000..2c86aca
Binary files /dev/null and b/build/hpl/gclk/hpl_gclk.o differ
diff --git a/build/hpl/mclk/hpl_mclk.d b/build/hpl/mclk/hpl_mclk.d
new file mode 100644
index 0000000..b4657a6
--- /dev/null
+++ b/build/hpl/mclk/hpl_mclk.d
@@ -0,0 +1,243 @@
+hpl/mclk/hpl_mclk.d hpl/mclk/hpl_mclk.o: ../hpl/mclk/hpl_mclk.c \
+ ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h ../config/hpl_mclk_config.h \
+ ../config/peripheral_clk_config.h
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
+../config/hpl_mclk_config.h:
+../config/peripheral_clk_config.h:
diff --git a/build/hpl/mclk/hpl_mclk.o b/build/hpl/mclk/hpl_mclk.o
new file mode 100644
index 0000000..fc96e5e
Binary files /dev/null and b/build/hpl/mclk/hpl_mclk.o differ
diff --git a/build/hpl/osc32kctrl/hpl_osc32kctrl.d b/build/hpl/osc32kctrl/hpl_osc32kctrl.d
new file mode 100644
index 0000000..3a65eab
--- /dev/null
+++ b/build/hpl/osc32kctrl/hpl_osc32kctrl.d
@@ -0,0 +1,243 @@
+hpl/osc32kctrl/hpl_osc32kctrl.d hpl/osc32kctrl/hpl_osc32kctrl.o: \
+ ../hpl/osc32kctrl/hpl_osc32kctrl.c ../hal/include/hpl_init.h \
+ ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h ../config/hpl_osc32kctrl_config.h
+../hal/include/hpl_init.h:
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
+../config/hpl_osc32kctrl_config.h:
diff --git a/build/hpl/osc32kctrl/hpl_osc32kctrl.o b/build/hpl/osc32kctrl/hpl_osc32kctrl.o
new file mode 100644
index 0000000..9e197b3
Binary files /dev/null and b/build/hpl/osc32kctrl/hpl_osc32kctrl.o differ
diff --git a/build/hpl/oscctrl/hpl_oscctrl.d b/build/hpl/oscctrl/hpl_oscctrl.d
new file mode 100644
index 0000000..8530c8a
--- /dev/null
+++ b/build/hpl/oscctrl/hpl_oscctrl.d
@@ -0,0 +1,245 @@
+hpl/oscctrl/hpl_oscctrl.d hpl/oscctrl/hpl_oscctrl.o: \
+ ../hpl/oscctrl/hpl_oscctrl.c ../hal/include/hpl_init.h \
+ ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h ../config/hpl_oscctrl_config.h \
+ ../config/hpl_gclk_config.h
+../hal/include/hpl_init.h:
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
+../config/hpl_oscctrl_config.h:
+../config/hpl_gclk_config.h:
diff --git a/build/hpl/oscctrl/hpl_oscctrl.o b/build/hpl/oscctrl/hpl_oscctrl.o
new file mode 100644
index 0000000..ab827c4
Binary files /dev/null and b/build/hpl/oscctrl/hpl_oscctrl.o differ
diff --git a/build/hpl/pm/hpl_pm.d b/build/hpl/pm/hpl_pm.d
new file mode 100644
index 0000000..d8a9171
--- /dev/null
+++ b/build/hpl/pm/hpl_pm.d
@@ -0,0 +1,242 @@
+hpl/pm/hpl_pm.d hpl/pm/hpl_pm.o: ../hpl/pm/hpl_pm.c \
+ ../hal/include/hpl_sleep.h ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h ../hal/include/hpl_init.h
+../hal/include/hpl_sleep.h:
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
+../hal/include/hpl_init.h:
diff --git a/build/hpl/pm/hpl_pm.o b/build/hpl/pm/hpl_pm.o
new file mode 100644
index 0000000..11b8102
Binary files /dev/null and b/build/hpl/pm/hpl_pm.o differ
diff --git a/build/hpl/ramecc/hpl_ramecc.d b/build/hpl/ramecc/hpl_ramecc.d
new file mode 100644
index 0000000..68c4689
--- /dev/null
+++ b/build/hpl/ramecc/hpl_ramecc.d
@@ -0,0 +1,246 @@
+hpl/ramecc/hpl_ramecc.d hpl/ramecc/hpl_ramecc.o: \
+ ../hpl/ramecc/hpl_ramecc.c ../hal/utils/include/utils.h \
+ ../hal/utils/include/utils_assert.h ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h ../hal/include/hpl_ramecc.h \
+ ../hal/include/hpl_irq.h
+../hal/utils/include/utils.h:
+../hal/utils/include/utils_assert.h:
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
+../hal/include/hpl_ramecc.h:
+../hal/include/hpl_irq.h:
diff --git a/build/hpl/ramecc/hpl_ramecc.o b/build/hpl/ramecc/hpl_ramecc.o
new file mode 100644
index 0000000..adcd579
Binary files /dev/null and b/build/hpl/ramecc/hpl_ramecc.o differ
diff --git a/build/hpl/rtc/hpl_rtc.d b/build/hpl/rtc/hpl_rtc.d
new file mode 100644
index 0000000..9b19ca9
--- /dev/null
+++ b/build/hpl/rtc/hpl_rtc.d
@@ -0,0 +1,247 @@
+hpl/rtc/hpl_rtc.d hpl/rtc/hpl_rtc.o: ../hpl/rtc/hpl_rtc.c \
+ ../hal/include/hpl_calendar.h ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h ../hal/utils/include/utils_list.h \
+ ../hal/include/hpl_irq.h ../hal/utils/include/utils_assert.h \
+ ../config/hpl_rtc_config.h
+../hal/include/hpl_calendar.h:
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
+../hal/utils/include/utils_list.h:
+../hal/include/hpl_irq.h:
+../hal/utils/include/utils_assert.h:
+../config/hpl_rtc_config.h:
diff --git a/build/hpl/rtc/hpl_rtc.o b/build/hpl/rtc/hpl_rtc.o
new file mode 100644
index 0000000..868eb6b
Binary files /dev/null and b/build/hpl/rtc/hpl_rtc.o differ
diff --git a/build/hpl/sdhc/hpl_sdhc.d b/build/hpl/sdhc/hpl_sdhc.d
new file mode 100644
index 0000000..af198e8
--- /dev/null
+++ b/build/hpl/sdhc/hpl_sdhc.d
@@ -0,0 +1,247 @@
+hpl/sdhc/hpl_sdhc.d hpl/sdhc/hpl_sdhc.o: ../hpl/sdhc/hpl_sdhc.c \
+ ../hal/utils/include/utils_assert.h ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h ../hal/include/hpl_mci_sync.h \
+ ../hal/utils/include/utils.h ../config/hpl_sdhc_config.h \
+ ../config/peripheral_clk_config.h
+../hal/utils/include/utils_assert.h:
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
+../hal/include/hpl_mci_sync.h:
+../hal/utils/include/utils.h:
+../config/hpl_sdhc_config.h:
+../config/peripheral_clk_config.h:
diff --git a/build/hpl/sdhc/hpl_sdhc.o b/build/hpl/sdhc/hpl_sdhc.o
new file mode 100644
index 0000000..f74aec4
Binary files /dev/null and b/build/hpl/sdhc/hpl_sdhc.o differ
diff --git a/build/hpl/sercom/hpl_sercom.d b/build/hpl/sercom/hpl_sercom.d
new file mode 100644
index 0000000..056a84b
--- /dev/null
+++ b/build/hpl/sercom/hpl_sercom.d
@@ -0,0 +1,275 @@
+hpl/sercom/hpl_sercom.d hpl/sercom/hpl_sercom.o: \
+ ../hpl/sercom/hpl_sercom.c ../hal/include/hpl_dma.h \
+ ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h ../hal/include/hpl_irq.h \
+ ../hal/include/hpl_i2c_m_async.h ../hal/include/hpl_i2c_m_sync.h \
+ ../hal/include/hpl_irq.h ../hal/utils/include/utils.h \
+ ../hal/include/hpl_i2c_m_sync.h ../hal/include/hpl_i2c_s_async.h \
+ ../hal/include/hpl_i2c_s_sync.h ../config/hpl_sercom_config.h \
+ ../config/peripheral_clk_config.h ../hal/include/hpl_spi_m_async.h \
+ ../hal/include/hpl_spi.h ../hal/include/hpl_spi_async.h \
+ ../hal/include/hpl_spi_m_sync.h ../hal/include/hpl_spi_sync.h \
+ ../hal/include/hpl_spi_s_async.h ../hal/include/hpl_spi_s_sync.h \
+ ../hal/include/hpl_usart_async.h ../hal/include/hpl_usart.h \
+ ../hal/include/hpl_usart_sync.h ../hal/include/hpl_usart.h \
+ ../hal/utils/include/utils_assert.h
+../hal/include/hpl_dma.h:
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
+../hal/include/hpl_irq.h:
+../hal/include/hpl_i2c_m_async.h:
+../hal/include/hpl_i2c_m_sync.h:
+../hal/include/hpl_irq.h:
+../hal/utils/include/utils.h:
+../hal/include/hpl_i2c_m_sync.h:
+../hal/include/hpl_i2c_s_async.h:
+../hal/include/hpl_i2c_s_sync.h:
+../config/hpl_sercom_config.h:
+../config/peripheral_clk_config.h:
+../hal/include/hpl_spi_m_async.h:
+../hal/include/hpl_spi.h:
+../hal/include/hpl_spi_async.h:
+../hal/include/hpl_spi_m_sync.h:
+../hal/include/hpl_spi_sync.h:
+../hal/include/hpl_spi_s_async.h:
+../hal/include/hpl_spi_s_sync.h:
+../hal/include/hpl_usart_async.h:
+../hal/include/hpl_usart.h:
+../hal/include/hpl_usart_sync.h:
+../hal/include/hpl_usart.h:
+../hal/utils/include/utils_assert.h:
diff --git a/build/hpl/sercom/hpl_sercom.o b/build/hpl/sercom/hpl_sercom.o
new file mode 100644
index 0000000..db562ab
Binary files /dev/null and b/build/hpl/sercom/hpl_sercom.o differ
diff --git a/build/hpl/systick/hpl_systick.d b/build/hpl/systick/hpl_systick.d
new file mode 100644
index 0000000..54f8e0f
--- /dev/null
+++ b/build/hpl/systick/hpl_systick.d
@@ -0,0 +1,243 @@
+hpl/systick/hpl_systick.d hpl/systick/hpl_systick.o: \
+ ../hpl/systick/hpl_systick.c ../hal/include/hpl_time_measure.h \
+ ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h ../config/hpl_systick_config.h
+../hal/include/hpl_time_measure.h:
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
+../config/hpl_systick_config.h:
diff --git a/build/hpl/systick/hpl_systick.o b/build/hpl/systick/hpl_systick.o
new file mode 100644
index 0000000..e6375dc
Binary files /dev/null and b/build/hpl/systick/hpl_systick.o differ
diff --git a/build/main.d b/build/main.d
new file mode 100644
index 0000000..badac50
--- /dev/null
+++ b/build/main.d
@@ -0,0 +1,336 @@
+main.d main.o: ../main.c ../atmel_start.h ../driver_init.h \
+ ../atmel_start_pins.h ../hal/include/hal_gpio.h \
+ ../hal/include/hpl_gpio.h ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h ../hpl/port/hpl_gpio_base.h \
+ ../hal/utils/include/utils_assert.h ../config/hpl_port_config.h \
+ ../hal/include/hal_delay.h ../hal/include/hpl_irq.h \
+ ../hal/include/hpl_reset.h ../hal/include/hpl_sleep.h \
+ ../hal/include/hal_init.h ../hal/include/hpl_init.h \
+ ../hal/include/hal_io.h ../hal/include/hal_sleep.h \
+ ../hal/include/hal_calendar.h ../hal/include/hpl_calendar.h \
+ ../hal/utils/include/utils_list.h ../hal/include/hpl_irq.h \
+ ../hal/include/hal_usart_sync.h ../hal/include/hal_io.h \
+ ../hal/include/hpl_usart_sync.h ../hal/include/hpl_usart.h \
+ ../hal/include/hal_spi_m_sync.h ../hal/include/hpl_spi_m_sync.h \
+ ../hal/include/hpl_spi.h ../hal/utils/include/utils.h \
+ ../hal/include/hpl_spi_sync.h ../hal/include/hal_mci_sync.h \
+ ../hal/include/hpl_mci_sync.h ../sd_mmc_start.h \
+ /usr/arm-none-eabi/include/stdio.h /usr/arm-none-eabi/include/_ansi.h \
+ /usr/arm-none-eabi/include/newlib.h \
+ /usr/arm-none-eabi/include/sys/config.h \
+ /usr/arm-none-eabi/include/machine/ieeefp.h \
+ /usr/arm-none-eabi/include/sys/cdefs.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdarg.h \
+ /usr/arm-none-eabi/include/sys/reent.h \
+ /usr/arm-none-eabi/include/_ansi.h \
+ /usr/arm-none-eabi/include/sys/_types.h \
+ /usr/arm-none-eabi/include/machine/_types.h \
+ /usr/arm-none-eabi/include/sys/lock.h \
+ /usr/arm-none-eabi/include/sys/types.h \
+ /usr/arm-none-eabi/include/machine/endian.h \
+ /usr/arm-none-eabi/include/machine/_endian.h \
+ /usr/arm-none-eabi/include/sys/select.h \
+ /usr/arm-none-eabi/include/sys/_sigset.h \
+ /usr/arm-none-eabi/include/sys/_timeval.h \
+ /usr/arm-none-eabi/include/sys/timespec.h \
+ /usr/arm-none-eabi/include/sys/_timespec.h \
+ /usr/arm-none-eabi/include/sys/_pthreadtypes.h \
+ /usr/arm-none-eabi/include/sys/sched.h \
+ /usr/arm-none-eabi/include/machine/types.h \
+ /usr/arm-none-eabi/include/sys/stdio.h ../diskio_start.h \
+ ../shared/util/pdebug.h
+../atmel_start.h:
+../driver_init.h:
+../atmel_start_pins.h:
+../hal/include/hal_gpio.h:
+../hal/include/hpl_gpio.h:
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
+../hpl/port/hpl_gpio_base.h:
+../hal/utils/include/utils_assert.h:
+../config/hpl_port_config.h:
+../hal/include/hal_delay.h:
+../hal/include/hpl_irq.h:
+../hal/include/hpl_reset.h:
+../hal/include/hpl_sleep.h:
+../hal/include/hal_init.h:
+../hal/include/hpl_init.h:
+../hal/include/hal_io.h:
+../hal/include/hal_sleep.h:
+../hal/include/hal_calendar.h:
+../hal/include/hpl_calendar.h:
+../hal/utils/include/utils_list.h:
+../hal/include/hpl_irq.h:
+../hal/include/hal_usart_sync.h:
+../hal/include/hal_io.h:
+../hal/include/hpl_usart_sync.h:
+../hal/include/hpl_usart.h:
+../hal/include/hal_spi_m_sync.h:
+../hal/include/hpl_spi_m_sync.h:
+../hal/include/hpl_spi.h:
+../hal/utils/include/utils.h:
+../hal/include/hpl_spi_sync.h:
+../hal/include/hal_mci_sync.h:
+../hal/include/hpl_mci_sync.h:
+../sd_mmc_start.h:
+/usr/arm-none-eabi/include/stdio.h:
+/usr/arm-none-eabi/include/_ansi.h:
+/usr/arm-none-eabi/include/newlib.h:
+/usr/arm-none-eabi/include/sys/config.h:
+/usr/arm-none-eabi/include/machine/ieeefp.h:
+/usr/arm-none-eabi/include/sys/cdefs.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdarg.h:
+/usr/arm-none-eabi/include/sys/reent.h:
+/usr/arm-none-eabi/include/_ansi.h:
+/usr/arm-none-eabi/include/sys/_types.h:
+/usr/arm-none-eabi/include/machine/_types.h:
+/usr/arm-none-eabi/include/sys/lock.h:
+/usr/arm-none-eabi/include/sys/types.h:
+/usr/arm-none-eabi/include/machine/endian.h:
+/usr/arm-none-eabi/include/machine/_endian.h:
+/usr/arm-none-eabi/include/sys/select.h:
+/usr/arm-none-eabi/include/sys/_sigset.h:
+/usr/arm-none-eabi/include/sys/_timeval.h:
+/usr/arm-none-eabi/include/sys/timespec.h:
+/usr/arm-none-eabi/include/sys/_timespec.h:
+/usr/arm-none-eabi/include/sys/_pthreadtypes.h:
+/usr/arm-none-eabi/include/sys/sched.h:
+/usr/arm-none-eabi/include/machine/types.h:
+/usr/arm-none-eabi/include/sys/stdio.h:
+../diskio_start.h:
+../shared/util/pdebug.h:
diff --git a/build/main.o b/build/main.o
new file mode 100644
index 0000000..846f1db
Binary files /dev/null and b/build/main.o differ
diff --git a/build/scripts/debug.gdb b/build/scripts/debug.gdb
index c765f5e..af24591 100644
--- a/build/scripts/debug.gdb
+++ b/build/scripts/debug.gdb
@@ -1,6 +1,7 @@
 set pagination off
 set logging file gdb.txt
 set logging on
-target extended-remote localhost:3333
+target extended-remote /dev/ttyACM0 
+blackmagic
 load
 monitor reset
diff --git a/build/scripts/push.gdb b/build/scripts/push.gdb
index c979684..fe7c2e3 100644
--- a/build/scripts/push.gdb
+++ b/build/scripts/push.gdb
@@ -2,8 +2,11 @@ set pagination off
 set logging file gdb.txt
 set logging redirect on
 set logging on
-target extended-remote localhost:3333
+target extended-remote /dev/ttyACM0
+attach 1
+b main
 load
-monitor reset
+r
+detach
 q
 y
diff --git a/build/sd_mmc/sd_mmc.d b/build/sd_mmc/sd_mmc.d
new file mode 100644
index 0000000..2a7f075
--- /dev/null
+++ b/build/sd_mmc/sd_mmc.d
@@ -0,0 +1,352 @@
+sd_mmc/sd_mmc.d sd_mmc/sd_mmc.o: ../sd_mmc/sd_mmc.c \
+ /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \
+ /usr/arm-none-eabi/include/newlib.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/config.h \
+ /usr/arm-none-eabi/include/machine/ieeefp.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/sys/reent.h \
+ /usr/arm-none-eabi/include/_ansi.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/arm-none-eabi/include/sys/_types.h \
+ /usr/arm-none-eabi/include/machine/_types.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/lock.h \
+ /usr/arm-none-eabi/include/sys/cdefs.h \
+ /usr/arm-none-eabi/include/sys/_locale.h \
+ /usr/arm-none-eabi/include/strings.h \
+ /usr/arm-none-eabi/include/sys/string.h ../config/conf_sd_mmc.h \
+ ../hal/include/hal_spi_m_sync.h ../hal/include/hal_io.h \
+ ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h ../hal/include/hpl_spi_m_sync.h \
+ ../hal/include/hpl_spi.h ../hal/utils/include/utils.h \
+ ../hal/include/hpl_spi_sync.h ../sd_mmc/sd_mmc_protocol.h \
+ ../sd_mmc/sd_mmc.h ../hal/include/hal_gpio.h ../hal/include/hpl_gpio.h \
+ ../hpl/port/hpl_gpio_base.h ../hal/utils/include/utils_assert.h \
+ ../config/hpl_port_config.h ../hal/utils/include/utils_repeat_macro.h \
+ ../hal/utils/include/utils_increment_macro.h \
+ ../hal/include/hal_mci_sync.h ../hal/include/hpl_mci_sync.h \
+ ../sd_mmc/sd_mmc_spi.h /usr/arm-none-eabi/include/stdio.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdarg.h \
+ /usr/arm-none-eabi/include/sys/types.h \
+ /usr/arm-none-eabi/include/machine/endian.h \
+ /usr/arm-none-eabi/include/machine/_endian.h \
+ /usr/arm-none-eabi/include/sys/select.h \
+ /usr/arm-none-eabi/include/sys/_sigset.h \
+ /usr/arm-none-eabi/include/sys/_timeval.h \
+ /usr/arm-none-eabi/include/sys/timespec.h \
+ /usr/arm-none-eabi/include/sys/_timespec.h \
+ /usr/arm-none-eabi/include/sys/_pthreadtypes.h \
+ /usr/arm-none-eabi/include/sys/sched.h \
+ /usr/arm-none-eabi/include/machine/types.h \
+ /usr/arm-none-eabi/include/sys/stdio.h ../shared/util/pdebug.h \
+ ../atmel_start.h ../driver_init.h ../atmel_start_pins.h \
+ ../hal/include/hal_delay.h ../hal/include/hpl_irq.h \
+ ../hal/include/hpl_reset.h ../hal/include/hpl_sleep.h \
+ ../hal/include/hal_init.h ../hal/include/hpl_init.h \
+ ../hal/include/hal_sleep.h ../hal/include/hal_calendar.h \
+ ../hal/include/hpl_calendar.h ../hal/utils/include/utils_list.h \
+ ../hal/include/hpl_irq.h ../hal/include/hal_usart_sync.h \
+ ../hal/include/hal_io.h ../hal/include/hpl_usart_sync.h \
+ ../hal/include/hpl_usart.h ../sd_mmc_start.h ../diskio_start.h
+/usr/arm-none-eabi/include/string.h:
+/usr/arm-none-eabi/include/_ansi.h:
+/usr/arm-none-eabi/include/newlib.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/config.h:
+/usr/arm-none-eabi/include/machine/ieeefp.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/sys/reent.h:
+/usr/arm-none-eabi/include/_ansi.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/arm-none-eabi/include/sys/_types.h:
+/usr/arm-none-eabi/include/machine/_types.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/lock.h:
+/usr/arm-none-eabi/include/sys/cdefs.h:
+/usr/arm-none-eabi/include/sys/_locale.h:
+/usr/arm-none-eabi/include/strings.h:
+/usr/arm-none-eabi/include/sys/string.h:
+../config/conf_sd_mmc.h:
+../hal/include/hal_spi_m_sync.h:
+../hal/include/hal_io.h:
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
+../hal/include/hpl_spi_m_sync.h:
+../hal/include/hpl_spi.h:
+../hal/utils/include/utils.h:
+../hal/include/hpl_spi_sync.h:
+../sd_mmc/sd_mmc_protocol.h:
+../sd_mmc/sd_mmc.h:
+../hal/include/hal_gpio.h:
+../hal/include/hpl_gpio.h:
+../hpl/port/hpl_gpio_base.h:
+../hal/utils/include/utils_assert.h:
+../config/hpl_port_config.h:
+../hal/utils/include/utils_repeat_macro.h:
+../hal/utils/include/utils_increment_macro.h:
+../hal/include/hal_mci_sync.h:
+../hal/include/hpl_mci_sync.h:
+../sd_mmc/sd_mmc_spi.h:
+/usr/arm-none-eabi/include/stdio.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdarg.h:
+/usr/arm-none-eabi/include/sys/types.h:
+/usr/arm-none-eabi/include/machine/endian.h:
+/usr/arm-none-eabi/include/machine/_endian.h:
+/usr/arm-none-eabi/include/sys/select.h:
+/usr/arm-none-eabi/include/sys/_sigset.h:
+/usr/arm-none-eabi/include/sys/_timeval.h:
+/usr/arm-none-eabi/include/sys/timespec.h:
+/usr/arm-none-eabi/include/sys/_timespec.h:
+/usr/arm-none-eabi/include/sys/_pthreadtypes.h:
+/usr/arm-none-eabi/include/sys/sched.h:
+/usr/arm-none-eabi/include/machine/types.h:
+/usr/arm-none-eabi/include/sys/stdio.h:
+../shared/util/pdebug.h:
+../atmel_start.h:
+../driver_init.h:
+../atmel_start_pins.h:
+../hal/include/hal_delay.h:
+../hal/include/hpl_irq.h:
+../hal/include/hpl_reset.h:
+../hal/include/hpl_sleep.h:
+../hal/include/hal_init.h:
+../hal/include/hpl_init.h:
+../hal/include/hal_sleep.h:
+../hal/include/hal_calendar.h:
+../hal/include/hpl_calendar.h:
+../hal/utils/include/utils_list.h:
+../hal/include/hpl_irq.h:
+../hal/include/hal_usart_sync.h:
+../hal/include/hal_io.h:
+../hal/include/hpl_usart_sync.h:
+../hal/include/hpl_usart.h:
+../sd_mmc_start.h:
+../diskio_start.h:
diff --git a/build/sd_mmc/sd_mmc.o b/build/sd_mmc/sd_mmc.o
new file mode 100644
index 0000000..d0e3e4d
Binary files /dev/null and b/build/sd_mmc/sd_mmc.o differ
diff --git a/build/sd_mmc/sd_mmc_spi.d b/build/sd_mmc/sd_mmc_spi.d
new file mode 100644
index 0000000..347175e
--- /dev/null
+++ b/build/sd_mmc/sd_mmc_spi.d
@@ -0,0 +1,340 @@
+sd_mmc/sd_mmc_spi.d sd_mmc/sd_mmc_spi.o: ../sd_mmc/sd_mmc_spi.c \
+ ../sd_mmc/sd_mmc_spi.h ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h ../sd_mmc/sd_mmc_protocol.h \
+ ../hal/include/hal_spi_m_sync.h ../hal/include/hal_io.h \
+ ../hal/include/hpl_spi_m_sync.h ../hal/include/hpl_spi.h \
+ ../hal/utils/include/utils.h ../hal/include/hpl_spi_sync.h \
+ /usr/arm-none-eabi/include/stdio.h /usr/arm-none-eabi/include/_ansi.h \
+ /usr/arm-none-eabi/include/newlib.h \
+ /usr/arm-none-eabi/include/sys/config.h \
+ /usr/arm-none-eabi/include/machine/ieeefp.h \
+ /usr/arm-none-eabi/include/sys/cdefs.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdarg.h \
+ /usr/arm-none-eabi/include/sys/reent.h \
+ /usr/arm-none-eabi/include/_ansi.h \
+ /usr/arm-none-eabi/include/sys/_types.h \
+ /usr/arm-none-eabi/include/machine/_types.h \
+ /usr/arm-none-eabi/include/sys/lock.h \
+ /usr/arm-none-eabi/include/sys/types.h \
+ /usr/arm-none-eabi/include/machine/endian.h \
+ /usr/arm-none-eabi/include/machine/_endian.h \
+ /usr/arm-none-eabi/include/sys/select.h \
+ /usr/arm-none-eabi/include/sys/_sigset.h \
+ /usr/arm-none-eabi/include/sys/_timeval.h \
+ /usr/arm-none-eabi/include/sys/timespec.h \
+ /usr/arm-none-eabi/include/sys/_timespec.h \
+ /usr/arm-none-eabi/include/sys/_pthreadtypes.h \
+ /usr/arm-none-eabi/include/sys/sched.h \
+ /usr/arm-none-eabi/include/machine/types.h \
+ /usr/arm-none-eabi/include/sys/stdio.h ../shared/util/pdebug.h \
+ ../atmel_start.h ../driver_init.h ../atmel_start_pins.h \
+ ../hal/include/hal_gpio.h ../hal/include/hpl_gpio.h \
+ ../hpl/port/hpl_gpio_base.h ../hal/utils/include/utils_assert.h \
+ ../config/hpl_port_config.h ../hal/include/hal_delay.h \
+ ../hal/include/hpl_irq.h ../hal/include/hpl_reset.h \
+ ../hal/include/hpl_sleep.h ../hal/include/hal_init.h \
+ ../hal/include/hpl_init.h ../hal/include/hal_sleep.h \
+ ../hal/include/hal_calendar.h ../hal/include/hpl_calendar.h \
+ ../hal/utils/include/utils_list.h ../hal/include/hpl_irq.h \
+ ../hal/include/hal_usart_sync.h ../hal/include/hal_io.h \
+ ../hal/include/hpl_usart_sync.h ../hal/include/hpl_usart.h \
+ ../hal/include/hal_mci_sync.h ../hal/include/hpl_mci_sync.h \
+ ../sd_mmc_start.h ../diskio_start.h ../atmel_start_pins.h
+../sd_mmc/sd_mmc_spi.h:
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
+../sd_mmc/sd_mmc_protocol.h:
+../hal/include/hal_spi_m_sync.h:
+../hal/include/hal_io.h:
+../hal/include/hpl_spi_m_sync.h:
+../hal/include/hpl_spi.h:
+../hal/utils/include/utils.h:
+../hal/include/hpl_spi_sync.h:
+/usr/arm-none-eabi/include/stdio.h:
+/usr/arm-none-eabi/include/_ansi.h:
+/usr/arm-none-eabi/include/newlib.h:
+/usr/arm-none-eabi/include/sys/config.h:
+/usr/arm-none-eabi/include/machine/ieeefp.h:
+/usr/arm-none-eabi/include/sys/cdefs.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdarg.h:
+/usr/arm-none-eabi/include/sys/reent.h:
+/usr/arm-none-eabi/include/_ansi.h:
+/usr/arm-none-eabi/include/sys/_types.h:
+/usr/arm-none-eabi/include/machine/_types.h:
+/usr/arm-none-eabi/include/sys/lock.h:
+/usr/arm-none-eabi/include/sys/types.h:
+/usr/arm-none-eabi/include/machine/endian.h:
+/usr/arm-none-eabi/include/machine/_endian.h:
+/usr/arm-none-eabi/include/sys/select.h:
+/usr/arm-none-eabi/include/sys/_sigset.h:
+/usr/arm-none-eabi/include/sys/_timeval.h:
+/usr/arm-none-eabi/include/sys/timespec.h:
+/usr/arm-none-eabi/include/sys/_timespec.h:
+/usr/arm-none-eabi/include/sys/_pthreadtypes.h:
+/usr/arm-none-eabi/include/sys/sched.h:
+/usr/arm-none-eabi/include/machine/types.h:
+/usr/arm-none-eabi/include/sys/stdio.h:
+../shared/util/pdebug.h:
+../atmel_start.h:
+../driver_init.h:
+../atmel_start_pins.h:
+../hal/include/hal_gpio.h:
+../hal/include/hpl_gpio.h:
+../hpl/port/hpl_gpio_base.h:
+../hal/utils/include/utils_assert.h:
+../config/hpl_port_config.h:
+../hal/include/hal_delay.h:
+../hal/include/hpl_irq.h:
+../hal/include/hpl_reset.h:
+../hal/include/hpl_sleep.h:
+../hal/include/hal_init.h:
+../hal/include/hpl_init.h:
+../hal/include/hal_sleep.h:
+../hal/include/hal_calendar.h:
+../hal/include/hpl_calendar.h:
+../hal/utils/include/utils_list.h:
+../hal/include/hpl_irq.h:
+../hal/include/hal_usart_sync.h:
+../hal/include/hal_io.h:
+../hal/include/hpl_usart_sync.h:
+../hal/include/hpl_usart.h:
+../hal/include/hal_mci_sync.h:
+../hal/include/hpl_mci_sync.h:
+../sd_mmc_start.h:
+../diskio_start.h:
+../atmel_start_pins.h:
diff --git a/build/sd_mmc/sd_mmc_spi.o b/build/sd_mmc/sd_mmc_spi.o
new file mode 100644
index 0000000..b69f05f
Binary files /dev/null and b/build/sd_mmc/sd_mmc_spi.o differ
diff --git a/build/sd_mmc_start.d b/build/sd_mmc_start.d
new file mode 100644
index 0000000..ed0a3d2
--- /dev/null
+++ b/build/sd_mmc_start.d
@@ -0,0 +1,338 @@
+sd_mmc_start.d sd_mmc_start.o: ../sd_mmc_start.c ../atmel_start.h \
+ ../driver_init.h ../atmel_start_pins.h ../hal/include/hal_gpio.h \
+ ../hal/include/hpl_gpio.h ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h ../hpl/port/hpl_gpio_base.h \
+ ../hal/utils/include/utils_assert.h ../config/hpl_port_config.h \
+ ../hal/include/hal_delay.h ../hal/include/hpl_irq.h \
+ ../hal/include/hpl_reset.h ../hal/include/hpl_sleep.h \
+ ../hal/include/hal_init.h ../hal/include/hpl_init.h \
+ ../hal/include/hal_io.h ../hal/include/hal_sleep.h \
+ ../hal/include/hal_calendar.h ../hal/include/hpl_calendar.h \
+ ../hal/utils/include/utils_list.h ../hal/include/hpl_irq.h \
+ ../hal/include/hal_usart_sync.h ../hal/include/hal_io.h \
+ ../hal/include/hpl_usart_sync.h ../hal/include/hpl_usart.h \
+ ../hal/include/hal_spi_m_sync.h ../hal/include/hpl_spi_m_sync.h \
+ ../hal/include/hpl_spi.h ../hal/utils/include/utils.h \
+ ../hal/include/hpl_spi_sync.h ../hal/include/hal_mci_sync.h \
+ ../hal/include/hpl_mci_sync.h ../sd_mmc_start.h \
+ /usr/arm-none-eabi/include/stdio.h /usr/arm-none-eabi/include/_ansi.h \
+ /usr/arm-none-eabi/include/newlib.h \
+ /usr/arm-none-eabi/include/sys/config.h \
+ /usr/arm-none-eabi/include/machine/ieeefp.h \
+ /usr/arm-none-eabi/include/sys/cdefs.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdarg.h \
+ /usr/arm-none-eabi/include/sys/reent.h \
+ /usr/arm-none-eabi/include/_ansi.h \
+ /usr/arm-none-eabi/include/sys/_types.h \
+ /usr/arm-none-eabi/include/machine/_types.h \
+ /usr/arm-none-eabi/include/sys/lock.h \
+ /usr/arm-none-eabi/include/sys/types.h \
+ /usr/arm-none-eabi/include/machine/endian.h \
+ /usr/arm-none-eabi/include/machine/_endian.h \
+ /usr/arm-none-eabi/include/sys/select.h \
+ /usr/arm-none-eabi/include/sys/_sigset.h \
+ /usr/arm-none-eabi/include/sys/_timeval.h \
+ /usr/arm-none-eabi/include/sys/timespec.h \
+ /usr/arm-none-eabi/include/sys/_timespec.h \
+ /usr/arm-none-eabi/include/sys/_pthreadtypes.h \
+ /usr/arm-none-eabi/include/sys/sched.h \
+ /usr/arm-none-eabi/include/machine/types.h \
+ /usr/arm-none-eabi/include/sys/stdio.h ../diskio_start.h \
+ ../atmel_start.h ../sd_mmc/sd_mmc.h ../config/conf_sd_mmc.h
+../atmel_start.h:
+../driver_init.h:
+../atmel_start_pins.h:
+../hal/include/hal_gpio.h:
+../hal/include/hpl_gpio.h:
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
+../include/instance/aes.h:
+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
+../include/instance/cmcc.h:
+../include/instance/dac.h:
+../include/instance/dmac.h:
+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
+../include/instance/hmatrix.h:
+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
+../include/instance/tc6.h:
+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
+../hri/hri_port_e54.h:
+../hri/hri_qspi_e54.h:
+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
+../hri/hri_sercom_e54.h:
+../hri/hri_supc_e54.h:
+../hri/hri_tc_e54.h:
+../hri/hri_tcc_e54.h:
+../hri/hri_trng_e54.h:
+../hri/hri_usb_e54.h:
+../hri/hri_wdt_e54.h:
+../hal/utils/include/err_codes.h:
+../hpl/port/hpl_gpio_base.h:
+../hal/utils/include/utils_assert.h:
+../config/hpl_port_config.h:
+../hal/include/hal_delay.h:
+../hal/include/hpl_irq.h:
+../hal/include/hpl_reset.h:
+../hal/include/hpl_sleep.h:
+../hal/include/hal_init.h:
+../hal/include/hpl_init.h:
+../hal/include/hal_io.h:
+../hal/include/hal_sleep.h:
+../hal/include/hal_calendar.h:
+../hal/include/hpl_calendar.h:
+../hal/utils/include/utils_list.h:
+../hal/include/hpl_irq.h:
+../hal/include/hal_usart_sync.h:
+../hal/include/hal_io.h:
+../hal/include/hpl_usart_sync.h:
+../hal/include/hpl_usart.h:
+../hal/include/hal_spi_m_sync.h:
+../hal/include/hpl_spi_m_sync.h:
+../hal/include/hpl_spi.h:
+../hal/utils/include/utils.h:
+../hal/include/hpl_spi_sync.h:
+../hal/include/hal_mci_sync.h:
+../hal/include/hpl_mci_sync.h:
+../sd_mmc_start.h:
+/usr/arm-none-eabi/include/stdio.h:
+/usr/arm-none-eabi/include/_ansi.h:
+/usr/arm-none-eabi/include/newlib.h:
+/usr/arm-none-eabi/include/sys/config.h:
+/usr/arm-none-eabi/include/machine/ieeefp.h:
+/usr/arm-none-eabi/include/sys/cdefs.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdarg.h:
+/usr/arm-none-eabi/include/sys/reent.h:
+/usr/arm-none-eabi/include/_ansi.h:
+/usr/arm-none-eabi/include/sys/_types.h:
+/usr/arm-none-eabi/include/machine/_types.h:
+/usr/arm-none-eabi/include/sys/lock.h:
+/usr/arm-none-eabi/include/sys/types.h:
+/usr/arm-none-eabi/include/machine/endian.h:
+/usr/arm-none-eabi/include/machine/_endian.h:
+/usr/arm-none-eabi/include/sys/select.h:
+/usr/arm-none-eabi/include/sys/_sigset.h:
+/usr/arm-none-eabi/include/sys/_timeval.h:
+/usr/arm-none-eabi/include/sys/timespec.h:
+/usr/arm-none-eabi/include/sys/_timespec.h:
+/usr/arm-none-eabi/include/sys/_pthreadtypes.h:
+/usr/arm-none-eabi/include/sys/sched.h:
+/usr/arm-none-eabi/include/machine/types.h:
+/usr/arm-none-eabi/include/sys/stdio.h:
+../diskio_start.h:
+../atmel_start.h:
+../sd_mmc/sd_mmc.h:
+../config/conf_sd_mmc.h:
diff --git a/build/sd_mmc_start.o b/build/sd_mmc_start.o
new file mode 100644
index 0000000..17f0f61
Binary files /dev/null and b/build/sd_mmc_start.o differ
diff --git a/build/shared/util/pdebug.d b/build/shared/util/pdebug.d
new file mode 100644
index 0000000..a271f82
--- /dev/null
+++ b/build/shared/util/pdebug.d
@@ -0,0 +1,345 @@
+shared/util/pdebug.d shared/util/pdebug.o: ../shared/util/pdebug.c \
+ ../shared/util/pdebug.h ../atmel_start.h ../driver_init.h \
+ ../atmel_start_pins.h ../hal/include/hal_gpio.h \
+ ../hal/include/hpl_gpio.h ../hal/utils/include/compiler.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h \
+ /usr/arm-none-eabi/include/stdint.h \
+ /usr/arm-none-eabi/include/machine/_default_types.h \
+ /usr/arm-none-eabi/include/sys/features.h \
+ /usr/arm-none-eabi/include/_newlib_version.h \
+ /usr/arm-none-eabi/include/sys/_intsup.h \
+ /usr/arm-none-eabi/include/sys/_stdint.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h \
+ ../hal/utils/include/parts.h ../include/same54.h ../include/same54p20a.h \
+ ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \
+ ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \
+ ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \
+ ../include/component/ac.h ../include/component/adc.h \
+ ../include/component/aes.h ../include/component/can.h \
+ ../include/component/ccl.h ../include/component/cmcc.h \
+ ../include/component/dac.h ../include/component/dmac.h \
+ ../include/component/dsu.h ../include/component/eic.h \
+ ../include/component/evsys.h ../include/component/freqm.h \
+ ../include/component/gclk.h ../include/component/gmac.h \
+ ../include/component/hmatrixb.h ../include/component/icm.h \
+ ../include/component/i2s.h ../include/component/mclk.h \
+ ../include/component/nvmctrl.h ../include/component/oscctrl.h \
+ ../include/component/osc32kctrl.h ../include/component/pac.h \
+ ../include/component/pcc.h ../include/component/pdec.h \
+ ../include/component/pm.h ../include/component/port.h \
+ ../include/component/qspi.h ../include/component/ramecc.h \
+ ../include/component/rstc.h ../include/component/rtc.h \
+ ../include/component/sdhc.h ../include/component/sercom.h \
+ ../include/component/supc.h ../include/component/tc.h \
+ ../include/component/tcc.h ../include/component/trng.h \
+ ../include/component/usb.h ../include/component/wdt.h \
+ ../include/instance/ac.h ../include/instance/adc0.h \
+ ../include/instance/adc1.h ../include/instance/aes.h \
+ ../include/instance/can0.h ../include/instance/can1.h \
+ ../include/instance/ccl.h ../include/instance/cmcc.h \
+ ../include/instance/dac.h ../include/instance/dmac.h \
+ ../include/instance/dsu.h ../include/instance/eic.h \
+ ../include/instance/evsys.h ../include/instance/freqm.h \
+ ../include/instance/gclk.h ../include/instance/gmac.h \
+ ../include/instance/hmatrix.h ../include/instance/icm.h \
+ ../include/instance/i2s.h ../include/instance/mclk.h \
+ ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \
+ ../include/instance/osc32kctrl.h ../include/instance/pac.h \
+ ../include/instance/pcc.h ../include/instance/pdec.h \
+ ../include/instance/pm.h ../include/instance/port.h \
+ ../include/instance/pukcc.h ../include/instance/qspi.h \
+ ../include/instance/ramecc.h ../include/instance/rstc.h \
+ ../include/instance/rtc.h ../include/instance/sdhc0.h \
+ ../include/instance/sdhc1.h ../include/instance/sercom0.h \
+ ../include/instance/sercom1.h ../include/instance/sercom2.h \
+ ../include/instance/sercom3.h ../include/instance/sercom4.h \
+ ../include/instance/sercom5.h ../include/instance/sercom6.h \
+ ../include/instance/sercom7.h ../include/instance/supc.h \
+ ../include/instance/tc0.h ../include/instance/tc1.h \
+ ../include/instance/tc2.h ../include/instance/tc3.h \
+ ../include/instance/tc4.h ../include/instance/tc5.h \
+ ../include/instance/tc6.h ../include/instance/tc7.h \
+ ../include/instance/tcc0.h ../include/instance/tcc1.h \
+ ../include/instance/tcc2.h ../include/instance/tcc3.h \
+ ../include/instance/tcc4.h ../include/instance/trng.h \
+ ../include/instance/usb.h ../include/instance/wdt.h \
+ ../include/pio/same54p20a.h ../hri/hri_e54.h ../include/sam.h \
+ ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \
+ ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \
+ ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \
+ ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \
+ ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \
+ ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \
+ ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \
+ ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \
+ ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \
+ ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \
+ ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \
+ ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \
+ ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \
+ ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \
+ ../hal/utils/include/err_codes.h ../hpl/port/hpl_gpio_base.h \
+ ../hal/utils/include/utils_assert.h ../config/hpl_port_config.h \
+ ../hal/include/hal_delay.h ../hal/include/hpl_irq.h \
+ ../hal/include/hpl_reset.h ../hal/include/hpl_sleep.h \
+ ../hal/include/hal_init.h ../hal/include/hpl_init.h \
+ ../hal/include/hal_io.h ../hal/include/hal_sleep.h \
+ ../hal/include/hal_calendar.h ../hal/include/hpl_calendar.h \
+ ../hal/utils/include/utils_list.h ../hal/include/hpl_irq.h \
+ ../hal/include/hal_usart_sync.h ../hal/include/hal_io.h \
+ ../hal/include/hpl_usart_sync.h ../hal/include/hpl_usart.h \
+ ../hal/include/hal_spi_m_sync.h ../hal/include/hpl_spi_m_sync.h \
+ ../hal/include/hpl_spi.h ../hal/utils/include/utils.h \
+ ../hal/include/hpl_spi_sync.h ../hal/include/hal_mci_sync.h \
+ ../hal/include/hpl_mci_sync.h ../sd_mmc_start.h \
+ /usr/arm-none-eabi/include/stdio.h /usr/arm-none-eabi/include/_ansi.h \
+ /usr/arm-none-eabi/include/newlib.h \
+ /usr/arm-none-eabi/include/sys/config.h \
+ /usr/arm-none-eabi/include/machine/ieeefp.h \
+ /usr/arm-none-eabi/include/sys/cdefs.h \
+ /usr/lib/gcc/arm-none-eabi/10.2.0/include/stdarg.h \
+ /usr/arm-none-eabi/include/sys/reent.h \
+ /usr/arm-none-eabi/include/_ansi.h \
+ /usr/arm-none-eabi/include/sys/_types.h \
+ /usr/arm-none-eabi/include/machine/_types.h \
+ /usr/arm-none-eabi/include/sys/lock.h \
+ /usr/arm-none-eabi/include/sys/types.h \
+ /usr/arm-none-eabi/include/machine/endian.h \
+ /usr/arm-none-eabi/include/machine/_endian.h \
+ /usr/arm-none-eabi/include/sys/select.h \
+ /usr/arm-none-eabi/include/sys/_sigset.h \
+ /usr/arm-none-eabi/include/sys/_timeval.h \
+ /usr/arm-none-eabi/include/sys/timespec.h \
+ /usr/arm-none-eabi/include/sys/_timespec.h \
+ /usr/arm-none-eabi/include/sys/_pthreadtypes.h \
+ /usr/arm-none-eabi/include/sys/sched.h \
+ /usr/arm-none-eabi/include/machine/types.h \
+ /usr/arm-none-eabi/include/sys/stdio.h ../diskio_start.h \
+ ../driver_init.h /usr/arm-none-eabi/include/string.h \
+ /usr/arm-none-eabi/include/sys/_locale.h \
+ /usr/arm-none-eabi/include/strings.h \
+ /usr/arm-none-eabi/include/sys/string.h
+../shared/util/pdebug.h:
+../atmel_start.h:
+../driver_init.h:
+../atmel_start_pins.h:
+../hal/include/hal_gpio.h:
+../hal/include/hpl_gpio.h:
+../hal/utils/include/compiler.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdint.h:
+/usr/arm-none-eabi/include/stdint.h:
+/usr/arm-none-eabi/include/machine/_default_types.h:
+/usr/arm-none-eabi/include/sys/features.h:
+/usr/arm-none-eabi/include/_newlib_version.h:
+/usr/arm-none-eabi/include/sys/_intsup.h:
+/usr/arm-none-eabi/include/sys/_stdint.h:
+/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdbool.h:
+../hal/utils/include/parts.h:
+../include/same54.h:
+../include/same54p20a.h:
+../CMSIS/Core/Include/core_cm4.h:
+../CMSIS/Core/Include/cmsis_version.h:
+../CMSIS/Core/Include/cmsis_compiler.h:
+../CMSIS/Core/Include/cmsis_gcc.h:
+../CMSIS/Core/Include/mpu_armv7.h:
+../include/system_same54.h:
+../include/component/ac.h:
+../include/component/adc.h:
+../include/component/aes.h:
+../include/component/can.h:
+../include/component/ccl.h:
+../include/component/cmcc.h:
+../include/component/dac.h:
+../include/component/dmac.h:
+../include/component/dsu.h:
+../include/component/eic.h:
+../include/component/evsys.h:
+../include/component/freqm.h:
+../include/component/gclk.h:
+../include/component/gmac.h:
+../include/component/hmatrixb.h:
+../include/component/icm.h:
+../include/component/i2s.h:
+../include/component/mclk.h:
+../include/component/nvmctrl.h:
+../include/component/oscctrl.h:
+../include/component/osc32kctrl.h:
+../include/component/pac.h:
+../include/component/pcc.h:
+../include/component/pdec.h:
+../include/component/pm.h:
+../include/component/port.h:
+../include/component/qspi.h:
+../include/component/ramecc.h:
+../include/component/rstc.h:
+../include/component/rtc.h:
+../include/component/sdhc.h:
+../include/component/sercom.h:
+../include/component/supc.h:
+../include/component/tc.h:
+../include/component/tcc.h:
+../include/component/trng.h:
+../include/component/usb.h:
+../include/component/wdt.h:
+../include/instance/ac.h:
+../include/instance/adc0.h:
+../include/instance/adc1.h:
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+../include/instance/can0.h:
+../include/instance/can1.h:
+../include/instance/ccl.h:
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+../include/instance/dac.h:
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+../include/instance/dsu.h:
+../include/instance/eic.h:
+../include/instance/evsys.h:
+../include/instance/freqm.h:
+../include/instance/gclk.h:
+../include/instance/gmac.h:
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+../include/instance/icm.h:
+../include/instance/i2s.h:
+../include/instance/mclk.h:
+../include/instance/nvmctrl.h:
+../include/instance/oscctrl.h:
+../include/instance/osc32kctrl.h:
+../include/instance/pac.h:
+../include/instance/pcc.h:
+../include/instance/pdec.h:
+../include/instance/pm.h:
+../include/instance/port.h:
+../include/instance/pukcc.h:
+../include/instance/qspi.h:
+../include/instance/ramecc.h:
+../include/instance/rstc.h:
+../include/instance/rtc.h:
+../include/instance/sdhc0.h:
+../include/instance/sdhc1.h:
+../include/instance/sercom0.h:
+../include/instance/sercom1.h:
+../include/instance/sercom2.h:
+../include/instance/sercom3.h:
+../include/instance/sercom4.h:
+../include/instance/sercom5.h:
+../include/instance/sercom6.h:
+../include/instance/sercom7.h:
+../include/instance/supc.h:
+../include/instance/tc0.h:
+../include/instance/tc1.h:
+../include/instance/tc2.h:
+../include/instance/tc3.h:
+../include/instance/tc4.h:
+../include/instance/tc5.h:
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+../include/instance/tc7.h:
+../include/instance/tcc0.h:
+../include/instance/tcc1.h:
+../include/instance/tcc2.h:
+../include/instance/tcc3.h:
+../include/instance/tcc4.h:
+../include/instance/trng.h:
+../include/instance/usb.h:
+../include/instance/wdt.h:
+../include/pio/same54p20a.h:
+../hri/hri_e54.h:
+../include/sam.h:
+../hri/hri_ac_e54.h:
+../hal/include/hal_atomic.h:
+../hri/hri_adc_e54.h:
+../hri/hri_aes_e54.h:
+../hri/hri_can_e54.h:
+../hri/hri_ccl_e54.h:
+../hri/hri_cmcc_e54.h:
+../hri/hri_dac_e54.h:
+../hri/hri_dmac_e54.h:
+../hri/hri_dsu_e54.h:
+../hri/hri_eic_e54.h:
+../hri/hri_evsys_e54.h:
+../hri/hri_freqm_e54.h:
+../hri/hri_gclk_e54.h:
+../hri/hri_gmac_e54.h:
+../hri/hri_hmatrixb_e54.h:
+../hri/hri_i2s_e54.h:
+../hri/hri_icm_e54.h:
+../hri/hri_mclk_e54.h:
+../hri/hri_nvmctrl_e54.h:
+../hri/hri_osc32kctrl_e54.h:
+../hri/hri_oscctrl_e54.h:
+../hri/hri_pac_e54.h:
+../hri/hri_pcc_e54.h:
+../hri/hri_pdec_e54.h:
+../hri/hri_pm_e54.h:
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+../hri/hri_ramecc_e54.h:
+../hri/hri_rstc_e54.h:
+../hri/hri_rtc_e54.h:
+../hri/hri_sdhc_e54.h:
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+../hri/hri_usb_e54.h:
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+../hal/utils/include/err_codes.h:
+../hpl/port/hpl_gpio_base.h:
+../hal/utils/include/utils_assert.h:
+../config/hpl_port_config.h:
+../hal/include/hal_delay.h:
+../hal/include/hpl_irq.h:
+../hal/include/hpl_reset.h:
+../hal/include/hpl_sleep.h:
+../hal/include/hal_init.h:
+../hal/include/hpl_init.h:
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+../hal/include/hal_calendar.h:
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+../hal/include/hpl_spi.h:
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+../hal/include/hpl_spi_sync.h:
+../hal/include/hal_mci_sync.h:
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diff --git a/build/shared/util/pdebug.o b/build/shared/util/pdebug.o
new file mode 100644
index 0000000..6e887b3
Binary files /dev/null and b/build/shared/util/pdebug.o differ
diff --git a/build/spi_sd_mmc_lib.bin b/build/spi_sd_mmc_lib.bin
new file mode 100644
index 0000000..e9fd0f8
Binary files /dev/null and b/build/spi_sd_mmc_lib.bin differ
diff --git a/build/spi_sd_mmc_lib.eep b/build/spi_sd_mmc_lib.eep
new file mode 100644
index 0000000..e69de29
diff --git a/build/spi_sd_mmc_lib.elf b/build/spi_sd_mmc_lib.elf
new file mode 100644
index 0000000..f8cf66d
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diff --git a/build/spi_sd_mmc_lib.hex b/build/spi_sd_mmc_lib.hex
new file mode 100644
index 0000000..27b905c
--- /dev/null
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diff --git a/build/spi_sd_mmc_lib.lss b/build/spi_sd_mmc_lib.lss
new file mode 100644
index 0000000..fbef162
--- /dev/null
+++ b/build/spi_sd_mmc_lib.lss
@@ -0,0 +1,6831 @@
+
+spi_sd_mmc_lib.elf:     file format elf32-littlearm
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 .text         000031c0  00000000  00000000  00010000  2**4
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 .relocate     0000006c  20000000  000031c0  00020000  2**2
+                  CONTENTS, ALLOC, LOAD, DATA
+  2 .bkupram      00000000  47000000  47000000  0002006c  2**0
+                  CONTENTS
+  3 .qspi         00000000  04000000  04000000  0002006c  2**0
+                  CONTENTS
+  4 .bss          000002fc  20000070  00003230  0002006c  2**3
+                  ALLOC
+  5 .stack        00010004  2000036c  0000352c  0002006c  2**0
+                  ALLOC
+  6 .ARM.attributes 0000002e  00000000  00000000  0002006c  2**0
+                  CONTENTS, READONLY
+  7 .comment      0000001e  00000000  00000000  0002009a  2**0
+                  CONTENTS, READONLY
+  8 .debug_info   0002b3e2  00000000  00000000  000200b8  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+  9 .debug_abbrev 00004153  00000000  00000000  0004b49a  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 10 .debug_loc    0000d96f  00000000  00000000  0004f5ed  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 11 .debug_aranges 00000e48  00000000  00000000  0005cf5c  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 12 .debug_ranges 00001f20  00000000  00000000  0005dda4  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 13 .debug_macro  0003942f  00000000  00000000  0005fcc4  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 14 .debug_line   0001be9e  00000000  00000000  000990f3  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 15 .debug_str    00126de5  00000000  00000000  000b4f91  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 16 .debug_frame  00002d24  00000000  00000000  001dbd78  2**2
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+
+Disassembly of section .text:
+
+00000000 <exception_table>:
+ * \brief Delay loop to delay n number of cycles
+ */
+void _delay_cycles(void *const hw, uint32_t cycles)
+{
+	(void)hw;
+	uint8_t  n   = cycles >> 24;
+       0:	70 03 01 20 55 18 00 00 53 18 00 00 53 18 00 00     p.. U...S...S...
+	uint32_t buf = cycles;
+
+	while (n--) {
+      10:	53 18 00 00 53 18 00 00 53 18 00 00 00 00 00 00     S...S...S.......
+	...
+		SysTick->LOAD = 0xFFFFFF;
+      2c:	53 18 00 00 53 18 00 00 00 00 00 00 53 18 00 00     S...S.......S...
+      3c:	53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00     S...S...S...S...
+      4c:	53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00     S...S...S...S...
+      5c:	53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00     S...S...S...S...
+      6c:	b5 19 00 00 53 18 00 00 53 18 00 00 53 18 00 00     ....S...S...S...
+      7c:	53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00     S...S...S...S...
+      8c:	53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00     S...S...S...S...
+      9c:	53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00     S...S...S...S...
+      ac:	53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00     S...S...S...S...
+      bc:	53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00     S...S...S...S...
+      cc:	53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00     S...S...S...S...
+      dc:	53 18 00 00 53 18 00 00 53 18 00 00 00 00 00 00     S...S...S.......
+	...
+      f4:	19 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00     ....S...S...S...
+     104:	53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00     S...S...S...S...
+     114:	53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00     S...S...S...S...
+     124:	53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00     S...S...S...S...
+     134:	53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00     S...S...S...S...
+     144:	53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00     S...S...S...S...
+     154:	53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00     S...S...S...S...
+     164:	53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00     S...S...S...S...
+     174:	53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00     S...S...S...S...
+     184:	53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00     S...S...S...S...
+     194:	53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00     S...S...S...S...
+     1a4:	53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00     S...S...S...S...
+     1b4:	53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00     S...S...S...S...
+     1c4:	53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00     S...S...S...S...
+     1d4:	53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00     S...S...S...S...
+     1e4:	53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00     S...S...S...S...
+     1f4:	53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00     S...S...S...S...
+     204:	53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00     S...S...S...S...
+     214:	53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00     S...S...S...S...
+     224:	53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00     S...S...S...S...
+     234:	53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00     S...S...S...S...
+     244:	53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00     S...S...S...S...
+     254:	53 18 00 00 53 18 00 00 53 18 00 00 53 18 00 00     S...S...S...S...
+
+00000264 <__do_global_dtors_aux>:
+     264:	b510      	push	{r4, lr}
+     266:	4c05      	ldr	r4, [pc, #20]	; (27c <__do_global_dtors_aux+0x18>)
+     268:	7823      	ldrb	r3, [r4, #0]
+     26a:	b933      	cbnz	r3, 27a <__do_global_dtors_aux+0x16>
+     26c:	4b04      	ldr	r3, [pc, #16]	; (280 <__do_global_dtors_aux+0x1c>)
+     26e:	b113      	cbz	r3, 276 <__do_global_dtors_aux+0x12>
+     270:	4804      	ldr	r0, [pc, #16]	; (284 <__do_global_dtors_aux+0x20>)
+     272:	f3af 8000 	nop.w
+     276:	2301      	movs	r3, #1
+     278:	7023      	strb	r3, [r4, #0]
+     27a:	bd10      	pop	{r4, pc}
+     27c:	20000070 	.word	0x20000070
+     280:	00000000 	.word	0x00000000
+     284:	000031c0 	.word	0x000031c0
+
+00000288 <frame_dummy>:
+     288:	b508      	push	{r3, lr}
+     28a:	4b03      	ldr	r3, [pc, #12]	; (298 <frame_dummy+0x10>)
+     28c:	b11b      	cbz	r3, 296 <frame_dummy+0xe>
+     28e:	4903      	ldr	r1, [pc, #12]	; (29c <frame_dummy+0x14>)
+     290:	4803      	ldr	r0, [pc, #12]	; (2a0 <frame_dummy+0x18>)
+     292:	f3af 8000 	nop.w
+     296:	bd08      	pop	{r3, pc}
+     298:	00000000 	.word	0x00000000
+     29c:	20000074 	.word	0x20000074
+     2a0:	000031c0 	.word	0x000031c0
+
+000002a4 <io_write>:
+
+/**
+ * \brief I/O write interface
+ */
+int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length)
+{
+     2a4:	b570      	push	{r4, r5, r6, lr}
+     2a6:	460d      	mov	r5, r1
+     2a8:	4616      	mov	r6, r2
+	ASSERT(io_descr && buf);
+     2aa:	4604      	mov	r4, r0
+     2ac:	b110      	cbz	r0, 2b4 <io_write+0x10>
+     2ae:	1e08      	subs	r0, r1, #0
+     2b0:	bf18      	it	ne
+     2b2:	2001      	movne	r0, #1
+     2b4:	4905      	ldr	r1, [pc, #20]	; (2cc <io_write+0x28>)
+     2b6:	4b06      	ldr	r3, [pc, #24]	; (2d0 <io_write+0x2c>)
+     2b8:	2234      	movs	r2, #52	; 0x34
+     2ba:	4798      	blx	r3
+	return io_descr->write(io_descr, buf, length);
+     2bc:	6823      	ldr	r3, [r4, #0]
+     2be:	4632      	mov	r2, r6
+     2c0:	4629      	mov	r1, r5
+     2c2:	4620      	mov	r0, r4
+}
+     2c4:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
+	return io_descr->write(io_descr, buf, length);
+     2c8:	4718      	bx	r3
+     2ca:	bf00      	nop
+     2cc:	00002ae4 	.word	0x00002ae4
+     2d0:	00001605 	.word	0x00001605
+
+000002d4 <io_read>:
+
+/**
+ * \brief I/O read interface
+ */
+int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length)
+{
+     2d4:	b570      	push	{r4, r5, r6, lr}
+     2d6:	460d      	mov	r5, r1
+     2d8:	4616      	mov	r6, r2
+	ASSERT(io_descr && buf);
+     2da:	4604      	mov	r4, r0
+     2dc:	b110      	cbz	r0, 2e4 <io_read+0x10>
+     2de:	1e08      	subs	r0, r1, #0
+     2e0:	bf18      	it	ne
+     2e2:	2001      	movne	r0, #1
+     2e4:	4905      	ldr	r1, [pc, #20]	; (2fc <io_read+0x28>)
+     2e6:	4b06      	ldr	r3, [pc, #24]	; (300 <io_read+0x2c>)
+     2e8:	223d      	movs	r2, #61	; 0x3d
+     2ea:	4798      	blx	r3
+	return io_descr->read(io_descr, buf, length);
+     2ec:	6863      	ldr	r3, [r4, #4]
+     2ee:	4632      	mov	r2, r6
+     2f0:	4629      	mov	r1, r5
+     2f2:	4620      	mov	r0, r4
+}
+     2f4:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
+	return io_descr->read(io_descr, buf, length);
+     2f8:	4718      	bx	r3
+     2fa:	bf00      	nop
+     2fc:	00002ae4 	.word	0x00002ae4
+     300:	00001605 	.word	0x00001605
+
+00000304 <_delay_init>:
+     304:	f04f 23e0 	mov.w	r3, #3758153728	; 0xe000e000
+     308:	f06f 427f 	mvn.w	r2, #4278190080	; 0xff000000
+     30c:	615a      	str	r2, [r3, #20]
+     30e:	2205      	movs	r2, #5
+     310:	611a      	str	r2, [r3, #16]
+     312:	4770      	bx	lr
+
+00000314 <calendar_init>:
+}
+
+/** \brief Initialize Calendar
+ */
+int32_t calendar_init(struct calendar_descriptor *const calendar, const void *hw)
+{
+     314:	b538      	push	{r3, r4, r5, lr}
+	int32_t ret = 0;
+
+	/* Sanity check arguments */
+	ASSERT(calendar);
+     316:	4604      	mov	r4, r0
+     318:	3800      	subs	r0, #0
+     31a:	4b0c      	ldr	r3, [pc, #48]	; (34c <calendar_init+0x38>)
+{
+     31c:	460d      	mov	r5, r1
+	ASSERT(calendar);
+     31e:	bf18      	it	ne
+     320:	2001      	movne	r0, #1
+     322:	490b      	ldr	r1, [pc, #44]	; (350 <calendar_init+0x3c>)
+     324:	f44f 72e0 	mov.w	r2, #448	; 0x1c0
+     328:	4798      	blx	r3
+
+	if (calendar->device.hw == hw) {
+     32a:	6823      	ldr	r3, [r4, #0]
+     32c:	42ab      	cmp	r3, r5
+     32e:	d008      	beq.n	342 <calendar_init+0x2e>
+		/* Already initialized with current configuration */
+		return ERR_NONE;
+	} else if (calendar->device.hw != NULL) {
+     330:	b94b      	cbnz	r3, 346 <calendar_init+0x32>
+		/* Initialized with another configuration */
+		return ERR_ALREADY_INITIALIZED;
+	}
+	calendar->device.hw = (void *)hw;
+	ret                 = _calendar_init(&calendar->device);
+     332:	4b08      	ldr	r3, [pc, #32]	; (354 <calendar_init+0x40>)
+	calendar->device.hw = (void *)hw;
+     334:	6025      	str	r5, [r4, #0]
+	ret                 = _calendar_init(&calendar->device);
+     336:	4620      	mov	r0, r4
+     338:	4798      	blx	r3
+	calendar->base_year = DEFAULT_BASE_YEAR;
+     33a:	f240 73b2 	movw	r3, #1970	; 0x7b2
+     33e:	61a3      	str	r3, [r4, #24]
+
+	return ret;
+}
+     340:	bd38      	pop	{r3, r4, r5, pc}
+		return ERR_NONE;
+     342:	2000      	movs	r0, #0
+     344:	e7fc      	b.n	340 <calendar_init+0x2c>
+		return ERR_ALREADY_INITIALIZED;
+     346:	f06f 0011 	mvn.w	r0, #17
+     34a:	e7f9      	b.n	340 <calendar_init+0x2c>
+     34c:	00001605 	.word	0x00001605
+     350:	00002af8 	.word	0x00002af8
+     354:	00001939 	.word	0x00001939
+
+00000358 <SDMMC_example>:
+
+/*
+ * Example
+ */
+void SDMMC_example(void)
+{
+     358:	b537      	push	{r0, r1, r2, r4, r5, lr}
+	while (SD_MMC_OK != sd_mmc_check(0)) {
+     35a:	4d13      	ldr	r5, [pc, #76]	; (3a8 <SDMMC_example+0x50>)
+     35c:	2000      	movs	r0, #0
+     35e:	47a8      	blx	r5
+     360:	4604      	mov	r4, r0
+     362:	2800      	cmp	r0, #0
+     364:	d1fa      	bne.n	35c <SDMMC_example+0x4>
+		/* Wait card ready. */
+	}
+	if (sd_mmc_get_type(0) & (CARD_TYPE_SD | CARD_TYPE_MMC)) {
+     366:	4d11      	ldr	r5, [pc, #68]	; (3ac <SDMMC_example+0x54>)
+     368:	47a8      	blx	r5
+     36a:	0782      	lsls	r2, r0, #30
+     36c:	d00b      	beq.n	386 <SDMMC_example+0x2e>
+		/* Read card block 0 */
+		sd_mmc_init_read_blocks(0, 0, 1);
+     36e:	4b10      	ldr	r3, [pc, #64]	; (3b0 <SDMMC_example+0x58>)
+     370:	2201      	movs	r2, #1
+     372:	4621      	mov	r1, r4
+     374:	4620      	mov	r0, r4
+     376:	4798      	blx	r3
+		sd_mmc_start_read_blocks(sd_mmc_block, 1);
+     378:	4b0e      	ldr	r3, [pc, #56]	; (3b4 <SDMMC_example+0x5c>)
+     37a:	480f      	ldr	r0, [pc, #60]	; (3b8 <SDMMC_example+0x60>)
+     37c:	2101      	movs	r1, #1
+     37e:	4798      	blx	r3
+		sd_mmc_wait_end_of_read_blocks(false);
+     380:	4b0e      	ldr	r3, [pc, #56]	; (3bc <SDMMC_example+0x64>)
+     382:	4620      	mov	r0, r4
+     384:	4798      	blx	r3
+	}
+#if (CONF_SDIO_SUPPORT == 1)
+	if (sd_mmc_get_type(0) & CARD_TYPE_SDIO) {
+     386:	2000      	movs	r0, #0
+     388:	47a8      	blx	r5
+     38a:	0743      	lsls	r3, r0, #29
+     38c:	d509      	bpl.n	3a2 <SDMMC_example+0x4a>
+		/* Read 22 bytes from SDIO Function 0 (CIA) */
+		sdio_read_extended(0, 0, 0, 1, sd_mmc_block, 22);
+     38e:	2316      	movs	r3, #22
+     390:	2200      	movs	r2, #0
+     392:	9301      	str	r3, [sp, #4]
+     394:	4b08      	ldr	r3, [pc, #32]	; (3b8 <SDMMC_example+0x60>)
+     396:	9300      	str	r3, [sp, #0]
+     398:	4c09      	ldr	r4, [pc, #36]	; (3c0 <SDMMC_example+0x68>)
+     39a:	2301      	movs	r3, #1
+     39c:	4611      	mov	r1, r2
+     39e:	4610      	mov	r0, r2
+     3a0:	47a0      	blx	r4
+	}
+#endif
+}
+     3a2:	b003      	add	sp, #12
+     3a4:	bd30      	pop	{r4, r5, pc}
+     3a6:	bf00      	nop
+     3a8:	00000721 	.word	0x00000721
+     3ac:	00000d09 	.word	0x00000d09
+     3b0:	00000d2d 	.word	0x00000d2d
+     3b4:	00000db1 	.word	0x00000db1
+     3b8:	2000008c 	.word	0x2000008c
+     3bc:	00000e01 	.word	0x00000e01
+     3c0:	00000e5d 	.word	0x00000e5d
+
+000003c4 <sd_mmc_stack_init>:
+
+void sd_mmc_stack_init(void)
+{
+
+	sd_mmc_init(&SPI_SD_MMC, SDMMC_cd, SDMMC_wp);
+     3c4:	4a02      	ldr	r2, [pc, #8]	; (3d0 <sd_mmc_stack_init+0xc>)
+     3c6:	4803      	ldr	r0, [pc, #12]	; (3d4 <sd_mmc_stack_init+0x10>)
+     3c8:	4b03      	ldr	r3, [pc, #12]	; (3d8 <sd_mmc_stack_init+0x14>)
+     3ca:	1d11      	adds	r1, r2, #4
+     3cc:	4718      	bx	r3
+     3ce:	bf00      	nop
+     3d0:	20000000 	.word	0x20000000
+     3d4:	2000031c 	.word	0x2000031c
+     3d8:	00000709 	.word	0x00000709
+
+000003dc <_sbrk>:
+extern caddr_t _sbrk(int incr)
+{
+	static unsigned char *heap = NULL;
+	unsigned char *       prev_heap;
+
+	if (heap == NULL) {
+     3dc:	4a04      	ldr	r2, [pc, #16]	; (3f0 <_sbrk+0x14>)
+     3de:	6811      	ldr	r1, [r2, #0]
+{
+     3e0:	4603      	mov	r3, r0
+	if (heap == NULL) {
+     3e2:	b909      	cbnz	r1, 3e8 <_sbrk+0xc>
+		heap = (unsigned char *)&_end;
+     3e4:	4903      	ldr	r1, [pc, #12]	; (3f4 <_sbrk+0x18>)
+     3e6:	6011      	str	r1, [r2, #0]
+	}
+	prev_heap = heap;
+     3e8:	6810      	ldr	r0, [r2, #0]
+
+	heap += incr;
+     3ea:	4403      	add	r3, r0
+     3ec:	6013      	str	r3, [r2, #0]
+
+	return (caddr_t)prev_heap;
+}
+     3ee:	4770      	bx	lr
+     3f0:	2000028c 	.word	0x2000028c
+     3f4:	20010370 	.word	0x20010370
+
+000003f8 <SDMMC_UNSTUFF_BITS>:
+ * Used by : CSD, SCR, Switch status
+ */
+static inline uint32_t SDMMC_UNSTUFF_BITS(uint8_t *reg, uint16_t reg_size, uint16_t pos, uint8_t size)
+{
+	uint32_t value;
+	value = reg[((reg_size - pos + 7) / 8) - 1] >> (pos % 8);
+     3f8:	1a89      	subs	r1, r1, r2
+{
+     3fa:	b570      	push	{r4, r5, r6, lr}
+	value = reg[((reg_size - pos + 7) / 8) - 1] >> (pos % 8);
+     3fc:	1dcc      	adds	r4, r1, #7
+     3fe:	bf48      	it	mi
+     400:	f101 040e 	addmi.w	r4, r1, #14
+     404:	eb00 00e4 	add.w	r0, r0, r4, asr #3
+     408:	f002 0207 	and.w	r2, r2, #7
+     40c:	f810 1c01 	ldrb.w	r1, [r0, #-1]
+	if (((pos % 8) + size) > 8) {
+     410:	18d4      	adds	r4, r2, r3
+     412:	2c08      	cmp	r4, #8
+	value = reg[((reg_size - pos + 7) / 8) - 1] >> (pos % 8);
+     414:	fa41 f102 	asr.w	r1, r1, r2
+	if (((pos % 8) + size) > 8) {
+     418:	dd18      	ble.n	44c <SDMMC_UNSTUFF_BITS+0x54>
+		value |= (uint32_t)reg[((reg_size - pos + 7) / 8) - 2] << (8 - (pos % 8));
+     41a:	f810 5c02 	ldrb.w	r5, [r0, #-2]
+     41e:	f1c2 0608 	rsb	r6, r2, #8
+     422:	40b5      	lsls	r5, r6
+	}
+	if (((pos % 8) + size) > 16) {
+     424:	2c10      	cmp	r4, #16
+		value |= (uint32_t)reg[((reg_size - pos + 7) / 8) - 2] << (8 - (pos % 8));
+     426:	ea41 0105 	orr.w	r1, r1, r5
+	if (((pos % 8) + size) > 16) {
+     42a:	dd0f      	ble.n	44c <SDMMC_UNSTUFF_BITS+0x54>
+		value |= (uint32_t)reg[((reg_size - pos + 7) / 8) - 3] << (16 - (pos % 8));
+     42c:	f810 0c03 	ldrb.w	r0, [r0, #-3]
+     430:	f1c2 0510 	rsb	r5, r2, #16
+	}
+	if (((pos % 8) + size) > 24) {
+     434:	2c18      	cmp	r4, #24
+		value |= (uint32_t)reg[((reg_size - pos + 7) / 8) - 3] << (24 - (pos % 8));
+     436:	bfc8      	it	gt
+     438:	f1c2 0218 	rsbgt	r2, r2, #24
+		value |= (uint32_t)reg[((reg_size - pos + 7) / 8) - 3] << (16 - (pos % 8));
+     43c:	fa00 f505 	lsl.w	r5, r0, r5
+     440:	ea41 0105 	orr.w	r1, r1, r5
+		value |= (uint32_t)reg[((reg_size - pos + 7) / 8) - 3] << (24 - (pos % 8));
+     444:	bfc4      	itt	gt
+     446:	fa00 f202 	lslgt.w	r2, r0, r2
+     44a:	4311      	orrgt	r1, r2
+	}
+	value &= ((uint32_t)1 << size) - 1;
+     44c:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
+     450:	4098      	lsls	r0, r3
+	return value;
+}
+     452:	ea21 0000 	bic.w	r0, r1, r0
+     456:	bd70      	pop	{r4, r5, r6, pc}
+
+00000458 <gpio_get_pin_level>:
+ * Reads the level on pins connected to a port
+ *
+ * \param[in] pin       The pin number for device
+ */
+static inline bool gpio_get_pin_level(const uint8_t pin)
+{
+     458:	b537      	push	{r0, r1, r2, r4, r5, lr}
+ */
+static inline uint32_t _gpio_get_level(const enum gpio_port port)
+{
+	uint32_t tmp;
+
+	CRITICAL_SECTION_ENTER();
+     45a:	4b0e      	ldr	r3, [pc, #56]	; (494 <gpio_get_pin_level+0x3c>)
+     45c:	4605      	mov	r5, r0
+     45e:	a801      	add	r0, sp, #4
+     460:	4798      	blx	r3
+	return tmp;
+}
+
+static inline hri_port_dir_reg_t hri_port_read_DIR_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Port *)hw)->Group[submodule_index].DIR.reg;
+     462:	4a0d      	ldr	r2, [pc, #52]	; (498 <gpio_get_pin_level+0x40>)
+     464:	096b      	lsrs	r3, r5, #5
+     466:	01d9      	lsls	r1, r3, #7
+     468:	eb02 13c3 	add.w	r3, r2, r3, lsl #7
+     46c:	5851      	ldr	r1, [r2, r1]
+	return tmp;
+}
+
+static inline hri_port_in_reg_t hri_port_read_IN_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Port *)hw)->Group[submodule_index].IN.reg;
+     46e:	6a1a      	ldr	r2, [r3, #32]
+	return ((Port *)hw)->Group[submodule_index].OUT.reg;
+     470:	691c      	ldr	r4, [r3, #16]
+	uint32_t dir_tmp = hri_port_read_DIR_reg(PORT, port);
+
+	tmp = hri_port_read_IN_reg(PORT, port) & ~dir_tmp;
+	tmp |= hri_port_read_OUT_reg(PORT, port) & dir_tmp;
+
+	CRITICAL_SECTION_LEAVE();
+     472:	4b0a      	ldr	r3, [pc, #40]	; (49c <gpio_get_pin_level+0x44>)
+	tmp |= hri_port_read_OUT_reg(PORT, port) & dir_tmp;
+     474:	4054      	eors	r4, r2
+     476:	400c      	ands	r4, r1
+	CRITICAL_SECTION_LEAVE();
+     478:	a801      	add	r0, sp, #4
+	tmp |= hri_port_read_OUT_reg(PORT, port) & dir_tmp;
+     47a:	4054      	eors	r4, r2
+	return (bool)(_gpio_get_level((enum gpio_port)GPIO_PORT(pin)) & (0x01U << GPIO_PIN(pin)));
+     47c:	f005 051f 	and.w	r5, r5, #31
+	CRITICAL_SECTION_LEAVE();
+     480:	4798      	blx	r3
+     482:	2001      	movs	r0, #1
+     484:	fa00 f505 	lsl.w	r5, r0, r5
+     488:	4225      	tst	r5, r4
+}
+     48a:	bf08      	it	eq
+     48c:	2000      	moveq	r0, #0
+     48e:	b003      	add	sp, #12
+     490:	bd30      	pop	{r4, r5, pc}
+     492:	bf00      	nop
+     494:	00002099 	.word	0x00002099
+     498:	41008000 	.word	0x41008000
+     49c:	000020a7 	.word	0x000020a7
+
+000004a0 <sd_mmc_configure_slot>:
+
+/**
+ * \brief Configures the driver with the selected card configuration
+ */
+static void sd_mmc_configure_slot(void)
+{
+     4a0:	b513      	push	{r0, r1, r4, lr}
+	driver_select_device(
+	    sd_mmc_hal, sd_mmc_slot_sel, sd_mmc_card->clock, sd_mmc_card->bus_width, sd_mmc_card->high_speed);
+     4a2:	4807      	ldr	r0, [pc, #28]	; (4c0 <sd_mmc_configure_slot+0x20>)
+	driver_select_device(
+     4a4:	4c07      	ldr	r4, [pc, #28]	; (4c4 <sd_mmc_configure_slot+0x24>)
+	    sd_mmc_hal, sd_mmc_slot_sel, sd_mmc_card->clock, sd_mmc_card->bus_width, sd_mmc_card->high_speed);
+     4a6:	6802      	ldr	r2, [r0, #0]
+	driver_select_device(
+     4a8:	7f91      	ldrb	r1, [r2, #30]
+     4aa:	7b53      	ldrb	r3, [r2, #13]
+     4ac:	3900      	subs	r1, #0
+     4ae:	bf18      	it	ne
+     4b0:	2101      	movne	r1, #1
+     4b2:	9100      	str	r1, [sp, #0]
+     4b4:	7901      	ldrb	r1, [r0, #4]
+     4b6:	6812      	ldr	r2, [r2, #0]
+     4b8:	6880      	ldr	r0, [r0, #8]
+     4ba:	47a0      	blx	r4
+}
+     4bc:	b002      	add	sp, #8
+     4be:	bd10      	pop	{r4, pc}
+     4c0:	20000290 	.word	0x20000290
+     4c4:	000013f9 	.word	0x000013f9
+
+000004c8 <sd_mmc_select_slot>:
+{
+     4c8:	b538      	push	{r3, r4, r5, lr}
+	if (slot >= CONF_SD_MMC_MEM_CNT) {
+     4ca:	2800      	cmp	r0, #0
+     4cc:	d143      	bne.n	556 <sd_mmc_select_slot+0x8e>
+	if (_cd && _cd[slot].pin != -1) {
+     4ce:	4c23      	ldr	r4, [pc, #140]	; (55c <sd_mmc_select_slot+0x94>)
+     4d0:	68e3      	ldr	r3, [r4, #12]
+     4d2:	2b00      	cmp	r3, #0
+     4d4:	d038      	beq.n	548 <sd_mmc_select_slot+0x80>
+     4d6:	f9b3 0000 	ldrsh.w	r0, [r3]
+     4da:	1c42      	adds	r2, r0, #1
+     4dc:	d034      	beq.n	548 <sd_mmc_select_slot+0x80>
+		if (gpio_get_pin_level(_cd[slot].pin) != _cd[slot].val) {
+     4de:	4b20      	ldr	r3, [pc, #128]	; (560 <sd_mmc_select_slot+0x98>)
+     4e0:	b2c0      	uxtb	r0, r0
+     4e2:	4798      	blx	r3
+     4e4:	68e3      	ldr	r3, [r4, #12]
+     4e6:	885b      	ldrh	r3, [r3, #2]
+     4e8:	4298      	cmp	r0, r3
+     4ea:	d003      	beq.n	4f4 <sd_mmc_select_slot+0x2c>
+			sd_mmc_cards[slot].state = SD_MMC_CARD_STATE_NO_CARD;
+     4ec:	2304      	movs	r3, #4
+			sd_mmc_cards[slot].state = SD_MMC_CARD_STATE_DEBOUNCE;
+     4ee:	76a3      	strb	r3, [r4, #26]
+			return SD_MMC_ERR_NO_CARD;
+     4f0:	2002      	movs	r0, #2
+}
+     4f2:	bd38      	pop	{r3, r4, r5, pc}
+		if (sd_mmc_cards[slot].state == SD_MMC_CARD_STATE_NO_CARD) {
+     4f4:	7ea0      	ldrb	r0, [r4, #26]
+     4f6:	2804      	cmp	r0, #4
+     4f8:	d101      	bne.n	4fe <sd_mmc_select_slot+0x36>
+			sd_mmc_cards[slot].state = SD_MMC_CARD_STATE_DEBOUNCE;
+     4fa:	2301      	movs	r3, #1
+     4fc:	e7f7      	b.n	4ee <sd_mmc_select_slot+0x26>
+		if (sd_mmc_cards[slot].state == SD_MMC_CARD_STATE_DEBOUNCE) {
+     4fe:	2801      	cmp	r0, #1
+     500:	d11f      	bne.n	542 <sd_mmc_select_slot+0x7a>
+			sd_mmc_cards[slot].state = SD_MMC_CARD_STATE_INIT;
+     502:	2302      	movs	r3, #2
+     504:	76a3      	strb	r3, [r4, #26]
+			sd_mmc_cards[slot].clock      = SDMMC_CLOCK_INIT;
+     506:	4b17      	ldr	r3, [pc, #92]	; (564 <sd_mmc_select_slot+0x9c>)
+     508:	6123      	str	r3, [r4, #16]
+			sd_mmc_cards[slot].bus_width  = 1;
+     50a:	2301      	movs	r3, #1
+     50c:	7763      	strb	r3, [r4, #29]
+			sd_mmc_cards[slot].high_speed = 0;
+     50e:	2300      	movs	r3, #0
+     510:	f884 302e 	strb.w	r3, [r4, #46]	; 0x2e
+	assert(!(sd_mmc_slot_sel != slot && sd_mmc_nb_block_remaining != 0), ">>>");
+     514:	7923      	ldrb	r3, [r4, #4]
+     516:	b1e3      	cbz	r3, 552 <sd_mmc_select_slot+0x8a>
+     518:	8e20      	ldrh	r0, [r4, #48]	; 0x30
+     51a:	fab0 f080 	clz	r0, r0
+     51e:	0940      	lsrs	r0, r0, #5
+     520:	4a11      	ldr	r2, [pc, #68]	; (568 <sd_mmc_select_slot+0xa0>)
+     522:	4912      	ldr	r1, [pc, #72]	; (56c <sd_mmc_select_slot+0xa4>)
+     524:	4d12      	ldr	r5, [pc, #72]	; (570 <sd_mmc_select_slot+0xa8>)
+     526:	f240 532c 	movw	r3, #1324	; 0x52c
+     52a:	47a8      	blx	r5
+	sd_mmc_slot_sel = slot;
+     52c:	2300      	movs	r3, #0
+     52e:	7123      	strb	r3, [r4, #4]
+	sd_mmc_card     = &sd_mmc_cards[slot];
+     530:	4b10      	ldr	r3, [pc, #64]	; (574 <sd_mmc_select_slot+0xac>)
+     532:	6023      	str	r3, [r4, #0]
+	sd_mmc_configure_slot();
+     534:	4b10      	ldr	r3, [pc, #64]	; (578 <sd_mmc_select_slot+0xb0>)
+     536:	4798      	blx	r3
+	return (sd_mmc_cards[slot].state == SD_MMC_CARD_STATE_INIT) ? SD_MMC_INIT_ONGOING : SD_MMC_OK;
+     538:	7ea0      	ldrb	r0, [r4, #26]
+     53a:	1e83      	subs	r3, r0, #2
+     53c:	4258      	negs	r0, r3
+     53e:	4158      	adcs	r0, r3
+     540:	e7d7      	b.n	4f2 <sd_mmc_select_slot+0x2a>
+		if (sd_mmc_cards[slot].state == SD_MMC_CARD_STATE_UNUSABLE) {
+     542:	2803      	cmp	r0, #3
+     544:	d1e6      	bne.n	514 <sd_mmc_select_slot+0x4c>
+     546:	e7d4      	b.n	4f2 <sd_mmc_select_slot+0x2a>
+		    || (sd_mmc_cards[slot].state == SD_MMC_CARD_STATE_UNUSABLE)) {
+     548:	7ea3      	ldrb	r3, [r4, #26]
+		if ((sd_mmc_cards[slot].state == SD_MMC_CARD_STATE_NO_CARD)
+     54a:	3b03      	subs	r3, #3
+     54c:	2b01      	cmp	r3, #1
+     54e:	d8e1      	bhi.n	514 <sd_mmc_select_slot+0x4c>
+     550:	e7d7      	b.n	502 <sd_mmc_select_slot+0x3a>
+	assert(!(sd_mmc_slot_sel != slot && sd_mmc_nb_block_remaining != 0), ">>>");
+     552:	2001      	movs	r0, #1
+     554:	e7e4      	b.n	520 <sd_mmc_select_slot+0x58>
+		return SD_MMC_ERR_SLOT;
+     556:	2004      	movs	r0, #4
+     558:	e7cb      	b.n	4f2 <sd_mmc_select_slot+0x2a>
+     55a:	bf00      	nop
+     55c:	20000290 	.word	0x20000290
+     560:	00000459 	.word	0x00000459
+     564:	00061a80 	.word	0x00061a80
+     568:	00002b12 	.word	0x00002b12
+     56c:	00002b25 	.word	0x00002b25
+     570:	00002169 	.word	0x00002169
+     574:	200002a0 	.word	0x200002a0
+     578:	000004a1 	.word	0x000004a1
+
+0000057c <sd_mmc_cmd13>:
+{
+     57c:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
+     580:	4d0b      	ldr	r5, [pc, #44]	; (5b0 <sd_mmc_cmd13+0x34>)
+		if (!driver_send_cmd(sd_mmc_hal, SDMMC_MCI_CMD13_SEND_STATUS, (uint32_t)sd_mmc_card->rca << 16)) {
+     582:	4e0c      	ldr	r6, [pc, #48]	; (5b4 <sd_mmc_cmd13+0x38>)
+     584:	4f0c      	ldr	r7, [pc, #48]	; (5b8 <sd_mmc_cmd13+0x3c>)
+		if (driver_get_response(sd_mmc_hal) & CARD_STATUS_READY_FOR_DATA) {
+     586:	f8df 8034 	ldr.w	r8, [pc, #52]	; 5bc <sd_mmc_cmd13+0x40>
+		if (!driver_send_cmd(sd_mmc_hal, SDMMC_MCI_CMD13_SEND_STATUS, (uint32_t)sd_mmc_card->rca << 16)) {
+     58a:	6833      	ldr	r3, [r6, #0]
+     58c:	68b0      	ldr	r0, [r6, #8]
+     58e:	891a      	ldrh	r2, [r3, #8]
+     590:	f241 110d 	movw	r1, #4365	; 0x110d
+     594:	0412      	lsls	r2, r2, #16
+     596:	47b8      	blx	r7
+     598:	4604      	mov	r4, r0
+     59a:	b128      	cbz	r0, 5a8 <sd_mmc_cmd13+0x2c>
+		if (driver_get_response(sd_mmc_hal) & CARD_STATUS_READY_FOR_DATA) {
+     59c:	68b0      	ldr	r0, [r6, #8]
+     59e:	47c0      	blx	r8
+     5a0:	05c3      	lsls	r3, r0, #23
+     5a2:	d402      	bmi.n	5aa <sd_mmc_cmd13+0x2e>
+		if (nec_timeout-- == 0) {
+     5a4:	3d01      	subs	r5, #1
+     5a6:	d1f0      	bne.n	58a <sd_mmc_cmd13+0xe>
+			return false;
+     5a8:	2400      	movs	r4, #0
+}
+     5aa:	4620      	mov	r0, r4
+     5ac:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
+     5b0:	00030d41 	.word	0x00030d41
+     5b4:	20000290 	.word	0x20000290
+     5b8:	00001249 	.word	0x00001249
+     5bc:	000013b9 	.word	0x000013b9
+
+000005c0 <sd_mmc_cmd9_spi>:
+ * data (CSD) on the CMD line spi.
+ *
+ * \return true if success, otherwise false
+ */
+static bool sd_mmc_cmd9_spi(void)
+{
+     5c0:	b573      	push	{r0, r1, r4, r5, r6, lr}
+	if (!driver_adtc_start(sd_mmc_hal, SDMMC_SPI_CMD9_SEND_CSD, (uint32_t)sd_mmc_card->rca << 16,
+     5c2:	4c0e      	ldr	r4, [pc, #56]	; (5fc <sd_mmc_cmd9_spi+0x3c>)
+     5c4:	490e      	ldr	r1, [pc, #56]	; (600 <sd_mmc_cmd9_spi+0x40>)
+     5c6:	6823      	ldr	r3, [r4, #0]
+     5c8:	68a0      	ldr	r0, [r4, #8]
+     5ca:	891a      	ldrh	r2, [r3, #8]
+     5cc:	4e0d      	ldr	r6, [pc, #52]	; (604 <sd_mmc_cmd9_spi+0x44>)
+     5ce:	2501      	movs	r5, #1
+     5d0:	2310      	movs	r3, #16
+     5d2:	e9cd 5500 	strd	r5, r5, [sp]
+     5d6:	409a      	lsls	r2, r3
+     5d8:	47b0      	blx	r6
+     5da:	b160      	cbz	r0, 5f6 <sd_mmc_cmd9_spi+0x36>
+						   CSD_REG_BSIZE, 1, true)) {
+		return false;
+	}
+	if (!driver_start_read_blocks(sd_mmc_hal, sd_mmc_card->csd, 1)) {
+     5dc:	6821      	ldr	r1, [r4, #0]
+     5de:	68a0      	ldr	r0, [r4, #8]
+     5e0:	4b09      	ldr	r3, [pc, #36]	; (608 <sd_mmc_cmd9_spi+0x48>)
+     5e2:	462a      	mov	r2, r5
+     5e4:	310e      	adds	r1, #14
+     5e6:	4798      	blx	r3
+     5e8:	b128      	cbz	r0, 5f6 <sd_mmc_cmd9_spi+0x36>
+		return false;
+	}
+	return driver_wait_end_of_read_blocks(sd_mmc_hal);
+     5ea:	68a0      	ldr	r0, [r4, #8]
+     5ec:	4b07      	ldr	r3, [pc, #28]	; (60c <sd_mmc_cmd9_spi+0x4c>)
+}
+     5ee:	b002      	add	sp, #8
+     5f0:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
+	return driver_wait_end_of_read_blocks(sd_mmc_hal);
+     5f4:	4718      	bx	r3
+}
+     5f6:	2000      	movs	r0, #0
+     5f8:	b002      	add	sp, #8
+     5fa:	bd70      	pop	{r4, r5, r6, pc}
+     5fc:	20000290 	.word	0x20000290
+     600:	00081109 	.word	0x00081109
+     604:	00001061 	.word	0x00001061
+     608:	0000125d 	.word	0x0000125d
+     60c:	00001309 	.word	0x00001309
+
+00000610 <sd_mmc_deselect_slot>:
+	if (sd_mmc_slot_sel < CONF_SD_MMC_MEM_CNT) {
+     610:	4b03      	ldr	r3, [pc, #12]	; (620 <sd_mmc_deselect_slot+0x10>)
+     612:	7919      	ldrb	r1, [r3, #4]
+     614:	b911      	cbnz	r1, 61c <sd_mmc_deselect_slot+0xc>
+		driver_deselect_device(sd_mmc_hal, sd_mmc_slot_sel);
+     616:	6898      	ldr	r0, [r3, #8]
+     618:	4b02      	ldr	r3, [pc, #8]	; (624 <sd_mmc_deselect_slot+0x14>)
+     61a:	4718      	bx	r3
+}
+     61c:	4770      	bx	lr
+     61e:	bf00      	nop
+     620:	20000290 	.word	0x20000290
+     624:	00001411 	.word	0x00001411
+
+00000628 <sdio_cmd53.constprop.0>:
+static bool sdio_cmd53(uint8_t rw_flag, uint8_t func_nb, uint32_t reg_addr, uint8_t inc_addr, uint32_t size,
+     628:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
+     62c:	4605      	mov	r5, r0
+	assert(size != 0, ">>>");
+     62e:	f8df 9070 	ldr.w	r9, [pc, #112]	; 6a0 <sdio_cmd53.constprop.0+0x78>
+static bool sdio_cmd53(uint8_t rw_flag, uint8_t func_nb, uint32_t reg_addr, uint8_t inc_addr, uint32_t size,
+     632:	9f0a      	ldr	r7, [sp, #40]	; 0x28
+     634:	460e      	mov	r6, r1
+     636:	4690      	mov	r8, r2
+     638:	461c      	mov	r4, r3
+	assert(size != 0, ">>>");
+     63a:	4a13      	ldr	r2, [pc, #76]	; (688 <sdio_cmd53.constprop.0+0x60>)
+     63c:	4913      	ldr	r1, [pc, #76]	; (68c <sdio_cmd53.constprop.0+0x64>)
+     63e:	f240 4395 	movw	r3, #1173	; 0x495
+     642:	2001      	movs	r0, #1
+     644:	47c8      	blx	r9
+	assert(size <= 512, ">>>");
+     646:	4a10      	ldr	r2, [pc, #64]	; (688 <sdio_cmd53.constprop.0+0x60>)
+     648:	4910      	ldr	r1, [pc, #64]	; (68c <sdio_cmd53.constprop.0+0x64>)
+     64a:	f240 4396 	movw	r3, #1174	; 0x496
+     64e:	2001      	movs	r0, #1
+     650:	47c8      	blx	r9
+	        | ((uint32_t)inc_addr << SDIO_CMD53_OP_CODE) | ((uint32_t)0 << SDIO_CMD53_BLOCK_MODE)
+     652:	06a3      	lsls	r3, r4, #26
+	        | ((uint32_t)func_nb << SDIO_CMD53_FUNCTION_NUM) | ((uint32_t)rw_flag << SDIO_CMD53_RW_FLAG),
+     654:	ea43 2448 	orr.w	r4, r3, r8, lsl #9
+     658:	ea44 7206 	orr.w	r2, r4, r6, lsl #28
+	    ((size % 512) << SDIO_CMD53_COUNT) | ((uint32_t)reg_addr << SDIO_CMD53_REG_ADDR)
+     65c:	f3c7 0108 	ubfx	r1, r7, #0, #9
+	return driver_adtc_start(
+     660:	480b      	ldr	r0, [pc, #44]	; (690 <sdio_cmd53.constprop.0+0x68>)
+     662:	4c0c      	ldr	r4, [pc, #48]	; (694 <sdio_cmd53.constprop.0+0x6c>)
+	        | ((uint32_t)func_nb << SDIO_CMD53_FUNCTION_NUM) | ((uint32_t)rw_flag << SDIO_CMD53_RW_FLAG),
+     664:	430a      	orrs	r2, r1
+	return driver_adtc_start(
+     666:	2301      	movs	r3, #1
+     668:	490b      	ldr	r1, [pc, #44]	; (698 <sdio_cmd53.constprop.0+0x70>)
+     66a:	e9cd 3300 	strd	r3, r3, [sp]
+     66e:	2d00      	cmp	r5, #0
+     670:	bf08      	it	eq
+     672:	4601      	moveq	r1, r0
+     674:	4809      	ldr	r0, [pc, #36]	; (69c <sdio_cmd53.constprop.0+0x74>)
+     676:	b2bb      	uxth	r3, r7
+     678:	ea42 72c5 	orr.w	r2, r2, r5, lsl #31
+     67c:	6880      	ldr	r0, [r0, #8]
+     67e:	47a0      	blx	r4
+}
+     680:	b003      	add	sp, #12
+     682:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
+     686:	bf00      	nop
+     688:	00002b12 	.word	0x00002b12
+     68c:	00002b25 	.word	0x00002b25
+     690:	00011335 	.word	0x00011335
+     694:	00001061 	.word	0x00001061
+     698:	00019335 	.word	0x00019335
+     69c:	20000290 	.word	0x20000290
+     6a0:	00002169 	.word	0x00002169
+
+000006a4 <sdio_cmd52.constprop.0>:
+static bool sdio_cmd52(uint8_t rw_flag, uint8_t func_nb, uint32_t reg_addr, uint8_t rd_after_wr, uint8_t *io_data)
+     6a4:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
+	assert(io_data != NULL, ">>>");
+     6a8:	461d      	mov	r5, r3
+static bool sdio_cmd52(uint8_t rw_flag, uint8_t func_nb, uint32_t reg_addr, uint8_t rd_after_wr, uint8_t *io_data)
+     6aa:	4606      	mov	r6, r0
+     6ac:	4614      	mov	r4, r2
+	assert(io_data != NULL, ">>>");
+     6ae:	1e28      	subs	r0, r5, #0
+     6b0:	bf18      	it	ne
+     6b2:	2001      	movne	r0, #1
+     6b4:	4a0e      	ldr	r2, [pc, #56]	; (6f0 <sdio_cmd52.constprop.0+0x4c>)
+     6b6:	f8df 804c 	ldr.w	r8, [pc, #76]	; 704 <sdio_cmd52.constprop.0+0x60>
+static bool sdio_cmd52(uint8_t rw_flag, uint8_t func_nb, uint32_t reg_addr, uint8_t rd_after_wr, uint8_t *io_data)
+     6ba:	460f      	mov	r7, r1
+	assert(io_data != NULL, ">>>");
+     6bc:	f240 4376 	movw	r3, #1142	; 0x476
+     6c0:	490c      	ldr	r1, [pc, #48]	; (6f4 <sdio_cmd52.constprop.0+0x50>)
+	                         | ((uint32_t)reg_addr << SDIO_CMD52_REG_ADRR))) {
+     6c2:	0264      	lsls	r4, r4, #9
+	assert(io_data != NULL, ">>>");
+     6c4:	47c0      	blx	r8
+	if (!driver_send_cmd(sd_mmc_hal,
+     6c6:	ea44 7207 	orr.w	r2, r4, r7, lsl #28
+     6ca:	ea42 70c6 	orr.w	r0, r2, r6, lsl #31
+	                     ((uint32_t)*io_data << SDIO_CMD52_WR_DATA) | ((uint32_t)rw_flag << SDIO_CMD52_RW_FLAG)
+     6ce:	782a      	ldrb	r2, [r5, #0]
+	if (!driver_send_cmd(sd_mmc_hal,
+     6d0:	4e09      	ldr	r6, [pc, #36]	; (6f8 <sdio_cmd52.constprop.0+0x54>)
+     6d2:	4b0a      	ldr	r3, [pc, #40]	; (6fc <sdio_cmd52.constprop.0+0x58>)
+     6d4:	4302      	orrs	r2, r0
+     6d6:	f241 3134 	movw	r1, #4916	; 0x1334
+     6da:	68b0      	ldr	r0, [r6, #8]
+     6dc:	4798      	blx	r3
+     6de:	4604      	mov	r4, r0
+     6e0:	b118      	cbz	r0, 6ea <sdio_cmd52.constprop.0+0x46>
+	*io_data = driver_get_response(sd_mmc_hal) & 0xFF;
+     6e2:	68b0      	ldr	r0, [r6, #8]
+     6e4:	4b06      	ldr	r3, [pc, #24]	; (700 <sdio_cmd52.constprop.0+0x5c>)
+     6e6:	4798      	blx	r3
+     6e8:	7028      	strb	r0, [r5, #0]
+}
+     6ea:	4620      	mov	r0, r4
+     6ec:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
+     6f0:	00002b12 	.word	0x00002b12
+     6f4:	00002b25 	.word	0x00002b25
+     6f8:	20000290 	.word	0x20000290
+     6fc:	00001249 	.word	0x00001249
+     700:	000013b9 	.word	0x000013b9
+     704:	00002169 	.word	0x00002169
+
+00000708 <sd_mmc_init>:
+#endif
+
+/*--------------------- PUBLIC FUNCTIONS ----------------------------*/
+
+void sd_mmc_init(void *hal, sd_mmc_detect_t *card_detects, sd_mmc_detect_t *wp_detects)
+{
+     708:	b510      	push	{r4, lr}
+	/* GPIO will be used to detect card and write protect.
+	 * The related clocks and pinmux must be configurated in good
+	 * condition. */
+
+	for (uint8_t slot = 0; slot < CONF_SD_MMC_MEM_CNT; slot++) {
+		sd_mmc_cards[slot].state = SD_MMC_CARD_STATE_NO_CARD;
+     70a:	4b04      	ldr	r3, [pc, #16]	; (71c <sd_mmc_init+0x14>)
+     70c:	2404      	movs	r4, #4
+     70e:	769c      	strb	r4, [r3, #26]
+	}
+	sd_mmc_slot_sel = 0xFF; /* No slot configurated */
+     710:	24ff      	movs	r4, #255	; 0xff
+     712:	711c      	strb	r4, [r3, #4]
+	sd_mmc_hal      = hal;
+	_cd             = card_detects;
+     714:	e9c3 0102 	strd	r0, r1, [r3, #8]
+	_wp             = wp_detects;
+     718:	635a      	str	r2, [r3, #52]	; 0x34
+}
+     71a:	bd10      	pop	{r4, pc}
+     71c:	20000290 	.word	0x20000290
+
+00000720 <sd_mmc_check>:
+{
+	return CONF_SD_MMC_MEM_CNT;
+}
+
+sd_mmc_err_t sd_mmc_check(uint8_t slot)
+{
+     720:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
+	sd_mmc_err_t sd_mmc_err;
+
+	sd_mmc_err = sd_mmc_select_slot(slot);
+     724:	4b84      	ldr	r3, [pc, #528]	; (938 <sd_mmc_check+0x218>)
+{
+     726:	b089      	sub	sp, #36	; 0x24
+	sd_mmc_err = sd_mmc_select_slot(slot);
+     728:	4798      	blx	r3
+	if (sd_mmc_err != SD_MMC_INIT_ONGOING) {
+     72a:	2801      	cmp	r0, #1
+	sd_mmc_err = sd_mmc_select_slot(slot);
+     72c:	4680      	mov	r8, r0
+	if (sd_mmc_err != SD_MMC_INIT_ONGOING) {
+     72e:	d005      	beq.n	73c <sd_mmc_check+0x1c>
+		// To notify that the card has been just initialized
+		// It is necessary for USB Device MSC
+		return SD_MMC_INIT_ONGOING;
+	}
+	sd_mmc_card->state = SD_MMC_CARD_STATE_UNUSABLE;
+	sd_mmc_deselect_slot();
+     730:	4b82      	ldr	r3, [pc, #520]	; (93c <sd_mmc_check+0x21c>)
+     732:	4798      	blx	r3
+	return SD_MMC_ERR_UNUSABLE;
+}
+     734:	4640      	mov	r0, r8
+     736:	b009      	add	sp, #36	; 0x24
+     738:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
+	sd_mmc_card->type = CARD_TYPE_SD;
+     73c:	4c80      	ldr	r4, [pc, #512]	; (940 <sd_mmc_check+0x220>)
+	sd_mmc_spi_debug("Start SD card install\n\r");
+     73e:	4f81      	ldr	r7, [pc, #516]	; (944 <sd_mmc_check+0x224>)
+	sd_mmc_card->type = CARD_TYPE_SD;
+     740:	6823      	ldr	r3, [r4, #0]
+	sd_mmc_card->version = CARD_VER_UNKNOWN;
+     742:	2500      	movs	r5, #0
+	sd_mmc_card->type = CARD_TYPE_SD;
+     744:	72d8      	strb	r0, [r3, #11]
+	sd_mmc_card->version = CARD_VER_UNKNOWN;
+     746:	731d      	strb	r5, [r3, #12]
+	sd_mmc_card->rca = 0;
+     748:	811d      	strh	r5, [r3, #8]
+	sd_mmc_spi_debug("Start SD card install\n\r");
+     74a:	487f      	ldr	r0, [pc, #508]	; (948 <sd_mmc_check+0x228>)
+     74c:	47b8      	blx	r7
+	driver_send_clock(sd_mmc_hal);
+     74e:	68a0      	ldr	r0, [r4, #8]
+     750:	4b7e      	ldr	r3, [pc, #504]	; (94c <sd_mmc_check+0x22c>)
+     752:	4798      	blx	r3
+	if (!driver_send_cmd(sd_mmc_hal, SDMMC_SPI_CMD0_GO_IDLE_STATE, 0)) {
+     754:	462a      	mov	r2, r5
+     756:	68a0      	ldr	r0, [r4, #8]
+     758:	4d7d      	ldr	r5, [pc, #500]	; (950 <sd_mmc_check+0x230>)
+     75a:	f44f 5188 	mov.w	r1, #4352	; 0x1100
+     75e:	47a8      	blx	r5
+     760:	b338      	cbz	r0, 7b2 <sd_mmc_check+0x92>
+	if (!driver_send_cmd(sd_mmc_hal, SD_CMD8_SEND_IF_COND, SD_CMD8_PATTERN | SD_CMD8_HIGH_VOLTAGE)) {
+     762:	68a0      	ldr	r0, [r4, #8]
+     764:	f44f 72d5 	mov.w	r2, #426	; 0x1aa
+     768:	f245 5108 	movw	r1, #21768	; 0x5508
+     76c:	47a8      	blx	r5
+     76e:	bb30      	cbnz	r0, 7be <sd_mmc_check+0x9e>
+	*v2 = 0;
+     770:	2600      	movs	r6, #0
+	if (!driver_send_cmd(sd_mmc_hal, SDIO_CMD5_SEND_OP_COND, 0)) {
+     772:	68a0      	ldr	r0, [r4, #8]
+     774:	2200      	movs	r2, #0
+     776:	f244 5105 	movw	r1, #17669	; 0x4505
+     77a:	47a8      	blx	r5
+     77c:	2800      	cmp	r0, #0
+     77e:	f000 80a6 	beq.w	8ce <sd_mmc_check+0x1ae>
+	resp = driver_get_response(sd_mmc_hal);
+     782:	68a0      	ldr	r0, [r4, #8]
+     784:	f8df 91cc 	ldr.w	r9, [pc, #460]	; 954 <sd_mmc_check+0x234>
+     788:	47c8      	blx	r9
+	if ((resp & OCR_SDIO_NF) == 0) {
+     78a:	f010 4fe0 	tst.w	r0, #1879048192	; 0x70000000
+     78e:	f000 809e 	beq.w	8ce <sd_mmc_check+0x1ae>
+     792:	f241 3a89 	movw	sl, #5001	; 0x1389
+		if (!driver_send_cmd(sd_mmc_hal, SDIO_CMD5_SEND_OP_COND, resp & SD_MMC_VOLTAGE_SUPPORT)) {
+     796:	f400 12fc 	and.w	r2, r0, #2064384	; 0x1f8000
+     79a:	f244 5105 	movw	r1, #17669	; 0x4505
+     79e:	68a0      	ldr	r0, [r4, #8]
+     7a0:	47a8      	blx	r5
+     7a2:	b130      	cbz	r0, 7b2 <sd_mmc_check+0x92>
+		resp = driver_get_response(sd_mmc_hal);
+     7a4:	68a0      	ldr	r0, [r4, #8]
+     7a6:	47c8      	blx	r9
+		if ((resp & OCR_POWER_UP_BUSY) == OCR_POWER_UP_BUSY) {
+     7a8:	2800      	cmp	r0, #0
+     7aa:	db14      	blt.n	7d6 <sd_mmc_check+0xb6>
+		if (cmd5_retry-- == 0) {
+     7ac:	f1ba 0a01 	subs.w	sl, sl, #1
+     7b0:	d1f1      	bne.n	796 <sd_mmc_check+0x76>
+	sd_mmc_card->state = SD_MMC_CARD_STATE_UNUSABLE;
+     7b2:	6823      	ldr	r3, [r4, #0]
+     7b4:	f04f 0803 	mov.w	r8, #3
+     7b8:	f883 800a 	strb.w	r8, [r3, #10]
+     7bc:	e7b8      	b.n	730 <sd_mmc_check+0x10>
+	resp = driver_get_response(sd_mmc_hal);
+     7be:	68a0      	ldr	r0, [r4, #8]
+     7c0:	4b64      	ldr	r3, [pc, #400]	; (954 <sd_mmc_check+0x234>)
+     7c2:	4798      	blx	r3
+	if (resp == 0xFFFFFFFF) {
+     7c4:	1c41      	adds	r1, r0, #1
+     7c6:	d0d3      	beq.n	770 <sd_mmc_check+0x50>
+	if ((resp & (SD_CMD8_MASK_PATTERN | SD_CMD8_MASK_VOLTAGE)) != (SD_CMD8_PATTERN | SD_CMD8_HIGH_VOLTAGE)) {
+     7c8:	f3c0 000b 	ubfx	r0, r0, #0, #12
+     7cc:	f5b0 7fd5 	cmp.w	r0, #426	; 0x1aa
+     7d0:	d1ef      	bne.n	7b2 <sd_mmc_check+0x92>
+	*v2 = 1;
+     7d2:	4646      	mov	r6, r8
+     7d4:	e7cd      	b.n	772 <sd_mmc_check+0x52>
+	if ((resp & OCR_SDIO_MP) > 0) {
+     7d6:	0102      	lsls	r2, r0, #4
+		sd_mmc_card->type = CARD_TYPE_SD_COMBO;
+     7d8:	6823      	ldr	r3, [r4, #0]
+	if ((resp & OCR_SDIO_MP) > 0) {
+     7da:	d52f      	bpl.n	83c <sd_mmc_check+0x11c>
+		sd_mmc_card->type = CARD_TYPE_SD_COMBO;
+     7dc:	2205      	movs	r2, #5
+     7de:	72da      	strb	r2, [r3, #11]
+	if (sd_mmc_card->type & CARD_TYPE_SD) {
+     7e0:	ea4f 7a86 	mov.w	sl, r6, lsl #30
+		resp = driver_get_response(sd_mmc_hal);
+     7e4:	4e5b      	ldr	r6, [pc, #364]	; (954 <sd_mmc_check+0x234>)
+     7e6:	f641 39ef 	movw	r9, #7151	; 0x1bef
+		if (!driver_send_cmd(sd_mmc_hal, SDMMC_CMD55_APP_CMD, 0)) {
+     7ea:	68a0      	ldr	r0, [r4, #8]
+     7ec:	2200      	movs	r2, #0
+     7ee:	f241 1137 	movw	r1, #4407	; 0x1137
+     7f2:	47a8      	blx	r5
+     7f4:	2800      	cmp	r0, #0
+     7f6:	d17f      	bne.n	8f8 <sd_mmc_check+0x1d8>
+			sd_mmc_spi_debug("%s: CMD55 Fail\n\r", __func__);
+     7f8:	4957      	ldr	r1, [pc, #348]	; (958 <sd_mmc_check+0x238>)
+     7fa:	4858      	ldr	r0, [pc, #352]	; (95c <sd_mmc_check+0x23c>)
+			sd_mmc_spi_debug("%s: ACMD41 Fail\n\r", __func__);
+     7fc:	47b8      	blx	r7
+			sd_mmc_spi_debug("Start MMC Install\n\r");
+     7fe:	4858      	ldr	r0, [pc, #352]	; (960 <sd_mmc_check+0x240>)
+     800:	47b8      	blx	r7
+			sd_mmc_card->type = CARD_TYPE_MMC;
+     802:	6823      	ldr	r3, [r4, #0]
+	if (!driver_send_cmd(sd_mmc_hal, SDMMC_SPI_CMD0_GO_IDLE_STATE, 0)) {
+     804:	68a0      	ldr	r0, [r4, #8]
+			sd_mmc_card->type = CARD_TYPE_MMC;
+     806:	2202      	movs	r2, #2
+     808:	72da      	strb	r2, [r3, #11]
+	if (!driver_send_cmd(sd_mmc_hal, SDMMC_SPI_CMD0_GO_IDLE_STATE, 0)) {
+     80a:	f44f 5188 	mov.w	r1, #4352	; 0x1100
+     80e:	2200      	movs	r2, #0
+     810:	47a8      	blx	r5
+     812:	2800      	cmp	r0, #0
+     814:	d0cd      	beq.n	7b2 <sd_mmc_check+0x92>
+		resp = driver_get_response(sd_mmc_hal);
+     816:	f8df 913c 	ldr.w	r9, [pc, #316]	; 954 <sd_mmc_check+0x234>
+	retry = 7150;
+     81a:	f641 36ee 	movw	r6, #7150	; 0x1bee
+		if (!driver_send_cmd(sd_mmc_hal, MMC_SPI_CMD1_SEND_OP_COND, 0)) {
+     81e:	68a0      	ldr	r0, [r4, #8]
+     820:	2200      	movs	r2, #0
+     822:	f241 1101 	movw	r1, #4353	; 0x1101
+     826:	47a8      	blx	r5
+     828:	2800      	cmp	r0, #0
+     82a:	f040 812a 	bne.w	a82 <sd_mmc_check+0x362>
+			sd_mmc_spi_debug("%s: CMD1 SPI Fail - Busy retry %d\n\r",
+     82e:	f5c6 52df 	rsb	r2, r6, #7136	; 0x1be0
+     832:	494c      	ldr	r1, [pc, #304]	; (964 <sd_mmc_check+0x244>)
+     834:	484c      	ldr	r0, [pc, #304]	; (968 <sd_mmc_check+0x248>)
+     836:	320e      	adds	r2, #14
+     838:	47b8      	blx	r7
+			return false;
+     83a:	e7ba      	b.n	7b2 <sd_mmc_check+0x92>
+		sd_mmc_card->type = CARD_TYPE_SDIO;
+     83c:	2204      	movs	r2, #4
+     83e:	72da      	strb	r2, [r3, #11]
+		sdio_cmd52(SDIO_CMD52_READ_FLAG, SDIO_CIA, addr_old, 0, &addr_cis[i]);
+     840:	f8df a134 	ldr.w	sl, [pc, #308]	; 978 <sd_mmc_check+0x258>
+     844:	f10d 0914 	add.w	r9, sp, #20
+	addr_old = SDIO_CCCR_CIS_PTR;
+     848:	2609      	movs	r6, #9
+     84a:	46d3      	mov	fp, sl
+		sdio_cmd52(SDIO_CMD52_READ_FLAG, SDIO_CIA, addr_old, 0, &addr_cis[i]);
+     84c:	2100      	movs	r1, #0
+     84e:	464b      	mov	r3, r9
+     850:	4632      	mov	r2, r6
+     852:	4608      	mov	r0, r1
+		addr_old++;
+     854:	3601      	adds	r6, #1
+		sdio_cmd52(SDIO_CMD52_READ_FLAG, SDIO_CIA, addr_old, 0, &addr_cis[i]);
+     856:	47d0      	blx	sl
+	for (i = 0; i < 4; i++) {
+     858:	2e0d      	cmp	r6, #13
+     85a:	f109 0901 	add.w	r9, r9, #1
+     85e:	d1f5      	bne.n	84c <sd_mmc_check+0x12c>
+	addr_old = addr_cis[0] + (addr_cis[1] << 8) + (addr_cis[2] << 16) + (addr_cis[3] << 24);
+     860:	f89d 3015 	ldrb.w	r3, [sp, #21]
+     864:	f89d 6014 	ldrb.w	r6, [sp, #20]
+     868:	eb06 2603 	add.w	r6, r6, r3, lsl #8
+     86c:	f89d 3016 	ldrb.w	r3, [sp, #22]
+     870:	eb06 4603 	add.w	r6, r6, r3, lsl #16
+     874:	f89d 3017 	ldrb.w	r3, [sp, #23]
+     878:	eb06 6603 	add.w	r6, r6, r3, lsl #24
+		if (addr_new > (addr_old + 256)) {
+     87c:	f506 7380 	add.w	r3, r6, #256	; 0x100
+     880:	9303      	str	r3, [sp, #12]
+	addr_new = addr_old;
+     882:	f04f 0900 	mov.w	r9, #0
+			sdio_cmd52(SDIO_CMD52_READ_FLAG, SDIO_CIA, addr_new, 0, &buf[i]);
+     886:	2100      	movs	r1, #0
+     888:	f10d 0a18 	add.w	sl, sp, #24
+     88c:	eb0a 0309 	add.w	r3, sl, r9
+     890:	eb06 0209 	add.w	r2, r6, r9
+     894:	4608      	mov	r0, r1
+		for (i = 0; i < 3; i++) {
+     896:	f109 0901 	add.w	r9, r9, #1
+			sdio_cmd52(SDIO_CMD52_READ_FLAG, SDIO_CIA, addr_new, 0, &buf[i]);
+     89a:	47d8      	blx	fp
+		for (i = 0; i < 3; i++) {
+     89c:	f1b9 0f03 	cmp.w	r9, #3
+     8a0:	d1f1      	bne.n	886 <sd_mmc_check+0x166>
+		if (buf[0] == SDIO_CISTPL_END) {
+     8a2:	f89d 3018 	ldrb.w	r3, [sp, #24]
+     8a6:	2bff      	cmp	r3, #255	; 0xff
+     8a8:	d083      	beq.n	7b2 <sd_mmc_check+0x92>
+		if (buf[0] == SDIO_CISTPL_FUNCE && buf[2] == 0x00) {
+     8aa:	2b22      	cmp	r3, #34	; 0x22
+     8ac:	d104      	bne.n	8b8 <sd_mmc_check+0x198>
+     8ae:	f89d 301a 	ldrb.w	r3, [sp, #26]
+     8b2:	2b00      	cmp	r3, #0
+     8b4:	f000 81fa 	beq.w	cac <sd_mmc_check+0x58c>
+		if (buf[1] == 0) {
+     8b8:	f89d 3019 	ldrb.w	r3, [sp, #25]
+     8bc:	2b00      	cmp	r3, #0
+     8be:	f43f af78 	beq.w	7b2 <sd_mmc_check+0x92>
+		addr_new += buf[1] - 1;
+     8c2:	3302      	adds	r3, #2
+     8c4:	441e      	add	r6, r3
+		if (addr_new > (addr_old + 256)) {
+     8c6:	9b03      	ldr	r3, [sp, #12]
+     8c8:	429e      	cmp	r6, r3
+     8ca:	d9da      	bls.n	882 <sd_mmc_check+0x162>
+     8cc:	e771      	b.n	7b2 <sd_mmc_check+0x92>
+	if (sd_mmc_card->type & CARD_TYPE_SD) {
+     8ce:	6823      	ldr	r3, [r4, #0]
+     8d0:	7adb      	ldrb	r3, [r3, #11]
+     8d2:	07db      	lsls	r3, r3, #31
+     8d4:	d484      	bmi.n	7e0 <sd_mmc_check+0xc0>
+	if (IS_SDIO()) {
+     8d6:	6823      	ldr	r3, [r4, #0]
+     8d8:	7adb      	ldrb	r3, [r3, #11]
+     8da:	075a      	lsls	r2, r3, #29
+     8dc:	d4b0      	bmi.n	840 <sd_mmc_check+0x120>
+	if ((sd_mmc_card->type & CARD_TYPE_SD) &&
+     8de:	6823      	ldr	r3, [r4, #0]
+     8e0:	7adb      	ldrb	r3, [r3, #11]
+     8e2:	f003 0309 	and.w	r3, r3, #9
+     8e6:	2b01      	cmp	r3, #1
+     8e8:	f000 8202 	beq.w	cf0 <sd_mmc_check+0x5d0>
+	if (sd_mmc_card->type & CARD_TYPE_SD) {
+     8ec:	6823      	ldr	r3, [r4, #0]
+     8ee:	7adb      	ldrb	r3, [r3, #11]
+     8f0:	07db      	lsls	r3, r3, #31
+     8f2:	f100 8188 	bmi.w	c06 <sd_mmc_check+0x4e6>
+     8f6:	e18b      	b.n	c10 <sd_mmc_check+0x4f0>
+		if (!driver_send_cmd(sd_mmc_hal, SD_SPI_ACMD41_SD_SEND_OP_COND, arg)) {
+     8f8:	68a0      	ldr	r0, [r4, #8]
+     8fa:	4652      	mov	r2, sl
+     8fc:	f241 1129 	movw	r1, #4393	; 0x1129
+     900:	47a8      	blx	r5
+     902:	b910      	cbnz	r0, 90a <sd_mmc_check+0x1ea>
+			sd_mmc_spi_debug("%s: ACMD41 Fail\n\r", __func__);
+     904:	4914      	ldr	r1, [pc, #80]	; (958 <sd_mmc_check+0x238>)
+     906:	4819      	ldr	r0, [pc, #100]	; (96c <sd_mmc_check+0x24c>)
+     908:	e778      	b.n	7fc <sd_mmc_check+0xdc>
+		resp = driver_get_response(sd_mmc_hal);
+     90a:	68a0      	ldr	r0, [r4, #8]
+     90c:	47b0      	blx	r6
+		if (!(resp & R1_SPI_IDLE)) {
+     90e:	f010 0201 	ands.w	r2, r0, #1
+     912:	d008      	beq.n	926 <sd_mmc_check+0x206>
+		if (retry-- == 0) {
+     914:	f1b9 0901 	subs.w	r9, r9, #1
+     918:	f47f af67 	bne.w	7ea <sd_mmc_check+0xca>
+			sd_mmc_spi_debug("%s: ACMD41 Timeout on busy, resp32 0x%08x \n\r",
+     91c:	4602      	mov	r2, r0
+     91e:	490e      	ldr	r1, [pc, #56]	; (958 <sd_mmc_check+0x238>)
+     920:	4813      	ldr	r0, [pc, #76]	; (970 <sd_mmc_check+0x250>)
+     922:	47b8      	blx	r7
+			return false;
+     924:	e76b      	b.n	7fe <sd_mmc_check+0xde>
+	if (!driver_send_cmd(sd_mmc_hal, SDMMC_SPI_CMD58_READ_OCR, 0)) {
+     926:	68a0      	ldr	r0, [r4, #8]
+     928:	f240 513a 	movw	r1, #1338	; 0x53a
+     92c:	47a8      	blx	r5
+     92e:	bb28      	cbnz	r0, 97c <sd_mmc_check+0x25c>
+		sd_mmc_spi_debug("%s: CMD58 Fail\n\r", __func__);
+     930:	4909      	ldr	r1, [pc, #36]	; (958 <sd_mmc_check+0x238>)
+     932:	4810      	ldr	r0, [pc, #64]	; (974 <sd_mmc_check+0x254>)
+     934:	e762      	b.n	7fc <sd_mmc_check+0xdc>
+     936:	bf00      	nop
+     938:	000004c9 	.word	0x000004c9
+     93c:	00000611 	.word	0x00000611
+     940:	20000290 	.word	0x20000290
+     944:	000020d5 	.word	0x000020d5
+     948:	00002b29 	.word	0x00002b29
+     94c:	000013c5 	.word	0x000013c5
+     950:	00001249 	.word	0x00001249
+     954:	000013b9 	.word	0x000013b9
+     958:	00002c0c 	.word	0x00002c0c
+     95c:	00002b41 	.word	0x00002b41
+     960:	00002ba2 	.word	0x00002ba2
+     964:	00002c1b 	.word	0x00002c1b
+     968:	00002bb6 	.word	0x00002bb6
+     96c:	00002b52 	.word	0x00002b52
+     970:	00002b64 	.word	0x00002b64
+     974:	00002b91 	.word	0x00002b91
+     978:	000006a5 	.word	0x000006a5
+	if ((driver_get_response(sd_mmc_hal) & OCR_CCS) != 0) {
+     97c:	68a0      	ldr	r0, [r4, #8]
+     97e:	47b0      	blx	r6
+     980:	0040      	lsls	r0, r0, #1
+     982:	d504      	bpl.n	98e <sd_mmc_check+0x26e>
+		sd_mmc_card->type |= CARD_TYPE_HC;
+     984:	6822      	ldr	r2, [r4, #0]
+     986:	7ad3      	ldrb	r3, [r2, #11]
+     988:	f043 0308 	orr.w	r3, r3, #8
+     98c:	72d3      	strb	r3, [r2, #11]
+		if (!driver_send_cmd(sd_mmc_hal, SDMMC_SPI_CMD59_CRC_ON_OFF, 0)) {
+     98e:	68a0      	ldr	r0, [r4, #8]
+     990:	2200      	movs	r2, #0
+     992:	f241 113b 	movw	r1, #4411	; 0x113b
+     996:	47a8      	blx	r5
+     998:	2800      	cmp	r0, #0
+     99a:	f43f af0a 	beq.w	7b2 <sd_mmc_check+0x92>
+	if (sd_mmc_card->type & CARD_TYPE_SD) {
+     99e:	6823      	ldr	r3, [r4, #0]
+     9a0:	7adb      	ldrb	r3, [r3, #11]
+     9a2:	07d9      	lsls	r1, r3, #31
+     9a4:	d597      	bpl.n	8d6 <sd_mmc_check+0x1b6>
+		if (!sd_mmc_cmd9_spi()) {
+     9a6:	4bb2      	ldr	r3, [pc, #712]	; (c70 <sd_mmc_check+0x550>)
+     9a8:	4798      	blx	r3
+     9aa:	2800      	cmp	r0, #0
+     9ac:	f43f af01 	beq.w	7b2 <sd_mmc_check+0x92>
+	tran_speed         = CSD_TRAN_SPEED(sd_mmc_card->csd);
+     9b0:	f8d4 a000 	ldr.w	sl, [r4]
+     9b4:	4eaf      	ldr	r6, [pc, #700]	; (c74 <sd_mmc_check+0x554>)
+     9b6:	f10a 0b0e 	add.w	fp, sl, #14
+     9ba:	2308      	movs	r3, #8
+     9bc:	2260      	movs	r2, #96	; 0x60
+     9be:	2180      	movs	r1, #128	; 0x80
+     9c0:	4658      	mov	r0, fp
+     9c2:	47b0      	blx	r6
+	mul                = sd_trans_multipliers[(tran_speed >> 3) & 0xF];
+     9c4:	4bac      	ldr	r3, [pc, #688]	; (c78 <sd_mmc_check+0x558>)
+     9c6:	f3c0 02c3 	ubfx	r2, r0, #3, #4
+	unit               = sd_mmc_trans_units[tran_speed & 0x7];
+     9ca:	f000 0007 	and.w	r0, r0, #7
+     9ce:	eb03 0080 	add.w	r0, r3, r0, lsl #2
+	mul                = sd_trans_multipliers[(tran_speed >> 3) & 0xF];
+     9d2:	eb03 0282 	add.w	r2, r3, r2, lsl #2
+	if (CSD_STRUCTURE_VERSION(sd_mmc_card->csd) >= SD_CSD_VER_2_0) {
+     9d6:	2180      	movs	r1, #128	; 0x80
+	sd_mmc_card->clock = unit * mul * 1000;
+     9d8:	6fd3      	ldr	r3, [r2, #124]	; 0x7c
+     9da:	6e02      	ldr	r2, [r0, #96]	; 0x60
+     9dc:	4353      	muls	r3, r2
+     9de:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
+     9e2:	4353      	muls	r3, r2
+     9e4:	f8ca 3000 	str.w	r3, [sl]
+	if (CSD_STRUCTURE_VERSION(sd_mmc_card->csd) >= SD_CSD_VER_2_0) {
+     9e8:	227e      	movs	r2, #126	; 0x7e
+     9ea:	2302      	movs	r3, #2
+     9ec:	4658      	mov	r0, fp
+     9ee:	47b0      	blx	r6
+     9f0:	46b1      	mov	r9, r6
+     9f2:	2800      	cmp	r0, #0
+     9f4:	f000 811e 	beq.w	c34 <sd_mmc_check+0x514>
+		sd_mmc_card->capacity = (SD_CSD_2_0_C_SIZE(sd_mmc_card->csd) + 1) * 512;
+     9f8:	2316      	movs	r3, #22
+     9fa:	2230      	movs	r2, #48	; 0x30
+     9fc:	2180      	movs	r1, #128	; 0x80
+     9fe:	4658      	mov	r0, fp
+     a00:	47b0      	blx	r6
+     a02:	3001      	adds	r0, #1
+     a04:	0240      	lsls	r0, r0, #9
+	if (!driver_send_cmd(sd_mmc_hal, SDMMC_CMD55_APP_CMD, (uint32_t)sd_mmc_card->rca << 16)) {
+     a06:	f8ba 2008 	ldrh.w	r2, [sl, #8]
+     a0a:	f8ca 0004 	str.w	r0, [sl, #4]
+     a0e:	0412      	lsls	r2, r2, #16
+     a10:	68a0      	ldr	r0, [r4, #8]
+     a12:	f241 1137 	movw	r1, #4407	; 0x1137
+     a16:	47a8      	blx	r5
+     a18:	2800      	cmp	r0, #0
+     a1a:	f43f aeca 	beq.w	7b2 <sd_mmc_check+0x92>
+	if (!driver_adtc_start(sd_mmc_hal, SD_ACMD51_SEND_SCR, 0, SD_SCR_REG_BSIZE, 1, true)) {
+     a1e:	2601      	movs	r6, #1
+     a20:	e9cd 6600 	strd	r6, r6, [sp]
+     a24:	4995      	ldr	r1, [pc, #596]	; (c7c <sd_mmc_check+0x55c>)
+     a26:	68a0      	ldr	r0, [r4, #8]
+     a28:	f8df a26c 	ldr.w	sl, [pc, #620]	; c98 <sd_mmc_check+0x578>
+     a2c:	2308      	movs	r3, #8
+     a2e:	2200      	movs	r2, #0
+     a30:	47d0      	blx	sl
+     a32:	2800      	cmp	r0, #0
+     a34:	f43f aebd 	beq.w	7b2 <sd_mmc_check+0x92>
+	if (!driver_start_read_blocks(sd_mmc_hal, scr, 1)) {
+     a38:	68a0      	ldr	r0, [r4, #8]
+     a3a:	4b91      	ldr	r3, [pc, #580]	; (c80 <sd_mmc_check+0x560>)
+     a3c:	4632      	mov	r2, r6
+     a3e:	a906      	add	r1, sp, #24
+     a40:	4798      	blx	r3
+     a42:	2800      	cmp	r0, #0
+     a44:	f43f aeb5 	beq.w	7b2 <sd_mmc_check+0x92>
+	if (!driver_wait_end_of_read_blocks(sd_mmc_hal)) {
+     a48:	68a0      	ldr	r0, [r4, #8]
+     a4a:	4b8e      	ldr	r3, [pc, #568]	; (c84 <sd_mmc_check+0x564>)
+     a4c:	4798      	blx	r3
+     a4e:	2800      	cmp	r0, #0
+     a50:	f43f aeaf 	beq.w	7b2 <sd_mmc_check+0x92>
+	switch (SD_SCR_SD_SPEC(scr)) {
+     a54:	2304      	movs	r3, #4
+     a56:	2238      	movs	r2, #56	; 0x38
+     a58:	2140      	movs	r1, #64	; 0x40
+     a5a:	a806      	add	r0, sp, #24
+     a5c:	47c8      	blx	r9
+     a5e:	42b0      	cmp	r0, r6
+		sd_mmc_card->version = CARD_VER_SD_1_0;
+     a60:	f8d4 a000 	ldr.w	sl, [r4]
+	switch (SD_SCR_SD_SPEC(scr)) {
+     a64:	f000 80fd 	beq.w	c62 <sd_mmc_check+0x542>
+     a68:	2802      	cmp	r0, #2
+     a6a:	f040 80fe 	bne.w	c6a <sd_mmc_check+0x54a>
+		if (SD_SCR_SD_SPEC3(scr) == SD_SCR_SD_SPEC_3_00) {
+     a6e:	4633      	mov	r3, r6
+     a70:	222f      	movs	r2, #47	; 0x2f
+     a72:	2140      	movs	r1, #64	; 0x40
+     a74:	a806      	add	r0, sp, #24
+     a76:	47c8      	blx	r9
+     a78:	2801      	cmp	r0, #1
+			sd_mmc_card->version = CARD_VER_SD_3_0;
+     a7a:	bf0c      	ite	eq
+     a7c:	2330      	moveq	r3, #48	; 0x30
+			sd_mmc_card->version = CARD_VER_SD_2_0;
+     a7e:	2320      	movne	r3, #32
+     a80:	e0f0      	b.n	c64 <sd_mmc_check+0x544>
+		resp = driver_get_response(sd_mmc_hal);
+     a82:	68a0      	ldr	r0, [r4, #8]
+     a84:	47c8      	blx	r9
+		if (!(resp & R1_SPI_IDLE)) {
+     a86:	f010 0201 	ands.w	r2, r0, #1
+     a8a:	d006      	beq.n	a9a <sd_mmc_check+0x37a>
+		if (retry-- == 0) {
+     a8c:	3e01      	subs	r6, #1
+     a8e:	f4bf aec6 	bcs.w	81e <sd_mmc_check+0xfe>
+			sd_mmc_spi_debug("%s: CMD1 Timeout on busy\n\r", __func__);
+     a92:	497d      	ldr	r1, [pc, #500]	; (c88 <sd_mmc_check+0x568>)
+     a94:	487d      	ldr	r0, [pc, #500]	; (c8c <sd_mmc_check+0x56c>)
+		sd_mmc_spi_debug("%s: CMD58 Fail\n\r", __func__);
+     a96:	47b8      	blx	r7
+		return false;
+     a98:	e68b      	b.n	7b2 <sd_mmc_check+0x92>
+	if (!driver_send_cmd(sd_mmc_hal, SDMMC_SPI_CMD58_READ_OCR, 0)) {
+     a9a:	68a0      	ldr	r0, [r4, #8]
+     a9c:	f240 513a 	movw	r1, #1338	; 0x53a
+     aa0:	47a8      	blx	r5
+     aa2:	b910      	cbnz	r0, aaa <sd_mmc_check+0x38a>
+		sd_mmc_spi_debug("%s: CMD58 Fail\n\r", __func__);
+     aa4:	4978      	ldr	r1, [pc, #480]	; (c88 <sd_mmc_check+0x568>)
+     aa6:	487a      	ldr	r0, [pc, #488]	; (c90 <sd_mmc_check+0x570>)
+     aa8:	e7f5      	b.n	a96 <sd_mmc_check+0x376>
+	if ((driver_get_response(sd_mmc_hal) & OCR_ACCESS_MODE_MASK)
+     aaa:	68a0      	ldr	r0, [r4, #8]
+     aac:	47c8      	blx	r9
+     aae:	f000 40c0 	and.w	r0, r0, #1610612736	; 0x60000000
+     ab2:	f1b0 4f80 	cmp.w	r0, #1073741824	; 0x40000000
+		sd_mmc_card->type |= CARD_TYPE_HC;
+     ab6:	bf08      	it	eq
+     ab8:	6822      	ldreq	r2, [r4, #0]
+	if (!driver_send_cmd(sd_mmc_hal, SDMMC_SPI_CMD59_CRC_ON_OFF, 0)) {
+     aba:	68a0      	ldr	r0, [r4, #8]
+		sd_mmc_card->type |= CARD_TYPE_HC;
+     abc:	bf02      	ittt	eq
+     abe:	7ad3      	ldrbeq	r3, [r2, #11]
+     ac0:	f043 0308 	orreq.w	r3, r3, #8
+     ac4:	72d3      	strbeq	r3, [r2, #11]
+	if (!driver_send_cmd(sd_mmc_hal, SDMMC_SPI_CMD59_CRC_ON_OFF, 0)) {
+     ac6:	f241 113b 	movw	r1, #4411	; 0x113b
+     aca:	2200      	movs	r2, #0
+     acc:	47a8      	blx	r5
+     ace:	2800      	cmp	r0, #0
+     ad0:	f43f ae6f 	beq.w	7b2 <sd_mmc_check+0x92>
+	if (!sd_mmc_cmd9_spi()) {
+     ad4:	4b66      	ldr	r3, [pc, #408]	; (c70 <sd_mmc_check+0x550>)
+     ad6:	4798      	blx	r3
+     ad8:	2800      	cmp	r0, #0
+     ada:	f43f ae6a 	beq.w	7b2 <sd_mmc_check+0x92>
+	switch (MMC_CSD_SPEC_VERS(sd_mmc_card->csd)) {
+     ade:	f8d4 9000 	ldr.w	r9, [r4]
+     ae2:	4e64      	ldr	r6, [pc, #400]	; (c74 <sd_mmc_check+0x554>)
+     ae4:	f109 0b0e 	add.w	fp, r9, #14
+     ae8:	2304      	movs	r3, #4
+     aea:	227a      	movs	r2, #122	; 0x7a
+     aec:	2180      	movs	r1, #128	; 0x80
+     aee:	4658      	mov	r0, fp
+     af0:	47b0      	blx	r6
+     af2:	3801      	subs	r0, #1
+     af4:	46b2      	mov	sl, r6
+     af6:	2803      	cmp	r0, #3
+     af8:	d803      	bhi.n	b02 <sd_mmc_check+0x3e2>
+     afa:	e8df f000 	tbb	[pc, r0]
+     afe:	9391      	.short	0x9391
+     b00:	9795      	.short	0x9795
+		sd_mmc_card->version = CARD_VER_MMC_1_2;
+     b02:	2312      	movs	r3, #18
+		sd_mmc_card->version = CARD_VER_MMC_4;
+     b04:	f889 300c 	strb.w	r3, [r9, #12]
+	tran_speed         = CSD_TRAN_SPEED(sd_mmc_card->csd);
+     b08:	2260      	movs	r2, #96	; 0x60
+     b0a:	2308      	movs	r3, #8
+     b0c:	2180      	movs	r1, #128	; 0x80
+     b0e:	4658      	mov	r0, fp
+     b10:	47d0      	blx	sl
+	mul                = mmc_trans_multipliers[(tran_speed >> 3) & 0xF];
+     b12:	4b59      	ldr	r3, [pc, #356]	; (c78 <sd_mmc_check+0x558>)
+     b14:	f3c0 02c3 	ubfx	r2, r0, #3, #4
+	unit               = sd_mmc_trans_units[tran_speed & 0x7];
+     b18:	f000 0007 	and.w	r0, r0, #7
+     b1c:	eb03 0080 	add.w	r0, r3, r0, lsl #2
+	mul                = mmc_trans_multipliers[(tran_speed >> 3) & 0xF];
+     b20:	eb03 0282 	add.w	r2, r3, r2, lsl #2
+	if (MMC_CSD_C_SIZE(sd_mmc_card->csd) != 0xFFF) {
+     b24:	2180      	movs	r1, #128	; 0x80
+	sd_mmc_card->clock = unit * mul * 1000;
+     b26:	6a13      	ldr	r3, [r2, #32]
+     b28:	6e02      	ldr	r2, [r0, #96]	; 0x60
+     b2a:	4353      	muls	r3, r2
+     b2c:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
+     b30:	4353      	muls	r3, r2
+     b32:	f8c9 3000 	str.w	r3, [r9]
+	if (MMC_CSD_C_SIZE(sd_mmc_card->csd) != 0xFFF) {
+     b36:	223e      	movs	r2, #62	; 0x3e
+     b38:	230c      	movs	r3, #12
+     b3a:	4658      	mov	r0, fp
+     b3c:	47d0      	blx	sl
+     b3e:	f640 73ff 	movw	r3, #4095	; 0xfff
+     b42:	4298      	cmp	r0, r3
+     b44:	4606      	mov	r6, r0
+     b46:	d012      	beq.n	b6e <sd_mmc_check+0x44e>
+		    = ((MMC_CSD_C_SIZE(sd_mmc_card->csd) + 1) * (1 << (MMC_CSD_C_SIZE_MULT(sd_mmc_card->csd) + 2)));
+     b48:	2303      	movs	r3, #3
+     b4a:	222f      	movs	r2, #47	; 0x2f
+     b4c:	2180      	movs	r1, #128	; 0x80
+     b4e:	4658      	mov	r0, fp
+     b50:	47d0      	blx	sl
+     b52:	1c73      	adds	r3, r6, #1
+     b54:	3002      	adds	r0, #2
+		uint32_t blocknr
+     b56:	fa03 f600 	lsl.w	r6, r3, r0
+		sd_mmc_card->capacity = blocknr * (1 << MMC_CSD_READ_BL_LEN(sd_mmc_card->csd)) / 1024;
+     b5a:	2250      	movs	r2, #80	; 0x50
+     b5c:	2304      	movs	r3, #4
+     b5e:	2180      	movs	r1, #128	; 0x80
+     b60:	4658      	mov	r0, fp
+     b62:	47d0      	blx	sl
+     b64:	fa06 f000 	lsl.w	r0, r6, r0
+     b68:	0a80      	lsrs	r0, r0, #10
+     b6a:	f8c9 0004 	str.w	r0, [r9, #4]
+	if (sd_mmc_card->version >= CARD_VER_MMC_4) {
+     b6e:	f899 300c 	ldrb.w	r3, [r9, #12]
+     b72:	2b3f      	cmp	r3, #63	; 0x3f
+     b74:	d93e      	bls.n	bf4 <sd_mmc_check+0x4d4>
+	if (!driver_adtc_start(sd_mmc_hal, MMC_CMD8_SEND_EXT_CSD, 0, EXT_CSD_BSIZE, 1, false)) {
+     b76:	2301      	movs	r3, #1
+     b78:	2200      	movs	r2, #0
+     b7a:	e9cd 3200 	strd	r3, r2, [sp]
+     b7e:	4945      	ldr	r1, [pc, #276]	; (c94 <sd_mmc_check+0x574>)
+     b80:	68a0      	ldr	r0, [r4, #8]
+     b82:	4e45      	ldr	r6, [pc, #276]	; (c98 <sd_mmc_check+0x578>)
+     b84:	f44f 7300 	mov.w	r3, #512	; 0x200
+     b88:	47b0      	blx	r6
+     b8a:	2800      	cmp	r0, #0
+     b8c:	f43f ae11 	beq.w	7b2 <sd_mmc_check+0x92>
+		if (!driver_read_word(sd_mmc_hal, &ext_csd)) {
+     b90:	f8df b114 	ldr.w	fp, [pc, #276]	; ca8 <sd_mmc_check+0x588>
+     b94:	2632      	movs	r6, #50	; 0x32
+     b96:	46d9      	mov	r9, fp
+     b98:	68a0      	ldr	r0, [r4, #8]
+     b9a:	a905      	add	r1, sp, #20
+     b9c:	47d8      	blx	fp
+     b9e:	2800      	cmp	r0, #0
+     ba0:	f43f ae07 	beq.w	7b2 <sd_mmc_check+0x92>
+	for (i = 0; i < (EXT_CSD_CARD_TYPE_INDEX + 4) / 4; i++) {
+     ba4:	3e01      	subs	r6, #1
+     ba6:	b2b6      	uxth	r6, r6
+     ba8:	2e00      	cmp	r6, #0
+     baa:	d1f5      	bne.n	b98 <sd_mmc_check+0x478>
+	if (MMC_CSD_C_SIZE(sd_mmc_card->csd) == 0xFFF) {
+     bac:	6820      	ldr	r0, [r4, #0]
+     bae:	230c      	movs	r3, #12
+     bb0:	223e      	movs	r2, #62	; 0x3e
+     bb2:	2180      	movs	r1, #128	; 0x80
+     bb4:	300e      	adds	r0, #14
+     bb6:	47d0      	blx	sl
+     bb8:	f640 73ff 	movw	r3, #4095	; 0xfff
+     bbc:	4298      	cmp	r0, r3
+     bbe:	d137      	bne.n	c30 <sd_mmc_check+0x510>
+     bc0:	2604      	movs	r6, #4
+			if (!driver_read_word(sd_mmc_hal, &sec_count)) {
+     bc2:	68a0      	ldr	r0, [r4, #8]
+     bc4:	a906      	add	r1, sp, #24
+     bc6:	47c8      	blx	r9
+     bc8:	2800      	cmp	r0, #0
+     bca:	f43f adf2 	beq.w	7b2 <sd_mmc_check+0x92>
+		for (; i < (EXT_CSD_SEC_COUNT_INDEX + 4) / 4; i++) {
+     bce:	3e01      	subs	r6, #1
+     bd0:	b2b6      	uxth	r6, r6
+     bd2:	2e00      	cmp	r6, #0
+     bd4:	d1f5      	bne.n	bc2 <sd_mmc_check+0x4a2>
+		sd_mmc_card->capacity = sec_count / 2;
+     bd6:	9b06      	ldr	r3, [sp, #24]
+     bd8:	6822      	ldr	r2, [r4, #0]
+     bda:	085b      	lsrs	r3, r3, #1
+     bdc:	6053      	str	r3, [r2, #4]
+     bde:	2636      	movs	r6, #54	; 0x36
+		if (!driver_read_word(sd_mmc_hal, &sec_count)) {
+     be0:	68a0      	ldr	r0, [r4, #8]
+     be2:	a906      	add	r1, sp, #24
+     be4:	47c8      	blx	r9
+     be6:	2800      	cmp	r0, #0
+     be8:	f43f ade3 	beq.w	7b2 <sd_mmc_check+0x92>
+	for (; i < EXT_CSD_BSIZE / 4; i++) {
+     bec:	3601      	adds	r6, #1
+     bee:	b2b6      	uxth	r6, r6
+     bf0:	2e80      	cmp	r6, #128	; 0x80
+     bf2:	d1f5      	bne.n	be0 <sd_mmc_check+0x4c0>
+	if (!driver_send_cmd(sd_mmc_hal, SDMMC_CMD16_SET_BLOCKLEN, SD_MMC_BLOCK_SIZE)) {
+     bf4:	68a0      	ldr	r0, [r4, #8]
+     bf6:	f44f 7200 	mov.w	r2, #512	; 0x200
+     bfa:	f241 1110 	movw	r1, #4368	; 0x1110
+     bfe:	47a8      	blx	r5
+     c00:	2800      	cmp	r0, #0
+     c02:	f43f add6 	beq.w	7b2 <sd_mmc_check+0x92>
+	if (!sd_mmc_cmd13()) {
+     c06:	4b25      	ldr	r3, [pc, #148]	; (c9c <sd_mmc_check+0x57c>)
+     c08:	4798      	blx	r3
+     c0a:	2800      	cmp	r0, #0
+     c0c:	f43f add1 	beq.w	7b2 <sd_mmc_check+0x92>
+	sd_mmc_configure_slot();
+     c10:	4b23      	ldr	r3, [pc, #140]	; (ca0 <sd_mmc_check+0x580>)
+     c12:	4798      	blx	r3
+		sd_mmc_spi_debug("SD/MMC card ready\n\r");
+     c14:	4823      	ldr	r0, [pc, #140]	; (ca4 <sd_mmc_check+0x584>)
+     c16:	47b8      	blx	r7
+		sd_mmc_card->state = SD_MMC_CARD_STATE_READY;
+     c18:	6823      	ldr	r3, [r4, #0]
+     c1a:	2200      	movs	r2, #0
+     c1c:	729a      	strb	r2, [r3, #10]
+		sd_mmc_deselect_slot();
+     c1e:	e587      	b.n	730 <sd_mmc_check+0x10>
+		sd_mmc_card->version = CARD_VER_MMC_1_4;
+     c20:	2314      	movs	r3, #20
+     c22:	e76f      	b.n	b04 <sd_mmc_check+0x3e4>
+		sd_mmc_card->version = CARD_VER_MMC_2_2;
+     c24:	2322      	movs	r3, #34	; 0x22
+     c26:	e76d      	b.n	b04 <sd_mmc_check+0x3e4>
+		sd_mmc_card->version = CARD_VER_MMC_3;
+     c28:	2330      	movs	r3, #48	; 0x30
+     c2a:	e76b      	b.n	b04 <sd_mmc_check+0x3e4>
+		sd_mmc_card->version = CARD_VER_MMC_4;
+     c2c:	2340      	movs	r3, #64	; 0x40
+     c2e:	e769      	b.n	b04 <sd_mmc_check+0x3e4>
+     c30:	2632      	movs	r6, #50	; 0x32
+     c32:	e7d5      	b.n	be0 <sd_mmc_check+0x4c0>
+		    = ((SD_CSD_1_0_C_SIZE(sd_mmc_card->csd) + 1) * (1 << (SD_CSD_1_0_C_SIZE_MULT(sd_mmc_card->csd) + 2)));
+     c34:	230c      	movs	r3, #12
+     c36:	223e      	movs	r2, #62	; 0x3e
+     c38:	2180      	movs	r1, #128	; 0x80
+     c3a:	4658      	mov	r0, fp
+     c3c:	47b0      	blx	r6
+     c3e:	2303      	movs	r3, #3
+     c40:	4606      	mov	r6, r0
+     c42:	222f      	movs	r2, #47	; 0x2f
+     c44:	2180      	movs	r1, #128	; 0x80
+     c46:	4658      	mov	r0, fp
+     c48:	47c8      	blx	r9
+     c4a:	3601      	adds	r6, #1
+     c4c:	3002      	adds	r0, #2
+		uint32_t blocknr
+     c4e:	4086      	lsls	r6, r0
+		sd_mmc_card->capacity = blocknr * (1 << SD_CSD_1_0_READ_BL_LEN(sd_mmc_card->csd)) / 1024;
+     c50:	2304      	movs	r3, #4
+     c52:	2250      	movs	r2, #80	; 0x50
+     c54:	2180      	movs	r1, #128	; 0x80
+     c56:	4658      	mov	r0, fp
+     c58:	47c8      	blx	r9
+     c5a:	fa06 f000 	lsl.w	r0, r6, r0
+     c5e:	0a80      	lsrs	r0, r0, #10
+     c60:	e6d1      	b.n	a06 <sd_mmc_check+0x2e6>
+		sd_mmc_card->version = CARD_VER_SD_1_10;
+     c62:	231a      	movs	r3, #26
+		sd_mmc_card->version = CARD_VER_SD_1_0;
+     c64:	f88a 300c 	strb.w	r3, [sl, #12]
+		break;
+     c68:	e635      	b.n	8d6 <sd_mmc_check+0x1b6>
+		sd_mmc_card->version = CARD_VER_SD_1_0;
+     c6a:	2310      	movs	r3, #16
+     c6c:	e7fa      	b.n	c64 <sd_mmc_check+0x544>
+     c6e:	bf00      	nop
+     c70:	000005c1 	.word	0x000005c1
+     c74:	000003f9 	.word	0x000003f9
+     c78:	00002c0c 	.word	0x00002c0c
+     c7c:	00081133 	.word	0x00081133
+     c80:	0000125d 	.word	0x0000125d
+     c84:	00001309 	.word	0x00001309
+     c88:	00002c1b 	.word	0x00002c1b
+     c8c:	00002bda 	.word	0x00002bda
+     c90:	00002b91 	.word	0x00002b91
+     c94:	00081108 	.word	0x00081108
+     c98:	00001061 	.word	0x00001061
+     c9c:	0000057d 	.word	0x0000057d
+     ca0:	000004a1 	.word	0x000004a1
+     ca4:	00002bf5 	.word	0x00002bf5
+     ca8:	0000130d 	.word	0x0000130d
+	for (i = 0; i < 6; i++) {
+     cac:	f106 0906 	add.w	r9, r6, #6
+		sdio_cmd52(SDIO_CMD52_READ_FLAG, SDIO_CIA, addr_new, 0, &buf[i]);
+     cb0:	2100      	movs	r1, #0
+     cb2:	4653      	mov	r3, sl
+     cb4:	4632      	mov	r2, r6
+     cb6:	4608      	mov	r0, r1
+		addr_new++;
+     cb8:	3601      	adds	r6, #1
+		sdio_cmd52(SDIO_CMD52_READ_FLAG, SDIO_CIA, addr_new, 0, &buf[i]);
+     cba:	47d8      	blx	fp
+	for (i = 0; i < 6; i++) {
+     cbc:	454e      	cmp	r6, r9
+     cbe:	f10a 0a01 	add.w	sl, sl, #1
+     cc2:	d1f5      	bne.n	cb0 <sd_mmc_check+0x590>
+	tplfe_max_tran_speed = buf[5];
+     cc4:	f89d 301d 	ldrb.w	r3, [sp, #29]
+	unit               = sd_mmc_trans_units[tplfe_max_tran_speed & 0x7];
+     cc8:	490e      	ldr	r1, [pc, #56]	; (d04 <sd_mmc_check+0x5e4>)
+	sd_mmc_card->clock = unit * mul * 1000;
+     cca:	6822      	ldr	r2, [r4, #0]
+     ccc:	2b32      	cmp	r3, #50	; 0x32
+     cce:	bf28      	it	cs
+     cd0:	2332      	movcs	r3, #50	; 0x32
+	unit               = sd_mmc_trans_units[tplfe_max_tran_speed & 0x7];
+     cd2:	f003 0007 	and.w	r0, r3, #7
+	mul                = sd_trans_multipliers[(tplfe_max_tran_speed >> 3) & 0xF];
+     cd6:	08db      	lsrs	r3, r3, #3
+	unit               = sd_mmc_trans_units[tplfe_max_tran_speed & 0x7];
+     cd8:	eb01 0080 	add.w	r0, r1, r0, lsl #2
+	mul                = sd_trans_multipliers[(tplfe_max_tran_speed >> 3) & 0xF];
+     cdc:	eb01 0183 	add.w	r1, r1, r3, lsl #2
+	sd_mmc_card->clock = unit * mul * 1000;
+     ce0:	6e03      	ldr	r3, [r0, #96]	; 0x60
+     ce2:	6fc9      	ldr	r1, [r1, #124]	; 0x7c
+     ce4:	434b      	muls	r3, r1
+     ce6:	f44f 717a 	mov.w	r1, #1000	; 0x3e8
+     cea:	434b      	muls	r3, r1
+     cec:	6013      	str	r3, [r2, #0]
+	return true;
+     cee:	e5f6      	b.n	8de <sd_mmc_check+0x1be>
+		if (!driver_send_cmd(sd_mmc_hal, SDMMC_CMD16_SET_BLOCKLEN, SD_MMC_BLOCK_SIZE)) {
+     cf0:	68a0      	ldr	r0, [r4, #8]
+     cf2:	f44f 7200 	mov.w	r2, #512	; 0x200
+     cf6:	f241 1110 	movw	r1, #4368	; 0x1110
+     cfa:	47a8      	blx	r5
+     cfc:	2800      	cmp	r0, #0
+     cfe:	f47f adf5 	bne.w	8ec <sd_mmc_check+0x1cc>
+     d02:	e556      	b.n	7b2 <sd_mmc_check+0x92>
+     d04:	00002c0c 	.word	0x00002c0c
+
+00000d08 <sd_mmc_get_type>:
+
+card_type_t sd_mmc_get_type(uint8_t slot)
+{
+     d08:	b508      	push	{r3, lr}
+	if (SD_MMC_OK != sd_mmc_select_slot(slot)) {
+     d0a:	4b05      	ldr	r3, [pc, #20]	; (d20 <sd_mmc_get_type+0x18>)
+     d0c:	4798      	blx	r3
+     d0e:	b928      	cbnz	r0, d1c <sd_mmc_get_type+0x14>
+		return CARD_TYPE_UNKNOWN;
+	}
+	sd_mmc_deselect_slot();
+     d10:	4b04      	ldr	r3, [pc, #16]	; (d24 <sd_mmc_get_type+0x1c>)
+     d12:	4798      	blx	r3
+	return sd_mmc_card->type;
+     d14:	4b04      	ldr	r3, [pc, #16]	; (d28 <sd_mmc_get_type+0x20>)
+     d16:	681b      	ldr	r3, [r3, #0]
+     d18:	7ad8      	ldrb	r0, [r3, #11]
+}
+     d1a:	bd08      	pop	{r3, pc}
+		return CARD_TYPE_UNKNOWN;
+     d1c:	2000      	movs	r0, #0
+     d1e:	e7fc      	b.n	d1a <sd_mmc_get_type+0x12>
+     d20:	000004c9 	.word	0x000004c9
+     d24:	00000611 	.word	0x00000611
+     d28:	20000290 	.word	0x20000290
+
+00000d2c <sd_mmc_init_read_blocks>:
+	}
+	return false;
+}
+
+sd_mmc_err_t sd_mmc_init_read_blocks(uint8_t slot, uint32_t start, uint16_t nb_block)
+{
+     d2c:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
+	sd_mmc_err_t sd_mmc_err;
+	uint32_t     cmd, arg, resp;
+
+	sd_mmc_err = sd_mmc_select_slot(slot);
+     d2e:	4b17      	ldr	r3, [pc, #92]	; (d8c <sd_mmc_init_read_blocks+0x60>)
+{
+     d30:	460f      	mov	r7, r1
+     d32:	4614      	mov	r4, r2
+	sd_mmc_err = sd_mmc_select_slot(slot);
+     d34:	4798      	blx	r3
+	if (sd_mmc_err != SD_MMC_OK) {
+     d36:	4605      	mov	r5, r0
+     d38:	b928      	cbnz	r0, d46 <sd_mmc_init_read_blocks+0x1a>
+		return sd_mmc_err;
+	}
+
+	/* Wait for data ready status */
+	if (!sd_mmc_cmd13()) {
+     d3a:	4b15      	ldr	r3, [pc, #84]	; (d90 <sd_mmc_init_read_blocks+0x64>)
+     d3c:	4798      	blx	r3
+     d3e:	b928      	cbnz	r0, d4c <sd_mmc_init_read_blocks+0x20>
+		sd_mmc_deselect_slot();
+     d40:	4b14      	ldr	r3, [pc, #80]	; (d94 <sd_mmc_init_read_blocks+0x68>)
+     d42:	4798      	blx	r3
+		return SD_MMC_ERR_COMM;
+     d44:	2505      	movs	r5, #5
+	}
+
+	sd_mmc_nb_block_remaining  = nb_block;
+	sd_mmc_nb_block_to_tranfer = nb_block;
+	return SD_MMC_OK;
+}
+     d46:	4628      	mov	r0, r5
+     d48:	b003      	add	sp, #12
+     d4a:	bdf0      	pop	{r4, r5, r6, r7, pc}
+		cmd = SDMMC_CMD17_READ_SINGLE_BLOCK;
+     d4c:	4b12      	ldr	r3, [pc, #72]	; (d98 <sd_mmc_init_read_blocks+0x6c>)
+	if (sd_mmc_card->type & CARD_TYPE_HC) {
+     d4e:	4e13      	ldr	r6, [pc, #76]	; (d9c <sd_mmc_init_read_blocks+0x70>)
+		cmd = SDMMC_CMD17_READ_SINGLE_BLOCK;
+     d50:	4913      	ldr	r1, [pc, #76]	; (da0 <sd_mmc_init_read_blocks+0x74>)
+	if (!driver_adtc_start(sd_mmc_hal, cmd, arg, SD_MMC_BLOCK_SIZE, nb_block, true)) {
+     d52:	68b0      	ldr	r0, [r6, #8]
+		cmd = SDMMC_CMD17_READ_SINGLE_BLOCK;
+     d54:	2c01      	cmp	r4, #1
+     d56:	bf98      	it	ls
+     d58:	4619      	movls	r1, r3
+	if (sd_mmc_card->type & CARD_TYPE_HC) {
+     d5a:	6833      	ldr	r3, [r6, #0]
+     d5c:	7adb      	ldrb	r3, [r3, #11]
+     d5e:	071b      	lsls	r3, r3, #28
+		arg = (start * SD_MMC_BLOCK_SIZE);
+     d60:	bf58      	it	pl
+     d62:	027f      	lslpl	r7, r7, #9
+	if (!driver_adtc_start(sd_mmc_hal, cmd, arg, SD_MMC_BLOCK_SIZE, nb_block, true)) {
+     d64:	2301      	movs	r3, #1
+     d66:	e9cd 4300 	strd	r4, r3, [sp]
+     d6a:	463a      	mov	r2, r7
+     d6c:	f44f 7300 	mov.w	r3, #512	; 0x200
+     d70:	4f0c      	ldr	r7, [pc, #48]	; (da4 <sd_mmc_init_read_blocks+0x78>)
+     d72:	47b8      	blx	r7
+     d74:	2800      	cmp	r0, #0
+     d76:	d0e3      	beq.n	d40 <sd_mmc_init_read_blocks+0x14>
+	resp = driver_get_response(sd_mmc_hal);
+     d78:	4b0b      	ldr	r3, [pc, #44]	; (da8 <sd_mmc_init_read_blocks+0x7c>)
+     d7a:	68b0      	ldr	r0, [r6, #8]
+     d7c:	4798      	blx	r3
+	if (resp & CARD_STATUS_ERR_RD_WR) {
+     d7e:	4b0b      	ldr	r3, [pc, #44]	; (dac <sd_mmc_init_read_blocks+0x80>)
+     d80:	4003      	ands	r3, r0
+     d82:	2b00      	cmp	r3, #0
+     d84:	d1dc      	bne.n	d40 <sd_mmc_init_read_blocks+0x14>
+	sd_mmc_nb_block_remaining  = nb_block;
+     d86:	8634      	strh	r4, [r6, #48]	; 0x30
+	sd_mmc_nb_block_to_tranfer = nb_block;
+     d88:	8734      	strh	r4, [r6, #56]	; 0x38
+	return SD_MMC_OK;
+     d8a:	e7dc      	b.n	d46 <sd_mmc_init_read_blocks+0x1a>
+     d8c:	000004c9 	.word	0x000004c9
+     d90:	0000057d 	.word	0x0000057d
+     d94:	00000611 	.word	0x00000611
+     d98:	00081111 	.word	0x00081111
+     d9c:	20000290 	.word	0x20000290
+     da0:	00101112 	.word	0x00101112
+     da4:	00001061 	.word	0x00001061
+     da8:	000013b9 	.word	0x000013b9
+     dac:	e4580000 	.word	0xe4580000
+
+00000db0 <sd_mmc_start_read_blocks>:
+
+sd_mmc_err_t sd_mmc_start_read_blocks(void *dest, uint16_t nb_block)
+{
+     db0:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+	assert(sd_mmc_nb_block_remaining >= nb_block, ">>>");
+     db2:	4d0e      	ldr	r5, [pc, #56]	; (dec <sd_mmc_start_read_blocks+0x3c>)
+     db4:	4a0e      	ldr	r2, [pc, #56]	; (df0 <sd_mmc_start_read_blocks+0x40>)
+     db6:	4f0f      	ldr	r7, [pc, #60]	; (df4 <sd_mmc_start_read_blocks+0x44>)
+{
+     db8:	4606      	mov	r6, r0
+	assert(sd_mmc_nb_block_remaining >= nb_block, ">>>");
+     dba:	8e28      	ldrh	r0, [r5, #48]	; 0x30
+{
+     dbc:	460c      	mov	r4, r1
+	assert(sd_mmc_nb_block_remaining >= nb_block, ">>>");
+     dbe:	42a0      	cmp	r0, r4
+     dc0:	bf34      	ite	cc
+     dc2:	2000      	movcc	r0, #0
+     dc4:	2001      	movcs	r0, #1
+     dc6:	490c      	ldr	r1, [pc, #48]	; (df8 <sd_mmc_start_read_blocks+0x48>)
+     dc8:	f44f 63d9 	mov.w	r3, #1736	; 0x6c8
+     dcc:	47b8      	blx	r7
+
+	if (!driver_start_read_blocks(sd_mmc_hal, dest, nb_block)) {
+     dce:	68a8      	ldr	r0, [r5, #8]
+     dd0:	4b0a      	ldr	r3, [pc, #40]	; (dfc <sd_mmc_start_read_blocks+0x4c>)
+     dd2:	4622      	mov	r2, r4
+     dd4:	4631      	mov	r1, r6
+     dd6:	4798      	blx	r3
+     dd8:	b128      	cbz	r0, de6 <sd_mmc_start_read_blocks+0x36>
+		sd_mmc_nb_block_remaining = 0;
+		return SD_MMC_ERR_COMM;
+	}
+	sd_mmc_nb_block_remaining -= nb_block;
+     dda:	8e28      	ldrh	r0, [r5, #48]	; 0x30
+     ddc:	1b01      	subs	r1, r0, r4
+     dde:	b289      	uxth	r1, r1
+	return SD_MMC_OK;
+     de0:	2000      	movs	r0, #0
+     de2:	8629      	strh	r1, [r5, #48]	; 0x30
+}
+     de4:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+		sd_mmc_nb_block_remaining = 0;
+     de6:	4601      	mov	r1, r0
+		return SD_MMC_ERR_COMM;
+     de8:	2005      	movs	r0, #5
+     dea:	e7fa      	b.n	de2 <sd_mmc_start_read_blocks+0x32>
+     dec:	20000290 	.word	0x20000290
+     df0:	00002b12 	.word	0x00002b12
+     df4:	00002169 	.word	0x00002169
+     df8:	00002b25 	.word	0x00002b25
+     dfc:	0000125d 	.word	0x0000125d
+
+00000e00 <sd_mmc_wait_end_of_read_blocks>:
+
+sd_mmc_err_t sd_mmc_wait_end_of_read_blocks(bool abort)
+{
+     e00:	b538      	push	{r3, r4, r5, lr}
+	if (!driver_wait_end_of_read_blocks(sd_mmc_hal)) {
+     e02:	4d12      	ldr	r5, [pc, #72]	; (e4c <sd_mmc_wait_end_of_read_blocks+0x4c>)
+     e04:	4b12      	ldr	r3, [pc, #72]	; (e50 <sd_mmc_wait_end_of_read_blocks+0x50>)
+{
+     e06:	4604      	mov	r4, r0
+	if (!driver_wait_end_of_read_blocks(sd_mmc_hal)) {
+     e08:	68a8      	ldr	r0, [r5, #8]
+     e0a:	4798      	blx	r3
+     e0c:	b1e0      	cbz	r0, e48 <sd_mmc_wait_end_of_read_blocks+0x48>
+		return SD_MMC_ERR_COMM;
+	}
+	if (abort) {
+     e0e:	b144      	cbz	r4, e22 <sd_mmc_wait_end_of_read_blocks+0x22>
+		sd_mmc_nb_block_remaining = 0;
+     e10:	2300      	movs	r3, #0
+     e12:	862b      	strh	r3, [r5, #48]	; 0x30
+	} else if (sd_mmc_nb_block_remaining) {
+		return SD_MMC_OK;
+	}
+
+	/* All blocks are transfered then stop read operation */
+	if (sd_mmc_nb_block_to_tranfer == 1) {
+     e14:	8f2b      	ldrh	r3, [r5, #56]	; 0x38
+     e16:	2b01      	cmp	r3, #1
+     e18:	d108      	bne.n	e2c <sd_mmc_wait_end_of_read_blocks+0x2c>
+		/* Single block transfer, then nothing to do */
+		sd_mmc_deselect_slot();
+     e1a:	4b0e      	ldr	r3, [pc, #56]	; (e54 <sd_mmc_wait_end_of_read_blocks+0x54>)
+     e1c:	4798      	blx	r3
+		return SD_MMC_OK;
+     e1e:	2000      	movs	r0, #0
+	if (!driver_adtc_stop(sd_mmc_hal, SDMMC_CMD12_STOP_TRANSMISSION, 0)) {
+		driver_adtc_stop(sd_mmc_hal, SDMMC_CMD12_STOP_TRANSMISSION, 0);
+	}
+	sd_mmc_deselect_slot();
+	return SD_MMC_OK;
+}
+     e20:	bd38      	pop	{r3, r4, r5, pc}
+	} else if (sd_mmc_nb_block_remaining) {
+     e22:	8e2b      	ldrh	r3, [r5, #48]	; 0x30
+     e24:	2b00      	cmp	r3, #0
+     e26:	d0f5      	beq.n	e14 <sd_mmc_wait_end_of_read_blocks+0x14>
+		return SD_MMC_OK;
+     e28:	4620      	mov	r0, r4
+     e2a:	e7f9      	b.n	e20 <sd_mmc_wait_end_of_read_blocks+0x20>
+	if (!driver_adtc_stop(sd_mmc_hal, SDMMC_CMD12_STOP_TRANSMISSION, 0)) {
+     e2c:	2200      	movs	r2, #0
+     e2e:	68a8      	ldr	r0, [r5, #8]
+     e30:	4c09      	ldr	r4, [pc, #36]	; (e58 <sd_mmc_wait_end_of_read_blocks+0x58>)
+     e32:	f243 110c 	movw	r1, #12556	; 0x310c
+     e36:	47a0      	blx	r4
+     e38:	4602      	mov	r2, r0
+     e3a:	2800      	cmp	r0, #0
+     e3c:	d1ed      	bne.n	e1a <sd_mmc_wait_end_of_read_blocks+0x1a>
+		driver_adtc_stop(sd_mmc_hal, SDMMC_CMD12_STOP_TRANSMISSION, 0);
+     e3e:	68a8      	ldr	r0, [r5, #8]
+     e40:	f243 110c 	movw	r1, #12556	; 0x310c
+     e44:	47a0      	blx	r4
+     e46:	e7e8      	b.n	e1a <sd_mmc_wait_end_of_read_blocks+0x1a>
+		return SD_MMC_ERR_COMM;
+     e48:	2005      	movs	r0, #5
+     e4a:	e7e9      	b.n	e20 <sd_mmc_wait_end_of_read_blocks+0x20>
+     e4c:	20000290 	.word	0x20000290
+     e50:	00001309 	.word	0x00001309
+     e54:	00000611 	.word	0x00000611
+     e58:	00001249 	.word	0x00001249
+
+00000e5c <sdio_read_extended>:
+	return SD_MMC_OK;
+}
+
+sd_mmc_err_t sdio_read_extended(uint8_t slot, uint8_t func_num, uint32_t addr, uint8_t inc_addr, uint8_t *dest,
+                                uint16_t size)
+{
+     e5c:	b570      	push	{r4, r5, r6, lr}
+     e5e:	b086      	sub	sp, #24
+     e60:	e9cd 2104 	strd	r2, r1, [sp, #16]
+     e64:	f8bd 502c 	ldrh.w	r5, [sp, #44]	; 0x2c
+     e68:	9303      	str	r3, [sp, #12]
+	sd_mmc_err_t sd_mmc_err;
+
+	if ((size == 0) || (size > 512)) {
+     e6a:	1e6c      	subs	r4, r5, #1
+     e6c:	f5b4 7f00 	cmp.w	r4, #512	; 0x200
+     e70:	d21f      	bcs.n	eb2 <sdio_read_extended+0x56>
+		return SD_MMC_ERR_PARAM;
+	}
+
+	sd_mmc_err = sd_mmc_select_slot(slot);
+     e72:	4c11      	ldr	r4, [pc, #68]	; (eb8 <sdio_read_extended+0x5c>)
+     e74:	47a0      	blx	r4
+	if (sd_mmc_err != SD_MMC_OK) {
+     e76:	4604      	mov	r4, r0
+     e78:	b948      	cbnz	r0, e8e <sdio_read_extended+0x32>
+		return sd_mmc_err;
+	}
+
+	if (!sdio_cmd53(SDIO_CMD53_READ_FLAG, func_num, addr, inc_addr, size, true)) {
+     e7a:	9500      	str	r5, [sp, #0]
+     e7c:	e9dd 3203 	ldrd	r3, r2, [sp, #12]
+     e80:	4d0e      	ldr	r5, [pc, #56]	; (ebc <sdio_read_extended+0x60>)
+     e82:	9905      	ldr	r1, [sp, #20]
+     e84:	47a8      	blx	r5
+     e86:	4d0e      	ldr	r5, [pc, #56]	; (ec0 <sdio_read_extended+0x64>)
+     e88:	b920      	cbnz	r0, e94 <sdio_read_extended+0x38>
+		sd_mmc_deselect_slot();
+     e8a:	47a8      	blx	r5
+		return SD_MMC_ERR_COMM;
+     e8c:	2405      	movs	r4, #5
+		return SD_MMC_ERR_COMM;
+	}
+
+	sd_mmc_deselect_slot();
+	return SD_MMC_OK;
+}
+     e8e:	4620      	mov	r0, r4
+     e90:	b006      	add	sp, #24
+     e92:	bd70      	pop	{r4, r5, r6, pc}
+	if (!driver_start_read_blocks(sd_mmc_hal, dest, 1)) {
+     e94:	4e0b      	ldr	r6, [pc, #44]	; (ec4 <sdio_read_extended+0x68>)
+     e96:	990a      	ldr	r1, [sp, #40]	; 0x28
+     e98:	68b0      	ldr	r0, [r6, #8]
+     e9a:	4b0b      	ldr	r3, [pc, #44]	; (ec8 <sdio_read_extended+0x6c>)
+     e9c:	2201      	movs	r2, #1
+     e9e:	4798      	blx	r3
+     ea0:	2800      	cmp	r0, #0
+     ea2:	d0f2      	beq.n	e8a <sdio_read_extended+0x2e>
+	if (!driver_wait_end_of_read_blocks(sd_mmc_hal)) {
+     ea4:	68b0      	ldr	r0, [r6, #8]
+     ea6:	4b09      	ldr	r3, [pc, #36]	; (ecc <sdio_read_extended+0x70>)
+     ea8:	4798      	blx	r3
+     eaa:	2800      	cmp	r0, #0
+     eac:	d0ed      	beq.n	e8a <sdio_read_extended+0x2e>
+	sd_mmc_deselect_slot();
+     eae:	47a8      	blx	r5
+	return SD_MMC_OK;
+     eb0:	e7ed      	b.n	e8e <sdio_read_extended+0x32>
+		return SD_MMC_ERR_PARAM;
+     eb2:	2406      	movs	r4, #6
+     eb4:	e7eb      	b.n	e8e <sdio_read_extended+0x32>
+     eb6:	bf00      	nop
+     eb8:	000004c9 	.word	0x000004c9
+     ebc:	00000629 	.word	0x00000629
+     ec0:	00000611 	.word	0x00000611
+     ec4:	20000290 	.word	0x20000290
+     ec8:	0000125d 	.word	0x0000125d
+     ecc:	00001309 	.word	0x00001309
+
+00000ed0 <spi_m_sync_wait_busy>:
+	crc = (crc << 1) | 1;
+	return crc;
+}
+
+static bool spi_m_sync_wait_busy(struct spi_m_sync_descriptor* spi)
+{
+     ed0:	b573      	push	{r0, r1, r4, r5, r6, lr}
+	uint8_t line = 0xFF;
+     ed2:	23ff      	movs	r3, #255	; 0xff
+     ed4:	f88d 3002 	strb.w	r3, [sp, #2]
+	uint8_t dummy = 0xFF;
+     ed8:	f88d 3003 	strb.w	r3, [sp, #3]
+
+	/* Delay before check busy
+	 * Nbr timing minimum = 8 cylces
+	 */
+
+	struct io_descriptor* spi_inst = NULL;
+     edc:	2300      	movs	r3, #0
+     ede:	9301      	str	r3, [sp, #4]
+	spi_m_sync_get_io_descriptor(spi, &spi_inst);
+     ee0:	a901      	add	r1, sp, #4
+     ee2:	4b17      	ldr	r3, [pc, #92]	; (f40 <spi_m_sync_wait_busy+0x70>)
+	io_write(spi_inst, &dummy, 1);
+     ee4:	4d17      	ldr	r5, [pc, #92]	; (f44 <spi_m_sync_wait_busy+0x74>)
+	io_read(spi_inst, &line, 1);
+     ee6:	4e18      	ldr	r6, [pc, #96]	; (f48 <spi_m_sync_wait_busy+0x78>)
+	 * However a timeout is used.
+	 * 200 000 * 8 cycles
+	 */
+	uint32_t nec_timeout = 200000;
+	io_write(spi_inst, &dummy, 1);
+	io_read(spi_inst, &line, 1);
+     ee8:	4c18      	ldr	r4, [pc, #96]	; (f4c <spi_m_sync_wait_busy+0x7c>)
+	spi_m_sync_get_io_descriptor(spi, &spi_inst);
+     eea:	4798      	blx	r3
+	io_write(spi_inst, &dummy, 1);
+     eec:	2201      	movs	r2, #1
+     eee:	f10d 0103 	add.w	r1, sp, #3
+     ef2:	9801      	ldr	r0, [sp, #4]
+     ef4:	47a8      	blx	r5
+	io_read(spi_inst, &line, 1);
+     ef6:	2201      	movs	r2, #1
+     ef8:	f10d 0102 	add.w	r1, sp, #2
+     efc:	9801      	ldr	r0, [sp, #4]
+     efe:	47b0      	blx	r6
+	io_write(spi_inst, &dummy, 1);
+     f00:	2201      	movs	r2, #1
+     f02:	f10d 0103 	add.w	r1, sp, #3
+     f06:	9801      	ldr	r0, [sp, #4]
+     f08:	47a8      	blx	r5
+	io_read(spi_inst, &line, 1);
+     f0a:	9801      	ldr	r0, [sp, #4]
+     f0c:	2201      	movs	r2, #1
+     f0e:	f10d 0102 	add.w	r1, sp, #2
+     f12:	47b0      	blx	r6
+	do {
+		io_write(spi_inst, &dummy, 1);
+     f14:	2201      	movs	r2, #1
+     f16:	f10d 0103 	add.w	r1, sp, #3
+     f1a:	9801      	ldr	r0, [sp, #4]
+     f1c:	47a8      	blx	r5
+		io_read(spi_inst, &line, 1);
+     f1e:	9801      	ldr	r0, [sp, #4]
+     f20:	2201      	movs	r2, #1
+     f22:	f10d 0102 	add.w	r1, sp, #2
+     f26:	47b0      	blx	r6
+		if (!(nec_timeout--)) {
+     f28:	3c01      	subs	r4, #1
+     f2a:	d006      	beq.n	f3a <spi_m_sync_wait_busy+0x6a>
+			return false;
+		}
+	} while (line != 0xFF);
+     f2c:	f89d 3002 	ldrb.w	r3, [sp, #2]
+     f30:	2bff      	cmp	r3, #255	; 0xff
+     f32:	d1ef      	bne.n	f14 <spi_m_sync_wait_busy+0x44>
+	return true;
+     f34:	2001      	movs	r0, #1
+}
+     f36:	b002      	add	sp, #8
+     f38:	bd70      	pop	{r4, r5, r6, pc}
+			return false;
+     f3a:	4620      	mov	r0, r4
+     f3c:	e7fb      	b.n	f36 <spi_m_sync_wait_busy+0x66>
+     f3e:	bf00      	nop
+     f40:	00001521 	.word	0x00001521
+     f44:	000002a5 	.word	0x000002a5
+     f48:	000002d5 	.word	0x000002d5
+     f4c:	00030d41 	.word	0x00030d41
+
+00000f50 <spi_m_sync_stop_read_block>:
+
+	return true;
+}
+
+static void spi_m_sync_stop_read_block(struct spi_m_sync_descriptor* spi)
+{
+     f50:	b51f      	push	{r0, r1, r2, r3, r4, lr}
+	struct io_descriptor* spi_inst = NULL;
+     f52:	2300      	movs	r3, #0
+     f54:	9303      	str	r3, [sp, #12]
+	spi_m_sync_get_io_descriptor(spi, &spi_inst);
+     f56:	a903      	add	r1, sp, #12
+     f58:	4b09      	ldr	r3, [pc, #36]	; (f80 <spi_m_sync_stop_read_block+0x30>)
+     f5a:	4798      	blx	r3
+	uint8_t crc[2];
+	uint8_t dummy = 0xFF;
+     f5c:	23ff      	movs	r3, #255	; 0xff
+     f5e:	f88d 3007 	strb.w	r3, [sp, #7]
+	// Read 16-bit CRC (not cheked)
+	io_write(spi_inst, &dummy, 1);
+     f62:	f10d 0107 	add.w	r1, sp, #7
+     f66:	9803      	ldr	r0, [sp, #12]
+     f68:	4b06      	ldr	r3, [pc, #24]	; (f84 <spi_m_sync_stop_read_block+0x34>)
+     f6a:	2201      	movs	r2, #1
+     f6c:	4798      	blx	r3
+	io_read(spi_inst, crc, 2);
+     f6e:	9803      	ldr	r0, [sp, #12]
+     f70:	4b05      	ldr	r3, [pc, #20]	; (f88 <spi_m_sync_stop_read_block+0x38>)
+     f72:	2202      	movs	r2, #2
+     f74:	a902      	add	r1, sp, #8
+     f76:	4798      	blx	r3
+}
+     f78:	b005      	add	sp, #20
+     f7a:	f85d fb04 	ldr.w	pc, [sp], #4
+     f7e:	bf00      	nop
+     f80:	00001521 	.word	0x00001521
+     f84:	000002a5 	.word	0x000002a5
+     f88:	000002d5 	.word	0x000002d5
+
+00000f8c <spi_m_sync_start_read_block>:
+{
+     f8c:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
+	spi_m_sync_get_io_descriptor(spi, &spi_inst);
+     f90:	4b26      	ldr	r3, [pc, #152]	; (102c <spi_m_sync_start_read_block+0xa0>)
+	assert(!(sd_mmc_spi_transfert_pos % sd_mmc_spi_block_size), ">>>");
+     f92:	4d27      	ldr	r5, [pc, #156]	; (1030 <spi_m_sync_start_read_block+0xa4>)
+		io_write(spi_inst, &dummy, 1);
+     f94:	4e27      	ldr	r6, [pc, #156]	; (1034 <spi_m_sync_start_read_block+0xa8>)
+		io_read(spi_inst, &token, 1);
+     f96:	f8df 80c4 	ldr.w	r8, [pc, #196]	; 105c <spi_m_sync_start_read_block+0xd0>
+	struct io_descriptor* spi_inst = NULL;
+     f9a:	2400      	movs	r4, #0
+	spi_m_sync_get_io_descriptor(spi, &spi_inst);
+     f9c:	a901      	add	r1, sp, #4
+	struct io_descriptor* spi_inst = NULL;
+     f9e:	9401      	str	r4, [sp, #4]
+	spi_m_sync_get_io_descriptor(spi, &spi_inst);
+     fa0:	4798      	blx	r3
+	assert(!(sd_mmc_spi_transfert_pos % sd_mmc_spi_block_size), ">>>");
+     fa2:	4a25      	ldr	r2, [pc, #148]	; (1038 <spi_m_sync_start_read_block+0xac>)
+     fa4:	4925      	ldr	r1, [pc, #148]	; (103c <spi_m_sync_start_read_block+0xb0>)
+     fa6:	6810      	ldr	r0, [r2, #0]
+	uint8_t dummy = 0xFF;
+     fa8:	23ff      	movs	r3, #255	; 0xff
+     faa:	f88d 3003 	strb.w	r3, [sp, #3]
+	assert(!(sd_mmc_spi_transfert_pos % sd_mmc_spi_block_size), ">>>");
+     fae:	8893      	ldrh	r3, [r2, #4]
+     fb0:	fbb0 f2f3 	udiv	r2, r0, r3
+     fb4:	fb03 0012 	mls	r0, r3, r2, r0
+     fb8:	fab0 f080 	clz	r0, r0
+     fbc:	4a20      	ldr	r2, [pc, #128]	; (1040 <spi_m_sync_start_read_block+0xb4>)
+     fbe:	23b3      	movs	r3, #179	; 0xb3
+     fc0:	0940      	lsrs	r0, r0, #5
+     fc2:	47a8      	blx	r5
+	token = 0;
+     fc4:	f88d 4002 	strb.w	r4, [sp, #2]
+     fc8:	4c1e      	ldr	r4, [pc, #120]	; (1044 <spi_m_sync_start_read_block+0xb8>)
+		if (i-- == 0) {
+     fca:	3c01      	subs	r4, #1
+     fcc:	d105      	bne.n	fda <spi_m_sync_start_read_block+0x4e>
+			sd_mmc_spi_debug("%s: Read blocks timeout\n\r", __func__);
+     fce:	491e      	ldr	r1, [pc, #120]	; (1048 <spi_m_sync_start_read_block+0xbc>)
+     fd0:	481e      	ldr	r0, [pc, #120]	; (104c <spi_m_sync_start_read_block+0xc0>)
+     fd2:	4b1f      	ldr	r3, [pc, #124]	; (1050 <spi_m_sync_start_read_block+0xc4>)
+				sd_mmc_spi_debug("%s: Out of range data error token\n\r", __func__);
+     fd4:	4798      	blx	r3
+			return false;
+     fd6:	4620      	mov	r0, r4
+     fd8:	e01f      	b.n	101a <spi_m_sync_start_read_block+0x8e>
+		io_write(spi_inst, &dummy, 1);
+     fda:	2201      	movs	r2, #1
+     fdc:	f10d 0103 	add.w	r1, sp, #3
+     fe0:	9801      	ldr	r0, [sp, #4]
+     fe2:	47b0      	blx	r6
+		io_read(spi_inst, &token, 1);
+     fe4:	9801      	ldr	r0, [sp, #4]
+     fe6:	2201      	movs	r2, #1
+     fe8:	f10d 0102 	add.w	r1, sp, #2
+     fec:	47c0      	blx	r8
+		if (SPI_TOKEN_DATA_ERROR_VALID(token)) {
+     fee:	f89d 0002 	ldrb.w	r0, [sp, #2]
+     ff2:	f010 07f0 	ands.w	r7, r0, #240	; 0xf0
+     ff6:	d115      	bne.n	1024 <spi_m_sync_start_read_block+0x98>
+			assert(SPI_TOKEN_DATA_ERROR_ERRORS & token, ">>>");
+     ff8:	3800      	subs	r0, #0
+     ffa:	bf18      	it	ne
+     ffc:	2001      	movne	r0, #1
+     ffe:	490f      	ldr	r1, [pc, #60]	; (103c <spi_m_sync_start_read_block+0xb0>)
+    1000:	4a0f      	ldr	r2, [pc, #60]	; (1040 <spi_m_sync_start_read_block+0xb4>)
+    1002:	23c9      	movs	r3, #201	; 0xc9
+    1004:	47a8      	blx	r5
+			if (token & (SPI_TOKEN_DATA_ERROR_ERROR
+    1006:	f89d 0002 	ldrb.w	r0, [sp, #2]
+				sd_mmc_spi_debug("%s: CRC data error token\n\r", __func__);
+    100a:	490f      	ldr	r1, [pc, #60]	; (1048 <spi_m_sync_start_read_block+0xbc>)
+    100c:	4b10      	ldr	r3, [pc, #64]	; (1050 <spi_m_sync_start_read_block+0xc4>)
+			if (token & (SPI_TOKEN_DATA_ERROR_ERROR
+    100e:	f010 0407 	ands.w	r4, r0, #7
+    1012:	d005      	beq.n	1020 <spi_m_sync_start_read_block+0x94>
+				sd_mmc_spi_debug("%s: CRC data error token\n\r", __func__);
+    1014:	480f      	ldr	r0, [pc, #60]	; (1054 <spi_m_sync_start_read_block+0xc8>)
+    1016:	4798      	blx	r3
+			return false;
+    1018:	4638      	mov	r0, r7
+}
+    101a:	b002      	add	sp, #8
+    101c:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
+				sd_mmc_spi_debug("%s: Out of range data error token\n\r", __func__);
+    1020:	480d      	ldr	r0, [pc, #52]	; (1058 <spi_m_sync_start_read_block+0xcc>)
+    1022:	e7d7      	b.n	fd4 <spi_m_sync_start_read_block+0x48>
+	} while (token != SPI_TOKEN_SINGLE_MULTI_READ);
+    1024:	28fe      	cmp	r0, #254	; 0xfe
+    1026:	d1d0      	bne.n	fca <spi_m_sync_start_read_block+0x3e>
+	return true;
+    1028:	2001      	movs	r0, #1
+    102a:	e7f6      	b.n	101a <spi_m_sync_start_read_block+0x8e>
+    102c:	00001521 	.word	0x00001521
+    1030:	00002169 	.word	0x00002169
+    1034:	000002a5 	.word	0x000002a5
+    1038:	200002cc 	.word	0x200002cc
+    103c:	00002b25 	.word	0x00002b25
+    1040:	00002cc8 	.word	0x00002cc8
+    1044:	0007a121 	.word	0x0007a121
+    1048:	00002f1f 	.word	0x00002f1f
+    104c:	00002cdf 	.word	0x00002cdf
+    1050:	000020d5 	.word	0x000020d5
+    1054:	00002cf9 	.word	0x00002cf9
+    1058:	00002d14 	.word	0x00002d14
+    105c:	000002d5 	.word	0x000002d5
+
+00001060 <spi_m_sync_adtc_start>:
+	return spi_m_sync_adtc_start(spi, cmd, arg, 0, 0, false);
+}
+bool spi_m_sync_adtc_start(struct spi_m_sync_descriptor* spi,
+                           uint32_t cmd, uint32_t arg, uint16_t block_size,
+                           uint16_t nb_block, bool access_block)
+{
+    1060:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
+    1064:	b089      	sub	sp, #36	; 0x24
+    1066:	460e      	mov	r6, r1
+	struct io_descriptor* spi_inst = NULL;
+    1068:	2400      	movs	r4, #0
+{
+    106a:	9302      	str	r3, [sp, #8]
+	spi_m_sync_get_io_descriptor(spi, &spi_inst);
+    106c:	a905      	add	r1, sp, #20
+    106e:	4b66      	ldr	r3, [pc, #408]	; (1208 <spi_m_sync_adtc_start+0x1a8>)
+	struct io_descriptor* spi_inst = NULL;
+    1070:	9405      	str	r4, [sp, #20]
+{
+    1072:	4615      	mov	r5, r2
+    1074:	4682      	mov	sl, r0
+	spi_m_sync_get_io_descriptor(spi, &spi_inst);
+    1076:	4798      	blx	r3
+	uint8_t dummy = 0xFF;
+    1078:	23ff      	movs	r3, #255	; 0xff
+	uint8_t ncr_timeout;
+	uint8_t r1;
+	uint8_t dummy2 = 0xFF;
+
+	(void)access_block;
+	assert(cmd & SDMMC_RESP_PRESENT, "No SD Card response was present...");
+    107a:	4a64      	ldr	r2, [pc, #400]	; (120c <spi_m_sync_adtc_start+0x1ac>)
+    107c:	4f64      	ldr	r7, [pc, #400]	; (1210 <spi_m_sync_adtc_start+0x1b0>)
+	uint8_t dummy = 0xFF;
+    107e:	f88d 3011 	strb.w	r3, [sp, #17]
+	uint8_t dummy2 = 0xFF;
+    1082:	f88d 3013 	strb.w	r3, [sp, #19]
+	assert(cmd & SDMMC_RESP_PRESENT, "No SD Card response was present...");
+    1086:	4963      	ldr	r1, [pc, #396]	; (1214 <spi_m_sync_adtc_start+0x1b4>)
+    1088:	23f7      	movs	r3, #247	; 0xf7
+    108a:	f3c6 2000 	ubfx	r0, r6, #8, #1
+	sd_mmc_spi_err = SD_MMC_SPI_NO_ERR;
+
+	cmd_token[0] = SPI_CMD_ENCODE(SDMMC_CMD_GET_INDEX(cmd));
+    108e:	f006 093f 	and.w	r9, r6, #63	; 0x3f
+	assert(cmd & SDMMC_RESP_PRESENT, "No SD Card response was present...");
+    1092:	47b8      	blx	r7
+	cmd_token[0] = SPI_CMD_ENCODE(SDMMC_CMD_GET_INDEX(cmd));
+    1094:	f049 0340 	orr.w	r3, r9, #64	; 0x40
+    1098:	f88d 3018 	strb.w	r3, [sp, #24]
+	cmd_token[1] = arg >> 24;
+    109c:	0e2b      	lsrs	r3, r5, #24
+    109e:	f88d 3019 	strb.w	r3, [sp, #25]
+	cmd_token[2] = arg >> 16;
+    10a2:	0c2b      	lsrs	r3, r5, #16
+    10a4:	f88d 301a 	strb.w	r3, [sp, #26]
+	cmd_token[3] = arg >> 8;
+	cmd_token[4] = arg;
+    10a8:	af06      	add	r7, sp, #24
+	cmd_token[3] = arg >> 8;
+    10aa:	0a2b      	lsrs	r3, r5, #8
+    10ac:	f88d 301b 	strb.w	r3, [sp, #27]
+	cmd_token[4] = arg;
+    10b0:	f88d 501c 	strb.w	r5, [sp, #28]
+	crc = 0;
+    10b4:	4623      	mov	r3, r4
+	cmd_token[4] = arg;
+    10b6:	2206      	movs	r2, #6
+    10b8:	463c      	mov	r4, r7
+	while (size--) {
+    10ba:	3a01      	subs	r2, #1
+    10bc:	f012 02ff 	ands.w	r2, r2, #255	; 0xff
+    10c0:	d12f      	bne.n	1122 <spi_m_sync_adtc_start+0xc2>
+	crc = (crc << 1) | 1;
+    10c2:	005b      	lsls	r3, r3, #1
+    10c4:	f043 0301 	orr.w	r3, r3, #1
+	cmd_token[5] = spi_m_sync_crc7(cmd_token, 5);
+
+
+	// 8 cycles to respect Ncs timing
+	io_write(spi_inst, &dummy, 1);
+    10c8:	f8df 8174 	ldr.w	r8, [pc, #372]	; 1240 <spi_m_sync_adtc_start+0x1e0>
+    10cc:	9805      	ldr	r0, [sp, #20]
+	cmd_token[5] = spi_m_sync_crc7(cmd_token, 5);
+    10ce:	f88d 301d 	strb.w	r3, [sp, #29]
+	io_write(spi_inst, &dummy, 1);
+    10d2:	2201      	movs	r2, #1
+    10d4:	f10d 0111 	add.w	r1, sp, #17
+    10d8:	47c0      	blx	r8
+	// send command
+	io_write(spi_inst, cmd_token, sizeof(cmd_token));
+    10da:	4621      	mov	r1, r4
+    10dc:	2206      	movs	r2, #6
+    10de:	9805      	ldr	r0, [sp, #20]
+	// Two retries will be done to manage the Ncr timing between command and response
+	// Ncr: Min. 1x8 clock cycle, Max 8x8 clock cycles
+	// WORKAROUND for no compliance (Atmel Internal ref. SD13)
+	r1 = 0xFF;
+	// Ignore first byte because Ncr min. = 8 clock cycles
+	io_read(spi_inst, &r1, 1);
+    10e0:	4f4d      	ldr	r7, [pc, #308]	; (1218 <spi_m_sync_adtc_start+0x1b8>)
+	io_write(spi_inst, cmd_token, sizeof(cmd_token));
+    10e2:	47c0      	blx	r8
+	r1 = 0xFF;
+    10e4:	23ff      	movs	r3, #255	; 0xff
+	io_read(spi_inst, &r1, 1);
+    10e6:	9805      	ldr	r0, [sp, #20]
+	r1 = 0xFF;
+    10e8:	f88d 3012 	strb.w	r3, [sp, #18]
+	io_read(spi_inst, &r1, 1);
+    10ec:	2201      	movs	r2, #1
+    10ee:	f10d 0112 	add.w	r1, sp, #18
+    10f2:	47b8      	blx	r7
+    10f4:	2407      	movs	r4, #7
+	ncr_timeout = 7;
+
+	while(1)
+	{
+		io_read(spi_inst, &r1, 1);
+    10f6:	2201      	movs	r2, #1
+    10f8:	9805      	ldr	r0, [sp, #20]
+    10fa:	f10d 0112 	add.w	r1, sp, #18
+    10fe:	47b8      	blx	r7
+		if((r1 & R1_SPI_ERROR) == 0)
+    1100:	f99d 3012 	ldrsb.w	r3, [sp, #18]
+    1104:	f89d 2012 	ldrb.w	r2, [sp, #18]
+    1108:	2b00      	cmp	r3, #0
+    110a:	da1e      	bge.n	114a <spi_m_sync_adtc_start+0xea>
+		{
+			// Valid response
+			break;
+		}
+		if(--ncr_timeout == 0)
+    110c:	3c01      	subs	r4, #1
+    110e:	f014 04ff 	ands.w	r4, r4, #255	; 0xff
+    1112:	d1f0      	bne.n	10f6 <spi_m_sync_adtc_start+0x96>
+		{
+			// Here valid r1 response received
+			sd_mmc_spi_debug("%s: cmd %02d, arg 0x%08lX, R1 timeout\r\n",
+    1114:	4941      	ldr	r1, [pc, #260]	; (121c <spi_m_sync_adtc_start+0x1bc>)
+    1116:	4842      	ldr	r0, [pc, #264]	; (1220 <spi_m_sync_adtc_start+0x1c0>)
+    1118:	462b      	mov	r3, r5
+    111a:	464a      	mov	r2, r9
+
+	// Manage other responses
+	if (cmd & SDMMC_RESP_BUSY) {
+		if (!spi_m_sync_wait_busy(spi)) {
+			sd_mmc_spi_err = SD_MMC_SPI_ERR_RESP_BUSY_TIMEOUT;
+			sd_mmc_spi_debug("%s: cmd %02d, arg 0x%08lx, Busy signal always high\n\r",
+    111c:	4d41      	ldr	r5, [pc, #260]	; (1224 <spi_m_sync_adtc_start+0x1c4>)
+    111e:	47a8      	blx	r5
+							 __func__, (int)SDMMC_CMD_GET_INDEX(cmd), arg);
+			return false;
+    1120:	e023      	b.n	116a <spi_m_sync_adtc_start+0x10a>
+		value = *buf++;
+    1122:	f817 0b01 	ldrb.w	r0, [r7], #1
+    1126:	2108      	movs	r1, #8
+			crc <<= 1;
+    1128:	005b      	lsls	r3, r3, #1
+    112a:	b2db      	uxtb	r3, r3
+			if ((value & 0x80) ^ (crc & 0x80)) {
+    112c:	ea83 0c00 	eor.w	ip, r3, r0
+    1130:	f01c 0f80 	tst.w	ip, #128	; 0x80
+		for (i = 0; i < 8; i++) {
+    1134:	f101 31ff 	add.w	r1, r1, #4294967295	; 0xffffffff
+				crc ^= 0x09;
+    1138:	bf18      	it	ne
+    113a:	f083 0309 	eorne.w	r3, r3, #9
+			value <<= 1;
+    113e:	0040      	lsls	r0, r0, #1
+		for (i = 0; i < 8; i++) {
+    1140:	f011 01ff 	ands.w	r1, r1, #255	; 0xff
+			value <<= 1;
+    1144:	b2c0      	uxtb	r0, r0
+		for (i = 0; i < 8; i++) {
+    1146:	d1ef      	bne.n	1128 <spi_m_sync_adtc_start+0xc8>
+    1148:	e7b7      	b.n	10ba <spi_m_sync_adtc_start+0x5a>
+	sd_mmc_spi_response_32 = r1;
+    114a:	f8df b0f8 	ldr.w	fp, [pc, #248]	; 1244 <spi_m_sync_adtc_start+0x1e4>
+	if (r1 & R1_SPI_COM_CRC)
+    114e:	f012 0308 	ands.w	r3, r2, #8
+	sd_mmc_spi_response_32 = r1;
+    1152:	f8cb 2008 	str.w	r2, [fp, #8]
+	if (r1 & R1_SPI_COM_CRC)
+    1156:	9303      	str	r3, [sp, #12]
+    1158:	d00b      	beq.n	1172 <spi_m_sync_adtc_start+0x112>
+		sd_mmc_spi_debug("%s: cmd %02d, arg 0x%08lx, r1 0x%02x, R1_SPI_COM_CRC\n\r",
+    115a:	4930      	ldr	r1, [pc, #192]	; (121c <spi_m_sync_adtc_start+0x1bc>)
+    115c:	4832      	ldr	r0, [pc, #200]	; (1228 <spi_m_sync_adtc_start+0x1c8>)
+    115e:	9200      	str	r2, [sp, #0]
+    1160:	462b      	mov	r3, r5
+    1162:	464a      	mov	r2, r9
+    1164:	4c2f      	ldr	r4, [pc, #188]	; (1224 <spi_m_sync_adtc_start+0x1c4>)
+    1166:	47a0      	blx	r4
+		return false;
+    1168:	2400      	movs	r4, #0
+
+	sd_mmc_spi_block_size = block_size;
+	sd_mmc_spi_nb_block = nb_block;
+	sd_mmc_spi_transfert_pos = 0;
+	return true;
+}
+    116a:	4620      	mov	r0, r4
+    116c:	b009      	add	sp, #36	; 0x24
+    116e:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
+	if (r1 & R1_SPI_ILLEGAL_COMMAND)
+    1172:	f012 0404 	ands.w	r4, r2, #4
+    1176:	d005      	beq.n	1184 <spi_m_sync_adtc_start+0x124>
+		sd_mmc_spi_debug("%s: cmd %02d, arg 0x%08lx, r1 0x%x, R1 ILLEGAL_COMMAND\n\r",
+    1178:	9200      	str	r2, [sp, #0]
+    117a:	4928      	ldr	r1, [pc, #160]	; (121c <spi_m_sync_adtc_start+0x1bc>)
+    117c:	482b      	ldr	r0, [pc, #172]	; (122c <spi_m_sync_adtc_start+0x1cc>)
+    117e:	462b      	mov	r3, r5
+    1180:	464a      	mov	r2, r9
+    1182:	e7ef      	b.n	1164 <spi_m_sync_adtc_start+0x104>
+	if (r1 & ~R1_SPI_IDLE) {
+    1184:	f012 0ffe 	tst.w	r2, #254	; 0xfe
+    1188:	d007      	beq.n	119a <spi_m_sync_adtc_start+0x13a>
+		sd_mmc_spi_debug("%s: cmd %02d, arg 0x%08lx, r1 0x%x, R1 error\n\r",
+    118a:	9200      	str	r2, [sp, #0]
+    118c:	462b      	mov	r3, r5
+    118e:	4923      	ldr	r1, [pc, #140]	; (121c <spi_m_sync_adtc_start+0x1bc>)
+    1190:	4d24      	ldr	r5, [pc, #144]	; (1224 <spi_m_sync_adtc_start+0x1c4>)
+    1192:	4827      	ldr	r0, [pc, #156]	; (1230 <spi_m_sync_adtc_start+0x1d0>)
+    1194:	464a      	mov	r2, r9
+    1196:	47a8      	blx	r5
+		return false;
+    1198:	e7e7      	b.n	116a <spi_m_sync_adtc_start+0x10a>
+	if (cmd & SDMMC_RESP_BUSY) {
+    119a:	04b1      	lsls	r1, r6, #18
+    119c:	d509      	bpl.n	11b2 <spi_m_sync_adtc_start+0x152>
+		if (!spi_m_sync_wait_busy(spi)) {
+    119e:	4a25      	ldr	r2, [pc, #148]	; (1234 <spi_m_sync_adtc_start+0x1d4>)
+    11a0:	4650      	mov	r0, sl
+    11a2:	4790      	blx	r2
+    11a4:	4604      	mov	r4, r0
+    11a6:	b920      	cbnz	r0, 11b2 <spi_m_sync_adtc_start+0x152>
+			sd_mmc_spi_debug("%s: cmd %02d, arg 0x%08lx, Busy signal always high\n\r",
+    11a8:	491c      	ldr	r1, [pc, #112]	; (121c <spi_m_sync_adtc_start+0x1bc>)
+    11aa:	4823      	ldr	r0, [pc, #140]	; (1238 <spi_m_sync_adtc_start+0x1d8>)
+    11ac:	462b      	mov	r3, r5
+    11ae:	464a      	mov	r2, r9
+    11b0:	e7b4      	b.n	111c <spi_m_sync_adtc_start+0xbc>
+	if (cmd & SDMMC_RESP_8) {
+    11b2:	05b2      	lsls	r2, r6, #22
+    11b4:	d50b      	bpl.n	11ce <spi_m_sync_adtc_start+0x16e>
+		sd_mmc_spi_response_32 = 0;
+    11b6:	2200      	movs	r2, #0
+    11b8:	f8cb 2008 	str.w	r2, [fp, #8]
+		io_write(spi_inst, &dummy2, 1);
+    11bc:	f10d 0113 	add.w	r1, sp, #19
+    11c0:	2201      	movs	r2, #1
+    11c2:	9805      	ldr	r0, [sp, #20]
+    11c4:	47c0      	blx	r8
+		io_read(spi_inst, (uint8_t*)&sd_mmc_spi_response_32, 1);
+    11c6:	491d      	ldr	r1, [pc, #116]	; (123c <spi_m_sync_adtc_start+0x1dc>)
+    11c8:	9805      	ldr	r0, [sp, #20]
+    11ca:	2201      	movs	r2, #1
+    11cc:	47b8      	blx	r7
+	if (cmd & SDMMC_RESP_32) {
+    11ce:	0573      	lsls	r3, r6, #21
+    11d0:	d50d      	bpl.n	11ee <spi_m_sync_adtc_start+0x18e>
+		io_write(spi_inst, &dummy2, 1);
+    11d2:	2201      	movs	r2, #1
+    11d4:	f10d 0113 	add.w	r1, sp, #19
+    11d8:	9805      	ldr	r0, [sp, #20]
+    11da:	47c0      	blx	r8
+		io_read(spi_inst, (uint8_t*)&sd_mmc_spi_response_32, 4);
+    11dc:	2204      	movs	r2, #4
+    11de:	4917      	ldr	r1, [pc, #92]	; (123c <spi_m_sync_adtc_start+0x1dc>)
+    11e0:	9805      	ldr	r0, [sp, #20]
+    11e2:	47b8      	blx	r7
+		sd_mmc_spi_response_32 = BE32(sd_mmc_spi_response_32);
+    11e4:	f8db 2008 	ldr.w	r2, [fp, #8]
+    11e8:	ba12      	rev	r2, r2
+    11ea:	f8cb 2008 	str.w	r2, [fp, #8]
+	sd_mmc_spi_nb_block = nb_block;
+    11ee:	f8bd 2048 	ldrh.w	r2, [sp, #72]	; 0x48
+	sd_mmc_spi_block_size = block_size;
+    11f2:	9b02      	ldr	r3, [sp, #8]
+	sd_mmc_spi_nb_block = nb_block;
+    11f4:	f8ab 2006 	strh.w	r2, [fp, #6]
+	sd_mmc_spi_transfert_pos = 0;
+    11f8:	2200      	movs	r2, #0
+	sd_mmc_spi_block_size = block_size;
+    11fa:	f8ab 3004 	strh.w	r3, [fp, #4]
+	sd_mmc_spi_transfert_pos = 0;
+    11fe:	f8cb 2000 	str.w	r2, [fp]
+	return true;
+    1202:	2401      	movs	r4, #1
+    1204:	e7b1      	b.n	116a <spi_m_sync_adtc_start+0x10a>
+    1206:	bf00      	nop
+    1208:	00001521 	.word	0x00001521
+    120c:	00002cc8 	.word	0x00002cc8
+    1210:	00002169 	.word	0x00002169
+    1214:	00002de1 	.word	0x00002de1
+    1218:	000002d5 	.word	0x000002d5
+    121c:	00002f78 	.word	0x00002f78
+    1220:	00002e04 	.word	0x00002e04
+    1224:	000020d5 	.word	0x000020d5
+    1228:	00002e2c 	.word	0x00002e2c
+    122c:	00002e63 	.word	0x00002e63
+    1230:	00002e9c 	.word	0x00002e9c
+    1234:	00000ed1 	.word	0x00000ed1
+    1238:	00002ecb 	.word	0x00002ecb
+    123c:	200002d4 	.word	0x200002d4
+    1240:	000002a5 	.word	0x000002a5
+    1244:	200002cc 	.word	0x200002cc
+
+00001248 <spi_m_sync_send_cmd>:
+{
+    1248:	b513      	push	{r0, r1, r4, lr}
+	return spi_m_sync_adtc_start(spi, cmd, arg, 0, 0, false);
+    124a:	2300      	movs	r3, #0
+    124c:	e9cd 3300 	strd	r3, r3, [sp]
+    1250:	4c01      	ldr	r4, [pc, #4]	; (1258 <spi_m_sync_send_cmd+0x10>)
+    1252:	47a0      	blx	r4
+}
+    1254:	b002      	add	sp, #8
+    1256:	bd10      	pop	{r4, pc}
+    1258:	00001061 	.word	0x00001061
+
+0000125c <spi_m_sync_start_read_blocks>:
+bool spi_m_sync_start_read_blocks(struct spi_m_sync_descriptor* spi,
+                                  void *dst, uint16_t nb_block)
+{
+    125c:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
+	struct io_descriptor* spi_inst = NULL;
+	spi_m_sync_get_io_descriptor(spi, &spi_inst);
+    1260:	4b20      	ldr	r3, [pc, #128]	; (12e4 <spi_m_sync_start_read_blocks+0x88>)
+	uint8_t dummy = 0xFF;
+
+	sd_mmc_spi_err = SD_MMC_SPI_NO_ERR;
+	pos = 0;
+	while (nb_block--) {
+		assert(sd_mmc_spi_nb_block >
+    1262:	4d21      	ldr	r5, [pc, #132]	; (12e8 <spi_m_sync_start_read_blocks+0x8c>)
+    1264:	f8df 9094 	ldr.w	r9, [pc, #148]	; 12fc <spi_m_sync_start_read_blocks+0xa0>
+    1268:	f8df a094 	ldr.w	sl, [pc, #148]	; 1300 <spi_m_sync_start_read_blocks+0xa4>
+{
+    126c:	4688      	mov	r8, r1
+	struct io_descriptor* spi_inst = NULL;
+    126e:	2600      	movs	r6, #0
+	spi_m_sync_get_io_descriptor(spi, &spi_inst);
+    1270:	a901      	add	r1, sp, #4
+{
+    1272:	4607      	mov	r7, r0
+    1274:	4614      	mov	r4, r2
+	struct io_descriptor* spi_inst = NULL;
+    1276:	9601      	str	r6, [sp, #4]
+	spi_m_sync_get_io_descriptor(spi, &spi_inst);
+    1278:	4798      	blx	r3
+	uint8_t dummy = 0xFF;
+    127a:	23ff      	movs	r3, #255	; 0xff
+    127c:	f88d 3003 	strb.w	r3, [sp, #3]
+	while (nb_block--) {
+    1280:	b91c      	cbnz	r4, 128a <spi_m_sync_start_read_blocks+0x2e>
+		pos += sd_mmc_spi_block_size;
+		sd_mmc_spi_transfert_pos += sd_mmc_spi_block_size;
+
+		spi_m_sync_stop_read_block(spi);
+	}
+	return true;
+    1282:	2001      	movs	r0, #1
+}
+    1284:	b003      	add	sp, #12
+    1286:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
+		assert(sd_mmc_spi_nb_block >
+    128a:	f8b5 c006 	ldrh.w	ip, [r5, #6]
+    128e:	682b      	ldr	r3, [r5, #0]
+    1290:	88a8      	ldrh	r0, [r5, #4]
+    1292:	fbb3 f0f0 	udiv	r0, r3, r0
+    1296:	4584      	cmp	ip, r0
+    1298:	bf94      	ite	ls
+    129a:	2000      	movls	r0, #0
+    129c:	2001      	movhi	r0, #1
+    129e:	f44f 73b2 	mov.w	r3, #356	; 0x164
+    12a2:	464a      	mov	r2, r9
+    12a4:	4651      	mov	r1, sl
+    12a6:	f8df b05c 	ldr.w	fp, [pc, #92]	; 1304 <spi_m_sync_start_read_blocks+0xa8>
+    12aa:	47d8      	blx	fp
+		if (!spi_m_sync_start_read_block(spi)) {
+    12ac:	4b0f      	ldr	r3, [pc, #60]	; (12ec <spi_m_sync_start_read_blocks+0x90>)
+    12ae:	4638      	mov	r0, r7
+    12b0:	4798      	blx	r3
+    12b2:	3c01      	subs	r4, #1
+    12b4:	b2a4      	uxth	r4, r4
+    12b6:	2800      	cmp	r0, #0
+    12b8:	d0e4      	beq.n	1284 <spi_m_sync_start_read_blocks+0x28>
+		io_write(spi_inst, &dummy, 1);
+    12ba:	f10d 0103 	add.w	r1, sp, #3
+    12be:	9801      	ldr	r0, [sp, #4]
+    12c0:	4b0b      	ldr	r3, [pc, #44]	; (12f0 <spi_m_sync_start_read_blocks+0x94>)
+    12c2:	2201      	movs	r2, #1
+    12c4:	4798      	blx	r3
+		io_read(spi_inst, &((uint8_t*)dst)[pos], sd_mmc_spi_block_size);
+    12c6:	88aa      	ldrh	r2, [r5, #4]
+    12c8:	9801      	ldr	r0, [sp, #4]
+    12ca:	4b0a      	ldr	r3, [pc, #40]	; (12f4 <spi_m_sync_start_read_blocks+0x98>)
+    12cc:	eb08 0106 	add.w	r1, r8, r6
+    12d0:	4798      	blx	r3
+		pos += sd_mmc_spi_block_size;
+    12d2:	88aa      	ldrh	r2, [r5, #4]
+		sd_mmc_spi_transfert_pos += sd_mmc_spi_block_size;
+    12d4:	682b      	ldr	r3, [r5, #0]
+    12d6:	4413      	add	r3, r2
+    12d8:	602b      	str	r3, [r5, #0]
+		spi_m_sync_stop_read_block(spi);
+    12da:	4638      	mov	r0, r7
+    12dc:	4b06      	ldr	r3, [pc, #24]	; (12f8 <spi_m_sync_start_read_blocks+0x9c>)
+		pos += sd_mmc_spi_block_size;
+    12de:	4416      	add	r6, r2
+		spi_m_sync_stop_read_block(spi);
+    12e0:	4798      	blx	r3
+    12e2:	e7cd      	b.n	1280 <spi_m_sync_start_read_blocks+0x24>
+    12e4:	00001521 	.word	0x00001521
+    12e8:	200002cc 	.word	0x200002cc
+    12ec:	00000f8d 	.word	0x00000f8d
+    12f0:	000002a5 	.word	0x000002a5
+    12f4:	000002d5 	.word	0x000002d5
+    12f8:	00000f51 	.word	0x00000f51
+    12fc:	00002cc8 	.word	0x00002cc8
+    1300:	00002b25 	.word	0x00002b25
+    1304:	00002169 	.word	0x00002169
+
+00001308 <spi_m_sync_wait_end_of_read_blocks>:
+}
+
+bool spi_m_sync_wait_end_of_read_blocks(struct spi_m_sync_descriptor* spi)
+{
+	return true;
+}
+    1308:	2001      	movs	r0, #1
+    130a:	4770      	bx	lr
+
+0000130c <spi_m_sync_read_word>:
+	}
+	return spi_m_sync_stop_multiwrite_block(spi);
+}
+
+bool spi_m_sync_read_word(struct spi_m_sync_descriptor* spi, uint32_t* value)
+{
+    130c:	b57f      	push	{r0, r1, r2, r3, r4, r5, r6, lr}
+	struct io_descriptor* spi_inst = NULL;
+	spi_m_sync_get_io_descriptor(spi, &spi_inst);
+	uint8_t dummy = 0xFF;
+
+	sd_mmc_spi_err = SD_MMC_SPI_NO_ERR;
+	assert(sd_mmc_spi_nb_block >
+    130e:	4c21      	ldr	r4, [pc, #132]	; (1394 <spi_m_sync_read_word+0x88>)
+{
+    1310:	9101      	str	r1, [sp, #4]
+	struct io_descriptor* spi_inst = NULL;
+    1312:	2300      	movs	r3, #0
+    1314:	9303      	str	r3, [sp, #12]
+	spi_m_sync_get_io_descriptor(spi, &spi_inst);
+    1316:	a903      	add	r1, sp, #12
+    1318:	4b1f      	ldr	r3, [pc, #124]	; (1398 <spi_m_sync_read_word+0x8c>)
+{
+    131a:	4605      	mov	r5, r0
+	spi_m_sync_get_io_descriptor(spi, &spi_inst);
+    131c:	4798      	blx	r3
+	assert(sd_mmc_spi_nb_block >
+    131e:	88e6      	ldrh	r6, [r4, #6]
+    1320:	88a0      	ldrh	r0, [r4, #4]
+    1322:	4a1e      	ldr	r2, [pc, #120]	; (139c <spi_m_sync_read_word+0x90>)
+    1324:	491e      	ldr	r1, [pc, #120]	; (13a0 <spi_m_sync_read_word+0x94>)
+	uint8_t dummy = 0xFF;
+    1326:	23ff      	movs	r3, #255	; 0xff
+    1328:	f88d 300b 	strb.w	r3, [sp, #11]
+	assert(sd_mmc_spi_nb_block >
+    132c:	6823      	ldr	r3, [r4, #0]
+    132e:	fbb3 f0f0 	udiv	r0, r3, r0
+    1332:	4286      	cmp	r6, r0
+    1334:	f44f 73e7 	mov.w	r3, #462	; 0x1ce
+    1338:	4e1a      	ldr	r6, [pc, #104]	; (13a4 <spi_m_sync_read_word+0x98>)
+    133a:	bf94      	ite	ls
+    133c:	2000      	movls	r0, #0
+    133e:	2001      	movhi	r0, #1
+    1340:	47b0      	blx	r6
+		   (sd_mmc_spi_transfert_pos / sd_mmc_spi_block_size),
+		">>>");
+
+	if (!(sd_mmc_spi_transfert_pos % sd_mmc_spi_block_size)) {
+    1342:	88a2      	ldrh	r2, [r4, #4]
+    1344:	6823      	ldr	r3, [r4, #0]
+    1346:	fbb3 f1f2 	udiv	r1, r3, r2
+    134a:	fb02 3311 	mls	r3, r2, r1, r3
+    134e:	b1b3      	cbz	r3, 137e <spi_m_sync_read_word+0x72>
+		if (!spi_m_sync_start_read_block(spi)) {
+			return false;
+		}
+	}
+	// Read data
+	io_write(spi_inst, &dummy, 1);
+    1350:	4b15      	ldr	r3, [pc, #84]	; (13a8 <spi_m_sync_read_word+0x9c>)
+    1352:	9803      	ldr	r0, [sp, #12]
+    1354:	2201      	movs	r2, #1
+    1356:	f10d 010b 	add.w	r1, sp, #11
+    135a:	4798      	blx	r3
+	io_read(spi_inst, (uint8_t*)&value, 4);
+    135c:	2204      	movs	r2, #4
+    135e:	eb0d 0102 	add.w	r1, sp, r2
+    1362:	4b12      	ldr	r3, [pc, #72]	; (13ac <spi_m_sync_read_word+0xa0>)
+    1364:	9803      	ldr	r0, [sp, #12]
+    1366:	4798      	blx	r3
+	*value = LE32(*value);
+	sd_mmc_spi_transfert_pos += 4;
+    1368:	6823      	ldr	r3, [r4, #0]
+
+	if (!(sd_mmc_spi_transfert_pos % sd_mmc_spi_block_size)) {
+    136a:	88a2      	ldrh	r2, [r4, #4]
+	sd_mmc_spi_transfert_pos += 4;
+    136c:	3304      	adds	r3, #4
+    136e:	6023      	str	r3, [r4, #0]
+	if (!(sd_mmc_spi_transfert_pos % sd_mmc_spi_block_size)) {
+    1370:	fbb3 f1f2 	udiv	r1, r3, r2
+    1374:	fb02 3311 	mls	r3, r2, r1, r3
+    1378:	b143      	cbz	r3, 138c <spi_m_sync_read_word+0x80>
+		// End of block
+		spi_m_sync_stop_read_block(spi);
+	}
+	return true;}
+    137a:	2001      	movs	r0, #1
+    137c:	e004      	b.n	1388 <spi_m_sync_read_word+0x7c>
+		if (!spi_m_sync_start_read_block(spi)) {
+    137e:	4b0c      	ldr	r3, [pc, #48]	; (13b0 <spi_m_sync_read_word+0xa4>)
+    1380:	4628      	mov	r0, r5
+    1382:	4798      	blx	r3
+    1384:	2800      	cmp	r0, #0
+    1386:	d1e3      	bne.n	1350 <spi_m_sync_read_word+0x44>
+	return true;}
+    1388:	b004      	add	sp, #16
+    138a:	bd70      	pop	{r4, r5, r6, pc}
+		spi_m_sync_stop_read_block(spi);
+    138c:	4b09      	ldr	r3, [pc, #36]	; (13b4 <spi_m_sync_read_word+0xa8>)
+    138e:	4628      	mov	r0, r5
+    1390:	4798      	blx	r3
+    1392:	e7f2      	b.n	137a <spi_m_sync_read_word+0x6e>
+    1394:	200002cc 	.word	0x200002cc
+    1398:	00001521 	.word	0x00001521
+    139c:	00002cc8 	.word	0x00002cc8
+    13a0:	00002b25 	.word	0x00002b25
+    13a4:	00002169 	.word	0x00002169
+    13a8:	000002a5 	.word	0x000002a5
+    13ac:	000002d5 	.word	0x000002d5
+    13b0:	00000f8d 	.word	0x00000f8d
+    13b4:	00000f51 	.word	0x00000f51
+
+000013b8 <spi_m_sync_get_response>:
+
+uint32_t spi_m_sync_get_response(struct spi_m_sync_descriptor* spi)
+{
+	return sd_mmc_spi_response_32;
+}
+    13b8:	4b01      	ldr	r3, [pc, #4]	; (13c0 <spi_m_sync_get_response+0x8>)
+    13ba:	6898      	ldr	r0, [r3, #8]
+    13bc:	4770      	bx	lr
+    13be:	bf00      	nop
+    13c0:	200002cc 	.word	0x200002cc
+
+000013c4 <spi_m_sync_send_clock>:
+
+
+void spi_m_sync_send_clock(struct spi_m_sync_descriptor* spi)
+{
+    13c4:	b537      	push	{r0, r1, r2, r4, r5, lr}
+	struct io_descriptor* spi_inst = NULL;
+    13c6:	2300      	movs	r3, #0
+    13c8:	9301      	str	r3, [sp, #4]
+	spi_m_sync_get_io_descriptor(spi, &spi_inst);
+    13ca:	a901      	add	r1, sp, #4
+    13cc:	4b08      	ldr	r3, [pc, #32]	; (13f0 <spi_m_sync_send_clock+0x2c>)
+
+	sd_mmc_spi_err = SD_MMC_SPI_NO_ERR;
+	// Send 80 cycles
+	for(i = 0; i < 10; i++)
+	{
+		io_write(spi_inst, &dummy, 1); // 8 cycles
+    13ce:	4d09      	ldr	r5, [pc, #36]	; (13f4 <spi_m_sync_send_clock+0x30>)
+	spi_m_sync_get_io_descriptor(spi, &spi_inst);
+    13d0:	4798      	blx	r3
+	uint8_t dummy = 0xFF;
+    13d2:	23ff      	movs	r3, #255	; 0xff
+    13d4:	f88d 3003 	strb.w	r3, [sp, #3]
+    13d8:	240a      	movs	r4, #10
+		io_write(spi_inst, &dummy, 1); // 8 cycles
+    13da:	9801      	ldr	r0, [sp, #4]
+    13dc:	2201      	movs	r2, #1
+    13de:	f10d 0103 	add.w	r1, sp, #3
+	for(i = 0; i < 10; i++)
+    13e2:	3c01      	subs	r4, #1
+		io_write(spi_inst, &dummy, 1); // 8 cycles
+    13e4:	47a8      	blx	r5
+	for(i = 0; i < 10; i++)
+    13e6:	f014 04ff 	ands.w	r4, r4, #255	; 0xff
+    13ea:	d1f6      	bne.n	13da <spi_m_sync_send_clock+0x16>
+	}
+}
+    13ec:	b003      	add	sp, #12
+    13ee:	bd30      	pop	{r4, r5, pc}
+    13f0:	00001521 	.word	0x00001521
+    13f4:	000002a5 	.word	0x000002a5
+
+000013f8 <spi_m_sync_select_device>:
+int32_t spi_m_sync_select_device(struct spi_m_sync_descriptor* spi, uint8_t slot, uint32_t clock, uint8_t bus_width, bool high_speed)
+{
+	UNUSED(bus_width);
+	UNUSED(high_speed);
+	sd_mmc_spi_err = SD_MMC_SPI_NO_ERR;
+	PORT->Group[SPI_CS_PORT].OUT.reg &= ~(1 << SPI_CS_PIN);
+    13f8:	4a04      	ldr	r2, [pc, #16]	; (140c <spi_m_sync_select_device+0x14>)
+    13fa:	f8d2 3090 	ldr.w	r3, [r2, #144]	; 0x90
+    13fe:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
+    1402:	f8c2 3090 	str.w	r3, [r2, #144]	; 0x90
+
+	return 0;
+}
+    1406:	2000      	movs	r0, #0
+    1408:	4770      	bx	lr
+    140a:	bf00      	nop
+    140c:	41008000 	.word	0x41008000
+
+00001410 <spi_m_sync_deselect_device>:
+
+int32_t spi_m_sync_deselect_device(struct spi_m_sync_descriptor* spi, uint8_t slot)
+{
+	sd_mmc_spi_err = SD_MMC_SPI_NO_ERR;
+	PORT->Group[1].OUT.reg |= (1 << SPI_CS_PIN);
+    1410:	4a04      	ldr	r2, [pc, #16]	; (1424 <spi_m_sync_deselect_device+0x14>)
+    1412:	f8d2 3090 	ldr.w	r3, [r2, #144]	; 0x90
+    1416:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
+    141a:	f8c2 3090 	str.w	r3, [r2, #144]	; 0x90
+	return 0;
+}
+    141e:	2000      	movs	r0, #0
+    1420:	4770      	bx	lr
+    1422:	bf00      	nop
+    1424:	41008000 	.word	0x41008000
+
+00001428 <spi_m_sync_init>:
+	ASSERT(spi);
+	spi->func = (struct _spi_m_sync_hpl_interface *)func;
+}
+
+int32_t spi_m_sync_init(struct spi_m_sync_descriptor *spi, void *const hw)
+{
+    1428:	b538      	push	{r3, r4, r5, lr}
+    142a:	460d      	mov	r5, r1
+	int32_t rc = 0;
+	ASSERT(spi && hw);
+    142c:	4604      	mov	r4, r0
+    142e:	b110      	cbz	r0, 1436 <spi_m_sync_init+0xe>
+    1430:	1e08      	subs	r0, r1, #0
+    1432:	bf18      	it	ne
+    1434:	2001      	movne	r0, #1
+    1436:	490a      	ldr	r1, [pc, #40]	; (1460 <spi_m_sync_init+0x38>)
+    1438:	4b0a      	ldr	r3, [pc, #40]	; (1464 <spi_m_sync_init+0x3c>)
+    143a:	2240      	movs	r2, #64	; 0x40
+    143c:	4798      	blx	r3
+	spi->dev.prvt = (void *)hw;
+    143e:	4620      	mov	r0, r4
+	rc            = _spi_m_sync_init(&spi->dev, hw);
+    1440:	4b09      	ldr	r3, [pc, #36]	; (1468 <spi_m_sync_init+0x40>)
+	spi->dev.prvt = (void *)hw;
+    1442:	f840 5f04 	str.w	r5, [r0, #4]!
+	rc            = _spi_m_sync_init(&spi->dev, hw);
+    1446:	4629      	mov	r1, r5
+    1448:	4798      	blx	r3
+
+	if (rc < 0) {
+    144a:	2800      	cmp	r0, #0
+    144c:	db07      	blt.n	145e <spi_m_sync_init+0x36>
+		return rc;
+	}
+
+	spi->flags    = SPI_DEACTIVATE_NEXT;
+    144e:	f44f 4300 	mov.w	r3, #32768	; 0x8000
+    1452:	82a3      	strh	r3, [r4, #20]
+	spi->io.read  = _spi_m_sync_io_read;
+    1454:	4b05      	ldr	r3, [pc, #20]	; (146c <spi_m_sync_init+0x44>)
+    1456:	6123      	str	r3, [r4, #16]
+	spi->io.write = _spi_m_sync_io_write;
+    1458:	4b05      	ldr	r3, [pc, #20]	; (1470 <spi_m_sync_init+0x48>)
+    145a:	60e3      	str	r3, [r4, #12]
+
+	return ERR_NONE;
+    145c:	2000      	movs	r0, #0
+}
+    145e:	bd38      	pop	{r3, r4, r5, pc}
+    1460:	00002fe6 	.word	0x00002fe6
+    1464:	00001605 	.word	0x00001605
+    1468:	00001ea5 	.word	0x00001ea5
+    146c:	000014e9 	.word	0x000014e9
+    1470:	000014b1 	.word	0x000014b1
+
+00001474 <spi_m_sync_transfer>:
+
+	return spi_m_sync_transfer(spi, &xfer);
+}
+
+int32_t spi_m_sync_transfer(struct spi_m_sync_descriptor *spi, const struct spi_xfer *p_xfer)
+{
+    1474:	b530      	push	{r4, r5, lr}
+    1476:	460c      	mov	r4, r1
+    1478:	b085      	sub	sp, #20
+	struct spi_msg msg;
+
+	ASSERT(spi && p_xfer);
+    147a:	4605      	mov	r5, r0
+    147c:	b110      	cbz	r0, 1484 <spi_m_sync_transfer+0x10>
+    147e:	1e08      	subs	r0, r1, #0
+    1480:	bf18      	it	ne
+    1482:	2001      	movne	r0, #1
+    1484:	22b3      	movs	r2, #179	; 0xb3
+    1486:	4907      	ldr	r1, [pc, #28]	; (14a4 <spi_m_sync_transfer+0x30>)
+    1488:	4b07      	ldr	r3, [pc, #28]	; (14a8 <spi_m_sync_transfer+0x34>)
+    148a:	4798      	blx	r3
+
+	msg.txbuf = p_xfer->txbuf;
+    148c:	6823      	ldr	r3, [r4, #0]
+    148e:	9301      	str	r3, [sp, #4]
+	msg.rxbuf = p_xfer->rxbuf;
+    1490:	6863      	ldr	r3, [r4, #4]
+    1492:	9302      	str	r3, [sp, #8]
+	msg.size  = p_xfer->size;
+    1494:	68a3      	ldr	r3, [r4, #8]
+    1496:	9303      	str	r3, [sp, #12]
+	return _spi_m_sync_trans(&spi->dev, &msg);
+    1498:	a901      	add	r1, sp, #4
+    149a:	4b04      	ldr	r3, [pc, #16]	; (14ac <spi_m_sync_transfer+0x38>)
+    149c:	1d28      	adds	r0, r5, #4
+    149e:	4798      	blx	r3
+}
+    14a0:	b005      	add	sp, #20
+    14a2:	bd30      	pop	{r4, r5, pc}
+    14a4:	00002fe6 	.word	0x00002fe6
+    14a8:	00001605 	.word	0x00001605
+    14ac:	00001fd9 	.word	0x00001fd9
+
+000014b0 <_spi_m_sync_io_write>:
+{
+    14b0:	b57f      	push	{r0, r1, r2, r3, r4, r5, r6, lr}
+	ASSERT(io);
+    14b2:	4604      	mov	r4, r0
+    14b4:	3800      	subs	r0, #0
+    14b6:	bf18      	it	ne
+    14b8:	2001      	movne	r0, #1
+{
+    14ba:	460e      	mov	r6, r1
+    14bc:	4615      	mov	r5, r2
+	ASSERT(io);
+    14be:	4907      	ldr	r1, [pc, #28]	; (14dc <_spi_m_sync_io_write+0x2c>)
+    14c0:	4b07      	ldr	r3, [pc, #28]	; (14e0 <_spi_m_sync_io_write+0x30>)
+    14c2:	22a3      	movs	r2, #163	; 0xa3
+    14c4:	4798      	blx	r3
+	xfer.rxbuf = 0;
+    14c6:	2300      	movs	r3, #0
+	xfer.txbuf = (uint8_t *)buf;
+    14c8:	e9cd 6301 	strd	r6, r3, [sp, #4]
+	return spi_m_sync_transfer(spi, &xfer);
+    14cc:	a901      	add	r1, sp, #4
+    14ce:	4b05      	ldr	r3, [pc, #20]	; (14e4 <_spi_m_sync_io_write+0x34>)
+	xfer.size  = length;
+    14d0:	9503      	str	r5, [sp, #12]
+	return spi_m_sync_transfer(spi, &xfer);
+    14d2:	f1a4 000c 	sub.w	r0, r4, #12
+    14d6:	4798      	blx	r3
+}
+    14d8:	b004      	add	sp, #16
+    14da:	bd70      	pop	{r4, r5, r6, pc}
+    14dc:	00002fe6 	.word	0x00002fe6
+    14e0:	00001605 	.word	0x00001605
+    14e4:	00001475 	.word	0x00001475
+
+000014e8 <_spi_m_sync_io_read>:
+{
+    14e8:	b57f      	push	{r0, r1, r2, r3, r4, r5, r6, lr}
+	ASSERT(io);
+    14ea:	4604      	mov	r4, r0
+    14ec:	3800      	subs	r0, #0
+    14ee:	bf18      	it	ne
+    14f0:	2001      	movne	r0, #1
+{
+    14f2:	460e      	mov	r6, r1
+    14f4:	4615      	mov	r5, r2
+	ASSERT(io);
+    14f6:	4907      	ldr	r1, [pc, #28]	; (1514 <_spi_m_sync_io_read+0x2c>)
+    14f8:	4b07      	ldr	r3, [pc, #28]	; (1518 <_spi_m_sync_io_read+0x30>)
+    14fa:	2287      	movs	r2, #135	; 0x87
+    14fc:	4798      	blx	r3
+	xfer.txbuf = 0;
+    14fe:	2300      	movs	r3, #0
+    1500:	9301      	str	r3, [sp, #4]
+	return spi_m_sync_transfer(spi, &xfer);
+    1502:	a901      	add	r1, sp, #4
+    1504:	4b05      	ldr	r3, [pc, #20]	; (151c <_spi_m_sync_io_read+0x34>)
+	xfer.rxbuf = buf;
+    1506:	9602      	str	r6, [sp, #8]
+	return spi_m_sync_transfer(spi, &xfer);
+    1508:	f1a4 000c 	sub.w	r0, r4, #12
+	xfer.size  = length;
+    150c:	9503      	str	r5, [sp, #12]
+	return spi_m_sync_transfer(spi, &xfer);
+    150e:	4798      	blx	r3
+}
+    1510:	b004      	add	sp, #16
+    1512:	bd70      	pop	{r4, r5, r6, pc}
+    1514:	00002fe6 	.word	0x00002fe6
+    1518:	00001605 	.word	0x00001605
+    151c:	00001475 	.word	0x00001475
+
+00001520 <spi_m_sync_get_io_descriptor>:
+
+int32_t spi_m_sync_get_io_descriptor(struct spi_m_sync_descriptor *const spi, struct io_descriptor **io)
+{
+    1520:	b538      	push	{r3, r4, r5, lr}
+    1522:	460d      	mov	r5, r1
+	ASSERT(spi && io);
+    1524:	4604      	mov	r4, r0
+    1526:	b110      	cbz	r0, 152e <spi_m_sync_get_io_descriptor+0xe>
+    1528:	1e08      	subs	r0, r1, #0
+    152a:	bf18      	it	ne
+    152c:	2001      	movne	r0, #1
+    152e:	4904      	ldr	r1, [pc, #16]	; (1540 <spi_m_sync_get_io_descriptor+0x20>)
+    1530:	4b04      	ldr	r3, [pc, #16]	; (1544 <spi_m_sync_get_io_descriptor+0x24>)
+    1532:	22bd      	movs	r2, #189	; 0xbd
+	*io = &spi->io;
+    1534:	340c      	adds	r4, #12
+	ASSERT(spi && io);
+    1536:	4798      	blx	r3
+	*io = &spi->io;
+    1538:	602c      	str	r4, [r5, #0]
+	return 0;
+}
+    153a:	2000      	movs	r0, #0
+    153c:	bd38      	pop	{r3, r4, r5, pc}
+    153e:	bf00      	nop
+    1540:	00002fe6 	.word	0x00002fe6
+    1544:	00001605 	.word	0x00001605
+
+00001548 <mci_sync_init>:
+
+/**
+ *  \brief Initialize MCI low level driver.
+ */
+int32_t mci_sync_init(struct mci_sync_desc *mci, void *hw)
+{
+    1548:	b570      	push	{r4, r5, r6, lr}
+    154a:	460d      	mov	r5, r1
+	ASSERT(mci && hw);
+    154c:	4604      	mov	r4, r0
+    154e:	b110      	cbz	r0, 1556 <mci_sync_init+0xe>
+    1550:	1e08      	subs	r0, r1, #0
+    1552:	bf18      	it	ne
+    1554:	2001      	movne	r0, #1
+    1556:	4905      	ldr	r1, [pc, #20]	; (156c <mci_sync_init+0x24>)
+    1558:	4b05      	ldr	r3, [pc, #20]	; (1570 <mci_sync_init+0x28>)
+    155a:	2231      	movs	r2, #49	; 0x31
+    155c:	4798      	blx	r3
+	return _mci_sync_init(&mci->device, hw);
+    155e:	4629      	mov	r1, r5
+    1560:	4620      	mov	r0, r4
+    1562:	4b04      	ldr	r3, [pc, #16]	; (1574 <mci_sync_init+0x2c>)
+}
+    1564:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
+	return _mci_sync_init(&mci->device, hw);
+    1568:	4718      	bx	r3
+    156a:	bf00      	nop
+    156c:	00003002 	.word	0x00003002
+    1570:	00001605 	.word	0x00001605
+    1574:	00001649 	.word	0x00001649
+
+00001578 <delay_init>:
+/**
+ * \brief Initialize Delay driver
+ */
+void delay_init(void *const hw)
+{
+	_delay_init(hardware = hw);
+    1578:	4b01      	ldr	r3, [pc, #4]	; (1580 <delay_init+0x8>)
+    157a:	6018      	str	r0, [r3, #0]
+    157c:	4b01      	ldr	r3, [pc, #4]	; (1584 <delay_init+0xc>)
+    157e:	4718      	bx	r3
+    1580:	200002d8 	.word	0x200002d8
+    1584:	00000305 	.word	0x00000305
+
+00001588 <_init_chip>:
+}
+
+static inline void hri_nvmctrl_set_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_RWS(mask);
+    1588:	4a0a      	ldr	r2, [pc, #40]	; (15b4 <_init_chip+0x2c>)
+    158a:	8813      	ldrh	r3, [r2, #0]
+    158c:	b29b      	uxth	r3, r3
+
+/**
+ * \brief Initialize the hardware abstraction layer
+ */
+void _init_chip(void)
+{
+    158e:	b510      	push	{r4, lr}
+    1590:	f443 63a0 	orr.w	r3, r3, #1280	; 0x500
+    1594:	8013      	strh	r3, [r2, #0]
+	hri_nvmctrl_set_CTRLA_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE);
+
+	_osc32kctrl_init_sources();
+    1596:	4b08      	ldr	r3, [pc, #32]	; (15b8 <_init_chip+0x30>)
+    1598:	4798      	blx	r3
+	_oscctrl_init_sources();
+    159a:	4b08      	ldr	r3, [pc, #32]	; (15bc <_init_chip+0x34>)
+    159c:	4798      	blx	r3
+	_mclk_init();
+    159e:	4b08      	ldr	r3, [pc, #32]	; (15c0 <_init_chip+0x38>)
+    15a0:	4798      	blx	r3
+#if _GCLK_INIT_1ST
+	_gclk_init_generators_by_fref(_GCLK_INIT_1ST);
+#endif
+	_oscctrl_init_referenced_generators();
+    15a2:	4b08      	ldr	r3, [pc, #32]	; (15c4 <_init_chip+0x3c>)
+    15a4:	4798      	blx	r3
+#endif
+
+#if CONF_CMCC_ENABLE
+	cache_init();
+#endif
+}
+    15a6:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
+	_gclk_init_generators_by_fref(_GCLK_INIT_LAST);
+    15aa:	4b07      	ldr	r3, [pc, #28]	; (15c8 <_init_chip+0x40>)
+    15ac:	f640 70ff 	movw	r0, #4095	; 0xfff
+    15b0:	4718      	bx	r3
+    15b2:	bf00      	nop
+    15b4:	41004000 	.word	0x41004000
+    15b8:	00001911 	.word	0x00001911
+    15bc:	0000160b 	.word	0x0000160b
+    15c0:	0000180d 	.word	0x0000180d
+    15c4:	0000160d 	.word	0x0000160d
+    15c8:	000015cd 	.word	0x000015cd
+
+000015cc <_gclk_init_generators_by_fref>:
+
+void _gclk_init_generators_by_fref(uint32_t bm)
+{
+
+#if CONF_GCLK_GENERATOR_0_CONFIG == 1
+	if (bm & (1ul << 0)) {
+    15cc:	07c2      	lsls	r2, r0, #31
+    15ce:	d507      	bpl.n	15e0 <_gclk_init_generators_by_fref+0x14>
+}
+
+static inline void hri_gclk_write_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg = data;
+    15d0:	4b09      	ldr	r3, [pc, #36]	; (15f8 <_gclk_init_generators_by_fref+0x2c>)
+    15d2:	4a0a      	ldr	r2, [pc, #40]	; (15fc <_gclk_init_generators_by_fref+0x30>)
+    15d4:	621a      	str	r2, [r3, #32]
+	while (((Gclk *)hw)->SYNCBUSY.reg & reg) {
+    15d6:	f643 72fd 	movw	r2, #16381	; 0x3ffd
+    15da:	6859      	ldr	r1, [r3, #4]
+    15dc:	4211      	tst	r1, r2
+    15de:	d1fc      	bne.n	15da <_gclk_init_generators_by_fref+0xe>
+		        | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE);
+	}
+#endif
+
+#if CONF_GCLK_GENERATOR_3_CONFIG == 1
+	if (bm & (1ul << 3)) {
+    15e0:	0703      	lsls	r3, r0, #28
+    15e2:	d507      	bpl.n	15f4 <_gclk_init_generators_by_fref+0x28>
+	((Gclk *)hw)->GENCTRL[index].reg = data;
+    15e4:	4b04      	ldr	r3, [pc, #16]	; (15f8 <_gclk_init_generators_by_fref+0x2c>)
+    15e6:	4a06      	ldr	r2, [pc, #24]	; (1600 <_gclk_init_generators_by_fref+0x34>)
+    15e8:	62da      	str	r2, [r3, #44]	; 0x2c
+	while (((Gclk *)hw)->SYNCBUSY.reg & reg) {
+    15ea:	f643 72fd 	movw	r2, #16381	; 0x3ffd
+    15ee:	6859      	ldr	r1, [r3, #4]
+    15f0:	4211      	tst	r1, r2
+    15f2:	d1fc      	bne.n	15ee <_gclk_init_generators_by_fref+0x22>
+		        | (CONF_GCLK_GEN_11_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_11_OE << GCLK_GENCTRL_OE_Pos)
+		        | (CONF_GCLK_GEN_11_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_11_IDC << GCLK_GENCTRL_IDC_Pos)
+		        | (CONF_GCLK_GENERATOR_11_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_11_SOURCE);
+	}
+#endif
+}
+    15f4:	4770      	bx	lr
+    15f6:	bf00      	nop
+    15f8:	40001c00 	.word	0x40001c00
+    15fc:	00010107 	.word	0x00010107
+    1600:	00010105 	.word	0x00010105
+
+00001604 <assert>:
+/**
+ * \brief Assert function
+ */
+void assert(const bool condition, const char *const file, const int line)
+{
+	if (!(condition)) {
+    1604:	b900      	cbnz	r0, 1608 <assert+0x4>
+		__asm("BKPT #0");
+    1606:	be00      	bkpt	0x0000
+	}
+	(void)file;
+	(void)line;
+}
+    1608:	4770      	bx	lr
+
+0000160a <_oscctrl_init_sources>:
+	hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(hw, 1);
+#endif
+#endif
+
+	(void)hw;
+}
+    160a:	4770      	bx	lr
+
+0000160c <_oscctrl_init_referenced_generators>:
+
+static inline void hri_oscctrl_write_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_oscctrl_dpllratio_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = data;
+    160c:	4b0c      	ldr	r3, [pc, #48]	; (1640 <_oscctrl_init_referenced_generators+0x34>)
+    160e:	4a0d      	ldr	r2, [pc, #52]	; (1644 <_oscctrl_init_referenced_generators+0x38>)
+    1610:	635a      	str	r2, [r3, #52]	; 0x34
+	while (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & reg) {
+    1612:	6bda      	ldr	r2, [r3, #60]	; 0x3c
+    1614:	f012 0f06 	tst.w	r2, #6
+    1618:	d1fb      	bne.n	1612 <_oscctrl_init_referenced_generators+0x6>
+
+static inline void hri_oscctrl_write_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_oscctrl_dpllctrlb_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = data;
+    161a:	f44f 6202 	mov.w	r2, #2080	; 0x820
+    161e:	639a      	str	r2, [r3, #56]	; 0x38
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = data;
+    1620:	2202      	movs	r2, #2
+    1622:	f883 2030 	strb.w	r2, [r3, #48]	; 0x30
+	while (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & reg) {
+    1626:	4a06      	ldr	r2, [pc, #24]	; (1640 <_oscctrl_init_referenced_generators+0x34>)
+    1628:	6bd3      	ldr	r3, [r2, #60]	; 0x3c
+    162a:	0798      	lsls	r0, r3, #30
+    162c:	d4fc      	bmi.n	1628 <_oscctrl_init_referenced_generators+0x1c>
+	return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK)
+    162e:	4b04      	ldr	r3, [pc, #16]	; (1640 <_oscctrl_init_referenced_generators+0x34>)
+    1630:	6c1a      	ldr	r2, [r3, #64]	; 0x40
+#endif
+#endif
+
+#if CONF_FDPLL0_CONFIG == 1
+#if CONF_FDPLL0_ENABLE == 1
+	while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw, 0) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw, 0)))
+    1632:	07d1      	lsls	r1, r2, #31
+    1634:	d402      	bmi.n	163c <_oscctrl_init_referenced_generators+0x30>
+	return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY)
+    1636:	6c1a      	ldr	r2, [r3, #64]	; 0x40
+    1638:	0792      	lsls	r2, r2, #30
+    163a:	d5f9      	bpl.n	1630 <_oscctrl_init_referenced_generators+0x24>
+	hri_gclk_write_GENCTRL_SRC_bf(GCLK, 0, CONF_GCLK_GEN_0_SOURCE);
+	while (hri_gclk_get_SYNCBUSY_GENCTRL0_bit(GCLK))
+		;
+#endif
+	(void)hw;
+}
+    163c:	4770      	bx	lr
+    163e:	bf00      	nop
+    1640:	40001000 	.word	0x40001000
+    1644:	00010e4d 	.word	0x00010e4d
+
+00001648 <_mci_sync_init>:
+
+/**
+ *  \brief Initialize MCI low level driver.
+ */
+int32_t _mci_sync_init(struct _mci_sync_device *const mci_dev, void *const hw)
+{
+    1648:	b538      	push	{r3, r4, r5, lr}
+    164a:	460c      	mov	r4, r1
+	ASSERT(mci_dev && hw);
+    164c:	4605      	mov	r5, r0
+    164e:	b110      	cbz	r0, 1656 <_mci_sync_init+0xe>
+    1650:	1e08      	subs	r0, r1, #0
+    1652:	bf18      	it	ne
+    1654:	2001      	movne	r0, #1
+    1656:	4b12      	ldr	r3, [pc, #72]	; (16a0 <_mci_sync_init+0x58>)
+    1658:	4912      	ldr	r1, [pc, #72]	; (16a4 <_mci_sync_init+0x5c>)
+    165a:	22d8      	movs	r2, #216	; 0xd8
+    165c:	4798      	blx	r3
+}
+
+static inline void hri_sdhc_set_SRR_SWRSTALL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTALL;
+    165e:	f894 302f 	ldrb.w	r3, [r4, #47]	; 0x2f
+
+	mci_dev->hw = hw;
+    1662:	602c      	str	r4, [r5, #0]
+    1664:	f043 0301 	orr.w	r3, r3, #1
+    1668:	f884 302f 	strb.w	r3, [r4, #47]	; 0x2f
+}
+
+static inline bool hri_sdhc_get_SRR_SWRSTALL_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->SRR.reg;
+    166c:	f894 002f 	ldrb.w	r0, [r4, #47]	; 0x2f
+
+	hri_sdhc_set_SRR_SWRSTALL_bit(hw);
+	while (hri_sdhc_get_SRR_SWRSTALL_bit(hw))
+    1670:	f010 0001 	ands.w	r0, r0, #1
+    1674:	d1fa      	bne.n	166c <_mci_sync_init+0x24>
+	((Sdhc *)hw)->TCR.reg = data;
+    1676:	230e      	movs	r3, #14
+    1678:	f884 302e 	strb.w	r3, [r4, #46]	; 0x2e
+	((Sdhc *)hw)->PCR.reg = data;
+    167c:	230f      	movs	r3, #15
+    167e:	f884 3029 	strb.w	r3, [r4, #41]	; 0x29
+}
+
+static inline void hri_sdhc_set_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg |= mask;
+    1682:	8ea3      	ldrh	r3, [r4, #52]	; 0x34
+    1684:	b29b      	uxth	r3, r3
+    1686:	ea6f 2353 	mvn.w	r3, r3, lsr #9
+    168a:	ea6f 2343 	mvn.w	r3, r3, lsl #9
+    168e:	86a3      	strh	r3, [r4, #52]	; 0x34
+}
+
+static inline void hri_sdhc_set_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= mask;
+    1690:	8ee3      	ldrh	r3, [r4, #54]	; 0x36
+    1692:	b29b      	uxth	r3, r3
+    1694:	ea6f 2393 	mvn.w	r3, r3, lsr #10
+    1698:	ea6f 2383 	mvn.w	r3, r3, lsl #10
+    169c:	86e3      	strh	r3, [r4, #54]	; 0x36
+
+	hri_sdhc_set_NISTER_reg(hw, SDHC_NISTER_MASK);
+	hri_sdhc_set_EISTER_reg(hw, SDHC_EISTER_MASK);
+
+	return ERR_NONE;
+}
+    169e:	bd38      	pop	{r3, r4, r5, pc}
+    16a0:	00001605 	.word	0x00001605
+    16a4:	0000301c 	.word	0x0000301c
+
+000016a8 <usart_sync_write>:
+ * \param[in] length The number of bytes to write
+ *
+ * \return The number of bytes written.
+ */
+static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length)
+{
+    16a8:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
+    16ac:	460e      	mov	r6, r1
+    16ae:	4615      	mov	r5, r2
+	uint32_t                      offset = 0;
+	struct usart_sync_descriptor *descr  = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io);
+
+	ASSERT(io_descr && buf && length);
+    16b0:	4604      	mov	r4, r0
+    16b2:	b118      	cbz	r0, 16bc <usart_sync_write+0x14>
+    16b4:	b329      	cbz	r1, 1702 <usart_sync_write+0x5a>
+    16b6:	1e10      	subs	r0, r2, #0
+    16b8:	bf18      	it	ne
+    16ba:	2001      	movne	r0, #1
+    16bc:	4912      	ldr	r1, [pc, #72]	; (1708 <usart_sync_write+0x60>)
+    16be:	4b13      	ldr	r3, [pc, #76]	; (170c <usart_sync_write+0x64>)
+	while (!_usart_sync_is_ready_to_send(&descr->device))
+    16c0:	4f13      	ldr	r7, [pc, #76]	; (1710 <usart_sync_write+0x68>)
+	ASSERT(io_descr && buf && length);
+    16c2:	22f1      	movs	r2, #241	; 0xf1
+    16c4:	4798      	blx	r3
+	while (!_usart_sync_is_ready_to_send(&descr->device))
+    16c6:	3408      	adds	r4, #8
+    16c8:	46b9      	mov	r9, r7
+    16ca:	4620      	mov	r0, r4
+    16cc:	47b8      	blx	r7
+    16ce:	2800      	cmp	r0, #0
+    16d0:	d0fb      	beq.n	16ca <usart_sync_write+0x22>
+		;
+	do {
+		_usart_sync_write_byte(&descr->device, buf[offset]);
+    16d2:	f8df 8044 	ldr.w	r8, [pc, #68]	; 1718 <usart_sync_write+0x70>
+	uint32_t                      offset = 0;
+    16d6:	2700      	movs	r7, #0
+		_usart_sync_write_byte(&descr->device, buf[offset]);
+    16d8:	5df1      	ldrb	r1, [r6, r7]
+    16da:	4620      	mov	r0, r4
+    16dc:	47c0      	blx	r8
+		while (!_usart_sync_is_ready_to_send(&descr->device))
+    16de:	4620      	mov	r0, r4
+    16e0:	47c8      	blx	r9
+    16e2:	2800      	cmp	r0, #0
+    16e4:	d0fb      	beq.n	16de <usart_sync_write+0x36>
+			;
+	} while (++offset < length);
+    16e6:	3701      	adds	r7, #1
+    16e8:	42bd      	cmp	r5, r7
+    16ea:	d8f5      	bhi.n	16d8 <usart_sync_write+0x30>
+    16ec:	2d00      	cmp	r5, #0
+	while (!_usart_sync_is_transmit_done(&descr->device))
+    16ee:	4e09      	ldr	r6, [pc, #36]	; (1714 <usart_sync_write+0x6c>)
+	} while (++offset < length);
+    16f0:	bf08      	it	eq
+    16f2:	2501      	moveq	r5, #1
+	while (!_usart_sync_is_transmit_done(&descr->device))
+    16f4:	4620      	mov	r0, r4
+    16f6:	47b0      	blx	r6
+    16f8:	2800      	cmp	r0, #0
+    16fa:	d0fb      	beq.n	16f4 <usart_sync_write+0x4c>
+		;
+	return (int32_t)offset;
+}
+    16fc:	4628      	mov	r0, r5
+    16fe:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
+	ASSERT(io_descr && buf && length);
+    1702:	4608      	mov	r0, r1
+    1704:	e7da      	b.n	16bc <usart_sync_write+0x14>
+    1706:	bf00      	nop
+    1708:	00003033 	.word	0x00003033
+    170c:	00001605 	.word	0x00001605
+    1710:	00001e87 	.word	0x00001e87
+    1714:	00001e91 	.word	0x00001e91
+    1718:	00001e79 	.word	0x00001e79
+
+0000171c <usart_sync_read>:
+ * \param[in] length The size of a buffer
+ *
+ * \return The number of bytes read.
+ */
+static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length)
+{
+    171c:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
+    1720:	460e      	mov	r6, r1
+    1722:	4615      	mov	r5, r2
+	uint32_t                      offset = 0;
+	struct usart_sync_descriptor *descr  = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io);
+
+	ASSERT(io_descr && buf && length);
+    1724:	4604      	mov	r4, r0
+    1726:	b118      	cbz	r0, 1730 <usart_sync_read+0x14>
+    1728:	b1e9      	cbz	r1, 1766 <usart_sync_read+0x4a>
+    172a:	1e10      	subs	r0, r2, #0
+    172c:	bf18      	it	ne
+    172e:	2001      	movne	r0, #1
+    1730:	490e      	ldr	r1, [pc, #56]	; (176c <usart_sync_read+0x50>)
+    1732:	4b0f      	ldr	r3, [pc, #60]	; (1770 <usart_sync_read+0x54>)
+	do {
+		while (!_usart_sync_is_byte_received(&descr->device))
+    1734:	f8df 903c 	ldr.w	r9, [pc, #60]	; 1774 <usart_sync_read+0x58>
+			;
+		buf[offset] = _usart_sync_read_byte(&descr->device);
+    1738:	f8df 803c 	ldr.w	r8, [pc, #60]	; 1778 <usart_sync_read+0x5c>
+	ASSERT(io_descr && buf && length);
+    173c:	f44f 7286 	mov.w	r2, #268	; 0x10c
+    1740:	4798      	blx	r3
+	uint32_t                      offset = 0;
+    1742:	2700      	movs	r7, #0
+		while (!_usart_sync_is_byte_received(&descr->device))
+    1744:	3408      	adds	r4, #8
+    1746:	4620      	mov	r0, r4
+    1748:	47c8      	blx	r9
+    174a:	2800      	cmp	r0, #0
+    174c:	d0fb      	beq.n	1746 <usart_sync_read+0x2a>
+		buf[offset] = _usart_sync_read_byte(&descr->device);
+    174e:	4620      	mov	r0, r4
+    1750:	47c0      	blx	r8
+    1752:	55f0      	strb	r0, [r6, r7]
+	} while (++offset < length);
+    1754:	3701      	adds	r7, #1
+    1756:	42bd      	cmp	r5, r7
+    1758:	d8f5      	bhi.n	1746 <usart_sync_read+0x2a>
+    175a:	2d00      	cmp	r5, #0
+
+	return (int32_t)offset;
+}
+    175c:	bf14      	ite	ne
+    175e:	4628      	movne	r0, r5
+    1760:	2001      	moveq	r0, #1
+    1762:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
+	ASSERT(io_descr && buf && length);
+    1766:	4608      	mov	r0, r1
+    1768:	e7e2      	b.n	1730 <usart_sync_read+0x14>
+    176a:	bf00      	nop
+    176c:	00003033 	.word	0x00003033
+    1770:	00001605 	.word	0x00001605
+    1774:	00001e9b 	.word	0x00001e9b
+    1778:	00001e7f 	.word	0x00001e7f
+
+0000177c <usart_sync_init>:
+{
+    177c:	b538      	push	{r3, r4, r5, lr}
+    177e:	460d      	mov	r5, r1
+	ASSERT(descr && hw);
+    1780:	4604      	mov	r4, r0
+    1782:	b110      	cbz	r0, 178a <usart_sync_init+0xe>
+    1784:	1e08      	subs	r0, r1, #0
+    1786:	bf18      	it	ne
+    1788:	2001      	movne	r0, #1
+    178a:	4907      	ldr	r1, [pc, #28]	; (17a8 <usart_sync_init+0x2c>)
+    178c:	4b07      	ldr	r3, [pc, #28]	; (17ac <usart_sync_init+0x30>)
+    178e:	2234      	movs	r2, #52	; 0x34
+    1790:	4798      	blx	r3
+	init_status = _usart_sync_init(&descr->device, hw);
+    1792:	4b07      	ldr	r3, [pc, #28]	; (17b0 <usart_sync_init+0x34>)
+    1794:	4629      	mov	r1, r5
+    1796:	f104 0008 	add.w	r0, r4, #8
+    179a:	4798      	blx	r3
+	if (init_status) {
+    179c:	b918      	cbnz	r0, 17a6 <usart_sync_init+0x2a>
+	descr->io.read  = usart_sync_read;
+    179e:	4b05      	ldr	r3, [pc, #20]	; (17b4 <usart_sync_init+0x38>)
+    17a0:	6063      	str	r3, [r4, #4]
+	descr->io.write = usart_sync_write;
+    17a2:	4b05      	ldr	r3, [pc, #20]	; (17b8 <usart_sync_init+0x3c>)
+    17a4:	6023      	str	r3, [r4, #0]
+}
+    17a6:	bd38      	pop	{r3, r4, r5, pc}
+    17a8:	00003033 	.word	0x00003033
+    17ac:	00001605 	.word	0x00001605
+    17b0:	00001e39 	.word	0x00001e39
+    17b4:	0000171d 	.word	0x0000171d
+    17b8:	000016a9 	.word	0x000016a9
+
+000017bc <usart_sync_enable>:
+{
+    17bc:	b510      	push	{r4, lr}
+	ASSERT(descr);
+    17be:	4604      	mov	r4, r0
+    17c0:	3800      	subs	r0, #0
+    17c2:	bf18      	it	ne
+    17c4:	2001      	movne	r0, #1
+    17c6:	4905      	ldr	r1, [pc, #20]	; (17dc <usart_sync_enable+0x20>)
+    17c8:	4b05      	ldr	r3, [pc, #20]	; (17e0 <usart_sync_enable+0x24>)
+    17ca:	2253      	movs	r2, #83	; 0x53
+    17cc:	4798      	blx	r3
+	_usart_sync_enable(&descr->device);
+    17ce:	f104 0008 	add.w	r0, r4, #8
+    17d2:	4b04      	ldr	r3, [pc, #16]	; (17e4 <usart_sync_enable+0x28>)
+    17d4:	4798      	blx	r3
+}
+    17d6:	2000      	movs	r0, #0
+    17d8:	bd10      	pop	{r4, pc}
+    17da:	bf00      	nop
+    17dc:	00003033 	.word	0x00003033
+    17e0:	00001605 	.word	0x00001605
+    17e4:	00001e65 	.word	0x00001e65
+
+000017e8 <usart_sync_get_io_descriptor>:
+{
+    17e8:	b538      	push	{r3, r4, r5, lr}
+    17ea:	460d      	mov	r5, r1
+	ASSERT(descr && io);
+    17ec:	4604      	mov	r4, r0
+    17ee:	b110      	cbz	r0, 17f6 <usart_sync_get_io_descriptor+0xe>
+    17f0:	1e08      	subs	r0, r1, #0
+    17f2:	bf18      	it	ne
+    17f4:	2001      	movne	r0, #1
+    17f6:	4903      	ldr	r1, [pc, #12]	; (1804 <usart_sync_get_io_descriptor+0x1c>)
+    17f8:	4b03      	ldr	r3, [pc, #12]	; (1808 <usart_sync_get_io_descriptor+0x20>)
+    17fa:	2269      	movs	r2, #105	; 0x69
+    17fc:	4798      	blx	r3
+	*io = &descr->io;
+    17fe:	602c      	str	r4, [r5, #0]
+}
+    1800:	2000      	movs	r0, #0
+    1802:	bd38      	pop	{r3, r4, r5, pc}
+    1804:	00003033 	.word	0x00003033
+    1808:	00001605 	.word	0x00001605
+
+0000180c <_mclk_init>:
+}
+
+static inline void hri_mclk_write_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t data)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->CPUDIV.reg = data;
+    180c:	4b01      	ldr	r3, [pc, #4]	; (1814 <_mclk_init+0x8>)
+    180e:	2201      	movs	r2, #1
+    1810:	715a      	strb	r2, [r3, #5]
+ */
+void _mclk_init(void)
+{
+	void *hw = (void *)MCLK;
+	hri_mclk_write_CPUDIV_reg(hw, MCLK_CPUDIV_DIV(CONF_MCLK_CPUDIV));
+}
+    1812:	4770      	bx	lr
+    1814:	40000800 	.word	0x40000800
+
+00001818 <RAMECC_Handler>:
+	return tmp;
+}
+
+static inline hri_ramecc_intflag_reg_t hri_ramecc_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Ramecc *)hw)->INTFLAG.reg;
+    1818:	4a0b      	ldr	r2, [pc, #44]	; (1848 <RAMECC_Handler+0x30>)
+    181a:	7893      	ldrb	r3, [r2, #2]
+
+/**
+ * \internal RAMECC interrupt handler
+ */
+void RAMECC_Handler(void)
+{
+    181c:	b082      	sub	sp, #8
+    181e:	b2db      	uxtb	r3, r3
+	struct _ramecc_device *dev      = (struct _ramecc_device *)&device;
+	volatile uint32_t      int_mask = hri_ramecc_read_INTFLAG_reg(RAMECC);
+    1820:	9301      	str	r3, [sp, #4]
+
+	if (int_mask & RAMECC_INTFLAG_DUALE && dev->ramecc_cb.dual_bit_err) {
+    1822:	9b01      	ldr	r3, [sp, #4]
+    1824:	0799      	lsls	r1, r3, #30
+    1826:	d505      	bpl.n	1834 <RAMECC_Handler+0x1c>
+    1828:	4b08      	ldr	r3, [pc, #32]	; (184c <RAMECC_Handler+0x34>)
+    182a:	681b      	ldr	r3, [r3, #0]
+    182c:	b113      	cbz	r3, 1834 <RAMECC_Handler+0x1c>
+	return tmp;
+}
+
+static inline hri_ramecc_erraddr_reg_t hri_ramecc_read_ERRADDR_reg(const void *const hw)
+{
+	return ((Ramecc *)hw)->ERRADDR.reg;
+    182e:	6850      	ldr	r0, [r2, #4]
+	} else if (int_mask & RAMECC_INTFLAG_SINGLEE && dev->ramecc_cb.single_bit_err) {
+		dev->ramecc_cb.single_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC));
+	} else {
+		return;
+	}
+}
+    1830:	b002      	add	sp, #8
+		dev->ramecc_cb.single_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC));
+    1832:	4718      	bx	r3
+	} else if (int_mask & RAMECC_INTFLAG_SINGLEE && dev->ramecc_cb.single_bit_err) {
+    1834:	9b01      	ldr	r3, [sp, #4]
+    1836:	07db      	lsls	r3, r3, #31
+    1838:	d504      	bpl.n	1844 <RAMECC_Handler+0x2c>
+    183a:	4b04      	ldr	r3, [pc, #16]	; (184c <RAMECC_Handler+0x34>)
+    183c:	685b      	ldr	r3, [r3, #4]
+    183e:	b10b      	cbz	r3, 1844 <RAMECC_Handler+0x2c>
+    1840:	4a01      	ldr	r2, [pc, #4]	; (1848 <RAMECC_Handler+0x30>)
+    1842:	e7f4      	b.n	182e <RAMECC_Handler+0x16>
+}
+    1844:	b002      	add	sp, #8
+    1846:	4770      	bx	lr
+    1848:	41020000 	.word	0x41020000
+    184c:	200002dc 	.word	0x200002dc
+
+00001850 <diskio_init>:
+
+#include "diskio_start.h"
+
+void diskio_init(void)
+{
+}
+    1850:	4770      	bx	lr
+
+00001852 <Dummy_Handler>:
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+	while (1) {
+    1852:	e7fe      	b.n	1852 <Dummy_Handler>
+
+00001854 <Reset_Handler>:
+	if (pSrc != pDest) {
+    1854:	4918      	ldr	r1, [pc, #96]	; (18b8 <Reset_Handler+0x64>)
+    1856:	4819      	ldr	r0, [pc, #100]	; (18bc <Reset_Handler+0x68>)
+    1858:	4281      	cmp	r1, r0
+{
+    185a:	b510      	push	{r4, lr}
+	if (pSrc != pDest) {
+    185c:	d00a      	beq.n	1874 <Reset_Handler+0x20>
+			*pDest++ = *pSrc++;
+    185e:	4b18      	ldr	r3, [pc, #96]	; (18c0 <Reset_Handler+0x6c>)
+    1860:	1cda      	adds	r2, r3, #3
+    1862:	1a12      	subs	r2, r2, r0
+    1864:	f022 0203 	bic.w	r2, r2, #3
+    1868:	1ec4      	subs	r4, r0, #3
+    186a:	42a3      	cmp	r3, r4
+    186c:	bf38      	it	cc
+    186e:	2200      	movcc	r2, #0
+    1870:	4b14      	ldr	r3, [pc, #80]	; (18c4 <Reset_Handler+0x70>)
+    1872:	4798      	blx	r3
+		*pDest++ = 0;
+    1874:	4b14      	ldr	r3, [pc, #80]	; (18c8 <Reset_Handler+0x74>)
+    1876:	4815      	ldr	r0, [pc, #84]	; (18cc <Reset_Handler+0x78>)
+    1878:	1cda      	adds	r2, r3, #3
+    187a:	1a12      	subs	r2, r2, r0
+    187c:	1ec1      	subs	r1, r0, #3
+    187e:	f022 0203 	bic.w	r2, r2, #3
+    1882:	4299      	cmp	r1, r3
+    1884:	bf88      	it	hi
+    1886:	2200      	movhi	r2, #0
+    1888:	4b11      	ldr	r3, [pc, #68]	; (18d0 <Reset_Handler+0x7c>)
+    188a:	2100      	movs	r1, #0
+    188c:	4798      	blx	r3
+	SCB->VTOR = ((uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk);
+    188e:	4a11      	ldr	r2, [pc, #68]	; (18d4 <Reset_Handler+0x80>)
+    1890:	4b11      	ldr	r3, [pc, #68]	; (18d8 <Reset_Handler+0x84>)
+    1892:	f022 027f 	bic.w	r2, r2, #127	; 0x7f
+    1896:	609a      	str	r2, [r3, #8]
+	SCB->CPACR |= (0xFu << 20);
+    1898:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
+    189c:	f442 0270 	orr.w	r2, r2, #15728640	; 0xf00000
+    18a0:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+    18a4:	f3bf 8f4f 	dsb	sy
+  __ASM volatile ("isb 0xF":::"memory");
+    18a8:	f3bf 8f6f 	isb	sy
+	__libc_init_array();
+    18ac:	4b0b      	ldr	r3, [pc, #44]	; (18dc <Reset_Handler+0x88>)
+    18ae:	4798      	blx	r3
+	main();
+    18b0:	4b0b      	ldr	r3, [pc, #44]	; (18e0 <Reset_Handler+0x8c>)
+    18b2:	4798      	blx	r3
+	while (1)
+    18b4:	e7fe      	b.n	18b4 <Reset_Handler+0x60>
+    18b6:	bf00      	nop
+    18b8:	000031c0 	.word	0x000031c0
+    18bc:	20000000 	.word	0x20000000
+    18c0:	2000006c 	.word	0x2000006c
+    18c4:	000021cd 	.word	0x000021cd
+    18c8:	2000036c 	.word	0x2000036c
+    18cc:	20000070 	.word	0x20000070
+    18d0:	000021e9 	.word	0x000021e9
+    18d4:	00000000 	.word	0x00000000
+    18d8:	e000ed00 	.word	0xe000ed00
+    18dc:	00002185 	.word	0x00002185
+    18e0:	000018e5 	.word	0x000018e5
+
+000018e4 <main>:
+#include <atmel_start.h>
+#include "pdebug.h"
+#include "sd_mmc_start.h"
+
+int main(void)
+{
+    18e4:	b508      	push	{r3, lr}
+	/* Initializes MCU, drivers and middleware */
+	atmel_start_init();
+    18e6:	4b05      	ldr	r3, [pc, #20]	; (18fc <main+0x18>)
+    18e8:	4798      	blx	r3
+	pdebug_init();
+    18ea:	4b05      	ldr	r3, [pc, #20]	; (1900 <main+0x1c>)
+    18ec:	4798      	blx	r3
+	printf("Hello world\n");
+    18ee:	4b05      	ldr	r3, [pc, #20]	; (1904 <main+0x20>)
+    18f0:	4805      	ldr	r0, [pc, #20]	; (1908 <main+0x24>)
+    18f2:	4798      	blx	r3
+
+	SDMMC_example();
+    18f4:	4b05      	ldr	r3, [pc, #20]	; (190c <main+0x28>)
+    18f6:	4798      	blx	r3
+	/* Replace with your application code */
+	while (1) {
+    18f8:	e7fe      	b.n	18f8 <main+0x14>
+    18fa:	bf00      	nop
+    18fc:	000020b5 	.word	0x000020b5
+    1900:	00002135 	.word	0x00002135
+    1904:	000020d5 	.word	0x000020d5
+    1908:	0000304f 	.word	0x0000304f
+    190c:	00000359 	.word	0x00000359
+
+00001910 <_osc32kctrl_init_sources>:
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg = data;
+    1910:	4b06      	ldr	r3, [pc, #24]	; (192c <_osc32kctrl_init_sources+0x1c>)
+    1912:	f242 328e 	movw	r2, #9102	; 0x238e
+    1916:	829a      	strh	r2, [r3, #20]
+}
+
+static inline void hri_osc32kctrl_write_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t data)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg = data;
+    1918:	2200      	movs	r2, #0
+    191a:	759a      	strb	r2, [r3, #22]
+}
+
+static inline void hri_osc32kctrl_write_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t data)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg = data;
+    191c:	75da      	strb	r2, [r3, #23]
+}
+
+static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_CALIB_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+    191e:	69da      	ldr	r2, [r3, #28]
+	calib = hri_osc32kctrl_read_OSCULP32K_CALIB_bf(hw);
+	hri_osc32kctrl_write_OSCULP32K_reg(hw,
+#if CONF_OSCULP32K_CALIB_ENABLE == 1
+	                                   OSC32KCTRL_OSCULP32K_CALIB(CONF_OSCULP32K_CALIB)
+#else
+	                                   OSC32KCTRL_OSCULP32K_CALIB(calib)
+    1920:	f402 527c 	and.w	r2, r2, #16128	; 0x3f00
+}
+
+static inline void hri_osc32kctrl_write_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg = data;
+    1924:	61da      	str	r2, [r3, #28]
+	((Osc32kctrl *)hw)->RTCCTRL.reg = data;
+    1926:	2201      	movs	r2, #1
+    1928:	741a      	strb	r2, [r3, #16]
+#endif
+#endif
+
+	hri_osc32kctrl_write_RTCCTRL_reg(hw, OSC32KCTRL_RTCCTRL_RTCSEL(CONF_RTCCTRL));
+	(void)calib;
+}
+    192a:	4770      	bx	lr
+    192c:	40001400 	.word	0x40001400
+
+00001930 <hri_rtcmode0_wait_for_sync>:
+typedef uint8_t  hri_rtcalarm_mask_reg_t;
+typedef uint8_t  hri_rtcmode2_mask_reg_t;
+
+static inline void hri_rtcmode0_wait_for_sync(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg)
+{
+	while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) {
+    1930:	6903      	ldr	r3, [r0, #16]
+    1932:	420b      	tst	r3, r1
+    1934:	d1fc      	bne.n	1930 <hri_rtcmode0_wait_for_sync>
+	};
+}
+    1936:	4770      	bx	lr
+
+00001938 <_calendar_init>:
+
+/**
+ * \brief Initializes the RTC module with given configurations.
+ */
+int32_t _calendar_init(struct calendar_dev *const dev)
+{
+    1938:	b510      	push	{r4, lr}
+	ASSERT(dev && dev->hw);
+    193a:	4604      	mov	r4, r0
+    193c:	b118      	cbz	r0, 1946 <_calendar_init+0xe>
+    193e:	6800      	ldr	r0, [r0, #0]
+    1940:	3800      	subs	r0, #0
+    1942:	bf18      	it	ne
+    1944:	2001      	movne	r0, #1
+    1946:	4917      	ldr	r1, [pc, #92]	; (19a4 <_calendar_init+0x6c>)
+    1948:	4b17      	ldr	r3, [pc, #92]	; (19a8 <_calendar_init+0x70>)
+    194a:	222f      	movs	r2, #47	; 0x2f
+    194c:	4798      	blx	r3
+
+	_rtc_dev = dev;
+    194e:	4b17      	ldr	r3, [pc, #92]	; (19ac <_calendar_init+0x74>)
+}
+
+static inline bool hri_rtcmode0_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+    1950:	6820      	ldr	r0, [r4, #0]
+    1952:	4a17      	ldr	r2, [pc, #92]	; (19b0 <_calendar_init+0x78>)
+    1954:	601c      	str	r4, [r3, #0]
+    1956:	f248 0103 	movw	r1, #32771	; 0x8003
+    195a:	4790      	blx	r2
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+    195c:	8803      	ldrh	r3, [r0, #0]
+
+	if (hri_rtcmode0_get_CTRLA_ENABLE_bit(dev->hw)) {
+    195e:	079b      	lsls	r3, r3, #30
+    1960:	d50a      	bpl.n	1978 <_calendar_init+0x40>
+#if !CONF_RTC_INIT_RESET
+		return ERR_DENIED;
+#else
+		hri_rtcmode0_clear_CTRLA_ENABLE_bit(dev->hw);
+    1962:	6820      	ldr	r0, [r4, #0]
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE;
+    1964:	8803      	ldrh	r3, [r0, #0]
+    1966:	f023 0302 	bic.w	r3, r3, #2
+    196a:	041b      	lsls	r3, r3, #16
+    196c:	0c1b      	lsrs	r3, r3, #16
+    196e:	8003      	strh	r3, [r0, #0]
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+    1970:	4790      	blx	r2
+		hri_rtcmode0_wait_for_sync(dev->hw, RTC_MODE0_SYNCBUSY_ENABLE);
+    1972:	6820      	ldr	r0, [r4, #0]
+    1974:	2102      	movs	r1, #2
+    1976:	4790      	blx	r2
+#endif
+	}
+	hri_rtcmode0_set_CTRLA_SWRST_bit(dev->hw);
+    1978:	6820      	ldr	r0, [r4, #0]
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_SWRST;
+    197a:	8803      	ldrh	r3, [r0, #0]
+    197c:	b29b      	uxth	r3, r3
+    197e:	f043 0301 	orr.w	r3, r3, #1
+    1982:	8003      	strh	r3, [r0, #0]
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST);
+    1984:	2101      	movs	r1, #1
+    1986:	4790      	blx	r2
+	hri_rtcmode0_wait_for_sync(dev->hw, RTC_MODE0_SYNCBUSY_SWRST);
+    1988:	6820      	ldr	r0, [r4, #0]
+    198a:	4790      	blx	r2
+	        | (CONF_RTC_COMPE0 << RTC_MODE0_EVCTRL_CMPEO_Pos) | (CONF_RTC_COMPE1 << RTC_MODE0_EVCTRL_CMPEO1_Pos)
+	        | (CONF_RTC_TAMPEREO << RTC_MODE0_EVCTRL_TAMPEREO_Pos)
+	        | (CONF_RTC_TAMPEVEI << RTC_MODE0_EVCTRL_TAMPEVEI_Pos) | (CONF_RTC_OVFEO << RTC_MODE0_EVCTRL_OVFEO_Pos));
+#endif
+
+	hri_rtcmode0_write_CTRLA_reg(dev->hw, RTC_MODE0_CTRLA_PRESCALER(CONF_RTC_PRESCALER) | RTC_MODE0_CTRLA_COUNTSYNC);
+    198c:	6820      	ldr	r0, [r4, #0]
+}
+
+static inline void hri_rtcmode0_write_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg = data;
+    198e:	f44f 4301 	mov.w	r3, #33024	; 0x8100
+    1992:	8003      	strh	r3, [r0, #0]
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+    1994:	f248 0103 	movw	r1, #32771	; 0x8003
+    1998:	4790      	blx	r2
+
+	hri_rtc_write_TAMPCTRL_reg(
+	    dev->hw,
+    199a:	6823      	ldr	r3, [r4, #0]
+}
+
+static inline void hri_rtc_write_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = data;
+    199c:	2000      	movs	r0, #0
+    199e:	6618      	str	r0, [r3, #96]	; 0x60
+	    | (CONF_RTC_TAMPER_INACT_2 == TAMPER_MODE_ACTL) | (CONF_RTC_TAMPER_INACT_3 == TAMPER_MODE_ACTL)
+	    | (CONF_RTC_TAMPER_INACT_4 == TAMPER_MODE_ACTL)) {
+		hri_rtcmode0_set_CTRLB_RTCOUT_bit(dev->hw);
+	}
+	return ERR_NONE;
+}
+    19a0:	bd10      	pop	{r4, pc}
+    19a2:	bf00      	nop
+    19a4:	0000305c 	.word	0x0000305c
+    19a8:	00001605 	.word	0x00001605
+    19ac:	200002ec 	.word	0x200002ec
+    19b0:	00001931 	.word	0x00001931
+
+000019b4 <RTC_Handler>:
+/**
+ * \brief Rtc interrupt handler
+ */
+void RTC_Handler(void)
+{
+	_rtc_interrupt_handler(_rtc_dev);
+    19b4:	4b0d      	ldr	r3, [pc, #52]	; (19ec <RTC_Handler+0x38>)
+{
+    19b6:	b510      	push	{r4, lr}
+	_rtc_interrupt_handler(_rtc_dev);
+    19b8:	681c      	ldr	r4, [r3, #0]
+	uint16_t interrupt_status  = hri_rtcmode0_read_INTFLAG_reg(dev->hw);
+    19ba:	6822      	ldr	r2, [r4, #0]
+	return ((Rtc *)hw)->MODE0.INTFLAG.reg;
+    19bc:	8991      	ldrh	r1, [r2, #12]
+	return ((Rtc *)hw)->MODE0.INTENSET.reg;
+    19be:	8953      	ldrh	r3, [r2, #10]
+    19c0:	b29b      	uxth	r3, r3
+	if ((interrupt_status & interrupt_enabled) & RTC_MODE2_INTFLAG_ALARM0) {
+    19c2:	400b      	ands	r3, r1
+    19c4:	05da      	lsls	r2, r3, #23
+    19c6:	d507      	bpl.n	19d8 <RTC_Handler+0x24>
+		dev->callback(dev);
+    19c8:	6863      	ldr	r3, [r4, #4]
+    19ca:	4620      	mov	r0, r4
+    19cc:	4798      	blx	r3
+		hri_rtcmode0_clear_interrupt_CMP0_bit(dev->hw);
+    19ce:	6823      	ldr	r3, [r4, #0]
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0;
+    19d0:	f44f 7280 	mov.w	r2, #256	; 0x100
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER;
+    19d4:	819a      	strh	r2, [r3, #12]
+}
+    19d6:	bd10      	pop	{r4, pc}
+	} else if ((interrupt_status & interrupt_enabled) & RTC_MODE2_INTFLAG_TAMPER) {
+    19d8:	045b      	lsls	r3, r3, #17
+    19da:	d5fc      	bpl.n	19d6 <RTC_Handler+0x22>
+		dev->callback_tamper(dev);
+    19dc:	68a3      	ldr	r3, [r4, #8]
+    19de:	4620      	mov	r0, r4
+    19e0:	4798      	blx	r3
+		hri_rtcmode0_clear_interrupt_TAMPER_bit(dev->hw);
+    19e2:	6823      	ldr	r3, [r4, #0]
+    19e4:	f44f 4280 	mov.w	r2, #16384	; 0x4000
+    19e8:	e7f4      	b.n	19d4 <RTC_Handler+0x20>
+    19ea:	bf00      	nop
+    19ec:	200002ec 	.word	0x200002ec
+
+000019f0 <gpio_set_pin_direction>:
+	_gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction);
+    19f0:	f000 031f 	and.w	r3, r0, #31
+{
+    19f4:	b530      	push	{r4, r5, lr}
+	_gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction);
+    19f6:	2501      	movs	r5, #1
+    19f8:	409d      	lsls	r5, r3
+	((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask;
+    19fa:	0940      	lsrs	r0, r0, #5
+    19fc:	4b0d      	ldr	r3, [pc, #52]	; (1a34 <gpio_set_pin_direction+0x44>)
+    19fe:	01c0      	lsls	r0, r0, #7
+	switch (direction) {
+    1a00:	2902      	cmp	r1, #2
+		hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN | (mask & 0xffff));
+    1a02:	b2ac      	uxth	r4, r5
+		                                | ((mask & 0xffff0000) >> 16));
+    1a04:	ea4f 4215 	mov.w	r2, r5, lsr #16
+	((Port *)hw)->Group[submodule_index].DIRSET.reg = mask;
+    1a08:	4403      	add	r3, r0
+	switch (direction) {
+    1a0a:	d00b      	beq.n	1a24 <gpio_set_pin_direction+0x34>
+		hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN | (mask & 0xffff));
+    1a0c:	f044 4480 	orr.w	r4, r4, #1073741824	; 0x40000000
+    1a10:	f444 3400 	orr.w	r4, r4, #131072	; 0x20000
+		hri_port_write_WRCONFIG_reg(PORT,
+    1a14:	f042 4240 	orr.w	r2, r2, #3221225472	; 0xc0000000
+	((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask;
+    1a18:	605d      	str	r5, [r3, #4]
+    1a1a:	f442 3200 	orr.w	r2, r2, #131072	; 0x20000
+
+static inline void hri_port_write_WRCONFIG_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_port_wrconfig_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
+    1a1e:	629c      	str	r4, [r3, #40]	; 0x28
+    1a20:	629a      	str	r2, [r3, #40]	; 0x28
+}
+    1a22:	bd30      	pop	{r4, r5, pc}
+		hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff));
+    1a24:	f044 4480 	orr.w	r4, r4, #1073741824	; 0x40000000
+	((Port *)hw)->Group[submodule_index].DIRSET.reg = mask;
+    1a28:	609d      	str	r5, [r3, #8]
+		hri_port_write_WRCONFIG_reg(
+    1a2a:	f042 4240 	orr.w	r2, r2, #3221225472	; 0xc0000000
+	((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
+    1a2e:	629c      	str	r4, [r3, #40]	; 0x28
+    1a30:	e7f6      	b.n	1a20 <gpio_set_pin_direction+0x30>
+    1a32:	bf00      	nop
+    1a34:	41008000 	.word	0x41008000
+
+00001a38 <gpio_set_pin_pull_mode.constprop.0>:
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PULLEN;
+    1a38:	0942      	lsrs	r2, r0, #5
+    1a3a:	f000 031f 	and.w	r3, r0, #31
+    1a3e:	eb03 13c2 	add.w	r3, r3, r2, lsl #7
+    1a42:	f103 4382 	add.w	r3, r3, #1090519040	; 0x41000000
+    1a46:	f503 4300 	add.w	r3, r3, #32768	; 0x8000
+    1a4a:	f893 2040 	ldrb.w	r2, [r3, #64]	; 0x40
+    1a4e:	f002 02fb 	and.w	r2, r2, #251	; 0xfb
+    1a52:	f883 2040 	strb.w	r2, [r3, #64]	; 0x40
+}
+    1a56:	4770      	bx	lr
+
+00001a58 <_gpio_set_pin_function>:
+/**
+ * \brief Set gpio pin function
+ */
+static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function)
+{
+	uint8_t port = GPIO_PORT(gpio);
+    1a58:	0943      	lsrs	r3, r0, #5
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+    1a5a:	01db      	lsls	r3, r3, #7
+    1a5c:	f103 4382 	add.w	r3, r3, #1090519040	; 0x41000000
+{
+    1a60:	b530      	push	{r4, r5, lr}
+    1a62:	f503 4300 	add.w	r3, r3, #32768	; 0x8000
+	uint8_t pin  = GPIO_PIN(gpio);
+    1a66:	f000 041f 	and.w	r4, r0, #31
+    1a6a:	191d      	adds	r5, r3, r4
+    1a6c:	eb03 0354 	add.w	r3, r3, r4, lsr #1
+    1a70:	f895 2040 	ldrb.w	r2, [r5, #64]	; 0x40
+	tmp &= ~PORT_PINCFG_PMUXEN;
+    1a74:	f002 02fe 	and.w	r2, r2, #254	; 0xfe
+	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+    1a78:	f042 0201 	orr.w	r2, r2, #1
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+    1a7c:	f885 2040 	strb.w	r2, [r5, #64]	; 0x40
+	} else {
+		hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, true);
+
+		if (pin & 1) {
+			// Odd numbered pin
+			hri_port_write_PMUX_PMUXO_bf(PORT, port, pin >> 1, function & 0xffff);
+    1a80:	b2ca      	uxtb	r2, r1
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+    1a82:	f893 1030 	ldrb.w	r1, [r3, #48]	; 0x30
+		if (pin & 1) {
+    1a86:	f010 0f01 	tst.w	r0, #1
+	tmp &= ~PORT_PMUX_PMUXO_Msk;
+    1a8a:	bf1b      	ittet	ne
+    1a8c:	f001 010f 	andne.w	r1, r1, #15
+	tmp |= PORT_PMUX_PMUXO(data);
+    1a90:	ea41 1102 	orrne.w	r1, r1, r2, lsl #4
+	tmp &= ~PORT_PMUX_PMUXE_Msk;
+    1a94:	f001 01f0 	andeq.w	r1, r1, #240	; 0xf0
+	tmp |= PORT_PMUX_PMUXO(data);
+    1a98:	b2c9      	uxtbne	r1, r1
+	tmp |= PORT_PMUX_PMUXE(data);
+    1a9a:	bf08      	it	eq
+    1a9c:	4311      	orreq	r1, r2
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+    1a9e:	f883 1030 	strb.w	r1, [r3, #48]	; 0x30
+		} else {
+			// Even numbered pin
+			hri_port_write_PMUX_PMUXE_bf(PORT, port, pin >> 1, function & 0xffff);
+		}
+	}
+}
+    1aa2:	bd30      	pop	{r4, r5, pc}
+
+00001aa4 <CALENDER_INTERFACE_CLOCK_init>:
+}
+
+static inline void hri_mclk_set_APBAMASK_RTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RTC;
+    1aa4:	4a02      	ldr	r2, [pc, #8]	; (1ab0 <CALENDER_INTERFACE_CLOCK_init+0xc>)
+    1aa6:	6953      	ldr	r3, [r2, #20]
+    1aa8:	f443 7300 	orr.w	r3, r3, #512	; 0x200
+    1aac:	6153      	str	r3, [r2, #20]
+struct mci_sync_desc IO_BUS;
+
+void CALENDER_INTERFACE_CLOCK_init(void)
+{
+	hri_mclk_set_APBAMASK_RTC_bit(MCLK);
+}
+    1aae:	4770      	bx	lr
+    1ab0:	40000800 	.word	0x40000800
+
+00001ab4 <CALENDER_INTERFACE_init>:
+
+void CALENDER_INTERFACE_init(void)
+{
+    1ab4:	b510      	push	{r4, lr}
+	CALENDER_INTERFACE_CLOCK_init();
+    1ab6:	4b04      	ldr	r3, [pc, #16]	; (1ac8 <CALENDER_INTERFACE_init+0x14>)
+	calendar_init(&CALENDER_INTERFACE, RTC);
+    1ab8:	4904      	ldr	r1, [pc, #16]	; (1acc <CALENDER_INTERFACE_init+0x18>)
+    1aba:	4805      	ldr	r0, [pc, #20]	; (1ad0 <CALENDER_INTERFACE_init+0x1c>)
+	CALENDER_INTERFACE_CLOCK_init();
+    1abc:	4798      	blx	r3
+}
+    1abe:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
+	calendar_init(&CALENDER_INTERFACE, RTC);
+    1ac2:	4b04      	ldr	r3, [pc, #16]	; (1ad4 <CALENDER_INTERFACE_init+0x20>)
+    1ac4:	4718      	bx	r3
+    1ac6:	bf00      	nop
+    1ac8:	00001aa5 	.word	0x00001aa5
+    1acc:	40002400 	.word	0x40002400
+    1ad0:	200002f0 	.word	0x200002f0
+    1ad4:	00000315 	.word	0x00000315
+
+00001ad8 <USART_DBG_PORT_init>:
+
+void USART_DBG_PORT_init(void)
+{
+    1ad8:	b510      	push	{r4, lr}
+	_gpio_set_pin_function(pin, function);
+    1ada:	4c05      	ldr	r4, [pc, #20]	; (1af0 <USART_DBG_PORT_init+0x18>)
+    1adc:	4905      	ldr	r1, [pc, #20]	; (1af4 <USART_DBG_PORT_init+0x1c>)
+    1ade:	2039      	movs	r0, #57	; 0x39
+    1ae0:	47a0      	blx	r4
+    1ae2:	4623      	mov	r3, r4
+    1ae4:	4904      	ldr	r1, [pc, #16]	; (1af8 <USART_DBG_PORT_init+0x20>)
+
+	gpio_set_pin_function(PB25, PINMUX_PB25D_SERCOM2_PAD0);
+
+	gpio_set_pin_function(PB24, PINMUX_PB24D_SERCOM2_PAD1);
+}
+    1ae6:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
+    1aea:	2038      	movs	r0, #56	; 0x38
+    1aec:	4718      	bx	r3
+    1aee:	bf00      	nop
+    1af0:	00001a59 	.word	0x00001a59
+    1af4:	00390003 	.word	0x00390003
+    1af8:	00380003 	.word	0x00380003
+
+00001afc <USART_DBG_CLOCK_init>:
+}
+
+static inline void hri_gclk_write_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg = data;
+    1afc:	4b06      	ldr	r3, [pc, #24]	; (1b18 <USART_DBG_CLOCK_init+0x1c>)
+    1afe:	2240      	movs	r2, #64	; 0x40
+    1b00:	f8c3 20dc 	str.w	r2, [r3, #220]	; 0xdc
+    1b04:	2243      	movs	r2, #67	; 0x43
+    1b06:	f8c3 208c 	str.w	r2, [r3, #140]	; 0x8c
+}
+
+static inline void hri_mclk_set_APBBMASK_SERCOM2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_SERCOM2;
+    1b0a:	4a04      	ldr	r2, [pc, #16]	; (1b1c <USART_DBG_CLOCK_init+0x20>)
+    1b0c:	6993      	ldr	r3, [r2, #24]
+    1b0e:	f443 7300 	orr.w	r3, r3, #512	; 0x200
+    1b12:	6193      	str	r3, [r2, #24]
+{
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+
+	hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK);
+}
+    1b14:	4770      	bx	lr
+    1b16:	bf00      	nop
+    1b18:	40001c00 	.word	0x40001c00
+    1b1c:	40000800 	.word	0x40000800
+
+00001b20 <USART_DBG_init>:
+
+void USART_DBG_init(void)
+{
+    1b20:	b510      	push	{r4, lr}
+	USART_DBG_CLOCK_init();
+    1b22:	4b05      	ldr	r3, [pc, #20]	; (1b38 <USART_DBG_init+0x18>)
+	usart_sync_init(&USART_DBG, SERCOM2, (void *)NULL);
+    1b24:	4905      	ldr	r1, [pc, #20]	; (1b3c <USART_DBG_init+0x1c>)
+    1b26:	4806      	ldr	r0, [pc, #24]	; (1b40 <USART_DBG_init+0x20>)
+	USART_DBG_CLOCK_init();
+    1b28:	4798      	blx	r3
+	usart_sync_init(&USART_DBG, SERCOM2, (void *)NULL);
+    1b2a:	4b06      	ldr	r3, [pc, #24]	; (1b44 <USART_DBG_init+0x24>)
+    1b2c:	2200      	movs	r2, #0
+    1b2e:	4798      	blx	r3
+	USART_DBG_PORT_init();
+}
+    1b30:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
+	USART_DBG_PORT_init();
+    1b34:	4b04      	ldr	r3, [pc, #16]	; (1b48 <USART_DBG_init+0x28>)
+    1b36:	4718      	bx	r3
+    1b38:	00001afd 	.word	0x00001afd
+    1b3c:	41012000 	.word	0x41012000
+    1b40:	20000310 	.word	0x20000310
+    1b44:	0000177d 	.word	0x0000177d
+    1b48:	00001ad9 	.word	0x00001ad9
+
+00001b4c <SPI_SD_MMC_PORT_init>:
+
+void SPI_SD_MMC_PORT_init(void)
+{
+    1b4c:	b570      	push	{r4, r5, r6, lr}
+	((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask;
+    1b4e:	4e11      	ldr	r6, [pc, #68]	; (1b94 <SPI_SD_MMC_PORT_init+0x48>)
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	// Set pin direction to output
+	gpio_set_pin_direction(PB27, GPIO_DIRECTION_OUT);
+    1b50:	4d11      	ldr	r5, [pc, #68]	; (1b98 <SPI_SD_MMC_PORT_init+0x4c>)
+    1b52:	4c12      	ldr	r4, [pc, #72]	; (1b9c <SPI_SD_MMC_PORT_init+0x50>)
+    1b54:	f04f 6300 	mov.w	r3, #134217728	; 0x8000000
+    1b58:	f8c6 3094 	str.w	r3, [r6, #148]	; 0x94
+    1b5c:	2102      	movs	r1, #2
+    1b5e:	203b      	movs	r0, #59	; 0x3b
+    1b60:	47a8      	blx	r5
+    1b62:	490f      	ldr	r1, [pc, #60]	; (1ba0 <SPI_SD_MMC_PORT_init+0x54>)
+    1b64:	203b      	movs	r0, #59	; 0x3b
+    1b66:	47a0      	blx	r4
+    1b68:	f04f 6380 	mov.w	r3, #67108864	; 0x4000000
+    1b6c:	f8c6 3094 	str.w	r3, [r6, #148]	; 0x94
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	// Set pin direction to output
+	gpio_set_pin_direction(PB26, GPIO_DIRECTION_OUT);
+    1b70:	2102      	movs	r1, #2
+    1b72:	203a      	movs	r0, #58	; 0x3a
+    1b74:	47a8      	blx	r5
+    1b76:	490b      	ldr	r1, [pc, #44]	; (1ba4 <SPI_SD_MMC_PORT_init+0x58>)
+    1b78:	203a      	movs	r0, #58	; 0x3a
+    1b7a:	47a0      	blx	r4
+
+	gpio_set_pin_function(PB26, PINMUX_PB26D_SERCOM4_PAD1);
+
+	// Set pin direction to input
+	gpio_set_pin_direction(PB29, GPIO_DIRECTION_IN);
+    1b7c:	2101      	movs	r1, #1
+    1b7e:	203d      	movs	r0, #61	; 0x3d
+    1b80:	47a8      	blx	r5
+
+	gpio_set_pin_pull_mode(PB29,
+    1b82:	4b09      	ldr	r3, [pc, #36]	; (1ba8 <SPI_SD_MMC_PORT_init+0x5c>)
+    1b84:	4909      	ldr	r1, [pc, #36]	; (1bac <SPI_SD_MMC_PORT_init+0x60>)
+    1b86:	203d      	movs	r0, #61	; 0x3d
+    1b88:	4798      	blx	r3
+    1b8a:	4623      	mov	r3, r4
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(PB29, PINMUX_PB29D_SERCOM4_PAD3);
+}
+    1b8c:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
+    1b90:	4718      	bx	r3
+    1b92:	bf00      	nop
+    1b94:	41008000 	.word	0x41008000
+    1b98:	000019f1 	.word	0x000019f1
+    1b9c:	00001a59 	.word	0x00001a59
+    1ba0:	003b0003 	.word	0x003b0003
+    1ba4:	003a0003 	.word	0x003a0003
+    1ba8:	00001a39 	.word	0x00001a39
+    1bac:	003d0003 	.word	0x003d0003
+
+00001bb0 <SPI_SD_MMC_CLOCK_init>:
+    1bb0:	4b06      	ldr	r3, [pc, #24]	; (1bcc <SPI_SD_MMC_CLOCK_init+0x1c>)
+    1bb2:	2240      	movs	r2, #64	; 0x40
+    1bb4:	f8c3 2108 	str.w	r2, [r3, #264]	; 0x108
+    1bb8:	2243      	movs	r2, #67	; 0x43
+    1bba:	f8c3 208c 	str.w	r2, [r3, #140]	; 0x8c
+}
+
+static inline void hri_mclk_set_APBDMASK_SERCOM4_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM4;
+    1bbe:	4a04      	ldr	r2, [pc, #16]	; (1bd0 <SPI_SD_MMC_CLOCK_init+0x20>)
+    1bc0:	6a13      	ldr	r3, [r2, #32]
+    1bc2:	f043 0301 	orr.w	r3, r3, #1
+    1bc6:	6213      	str	r3, [r2, #32]
+{
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM4_GCLK_ID_CORE, CONF_GCLK_SERCOM4_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM4_GCLK_ID_SLOW, CONF_GCLK_SERCOM4_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+
+	hri_mclk_set_APBDMASK_SERCOM4_bit(MCLK);
+}
+    1bc8:	4770      	bx	lr
+    1bca:	bf00      	nop
+    1bcc:	40001c00 	.word	0x40001c00
+    1bd0:	40000800 	.word	0x40000800
+
+00001bd4 <SPI_SD_MMC_init>:
+
+void SPI_SD_MMC_init(void)
+{
+    1bd4:	b510      	push	{r4, lr}
+	SPI_SD_MMC_CLOCK_init();
+    1bd6:	4b05      	ldr	r3, [pc, #20]	; (1bec <SPI_SD_MMC_init+0x18>)
+	spi_m_sync_init(&SPI_SD_MMC, SERCOM4);
+    1bd8:	4805      	ldr	r0, [pc, #20]	; (1bf0 <SPI_SD_MMC_init+0x1c>)
+	SPI_SD_MMC_CLOCK_init();
+    1bda:	4798      	blx	r3
+	spi_m_sync_init(&SPI_SD_MMC, SERCOM4);
+    1bdc:	f04f 4186 	mov.w	r1, #1124073472	; 0x43000000
+    1be0:	4b04      	ldr	r3, [pc, #16]	; (1bf4 <SPI_SD_MMC_init+0x20>)
+    1be2:	4798      	blx	r3
+	SPI_SD_MMC_PORT_init();
+}
+    1be4:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
+	SPI_SD_MMC_PORT_init();
+    1be8:	4b03      	ldr	r3, [pc, #12]	; (1bf8 <SPI_SD_MMC_init+0x24>)
+    1bea:	4718      	bx	r3
+    1bec:	00001bb1 	.word	0x00001bb1
+    1bf0:	2000031c 	.word	0x2000031c
+    1bf4:	00001429 	.word	0x00001429
+    1bf8:	00001b4d 	.word	0x00001b4d
+
+00001bfc <IO_BUS_PORT_init>:
+
+void IO_BUS_PORT_init(void)
+{
+    1bfc:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
+    1c00:	4e21      	ldr	r6, [pc, #132]	; (1c88 <IO_BUS_PORT_init+0x8c>)
+
+	gpio_set_pin_direction(PB11,
+    1c02:	4f22      	ldr	r7, [pc, #136]	; (1c8c <IO_BUS_PORT_init+0x90>)
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	gpio_set_pin_pull_mode(PB11,
+    1c04:	4d22      	ldr	r5, [pc, #136]	; (1c90 <IO_BUS_PORT_init+0x94>)
+    1c06:	4c23      	ldr	r4, [pc, #140]	; (1c94 <IO_BUS_PORT_init+0x98>)
+    1c08:	f44f 6900 	mov.w	r9, #2048	; 0x800
+	gpio_set_pin_direction(PB11,
+    1c0c:	2102      	movs	r1, #2
+    1c0e:	202b      	movs	r0, #43	; 0x2b
+    1c10:	47b8      	blx	r7
+	gpio_set_pin_pull_mode(PB11,
+    1c12:	202b      	movs	r0, #43	; 0x2b
+    1c14:	4920      	ldr	r1, [pc, #128]	; (1c98 <IO_BUS_PORT_init+0x9c>)
+    1c16:	f8c6 9094 	str.w	r9, [r6, #148]	; 0x94
+    1c1a:	47a8      	blx	r5
+    1c1c:	47a0      	blx	r4
+	                      // <GPIO_PIN_FUNCTION_L"> L
+	                      // <GPIO_PIN_FUNCTION_M"> M
+	                      // <GPIO_PIN_FUNCTION_N"> N
+	                      PINMUX_PB11I_SDHC0_SDCK);
+
+	gpio_set_pin_direction(PA08,
+    1c1e:	2102      	movs	r1, #2
+    1c20:	2008      	movs	r0, #8
+    1c22:	47b8      	blx	r7
+    1c24:	f44f 7380 	mov.w	r3, #256	; 0x100
+    1c28:	6173      	str	r3, [r6, #20]
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	gpio_set_pin_pull_mode(PA08,
+    1c2a:	2008      	movs	r0, #8
+    1c2c:	f04f 1108 	mov.w	r1, #524296	; 0x80008
+    1c30:	47a8      	blx	r5
+    1c32:	47a0      	blx	r4
+	                      // <GPIO_PIN_FUNCTION_L"> L
+	                      // <GPIO_PIN_FUNCTION_M"> M
+	                      // <GPIO_PIN_FUNCTION_N"> N
+	                      PINMUX_PA08I_SDHC0_SDCMD);
+
+	gpio_set_pin_direction(PA09,
+    1c34:	2102      	movs	r1, #2
+    1c36:	2009      	movs	r0, #9
+    1c38:	47b8      	blx	r7
+    1c3a:	f44f 7300 	mov.w	r3, #512	; 0x200
+    1c3e:	6173      	str	r3, [r6, #20]
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	gpio_set_pin_pull_mode(PA09,
+    1c40:	2009      	movs	r0, #9
+    1c42:	4916      	ldr	r1, [pc, #88]	; (1c9c <IO_BUS_PORT_init+0xa0>)
+    1c44:	47a8      	blx	r5
+    1c46:	f44f 6880 	mov.w	r8, #1024	; 0x400
+    1c4a:	47a0      	blx	r4
+	                      // <GPIO_PIN_FUNCTION_L"> L
+	                      // <GPIO_PIN_FUNCTION_M"> M
+	                      // <GPIO_PIN_FUNCTION_N"> N
+	                      PINMUX_PA09I_SDHC0_SDDAT0);
+
+	gpio_set_pin_direction(PA10,
+    1c4c:	2102      	movs	r1, #2
+    1c4e:	200a      	movs	r0, #10
+    1c50:	47b8      	blx	r7
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	gpio_set_pin_pull_mode(PA10,
+    1c52:	200a      	movs	r0, #10
+    1c54:	4912      	ldr	r1, [pc, #72]	; (1ca0 <IO_BUS_PORT_init+0xa4>)
+    1c56:	f8c6 8014 	str.w	r8, [r6, #20]
+    1c5a:	47a8      	blx	r5
+    1c5c:	47a0      	blx	r4
+	                      // <GPIO_PIN_FUNCTION_L"> L
+	                      // <GPIO_PIN_FUNCTION_M"> M
+	                      // <GPIO_PIN_FUNCTION_N"> N
+	                      PINMUX_PA10I_SDHC0_SDDAT1);
+
+	gpio_set_pin_direction(PA11,
+    1c5e:	2102      	movs	r1, #2
+    1c60:	200b      	movs	r0, #11
+    1c62:	47b8      	blx	r7
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	gpio_set_pin_pull_mode(PA11,
+    1c64:	200b      	movs	r0, #11
+    1c66:	490f      	ldr	r1, [pc, #60]	; (1ca4 <IO_BUS_PORT_init+0xa8>)
+    1c68:	f8c6 9014 	str.w	r9, [r6, #20]
+    1c6c:	47a8      	blx	r5
+    1c6e:	47a0      	blx	r4
+	                      // <GPIO_PIN_FUNCTION_L"> L
+	                      // <GPIO_PIN_FUNCTION_M"> M
+	                      // <GPIO_PIN_FUNCTION_N"> N
+	                      PINMUX_PA11I_SDHC0_SDDAT2);
+
+	gpio_set_pin_direction(PB10,
+    1c70:	2102      	movs	r1, #2
+    1c72:	202a      	movs	r0, #42	; 0x2a
+    1c74:	47b8      	blx	r7
+    1c76:	f8c6 8094 	str.w	r8, [r6, #148]	; 0x94
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	gpio_set_pin_pull_mode(PB10,
+    1c7a:	202a      	movs	r0, #42	; 0x2a
+    1c7c:	47a8      	blx	r5
+    1c7e:	490a      	ldr	r1, [pc, #40]	; (1ca8 <IO_BUS_PORT_init+0xac>)
+    1c80:	4623      	mov	r3, r4
+	                      // <GPIO_PIN_FUNCTION_K"> K
+	                      // <GPIO_PIN_FUNCTION_L"> L
+	                      // <GPIO_PIN_FUNCTION_M"> M
+	                      // <GPIO_PIN_FUNCTION_N"> N
+	                      PINMUX_PB10I_SDHC0_SDDAT3);
+}
+    1c82:	e8bd 47f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
+    1c86:	4718      	bx	r3
+    1c88:	41008000 	.word	0x41008000
+    1c8c:	000019f1 	.word	0x000019f1
+    1c90:	00001a39 	.word	0x00001a39
+    1c94:	00001a59 	.word	0x00001a59
+    1c98:	002b0008 	.word	0x002b0008
+    1c9c:	00090008 	.word	0x00090008
+    1ca0:	000a0008 	.word	0x000a0008
+    1ca4:	000b0008 	.word	0x000b0008
+    1ca8:	002a0008 	.word	0x002a0008
+
+00001cac <IO_BUS_CLOCK_init>:
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_SDHC0;
+    1cac:	4a05      	ldr	r2, [pc, #20]	; (1cc4 <IO_BUS_CLOCK_init+0x18>)
+    1cae:	6913      	ldr	r3, [r2, #16]
+    1cb0:	f443 4300 	orr.w	r3, r3, #32768	; 0x8000
+    1cb4:	6113      	str	r3, [r2, #16]
+    1cb6:	4b04      	ldr	r3, [pc, #16]	; (1cc8 <IO_BUS_CLOCK_init+0x1c>)
+    1cb8:	2240      	movs	r2, #64	; 0x40
+    1cba:	f8c3 2134 	str.w	r2, [r3, #308]	; 0x134
+    1cbe:	f8c3 208c 	str.w	r2, [r3, #140]	; 0x8c
+void IO_BUS_CLOCK_init(void)
+{
+	hri_mclk_set_AHBMASK_SDHC0_bit(MCLK);
+	hri_gclk_write_PCHCTRL_reg(GCLK, SDHC0_GCLK_ID, CONF_GCLK_SDHC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, SDHC0_GCLK_ID_SLOW, CONF_GCLK_SDHC0_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+}
+    1cc2:	4770      	bx	lr
+    1cc4:	40000800 	.word	0x40000800
+    1cc8:	40001c00 	.word	0x40001c00
+
+00001ccc <IO_BUS_init>:
+
+void IO_BUS_init(void)
+{
+    1ccc:	b510      	push	{r4, lr}
+	IO_BUS_CLOCK_init();
+    1cce:	4b05      	ldr	r3, [pc, #20]	; (1ce4 <IO_BUS_init+0x18>)
+	mci_sync_init(&IO_BUS, SDHC0);
+    1cd0:	4805      	ldr	r0, [pc, #20]	; (1ce8 <IO_BUS_init+0x1c>)
+	IO_BUS_CLOCK_init();
+    1cd2:	4798      	blx	r3
+	mci_sync_init(&IO_BUS, SDHC0);
+    1cd4:	f04f 418a 	mov.w	r1, #1157627904	; 0x45000000
+    1cd8:	4b04      	ldr	r3, [pc, #16]	; (1cec <IO_BUS_init+0x20>)
+    1cda:	4798      	blx	r3
+	IO_BUS_PORT_init();
+}
+    1cdc:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
+	IO_BUS_PORT_init();
+    1ce0:	4b03      	ldr	r3, [pc, #12]	; (1cf0 <IO_BUS_init+0x24>)
+    1ce2:	4718      	bx	r3
+    1ce4:	00001cad 	.word	0x00001cad
+    1ce8:	20000338 	.word	0x20000338
+    1cec:	00001549 	.word	0x00001549
+    1cf0:	00001bfd 	.word	0x00001bfd
+
+00001cf4 <delay_driver_init>:
+
+void delay_driver_init(void)
+{
+	delay_init(SysTick);
+    1cf4:	4801      	ldr	r0, [pc, #4]	; (1cfc <delay_driver_init+0x8>)
+    1cf6:	4b02      	ldr	r3, [pc, #8]	; (1d00 <delay_driver_init+0xc>)
+    1cf8:	4718      	bx	r3
+    1cfa:	bf00      	nop
+    1cfc:	e000e010 	.word	0xe000e010
+    1d00:	00001579 	.word	0x00001579
+
+00001d04 <system_init>:
+}
+
+void system_init(void)
+{
+    1d04:	b510      	push	{r4, lr}
+ * Currently the following initialization functions are supported:
+ *  - System clock initialization
+ */
+static inline void init_mcu(void)
+{
+	_init_chip();
+    1d06:	4b07      	ldr	r3, [pc, #28]	; (1d24 <system_init+0x20>)
+    1d08:	4798      	blx	r3
+	init_mcu();
+
+	CALENDER_INTERFACE_init();
+    1d0a:	4b07      	ldr	r3, [pc, #28]	; (1d28 <system_init+0x24>)
+    1d0c:	4798      	blx	r3
+
+	USART_DBG_init();
+    1d0e:	4b07      	ldr	r3, [pc, #28]	; (1d2c <system_init+0x28>)
+    1d10:	4798      	blx	r3
+
+	SPI_SD_MMC_init();
+    1d12:	4b07      	ldr	r3, [pc, #28]	; (1d30 <system_init+0x2c>)
+    1d14:	4798      	blx	r3
+
+	IO_BUS_init();
+    1d16:	4b07      	ldr	r3, [pc, #28]	; (1d34 <system_init+0x30>)
+    1d18:	4798      	blx	r3
+
+	delay_driver_init();
+}
+    1d1a:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
+	delay_driver_init();
+    1d1e:	4b06      	ldr	r3, [pc, #24]	; (1d38 <system_init+0x34>)
+    1d20:	4718      	bx	r3
+    1d22:	bf00      	nop
+    1d24:	00001589 	.word	0x00001589
+    1d28:	00001ab5 	.word	0x00001ab5
+    1d2c:	00001b21 	.word	0x00001b21
+    1d30:	00001bd5 	.word	0x00001bd5
+    1d34:	00001ccd 	.word	0x00001ccd
+    1d38:	00001cf5 	.word	0x00001cf5
+
+00001d3c <hri_sercomspi_wait_for_sync>:
+	return ((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_sercomspi_wait_for_sync(const void *const hw, hri_sercomspi_syncbusy_reg_t reg)
+{
+	while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) {
+    1d3c:	69c3      	ldr	r3, [r0, #28]
+    1d3e:	420b      	tst	r3, r1
+    1d40:	d1fc      	bne.n	1d3c <hri_sercomspi_wait_for_sync>
+	};
+}
+    1d42:	4770      	bx	lr
+
+00001d44 <hri_sercomusart_wait_for_sync>:
+	return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_sercomusart_wait_for_sync(const void *const hw, hri_sercomusart_syncbusy_reg_t reg)
+{
+	while (((Sercom *)hw)->USART.SYNCBUSY.reg & reg) {
+    1d44:	69c3      	ldr	r3, [r0, #28]
+    1d46:	420b      	tst	r3, r1
+    1d48:	d1fc      	bne.n	1d44 <hri_sercomusart_wait_for_sync>
+	};
+}
+    1d4a:	4770      	bx	lr
+
+00001d4c <hri_sercomspi_clear_CTRLA_ENABLE_bit>:
+}
+
+static inline void hri_sercomspi_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE;
+    1d4c:	6802      	ldr	r2, [r0, #0]
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+    1d4e:	4b03      	ldr	r3, [pc, #12]	; (1d5c <hri_sercomspi_clear_CTRLA_ENABLE_bit+0x10>)
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE;
+    1d50:	f022 0202 	bic.w	r2, r2, #2
+    1d54:	6002      	str	r2, [r0, #0]
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+    1d56:	2103      	movs	r1, #3
+    1d58:	4718      	bx	r3
+    1d5a:	bf00      	nop
+    1d5c:	00001d3d 	.word	0x00001d3d
+
+00001d60 <hri_sercomusart_clear_CTRLA_ENABLE_bit>:
+}
+
+static inline void hri_sercomusart_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE;
+    1d60:	6802      	ldr	r2, [r0, #0]
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+    1d62:	4b03      	ldr	r3, [pc, #12]	; (1d70 <hri_sercomusart_clear_CTRLA_ENABLE_bit+0x10>)
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE;
+    1d64:	f022 0202 	bic.w	r2, r2, #2
+    1d68:	6002      	str	r2, [r0, #0]
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+    1d6a:	2103      	movs	r1, #3
+    1d6c:	4718      	bx	r3
+    1d6e:	bf00      	nop
+    1d70:	00001d45 	.word	0x00001d45
+
+00001d74 <_sercom_get_hardware_index>:
+
+/**
+ * \brief Retrieve ordinal number of the given sercom hardware instance
+ */
+static uint8_t _sercom_get_hardware_index(const void *const hw)
+{
+    1d74:	b570      	push	{r4, r5, r6, lr}
+	Sercom *const sercom_modules[] = SERCOM_INSTS;
+    1d76:	4d0c      	ldr	r5, [pc, #48]	; (1da8 <_sercom_get_hardware_index+0x34>)
+{
+    1d78:	4606      	mov	r6, r0
+	Sercom *const sercom_modules[] = SERCOM_INSTS;
+    1d7a:	cd0f      	ldmia	r5!, {r0, r1, r2, r3}
+{
+    1d7c:	b088      	sub	sp, #32
+	Sercom *const sercom_modules[] = SERCOM_INSTS;
+    1d7e:	466c      	mov	r4, sp
+    1d80:	c40f      	stmia	r4!, {r0, r1, r2, r3}
+    1d82:	e895 000f 	ldmia.w	r5, {r0, r1, r2, r3}
+    1d86:	e884 000f 	stmia.w	r4, {r0, r1, r2, r3}
+	/* Find index for SERCOM instance. */
+	for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
+    1d8a:	466a      	mov	r2, sp
+    1d8c:	2300      	movs	r3, #0
+		if ((uint32_t)hw == (uint32_t)sercom_modules[i]) {
+    1d8e:	f852 1b04 	ldr.w	r1, [r2], #4
+    1d92:	42b1      	cmp	r1, r6
+    1d94:	d102      	bne.n	1d9c <_sercom_get_hardware_index+0x28>
+			return i;
+    1d96:	b2d8      	uxtb	r0, r3
+		}
+	}
+	return 0;
+}
+    1d98:	b008      	add	sp, #32
+    1d9a:	bd70      	pop	{r4, r5, r6, pc}
+	for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
+    1d9c:	3301      	adds	r3, #1
+    1d9e:	2b08      	cmp	r3, #8
+    1da0:	d1f5      	bne.n	1d8e <_sercom_get_hardware_index+0x1a>
+	return 0;
+    1da2:	2000      	movs	r0, #0
+    1da4:	e7f8      	b.n	1d98 <_sercom_get_hardware_index+0x24>
+    1da6:	bf00      	nop
+    1da8:	0000308c 	.word	0x0000308c
+
+00001dac <_usart_init>:
+ * \param[in] hw The pointer to hardware instance
+ *
+ * \return The status of initialization
+ */
+static int32_t _usart_init(void *const hw)
+{
+    1dac:	b538      	push	{r3, r4, r5, lr}
+	uint8_t sercom_offset = _sercom_get_hardware_index(hw);
+    1dae:	4b1b      	ldr	r3, [pc, #108]	; (1e1c <_usart_init+0x70>)
+{
+    1db0:	4604      	mov	r4, r0
+	uint8_t sercom_offset = _sercom_get_hardware_index(hw);
+    1db2:	4798      	blx	r3
+		if (_usarts[i].number == sercom_offset) {
+    1db4:	2802      	cmp	r0, #2
+    1db6:	d005      	beq.n	1dc4 <_usart_init+0x18>
+	ASSERT(false);
+    1db8:	4919      	ldr	r1, [pc, #100]	; (1e20 <_usart_init+0x74>)
+    1dba:	4b1a      	ldr	r3, [pc, #104]	; (1e24 <_usart_init+0x78>)
+    1dbc:	f240 2247 	movw	r2, #583	; 0x247
+    1dc0:	2000      	movs	r0, #0
+    1dc2:	4798      	blx	r3
+	return ((Sercom *)hw)->USART.SYNCBUSY.reg & reg;
+    1dc4:	69e3      	ldr	r3, [r4, #28]
+    1dc6:	4d18      	ldr	r5, [pc, #96]	; (1e28 <_usart_init+0x7c>)
+	uint8_t i = _get_sercom_index(hw);
+
+	if (!hri_sercomusart_is_syncing(hw, SERCOM_USART_SYNCBUSY_SWRST)) {
+    1dc8:	f013 0f01 	tst.w	r3, #1
+    1dcc:	d10e      	bne.n	1dec <_usart_init+0x40>
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_reg(const void *const           hw,
+                                                                        hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+    1dce:	2103      	movs	r1, #3
+    1dd0:	4620      	mov	r0, r4
+    1dd2:	47a8      	blx	r5
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+    1dd4:	6823      	ldr	r3, [r4, #0]
+		uint32_t mode = _usarts[i].ctrl_a & SERCOM_USART_CTRLA_MODE_Msk;
+		if (hri_sercomusart_get_CTRLA_reg(hw, SERCOM_USART_CTRLA_ENABLE)) {
+    1dd6:	079b      	lsls	r3, r3, #30
+    1dd8:	d503      	bpl.n	1de2 <_usart_init+0x36>
+			hri_sercomusart_clear_CTRLA_ENABLE_bit(hw);
+    1dda:	4b14      	ldr	r3, [pc, #80]	; (1e2c <_usart_init+0x80>)
+    1ddc:	4798      	blx	r3
+			hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE);
+    1dde:	2102      	movs	r1, #2
+    1de0:	47a8      	blx	r5
+}
+
+static inline void hri_sercomusart_write_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg = data;
+    1de2:	2305      	movs	r3, #5
+    1de4:	6023      	str	r3, [r4, #0]
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+    1de6:	2103      	movs	r1, #3
+    1de8:	4620      	mov	r0, r4
+    1dea:	47a8      	blx	r5
+		}
+		hri_sercomusart_write_CTRLA_reg(hw, SERCOM_USART_CTRLA_SWRST | mode);
+	}
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST);
+    1dec:	4620      	mov	r0, r4
+    1dee:	2101      	movs	r1, #1
+    1df0:	47a8      	blx	r5
+	((Sercom *)hw)->USART.CTRLA.reg = data;
+    1df2:	4b0f      	ldr	r3, [pc, #60]	; (1e30 <_usart_init+0x84>)
+    1df4:	6023      	str	r3, [r4, #0]
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+    1df6:	2103      	movs	r1, #3
+    1df8:	47a8      	blx	r5
+}
+
+static inline void hri_sercomusart_write_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg = data;
+    1dfa:	f44f 3340 	mov.w	r3, #196608	; 0x30000
+    1dfe:	6063      	str	r3, [r4, #4]
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+    1e00:	211f      	movs	r1, #31
+    1e02:	47a8      	blx	r5
+}
+
+static inline void hri_sercomusart_write_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg = data;
+    1e04:	4b0b      	ldr	r3, [pc, #44]	; (1e34 <_usart_init+0x88>)
+    1e06:	60a3      	str	r3, [r4, #8]
+}
+
+static inline void hri_sercomusart_write_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg = data;
+    1e08:	f64f 4311 	movw	r3, #64529	; 0xfc11
+    1e0c:	81a3      	strh	r3, [r4, #12]
+}
+
+static inline void hri_sercomusart_write_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg = data;
+    1e0e:	2300      	movs	r3, #0
+    1e10:	73a3      	strb	r3, [r4, #14]
+
+	hri_sercomusart_write_RXPL_reg(hw, _usarts[i].rxpl);
+	hri_sercomusart_write_DBGCTRL_reg(hw, _usarts[i].debug_ctrl);
+
+	return ERR_NONE;
+}
+    1e12:	4618      	mov	r0, r3
+}
+
+static inline void hri_sercomusart_write_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg = data;
+    1e14:	f884 3030 	strb.w	r3, [r4, #48]	; 0x30
+    1e18:	bd38      	pop	{r3, r4, r5, pc}
+    1e1a:	bf00      	nop
+    1e1c:	00001d75 	.word	0x00001d75
+    1e20:	00003071 	.word	0x00003071
+    1e24:	00001605 	.word	0x00001605
+    1e28:	00001d45 	.word	0x00001d45
+    1e2c:	00001d61 	.word	0x00001d61
+    1e30:	40100004 	.word	0x40100004
+    1e34:	00700002 	.word	0x00700002
+
+00001e38 <_usart_sync_init>:
+{
+    1e38:	b570      	push	{r4, r5, r6, lr}
+	ASSERT(device);
+    1e3a:	4605      	mov	r5, r0
+    1e3c:	3800      	subs	r0, #0
+{
+    1e3e:	460c      	mov	r4, r1
+	ASSERT(device);
+    1e40:	4b05      	ldr	r3, [pc, #20]	; (1e58 <_usart_sync_init+0x20>)
+    1e42:	4906      	ldr	r1, [pc, #24]	; (1e5c <_usart_sync_init+0x24>)
+    1e44:	bf18      	it	ne
+    1e46:	2001      	movne	r0, #1
+    1e48:	22bb      	movs	r2, #187	; 0xbb
+    1e4a:	4798      	blx	r3
+	device->hw = hw;
+    1e4c:	602c      	str	r4, [r5, #0]
+	return _usart_init(hw);
+    1e4e:	4620      	mov	r0, r4
+    1e50:	4b03      	ldr	r3, [pc, #12]	; (1e60 <_usart_sync_init+0x28>)
+}
+    1e52:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
+	return _usart_init(hw);
+    1e56:	4718      	bx	r3
+    1e58:	00001605 	.word	0x00001605
+    1e5c:	00003071 	.word	0x00003071
+    1e60:	00001dad 	.word	0x00001dad
+
+00001e64 <_usart_sync_enable>:
+	hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw);
+    1e64:	6800      	ldr	r0, [r0, #0]
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
+    1e66:	6803      	ldr	r3, [r0, #0]
+    1e68:	f043 0302 	orr.w	r3, r3, #2
+    1e6c:	6003      	str	r3, [r0, #0]
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+    1e6e:	2103      	movs	r1, #3
+    1e70:	4b00      	ldr	r3, [pc, #0]	; (1e74 <_usart_sync_enable+0x10>)
+    1e72:	4718      	bx	r3
+    1e74:	00001d45 	.word	0x00001d45
+
+00001e78 <_usart_sync_write_byte>:
+	hri_sercomusart_write_DATA_reg(device->hw, data);
+    1e78:	6803      	ldr	r3, [r0, #0]
+	((Sercom *)hw)->USART.DATA.reg = data;
+    1e7a:	6299      	str	r1, [r3, #40]	; 0x28
+}
+    1e7c:	4770      	bx	lr
+
+00001e7e <_usart_sync_read_byte>:
+	return hri_sercomusart_read_DATA_reg(device->hw);
+    1e7e:	6803      	ldr	r3, [r0, #0]
+	return ((Sercom *)hw)->USART.DATA.reg;
+    1e80:	6a98      	ldr	r0, [r3, #40]	; 0x28
+}
+    1e82:	b2c0      	uxtb	r0, r0
+    1e84:	4770      	bx	lr
+
+00001e86 <_usart_sync_is_ready_to_send>:
+	return hri_sercomusart_get_interrupt_DRE_bit(device->hw);
+    1e86:	6803      	ldr	r3, [r0, #0]
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos;
+    1e88:	7e18      	ldrb	r0, [r3, #24]
+}
+    1e8a:	f000 0001 	and.w	r0, r0, #1
+    1e8e:	4770      	bx	lr
+
+00001e90 <_usart_sync_is_transmit_done>:
+	return hri_sercomusart_get_interrupt_TXC_bit(device->hw);
+    1e90:	6803      	ldr	r3, [r0, #0]
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos;
+    1e92:	7e18      	ldrb	r0, [r3, #24]
+}
+    1e94:	f3c0 0040 	ubfx	r0, r0, #1, #1
+    1e98:	4770      	bx	lr
+
+00001e9a <_usart_sync_is_byte_received>:
+	return hri_sercomusart_get_interrupt_RXC_bit(device->hw);
+    1e9a:	6803      	ldr	r3, [r0, #0]
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos;
+    1e9c:	7e18      	ldrb	r0, [r3, #24]
+}
+    1e9e:	f3c0 0080 	ubfx	r0, r0, #2, #1
+    1ea2:	4770      	bx	lr
+
+00001ea4 <_spi_m_sync_init>:
+
+	return NULL;
+}
+
+int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw)
+{
+    1ea4:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
+	uint8_t n = _sercom_get_hardware_index((const void *)hw_addr);
+    1ea8:	4b44      	ldr	r3, [pc, #272]	; (1fbc <_spi_m_sync_init+0x118>)
+	return NULL;
+    1eaa:	4d45      	ldr	r5, [pc, #276]	; (1fc0 <_spi_m_sync_init+0x11c>)
+{
+    1eac:	4607      	mov	r7, r0
+	uint8_t n = _sercom_get_hardware_index((const void *)hw_addr);
+    1eae:	4608      	mov	r0, r1
+{
+    1eb0:	460c      	mov	r4, r1
+	uint8_t n = _sercom_get_hardware_index((const void *)hw_addr);
+    1eb2:	4798      	blx	r3
+	return NULL;
+    1eb4:	2804      	cmp	r0, #4
+    1eb6:	bf18      	it	ne
+    1eb8:	2500      	movne	r5, #0
+	const struct sercomspi_regs_cfg *regs = _spi_get_regs((uint32_t)hw);
+
+	ASSERT(dev && hw);
+    1eba:	2f00      	cmp	r7, #0
+    1ebc:	d05d      	beq.n	1f7a <_spi_m_sync_init+0xd6>
+    1ebe:	1e20      	subs	r0, r4, #0
+    1ec0:	bf18      	it	ne
+    1ec2:	2001      	movne	r0, #1
+    1ec4:	4e3f      	ldr	r6, [pc, #252]	; (1fc4 <_spi_m_sync_init+0x120>)
+    1ec6:	4940      	ldr	r1, [pc, #256]	; (1fc8 <_spi_m_sync_init+0x124>)
+    1ec8:	f640 123f 	movw	r2, #2367	; 0x93f
+    1ecc:	47b0      	blx	r6
+
+	if (regs == NULL) {
+    1ece:	46b0      	mov	r8, r6
+    1ed0:	2d00      	cmp	r5, #0
+    1ed2:	d070      	beq.n	1fb6 <_spi_m_sync_init+0x112>
+	return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg;
+    1ed4:	69e3      	ldr	r3, [r4, #28]
+    1ed6:	4e3d      	ldr	r6, [pc, #244]	; (1fcc <_spi_m_sync_init+0x128>)
+		return ERR_INVALID_ARG;
+	}
+
+	if (!hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) {
+    1ed8:	f013 0f01 	tst.w	r3, #1
+    1edc:	d113      	bne.n	1f06 <_spi_m_sync_init+0x62>
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+    1ede:	2103      	movs	r1, #3
+    1ee0:	4620      	mov	r0, r4
+		uint32_t mode = regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk;
+    1ee2:	f8d5 9000 	ldr.w	r9, [r5]
+    1ee6:	47b0      	blx	r6
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+    1ee8:	6823      	ldr	r3, [r4, #0]
+		if (hri_sercomspi_get_CTRLA_reg(hw, SERCOM_SPI_CTRLA_ENABLE)) {
+    1eea:	079b      	lsls	r3, r3, #30
+		uint32_t mode = regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk;
+    1eec:	f009 091c 	and.w	r9, r9, #28
+		if (hri_sercomspi_get_CTRLA_reg(hw, SERCOM_SPI_CTRLA_ENABLE)) {
+    1ef0:	d503      	bpl.n	1efa <_spi_m_sync_init+0x56>
+			hri_sercomspi_clear_CTRLA_ENABLE_bit(hw);
+    1ef2:	4b37      	ldr	r3, [pc, #220]	; (1fd0 <_spi_m_sync_init+0x12c>)
+    1ef4:	4798      	blx	r3
+			hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_ENABLE);
+    1ef6:	2102      	movs	r1, #2
+    1ef8:	47b0      	blx	r6
+		}
+		hri_sercomspi_write_CTRLA_reg(hw, SERCOM_SPI_CTRLA_SWRST | mode);
+    1efa:	f049 0301 	orr.w	r3, r9, #1
+	((Sercom *)hw)->SPI.CTRLA.reg = data;
+    1efe:	6023      	str	r3, [r4, #0]
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+    1f00:	2103      	movs	r1, #3
+    1f02:	4620      	mov	r0, r4
+    1f04:	47b0      	blx	r6
+	}
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST);
+    1f06:	2101      	movs	r1, #1
+    1f08:	4620      	mov	r0, r4
+    1f0a:	47b0      	blx	r6
+
+	dev->prvt = hw;
+
+	if ((regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk) == SERCOM_USART_CTRLA_MODE_SPI_SLAVE) {
+    1f0c:	682b      	ldr	r3, [r5, #0]
+    1f0e:	f8df 90c4 	ldr.w	r9, [pc, #196]	; 1fd4 <_spi_m_sync_init+0x130>
+	dev->prvt = hw;
+    1f12:	603c      	str	r4, [r7, #0]
+	if ((regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk) == SERCOM_USART_CTRLA_MODE_SPI_SLAVE) {
+    1f14:	f003 031c 	and.w	r3, r3, #28
+    1f18:	2b08      	cmp	r3, #8
+    1f1a:	d130      	bne.n	1f7e <_spi_m_sync_init+0xda>
+	ASSERT(hw && regs);
+    1f1c:	492a      	ldr	r1, [pc, #168]	; (1fc8 <_spi_m_sync_init+0x124>)
+    1f1e:	2001      	movs	r0, #1
+    1f20:	f640 121d 	movw	r2, #2333	; 0x91d
+    1f24:	47c0      	blx	r8
+	    hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST));
+    1f26:	682b      	ldr	r3, [r5, #0]
+	hri_sercomspi_write_CTRLA_reg(
+    1f28:	ea03 0309 	and.w	r3, r3, r9
+	((Sercom *)hw)->SPI.CTRLA.reg = data;
+    1f2c:	6023      	str	r3, [r4, #0]
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+    1f2e:	2103      	movs	r1, #3
+    1f30:	4620      	mov	r0, r4
+    1f32:	47b0      	blx	r6
+	                              (regs->ctrlb & ~(SERCOM_SPI_CTRLB_MSSEN))
+    1f34:	686b      	ldr	r3, [r5, #4]
+	                                  | (SERCOM_SPI_CTRLB_RXEN | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN));
+    1f36:	f423 3308 	bic.w	r3, r3, #139264	; 0x22000
+    1f3a:	f423 7310 	bic.w	r3, r3, #576	; 0x240
+	hri_sercomspi_write_CTRLB_reg(hw,
+    1f3e:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
+    1f42:	f443 7310 	orr.w	r3, r3, #576	; 0x240
+	((Sercom *)hw)->SPI.CTRLB.reg = data;
+    1f46:	6063      	str	r3, [r4, #4]
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+    1f48:	2117      	movs	r1, #23
+    1f4a:	47b0      	blx	r6
+	hri_sercomspi_write_ADDR_reg(hw, regs->addr);
+    1f4c:	68ab      	ldr	r3, [r5, #8]
+	((Sercom *)hw)->SPI.ADDR.reg = data;
+    1f4e:	6263      	str	r3, [r4, #36]	; 0x24
+	hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl);
+    1f50:	7b6b      	ldrb	r3, [r5, #13]
+	((Sercom *)hw)->SPI.DBGCTRL.reg = data;
+    1f52:	f884 3030 	strb.w	r3, [r4, #48]	; 0x30
+	return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg;
+    1f56:	69e3      	ldr	r3, [r4, #28]
+	while (hri_sercomspi_is_syncing(hw, 0xFFFFFFFF))
+    1f58:	2b00      	cmp	r3, #0
+    1f5a:	d1fc      	bne.n	1f56 <_spi_m_sync_init+0xb2>
+	} else {
+		_spi_load_regs_master(hw, regs);
+	}
+
+	/* Load character size from default hardware configuration */
+	dev->char_size = ((regs->ctrlb & SERCOM_SPI_CTRLB_CHSIZE_Msk) == 0) ? 1 : 2;
+    1f5c:	686b      	ldr	r3, [r5, #4]
+    1f5e:	f013 0f07 	tst.w	r3, #7
+    1f62:	bf0c      	ite	eq
+    1f64:	2301      	moveq	r3, #1
+    1f66:	2302      	movne	r3, #2
+    1f68:	713b      	strb	r3, [r7, #4]
+
+	dev->dummy_byte = regs->dummy_byte;
+    1f6a:	7bab      	ldrb	r3, [r5, #14]
+    1f6c:	7bea      	ldrb	r2, [r5, #15]
+    1f6e:	ea43 2302 	orr.w	r3, r3, r2, lsl #8
+    1f72:	80fb      	strh	r3, [r7, #6]
+
+	return ERR_NONE;
+    1f74:	2000      	movs	r0, #0
+}
+    1f76:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
+	ASSERT(dev && hw);
+    1f7a:	4638      	mov	r0, r7
+    1f7c:	e7a2      	b.n	1ec4 <_spi_m_sync_init+0x20>
+	ASSERT(hw && regs);
+    1f7e:	4912      	ldr	r1, [pc, #72]	; (1fc8 <_spi_m_sync_init+0x124>)
+    1f80:	2001      	movs	r0, #1
+    1f82:	f640 1209 	movw	r2, #2313	; 0x909
+    1f86:	47c0      	blx	r8
+	    hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST));
+    1f88:	682b      	ldr	r3, [r5, #0]
+	hri_sercomspi_write_CTRLA_reg(
+    1f8a:	ea03 0309 	and.w	r3, r3, r9
+	((Sercom *)hw)->SPI.CTRLA.reg = data;
+    1f8e:	6023      	str	r3, [r4, #0]
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+    1f90:	2103      	movs	r1, #3
+    1f92:	4620      	mov	r0, r4
+    1f94:	47b0      	blx	r6
+	    (regs->ctrlb
+    1f96:	686b      	ldr	r3, [r5, #4]
+	        | (SERCOM_SPI_CTRLB_RXEN));
+    1f98:	f423 3338 	bic.w	r3, r3, #188416	; 0x2e000
+    1f9c:	f423 7310 	bic.w	r3, r3, #576	; 0x240
+	hri_sercomspi_write_CTRLB_reg(
+    1fa0:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
+	((Sercom *)hw)->SPI.CTRLB.reg = data;
+    1fa4:	6063      	str	r3, [r4, #4]
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+    1fa6:	2117      	movs	r1, #23
+    1fa8:	47b0      	blx	r6
+	hri_sercomspi_write_BAUD_reg(hw, regs->baud);
+    1faa:	7b2b      	ldrb	r3, [r5, #12]
+	((Sercom *)hw)->SPI.BAUD.reg = data;
+    1fac:	7323      	strb	r3, [r4, #12]
+	hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl);
+    1fae:	7b6b      	ldrb	r3, [r5, #13]
+	((Sercom *)hw)->SPI.DBGCTRL.reg = data;
+    1fb0:	f884 3030 	strb.w	r3, [r4, #48]	; 0x30
+}
+    1fb4:	e7d2      	b.n	1f5c <_spi_m_sync_init+0xb8>
+		return ERR_INVALID_ARG;
+    1fb6:	f06f 000c 	mvn.w	r0, #12
+    1fba:	e7dc      	b.n	1f76 <_spi_m_sync_init+0xd2>
+    1fbc:	00001d75 	.word	0x00001d75
+    1fc0:	000030c4 	.word	0x000030c4
+    1fc4:	00001605 	.word	0x00001605
+    1fc8:	00003071 	.word	0x00003071
+    1fcc:	00001d3d 	.word	0x00001d3d
+    1fd0:	00001d4d 	.word	0x00001d4d
+    1fd4:	fffffefc 	.word	0xfffffefc
+
+00001fd8 <_spi_m_sync_trans>:
+
+	return ERR_NONE;
+}
+
+int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg)
+{
+    1fd8:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
+	void *                 hw   = dev->prvt;
+    1fdc:	6804      	ldr	r4, [r0, #0]
+	int32_t                rc   = 0;
+	struct _spi_trans_ctrl ctrl = {msg->txbuf, msg->rxbuf, 0, 0, dev->char_size};
+    1fde:	f890 8004 	ldrb.w	r8, [r0, #4]
+
+	ASSERT(dev && hw);
+    1fe2:	4b2a      	ldr	r3, [pc, #168]	; (208c <_spi_m_sync_trans+0xb4>)
+{
+    1fe4:	4607      	mov	r7, r0
+	ASSERT(dev && hw);
+    1fe6:	1e20      	subs	r0, r4, #0
+	struct _spi_trans_ctrl ctrl = {msg->txbuf, msg->rxbuf, 0, 0, dev->char_size};
+    1fe8:	e9d1 6500 	ldrd	r6, r5, [r1]
+	ASSERT(dev && hw);
+    1fec:	f640 22a3 	movw	r2, #2723	; 0xaa3
+    1ff0:	bf18      	it	ne
+    1ff2:	2001      	movne	r0, #1
+{
+    1ff4:	4689      	mov	r9, r1
+	ASSERT(dev && hw);
+    1ff6:	4926      	ldr	r1, [pc, #152]	; (2090 <_spi_m_sync_trans+0xb8>)
+    1ff8:	4798      	blx	r3
+	return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg;
+    1ffa:	69e2      	ldr	r2, [r4, #28]
+
+	/* If settings are not applied (pending), we can not go on */
+	if (hri_sercomspi_is_syncing(
+    1ffc:	f012 0207 	ands.w	r2, r2, #7
+    2000:	d13e      	bne.n	2080 <_spi_m_sync_trans+0xa8>
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+    2002:	4b24      	ldr	r3, [pc, #144]	; (2094 <_spi_m_sync_trans+0xbc>)
+    2004:	2103      	movs	r1, #3
+    2006:	4620      	mov	r0, r4
+    2008:	4798      	blx	r3
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+    200a:	6823      	ldr	r3, [r4, #0]
+	        hw, (SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE | SERCOM_SPI_SYNCBUSY_CTRLB))) {
+		return ERR_BUSY;
+	}
+
+	/* SPI must be enabled to start synchronous transfer */
+	if (!hri_sercomspi_get_CTRLA_ENABLE_bit(hw)) {
+    200c:	0799      	lsls	r1, r3, #30
+    200e:	d53a      	bpl.n	2086 <_spi_m_sync_trans+0xae>
+	struct _spi_trans_ctrl ctrl = {msg->txbuf, msg->rxbuf, 0, 0, dev->char_size};
+    2010:	4611      	mov	r1, r2
+	return ((Sercom *)hw)->SPI.INTFLAG.reg;
+    2012:	7e23      	ldrb	r3, [r4, #24]
+    2014:	b2d8      	uxtb	r0, r3
+	if (!(iflag & SERCOM_SPI_INTFLAG_RXC)) {
+    2016:	075b      	lsls	r3, r3, #29
+    2018:	d40f      	bmi.n	203a <_spi_m_sync_trans+0x62>
+		uint32_t iflag = hri_sercomspi_read_INTFLAG_reg(hw);
+
+		if (!_spi_rx_check_and_receive(hw, iflag, &ctrl)) {
+			/* In master mode, do not start next byte before previous byte received
+			 * to make better output waveform */
+			if (ctrl.rxcnt >= ctrl.txcnt) {
+    201a:	428a      	cmp	r2, r1
+    201c:	d818      	bhi.n	2050 <_spi_m_sync_trans+0x78>
+	if (!(SERCOM_SPI_INTFLAG_DRE & iflag)) {
+    201e:	07c3      	lsls	r3, r0, #31
+    2020:	d516      	bpl.n	2050 <_spi_m_sync_trans+0x78>
+				_spi_tx_check_and_send(hw, iflag, &ctrl, dev->dummy_byte);
+    2022:	88fb      	ldrh	r3, [r7, #6]
+	if (ctrl->txbuf) {
+    2024:	b136      	cbz	r6, 2034 <_spi_m_sync_trans+0x5c>
+		if (ctrl->char_size > 1) {
+    2026:	f1b8 0f01 	cmp.w	r8, #1
+		data = *ctrl->txbuf++;
+    202a:	7833      	ldrb	r3, [r6, #0]
+			data |= (*ctrl->txbuf) << 8;
+    202c:	bf8c      	ite	hi
+    202e:	f836 3b02 	ldrhhi.w	r3, [r6], #2
+		data = *ctrl->txbuf++;
+    2032:	3601      	addls	r6, #1
+	ctrl->txcnt++;
+    2034:	3201      	adds	r2, #1
+	((Sercom *)hw)->SPI.DATA.reg = data;
+    2036:	62a3      	str	r3, [r4, #40]	; 0x28
+}
+    2038:	e00a      	b.n	2050 <_spi_m_sync_trans+0x78>
+	return ((Sercom *)hw)->SPI.DATA.reg;
+    203a:	6aa3      	ldr	r3, [r4, #40]	; 0x28
+	if (ctrl->rxbuf) {
+    203c:	b13d      	cbz	r5, 204e <_spi_m_sync_trans+0x76>
+		if (ctrl->char_size > 1) {
+    203e:	f1b8 0f01 	cmp.w	r8, #1
+		*ctrl->rxbuf++ = (uint8_t)data;
+    2042:	702b      	strb	r3, [r5, #0]
+			*ctrl->rxbuf++ = (uint8_t)(data >> 8);
+    2044:	bf85      	ittet	hi
+    2046:	0a1b      	lsrhi	r3, r3, #8
+    2048:	706b      	strbhi	r3, [r5, #1]
+		*ctrl->rxbuf++ = (uint8_t)data;
+    204a:	3501      	addls	r5, #1
+			*ctrl->rxbuf++ = (uint8_t)(data >> 8);
+    204c:	3502      	addhi	r5, #2
+	ctrl->rxcnt++;
+    204e:	3101      	adds	r1, #1
+	if (SERCOM_SPI_INTFLAG_ERROR & iflag) {
+    2050:	0600      	lsls	r0, r0, #24
+    2052:	d407      	bmi.n	2064 <_spi_m_sync_trans+0x8c>
+		rc = _spi_err_check(iflag, hw);
+
+		if (rc < 0) {
+			break;
+		}
+		if (ctrl.txcnt >= msg->size && ctrl.rxcnt >= msg->size) {
+    2054:	f8d9 3008 	ldr.w	r3, [r9, #8]
+    2058:	4293      	cmp	r3, r2
+    205a:	d8da      	bhi.n	2012 <_spi_m_sync_trans+0x3a>
+    205c:	428b      	cmp	r3, r1
+    205e:	d8d8      	bhi.n	2012 <_spi_m_sync_trans+0x3a>
+			rc = ctrl.txcnt;
+    2060:	4610      	mov	r0, r2
+	while (!(hri_sercomspi_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE))) {
+    2062:	e006      	b.n	2072 <_spi_m_sync_trans+0x9a>
+}
+
+static inline void hri_sercomspi_clear_STATUS_reg(const void *const hw, hri_sercomspi_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.STATUS.reg = mask;
+    2064:	f64f 73ff 	movw	r3, #65535	; 0xffff
+    2068:	8363      	strh	r3, [r4, #26]
+	((Sercom *)hw)->SPI.INTFLAG.reg = mask;
+    206a:	2380      	movs	r3, #128	; 0x80
+    206c:	7623      	strb	r3, [r4, #24]
+		return ERR_OVERFLOW;
+    206e:	f06f 0012 	mvn.w	r0, #18
+	tmp = ((Sercom *)hw)->SPI.INTFLAG.reg;
+    2072:	7e23      	ldrb	r3, [r4, #24]
+	while (!(hri_sercomspi_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE))) {
+    2074:	079b      	lsls	r3, r3, #30
+    2076:	d0fc      	beq.n	2072 <_spi_m_sync_trans+0x9a>
+	((Sercom *)hw)->SPI.INTFLAG.reg = mask;
+    2078:	2303      	movs	r3, #3
+    207a:	7623      	strb	r3, [r4, #24]
+	}
+	/* Wait until SPI bus idle */
+	_spi_wait_bus_idle(hw);
+
+	return rc;
+}
+    207c:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
+		return ERR_BUSY;
+    2080:	f06f 0003 	mvn.w	r0, #3
+    2084:	e7fa      	b.n	207c <_spi_m_sync_trans+0xa4>
+		return ERR_NOT_INITIALIZED;
+    2086:	f06f 0013 	mvn.w	r0, #19
+    208a:	e7f7      	b.n	207c <_spi_m_sync_trans+0xa4>
+    208c:	00001605 	.word	0x00001605
+    2090:	00003071 	.word	0x00003071
+    2094:	00001d3d 	.word	0x00001d3d
+
+00002098 <atomic_enter_critical>:
+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+    2098:	f3ef 8310 	mrs	r3, PRIMASK
+/**
+ * \brief Disable interrupts, enter critical section
+ */
+void atomic_enter_critical(hal_atomic_t volatile *atomic)
+{
+	*atomic = __get_PRIMASK();
+    209c:	6003      	str	r3, [r0, #0]
+  __ASM volatile ("cpsid i" : : : "memory");
+    209e:	b672      	cpsid	i
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+    20a0:	f3bf 8f5f 	dmb	sy
+	__disable_irq();
+	__DMB();
+}
+    20a4:	4770      	bx	lr
+
+000020a6 <atomic_leave_critical>:
+    20a6:	f3bf 8f5f 	dmb	sy
+ * \brief Exit atomic section
+ */
+void atomic_leave_critical(hal_atomic_t volatile *atomic)
+{
+	__DMB();
+	__set_PRIMASK(*atomic);
+    20aa:	6803      	ldr	r3, [r0, #0]
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+    20ac:	f383 8810 	msr	PRIMASK, r3
+}
+    20b0:	4770      	bx	lr
+	...
+
+000020b4 <atmel_start_init>:
+
+/**
+ * Initializes MCU, drivers and middleware in the project
+ **/
+void atmel_start_init(void)
+{
+    20b4:	b510      	push	{r4, lr}
+	system_init();
+    20b6:	4b04      	ldr	r3, [pc, #16]	; (20c8 <atmel_start_init+0x14>)
+    20b8:	4798      	blx	r3
+	sd_mmc_stack_init();
+    20ba:	4b04      	ldr	r3, [pc, #16]	; (20cc <atmel_start_init+0x18>)
+    20bc:	4798      	blx	r3
+	diskio_init();
+}
+    20be:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
+	diskio_init();
+    20c2:	4b03      	ldr	r3, [pc, #12]	; (20d0 <atmel_start_init+0x1c>)
+    20c4:	4718      	bx	r3
+    20c6:	bf00      	nop
+    20c8:	00001d05 	.word	0x00001d05
+    20cc:	000003c5 	.word	0x000003c5
+    20d0:	00001851 	.word	0x00001851
+
+000020d4 <pprintf>:
+
+	return 0;
+}
+
+int pprintf(const char* fmt, ...)
+{
+    20d4:	b40f      	push	{r0, r1, r2, r3}
+    20d6:	b530      	push	{r4, r5, lr}
+    20d8:	b0c3      	sub	sp, #268	; 0x10c
+	size_t size_str = strlen(fmt);
+    20da:	4c11      	ldr	r4, [pc, #68]	; (2120 <pprintf+0x4c>)
+{
+    20dc:	9d46      	ldr	r5, [sp, #280]	; 0x118
+	size_t size_str = strlen(fmt);
+    20de:	4628      	mov	r0, r5
+    20e0:	47a0      	blx	r4
+	if (size_str >= MAX_PRINTF_BUFFER)
+    20e2:	28ff      	cmp	r0, #255	; 0xff
+    20e4:	d818      	bhi.n	2118 <pprintf+0x44>
+	{
+		return -1;
+	}
+	uint8_t printf_buffer[MAX_PRINTF_BUFFER];
+	memset(printf_buffer, '\0', MAX_PRINTF_BUFFER);
+    20e6:	4b0f      	ldr	r3, [pc, #60]	; (2124 <pprintf+0x50>)
+    20e8:	f44f 7280 	mov.w	r2, #256	; 0x100
+    20ec:	2100      	movs	r1, #0
+    20ee:	a802      	add	r0, sp, #8
+    20f0:	4798      	blx	r3
+	va_list args;
+	va_start(args, fmt);
+    20f2:	aa47      	add	r2, sp, #284	; 0x11c
+	vsprintf((char*)printf_buffer, fmt, args);
+    20f4:	4b0c      	ldr	r3, [pc, #48]	; (2128 <pprintf+0x54>)
+	va_start(args, fmt);
+    20f6:	9201      	str	r2, [sp, #4]
+	vsprintf((char*)printf_buffer, fmt, args);
+    20f8:	4629      	mov	r1, r5
+    20fa:	a802      	add	r0, sp, #8
+    20fc:	4798      	blx	r3
+	va_end(args);
+	return io_write(debug_io, (const uint8_t*)printf_buffer, strlen((const char*)printf_buffer));
+    20fe:	a802      	add	r0, sp, #8
+    2100:	47a0      	blx	r4
+    2102:	4b0a      	ldr	r3, [pc, #40]	; (212c <pprintf+0x58>)
+    2104:	b282      	uxth	r2, r0
+    2106:	a902      	add	r1, sp, #8
+    2108:	6818      	ldr	r0, [r3, #0]
+    210a:	4b09      	ldr	r3, [pc, #36]	; (2130 <pprintf+0x5c>)
+    210c:	4798      	blx	r3
+}
+    210e:	b043      	add	sp, #268	; 0x10c
+    2110:	e8bd 4030 	ldmia.w	sp!, {r4, r5, lr}
+    2114:	b004      	add	sp, #16
+    2116:	4770      	bx	lr
+		return -1;
+    2118:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
+    211c:	e7f7      	b.n	210e <pprintf+0x3a>
+    211e:	bf00      	nop
+    2120:	000021f9 	.word	0x000021f9
+    2124:	000021e9 	.word	0x000021e9
+    2128:	00002235 	.word	0x00002235
+    212c:	20000350 	.word	0x20000350
+    2130:	000002a5 	.word	0x000002a5
+
+00002134 <pdebug_init>:
+{
+    2134:	b510      	push	{r4, lr}
+	usart_sync_get_io_descriptor(&USART_DBG, &debug_io);
+    2136:	4c06      	ldr	r4, [pc, #24]	; (2150 <pdebug_init+0x1c>)
+    2138:	4906      	ldr	r1, [pc, #24]	; (2154 <pdebug_init+0x20>)
+    213a:	4b07      	ldr	r3, [pc, #28]	; (2158 <pdebug_init+0x24>)
+    213c:	4620      	mov	r0, r4
+    213e:	4798      	blx	r3
+	usart_sync_enable(&USART_DBG);
+    2140:	4b06      	ldr	r3, [pc, #24]	; (215c <pdebug_init+0x28>)
+    2142:	4620      	mov	r0, r4
+    2144:	4798      	blx	r3
+	printf("Debug Initialized\n");
+    2146:	4b06      	ldr	r3, [pc, #24]	; (2160 <pdebug_init+0x2c>)
+    2148:	4806      	ldr	r0, [pc, #24]	; (2164 <pdebug_init+0x30>)
+    214a:	4798      	blx	r3
+}
+    214c:	2000      	movs	r0, #0
+    214e:	bd10      	pop	{r4, pc}
+    2150:	20000310 	.word	0x20000310
+    2154:	20000350 	.word	0x20000350
+    2158:	000017e9 	.word	0x000017e9
+    215c:	000017bd 	.word	0x000017bd
+    2160:	000020d5 	.word	0x000020d5
+    2164:	000030d5 	.word	0x000030d5
+
+00002168 <passert>:
+
+void passert(const bool cond, const char* msg_failure, const char* file, const int line)
+{
+    2168:	b510      	push	{r4, lr}
+    216a:	460c      	mov	r4, r1
+    216c:	4619      	mov	r1, r3
+	if(!cond)
+    216e:	b920      	cbnz	r0, 217a <passert+0x12>
+	{
+		printf("Assert Failure at line %d, %s: %s\n",
+    2170:	4623      	mov	r3, r4
+    2172:	4802      	ldr	r0, [pc, #8]	; (217c <passert+0x14>)
+    2174:	4c02      	ldr	r4, [pc, #8]	; (2180 <passert+0x18>)
+    2176:	47a0      	blx	r4
+			   line,
+			   file,
+			   msg_failure);
+		for(;;){}
+    2178:	e7fe      	b.n	2178 <passert+0x10>
+	}
+}
+    217a:	bd10      	pop	{r4, pc}
+    217c:	000030e8 	.word	0x000030e8
+    2180:	000020d5 	.word	0x000020d5
+
+00002184 <__libc_init_array>:
+    2184:	b570      	push	{r4, r5, r6, lr}
+    2186:	4d0d      	ldr	r5, [pc, #52]	; (21bc <__libc_init_array+0x38>)
+    2188:	4c0d      	ldr	r4, [pc, #52]	; (21c0 <__libc_init_array+0x3c>)
+    218a:	1b64      	subs	r4, r4, r5
+    218c:	10a4      	asrs	r4, r4, #2
+    218e:	2600      	movs	r6, #0
+    2190:	42a6      	cmp	r6, r4
+    2192:	d109      	bne.n	21a8 <__libc_init_array+0x24>
+    2194:	4d0b      	ldr	r5, [pc, #44]	; (21c4 <__libc_init_array+0x40>)
+    2196:	4c0c      	ldr	r4, [pc, #48]	; (21c8 <__libc_init_array+0x44>)
+    2198:	f001 f802 	bl	31a0 <_init>
+    219c:	1b64      	subs	r4, r4, r5
+    219e:	10a4      	asrs	r4, r4, #2
+    21a0:	2600      	movs	r6, #0
+    21a2:	42a6      	cmp	r6, r4
+    21a4:	d105      	bne.n	21b2 <__libc_init_array+0x2e>
+    21a6:	bd70      	pop	{r4, r5, r6, pc}
+    21a8:	f855 3b04 	ldr.w	r3, [r5], #4
+    21ac:	4798      	blx	r3
+    21ae:	3601      	adds	r6, #1
+    21b0:	e7ee      	b.n	2190 <__libc_init_array+0xc>
+    21b2:	f855 3b04 	ldr.w	r3, [r5], #4
+    21b6:	4798      	blx	r3
+    21b8:	3601      	adds	r6, #1
+    21ba:	e7f2      	b.n	21a2 <__libc_init_array+0x1e>
+    21bc:	000031ac 	.word	0x000031ac
+    21c0:	000031ac 	.word	0x000031ac
+    21c4:	000031ac 	.word	0x000031ac
+    21c8:	000031b0 	.word	0x000031b0
+
+000021cc <memcpy>:
+    21cc:	440a      	add	r2, r1
+    21ce:	4291      	cmp	r1, r2
+    21d0:	f100 33ff 	add.w	r3, r0, #4294967295	; 0xffffffff
+    21d4:	d100      	bne.n	21d8 <memcpy+0xc>
+    21d6:	4770      	bx	lr
+    21d8:	b510      	push	{r4, lr}
+    21da:	f811 4b01 	ldrb.w	r4, [r1], #1
+    21de:	f803 4f01 	strb.w	r4, [r3, #1]!
+    21e2:	4291      	cmp	r1, r2
+    21e4:	d1f9      	bne.n	21da <memcpy+0xe>
+    21e6:	bd10      	pop	{r4, pc}
+
+000021e8 <memset>:
+    21e8:	4402      	add	r2, r0
+    21ea:	4603      	mov	r3, r0
+    21ec:	4293      	cmp	r3, r2
+    21ee:	d100      	bne.n	21f2 <memset+0xa>
+    21f0:	4770      	bx	lr
+    21f2:	f803 1b01 	strb.w	r1, [r3], #1
+    21f6:	e7f9      	b.n	21ec <memset+0x4>
+
+000021f8 <strlen>:
+    21f8:	4603      	mov	r3, r0
+    21fa:	f813 2b01 	ldrb.w	r2, [r3], #1
+    21fe:	2a00      	cmp	r2, #0
+    2200:	d1fb      	bne.n	21fa <strlen+0x2>
+    2202:	1a18      	subs	r0, r3, r0
+    2204:	3801      	subs	r0, #1
+    2206:	4770      	bx	lr
+
+00002208 <_vsiprintf_r>:
+    2208:	b500      	push	{lr}
+    220a:	b09b      	sub	sp, #108	; 0x6c
+    220c:	9100      	str	r1, [sp, #0]
+    220e:	9104      	str	r1, [sp, #16]
+    2210:	f06f 4100 	mvn.w	r1, #2147483648	; 0x80000000
+    2214:	9105      	str	r1, [sp, #20]
+    2216:	9102      	str	r1, [sp, #8]
+    2218:	4905      	ldr	r1, [pc, #20]	; (2230 <_vsiprintf_r+0x28>)
+    221a:	9103      	str	r1, [sp, #12]
+    221c:	4669      	mov	r1, sp
+    221e:	f000 f8cb 	bl	23b8 <_svfiprintf_r>
+    2222:	9b00      	ldr	r3, [sp, #0]
+    2224:	2200      	movs	r2, #0
+    2226:	701a      	strb	r2, [r3, #0]
+    2228:	b01b      	add	sp, #108	; 0x6c
+    222a:	f85d fb04 	ldr.w	pc, [sp], #4
+    222e:	bf00      	nop
+    2230:	ffff0208 	.word	0xffff0208
+
+00002234 <vsiprintf>:
+    2234:	4613      	mov	r3, r2
+    2236:	460a      	mov	r2, r1
+    2238:	4601      	mov	r1, r0
+    223a:	4802      	ldr	r0, [pc, #8]	; (2244 <vsiprintf+0x10>)
+    223c:	6800      	ldr	r0, [r0, #0]
+    223e:	f7ff bfe3 	b.w	2208 <_vsiprintf_r>
+    2242:	bf00      	nop
+    2244:	20000008 	.word	0x20000008
+
+00002248 <__retarget_lock_acquire_recursive>:
+    2248:	4770      	bx	lr
+
+0000224a <__retarget_lock_release_recursive>:
+    224a:	4770      	bx	lr
+
+0000224c <_malloc_r>:
+    224c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+    224e:	1ccd      	adds	r5, r1, #3
+    2250:	f025 0503 	bic.w	r5, r5, #3
+    2254:	3508      	adds	r5, #8
+    2256:	2d0c      	cmp	r5, #12
+    2258:	bf38      	it	cc
+    225a:	250c      	movcc	r5, #12
+    225c:	2d00      	cmp	r5, #0
+    225e:	4606      	mov	r6, r0
+    2260:	db01      	blt.n	2266 <_malloc_r+0x1a>
+    2262:	42a9      	cmp	r1, r5
+    2264:	d903      	bls.n	226e <_malloc_r+0x22>
+    2266:	230c      	movs	r3, #12
+    2268:	6033      	str	r3, [r6, #0]
+    226a:	2000      	movs	r0, #0
+    226c:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+    226e:	f000 fbb1 	bl	29d4 <__malloc_lock>
+    2272:	4921      	ldr	r1, [pc, #132]	; (22f8 <_malloc_r+0xac>)
+    2274:	680a      	ldr	r2, [r1, #0]
+    2276:	4614      	mov	r4, r2
+    2278:	b99c      	cbnz	r4, 22a2 <_malloc_r+0x56>
+    227a:	4f20      	ldr	r7, [pc, #128]	; (22fc <_malloc_r+0xb0>)
+    227c:	683b      	ldr	r3, [r7, #0]
+    227e:	b923      	cbnz	r3, 228a <_malloc_r+0x3e>
+    2280:	4621      	mov	r1, r4
+    2282:	4630      	mov	r0, r6
+    2284:	f000 fb2c 	bl	28e0 <_sbrk_r>
+    2288:	6038      	str	r0, [r7, #0]
+    228a:	4629      	mov	r1, r5
+    228c:	4630      	mov	r0, r6
+    228e:	f000 fb27 	bl	28e0 <_sbrk_r>
+    2292:	1c43      	adds	r3, r0, #1
+    2294:	d123      	bne.n	22de <_malloc_r+0x92>
+    2296:	230c      	movs	r3, #12
+    2298:	6033      	str	r3, [r6, #0]
+    229a:	4630      	mov	r0, r6
+    229c:	f000 fba0 	bl	29e0 <__malloc_unlock>
+    22a0:	e7e3      	b.n	226a <_malloc_r+0x1e>
+    22a2:	6823      	ldr	r3, [r4, #0]
+    22a4:	1b5b      	subs	r3, r3, r5
+    22a6:	d417      	bmi.n	22d8 <_malloc_r+0x8c>
+    22a8:	2b0b      	cmp	r3, #11
+    22aa:	d903      	bls.n	22b4 <_malloc_r+0x68>
+    22ac:	6023      	str	r3, [r4, #0]
+    22ae:	441c      	add	r4, r3
+    22b0:	6025      	str	r5, [r4, #0]
+    22b2:	e004      	b.n	22be <_malloc_r+0x72>
+    22b4:	6863      	ldr	r3, [r4, #4]
+    22b6:	42a2      	cmp	r2, r4
+    22b8:	bf0c      	ite	eq
+    22ba:	600b      	streq	r3, [r1, #0]
+    22bc:	6053      	strne	r3, [r2, #4]
+    22be:	4630      	mov	r0, r6
+    22c0:	f000 fb8e 	bl	29e0 <__malloc_unlock>
+    22c4:	f104 000b 	add.w	r0, r4, #11
+    22c8:	1d23      	adds	r3, r4, #4
+    22ca:	f020 0007 	bic.w	r0, r0, #7
+    22ce:	1ac2      	subs	r2, r0, r3
+    22d0:	d0cc      	beq.n	226c <_malloc_r+0x20>
+    22d2:	1a1b      	subs	r3, r3, r0
+    22d4:	50a3      	str	r3, [r4, r2]
+    22d6:	e7c9      	b.n	226c <_malloc_r+0x20>
+    22d8:	4622      	mov	r2, r4
+    22da:	6864      	ldr	r4, [r4, #4]
+    22dc:	e7cc      	b.n	2278 <_malloc_r+0x2c>
+    22de:	1cc4      	adds	r4, r0, #3
+    22e0:	f024 0403 	bic.w	r4, r4, #3
+    22e4:	42a0      	cmp	r0, r4
+    22e6:	d0e3      	beq.n	22b0 <_malloc_r+0x64>
+    22e8:	1a21      	subs	r1, r4, r0
+    22ea:	4630      	mov	r0, r6
+    22ec:	f000 faf8 	bl	28e0 <_sbrk_r>
+    22f0:	3001      	adds	r0, #1
+    22f2:	d1dd      	bne.n	22b0 <_malloc_r+0x64>
+    22f4:	e7cf      	b.n	2296 <_malloc_r+0x4a>
+    22f6:	bf00      	nop
+    22f8:	20000354 	.word	0x20000354
+    22fc:	20000358 	.word	0x20000358
+
+00002300 <__ssputs_r>:
+    2300:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
+    2304:	688e      	ldr	r6, [r1, #8]
+    2306:	429e      	cmp	r6, r3
+    2308:	4682      	mov	sl, r0
+    230a:	460c      	mov	r4, r1
+    230c:	4690      	mov	r8, r2
+    230e:	461f      	mov	r7, r3
+    2310:	d838      	bhi.n	2384 <__ssputs_r+0x84>
+    2312:	898a      	ldrh	r2, [r1, #12]
+    2314:	f412 6f90 	tst.w	r2, #1152	; 0x480
+    2318:	d032      	beq.n	2380 <__ssputs_r+0x80>
+    231a:	6825      	ldr	r5, [r4, #0]
+    231c:	6909      	ldr	r1, [r1, #16]
+    231e:	eba5 0901 	sub.w	r9, r5, r1
+    2322:	6965      	ldr	r5, [r4, #20]
+    2324:	eb05 0545 	add.w	r5, r5, r5, lsl #1
+    2328:	eb05 75d5 	add.w	r5, r5, r5, lsr #31
+    232c:	3301      	adds	r3, #1
+    232e:	444b      	add	r3, r9
+    2330:	106d      	asrs	r5, r5, #1
+    2332:	429d      	cmp	r5, r3
+    2334:	bf38      	it	cc
+    2336:	461d      	movcc	r5, r3
+    2338:	0553      	lsls	r3, r2, #21
+    233a:	d531      	bpl.n	23a0 <__ssputs_r+0xa0>
+    233c:	4629      	mov	r1, r5
+    233e:	f7ff ff85 	bl	224c <_malloc_r>
+    2342:	4606      	mov	r6, r0
+    2344:	b950      	cbnz	r0, 235c <__ssputs_r+0x5c>
+    2346:	230c      	movs	r3, #12
+    2348:	f8ca 3000 	str.w	r3, [sl]
+    234c:	89a3      	ldrh	r3, [r4, #12]
+    234e:	f043 0340 	orr.w	r3, r3, #64	; 0x40
+    2352:	81a3      	strh	r3, [r4, #12]
+    2354:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
+    2358:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
+    235c:	6921      	ldr	r1, [r4, #16]
+    235e:	464a      	mov	r2, r9
+    2360:	f7ff ff34 	bl	21cc <memcpy>
+    2364:	89a3      	ldrh	r3, [r4, #12]
+    2366:	f423 6390 	bic.w	r3, r3, #1152	; 0x480
+    236a:	f043 0380 	orr.w	r3, r3, #128	; 0x80
+    236e:	81a3      	strh	r3, [r4, #12]
+    2370:	6126      	str	r6, [r4, #16]
+    2372:	6165      	str	r5, [r4, #20]
+    2374:	444e      	add	r6, r9
+    2376:	eba5 0509 	sub.w	r5, r5, r9
+    237a:	6026      	str	r6, [r4, #0]
+    237c:	60a5      	str	r5, [r4, #8]
+    237e:	463e      	mov	r6, r7
+    2380:	42be      	cmp	r6, r7
+    2382:	d900      	bls.n	2386 <__ssputs_r+0x86>
+    2384:	463e      	mov	r6, r7
+    2386:	4632      	mov	r2, r6
+    2388:	6820      	ldr	r0, [r4, #0]
+    238a:	4641      	mov	r1, r8
+    238c:	f000 fb08 	bl	29a0 <memmove>
+    2390:	68a3      	ldr	r3, [r4, #8]
+    2392:	6822      	ldr	r2, [r4, #0]
+    2394:	1b9b      	subs	r3, r3, r6
+    2396:	4432      	add	r2, r6
+    2398:	60a3      	str	r3, [r4, #8]
+    239a:	6022      	str	r2, [r4, #0]
+    239c:	2000      	movs	r0, #0
+    239e:	e7db      	b.n	2358 <__ssputs_r+0x58>
+    23a0:	462a      	mov	r2, r5
+    23a2:	f000 fb71 	bl	2a88 <_realloc_r>
+    23a6:	4606      	mov	r6, r0
+    23a8:	2800      	cmp	r0, #0
+    23aa:	d1e1      	bne.n	2370 <__ssputs_r+0x70>
+    23ac:	6921      	ldr	r1, [r4, #16]
+    23ae:	4650      	mov	r0, sl
+    23b0:	f000 fb1c 	bl	29ec <_free_r>
+    23b4:	e7c7      	b.n	2346 <__ssputs_r+0x46>
+	...
+
+000023b8 <_svfiprintf_r>:
+    23b8:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
+    23bc:	4698      	mov	r8, r3
+    23be:	898b      	ldrh	r3, [r1, #12]
+    23c0:	061b      	lsls	r3, r3, #24
+    23c2:	b09d      	sub	sp, #116	; 0x74
+    23c4:	4607      	mov	r7, r0
+    23c6:	460d      	mov	r5, r1
+    23c8:	4614      	mov	r4, r2
+    23ca:	d50e      	bpl.n	23ea <_svfiprintf_r+0x32>
+    23cc:	690b      	ldr	r3, [r1, #16]
+    23ce:	b963      	cbnz	r3, 23ea <_svfiprintf_r+0x32>
+    23d0:	2140      	movs	r1, #64	; 0x40
+    23d2:	f7ff ff3b 	bl	224c <_malloc_r>
+    23d6:	6028      	str	r0, [r5, #0]
+    23d8:	6128      	str	r0, [r5, #16]
+    23da:	b920      	cbnz	r0, 23e6 <_svfiprintf_r+0x2e>
+    23dc:	230c      	movs	r3, #12
+    23de:	603b      	str	r3, [r7, #0]
+    23e0:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
+    23e4:	e0d1      	b.n	258a <_svfiprintf_r+0x1d2>
+    23e6:	2340      	movs	r3, #64	; 0x40
+    23e8:	616b      	str	r3, [r5, #20]
+    23ea:	2300      	movs	r3, #0
+    23ec:	9309      	str	r3, [sp, #36]	; 0x24
+    23ee:	2320      	movs	r3, #32
+    23f0:	f88d 3029 	strb.w	r3, [sp, #41]	; 0x29
+    23f4:	f8cd 800c 	str.w	r8, [sp, #12]
+    23f8:	2330      	movs	r3, #48	; 0x30
+    23fa:	f8df 81a8 	ldr.w	r8, [pc, #424]	; 25a4 <_svfiprintf_r+0x1ec>
+    23fe:	f88d 302a 	strb.w	r3, [sp, #42]	; 0x2a
+    2402:	f04f 0901 	mov.w	r9, #1
+    2406:	4623      	mov	r3, r4
+    2408:	469a      	mov	sl, r3
+    240a:	f813 2b01 	ldrb.w	r2, [r3], #1
+    240e:	b10a      	cbz	r2, 2414 <_svfiprintf_r+0x5c>
+    2410:	2a25      	cmp	r2, #37	; 0x25
+    2412:	d1f9      	bne.n	2408 <_svfiprintf_r+0x50>
+    2414:	ebba 0b04 	subs.w	fp, sl, r4
+    2418:	d00b      	beq.n	2432 <_svfiprintf_r+0x7a>
+    241a:	465b      	mov	r3, fp
+    241c:	4622      	mov	r2, r4
+    241e:	4629      	mov	r1, r5
+    2420:	4638      	mov	r0, r7
+    2422:	f7ff ff6d 	bl	2300 <__ssputs_r>
+    2426:	3001      	adds	r0, #1
+    2428:	f000 80aa 	beq.w	2580 <_svfiprintf_r+0x1c8>
+    242c:	9a09      	ldr	r2, [sp, #36]	; 0x24
+    242e:	445a      	add	r2, fp
+    2430:	9209      	str	r2, [sp, #36]	; 0x24
+    2432:	f89a 3000 	ldrb.w	r3, [sl]
+    2436:	2b00      	cmp	r3, #0
+    2438:	f000 80a2 	beq.w	2580 <_svfiprintf_r+0x1c8>
+    243c:	2300      	movs	r3, #0
+    243e:	f04f 32ff 	mov.w	r2, #4294967295	; 0xffffffff
+    2442:	e9cd 2305 	strd	r2, r3, [sp, #20]
+    2446:	f10a 0a01 	add.w	sl, sl, #1
+    244a:	9304      	str	r3, [sp, #16]
+    244c:	9307      	str	r3, [sp, #28]
+    244e:	f88d 3053 	strb.w	r3, [sp, #83]	; 0x53
+    2452:	931a      	str	r3, [sp, #104]	; 0x68
+    2454:	4654      	mov	r4, sl
+    2456:	2205      	movs	r2, #5
+    2458:	f814 1b01 	ldrb.w	r1, [r4], #1
+    245c:	4851      	ldr	r0, [pc, #324]	; (25a4 <_svfiprintf_r+0x1ec>)
+    245e:	f000 fa4f 	bl	2900 <memchr>
+    2462:	9a04      	ldr	r2, [sp, #16]
+    2464:	b9d8      	cbnz	r0, 249e <_svfiprintf_r+0xe6>
+    2466:	06d0      	lsls	r0, r2, #27
+    2468:	bf44      	itt	mi
+    246a:	2320      	movmi	r3, #32
+    246c:	f88d 3053 	strbmi.w	r3, [sp, #83]	; 0x53
+    2470:	0711      	lsls	r1, r2, #28
+    2472:	bf44      	itt	mi
+    2474:	232b      	movmi	r3, #43	; 0x2b
+    2476:	f88d 3053 	strbmi.w	r3, [sp, #83]	; 0x53
+    247a:	f89a 3000 	ldrb.w	r3, [sl]
+    247e:	2b2a      	cmp	r3, #42	; 0x2a
+    2480:	d015      	beq.n	24ae <_svfiprintf_r+0xf6>
+    2482:	9a07      	ldr	r2, [sp, #28]
+    2484:	4654      	mov	r4, sl
+    2486:	2000      	movs	r0, #0
+    2488:	f04f 0c0a 	mov.w	ip, #10
+    248c:	4621      	mov	r1, r4
+    248e:	f811 3b01 	ldrb.w	r3, [r1], #1
+    2492:	3b30      	subs	r3, #48	; 0x30
+    2494:	2b09      	cmp	r3, #9
+    2496:	d94e      	bls.n	2536 <_svfiprintf_r+0x17e>
+    2498:	b1b0      	cbz	r0, 24c8 <_svfiprintf_r+0x110>
+    249a:	9207      	str	r2, [sp, #28]
+    249c:	e014      	b.n	24c8 <_svfiprintf_r+0x110>
+    249e:	eba0 0308 	sub.w	r3, r0, r8
+    24a2:	fa09 f303 	lsl.w	r3, r9, r3
+    24a6:	4313      	orrs	r3, r2
+    24a8:	9304      	str	r3, [sp, #16]
+    24aa:	46a2      	mov	sl, r4
+    24ac:	e7d2      	b.n	2454 <_svfiprintf_r+0x9c>
+    24ae:	9b03      	ldr	r3, [sp, #12]
+    24b0:	1d19      	adds	r1, r3, #4
+    24b2:	681b      	ldr	r3, [r3, #0]
+    24b4:	9103      	str	r1, [sp, #12]
+    24b6:	2b00      	cmp	r3, #0
+    24b8:	bfbb      	ittet	lt
+    24ba:	425b      	neglt	r3, r3
+    24bc:	f042 0202 	orrlt.w	r2, r2, #2
+    24c0:	9307      	strge	r3, [sp, #28]
+    24c2:	9307      	strlt	r3, [sp, #28]
+    24c4:	bfb8      	it	lt
+    24c6:	9204      	strlt	r2, [sp, #16]
+    24c8:	7823      	ldrb	r3, [r4, #0]
+    24ca:	2b2e      	cmp	r3, #46	; 0x2e
+    24cc:	d10c      	bne.n	24e8 <_svfiprintf_r+0x130>
+    24ce:	7863      	ldrb	r3, [r4, #1]
+    24d0:	2b2a      	cmp	r3, #42	; 0x2a
+    24d2:	d135      	bne.n	2540 <_svfiprintf_r+0x188>
+    24d4:	9b03      	ldr	r3, [sp, #12]
+    24d6:	1d1a      	adds	r2, r3, #4
+    24d8:	681b      	ldr	r3, [r3, #0]
+    24da:	9203      	str	r2, [sp, #12]
+    24dc:	2b00      	cmp	r3, #0
+    24de:	bfb8      	it	lt
+    24e0:	f04f 33ff 	movlt.w	r3, #4294967295	; 0xffffffff
+    24e4:	3402      	adds	r4, #2
+    24e6:	9305      	str	r3, [sp, #20]
+    24e8:	f8df a0c8 	ldr.w	sl, [pc, #200]	; 25b4 <_svfiprintf_r+0x1fc>
+    24ec:	7821      	ldrb	r1, [r4, #0]
+    24ee:	2203      	movs	r2, #3
+    24f0:	4650      	mov	r0, sl
+    24f2:	f000 fa05 	bl	2900 <memchr>
+    24f6:	b140      	cbz	r0, 250a <_svfiprintf_r+0x152>
+    24f8:	2340      	movs	r3, #64	; 0x40
+    24fa:	eba0 000a 	sub.w	r0, r0, sl
+    24fe:	fa03 f000 	lsl.w	r0, r3, r0
+    2502:	9b04      	ldr	r3, [sp, #16]
+    2504:	4303      	orrs	r3, r0
+    2506:	3401      	adds	r4, #1
+    2508:	9304      	str	r3, [sp, #16]
+    250a:	f814 1b01 	ldrb.w	r1, [r4], #1
+    250e:	4826      	ldr	r0, [pc, #152]	; (25a8 <_svfiprintf_r+0x1f0>)
+    2510:	f88d 1028 	strb.w	r1, [sp, #40]	; 0x28
+    2514:	2206      	movs	r2, #6
+    2516:	f000 f9f3 	bl	2900 <memchr>
+    251a:	2800      	cmp	r0, #0
+    251c:	d038      	beq.n	2590 <_svfiprintf_r+0x1d8>
+    251e:	4b23      	ldr	r3, [pc, #140]	; (25ac <_svfiprintf_r+0x1f4>)
+    2520:	bb1b      	cbnz	r3, 256a <_svfiprintf_r+0x1b2>
+    2522:	9b03      	ldr	r3, [sp, #12]
+    2524:	3307      	adds	r3, #7
+    2526:	f023 0307 	bic.w	r3, r3, #7
+    252a:	3308      	adds	r3, #8
+    252c:	9303      	str	r3, [sp, #12]
+    252e:	9b09      	ldr	r3, [sp, #36]	; 0x24
+    2530:	4433      	add	r3, r6
+    2532:	9309      	str	r3, [sp, #36]	; 0x24
+    2534:	e767      	b.n	2406 <_svfiprintf_r+0x4e>
+    2536:	fb0c 3202 	mla	r2, ip, r2, r3
+    253a:	460c      	mov	r4, r1
+    253c:	2001      	movs	r0, #1
+    253e:	e7a5      	b.n	248c <_svfiprintf_r+0xd4>
+    2540:	2300      	movs	r3, #0
+    2542:	3401      	adds	r4, #1
+    2544:	9305      	str	r3, [sp, #20]
+    2546:	4619      	mov	r1, r3
+    2548:	f04f 0c0a 	mov.w	ip, #10
+    254c:	4620      	mov	r0, r4
+    254e:	f810 2b01 	ldrb.w	r2, [r0], #1
+    2552:	3a30      	subs	r2, #48	; 0x30
+    2554:	2a09      	cmp	r2, #9
+    2556:	d903      	bls.n	2560 <_svfiprintf_r+0x1a8>
+    2558:	2b00      	cmp	r3, #0
+    255a:	d0c5      	beq.n	24e8 <_svfiprintf_r+0x130>
+    255c:	9105      	str	r1, [sp, #20]
+    255e:	e7c3      	b.n	24e8 <_svfiprintf_r+0x130>
+    2560:	fb0c 2101 	mla	r1, ip, r1, r2
+    2564:	4604      	mov	r4, r0
+    2566:	2301      	movs	r3, #1
+    2568:	e7f0      	b.n	254c <_svfiprintf_r+0x194>
+    256a:	ab03      	add	r3, sp, #12
+    256c:	9300      	str	r3, [sp, #0]
+    256e:	462a      	mov	r2, r5
+    2570:	4b0f      	ldr	r3, [pc, #60]	; (25b0 <_svfiprintf_r+0x1f8>)
+    2572:	a904      	add	r1, sp, #16
+    2574:	4638      	mov	r0, r7
+    2576:	f3af 8000 	nop.w
+    257a:	1c42      	adds	r2, r0, #1
+    257c:	4606      	mov	r6, r0
+    257e:	d1d6      	bne.n	252e <_svfiprintf_r+0x176>
+    2580:	89ab      	ldrh	r3, [r5, #12]
+    2582:	065b      	lsls	r3, r3, #25
+    2584:	f53f af2c 	bmi.w	23e0 <_svfiprintf_r+0x28>
+    2588:	9809      	ldr	r0, [sp, #36]	; 0x24
+    258a:	b01d      	add	sp, #116	; 0x74
+    258c:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
+    2590:	ab03      	add	r3, sp, #12
+    2592:	9300      	str	r3, [sp, #0]
+    2594:	462a      	mov	r2, r5
+    2596:	4b06      	ldr	r3, [pc, #24]	; (25b0 <_svfiprintf_r+0x1f8>)
+    2598:	a904      	add	r1, sp, #16
+    259a:	4638      	mov	r0, r7
+    259c:	f000 f87a 	bl	2694 <_printf_i>
+    25a0:	e7eb      	b.n	257a <_svfiprintf_r+0x1c2>
+    25a2:	bf00      	nop
+    25a4:	0000316c 	.word	0x0000316c
+    25a8:	00003176 	.word	0x00003176
+    25ac:	00000000 	.word	0x00000000
+    25b0:	00002301 	.word	0x00002301
+    25b4:	00003172 	.word	0x00003172
+
+000025b8 <_printf_common>:
+    25b8:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
+    25bc:	4616      	mov	r6, r2
+    25be:	4699      	mov	r9, r3
+    25c0:	688a      	ldr	r2, [r1, #8]
+    25c2:	690b      	ldr	r3, [r1, #16]
+    25c4:	f8dd 8020 	ldr.w	r8, [sp, #32]
+    25c8:	4293      	cmp	r3, r2
+    25ca:	bfb8      	it	lt
+    25cc:	4613      	movlt	r3, r2
+    25ce:	6033      	str	r3, [r6, #0]
+    25d0:	f891 2043 	ldrb.w	r2, [r1, #67]	; 0x43
+    25d4:	4607      	mov	r7, r0
+    25d6:	460c      	mov	r4, r1
+    25d8:	b10a      	cbz	r2, 25de <_printf_common+0x26>
+    25da:	3301      	adds	r3, #1
+    25dc:	6033      	str	r3, [r6, #0]
+    25de:	6823      	ldr	r3, [r4, #0]
+    25e0:	0699      	lsls	r1, r3, #26
+    25e2:	bf42      	ittt	mi
+    25e4:	6833      	ldrmi	r3, [r6, #0]
+    25e6:	3302      	addmi	r3, #2
+    25e8:	6033      	strmi	r3, [r6, #0]
+    25ea:	6825      	ldr	r5, [r4, #0]
+    25ec:	f015 0506 	ands.w	r5, r5, #6
+    25f0:	d106      	bne.n	2600 <_printf_common+0x48>
+    25f2:	f104 0a19 	add.w	sl, r4, #25
+    25f6:	68e3      	ldr	r3, [r4, #12]
+    25f8:	6832      	ldr	r2, [r6, #0]
+    25fa:	1a9b      	subs	r3, r3, r2
+    25fc:	42ab      	cmp	r3, r5
+    25fe:	dc26      	bgt.n	264e <_printf_common+0x96>
+    2600:	f894 2043 	ldrb.w	r2, [r4, #67]	; 0x43
+    2604:	1e13      	subs	r3, r2, #0
+    2606:	6822      	ldr	r2, [r4, #0]
+    2608:	bf18      	it	ne
+    260a:	2301      	movne	r3, #1
+    260c:	0692      	lsls	r2, r2, #26
+    260e:	d42b      	bmi.n	2668 <_printf_common+0xb0>
+    2610:	f104 0243 	add.w	r2, r4, #67	; 0x43
+    2614:	4649      	mov	r1, r9
+    2616:	4638      	mov	r0, r7
+    2618:	47c0      	blx	r8
+    261a:	3001      	adds	r0, #1
+    261c:	d01e      	beq.n	265c <_printf_common+0xa4>
+    261e:	6823      	ldr	r3, [r4, #0]
+    2620:	68e5      	ldr	r5, [r4, #12]
+    2622:	6832      	ldr	r2, [r6, #0]
+    2624:	f003 0306 	and.w	r3, r3, #6
+    2628:	2b04      	cmp	r3, #4
+    262a:	bf08      	it	eq
+    262c:	1aad      	subeq	r5, r5, r2
+    262e:	68a3      	ldr	r3, [r4, #8]
+    2630:	6922      	ldr	r2, [r4, #16]
+    2632:	bf0c      	ite	eq
+    2634:	ea25 75e5 	biceq.w	r5, r5, r5, asr #31
+    2638:	2500      	movne	r5, #0
+    263a:	4293      	cmp	r3, r2
+    263c:	bfc4      	itt	gt
+    263e:	1a9b      	subgt	r3, r3, r2
+    2640:	18ed      	addgt	r5, r5, r3
+    2642:	2600      	movs	r6, #0
+    2644:	341a      	adds	r4, #26
+    2646:	42b5      	cmp	r5, r6
+    2648:	d11a      	bne.n	2680 <_printf_common+0xc8>
+    264a:	2000      	movs	r0, #0
+    264c:	e008      	b.n	2660 <_printf_common+0xa8>
+    264e:	2301      	movs	r3, #1
+    2650:	4652      	mov	r2, sl
+    2652:	4649      	mov	r1, r9
+    2654:	4638      	mov	r0, r7
+    2656:	47c0      	blx	r8
+    2658:	3001      	adds	r0, #1
+    265a:	d103      	bne.n	2664 <_printf_common+0xac>
+    265c:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
+    2660:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
+    2664:	3501      	adds	r5, #1
+    2666:	e7c6      	b.n	25f6 <_printf_common+0x3e>
+    2668:	18e1      	adds	r1, r4, r3
+    266a:	1c5a      	adds	r2, r3, #1
+    266c:	2030      	movs	r0, #48	; 0x30
+    266e:	f881 0043 	strb.w	r0, [r1, #67]	; 0x43
+    2672:	4422      	add	r2, r4
+    2674:	f894 1045 	ldrb.w	r1, [r4, #69]	; 0x45
+    2678:	f882 1043 	strb.w	r1, [r2, #67]	; 0x43
+    267c:	3302      	adds	r3, #2
+    267e:	e7c7      	b.n	2610 <_printf_common+0x58>
+    2680:	2301      	movs	r3, #1
+    2682:	4622      	mov	r2, r4
+    2684:	4649      	mov	r1, r9
+    2686:	4638      	mov	r0, r7
+    2688:	47c0      	blx	r8
+    268a:	3001      	adds	r0, #1
+    268c:	d0e6      	beq.n	265c <_printf_common+0xa4>
+    268e:	3601      	adds	r6, #1
+    2690:	e7d9      	b.n	2646 <_printf_common+0x8e>
+	...
+
+00002694 <_printf_i>:
+    2694:	e92d 47ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
+    2698:	460c      	mov	r4, r1
+    269a:	4691      	mov	r9, r2
+    269c:	7e27      	ldrb	r7, [r4, #24]
+    269e:	990c      	ldr	r1, [sp, #48]	; 0x30
+    26a0:	2f78      	cmp	r7, #120	; 0x78
+    26a2:	4680      	mov	r8, r0
+    26a4:	469a      	mov	sl, r3
+    26a6:	f104 0243 	add.w	r2, r4, #67	; 0x43
+    26aa:	d807      	bhi.n	26bc <_printf_i+0x28>
+    26ac:	2f62      	cmp	r7, #98	; 0x62
+    26ae:	d80a      	bhi.n	26c6 <_printf_i+0x32>
+    26b0:	2f00      	cmp	r7, #0
+    26b2:	f000 80d8 	beq.w	2866 <_printf_i+0x1d2>
+    26b6:	2f58      	cmp	r7, #88	; 0x58
+    26b8:	f000 80a3 	beq.w	2802 <_printf_i+0x16e>
+    26bc:	f104 0642 	add.w	r6, r4, #66	; 0x42
+    26c0:	f884 7042 	strb.w	r7, [r4, #66]	; 0x42
+    26c4:	e03a      	b.n	273c <_printf_i+0xa8>
+    26c6:	f1a7 0363 	sub.w	r3, r7, #99	; 0x63
+    26ca:	2b15      	cmp	r3, #21
+    26cc:	d8f6      	bhi.n	26bc <_printf_i+0x28>
+    26ce:	a001      	add	r0, pc, #4	; (adr r0, 26d4 <_printf_i+0x40>)
+    26d0:	f850 f023 	ldr.w	pc, [r0, r3, lsl #2]
+    26d4:	0000272d 	.word	0x0000272d
+    26d8:	00002741 	.word	0x00002741
+    26dc:	000026bd 	.word	0x000026bd
+    26e0:	000026bd 	.word	0x000026bd
+    26e4:	000026bd 	.word	0x000026bd
+    26e8:	000026bd 	.word	0x000026bd
+    26ec:	00002741 	.word	0x00002741
+    26f0:	000026bd 	.word	0x000026bd
+    26f4:	000026bd 	.word	0x000026bd
+    26f8:	000026bd 	.word	0x000026bd
+    26fc:	000026bd 	.word	0x000026bd
+    2700:	0000284d 	.word	0x0000284d
+    2704:	00002771 	.word	0x00002771
+    2708:	0000282f 	.word	0x0000282f
+    270c:	000026bd 	.word	0x000026bd
+    2710:	000026bd 	.word	0x000026bd
+    2714:	0000286f 	.word	0x0000286f
+    2718:	000026bd 	.word	0x000026bd
+    271c:	00002771 	.word	0x00002771
+    2720:	000026bd 	.word	0x000026bd
+    2724:	000026bd 	.word	0x000026bd
+    2728:	00002837 	.word	0x00002837
+    272c:	680b      	ldr	r3, [r1, #0]
+    272e:	1d1a      	adds	r2, r3, #4
+    2730:	681b      	ldr	r3, [r3, #0]
+    2732:	600a      	str	r2, [r1, #0]
+    2734:	f104 0642 	add.w	r6, r4, #66	; 0x42
+    2738:	f884 3042 	strb.w	r3, [r4, #66]	; 0x42
+    273c:	2301      	movs	r3, #1
+    273e:	e0a3      	b.n	2888 <_printf_i+0x1f4>
+    2740:	6825      	ldr	r5, [r4, #0]
+    2742:	6808      	ldr	r0, [r1, #0]
+    2744:	062e      	lsls	r6, r5, #24
+    2746:	f100 0304 	add.w	r3, r0, #4
+    274a:	d50a      	bpl.n	2762 <_printf_i+0xce>
+    274c:	6805      	ldr	r5, [r0, #0]
+    274e:	600b      	str	r3, [r1, #0]
+    2750:	2d00      	cmp	r5, #0
+    2752:	da03      	bge.n	275c <_printf_i+0xc8>
+    2754:	232d      	movs	r3, #45	; 0x2d
+    2756:	426d      	negs	r5, r5
+    2758:	f884 3043 	strb.w	r3, [r4, #67]	; 0x43
+    275c:	485e      	ldr	r0, [pc, #376]	; (28d8 <_printf_i+0x244>)
+    275e:	230a      	movs	r3, #10
+    2760:	e019      	b.n	2796 <_printf_i+0x102>
+    2762:	f015 0f40 	tst.w	r5, #64	; 0x40
+    2766:	6805      	ldr	r5, [r0, #0]
+    2768:	600b      	str	r3, [r1, #0]
+    276a:	bf18      	it	ne
+    276c:	b22d      	sxthne	r5, r5
+    276e:	e7ef      	b.n	2750 <_printf_i+0xbc>
+    2770:	680b      	ldr	r3, [r1, #0]
+    2772:	6825      	ldr	r5, [r4, #0]
+    2774:	1d18      	adds	r0, r3, #4
+    2776:	6008      	str	r0, [r1, #0]
+    2778:	0628      	lsls	r0, r5, #24
+    277a:	d501      	bpl.n	2780 <_printf_i+0xec>
+    277c:	681d      	ldr	r5, [r3, #0]
+    277e:	e002      	b.n	2786 <_printf_i+0xf2>
+    2780:	0669      	lsls	r1, r5, #25
+    2782:	d5fb      	bpl.n	277c <_printf_i+0xe8>
+    2784:	881d      	ldrh	r5, [r3, #0]
+    2786:	4854      	ldr	r0, [pc, #336]	; (28d8 <_printf_i+0x244>)
+    2788:	2f6f      	cmp	r7, #111	; 0x6f
+    278a:	bf0c      	ite	eq
+    278c:	2308      	moveq	r3, #8
+    278e:	230a      	movne	r3, #10
+    2790:	2100      	movs	r1, #0
+    2792:	f884 1043 	strb.w	r1, [r4, #67]	; 0x43
+    2796:	6866      	ldr	r6, [r4, #4]
+    2798:	60a6      	str	r6, [r4, #8]
+    279a:	2e00      	cmp	r6, #0
+    279c:	bfa2      	ittt	ge
+    279e:	6821      	ldrge	r1, [r4, #0]
+    27a0:	f021 0104 	bicge.w	r1, r1, #4
+    27a4:	6021      	strge	r1, [r4, #0]
+    27a6:	b90d      	cbnz	r5, 27ac <_printf_i+0x118>
+    27a8:	2e00      	cmp	r6, #0
+    27aa:	d04d      	beq.n	2848 <_printf_i+0x1b4>
+    27ac:	4616      	mov	r6, r2
+    27ae:	fbb5 f1f3 	udiv	r1, r5, r3
+    27b2:	fb03 5711 	mls	r7, r3, r1, r5
+    27b6:	5dc7      	ldrb	r7, [r0, r7]
+    27b8:	f806 7d01 	strb.w	r7, [r6, #-1]!
+    27bc:	462f      	mov	r7, r5
+    27be:	42bb      	cmp	r3, r7
+    27c0:	460d      	mov	r5, r1
+    27c2:	d9f4      	bls.n	27ae <_printf_i+0x11a>
+    27c4:	2b08      	cmp	r3, #8
+    27c6:	d10b      	bne.n	27e0 <_printf_i+0x14c>
+    27c8:	6823      	ldr	r3, [r4, #0]
+    27ca:	07df      	lsls	r7, r3, #31
+    27cc:	d508      	bpl.n	27e0 <_printf_i+0x14c>
+    27ce:	6923      	ldr	r3, [r4, #16]
+    27d0:	6861      	ldr	r1, [r4, #4]
+    27d2:	4299      	cmp	r1, r3
+    27d4:	bfde      	ittt	le
+    27d6:	2330      	movle	r3, #48	; 0x30
+    27d8:	f806 3c01 	strble.w	r3, [r6, #-1]
+    27dc:	f106 36ff 	addle.w	r6, r6, #4294967295	; 0xffffffff
+    27e0:	1b92      	subs	r2, r2, r6
+    27e2:	6122      	str	r2, [r4, #16]
+    27e4:	f8cd a000 	str.w	sl, [sp]
+    27e8:	464b      	mov	r3, r9
+    27ea:	aa03      	add	r2, sp, #12
+    27ec:	4621      	mov	r1, r4
+    27ee:	4640      	mov	r0, r8
+    27f0:	f7ff fee2 	bl	25b8 <_printf_common>
+    27f4:	3001      	adds	r0, #1
+    27f6:	d14c      	bne.n	2892 <_printf_i+0x1fe>
+    27f8:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
+    27fc:	b004      	add	sp, #16
+    27fe:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
+    2802:	4835      	ldr	r0, [pc, #212]	; (28d8 <_printf_i+0x244>)
+    2804:	f884 7045 	strb.w	r7, [r4, #69]	; 0x45
+    2808:	6823      	ldr	r3, [r4, #0]
+    280a:	680e      	ldr	r6, [r1, #0]
+    280c:	061f      	lsls	r7, r3, #24
+    280e:	f856 5b04 	ldr.w	r5, [r6], #4
+    2812:	600e      	str	r6, [r1, #0]
+    2814:	d514      	bpl.n	2840 <_printf_i+0x1ac>
+    2816:	07d9      	lsls	r1, r3, #31
+    2818:	bf44      	itt	mi
+    281a:	f043 0320 	orrmi.w	r3, r3, #32
+    281e:	6023      	strmi	r3, [r4, #0]
+    2820:	b91d      	cbnz	r5, 282a <_printf_i+0x196>
+    2822:	6823      	ldr	r3, [r4, #0]
+    2824:	f023 0320 	bic.w	r3, r3, #32
+    2828:	6023      	str	r3, [r4, #0]
+    282a:	2310      	movs	r3, #16
+    282c:	e7b0      	b.n	2790 <_printf_i+0xfc>
+    282e:	6823      	ldr	r3, [r4, #0]
+    2830:	f043 0320 	orr.w	r3, r3, #32
+    2834:	6023      	str	r3, [r4, #0]
+    2836:	2378      	movs	r3, #120	; 0x78
+    2838:	4828      	ldr	r0, [pc, #160]	; (28dc <_printf_i+0x248>)
+    283a:	f884 3045 	strb.w	r3, [r4, #69]	; 0x45
+    283e:	e7e3      	b.n	2808 <_printf_i+0x174>
+    2840:	065e      	lsls	r6, r3, #25
+    2842:	bf48      	it	mi
+    2844:	b2ad      	uxthmi	r5, r5
+    2846:	e7e6      	b.n	2816 <_printf_i+0x182>
+    2848:	4616      	mov	r6, r2
+    284a:	e7bb      	b.n	27c4 <_printf_i+0x130>
+    284c:	680b      	ldr	r3, [r1, #0]
+    284e:	6826      	ldr	r6, [r4, #0]
+    2850:	6960      	ldr	r0, [r4, #20]
+    2852:	1d1d      	adds	r5, r3, #4
+    2854:	600d      	str	r5, [r1, #0]
+    2856:	0635      	lsls	r5, r6, #24
+    2858:	681b      	ldr	r3, [r3, #0]
+    285a:	d501      	bpl.n	2860 <_printf_i+0x1cc>
+    285c:	6018      	str	r0, [r3, #0]
+    285e:	e002      	b.n	2866 <_printf_i+0x1d2>
+    2860:	0671      	lsls	r1, r6, #25
+    2862:	d5fb      	bpl.n	285c <_printf_i+0x1c8>
+    2864:	8018      	strh	r0, [r3, #0]
+    2866:	2300      	movs	r3, #0
+    2868:	6123      	str	r3, [r4, #16]
+    286a:	4616      	mov	r6, r2
+    286c:	e7ba      	b.n	27e4 <_printf_i+0x150>
+    286e:	680b      	ldr	r3, [r1, #0]
+    2870:	1d1a      	adds	r2, r3, #4
+    2872:	600a      	str	r2, [r1, #0]
+    2874:	681e      	ldr	r6, [r3, #0]
+    2876:	6862      	ldr	r2, [r4, #4]
+    2878:	2100      	movs	r1, #0
+    287a:	4630      	mov	r0, r6
+    287c:	f000 f840 	bl	2900 <memchr>
+    2880:	b108      	cbz	r0, 2886 <_printf_i+0x1f2>
+    2882:	1b80      	subs	r0, r0, r6
+    2884:	6060      	str	r0, [r4, #4]
+    2886:	6863      	ldr	r3, [r4, #4]
+    2888:	6123      	str	r3, [r4, #16]
+    288a:	2300      	movs	r3, #0
+    288c:	f884 3043 	strb.w	r3, [r4, #67]	; 0x43
+    2890:	e7a8      	b.n	27e4 <_printf_i+0x150>
+    2892:	6923      	ldr	r3, [r4, #16]
+    2894:	4632      	mov	r2, r6
+    2896:	4649      	mov	r1, r9
+    2898:	4640      	mov	r0, r8
+    289a:	47d0      	blx	sl
+    289c:	3001      	adds	r0, #1
+    289e:	d0ab      	beq.n	27f8 <_printf_i+0x164>
+    28a0:	6823      	ldr	r3, [r4, #0]
+    28a2:	079b      	lsls	r3, r3, #30
+    28a4:	d413      	bmi.n	28ce <_printf_i+0x23a>
+    28a6:	68e0      	ldr	r0, [r4, #12]
+    28a8:	9b03      	ldr	r3, [sp, #12]
+    28aa:	4298      	cmp	r0, r3
+    28ac:	bfb8      	it	lt
+    28ae:	4618      	movlt	r0, r3
+    28b0:	e7a4      	b.n	27fc <_printf_i+0x168>
+    28b2:	2301      	movs	r3, #1
+    28b4:	4632      	mov	r2, r6
+    28b6:	4649      	mov	r1, r9
+    28b8:	4640      	mov	r0, r8
+    28ba:	47d0      	blx	sl
+    28bc:	3001      	adds	r0, #1
+    28be:	d09b      	beq.n	27f8 <_printf_i+0x164>
+    28c0:	3501      	adds	r5, #1
+    28c2:	68e3      	ldr	r3, [r4, #12]
+    28c4:	9903      	ldr	r1, [sp, #12]
+    28c6:	1a5b      	subs	r3, r3, r1
+    28c8:	42ab      	cmp	r3, r5
+    28ca:	dcf2      	bgt.n	28b2 <_printf_i+0x21e>
+    28cc:	e7eb      	b.n	28a6 <_printf_i+0x212>
+    28ce:	2500      	movs	r5, #0
+    28d0:	f104 0619 	add.w	r6, r4, #25
+    28d4:	e7f5      	b.n	28c2 <_printf_i+0x22e>
+    28d6:	bf00      	nop
+    28d8:	0000317d 	.word	0x0000317d
+    28dc:	0000318e 	.word	0x0000318e
+
+000028e0 <_sbrk_r>:
+    28e0:	b538      	push	{r3, r4, r5, lr}
+    28e2:	4d06      	ldr	r5, [pc, #24]	; (28fc <_sbrk_r+0x1c>)
+    28e4:	2300      	movs	r3, #0
+    28e6:	4604      	mov	r4, r0
+    28e8:	4608      	mov	r0, r1
+    28ea:	602b      	str	r3, [r5, #0]
+    28ec:	f7fd fd76 	bl	3dc <_sbrk>
+    28f0:	1c43      	adds	r3, r0, #1
+    28f2:	d102      	bne.n	28fa <_sbrk_r+0x1a>
+    28f4:	682b      	ldr	r3, [r5, #0]
+    28f6:	b103      	cbz	r3, 28fa <_sbrk_r+0x1a>
+    28f8:	6023      	str	r3, [r4, #0]
+    28fa:	bd38      	pop	{r3, r4, r5, pc}
+    28fc:	20000368 	.word	0x20000368
+
+00002900 <memchr>:
+    2900:	f001 01ff 	and.w	r1, r1, #255	; 0xff
+    2904:	2a10      	cmp	r2, #16
+    2906:	db2b      	blt.n	2960 <memchr+0x60>
+    2908:	f010 0f07 	tst.w	r0, #7
+    290c:	d008      	beq.n	2920 <memchr+0x20>
+    290e:	f810 3b01 	ldrb.w	r3, [r0], #1
+    2912:	3a01      	subs	r2, #1
+    2914:	428b      	cmp	r3, r1
+    2916:	d02d      	beq.n	2974 <memchr+0x74>
+    2918:	f010 0f07 	tst.w	r0, #7
+    291c:	b342      	cbz	r2, 2970 <memchr+0x70>
+    291e:	d1f6      	bne.n	290e <memchr+0xe>
+    2920:	b4f0      	push	{r4, r5, r6, r7}
+    2922:	ea41 2101 	orr.w	r1, r1, r1, lsl #8
+    2926:	ea41 4101 	orr.w	r1, r1, r1, lsl #16
+    292a:	f022 0407 	bic.w	r4, r2, #7
+    292e:	f07f 0700 	mvns.w	r7, #0
+    2932:	2300      	movs	r3, #0
+    2934:	e8f0 5602 	ldrd	r5, r6, [r0], #8
+    2938:	3c08      	subs	r4, #8
+    293a:	ea85 0501 	eor.w	r5, r5, r1
+    293e:	ea86 0601 	eor.w	r6, r6, r1
+    2942:	fa85 f547 	uadd8	r5, r5, r7
+    2946:	faa3 f587 	sel	r5, r3, r7
+    294a:	fa86 f647 	uadd8	r6, r6, r7
+    294e:	faa5 f687 	sel	r6, r5, r7
+    2952:	b98e      	cbnz	r6, 2978 <memchr+0x78>
+    2954:	d1ee      	bne.n	2934 <memchr+0x34>
+    2956:	bcf0      	pop	{r4, r5, r6, r7}
+    2958:	f001 01ff 	and.w	r1, r1, #255	; 0xff
+    295c:	f002 0207 	and.w	r2, r2, #7
+    2960:	b132      	cbz	r2, 2970 <memchr+0x70>
+    2962:	f810 3b01 	ldrb.w	r3, [r0], #1
+    2966:	3a01      	subs	r2, #1
+    2968:	ea83 0301 	eor.w	r3, r3, r1
+    296c:	b113      	cbz	r3, 2974 <memchr+0x74>
+    296e:	d1f8      	bne.n	2962 <memchr+0x62>
+    2970:	2000      	movs	r0, #0
+    2972:	4770      	bx	lr
+    2974:	3801      	subs	r0, #1
+    2976:	4770      	bx	lr
+    2978:	2d00      	cmp	r5, #0
+    297a:	bf06      	itte	eq
+    297c:	4635      	moveq	r5, r6
+    297e:	3803      	subeq	r0, #3
+    2980:	3807      	subne	r0, #7
+    2982:	f015 0f01 	tst.w	r5, #1
+    2986:	d107      	bne.n	2998 <memchr+0x98>
+    2988:	3001      	adds	r0, #1
+    298a:	f415 7f80 	tst.w	r5, #256	; 0x100
+    298e:	bf02      	ittt	eq
+    2990:	3001      	addeq	r0, #1
+    2992:	f415 3fc0 	tsteq.w	r5, #98304	; 0x18000
+    2996:	3001      	addeq	r0, #1
+    2998:	bcf0      	pop	{r4, r5, r6, r7}
+    299a:	3801      	subs	r0, #1
+    299c:	4770      	bx	lr
+    299e:	bf00      	nop
+
+000029a0 <memmove>:
+    29a0:	4288      	cmp	r0, r1
+    29a2:	b510      	push	{r4, lr}
+    29a4:	eb01 0402 	add.w	r4, r1, r2
+    29a8:	d902      	bls.n	29b0 <memmove+0x10>
+    29aa:	4284      	cmp	r4, r0
+    29ac:	4623      	mov	r3, r4
+    29ae:	d807      	bhi.n	29c0 <memmove+0x20>
+    29b0:	1e43      	subs	r3, r0, #1
+    29b2:	42a1      	cmp	r1, r4
+    29b4:	d008      	beq.n	29c8 <memmove+0x28>
+    29b6:	f811 2b01 	ldrb.w	r2, [r1], #1
+    29ba:	f803 2f01 	strb.w	r2, [r3, #1]!
+    29be:	e7f8      	b.n	29b2 <memmove+0x12>
+    29c0:	4402      	add	r2, r0
+    29c2:	4601      	mov	r1, r0
+    29c4:	428a      	cmp	r2, r1
+    29c6:	d100      	bne.n	29ca <memmove+0x2a>
+    29c8:	bd10      	pop	{r4, pc}
+    29ca:	f813 4d01 	ldrb.w	r4, [r3, #-1]!
+    29ce:	f802 4d01 	strb.w	r4, [r2, #-1]!
+    29d2:	e7f7      	b.n	29c4 <memmove+0x24>
+
+000029d4 <__malloc_lock>:
+    29d4:	4801      	ldr	r0, [pc, #4]	; (29dc <__malloc_lock+0x8>)
+    29d6:	f7ff bc37 	b.w	2248 <__retarget_lock_acquire_recursive>
+    29da:	bf00      	nop
+    29dc:	20000360 	.word	0x20000360
+
+000029e0 <__malloc_unlock>:
+    29e0:	4801      	ldr	r0, [pc, #4]	; (29e8 <__malloc_unlock+0x8>)
+    29e2:	f7ff bc32 	b.w	224a <__retarget_lock_release_recursive>
+    29e6:	bf00      	nop
+    29e8:	20000360 	.word	0x20000360
+
+000029ec <_free_r>:
+    29ec:	b538      	push	{r3, r4, r5, lr}
+    29ee:	4605      	mov	r5, r0
+    29f0:	2900      	cmp	r1, #0
+    29f2:	d045      	beq.n	2a80 <_free_r+0x94>
+    29f4:	f851 3c04 	ldr.w	r3, [r1, #-4]
+    29f8:	1f0c      	subs	r4, r1, #4
+    29fa:	2b00      	cmp	r3, #0
+    29fc:	bfb8      	it	lt
+    29fe:	18e4      	addlt	r4, r4, r3
+    2a00:	f7ff ffe8 	bl	29d4 <__malloc_lock>
+    2a04:	4a1f      	ldr	r2, [pc, #124]	; (2a84 <_free_r+0x98>)
+    2a06:	6813      	ldr	r3, [r2, #0]
+    2a08:	4610      	mov	r0, r2
+    2a0a:	b933      	cbnz	r3, 2a1a <_free_r+0x2e>
+    2a0c:	6063      	str	r3, [r4, #4]
+    2a0e:	6014      	str	r4, [r2, #0]
+    2a10:	4628      	mov	r0, r5
+    2a12:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
+    2a16:	f7ff bfe3 	b.w	29e0 <__malloc_unlock>
+    2a1a:	42a3      	cmp	r3, r4
+    2a1c:	d90b      	bls.n	2a36 <_free_r+0x4a>
+    2a1e:	6821      	ldr	r1, [r4, #0]
+    2a20:	1862      	adds	r2, r4, r1
+    2a22:	4293      	cmp	r3, r2
+    2a24:	bf04      	itt	eq
+    2a26:	681a      	ldreq	r2, [r3, #0]
+    2a28:	685b      	ldreq	r3, [r3, #4]
+    2a2a:	6063      	str	r3, [r4, #4]
+    2a2c:	bf04      	itt	eq
+    2a2e:	1852      	addeq	r2, r2, r1
+    2a30:	6022      	streq	r2, [r4, #0]
+    2a32:	6004      	str	r4, [r0, #0]
+    2a34:	e7ec      	b.n	2a10 <_free_r+0x24>
+    2a36:	461a      	mov	r2, r3
+    2a38:	685b      	ldr	r3, [r3, #4]
+    2a3a:	b10b      	cbz	r3, 2a40 <_free_r+0x54>
+    2a3c:	42a3      	cmp	r3, r4
+    2a3e:	d9fa      	bls.n	2a36 <_free_r+0x4a>
+    2a40:	6811      	ldr	r1, [r2, #0]
+    2a42:	1850      	adds	r0, r2, r1
+    2a44:	42a0      	cmp	r0, r4
+    2a46:	d10b      	bne.n	2a60 <_free_r+0x74>
+    2a48:	6820      	ldr	r0, [r4, #0]
+    2a4a:	4401      	add	r1, r0
+    2a4c:	1850      	adds	r0, r2, r1
+    2a4e:	4283      	cmp	r3, r0
+    2a50:	6011      	str	r1, [r2, #0]
+    2a52:	d1dd      	bne.n	2a10 <_free_r+0x24>
+    2a54:	6818      	ldr	r0, [r3, #0]
+    2a56:	685b      	ldr	r3, [r3, #4]
+    2a58:	6053      	str	r3, [r2, #4]
+    2a5a:	4401      	add	r1, r0
+    2a5c:	6011      	str	r1, [r2, #0]
+    2a5e:	e7d7      	b.n	2a10 <_free_r+0x24>
+    2a60:	d902      	bls.n	2a68 <_free_r+0x7c>
+    2a62:	230c      	movs	r3, #12
+    2a64:	602b      	str	r3, [r5, #0]
+    2a66:	e7d3      	b.n	2a10 <_free_r+0x24>
+    2a68:	6820      	ldr	r0, [r4, #0]
+    2a6a:	1821      	adds	r1, r4, r0
+    2a6c:	428b      	cmp	r3, r1
+    2a6e:	bf04      	itt	eq
+    2a70:	6819      	ldreq	r1, [r3, #0]
+    2a72:	685b      	ldreq	r3, [r3, #4]
+    2a74:	6063      	str	r3, [r4, #4]
+    2a76:	bf04      	itt	eq
+    2a78:	1809      	addeq	r1, r1, r0
+    2a7a:	6021      	streq	r1, [r4, #0]
+    2a7c:	6054      	str	r4, [r2, #4]
+    2a7e:	e7c7      	b.n	2a10 <_free_r+0x24>
+    2a80:	bd38      	pop	{r3, r4, r5, pc}
+    2a82:	bf00      	nop
+    2a84:	20000354 	.word	0x20000354
+
+00002a88 <_realloc_r>:
+    2a88:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+    2a8a:	4607      	mov	r7, r0
+    2a8c:	4614      	mov	r4, r2
+    2a8e:	460e      	mov	r6, r1
+    2a90:	b921      	cbnz	r1, 2a9c <_realloc_r+0x14>
+    2a92:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
+    2a96:	4611      	mov	r1, r2
+    2a98:	f7ff bbd8 	b.w	224c <_malloc_r>
+    2a9c:	b922      	cbnz	r2, 2aa8 <_realloc_r+0x20>
+    2a9e:	f7ff ffa5 	bl	29ec <_free_r>
+    2aa2:	4625      	mov	r5, r4
+    2aa4:	4628      	mov	r0, r5
+    2aa6:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+    2aa8:	f000 f814 	bl	2ad4 <_malloc_usable_size_r>
+    2aac:	42a0      	cmp	r0, r4
+    2aae:	d20f      	bcs.n	2ad0 <_realloc_r+0x48>
+    2ab0:	4621      	mov	r1, r4
+    2ab2:	4638      	mov	r0, r7
+    2ab4:	f7ff fbca 	bl	224c <_malloc_r>
+    2ab8:	4605      	mov	r5, r0
+    2aba:	2800      	cmp	r0, #0
+    2abc:	d0f2      	beq.n	2aa4 <_realloc_r+0x1c>
+    2abe:	4631      	mov	r1, r6
+    2ac0:	4622      	mov	r2, r4
+    2ac2:	f7ff fb83 	bl	21cc <memcpy>
+    2ac6:	4631      	mov	r1, r6
+    2ac8:	4638      	mov	r0, r7
+    2aca:	f7ff ff8f 	bl	29ec <_free_r>
+    2ace:	e7e9      	b.n	2aa4 <_realloc_r+0x1c>
+    2ad0:	4635      	mov	r5, r6
+    2ad2:	e7e7      	b.n	2aa4 <_realloc_r+0x1c>
+
+00002ad4 <_malloc_usable_size_r>:
+    2ad4:	f851 3c04 	ldr.w	r3, [r1, #-4]
+    2ad8:	1f18      	subs	r0, r3, #4
+    2ada:	2b00      	cmp	r3, #0
+    2adc:	bfbc      	itt	lt
+    2ade:	580b      	ldrlt	r3, [r1, r0]
+    2ae0:	18c0      	addlt	r0, r0, r3
+    2ae2:	4770      	bx	lr
+    2ae4:	682f2e2e 	.word	0x682f2e2e
+    2ae8:	732f6c61 	.word	0x732f6c61
+    2aec:	682f6372 	.word	0x682f6372
+    2af0:	695f6c61 	.word	0x695f6c61
+    2af4:	00632e6f 	.word	0x00632e6f
+    2af8:	682f2e2e 	.word	0x682f2e2e
+    2afc:	732f6c61 	.word	0x732f6c61
+    2b00:	682f6372 	.word	0x682f6372
+    2b04:	635f6c61 	.word	0x635f6c61
+    2b08:	6e656c61 	.word	0x6e656c61
+    2b0c:	2e726164 	.word	0x2e726164
+    2b10:	0063      	.short	0x0063
+    2b12:	2e2e      	.short	0x2e2e
+    2b14:	5f64732f 	.word	0x5f64732f
+    2b18:	2f636d6d 	.word	0x2f636d6d
+    2b1c:	6d5f6473 	.word	0x6d5f6473
+    2b20:	632e636d 	.word	0x632e636d
+    2b24:	3e3e3e00 	.word	0x3e3e3e00
+    2b28:	61745300 	.word	0x61745300
+    2b2c:	53207472 	.word	0x53207472
+    2b30:	61632044 	.word	0x61632044
+    2b34:	69206472 	.word	0x69206472
+    2b38:	6174736e 	.word	0x6174736e
+    2b3c:	0d0a6c6c 	.word	0x0d0a6c6c
+    2b40:	3a732500 	.word	0x3a732500
+    2b44:	444d4320 	.word	0x444d4320
+    2b48:	46203535 	.word	0x46203535
+    2b4c:	0a6c6961 	.word	0x0a6c6961
+    2b50:	7325000d 	.word	0x7325000d
+    2b54:	4341203a 	.word	0x4341203a
+    2b58:	3134444d 	.word	0x3134444d
+    2b5c:	69614620 	.word	0x69614620
+    2b60:	000d0a6c 	.word	0x000d0a6c
+    2b64:	203a7325 	.word	0x203a7325
+    2b68:	444d4341 	.word	0x444d4341
+    2b6c:	54203134 	.word	0x54203134
+    2b70:	6f656d69 	.word	0x6f656d69
+    2b74:	6f207475 	.word	0x6f207475
+    2b78:	7562206e 	.word	0x7562206e
+    2b7c:	202c7973 	.word	0x202c7973
+    2b80:	70736572 	.word	0x70736572
+    2b84:	30203233 	.word	0x30203233
+    2b88:	38302578 	.word	0x38302578
+    2b8c:	0d0a2078 	.word	0x0d0a2078
+    2b90:	3a732500 	.word	0x3a732500
+    2b94:	444d4320 	.word	0x444d4320
+    2b98:	46203835 	.word	0x46203835
+    2b9c:	0a6c6961 	.word	0x0a6c6961
+    2ba0:	7453000d 	.word	0x7453000d
+    2ba4:	20747261 	.word	0x20747261
+    2ba8:	20434d4d 	.word	0x20434d4d
+    2bac:	74736e49 	.word	0x74736e49
+    2bb0:	0a6c6c61 	.word	0x0a6c6c61
+    2bb4:	7325000d 	.word	0x7325000d
+    2bb8:	4d43203a 	.word	0x4d43203a
+    2bbc:	53203144 	.word	0x53203144
+    2bc0:	46204950 	.word	0x46204950
+    2bc4:	206c6961 	.word	0x206c6961
+    2bc8:	7542202d 	.word	0x7542202d
+    2bcc:	72207973 	.word	0x72207973
+    2bd0:	79727465 	.word	0x79727465
+    2bd4:	0a642520 	.word	0x0a642520
+    2bd8:	7325000d 	.word	0x7325000d
+    2bdc:	4d43203a 	.word	0x4d43203a
+    2be0:	54203144 	.word	0x54203144
+    2be4:	6f656d69 	.word	0x6f656d69
+    2be8:	6f207475 	.word	0x6f207475
+    2bec:	7562206e 	.word	0x7562206e
+    2bf0:	0d0a7973 	.word	0x0d0a7973
+    2bf4:	2f445300 	.word	0x2f445300
+    2bf8:	20434d4d 	.word	0x20434d4d
+    2bfc:	64726163 	.word	0x64726163
+    2c00:	61657220 	.word	0x61657220
+    2c04:	0d0a7964 	.word	0x0d0a7964
+    2c08:	00000000 	.word	0x00000000
+
+00002c0c <__func__.1>:
+    2c0c:	735f6473 6f5f6970 6f635f70               sd_spi_op_cond.
+
+00002c1b <__func__.0>:
+    2c1b:	5f636d6d 5f697073 635f706f 00646e6f     mmc_spi_op_cond.
+	...
+
+00002c2c <mmc_trans_multipliers>:
+    2c2c:	00000000 0000000a 0000000c 0000000d     ................
+    2c3c:	0000000f 00000014 0000001a 0000001e     ................
+    2c4c:	00000023 00000028 0000002d 00000034     #...(...-...4...
+    2c5c:	00000037 0000003c 00000046 00000050     7...<...F...P...
+
+00002c6c <sd_mmc_trans_units>:
+    2c6c:	0000000a 00000064 000003e8 00002710     ....d........'..
+	...
+
+00002c88 <sd_trans_multipliers>:
+    2c88:	00000000 0000000a 0000000c 0000000d     ................
+    2c98:	0000000f 00000014 00000019 0000001e     ................
+    2ca8:	00000023 00000028 0000002d 00000032     #...(...-...2...
+    2cb8:	00000037 0000003c 00000046 00000050     7...<...F...P...
+    2cc8:	732f2e2e 6d6d5f64 64732f63 636d6d5f     ../sd_mmc/sd_mmc
+    2cd8:	6970735f 2500632e 52203a73 20646165     _spi.c.%s: Read 
+    2ce8:	636f6c62 7420736b 6f656d69 0d0a7475     blocks timeout..
+    2cf8:	3a732500 43524320 74616420 72652061     .%s: CRC data er
+    2d08:	20726f72 656b6f74 000d0a6e 203a7325     ror token...%s: 
+    2d18:	2074754f 7220666f 65676e61 74616420     Out of range dat
+    2d28:	72652061 20726f72 656b6f74 000d0a6e     a error token...
+    2d38:	203a7325 61766e49 2064696c 61746144     %s: Invalid Data
+    2d48:	73655220 736e6f70 6f542065 206e656b      Response Token 
+    2d58:	78257830 25000d0a 57203a73 65746972     0x%x...%s: Write
+    2d68:	6f6c6220 2c736b63 5f445320 5f434d4d      blocks, SD_MMC_
+    2d78:	5f495053 5f525245 2c435243 73657220     SPI_ERR_CRC, res
+    2d88:	78302070 0d0a7825 3a732500 69725720     p 0x%x...%s: Wri
+    2d98:	62206574 6b636f6c 44532073 434d4d5f     te blocks SD_MMC
+    2da8:	4950535f 5252455f 2c52575f 73657220     _SPI_ERR_WR, res
+    2db8:	78302070 0d0a7825 3a732500 6f745320     p 0x%x...%s: Sto
+    2dc8:	72772070 20657469 636f6c62 7420736b     p write blocks t
+    2dd8:	6f656d69 0d0a7475 206f4e00 43204453     imeout...No SD C
+    2de8:	20647261 70736572 65736e6f 73617720     ard response was
+    2df8:	65727020 746e6573 002e2e2e 203a7325      present....%s: 
+    2e08:	20646d63 64323025 7261202c 78302067     cmd %02d, arg 0x
+    2e18:	6c383025 52202c58 69742031 756f656d     %08lX, R1 timeou
+    2e28:	000a0d74 203a7325 20646d63 64323025     t...%s: cmd %02d
+    2e38:	7261202c 78302067 6c383025 72202c78     , arg 0x%08lx, r
+    2e48:	78302031 78323025 3152202c 4950535f     1 0x%02x, R1_SPI
+    2e58:	4d4f435f 4352435f 25000d0a 63203a73     _COM_CRC...%s: c
+    2e68:	2520646d 2c643230 67726120 25783020     md %02d, arg 0x%
+    2e78:	786c3830 3172202c 25783020 52202c78     08lx, r1 0x%x, R
+    2e88:	4c492031 4147454c 4f435f4c 4e414d4d     1 ILLEGAL_COMMAN
+    2e98:	000d0a44 203a7325 20646d63 64323025     D...%s: cmd %02d
+    2ea8:	7261202c 78302067 6c383025 72202c78     , arg 0x%08lx, r
+    2eb8:	78302031 202c7825 65203152 726f7272     1 0x%x, R1 error
+    2ec8:	25000d0a 63203a73 2520646d 2c643230     ...%s: cmd %02d,
+    2ed8:	67726120 25783020 786c3830 7542202c      arg 0x%08lx, Bu
+    2ee8:	73207973 616e6769 6c61206c 73796177     sy signal always
+    2ef8:	67696820 000d0a68 203a7325 74697257      high...%s: Writ
+    2f08:	6c622065 736b636f 6d697420 74756f65     e blocks timeout
+    2f18:	3c000d0a                                 ...<<<.
+
+00002f1f <__func__.5>:
+    2f1f:	5f697073 79735f6d 735f636e 74726174     spi_m_sync_start
+    2f2f:	6165725f 6c625f64 006b636f              _read_block.
+
+00002f3b <__func__.3>:
+    2f3b:	5f697073 79735f6d 735f636e 5f706f74     spi_m_sync_stop_
+    2f4b:	74697277 6c625f65 006b636f              write_block.
+
+00002f57 <__func__.1>:
+    2f57:	5f697073 79735f6d 735f636e 5f706f74     spi_m_sync_stop_
+    2f67:	746c756d 69727769 625f6574 6b636f6c     multiwrite_block
+	...
+
+00002f78 <__func__.6>:
+    2f78:	5f697073 79735f6d 615f636e 5f637464     spi_m_sync_adtc_
+    2f88:	72617473                                 start.
+
+00002f8e <__func__.4>:
+    2f8e:	5f697073 79735f6d 735f636e 74726174     spi_m_sync_start
+    2f9e:	6972775f 625f6574 6b636f6c               _write_blocks.
+
+00002fac <__func__.2>:
+    2fac:	5f697073 79735f6d 775f636e 5f746961     spi_m_sync_wait_
+    2fbc:	5f646e65 775f666f 65746972 6f6c625f     end_of_write_blo
+    2fcc:	00736b63                                cks.
+
+00002fd0 <__func__.0>:
+    2fd0:	5f697073 79735f6d 775f636e 65746972     spi_m_sync_write
+    2fe0:	726f775f 2e2e0064 6c61682f 6372732f     _word.../hal/src
+    2ff0:	6c61682f 6970735f 735f6d5f 2e636e79     /hal_spi_m_sync.
+    3000:	2e2e0063 6c61682f 6372732f 6c61682f     c.../hal/src/hal
+    3010:	69636d5f 6e79735f 00632e63 682f2e2e     _mci_sync.c.../h
+    3020:	732f6c70 2f636864 5f6c7068 63686473     pl/sdhc/hpl_sdhc
+    3030:	2e00632e 61682f2e 72732f6c 61682f63     .c.../hal/src/ha
+    3040:	73755f6c 5f747261 636e7973 4800632e     l_usart_sync.c.H
+    3050:	6f6c6c65 726f7720 000a646c 682f2e2e     ello world..../h
+    3060:	722f6c70 682f6374 725f6c70 632e6374     pl/rtc/hpl_rtc.c
+    3070:	2f2e2e00 2f6c7068 63726573 682f6d6f     .../hpl/sercom/h
+    3080:	735f6c70 6f637265 00632e6d 40003000     pl_sercom.c..0.@
+    3090:	40003400 41012000 41014000 43000000     .4.@. .A.@.A...C
+    30a0:	43000400 43000800 43000c00              ...C...C...C
+
+000030ac <_i2cms>:
+	...
+
+000030c4 <sercomspi_regs>:
+    30c4:	0030000c 00020000 00000000 01ff00fe     ..0.............
+    30d4:	62654404 49206775 6974696e 7a696c61     .Debug Initializ
+    30e4:	000a6465 65737341 46207472 756c6961     ed..Assert Failu
+    30f4:	61206572 696c2074 2520656e 25202c64     re at line %d, %
+    3104:	25203a73 00000a73                       s: %s...
+
+0000310c <__sf_fake_stderr>:
+	...
+
+0000312c <__sf_fake_stdin>:
+	...
+
+0000314c <__sf_fake_stdout>:
+	...
+    316c:	2b302d23 6c680020 6665004c 47464567     #-0+ .hlL.efgEFG
+    317c:	32313000 36353433 41393837 45444342     .0123456789ABCDE
+    318c:	31300046 35343332 39383736 64636261     F.0123456789abcd
+    319c:	00006665                                ef..
+
+000031a0 <_init>:
+    31a0:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+    31a2:	bf00      	nop
+    31a4:	bcf8      	pop	{r3, r4, r5, r6, r7}
+    31a6:	bc08      	pop	{r3}
+    31a8:	469e      	mov	lr, r3
+    31aa:	4770      	bx	lr
+
+000031ac <__frame_dummy_init_array_entry>:
+    31ac:	0289 0000                                   ....
+
+000031b0 <_fini>:
+    31b0:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+    31b2:	bf00      	nop
+    31b4:	bcf8      	pop	{r3, r4, r5, r6, r7}
+    31b6:	bc08      	pop	{r3}
+    31b8:	469e      	mov	lr, r3
+    31ba:	4770      	bx	lr
+
+000031bc <__do_global_dtors_aux_fini_array_entry>:
+    31bc:	0265 0000                                   e...
diff --git a/build/spi_sd_mmc_lib.map b/build/spi_sd_mmc_lib.map
new file mode 100644
index 0000000..c7229cd
--- /dev/null
+++ b/build/spi_sd_mmc_lib.map
@@ -0,0 +1,16309 @@
+Archive member included to satisfy reference by file (symbol)
+
+/usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m/nofp/libgcc.a(_arm_muldf3.o)
+                              hpl/sercom/hpl_sercom.o (__aeabi_dmul)
+/usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m/nofp/libgcc.a(_arm_addsubdf3.o)
+                              hpl/sercom/hpl_sercom.o (__aeabi_dsub)
+/usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m/nofp/libgcc.a(_arm_muldivdf3.o)
+                              hpl/sercom/hpl_sercom.o (__aeabi_ddiv)
+/usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m/nofp/libgcc.a(_arm_fixunsdfsi.o)
+                              hpl/sercom/hpl_sercom.o (__aeabi_d2uiz)
+/usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m/nofp/libgcc.a(_aeabi_ldivmod.o)
+                              hpl/sercom/hpl_sercom.o (__aeabi_ldivmod)
+/usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m/nofp/libgcc.a(_aeabi_uldivmod.o)
+                              hpl/sdhc/hpl_sdhc.o (__aeabi_uldivmod)
+/usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m/nofp/libgcc.a(_udivmoddi4.o)
+                              /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m/nofp/libgcc.a(_aeabi_ldivmod.o) (__udivmoddi4)
+/usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m/nofp/libgcc.a(_dvmd_tls.o)
+                              /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m/nofp/libgcc.a(_aeabi_ldivmod.o) (__aeabi_ldiv0)
+/usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-atexit.o)
+                              /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/crt0.o (atexit)
+/usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-exit.o)
+                              /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/crt0.o (exit)
+/usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-fini.o)
+                              /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/crt0.o (__libc_fini_array)
+/usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-impure.o)
+                              /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-exit.o) (_global_impure_ptr)
+/usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-init.o)
+                              /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/crt0.o (__libc_init_array)
+/usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-memcpy-stub.o)
+                              build/gcc/startup_same54.o (memcpy)
+/usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-memset.o)
+                              /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/crt0.o (memset)
+/usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-printf.o)
+                              hal/utils/src/utils_syscalls.o (printf)
+/usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-strlen.o)
+                              shared/util/pdebug.o (strlen)
+/usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-vsprintf.o)
+                              shared/util/pdebug.o (vsprintf)
+/usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-__atexit.o)
+                              /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-atexit.o) (__register_exitproc)
+/usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-__call_atexit.o)
+                              /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-__atexit.o) (__call_exitprocs)
+/usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-findfp.o)
+                              /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-printf.o) (__sinit)
+/usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-fwalk.o)
+                              /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-findfp.o) (_fwalk)
+/usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-lock.o)
+                              /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-findfp.o) (__retarget_lock_init_recursive)
+/usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-nano-mallocr.o)
+                              /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-findfp.o) (_malloc_r)
+/usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-nano-svfprintf.o)
+                              /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-vsprintf.o) (_svfprintf_r)
+/usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-nano-vfprintf_i.o)
+                              /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-nano-svfprintf.o) (_printf_i)
+/usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-nano-vfprintf.o)
+                              /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-printf.o) (_vfprintf_r)
+/usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-sbrkr.o)
+                              /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-nano-mallocr.o) (_sbrk_r)
+/usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-stdio.o)
+                              /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-findfp.o) (__sread)
+/usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-wbuf.o)
+                              /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-nano-vfprintf.o) (__swbuf_r)
+/usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-writer.o)
+                              /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-stdio.o) (_write_r)
+/usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-wsetup.o)
+                              /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-nano-vfprintf.o) (__swsetup_r)
+/usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-closer.o)
+                              /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-stdio.o) (_close_r)
+/usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-fflush.o)
+                              /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-findfp.o) (_fflush_r)
+/usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-fvwrite.o)
+                              /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-nano-vfprintf.o) (__sfvwrite_r)
+/usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-lseekr.o)
+                              /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-stdio.o) (_lseek_r)
+/usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-makebuf.o)
+                              /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-wsetup.o) (__smakebuf_r)
+/usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-memchr.o)
+                              /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-nano-svfprintf.o) (memchr)
+/usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-memmove.o)
+                              /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-nano-svfprintf.o) (memmove)
+/usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-mlock.o)
+                              /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-nano-mallocr.o) (__malloc_lock)
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+                              /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-nano-svfprintf.o) (_free_r)
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+                              /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-nano-svfprintf.o) (_realloc_r)
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+                              /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-stdio.o) (_read_r)
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+                              /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-sbrkr.o) (errno)
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+                              /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-makebuf.o) (_fstat_r)
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+                              /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-makebuf.o) (_isatty_r)
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+__lock___sinit_recursive_mutex
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+__lock___malloc_recursive_mutex
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+__lock___at_quick_exit_mutex
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+__lock___dd_hash_mutex
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+__lock___tz_mutex   0x1               /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-lock.o)
+__lock___sfp_recursive_mutex
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+ .text._usart_sync_get_status
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+ .text._usart_async_get_status
+                0x0000000000000000        0x8 hpl/sercom/hpl_sercom.o
+ .text._usart_async_write_byte
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+ .text._usart_async_is_byte_sent
+                0x0000000000000000        0xa hpl/sercom/hpl_sercom.o
+ .text._usart_sync_set_flow_control_state
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+ .text._usart_async_set_flow_control_state
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+ .text._usart_async_get_flow_control_state
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+ .text._usart_sync_get_flow_control_state
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+ .text._usart_async_enable_byte_sent_irq
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+ .text._usart_async_enable_tx_done_irq
+                0x0000000000000000        0x8 hpl/sercom/hpl_sercom.o
+ .text._usart_sync_get_hardware_index
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+ .text._usart_async_get_hardware_index
+                0x0000000000000000        0xc hpl/sercom/hpl_sercom.o
+ .text._usart_async_set_irq_state
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+ .text._i2c_m_async_enable
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+ .text._i2c_m_async_disable
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+ .text._i2c_m_async_set_baudrate
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+ .text._i2c_m_async_init
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+ .text._i2c_m_async_deinit
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+ .text._i2c_m_async_transfer
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+ .text._i2c_m_async_register_callback
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+ .text._i2c_m_async_send_stop
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+ .text._i2c_m_async_get_bytes_left
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+ .text._i2c_m_sync_init
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+ .text._i2c_m_sync_deinit
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+ .text._i2c_m_sync_enable
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+ .text._i2c_m_sync_disable
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+ .text._i2c_m_sync_set_baudrate
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+ .text._i2c_m_async_set_irq_state
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+ .text._i2c_m_sync_transfer
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+ .text._i2c_m_sync_send_stop
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+ .text._i2c_s_sync_init
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+ .text._i2c_s_async_init
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+ .text._i2c_s_sync_deinit
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+ .text._i2c_s_async_deinit
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+ .text._i2c_s_sync_enable
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+ .text._i2c_s_async_enable
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+ .text._i2c_s_sync_disable
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+ .text._i2c_s_async_disable
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+ .text._i2c_s_sync_is_10bit_addressing_on
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+ .text._i2c_s_async_is_10bit_addressing_on
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+ .text._i2c_s_sync_set_address
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+ .text._i2c_s_async_set_address
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+ .text._i2c_s_sync_write_byte
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+ .text._i2c_s_async_write_byte
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+ .text._i2c_s_sync_read_byte
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+ .text._i2c_s_sync_is_byte_sent
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+ .text._i2c_s_sync_is_byte_received
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+ .text._i2c_s_sync_get_status
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+ .text._i2c_s_sync_clear_data_ready_flag
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+ .text._i2c_s_async_get_status
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+ .text._i2c_s_async_abort_transmission
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+ .text._i2c_s_async_set_irq_state
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+ .text._spi_s_sync_init
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+ .text._spi_m_async_init
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+ .text._spi_s_async_init
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+ .text._spi_m_async_deinit
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+ .text._spi_s_async_deinit
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+ .text._spi_m_sync_deinit
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+ .text._spi_s_sync_deinit
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+ .text._spi_s_sync_enable
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+ .text._spi_s_async_enable
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+ .text._spi_s_sync_disable
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+ .text._spi_m_async_disable
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+ .text._spi_s_async_disable
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+ .text._spi_m_async_set_mode
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+ .text._spi_s_async_set_mode
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+ .text._spi_s_sync_set_mode
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+ .text._spi_calc_baud_val
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+ .text._spi_m_sync_set_baudrate
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+ .text._spi_m_async_set_baudrate
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+ .text._spi_m_sync_set_char_size
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+ .text._spi_m_async_set_char_size
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+ .text._spi_s_sync_set_char_size
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+ .text._spi_m_sync_set_data_order
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+ .text._spi_s_sync_set_data_order
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+ .text._spi_m_async_enable_tx
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+ .text._spi_s_async_enable_tx
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+ .text._spi_m_async_enable_rx
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+ .text._spi_s_async_enable_rx
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+ .text._spi_m_async_enable_tx_complete
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+ .text._spi_s_async_enable_ss_detect
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+ .text._spi_m_async_write_one
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+ .text._spi_s_async_read_one
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+ .text._spi_s_sync_is_rx_ready
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+ .text._spi_s_sync_is_ss_deactivated
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+ .text._spi_s_sync_is_error
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+
+Memory Configuration
+
+Name             Origin             Length             Attributes
+rom              0x0000000000000000 0x0000000000100000 xr
+ram              0x0000000020000000 0x0000000000040000 xrw
+bkupram          0x0000000047000000 0x0000000000002000 xrw
+qspi             0x0000000004000000 0x0000000001000000 xrw
+*default*        0x0000000000000000 0xffffffffffffffff
+
+Linker script and memory map
+
+LOAD /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m/nofp/crti.o
+LOAD /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m/nofp/crtbegin.o
+LOAD /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/crt0.o
+LOAD hal/src/hal_io.o
+LOAD hpl/systick/hpl_systick.o
+LOAD hal/src/hal_calendar.o
+LOAD sd_mmc_start.o
+LOAD fatfs_main.o
+LOAD hpl/core/hpl_core_m4.o
+LOAD hal/src/hal_cache.o
+LOAD hal/utils/src/utils_syscalls.o
+LOAD sd_mmc/sd_mmc.o
+LOAD sd_mmc/sd_mmc_spi.o
+LOAD hal/src/hal_spi_m_sync.o
+LOAD hal/src/hal_mci_sync.o
+LOAD hal/src/hal_delay.o
+LOAD hpl/pm/hpl_pm.o
+LOAD hpl/core/hpl_init.o
+LOAD hpl/gclk/hpl_gclk.o
+LOAD hal/utils/src/utils_list.o
+LOAD hal/utils/src/utils_assert.o
+LOAD hpl/oscctrl/hpl_oscctrl.o
+LOAD hpl/sdhc/hpl_sdhc.o
+LOAD hal/src/hal_usart_sync.o
+LOAD hpl/mclk/hpl_mclk.o
+LOAD hpl/ramecc/hpl_ramecc.o
+LOAD hal/src/hal_init.o
+LOAD diskio_start.o
+LOAD build/gcc/startup_same54.o
+LOAD main.o
+LOAD hpl/osc32kctrl/hpl_osc32kctrl.o
+LOAD diskio/sdmmc_diskio.o
+LOAD hpl/rtc/hpl_rtc.o
+LOAD examples/driver_examples.o
+LOAD driver_init.o
+LOAD hpl/sercom/hpl_sercom.o
+LOAD hal/src/hal_atomic.o
+LOAD hal/src/hal_gpio.o
+LOAD hal/utils/src/utils_event.o
+LOAD hal/src/hal_sleep.o
+LOAD hpl/dmac/hpl_dmac.o
+LOAD build/system_same54.o
+LOAD atmel_start.o
+LOAD fatfs/src/ff.o
+LOAD hpl/cmcc/hpl_cmcc.o
+LOAD shared/util/pdebug.o
+START GROUP
+LOAD /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libm.a
+END GROUP
+START GROUP
+LOAD /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m/nofp/libgcc.a
+LOAD /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a
+END GROUP
+START GROUP
+LOAD /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m/nofp/libgcc.a
+LOAD /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a
+END GROUP
+LOAD /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m/nofp/crtend.o
+LOAD /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m/nofp/crtn.o
+                0x0000000000010000                STACK_SIZE = DEFINED (STACK_SIZE)?STACK_SIZE:DEFINED (__stack_size__)?__stack_size__:0x10000
+
+.text           0x0000000000000000     0x31c0
+                0x0000000000000000                . = ALIGN (0x4)
+                0x0000000000000000                _sfixed = .
+ *(.vectors .vectors.*)
+ .vectors       0x0000000000000000      0x264 build/gcc/startup_same54.o
+                0x0000000000000000                exception_table
+ *(.text .text.* .gnu.linkonce.t.*)
+ .text.__do_global_dtors_aux
+                0x0000000000000264       0x24 /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m/nofp/crtbegin.o
+ .text.frame_dummy
+                0x0000000000000288       0x1c /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m/nofp/crtbegin.o
+ .text.io_write
+                0x00000000000002a4       0x30 hal/src/hal_io.o
+                0x00000000000002a4                io_write
+ .text.io_read  0x00000000000002d4       0x30 hal/src/hal_io.o
+                0x00000000000002d4                io_read
+ .text._delay_init
+                0x0000000000000304       0x10 hpl/systick/hpl_systick.o
+                0x0000000000000304                _delay_init
+ .text.calendar_init
+                0x0000000000000314       0x44 hal/src/hal_calendar.o
+                0x0000000000000314                calendar_init
+ .text.SDMMC_example
+                0x0000000000000358       0x6c sd_mmc_start.o
+                0x0000000000000358                SDMMC_example
+ .text.sd_mmc_stack_init
+                0x00000000000003c4       0x18 sd_mmc_start.o
+                0x00000000000003c4                sd_mmc_stack_init
+ .text._sbrk    0x00000000000003dc       0x1c hal/utils/src/utils_syscalls.o
+                0x00000000000003dc                _sbrk
+ .text.SDMMC_UNSTUFF_BITS
+                0x00000000000003f8       0x60 sd_mmc/sd_mmc.o
+ .text.gpio_get_pin_level
+                0x0000000000000458       0x48 sd_mmc/sd_mmc.o
+ .text.sd_mmc_configure_slot
+                0x00000000000004a0       0x28 sd_mmc/sd_mmc.o
+ .text.sd_mmc_select_slot
+                0x00000000000004c8       0xb4 sd_mmc/sd_mmc.o
+ .text.sd_mmc_cmd13
+                0x000000000000057c       0x44 sd_mmc/sd_mmc.o
+ .text.sd_mmc_cmd9_spi
+                0x00000000000005c0       0x50 sd_mmc/sd_mmc.o
+ .text.sd_mmc_deselect_slot
+                0x0000000000000610       0x18 sd_mmc/sd_mmc.o
+ .text.sdio_cmd53.constprop.0
+                0x0000000000000628       0x7c sd_mmc/sd_mmc.o
+ .text.sdio_cmd52.constprop.0
+                0x00000000000006a4       0x64 sd_mmc/sd_mmc.o
+ .text.sd_mmc_init
+                0x0000000000000708       0x18 sd_mmc/sd_mmc.o
+                0x0000000000000708                sd_mmc_init
+ .text.sd_mmc_check
+                0x0000000000000720      0x5e8 sd_mmc/sd_mmc.o
+                0x0000000000000720                sd_mmc_check
+ .text.sd_mmc_get_type
+                0x0000000000000d08       0x24 sd_mmc/sd_mmc.o
+                0x0000000000000d08                sd_mmc_get_type
+ .text.sd_mmc_init_read_blocks
+                0x0000000000000d2c       0x84 sd_mmc/sd_mmc.o
+                0x0000000000000d2c                sd_mmc_init_read_blocks
+ .text.sd_mmc_start_read_blocks
+                0x0000000000000db0       0x50 sd_mmc/sd_mmc.o
+                0x0000000000000db0                sd_mmc_start_read_blocks
+ .text.sd_mmc_wait_end_of_read_blocks
+                0x0000000000000e00       0x5c sd_mmc/sd_mmc.o
+                0x0000000000000e00                sd_mmc_wait_end_of_read_blocks
+ .text.sdio_read_extended
+                0x0000000000000e5c       0x74 sd_mmc/sd_mmc.o
+                0x0000000000000e5c                sdio_read_extended
+ .text.spi_m_sync_wait_busy
+                0x0000000000000ed0       0x80 sd_mmc/sd_mmc_spi.o
+ .text.spi_m_sync_stop_read_block
+                0x0000000000000f50       0x3c sd_mmc/sd_mmc_spi.o
+ .text.spi_m_sync_start_read_block
+                0x0000000000000f8c       0xd4 sd_mmc/sd_mmc_spi.o
+ .text.spi_m_sync_adtc_start
+                0x0000000000001060      0x1e8 sd_mmc/sd_mmc_spi.o
+                0x0000000000001060                spi_m_sync_adtc_start
+ .text.spi_m_sync_send_cmd
+                0x0000000000001248       0x14 sd_mmc/sd_mmc_spi.o
+                0x0000000000001248                spi_m_sync_send_cmd
+ .text.spi_m_sync_start_read_blocks
+                0x000000000000125c       0xac sd_mmc/sd_mmc_spi.o
+                0x000000000000125c                spi_m_sync_start_read_blocks
+ .text.spi_m_sync_wait_end_of_read_blocks
+                0x0000000000001308        0x4 sd_mmc/sd_mmc_spi.o
+                0x0000000000001308                spi_m_sync_wait_end_of_read_blocks
+ .text.spi_m_sync_read_word
+                0x000000000000130c       0xac sd_mmc/sd_mmc_spi.o
+                0x000000000000130c                spi_m_sync_read_word
+ .text.spi_m_sync_get_response
+                0x00000000000013b8        0xc sd_mmc/sd_mmc_spi.o
+                0x00000000000013b8                spi_m_sync_get_response
+ .text.spi_m_sync_send_clock
+                0x00000000000013c4       0x34 sd_mmc/sd_mmc_spi.o
+                0x00000000000013c4                spi_m_sync_send_clock
+ .text.spi_m_sync_select_device
+                0x00000000000013f8       0x18 sd_mmc/sd_mmc_spi.o
+                0x00000000000013f8                spi_m_sync_select_device
+ .text.spi_m_sync_deselect_device
+                0x0000000000001410       0x18 sd_mmc/sd_mmc_spi.o
+                0x0000000000001410                spi_m_sync_deselect_device
+ .text.spi_m_sync_init
+                0x0000000000001428       0x4c hal/src/hal_spi_m_sync.o
+                0x0000000000001428                spi_m_sync_init
+ .text.spi_m_sync_transfer
+                0x0000000000001474       0x3c hal/src/hal_spi_m_sync.o
+                0x0000000000001474                spi_m_sync_transfer
+ .text._spi_m_sync_io_write
+                0x00000000000014b0       0x38 hal/src/hal_spi_m_sync.o
+ .text._spi_m_sync_io_read
+                0x00000000000014e8       0x38 hal/src/hal_spi_m_sync.o
+ .text.spi_m_sync_get_io_descriptor
+                0x0000000000001520       0x28 hal/src/hal_spi_m_sync.o
+                0x0000000000001520                spi_m_sync_get_io_descriptor
+ .text.mci_sync_init
+                0x0000000000001548       0x30 hal/src/hal_mci_sync.o
+                0x0000000000001548                mci_sync_init
+ .text.delay_init
+                0x0000000000001578       0x10 hal/src/hal_delay.o
+                0x0000000000001578                delay_init
+ .text._init_chip
+                0x0000000000001588       0x44 hpl/core/hpl_init.o
+                0x0000000000001588                _init_chip
+ .text._gclk_init_generators_by_fref
+                0x00000000000015cc       0x38 hpl/gclk/hpl_gclk.o
+                0x00000000000015cc                _gclk_init_generators_by_fref
+ .text.assert   0x0000000000001604        0x6 hal/utils/src/utils_assert.o
+                0x0000000000001604                assert
+ .text._oscctrl_init_sources
+                0x000000000000160a        0x2 hpl/oscctrl/hpl_oscctrl.o
+                0x000000000000160a                _oscctrl_init_sources
+ .text._oscctrl_init_referenced_generators
+                0x000000000000160c       0x3c hpl/oscctrl/hpl_oscctrl.o
+                0x000000000000160c                _oscctrl_init_referenced_generators
+ .text._mci_sync_init
+                0x0000000000001648       0x60 hpl/sdhc/hpl_sdhc.o
+                0x0000000000001648                _mci_sync_init
+ .text.usart_sync_write
+                0x00000000000016a8       0x74 hal/src/hal_usart_sync.o
+ .text.usart_sync_read
+                0x000000000000171c       0x60 hal/src/hal_usart_sync.o
+ .text.usart_sync_init
+                0x000000000000177c       0x40 hal/src/hal_usart_sync.o
+                0x000000000000177c                usart_sync_init
+ .text.usart_sync_enable
+                0x00000000000017bc       0x2c hal/src/hal_usart_sync.o
+                0x00000000000017bc                usart_sync_enable
+ .text.usart_sync_get_io_descriptor
+                0x00000000000017e8       0x24 hal/src/hal_usart_sync.o
+                0x00000000000017e8                usart_sync_get_io_descriptor
+ .text._mclk_init
+                0x000000000000180c        0xc hpl/mclk/hpl_mclk.o
+                0x000000000000180c                _mclk_init
+ .text.RAMECC_Handler
+                0x0000000000001818       0x38 hpl/ramecc/hpl_ramecc.o
+                0x0000000000001818                RAMECC_Handler
+ .text.diskio_init
+                0x0000000000001850        0x2 diskio_start.o
+                0x0000000000001850                diskio_init
+ .text.Dummy_Handler
+                0x0000000000001852        0x2 build/gcc/startup_same54.o
+                0x0000000000001852                EIC_5_Handler
+                0x0000000000001852                SVCall_Handler
+                0x0000000000001852                SERCOM0_2_Handler
+                0x0000000000001852                EIC_13_Handler
+                0x0000000000001852                EVSYS_0_Handler
+                0x0000000000001852                TCC1_3_Handler
+                0x0000000000001852                DAC_3_Handler
+                0x0000000000001852                TRNG_Handler
+                0x0000000000001852                HardFault_Handler
+                0x0000000000001852                TC2_Handler
+                0x0000000000001852                PDEC_2_Handler
+                0x0000000000001852                EIC_4_Handler
+                0x0000000000001852                AC_Handler
+                0x0000000000001852                SERCOM3_1_Handler
+                0x0000000000001852                SysTick_Handler
+                0x0000000000001852                TCC2_3_Handler
+                0x0000000000001852                SERCOM3_2_Handler
+                0x0000000000001852                PendSV_Handler
+                0x0000000000001852                TC7_Handler
+                0x0000000000001852                ADC1_1_Handler
+                0x0000000000001852                EVSYS_3_Handler
+                0x0000000000001852                PDEC_0_Handler
+                0x0000000000001852                QSPI_Handler
+                0x0000000000001852                NonMaskableInt_Handler
+                0x0000000000001852                TCC0_0_Handler
+                0x0000000000001852                EIC_3_Handler
+                0x0000000000001852                MemManagement_Handler
+                0x0000000000001852                DAC_2_Handler
+                0x0000000000001852                SERCOM0_0_Handler
+                0x0000000000001852                UsageFault_Handler
+                0x0000000000001852                SERCOM4_0_Handler
+                0x0000000000001852                EIC_10_Handler
+                0x0000000000001852                SERCOM0_3_Handler
+                0x0000000000001852                EIC_11_Handler
+                0x0000000000001852                EIC_9_Handler
+                0x0000000000001852                OSC32KCTRL_Handler
+                0x0000000000001852                TCC2_1_Handler
+                0x0000000000001852                SUPC_1_Handler
+                0x0000000000001852                TCC0_5_Handler
+                0x0000000000001852                TCC0_6_Handler
+                0x0000000000001852                SERCOM6_2_Handler
+                0x0000000000001852                EVSYS_1_Handler
+                0x0000000000001852                TCC1_4_Handler
+                0x0000000000001852                TC6_Handler
+                0x0000000000001852                DMAC_0_Handler
+                0x0000000000001852                WDT_Handler
+                0x0000000000001852                CAN0_Handler
+                0x0000000000001852                EIC_8_Handler
+                0x0000000000001852                EIC_15_Handler
+                0x0000000000001852                SERCOM6_0_Handler
+                0x0000000000001852                SERCOM5_0_Handler
+                0x0000000000001852                TC4_Handler
+                0x0000000000001852                TC1_Handler
+                0x0000000000001852                OSCCTRL_4_Handler
+                0x0000000000001852                SERCOM4_3_Handler
+                0x0000000000001852                EIC_12_Handler
+                0x0000000000001852                DMAC_4_Handler
+                0x0000000000001852                TCC4_2_Handler
+                0x0000000000001852                PAC_Handler
+                0x0000000000001852                TCC1_0_Handler
+                0x0000000000001852                USB_0_Handler
+                0x0000000000001852                OSCCTRL_0_Handler
+                0x0000000000001852                EIC_0_Handler
+                0x0000000000001852                OSCCTRL_3_Handler
+                0x0000000000001852                SERCOM4_1_Handler
+                0x0000000000001852                TC3_Handler
+                0x0000000000001852                Dummy_Handler
+                0x0000000000001852                TCC3_0_Handler
+                0x0000000000001852                TCC2_2_Handler
+                0x0000000000001852                SERCOM5_1_Handler
+                0x0000000000001852                TCC1_1_Handler
+                0x0000000000001852                DMAC_2_Handler
+                0x0000000000001852                ADC0_0_Handler
+                0x0000000000001852                SERCOM0_1_Handler
+                0x0000000000001852                OSCCTRL_2_Handler
+                0x0000000000001852                ADC1_0_Handler
+                0x0000000000001852                TCC1_2_Handler
+                0x0000000000001852                SERCOM7_1_Handler
+                0x0000000000001852                USB_1_Handler
+                0x0000000000001852                PM_Handler
+                0x0000000000001852                SERCOM6_3_Handler
+                0x0000000000001852                SERCOM2_3_Handler
+                0x0000000000001852                DAC_4_Handler
+                0x0000000000001852                TCC3_2_Handler
+                0x0000000000001852                SERCOM7_0_Handler
+                0x0000000000001852                TCC0_2_Handler
+                0x0000000000001852                DMAC_1_Handler
+                0x0000000000001852                TCC4_0_Handler
+                0x0000000000001852                SERCOM7_3_Handler
+                0x0000000000001852                GMAC_Handler
+                0x0000000000001852                SDHC1_Handler
+                0x0000000000001852                USB_3_Handler
+                0x0000000000001852                SERCOM7_2_Handler
+                0x0000000000001852                CAN1_Handler
+                0x0000000000001852                TCC2_0_Handler
+                0x0000000000001852                PDEC_1_Handler
+                0x0000000000001852                TCC4_1_Handler
+                0x0000000000001852                SERCOM5_3_Handler
+                0x0000000000001852                USB_2_Handler
+                0x0000000000001852                SERCOM6_1_Handler
+                0x0000000000001852                SDHC0_Handler
+                0x0000000000001852                SERCOM1_1_Handler
+                0x0000000000001852                I2S_Handler
+                0x0000000000001852                EIC_2_Handler
+                0x0000000000001852                PCC_Handler
+                0x0000000000001852                DAC_0_Handler
+                0x0000000000001852                TCC0_1_Handler
+                0x0000000000001852                SERCOM1_3_Handler
+                0x0000000000001852                EIC_6_Handler
+                0x0000000000001852                OSCCTRL_1_Handler
+                0x0000000000001852                SERCOM1_0_Handler
+                0x0000000000001852                PUKCC_Handler
+                0x0000000000001852                SERCOM2_1_Handler
+                0x0000000000001852                SERCOM1_2_Handler
+                0x0000000000001852                SERCOM3_0_Handler
+                0x0000000000001852                EIC_1_Handler
+                0x0000000000001852                SERCOM4_2_Handler
+                0x0000000000001852                EVSYS_4_Handler
+                0x0000000000001852                EIC_7_Handler
+                0x0000000000001852                NVMCTRL_1_Handler
+                0x0000000000001852                SERCOM5_2_Handler
+                0x0000000000001852                SERCOM3_3_Handler
+                0x0000000000001852                ADC0_1_Handler
+                0x0000000000001852                SERCOM2_2_Handler
+                0x0000000000001852                TCC3_1_Handler
+                0x0000000000001852                EIC_14_Handler
+                0x0000000000001852                DAC_1_Handler
+                0x0000000000001852                NVMCTRL_0_Handler
+                0x0000000000001852                MCLK_Handler
+                0x0000000000001852                EVSYS_2_Handler
+                0x0000000000001852                SUPC_0_Handler
+                0x0000000000001852                BusFault_Handler
+                0x0000000000001852                FREQM_Handler
+                0x0000000000001852                TC0_Handler
+                0x0000000000001852                TCC0_3_Handler
+                0x0000000000001852                DMAC_3_Handler
+                0x0000000000001852                DebugMonitor_Handler
+                0x0000000000001852                TCC0_4_Handler
+                0x0000000000001852                TC5_Handler
+                0x0000000000001852                SERCOM2_0_Handler
+                0x0000000000001852                AES_Handler
+                0x0000000000001852                ICM_Handler
+ .text.Reset_Handler
+                0x0000000000001854       0x90 build/gcc/startup_same54.o
+                0x0000000000001854                Reset_Handler
+ .text.startup.main
+                0x00000000000018e4       0x2c main.o
+                0x00000000000018e4                main
+ .text._osc32kctrl_init_sources
+                0x0000000000001910       0x20 hpl/osc32kctrl/hpl_osc32kctrl.o
+                0x0000000000001910                _osc32kctrl_init_sources
+ .text.hri_rtcmode0_wait_for_sync
+                0x0000000000001930        0x8 hpl/rtc/hpl_rtc.o
+ .text._calendar_init
+                0x0000000000001938       0x7c hpl/rtc/hpl_rtc.o
+                0x0000000000001938                _calendar_init
+ .text.RTC_Handler
+                0x00000000000019b4       0x3c hpl/rtc/hpl_rtc.o
+                0x00000000000019b4                RTC_Handler
+ .text.gpio_set_pin_direction
+                0x00000000000019f0       0x48 driver_init.o
+ .text.gpio_set_pin_pull_mode.constprop.0
+                0x0000000000001a38       0x20 driver_init.o
+ .text._gpio_set_pin_function
+                0x0000000000001a58       0x4c driver_init.o
+ .text.CALENDER_INTERFACE_CLOCK_init
+                0x0000000000001aa4       0x10 driver_init.o
+                0x0000000000001aa4                CALENDER_INTERFACE_CLOCK_init
+ .text.CALENDER_INTERFACE_init
+                0x0000000000001ab4       0x24 driver_init.o
+                0x0000000000001ab4                CALENDER_INTERFACE_init
+ .text.USART_DBG_PORT_init
+                0x0000000000001ad8       0x24 driver_init.o
+                0x0000000000001ad8                USART_DBG_PORT_init
+ .text.USART_DBG_CLOCK_init
+                0x0000000000001afc       0x24 driver_init.o
+                0x0000000000001afc                USART_DBG_CLOCK_init
+ .text.USART_DBG_init
+                0x0000000000001b20       0x2c driver_init.o
+                0x0000000000001b20                USART_DBG_init
+ .text.SPI_SD_MMC_PORT_init
+                0x0000000000001b4c       0x64 driver_init.o
+                0x0000000000001b4c                SPI_SD_MMC_PORT_init
+ .text.SPI_SD_MMC_CLOCK_init
+                0x0000000000001bb0       0x24 driver_init.o
+                0x0000000000001bb0                SPI_SD_MMC_CLOCK_init
+ .text.SPI_SD_MMC_init
+                0x0000000000001bd4       0x28 driver_init.o
+                0x0000000000001bd4                SPI_SD_MMC_init
+ .text.IO_BUS_PORT_init
+                0x0000000000001bfc       0xb0 driver_init.o
+                0x0000000000001bfc                IO_BUS_PORT_init
+ .text.IO_BUS_CLOCK_init
+                0x0000000000001cac       0x20 driver_init.o
+                0x0000000000001cac                IO_BUS_CLOCK_init
+ .text.IO_BUS_init
+                0x0000000000001ccc       0x28 driver_init.o
+                0x0000000000001ccc                IO_BUS_init
+ .text.delay_driver_init
+                0x0000000000001cf4       0x10 driver_init.o
+                0x0000000000001cf4                delay_driver_init
+ .text.system_init
+                0x0000000000001d04       0x38 driver_init.o
+                0x0000000000001d04                system_init
+ .text.hri_sercomspi_wait_for_sync
+                0x0000000000001d3c        0x8 hpl/sercom/hpl_sercom.o
+ .text.hri_sercomusart_wait_for_sync
+                0x0000000000001d44        0x8 hpl/sercom/hpl_sercom.o
+ .text.hri_sercomspi_clear_CTRLA_ENABLE_bit
+                0x0000000000001d4c       0x14 hpl/sercom/hpl_sercom.o
+ .text.hri_sercomusart_clear_CTRLA_ENABLE_bit
+                0x0000000000001d60       0x14 hpl/sercom/hpl_sercom.o
+ .text._sercom_get_hardware_index
+                0x0000000000001d74       0x38 hpl/sercom/hpl_sercom.o
+ .text._usart_init
+                0x0000000000001dac       0x8c hpl/sercom/hpl_sercom.o
+ .text._usart_sync_init
+                0x0000000000001e38       0x2c hpl/sercom/hpl_sercom.o
+                0x0000000000001e38                _usart_sync_init
+ .text._usart_sync_enable
+                0x0000000000001e64       0x14 hpl/sercom/hpl_sercom.o
+                0x0000000000001e64                _usart_sync_enable
+ .text._usart_sync_write_byte
+                0x0000000000001e78        0x6 hpl/sercom/hpl_sercom.o
+                0x0000000000001e78                _usart_sync_write_byte
+ .text._usart_sync_read_byte
+                0x0000000000001e7e        0x8 hpl/sercom/hpl_sercom.o
+                0x0000000000001e7e                _usart_sync_read_byte
+ .text._usart_sync_is_ready_to_send
+                0x0000000000001e86        0xa hpl/sercom/hpl_sercom.o
+                0x0000000000001e86                _usart_sync_is_ready_to_send
+ .text._usart_sync_is_transmit_done
+                0x0000000000001e90        0xa hpl/sercom/hpl_sercom.o
+                0x0000000000001e90                _usart_sync_is_transmit_done
+ .text._usart_sync_is_byte_received
+                0x0000000000001e9a        0xa hpl/sercom/hpl_sercom.o
+                0x0000000000001e9a                _usart_sync_is_byte_received
+ .text._spi_m_sync_init
+                0x0000000000001ea4      0x134 hpl/sercom/hpl_sercom.o
+                0x0000000000001ea4                _spi_m_sync_init
+ .text._spi_m_sync_trans
+                0x0000000000001fd8       0xc0 hpl/sercom/hpl_sercom.o
+                0x0000000000001fd8                _spi_m_sync_trans
+ .text.atomic_enter_critical
+                0x0000000000002098        0xe hal/src/hal_atomic.o
+                0x0000000000002098                atomic_enter_critical
+ .text.atomic_leave_critical
+                0x00000000000020a6        0xc hal/src/hal_atomic.o
+                0x00000000000020a6                atomic_leave_critical
+ *fill*         0x00000000000020b2        0x2 
+ .text.atmel_start_init
+                0x00000000000020b4       0x20 atmel_start.o
+                0x00000000000020b4                atmel_start_init
+ .text.pprintf  0x00000000000020d4       0x60 shared/util/pdebug.o
+                0x00000000000020d4                pprintf
+ .text.pdebug_init
+                0x0000000000002134       0x34 shared/util/pdebug.o
+                0x0000000000002134                pdebug_init
+ .text.passert  0x0000000000002168       0x1c shared/util/pdebug.o
+                0x0000000000002168                passert
+ .text.__libc_init_array
+                0x0000000000002184       0x48 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-init.o)
+                0x0000000000002184                __libc_init_array
+ .text.memcpy   0x00000000000021cc       0x1c /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-memcpy-stub.o)
+                0x00000000000021cc                memcpy
+ .text.memset   0x00000000000021e8       0x10 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-memset.o)
+                0x00000000000021e8                memset
+ .text          0x00000000000021f8       0x10 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-strlen.o)
+                0x00000000000021f8                strlen
+ .text._vsprintf_r
+                0x0000000000002208       0x2c /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-vsprintf.o)
+                0x0000000000002208                _vsiprintf_r
+                0x0000000000002208                _vsprintf_r
+ .text.vsprintf
+                0x0000000000002234       0x14 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-vsprintf.o)
+                0x0000000000002234                vsprintf
+                0x0000000000002234                vsiprintf
+ .text.__retarget_lock_acquire_recursive
+                0x0000000000002248        0x2 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-lock.o)
+                0x0000000000002248                __retarget_lock_acquire_recursive
+ .text.__retarget_lock_release_recursive
+                0x000000000000224a        0x2 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-lock.o)
+                0x000000000000224a                __retarget_lock_release_recursive
+ .text._malloc_r
+                0x000000000000224c       0xb4 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-nano-mallocr.o)
+                0x000000000000224c                _malloc_r
+ .text.__ssputs_r
+                0x0000000000002300       0xb6 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-nano-svfprintf.o)
+                0x0000000000002300                __ssputs_r
+ *fill*         0x00000000000023b6        0x2 
+ .text._svfprintf_r
+                0x00000000000023b8      0x200 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-nano-svfprintf.o)
+                0x00000000000023b8                _svfprintf_r
+                0x00000000000023b8                _svfiprintf_r
+ .text._printf_common
+                0x00000000000025b8       0xda /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-nano-vfprintf_i.o)
+                0x00000000000025b8                _printf_common
+ *fill*         0x0000000000002692        0x2 
+ .text._printf_i
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+                0x0000000000002694                _printf_i
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+                0x00000000000028e0                _sbrk_r
+ .text          0x0000000000002900       0xa0 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-memchr.o)
+                0x0000000000002900                memchr
+ .text.memmove  0x00000000000029a0       0x34 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-memmove.o)
+                0x00000000000029a0                memmove
+ .text.__malloc_lock
+                0x00000000000029d4        0xc /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-mlock.o)
+                0x00000000000029d4                __malloc_lock
+ .text.__malloc_unlock
+                0x00000000000029e0        0xc /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-mlock.o)
+                0x00000000000029e0                __malloc_unlock
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+                0x00000000000029ec                _free_r
+ .text._realloc_r
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+                0x0000000000002a88                _realloc_r
+ .text._malloc_usable_size_r
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+                0x0000000000002ad4                _malloc_usable_size_r
+ *(.glue_7t)
+ .glue_7t       0x0000000000002ae4        0x0 linker stubs
+ *(.glue_7)
+ .glue_7        0x0000000000002ae4        0x0 linker stubs
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ .rodata.str1.1
+                0x0000000000002ae4       0x14 hal/src/hal_io.o
+ .rodata.str1.1
+                0x0000000000002af8       0x1a hal/src/hal_calendar.o
+ .rodata.str1.1
+                0x0000000000002b12       0xf7 sd_mmc/sd_mmc.o
+ *fill*         0x0000000000002c09        0x3 
+ .rodata        0x0000000000002c0c       0xbc sd_mmc/sd_mmc.o
+                0x0000000000002c2c                mmc_trans_multipliers
+                0x0000000000002c6c                sd_mmc_trans_units
+                0x0000000000002c88                sd_trans_multipliers
+ .rodata.str1.1
+                0x0000000000002cc8      0x257 sd_mmc/sd_mmc_spi.o
+                                        0x25b (size before relaxing)
+ .rodata        0x0000000000002f1f       0xc7 sd_mmc/sd_mmc_spi.o
+ .rodata.str1.1
+                0x0000000000002fe6       0x1c hal/src/hal_spi_m_sync.o
+ .rodata.str1.1
+                0x0000000000003002       0x1a hal/src/hal_mci_sync.o
+ .rodata.str1.1
+                0x000000000000301c       0x17 hpl/sdhc/hpl_sdhc.o
+ .rodata.str1.1
+                0x0000000000003033       0x1c hal/src/hal_usart_sync.o
+ .rodata.str1.1
+                0x000000000000304f        0xd main.o
+ .rodata.str1.1
+                0x000000000000305c       0x15 hpl/rtc/hpl_rtc.o
+ .rodata.str1.1
+                0x0000000000003071       0x1b hpl/sercom/hpl_sercom.o
+ .rodata        0x000000000000308c       0x49 hpl/sercom/hpl_sercom.o
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+OUTPUT(spi_sd_mmc_lib.elf elf32-littlearm)
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+ .debug_frame   0x0000000000002810       0x28 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-memcpy-stub.o)
+ .debug_frame   0x0000000000002838       0x20 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-memset.o)
+ .debug_frame   0x0000000000002858       0x3c /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-vsprintf.o)
+ .debug_frame   0x0000000000002894      0x14c /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-findfp.o)
+ .debug_frame   0x00000000000029e0       0xb0 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-lock.o)
+ .debug_frame   0x0000000000002a90       0x30 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-nano-mallocr.o)
+ .debug_frame   0x0000000000002ac0       0x90 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-nano-svfprintf.o)
+ .debug_frame   0x0000000000002b50       0x60 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-nano-vfprintf_i.o)
+ .debug_frame   0x0000000000002bb0       0x2c /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-sbrkr.o)
+ .debug_frame   0x0000000000002bdc       0x28 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-memmove.o)
+ .debug_frame   0x0000000000002c04       0x30 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-mlock.o)
+ .debug_frame   0x0000000000002c34       0x38 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-nano-freer.o)
+ .debug_frame   0x0000000000002c6c       0x3c /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-nano-reallocr.o)
+ .debug_frame   0x0000000000002ca8       0x5c /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-reent.o)
+ .debug_frame   0x0000000000002d04       0x20 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-nano-msizer.o)
diff --git a/config/conf_sd_mmc.h b/config/conf_sd_mmc.h
new file mode 100644
index 0000000..0627145
--- /dev/null
+++ b/config/conf_sd_mmc.h
@@ -0,0 +1,79 @@
+/* Auto-generated config file conf_sd_mmc.h */
+#ifndef CONF_SD_MMC_H
+#define CONF_SD_MMC_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <q> Enable the SDIO support
+// <id> conf_sdio_support
+#ifndef CONF_SDIO_SUPPORT
+#define CONF_SDIO_SUPPORT 1
+#endif
+
+// <q> Enable the MMC card support
+// <id> conf_mmc_support
+#ifndef CONF_MMC_SUPPORT
+#define CONF_MMC_SUPPORT 1
+#endif
+
+// <q> Enable the OS support
+// <id> conf_sd_mmc_os_support
+#ifndef CONF_OS_SUPPORT
+#define CONF_OS_SUPPORT 0
+#endif
+
+// Detection (card/write protect) timeout (ms/ticks)
+// conf_sd_mmc_debounce
+#ifndef CONF_SD_MMC_DEBOUNCE
+#define CONF_SD_MMC_DEBOUNCE 1000
+#endif
+
+#ifndef CONF_SD_MMC_MEM_CNT
+#define CONF_SD_MMC_MEM_CNT 1
+#endif
+
+// <e> SD/MMC Slot 0
+// <id> conf_sd_mmc_0_enable
+#ifndef CONF_SD_MMC_0_ENABLE
+#define CONF_SD_MMC_0_ENABLE 1
+#endif
+
+// <e> Card Detect (CD) 0 Enable
+// <id> conf_sd_mmc_0_cd_detect_en
+#ifndef CONF_SD_MMC_0_CD_DETECT_EN
+#define CONF_SD_MMC_0_CD_DETECT_EN 0
+#endif
+
+// <o> Card Detect (CD) detection level
+// <1=> High
+// <0=> Low
+// <id> conf_sd_mmc_0_cd_detect_value
+#ifndef CONF_SD_MMC_0_CD_DETECT_VALUE
+#define CONF_SD_MMC_0_CD_DETECT_VALUE 0
+#endif
+// </e>
+
+// <e> Write Protect (WP) 0 Enable
+// <id> conf_sd_mmc_0_wp_detect_en
+#ifndef CONF_SD_MMC_0_WP_DETECT_EN
+#define CONF_SD_MMC_0_WP_DETECT_EN 0
+#endif
+
+// <o> Write Protect (WP) detection level
+// <1=> High
+// <0=> Low
+// <id> conf_sd_mmc_0_wp_detect_value
+#ifndef CONF_SD_MMC_0_WP_DETECT_VALUE
+#define CONF_SD_MMC_0_WP_DETECT_VALUE 1
+#endif
+// </e>
+
+// </e>
+
+#ifndef CONF_MCI_OS_SUPPORT
+#define CONF_MCI_OS_SUPPORT 0
+#endif
+
+// <<< end of configuration section >>>
+
+#endif // CONF_SD_MMC_H
diff --git a/config/hpl_gclk_config.h b/config/hpl_gclk_config.h
index d3cc23c..72f4373 100644
--- a/config/hpl_gclk_config.h
+++ b/config/hpl_gclk_config.h
@@ -25,7 +25,7 @@
 // <i> This defines the clock source for generic clock generator 0
 // <id> gclk_gen_0_oscillator
 #ifndef CONF_GCLK_GEN_0_SOURCE
-#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_DFLL
+#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_DPLL0
 #endif
 
 // <q> Run in Standby
diff --git a/config/hpl_mclk_config.h b/config/hpl_mclk_config.h
index a5a7de5..4089d83 100644
--- a/config/hpl_mclk_config.h
+++ b/config/hpl_mclk_config.h
@@ -92,7 +92,7 @@
 // <15=> 15
 // <id> nvm_wait_states
 #ifndef CONF_NVM_WAIT_STATE
-#define CONF_NVM_WAIT_STATE 0
+#define CONF_NVM_WAIT_STATE 5
 #endif
 
 // </h>
diff --git a/config/hpl_osc32kctrl_config.h b/config/hpl_osc32kctrl_config.h
index 1ccc74f..1126a13 100644
--- a/config/hpl_osc32kctrl_config.h
+++ b/config/hpl_osc32kctrl_config.h
@@ -64,7 +64,7 @@
 // <0x6=>8000092us
 // <id> xosc32k_arch_startup
 #ifndef CONF_XOSC32K_STARTUP
-#define CONF_XOSC32K_STARTUP 0x0
+#define CONF_XOSC32K_STARTUP 0x3
 #endif
 
 // <q> On Demand Control
@@ -92,7 +92,7 @@
 // <i> Indicates whether 32kHz Output is enabled or not
 // <id> xosc32k_arch_en32k
 #ifndef CONF_XOSC32K_EN32K
-#define CONF_XOSC32K_EN32K 0
+#define CONF_XOSC32K_EN32K 1
 #endif
 
 // <q> Clock Switch Back
diff --git a/config/hpl_oscctrl_config.h b/config/hpl_oscctrl_config.h
index ac10a15..ca44181 100644
--- a/config/hpl_oscctrl_config.h
+++ b/config/hpl_oscctrl_config.h
@@ -234,7 +234,7 @@
 // <i> Indicates whether configuration for DFLL is enabled or not
 // <id> enable_dfll
 #ifndef CONF_DFLL_CONFIG
-#define CONF_DFLL_CONFIG 1
+#define CONF_DFLL_CONFIG 0
 #endif
 
 // <y> Reference Clock Source
@@ -261,7 +261,7 @@
 // <i> Indicates whether DFLL is enabled or not
 // <id> dfll_arch_enable
 #ifndef CONF_DFLL_ENABLE
-#define CONF_DFLL_ENABLE 1
+#define CONF_DFLL_ENABLE 0
 #endif
 
 // <q> On Demand Control
@@ -382,7 +382,7 @@
 // <i> Indicates whether configuration for FDPLL0 is enabled or not
 // <id> enable_fdpll0
 #ifndef CONF_FDPLL0_CONFIG
-#define CONF_FDPLL0_CONFIG 0
+#define CONF_FDPLL0_CONFIG 1
 #endif
 
 // <y> Reference Clock Source
@@ -412,7 +412,7 @@
 // <i> Indicates whether Digital Phase Locked Loop is enabled or not
 // <id> fdpll0_arch_enable
 #ifndef CONF_FDPLL0_ENABLE
-#define CONF_FDPLL0_ENABLE 0
+#define CONF_FDPLL0_ENABLE 1
 #endif
 
 // <q> On Demand Control
@@ -433,14 +433,14 @@
 // <i> Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
 // <id> fdpll0_ldrfrac
 #ifndef CONF_FDPLL0_LDRFRAC
-#define CONF_FDPLL0_LDRFRAC 0xd
+#define CONF_FDPLL0_LDRFRAC 0x1
 #endif
 
 // <o> Loop Divider Ratio Integer Part <0x0-0x1FFF>
 // <i> Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
 // <id> fdpll0_ldr
 #ifndef CONF_FDPLL0_LDR
-#define CONF_FDPLL0_LDR 0x5b7
+#define CONF_FDPLL0_LDR 0xe4d
 #endif
 
 // <o> Clock Divider <0x0-0x7FF>
@@ -467,7 +467,7 @@
 // <i> Indicates whether Lock Bypass is enabled or not
 // <id> fdpll0_arch_lbypass
 #ifndef CONF_FDPLL0_LBYPASS
-#define CONF_FDPLL0_LBYPASS 0
+#define CONF_FDPLL0_LBYPASS 1
 #endif
 
 // <o> Lock Time
diff --git a/config/hpl_rtc_config.h b/config/hpl_rtc_config.h
new file mode 100644
index 0000000..b1984c9
--- /dev/null
+++ b/config/hpl_rtc_config.h
@@ -0,0 +1,337 @@
+/* Auto-generated config file hpl_rtc_config.h */
+#ifndef HPL_RTC_CONFIG_H
+#define HPL_RTC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h> Basic settings
+
+#ifndef CONF_RTC_ENABLE
+#define CONF_RTC_ENABLE 1
+#endif
+
+// <q> Force reset RTC on initialization
+// <i> Force RTC to reset on initialization.
+// <i> Note that the previous power down data in RTC is lost if it's enabled.
+// <id> rtc_arch_init_reset
+#ifndef CONF_RTC_INIT_RESET
+#define CONF_RTC_INIT_RESET 1
+#endif
+
+// <o> Prescaler configuration
+// <0x0=>OFF(Peripheral clock divided by 1)
+// <0x1=>Peripheral clock divided by 1
+// <0x2=>Peripheral clock divided by 2
+// <0x3=>Peripheral clock divided by 4
+// <0x4=>Peripheral clock divided by 8
+// <0x5=>Peripheral clock divided by 16
+// <0x6=>Peripheral clock divided by 32
+// <0x7=>Peripheral clock divided by 64
+// <0x8=>Peripheral clock divided by 128
+// <0x9=>Peripheral clock divided by 256
+// <0xA=>Peripheral clock divided by 512
+// <0xB=>Peripheral clock divided by 1024
+// <i> These bits define the RTC clock relative to the peripheral clock
+// <id> rtc_arch_prescaler
+#ifndef CONF_RTC_PRESCALER
+
+#define CONF_RTC_PRESCALER 0x1
+
+#endif
+
+#ifndef CONF_RTC_COMP_VAL
+
+#define CONF_RTC_COMP_VAL 0
+
+#endif
+
+// <e> RTC Tamper Input 0 settings
+// <id> tamper_input_0_settings
+#ifndef CONF_TAMPER_INPUT_0_SETTINGS
+#define CONF_TAMPER_INPUT_0_SETTINGS 0
+#endif
+
+// <q> Tamper Level Settings
+// <i> Indicates Tamper input 0 level
+// <id> tamper_level_0
+#ifndef CONF_RTC_TAMP_LVL_0
+#define CONF_RTC_TAMP_LVL_0 0
+#endif
+
+// <o> RTC Tamper Input Action
+// <0x0=>OFF(Disabled)
+// <0x1=>Wake and Set Tamper Flag
+// <0x2=>Capture Timestamp and Set Tamper Flag
+// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured.
+// <i> These bits define the RTC Tamper Input Action to be performed
+// <id> rtc_tamper_input_action_0
+#ifndef CONF_RTC_TAMPER_INACT_0
+#define CONF_RTC_TAMPER_INACT_0 0
+#endif
+
+// <q> Debounce Enable for Tamper Input
+// <i> Indicates Debounce should be enabled for Tamper input 0
+// <id> tamper_debounce_enable_0
+#ifndef CONF_RTC_TAMP_DEBNC_0
+#define CONF_RTC_TAMP_DEBNC_0 0
+#endif
+
+// </e>
+
+// <e> RTC Tamper Input 1 settings
+// <id> tamper_input_1_settings
+#ifndef CONF_TAMPER_INPUT_1_SETTINGS
+#define CONF_TAMPER_INPUT_1_SETTINGS 0
+#endif
+
+// <q> Tamper Level Settings
+// <i> Indicates Tamper input 1 level
+// <id> tamper_level_1
+#ifndef CONF_RTC_TAMP_LVL_1
+#define CONF_RTC_TAMP_LVL_1 0
+#endif
+
+// <o> RTC Tamper Input Action
+// <0x0=>OFF(Disabled)
+// <0x1=>Wake and Set Tamper Flag
+// <0x2=>Capture Timestamp and Set Tamper Flag
+// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured.
+// <i> These bits define the RTC Tamper Input Action to be performed
+// <id> rtc_tamper_input_action_1
+#ifndef CONF_RTC_TAMPER_INACT_1
+#define CONF_RTC_TAMPER_INACT_1 0
+#endif
+
+// <q> Debounce Enable for Tamper Input
+// <i> Indicates Debounce should be enabled for Tamper input 1
+// <id> tamper_debounce_enable_1
+#ifndef CONF_RTC_TAMP_DEBNC_1
+#define CONF_RTC_TAMP_DEBNC_1 0
+#endif
+
+// </e>
+
+// <e> RTC Tamper Input 2 settings
+// <id> tamper_input_2_settings
+#ifndef CONF_TAMPER_INPUT_2_SETTINGS
+#define CONF_TAMPER_INPUT_2_SETTINGS 0
+#endif
+
+// <q> Tamper Level Settings
+// <i> Indicates Tamper input 2 level
+// <id> tamper_level_2
+#ifndef CONF_RTC_TAMP_LVL_2
+#define CONF_RTC_TAMP_LVL_2 0
+#endif
+
+// <o> RTC Tamper Input Action
+// <0x0=>OFF(Disabled)
+// <0x1=>Wake and Set Tamper Flag
+// <0x2=>Capture Timestamp and Set Tamper Flag
+// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured.
+// <i> These bits define the RTC Tamper Input Action to be performed
+// <id> rtc_tamper_input_action_2
+#ifndef CONF_RTC_TAMPER_INACT_2
+#define CONF_RTC_TAMPER_INACT_2 0
+#endif
+
+// <q> Debounce Enable for Tamper Input
+// <i> Indicates Debounce should be enabled for Tamper input 2
+// <id> tamper_debounce_enable_2
+#ifndef CONF_RTC_TAMP_DEBNC_2
+#define CONF_RTC_TAMP_DEBNC_2 0
+#endif
+
+// </e>
+
+// <e> RTC Tamper Input 3 settings
+// <id> tamper_input_3_settings
+#ifndef CONF_TAMPER_INPUT_3_SETTINGS
+#define CONF_TAMPER_INPUT_3_SETTINGS 0
+#endif
+
+// <q> Tamper Level Settings
+// <i> Indicates Tamper input 3 level
+// <id> tamper_level_3
+#ifndef CONF_RTC_TAMP_LVL_3
+#define CONF_RTC_TAMP_LVL_3 0
+#endif
+
+// <o> RTC Tamper Input Action
+// <0x0=>OFF(Disabled)
+// <0x1=>Wake and Set Tamper Flag
+// <0x2=>Capture Timestamp and Set Tamper Flag
+// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured.
+// <i> These bits define the RTC Tamper Input Action to be performed
+// <id> rtc_tamper_input_action_3
+#ifndef CONF_RTC_TAMPER_INACT_3
+#define CONF_RTC_TAMPER_INACT_3 0
+#endif
+
+// <q> Debounce Enable for Tamper Input
+// <i> Indicates Debounce should be enabled for Tamper input 3
+// <id> tamper_debounce_enable_3
+#ifndef CONF_RTC_TAMP_DEBNC_3
+#define CONF_RTC_TAMP_DEBNC_3 0
+#endif
+
+// </e>
+
+// <e> RTC Tamper Input 4 settings
+// <id> tamper_input_4_settings
+#ifndef CONF_TAMPER_INPUT_4_SETTINGS
+#define CONF_TAMPER_INPUT_4_SETTINGS 0
+#endif
+
+// <q> Tamper Level Settings
+// <i> Indicates Tamper input 4 level
+// <id> tamper_level_4
+#ifndef CONF_RTC_TAMP_LVL_4
+#define CONF_RTC_TAMP_LVL_4 0
+#endif
+
+// <o> RTC Tamper Input Action
+// <0x0=>OFF(Disabled)
+// <0x1=>Wake and Set Tamper Flag
+// <0x2=>Capture Timestamp and Set Tamper Flag
+// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured.
+// <i> These bits define the RTC Tamper Input Action to be performed
+// <id> rtc_tamper_input_action_4
+#ifndef CONF_RTC_TAMPER_INACT_4
+#define CONF_RTC_TAMPER_INACT_4 0
+#endif
+
+// <q> Debounce Enable for Tamper Input
+// <i> Indicates Debounce should be enabled for Tamper input 4
+// <id> tamper_debounce_enable_4
+#ifndef CONF_RTC_TAMP_DEBNC_4
+#define CONF_RTC_TAMP_DEBNC_4 0
+#endif
+
+// </e>
+
+// <o> RTC Tamper Active Layer Frequency Prescalar
+// <0x0=>DIV2 CLK_RTC_OUT is CLK_RTC /2
+// <0x1=>DIV4 CLK_RTC_OUT is CLK_RTC /4
+// <0x2=>DIV8 CLK_RTC_OUT is CLK_RTC /8
+// <0x3=>DIV16 CLK_RTC_OUT is CLK_RTC /16
+// <0x4=>DIV32 CLK_RTC_OUT is CLK_RTC /32
+// <0x5=>DIV64 CLK_RTC_OUT is CLK_RTC /64
+// <0x6=>DIV128 CLK_RTC_OUT is CLK_RTC /128
+// <0x7=>DIV256 CLK_RTC_OUT is CLK_RTC /256
+// <i> These bits define the RTC Tamper Active Layer Frequecny Prescalar
+// <id> rtc_tamper_active_layer_frequency_prescalar
+#ifndef CONF_RTC_TAMP_ACT_LAYER_FREQ_PRES
+#define CONF_RTC_TAMP_ACT_LAYER_FREQ_PRES 0
+#endif
+
+// <o> RTC Tamper Debounce Frequency Prescalar
+// <0x0=>DIV2 CLK_RTC_DEB is CLK_RTC /2
+// <0x1=>DIV4 CLK_RTC_DEB is CLK_RTC /4
+// <0x2=>DIV8 CLK_RTC_DEB is CLK_RTC /8
+// <0x3=>DIV16 CLK_RTC_DEB is CLK_RTC /16
+// <0x4=>DIV32 CLK_RTC_DEB is CLK_RTC /32
+// <0x5=>DIV64 CLK_RTC_DEB is CLK_RTC /64
+// <0x6=>DIV128 CLK_RTC_DEB is CLK_RTC /128
+// <0x7=>DIV256 CLK_RTC_DEB is CLK_RTC /256
+// <i> These bits define the RTC Debounce Frequency Prescalar
+// <id> rtc_tamper_debounce_frequency_prescalar
+#ifndef CONF_RTC_TAMP_DEBF_PRES
+#define CONF_RTC_TAMP_DEBF_PRES 0
+#endif
+
+// <e> Event control
+// <id> rtc_event_control
+#ifndef CONF_RTC_EVENT_CONTROL_ENABLE
+#define CONF_RTC_EVENT_CONTROL_ENABLE 0
+#endif
+
+// <q> Periodic Interval 0 Event Output
+// <i> This bit indicates whether Periodic interval 0 event is enabled and will be generated
+// <id> rtc_pereo0
+#ifndef CONF_RTC_PEREO0
+#define CONF_RTC_PEREO0 0
+#endif
+// <q> Periodic Interval 1 Event Output
+// <i> This bit indicates whether Periodic interval 1 event is enabled and will be generated
+// <id> rtc_pereo1
+#ifndef CONF_RTC_PEREO1
+#define CONF_RTC_PEREO1 0
+#endif
+// <q> Periodic Interval 2 Event Output
+// <i> This bit indicates whether Periodic interval 2 event is enabled and will be generated
+// <id> rtc_pereo2
+#ifndef CONF_RTC_PEREO2
+#define CONF_RTC_PEREO2 0
+#endif
+// <q> Periodic Interval 3 Event Output
+// <i> This bit indicates whether Periodic interval 3 event is enabled and will be generated
+// <id> rtc_pereo3
+#ifndef CONF_RTC_PEREO3
+#define CONF_RTC_PEREO3 0
+#endif
+// <q> Periodic Interval 4 Event Output
+// <i> This bit indicates whether Periodic interval 4 event is enabled and will be generated
+// <id> rtc_pereo4
+#ifndef CONF_RTC_PEREO4
+#define CONF_RTC_PEREO4 0
+#endif
+// <q> Periodic Interval 5 Event Output
+// <i> This bit indicates whether Periodic interval 5 event is enabled and will be generated
+// <id> rtc_pereo5
+#ifndef CONF_RTC_PEREO5
+#define CONF_RTC_PEREO5 0
+#endif
+// <q> Periodic Interval 6 Event Output
+// <i> This bit indicates whether Periodic interval 6 event is enabled and will be generated
+// <id> rtc_pereo6
+#ifndef CONF_RTC_PEREO6
+#define CONF_RTC_PEREO6 0
+#endif
+// <q> Periodic Interval 7 Event Output
+// <i> This bit indicates whether Periodic interval 7 event is enabled and will be generated
+// <id> rtc_pereo7
+#ifndef CONF_RTC_PEREO7
+#define CONF_RTC_PEREO7 0
+#endif
+
+// <q> Compare 0 Event Output
+// <i> This bit indicates whether Compare O event is enabled and will be generated
+// <id> rtc_cmpeo0
+#ifndef CONF_RTC_COMPE0
+#define CONF_RTC_COMPE0 0
+#endif
+
+// <q> Compare 1 Event Output
+// <i> This bit indicates whether Compare 1 event is enabled and will be generated
+// <id> rtc_cmpeo1
+#ifndef CONF_RTC_COMPE1
+#define CONF_RTC_COMPE1 0
+#endif
+// <q> Overflow Event Output
+// <i> This bit indicates whether Overflow event is enabled and will be generated
+// <id> rtc_ovfeo
+#ifndef CONF_RTC_OVFEO
+#define CONF_RTC_OVFEO 0
+#endif
+
+// <q> Tamper Event Output
+// <i> This bit indicates whether Tamper event output is enabled and will be generated
+// <id> rtc_tampereo
+#ifndef CONF_RTC_TAMPEREO
+#define CONF_RTC_TAMPEREO 0
+#endif
+
+// <q> Tamper Event Input
+// <i> This bit indicates whether Tamper event input is enabled and will be generated
+// <id> rtc_tampevei
+#ifndef CONF_RTC_TAMPEVEI
+#define CONF_RTC_TAMPEVEI 0
+#endif
+// </e>
+
+// </h>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_RTC_CONFIG_H
diff --git a/config/hpl_sdhc_config.h b/config/hpl_sdhc_config.h
new file mode 100644
index 0000000..daa6620
--- /dev/null
+++ b/config/hpl_sdhc_config.h
@@ -0,0 +1,24 @@
+/* Auto-generated config file hpl_sdhc_config.h */
+#ifndef HPL_SDHC_CONFIG_H
+#define HPL_SDHC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#include "peripheral_clk_config.h"
+
+#ifndef CONF_BASE_FREQUENCY
+#define CONF_BASE_FREQUENCY CONF_SDHC0_FREQUENCY
+#endif
+
+// <o> Clock Generator Select
+// <0=> Divided Clock mode
+// <1=> Programmable Clock mode
+// <i> This defines the clock generator mode in the SDCLK Frequency Select field
+// <id> sdhc_clk_gsel
+#ifndef CONF_SDHC0_CLK_GEN_SEL
+#define CONF_SDHC0_CLK_GEN_SEL 0
+#endif
+
+// <<< end of configuration section >>>
+
+#endif // HPL_SDHC_CONFIG_H
diff --git a/config/peripheral_clk_config.h b/config/peripheral_clk_config.h
index 09ddc7a..7ace024 100644
--- a/config/peripheral_clk_config.h
+++ b/config/peripheral_clk_config.h
@@ -9,7 +9,23 @@
  * \brief CPU's Clock frequency
  */
 #ifndef CONF_CPU_FREQUENCY
-#define CONF_CPU_FREQUENCY 48005120
+#define CONF_CPU_FREQUENCY 119997440
+#endif
+
+// <y> RTC Clock Source
+// <id> rtc_clk_selection
+// <RTC_CLOCK_SOURCE"> RTC source
+// <i> Select the clock source for RTC.
+#ifndef CONF_GCLK_RTC_SRC
+#define CONF_GCLK_RTC_SRC RTC_CLOCK_SOURCE
+#endif
+
+/**
+ * \def CONF_GCLK_RTC_FREQUENCY
+ * \brief RTC's Clock frequency
+ */
+#ifndef CONF_GCLK_RTC_FREQUENCY
+#define CONF_GCLK_RTC_FREQUENCY 32768
 #endif
 
 // <y> Core Clock Source
@@ -81,7 +97,7 @@
  * \brief SERCOM2's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 48005120
+#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 119997440
 #endif
 
 /**
@@ -161,7 +177,7 @@
  * \brief SERCOM4's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM4_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM4_CORE_FREQUENCY 48005120
+#define CONF_GCLK_SERCOM4_CORE_FREQUENCY 119997440
 #endif
 
 /**
@@ -172,6 +188,88 @@
 #define CONF_GCLK_SERCOM4_SLOW_FREQUENCY 32768
 #endif
 
+// <h> SDHC Clock Settings
+// <y> SDHC Clock source
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for SDHC.
+// <id> sdhc_gclk_selection
+#ifndef CONF_GCLK_SDHC0_SRC
+#define CONF_GCLK_SDHC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+// <y> SDHC clock slow source
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for SDHC.
+// <id> sdhc_slow_gclk_selection
+#ifndef CONF_GCLK_SDHC0_SLOW_SRC
+#define CONF_GCLK_SDHC0_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+// </h>
+
+/**
+ * \def SDHC FREQUENCY
+ * \brief SDHC's Clock frequency
+ */
+#ifndef CONF_SDHC0_FREQUENCY
+#define CONF_SDHC0_FREQUENCY 119997440
+#endif
+
+/**
+ * \def SDHC FREQUENCY
+ * \brief SDHC's Clock slow frequency
+ */
+#ifndef CONF_SDHC0_SLOW_FREQUENCY
+#define CONF_SDHC0_SLOW_FREQUENCY 119997440
+#endif
+
 // <<< end of configuration section >>>
 
 #endif // PERIPHERAL_CLK_CONFIG_H
diff --git a/diskio/diskio.h b/diskio/diskio.h
new file mode 100644
index 0000000..e57e961
--- /dev/null
+++ b/diskio/diskio.h
@@ -0,0 +1,200 @@
+/**
+ * \file
+ *
+ * \brief diskio.h
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef _DISKIO_DEFINED
+#define _DISKIO_DEFINED
+
+#include "stdint.h"
+#include <err_codes.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Definitions of physical drive number for each drive */
+#define DISKIO_ATA 0 /* Example: Map ATA harddisk to physical drive 0 */
+#define DISKIO_MMC 1 /* Example: Map MMC/SD card to physical drive 1 */
+#define DISKIO_USB 2 /* Example: Map USB MSD to physical drive 2 */
+
+/* Disk Status Bits (DSTATUS) */
+#define STA_NOINIT 0x01  /* Drive not initialized */
+#define STA_NODISK 0x02  /* No medium in the drive */
+#define STA_PROTECT 0x04 /* Write protected */
+
+/* Generic command (defined for FatFs) */
+#define CTRL_SYNC 0         /* Flush disk cache (for write functions) */
+#define GET_SECTOR_COUNT 1  /* Get media size (for only f_mkfs()) */
+#define GET_SECTOR_SIZE 2   /* Get sector size (for multiple sector size (_MAX_SS >= 1024)) */
+#define GET_BLOCK_SIZE 3    /* Get erase block size (for only f_mkfs()) */
+#define CTRL_ERASE_SECTOR 4 /* Force erased a block of sectors (for only _USE_ERASE) */
+
+/* Generic command */
+#define CTRL_POWER 5 /* Get/Set power status */
+#define CTRL_LOCK 6  /* Lock/Unlock media removal */
+#define CTRL_EJECT 7 /* Eject media */
+
+/* MMC/SDC specific ioctl command */
+#define MMC_GET_TYPE 10   /* Get card type */
+#define MMC_GET_CSD 11    /* Get CSD */
+#define MMC_GET_CID 12    /* Get CID */
+#define MMC_GET_OCR 13    /* Get OCR */
+#define MMC_GET_SDSTAT 14 /* Get SD status */
+
+/* ATA/CF specific ioctl command */
+#define ATA_GET_REV 20   /* Get F/W revision */
+#define ATA_GET_MODEL 21 /* Get model name */
+#define ATA_GET_SN 22    /* Get serial number */
+
+/* NAND specific ioctl command */
+#define NAND_FORMAT 30 /* Create physical format */
+
+/* Status of Disk Functions */
+typedef uint8_t   dstatus_t;
+typedef dstatus_t DSTATUS; /* DSTATUS is referred in ff.c the original open source fatfs code  */
+
+/* Results of Disk Functions */
+typedef enum {
+	RES_OK = 0, /* 0: Successful */
+	RES_ERROR,  /* 1: R/W Error */
+	RES_WRPRT,  /* 2: Write Protected */
+	RES_NOTRDY, /* 3: Not Ready */
+	RES_PARERR  /* 4: Invalid Parameter */
+} dresult_t;
+
+#ifndef SECTOR_SIZE
+#define SECTOR_SIZE 512
+#endif
+
+/** Default sector size */
+#define SECTOR_SIZE_DEFAULT 512
+
+/** Supported sector size. These values are based on the LUN function:
+ * mem_sector_size(). */
+#define SECTOR_SIZE_512 1
+#define SECTOR_SIZE_1024 2
+#define SECTOR_SIZE_2048 4
+#define SECTOR_SIZE_4096 8
+
+//! Status returned by CTRL_ACCESS interfaces.
+typedef enum {
+	CTRL_GOOD       = 0,             //!< Success, memory ready.
+	CTRL_FAIL       = CTRL_GOOD + 1, //!< An error occurred.
+	CTRL_NO_PRESENT = CTRL_GOOD + 2, //!< Memory unplugged.
+	CTRL_BUSY       = CTRL_GOOD + 3  //!< Memory not initialized or changed.
+} ctrl_status_t;
+
+/**
+ * \brief  Return disk status.
+ *
+ * \param drv Physical drive number (0..).
+ *
+ * \return 0 or disk status in combination of DSTATUS bits
+ *         (STA_NOINIT, STA_NODISK, STA_PROTECT).
+ *
+ */
+dstatus_t disk_status(uint8_t drv);
+
+/**
+ * \brief Initialize a disk.
+ *
+ * \param drv Physical drive number (0..).
+ *
+ * \return 0 or disk status in combination of DSTATUS bits
+ *         (STA_NOINIT, STA_PROTECT).
+ */
+dstatus_t disk_initialize(uint8_t drv);
+
+/**
+ * \brief  Read sector(s).
+ *
+ * \param drv Physical drive number (0..).
+ * \param buff Data buffer to store read data.
+ * \param sector Sector address (LBA).
+ * \param count Number of sectors to read (1..255).
+ *
+ * \return RES_OK for success, otherwise DRESULT error code.
+ */
+dstatus_t disk_read(uint8_t drv, uint8_t *buff, uint32_t sector, uint8_t count);
+
+/**
+ * \brief  Write sector(s).
+ *
+ * The FatFs module will issue multiple sector transfer request (count > 1) to
+ * the disk I/O layer. The disk function should process the multiple sector
+ * transfer properly. Do not translate it into multiple sector transfers to the
+ * media, or the data read/write performance may be drastically decreased.
+ *
+ * \param drv Physical drive number (0..).
+ * \param buff Data buffer to store read data.
+ * \param sector Sector address (LBA).
+ * \param count Number of sectors to read (1..255).
+ *
+ * \return RES_OK for success, otherwise DRESULT error code.
+ */
+dstatus_t disk_write(uint8_t drv, uint8_t const *buff, uint32_t sector, uint8_t count);
+
+/**
+ * \brief  Miscellaneous functions, which support the following commands:
+ *
+ * CTRL_SYNC    Make sure that the disk drive has finished pending write
+ * process. When the disk I/O module has a write back cache, flush the
+ * dirty sector immediately.
+ * In read-only configuration, this command is not needed.
+ *
+ * GET_SECTOR_COUNT    Return total sectors on the drive into the DWORD variable
+ * pointed by buffer.
+ * This command is used only in f_mkfs function.
+ *
+ * GET_BLOCK_SIZE    Return erase block size of the memory array in unit
+ * of sector into the DWORD variable pointed by Buffer.
+ * When the erase block size is unknown or magnetic disk device, return 1.
+ * This command is used only in f_mkfs function.
+ *
+ * GET_SECTOR_SIZE    Return sector size of the memory array.
+ *
+ * \param drv Physical drive number (0..).
+ * \param ctrl Control code.
+ * \param buff Buffer to send/receive control data.
+ *
+ * \return RES_OK for success, otherwise DRESULT error code.
+ */
+dstatus_t disk_ioctl(uint8_t drv, uint8_t ctrl, void *buff);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/diskio/sdmmc_diskio.c b/diskio/sdmmc_diskio.c
new file mode 100644
index 0000000..b453220
--- /dev/null
+++ b/diskio/sdmmc_diskio.c
@@ -0,0 +1,341 @@
+/**
+ * \file
+ *
+ * \brief Common SDMMC Diskio implementation
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#include <sd_mmc.h>
+#include "diskio.h"
+
+/*
+ * \brief Verify SD/MMC is ready to use.
+ *
+ * \param slot slot number (0..).
+ *
+ * \return CTRL_GOOD or card status like CTRL_NO_PRESENT, CTRL_BUSY, CTRL_FAIL.
+ *
+ */
+static ctrl_status_t sd_mmc_test_unit_ready(uint8_t slot)
+{
+	switch (sd_mmc_check(slot)) {
+	case SD_MMC_OK:
+		if (sd_mmc_get_type(slot) & (CARD_TYPE_SD | CARD_TYPE_MMC)) {
+			return CTRL_GOOD;
+		} else // It is not a memory card
+			return CTRL_NO_PRESENT;
+	case SD_MMC_INIT_ONGOING:
+		return CTRL_BUSY;
+
+	case SD_MMC_ERR_NO_CARD:
+		return CTRL_NO_PRESENT;
+	default:
+		return CTRL_FAIL;
+	}
+}
+
+/*
+ * \brief Reads the memory capacity.
+ *
+ * \param slot slot number (0..).
+ * \param nb_sector pointer to hold the size.
+ *
+ * \return CTRL_GOOD or card status like CTRL_NO_PRESENT, CTRL_BUSY, CTRL_FAIL.
+ *
+ */
+static ctrl_status_t sd_mmc_read_capacity(uint8_t slot, uint32_t *nb_sector)
+{
+	// Return last sector address (-1)
+	*nb_sector = (sd_mmc_get_capacity(slot) * 2) - 1;
+	return sd_mmc_test_unit_ready(slot);
+}
+
+/*
+ * \brief Copy data from SD/MMC to RAM.
+ *
+ * \param slot slot number (0..).
+ * \param addr address of memory location.
+ * \param ram  buffer to hold the data for single block(512).
+ *
+ * \return CTRL_GOOD or card status like CTRL_NO_PRESENT, CTRL_FAIL
+ *
+ */
+static ctrl_status_t sd_mmc_mem_2_ram(uint8_t slot, uint32_t addr, void *ram)
+{
+	switch (sd_mmc_init_read_blocks(slot, addr, 1)) {
+	case SD_MMC_OK: {
+		if (SD_MMC_OK != sd_mmc_start_read_blocks(ram, 1))
+			return CTRL_FAIL;
+
+		if (SD_MMC_OK != sd_mmc_wait_end_of_read_blocks(false))
+			return CTRL_FAIL;
+		break;
+	}
+	case SD_MMC_ERR_NO_CARD:
+		return CTRL_NO_PRESENT;
+	default:
+		return CTRL_FAIL;
+	}
+	return CTRL_GOOD;
+}
+
+/*
+ * \brief Copy data from RAM to SD/MMC.
+ *
+ * \param slot slot number (0..).
+ * \param addr address of memory location.
+ * \param ram  buffer to hold the data for single block(512).
+ *
+ * \return CTRL_GOOD or card status like CTRL_NO_PRESENT, CTRL_FAIL
+ *
+ */
+static ctrl_status_t sd_mmc_ram_2_mem(uint8_t slot, uint32_t addr, const void *ram)
+{
+	switch (sd_mmc_init_write_blocks(slot, addr, 1)) {
+	case SD_MMC_OK: {
+		if (SD_MMC_OK != sd_mmc_start_write_blocks(ram, 1))
+			return CTRL_FAIL;
+
+		if (SD_MMC_OK != sd_mmc_wait_end_of_write_blocks(false))
+			return CTRL_FAIL;
+		break;
+	}
+	case SD_MMC_ERR_NO_CARD:
+		return CTRL_NO_PRESENT;
+	default:
+		return CTRL_FAIL;
+	}
+
+	return CTRL_GOOD;
+}
+
+/**
+ * \brief Initialize a disk.
+ *
+ * \param drv Physical drive number (0..).
+ *
+ * \return 0 or disk status in combination of DSTATUS bits
+ *         (STA_NOINIT, STA_PROTECT).
+ */
+dstatus_t disk_initialize(uint8_t drv)
+{
+	int           i;
+	ctrl_status_t mem_status;
+
+	/* Check LUN ready (USB disk report CTRL_BUSY then CTRL_GOOD) */
+	for (i = 0; i < 2; i++) {
+		mem_status = sd_mmc_test_unit_ready(drv);
+		if (CTRL_BUSY != mem_status) {
+			break;
+		}
+	}
+	if (mem_status != CTRL_GOOD) {
+		return STA_NOINIT;
+	}
+
+	/* Check Write Protection Status */
+	if (sd_mmc_is_write_protected(drv)) {
+		return STA_PROTECT;
+	}
+
+	/* The memory should already be initialized */
+	return 0;
+}
+
+/**
+ * \brief  Return disk status.
+ *
+ * \param drv Physical drive number (0..).
+ *
+ * \return 0 or disk status in combination of DSTATUS bits
+ *         (STA_NOINIT, STA_NODISK, STA_PROTECT).
+ */
+dstatus_t disk_status(uint8_t drv)
+{
+	switch (sd_mmc_test_unit_ready(drv)) {
+	case CTRL_GOOD:
+		return ERR_NONE;
+	case CTRL_NO_PRESENT:
+		return STA_NOINIT | STA_NODISK;
+	default:
+		return STA_NOINIT;
+	}
+}
+
+/**
+ * \brief  Read sector(s).
+ *
+ * \param drv Physical drive number (0..).
+ * \param buff Data buffer to store read data.
+ * \param sector Sector address (LBA).
+ * \param count Number of sectors to read (1..255).
+ *
+ * \return ERR_NONE for success, otherwise DRESULT error code.
+ */
+dstatus_t disk_read(uint8_t drv, uint8_t *buff, uint32_t sector, uint8_t count)
+{
+	uint8_t  uc_sector_size = SECTOR_SIZE_512;
+	uint32_t i;
+	uint32_t ul_last_sector_num;
+
+	/* Check valid address */
+	sd_mmc_read_capacity(drv, &ul_last_sector_num);
+	if ((sector + count * uc_sector_size) > (ul_last_sector_num + 1) * uc_sector_size) {
+		return ERR_INVALID_ARG;
+	}
+
+	/* Read the data */
+	for (i = 0; i < count; i++) {
+		if (sd_mmc_mem_2_ram(drv, sector + uc_sector_size * i, buff + uc_sector_size * SECTOR_SIZE_DEFAULT * i)
+		    != CTRL_GOOD) {
+			return ERR_INVALID_DATA;
+		}
+	}
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief  Write sector(s).
+ *
+ * The FatFs module will issue multiple sector transfer request (count > 1) to
+ * the disk I/O layer. The disk function should process the multiple sector
+ * transfer properly. Do not translate it into multiple sector transfers to the
+ * media, or the data read/write performance may be drastically decreased.
+ *
+ * \param drv Physical drive number (0..).
+ * \param buff Data buffer to store read data.
+ * \param sector Sector address (LBA).
+ * \param count Number of sectors to read (1..255).
+ *
+ * \return ERR_NONE for success, otherwise DRESULT error code.
+ */
+dstatus_t disk_write(uint8_t drv, uint8_t const *buff, uint32_t sector, uint8_t count)
+{
+	uint8_t  uc_sector_size = SECTOR_SIZE_512;
+	uint32_t i;
+	uint32_t ul_last_sector_num;
+
+	/* Check valid address */
+	sd_mmc_read_capacity(drv, &ul_last_sector_num);
+	if ((sector + count * uc_sector_size) > (ul_last_sector_num + 1) * uc_sector_size) {
+		return ERR_INVALID_ARG;
+	}
+
+	/* Write the data */
+	for (i = 0; i < count; i++) {
+		if (sd_mmc_ram_2_mem(drv, sector + uc_sector_size * i, buff + uc_sector_size * SECTOR_SIZE_DEFAULT * i)
+		    != CTRL_GOOD) {
+			return ERR_INVALID_DATA;
+		}
+	}
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief  Miscellaneous functions, which support the following commands:
+ *
+ * CTRL_SYNC    Make sure that the disk drive has finished pending write
+ * process. When the disk I/O module has a write back cache, flush the
+ * dirty sector immediately.
+ * In read-only configuration, this command is not needed.
+ *
+ * GET_SECTOR_COUNT    Return total sectors on the drive into the DWORD variable
+ * pointed by buffer.
+ * This command is used only in f_mkfs function.
+ *
+ * GET_BLOCK_SIZE    Return erase block size of the memory array in unit
+ * of sector into the DWORD variable pointed by Buffer.
+ * When the erase block size is unknown or magnetic disk device, return 1.
+ * This command is used only in f_mkfs function.
+ *
+ * GET_SECTOR_SIZE    Return sector size of the memory array.
+ *
+ * \param drv Physical drive number (0..).
+ * \param ctrl Control code.
+ * \param buff Buffer to send/receive control data.
+ *
+ * \return ERR_NONE for success, otherwise DRESULT error code.
+ */
+dstatus_t disk_ioctl(uint8_t drv, uint8_t ctrl, void *buff)
+{
+	dstatus_t res = ERR_INVALID_ARG;
+
+	switch (ctrl) {
+	case GET_BLOCK_SIZE:
+		*(unsigned long *)buff = 1;
+		res                    = ERR_NONE;
+		break;
+
+	/* Get the number of sectors on the disk */
+	case GET_SECTOR_COUNT: {
+		uint32_t ul_last_sector_num;
+
+		/* Check valid address */
+		sd_mmc_read_capacity(drv, &ul_last_sector_num);
+
+		*(unsigned long *)buff = ul_last_sector_num + 1;
+
+		res = ERR_NONE;
+	} break;
+
+	/* Get sectors on the disk (WORD) */
+	case GET_SECTOR_SIZE: {
+		uint8_t uc_sector_size = SECTOR_SIZE_512;
+
+		if ((uc_sector_size != SECTOR_SIZE_512) && (uc_sector_size != SECTOR_SIZE_1024)
+		    && (uc_sector_size != SECTOR_SIZE_2048) && (uc_sector_size != SECTOR_SIZE_4096)) {
+			/* The sector size is not supported by the FatFS */
+			return ERR_INVALID_DATA;
+		}
+
+		*(uint8_t *)buff = uc_sector_size * SECTOR_SIZE_DEFAULT;
+
+		res = ERR_NONE;
+	} break;
+
+	/* Make sure that data has been written */
+	case CTRL_SYNC:
+		if (sd_mmc_test_unit_ready(drv) == CTRL_GOOD) {
+			res = ERR_NONE;
+		} else {
+			res = ERR_NOT_READY;
+		}
+		break;
+
+	default:
+		res = ERR_INVALID_ARG;
+	}
+
+	return res;
+}
diff --git a/diskio_start.c b/diskio_start.c
new file mode 100644
index 0000000..ae172a0
--- /dev/null
+++ b/diskio_start.c
@@ -0,0 +1,13 @@
+/*
+ * Code generated from Atmel Start.
+ *
+ * This file will be overwritten when reconfiguring your Atmel Start project.
+ * Please copy examples or other code you want to keep to a separate file or main.c
+ * to avoid loosing it when reconfiguring.
+ */
+
+#include "diskio_start.h"
+
+void diskio_init(void)
+{
+}
diff --git a/diskio_start.h b/diskio_start.h
new file mode 100644
index 0000000..06c38f4
--- /dev/null
+++ b/diskio_start.h
@@ -0,0 +1,26 @@
+/*
+ * Code generated from Atmel Start.
+ *
+ * This file will be overwritten when reconfiguring your Atmel Start project.
+ * Please copy examples or other code you want to keep to a separate file or main.c
+ * to avoid loosing it when reconfiguring.
+ */
+#ifndef DISKIO_START_H
+#define DISKIO_START_H
+
+#include <atmel_start.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif // __cplusplus
+
+/**
+ * \berif Initialize DISKIO
+ */
+void diskio_init(void);
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif // DISKIO_START_H
diff --git a/documentation/diskio_sdmmc.rst b/documentation/diskio_sdmmc.rst
new file mode 100644
index 0000000..560951d
--- /dev/null
+++ b/documentation/diskio_sdmmc.rst
@@ -0,0 +1,59 @@
+DISK IO
+=======
+Disk IO provides common disk access interfaces for different storage medias
+It supports widely used disk access APIs like initialize/read/write/status etc.
+
+Storage Media
+-------------
+
+The different storage media can be SD/MMC, USB, Flash etc.
+Storage media has the dependency to the low level driver modules.
+
+
+Dependencies
+------------
+
+::
+
+         DISKIO
+           |
+           |
+         SD/MMC
+           |
+           |
+          MCI
+
+* SD/MMC media accessor
+* Peripheral that supports multimedia card interface (MCI)
+
+API Example
+------------
+
+::
+
+	dstatus_t status;
+	dresult_t res;
+	status = disk_initialize( 0 /*drv*/);
+	if(0 == status){
+		uint8_t buffer[10]="Sample Data";
+		status = disk_status(0);
+		switch(status){
+		case 0:
+			res = disk_write(0 /*drv*/, buffer, 7 /*Sector*/, 512 /*count*/);
+			if(RES_OK == res){
+				res = disk_read(0 /*drv*/, buffer, 7 /*Sector*/, 512 /*count*/);
+				if(RES_OK == res)
+					return 0;
+			}
+			break;
+		case STA_NODISK:
+			//Disk not preset, Note that FatFs does not refer this flag
+			break;
+		case STA_NOINIT:
+			//Disk init failed
+			break;
+		case STA_PROTECT:
+			//Disk is write protected
+			break;
+		}
+	}
diff --git a/documentation/fatfs.rst b/documentation/fatfs.rst
new file mode 100644
index 0000000..1ca8924
--- /dev/null
+++ b/documentation/fatfs.rst
@@ -0,0 +1,85 @@
+FATFS
+=====
+The FATFS provides file system for the storage medium
+Based on the storage size the file system will be organized into FAT12/FAT16/FAT32
+The FATFS application interface provides File/Directory  Access, File/Directory Management and Volume Management
+
+
+Features
+--------
+
+* Very small footprint for FATFS API  implementation
+* Windows compatible FAT file system
+* File system settings are configurable
+
+Dependencies
+------------
+
+::
+
+            FATFS
+              /\
+             /  \
+            /    \
+         DISKIO  RTT
+           /\
+          /  \
+         /    \
+     SD/MMC   USB MSC
+       /        \ 
+      /          \
+    MCI          USB
+
+* Generic disk access layer to perform DiskIO functions
+* RTT calendar interface
+* SD/MMC media accessor
+* USB mass storage device media accessor
+* Peripheral that supports multimedia card interface (MCI)
+* USB Driver
+
+
+Example Applications
+--------------------
+
+* Generic FATFS application to demonstrate the API access
+* POSIX standard file system API access
+
+Limitations
+-----------
+
+* FAT sub-types: FAT12, FAT16 and FAT32.
+* Number of open files: Unlimited. (depends on available memory)
+* Number of volumes: Upto 10.
+* File size: Upto 4G-1 bytes. (by FAT specs.)
+* Volume size: Upto 2T bytes at 512 bytes/sector. (by FAT specs.)
+* Cluster size: Upto 64K bytes at 512 bytes/sector. (by FAT specs.)
+* Sector size: 512, 1024, 2048 and 4096 bytes. (by FAT specs.)
+
+Reference
+---------
+
+* :API Documentation: '<../fatfs/doc/00index_e.html>'
+* http://elm-chan.org/fsw/ff/00index_e.html 
+
+License
+--------
+
+::
+
+/*----------------------------------------------------------------------------/
+/  FatFs - FAT file system module  R0.11                 (C)ChaN, 2015
+/-----------------------------------------------------------------------------/
+/ FatFs module is a free software that opened under license policy of
+/ following conditions.
+/
+/ Copyright (C) 2015, ChaN, all right reserved.
+/
+/ 1. Redistributions of source code must retain the above copyright notice,
+/    this condition and the following disclaimer.
+/
+/ This software is provided by the copyright holder and contributors "AS IS"
+/ and any warranties related to this software are DISCLAIMED.
+/ The copyright owner or contributors be NOT LIABLE for any damages caused
+/ by use of this software.
+/----------------------------------------------------------------------------*/
+
diff --git a/documentation/sd_mmc.rst b/documentation/sd_mmc.rst
new file mode 100644
index 0000000..49744eb
--- /dev/null
+++ b/documentation/sd_mmc.rst
@@ -0,0 +1,31 @@
+SD/MMC/SDIO
+===========
+
+The SD/MMC stack supports SD/MMC memory card and SDIO card.
+
+The stack should be initialized with right HAL instance. Then sd_mmc_check is
+be used to detect and mount the card. When the card is ready, the block
+read/write functions are used to access the data on card. Note that the
+read/write functions split the read/write process to init/start/wait_end, so
+that user has chance to control the whole data process to remove overheads.
+Note if used MCI OS driver version,the operation for SD/MMC should be in os task.
+
+Features
+--------
+
+* Card initialization
+* Card detection and protection detection
+* Card type and capacity check
+* Card mount/unmount
+* Card read/write
+
+Dependencies
+------------
+
+* Peripheral that supports multimedia card interface (MCI)
+
+Limitations
+-----------
+
+* No SPI interface support yet
+* Support only one peripheral instance
diff --git a/driver_init.c b/driver_init.c
index 600bef0..a7f5fa5 100644
--- a/driver_init.c
+++ b/driver_init.c
@@ -13,8 +13,23 @@
 
 struct spi_m_sync_descriptor SPI_SD_MMC;
 
+struct calendar_descriptor CALENDER_INTERFACE;
+
 struct usart_sync_descriptor USART_DBG;
 
+struct mci_sync_desc IO_BUS;
+
+void CALENDER_INTERFACE_CLOCK_init(void)
+{
+	hri_mclk_set_APBAMASK_RTC_bit(MCLK);
+}
+
+void CALENDER_INTERFACE_init(void)
+{
+	CALENDER_INTERFACE_CLOCK_init();
+	calendar_init(&CALENDER_INTERFACE, RTC);
+}
+
 void USART_DBG_PORT_init(void)
 {
 
@@ -94,6 +109,294 @@ void SPI_SD_MMC_init(void)
 	SPI_SD_MMC_PORT_init();
 }
 
+void IO_BUS_PORT_init(void)
+{
+
+	gpio_set_pin_direction(PB11,
+	                       // <y> Pin direction
+	                       // <id> pad_direction
+	                       // <GPIO_DIRECTION_OFF"> Off
+	                       // <GPIO_DIRECTION_IN"> In
+	                       // <GPIO_DIRECTION_OUT"> Out
+	                       GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_level(PB11,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	gpio_set_pin_pull_mode(PB11,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(PB11,
+	                      // <y> Pin function
+	                      // <id> pad_function
+	                      // <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
+	                      // <PINMUX_PB11I_SDHC0_SDCK"> Auto
+	                      // <GPIO_PIN_FUNCTION_OFF"> Off
+	                      // <GPIO_PIN_FUNCTION_A"> A
+	                      // <GPIO_PIN_FUNCTION_B"> B
+	                      // <GPIO_PIN_FUNCTION_C"> C
+	                      // <GPIO_PIN_FUNCTION_D"> D
+	                      // <GPIO_PIN_FUNCTION_E"> E
+	                      // <GPIO_PIN_FUNCTION_F"> F
+	                      // <GPIO_PIN_FUNCTION_G"> G
+	                      // <GPIO_PIN_FUNCTION_H"> H
+	                      // <GPIO_PIN_FUNCTION_I"> I
+	                      // <GPIO_PIN_FUNCTION_J"> J
+	                      // <GPIO_PIN_FUNCTION_K"> K
+	                      // <GPIO_PIN_FUNCTION_L"> L
+	                      // <GPIO_PIN_FUNCTION_M"> M
+	                      // <GPIO_PIN_FUNCTION_N"> N
+	                      PINMUX_PB11I_SDHC0_SDCK);
+
+	gpio_set_pin_direction(PA08,
+	                       // <y> Pin direction
+	                       // <id> pad_direction
+	                       // <GPIO_DIRECTION_OFF"> Off
+	                       // <GPIO_DIRECTION_IN"> In
+	                       // <GPIO_DIRECTION_OUT"> Out
+	                       GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_level(PA08,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	gpio_set_pin_pull_mode(PA08,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(PA08,
+	                      // <y> Pin function
+	                      // <id> pad_function
+	                      // <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
+	                      // <PINMUX_PA08I_SDHC0_SDCMD"> Auto
+	                      // <GPIO_PIN_FUNCTION_OFF"> Off
+	                      // <GPIO_PIN_FUNCTION_A"> A
+	                      // <GPIO_PIN_FUNCTION_B"> B
+	                      // <GPIO_PIN_FUNCTION_C"> C
+	                      // <GPIO_PIN_FUNCTION_D"> D
+	                      // <GPIO_PIN_FUNCTION_E"> E
+	                      // <GPIO_PIN_FUNCTION_F"> F
+	                      // <GPIO_PIN_FUNCTION_G"> G
+	                      // <GPIO_PIN_FUNCTION_H"> H
+	                      // <GPIO_PIN_FUNCTION_I"> I
+	                      // <GPIO_PIN_FUNCTION_J"> J
+	                      // <GPIO_PIN_FUNCTION_K"> K
+	                      // <GPIO_PIN_FUNCTION_L"> L
+	                      // <GPIO_PIN_FUNCTION_M"> M
+	                      // <GPIO_PIN_FUNCTION_N"> N
+	                      PINMUX_PA08I_SDHC0_SDCMD);
+
+	gpio_set_pin_direction(PA09,
+	                       // <y> Pin direction
+	                       // <id> pad_direction
+	                       // <GPIO_DIRECTION_OFF"> Off
+	                       // <GPIO_DIRECTION_IN"> In
+	                       // <GPIO_DIRECTION_OUT"> Out
+	                       GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_level(PA09,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	gpio_set_pin_pull_mode(PA09,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(PA09,
+	                      // <y> Pin function
+	                      // <id> pad_function
+	                      // <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
+	                      // <PINMUX_PA09I_SDHC0_SDDAT0"> Auto
+	                      // <GPIO_PIN_FUNCTION_OFF"> Off
+	                      // <GPIO_PIN_FUNCTION_A"> A
+	                      // <GPIO_PIN_FUNCTION_B"> B
+	                      // <GPIO_PIN_FUNCTION_C"> C
+	                      // <GPIO_PIN_FUNCTION_D"> D
+	                      // <GPIO_PIN_FUNCTION_E"> E
+	                      // <GPIO_PIN_FUNCTION_F"> F
+	                      // <GPIO_PIN_FUNCTION_G"> G
+	                      // <GPIO_PIN_FUNCTION_H"> H
+	                      // <GPIO_PIN_FUNCTION_I"> I
+	                      // <GPIO_PIN_FUNCTION_J"> J
+	                      // <GPIO_PIN_FUNCTION_K"> K
+	                      // <GPIO_PIN_FUNCTION_L"> L
+	                      // <GPIO_PIN_FUNCTION_M"> M
+	                      // <GPIO_PIN_FUNCTION_N"> N
+	                      PINMUX_PA09I_SDHC0_SDDAT0);
+
+	gpio_set_pin_direction(PA10,
+	                       // <y> Pin direction
+	                       // <id> pad_direction
+	                       // <GPIO_DIRECTION_OFF"> Off
+	                       // <GPIO_DIRECTION_IN"> In
+	                       // <GPIO_DIRECTION_OUT"> Out
+	                       GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_level(PA10,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	gpio_set_pin_pull_mode(PA10,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(PA10,
+	                      // <y> Pin function
+	                      // <id> pad_function
+	                      // <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
+	                      // <PINMUX_PA10I_SDHC0_SDDAT1"> Auto
+	                      // <GPIO_PIN_FUNCTION_OFF"> Off
+	                      // <GPIO_PIN_FUNCTION_A"> A
+	                      // <GPIO_PIN_FUNCTION_B"> B
+	                      // <GPIO_PIN_FUNCTION_C"> C
+	                      // <GPIO_PIN_FUNCTION_D"> D
+	                      // <GPIO_PIN_FUNCTION_E"> E
+	                      // <GPIO_PIN_FUNCTION_F"> F
+	                      // <GPIO_PIN_FUNCTION_G"> G
+	                      // <GPIO_PIN_FUNCTION_H"> H
+	                      // <GPIO_PIN_FUNCTION_I"> I
+	                      // <GPIO_PIN_FUNCTION_J"> J
+	                      // <GPIO_PIN_FUNCTION_K"> K
+	                      // <GPIO_PIN_FUNCTION_L"> L
+	                      // <GPIO_PIN_FUNCTION_M"> M
+	                      // <GPIO_PIN_FUNCTION_N"> N
+	                      PINMUX_PA10I_SDHC0_SDDAT1);
+
+	gpio_set_pin_direction(PA11,
+	                       // <y> Pin direction
+	                       // <id> pad_direction
+	                       // <GPIO_DIRECTION_OFF"> Off
+	                       // <GPIO_DIRECTION_IN"> In
+	                       // <GPIO_DIRECTION_OUT"> Out
+	                       GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_level(PA11,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	gpio_set_pin_pull_mode(PA11,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(PA11,
+	                      // <y> Pin function
+	                      // <id> pad_function
+	                      // <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
+	                      // <PINMUX_PA11I_SDHC0_SDDAT2"> Auto
+	                      // <GPIO_PIN_FUNCTION_OFF"> Off
+	                      // <GPIO_PIN_FUNCTION_A"> A
+	                      // <GPIO_PIN_FUNCTION_B"> B
+	                      // <GPIO_PIN_FUNCTION_C"> C
+	                      // <GPIO_PIN_FUNCTION_D"> D
+	                      // <GPIO_PIN_FUNCTION_E"> E
+	                      // <GPIO_PIN_FUNCTION_F"> F
+	                      // <GPIO_PIN_FUNCTION_G"> G
+	                      // <GPIO_PIN_FUNCTION_H"> H
+	                      // <GPIO_PIN_FUNCTION_I"> I
+	                      // <GPIO_PIN_FUNCTION_J"> J
+	                      // <GPIO_PIN_FUNCTION_K"> K
+	                      // <GPIO_PIN_FUNCTION_L"> L
+	                      // <GPIO_PIN_FUNCTION_M"> M
+	                      // <GPIO_PIN_FUNCTION_N"> N
+	                      PINMUX_PA11I_SDHC0_SDDAT2);
+
+	gpio_set_pin_direction(PB10,
+	                       // <y> Pin direction
+	                       // <id> pad_direction
+	                       // <GPIO_DIRECTION_OFF"> Off
+	                       // <GPIO_DIRECTION_IN"> In
+	                       // <GPIO_DIRECTION_OUT"> Out
+	                       GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_level(PB10,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	gpio_set_pin_pull_mode(PB10,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(PB10,
+	                      // <y> Pin function
+	                      // <id> pad_function
+	                      // <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
+	                      // <PINMUX_PB10I_SDHC0_SDDAT3"> Auto
+	                      // <GPIO_PIN_FUNCTION_OFF"> Off
+	                      // <GPIO_PIN_FUNCTION_A"> A
+	                      // <GPIO_PIN_FUNCTION_B"> B
+	                      // <GPIO_PIN_FUNCTION_C"> C
+	                      // <GPIO_PIN_FUNCTION_D"> D
+	                      // <GPIO_PIN_FUNCTION_E"> E
+	                      // <GPIO_PIN_FUNCTION_F"> F
+	                      // <GPIO_PIN_FUNCTION_G"> G
+	                      // <GPIO_PIN_FUNCTION_H"> H
+	                      // <GPIO_PIN_FUNCTION_I"> I
+	                      // <GPIO_PIN_FUNCTION_J"> J
+	                      // <GPIO_PIN_FUNCTION_K"> K
+	                      // <GPIO_PIN_FUNCTION_L"> L
+	                      // <GPIO_PIN_FUNCTION_M"> M
+	                      // <GPIO_PIN_FUNCTION_N"> N
+	                      PINMUX_PB10I_SDHC0_SDDAT3);
+}
+
+void IO_BUS_CLOCK_init(void)
+{
+	hri_mclk_set_AHBMASK_SDHC0_bit(MCLK);
+	hri_gclk_write_PCHCTRL_reg(GCLK, SDHC0_GCLK_ID, CONF_GCLK_SDHC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, SDHC0_GCLK_ID_SLOW, CONF_GCLK_SDHC0_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+}
+
+void IO_BUS_init(void)
+{
+	IO_BUS_CLOCK_init();
+	mci_sync_init(&IO_BUS, SDHC0);
+	IO_BUS_PORT_init();
+}
+
 void delay_driver_init(void)
 {
 	delay_init(SysTick);
@@ -103,9 +406,13 @@ void system_init(void)
 {
 	init_mcu();
 
+	CALENDER_INTERFACE_init();
+
 	USART_DBG_init();
 
 	SPI_SD_MMC_init();
 
+	IO_BUS_init();
+
 	delay_driver_init();
 }
diff --git a/driver_init.h b/driver_init.h
index 4c29789..d06086c 100644
--- a/driver_init.h
+++ b/driver_init.h
@@ -21,14 +21,25 @@ extern "C" {
 #include <hal_io.h>
 #include <hal_sleep.h>
 
+#include <hal_calendar.h>
+
 #include <hal_usart_sync.h>
 #include <hal_spi_m_sync.h>
 
+#include <hal_mci_sync.h>
+
 #include <hal_delay.h>
 
+extern struct calendar_descriptor CALENDER_INTERFACE;
+
 extern struct usart_sync_descriptor USART_DBG;
 extern struct spi_m_sync_descriptor SPI_SD_MMC;
 
+extern struct mci_sync_desc IO_BUS;
+
+void CALENDER_INTERFACE_CLOCK_init(void);
+void CALENDER_INTERFACE_init(void);
+
 void USART_DBG_PORT_init(void);
 void USART_DBG_CLOCK_init(void);
 void USART_DBG_init(void);
@@ -37,6 +48,10 @@ void SPI_SD_MMC_PORT_init(void);
 void SPI_SD_MMC_CLOCK_init(void);
 void SPI_SD_MMC_init(void);
 
+void IO_BUS_PORT_init(void);
+void IO_BUS_CLOCK_init(void);
+void IO_BUS_init(void);
+
 void delay_driver_init(void);
 
 /**
diff --git a/examples/driver_examples.c b/examples/driver_examples.c
index 491e1bb..a8fd5de 100644
--- a/examples/driver_examples.c
+++ b/examples/driver_examples.c
@@ -10,6 +10,41 @@
 #include "driver_init.h"
 #include "utils.h"
 
+/**
+ * Example of using CALENDER_INTERFACE.
+ */
+static struct calendar_alarm alarm;
+
+static void alarm_cb(struct calendar_descriptor *const descr)
+{
+	/* alarm expired */
+}
+
+void CALENDER_INTERFACE_example(void)
+{
+	struct calendar_date date;
+	struct calendar_time time;
+
+	calendar_enable(&CALENDER_INTERFACE);
+
+	date.year  = 2000;
+	date.month = 12;
+	date.day   = 31;
+
+	time.hour = 12;
+	time.min  = 59;
+	time.sec  = 59;
+
+	calendar_set_date(&CALENDER_INTERFACE, &date);
+	calendar_set_time(&CALENDER_INTERFACE, &time);
+
+	alarm.cal_alarm.datetime.time.sec = 4;
+	alarm.cal_alarm.option            = CALENDAR_ALARM_MATCH_SEC;
+	alarm.cal_alarm.mode              = REPEAT;
+
+	calendar_set_alarm(&CALENDER_INTERFACE, &alarm, alarm_cb);
+}
+
 /**
  * Example of using USART_DBG to write "Hello World" using the IO abstraction.
  */
diff --git a/examples/driver_examples.h b/examples/driver_examples.h
index ae92944..0e78af9 100644
--- a/examples/driver_examples.h
+++ b/examples/driver_examples.h
@@ -12,6 +12,8 @@
 extern "C" {
 #endif
 
+void CALENDER_INTERFACE_example(void);
+
 void USART_DBG_example(void);
 
 void delay_example(void);
diff --git a/fatfs/src/conf_fatfs.h b/fatfs/src/conf_fatfs.h
new file mode 100644
index 0000000..cd4de81
--- /dev/null
+++ b/fatfs/src/conf_fatfs.h
@@ -0,0 +1,310 @@
+/* Auto-generated config file conf_fatfs.h */
+        #ifndef CONF_FATFS_H
+        #define CONF_FATFS_H
+
+        // <<< Use Configuration Wizard in Context Menu >>>
+
+        // <h> Function Configurations
+/*---------------------------------------------------------------------------/
+/  FatFs - FAT file system module configuration file  R0.11a (C)ChaN, 2015
+/---------------------------------------------------------------------------*/
+
+#define _FFCONF 64180	/* Revision ID */
+
+/*---------------------------------------------------------------------------/
+/ Function Configurations
+/---------------------------------------------------------------------------*/
+
+// <q> Read Only File System Enable
+// <i> This option switches read-only configuration. Read-only configuration removes writing API functions, f_write(), f_sync(), f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree() and optional writing functions as 	well.
+// <id> read_only_fs_enable
+#ifndef _FS_READONLY
+#   define _FS_READONLY 0x0
+#endif
+
+// <o> Minimisation Level (_FS_MINIMIZE)
+// <i> The _FS_MINIMIZE option defines minimization level to remove some functions.
+	// <0x0=> 0 - Full function
+	// <0x1=> 1 - f_stat, f_getfree, f_unlink, f_mkdir, f_chmod, f_truncate and f_rename are removed
+	// <0x2=> 2 - f_opendir and f_readdir are removed in addition to option 1
+	// <0x3=> 3 - f_lseek is removed in addition to option 2
+// <id> minimisation_level
+#ifndef _FS_MINIMIZE
+#   define _FS_MINIMIZE 0x0
+#endif
+
+// <q> String Functions Enable
+// <i> To enable string functions.
+// <id> strfunc_fs_enable
+#ifndef _USE_STRFUNC
+#   define _USE_STRFUNC 0x0
+#endif
+
+// <q> f_mkfs Function Enable
+// <i> This option switches f_mkfs() function.
+// <id> f_mkfs_fs_enable
+#ifndef _USE_MKFS
+#   define _USE_MKFS 0x1
+#endif
+
+// <q> f_forward() Function Enable
+// <i> This option switches f_forward() function. 
+// <id> use_forward_fs_enable
+#ifndef _USE_FORWARD
+#   define _USE_FORWARD 0x0
+#endif
+
+// <q> Fast Seek feature Enable
+// <i> This option switches fast seek feature.
+// <id> fast_seek_fs_enable
+#ifndef _USE_FASTSEEK
+#   define _USE_FASTSEEK 0x0
+#endif
+
+// <q> Filtered Directory read feature Enable
+// <i> This option switches filtered directory read feature and related functions, f_findfirst() and f_findnext(). 
+// <id> filtered_dir_enable
+#ifndef _USE_FIND
+#   define _USE_FIND 0x0
+#endif
+
+// <q> Volume Label Function Enable
+// <i> This option switches volume label functions, f_getlabel() and f_setlabel().
+// <id> volume_label_enable
+#ifndef _USE_LABEL
+#   define _USE_LABEL 0x0
+#endif
+
+// </h>
+
+// <h> Drive/Volume Configurations
+/*---------------------------------------------------------------------------/
+/ Drive/Volume Configurations
+/----------------------------------------------------------------------------*/
+
+// <o> Number of Volumes <1-10>
+// <i> Number of volumes (logical drives) to be used. (1 to 10)
+// <id> num_volumes
+#ifndef _VOLUMES
+#   define _VOLUMES 5
+#endif
+
+// <o> Minimum Sector Size 
+// <i> Minimum sector size to be handled. Always set 512 for memory card and hard disk but a larger value may be required for on-board flash memory, floppy disk and optical disk.
+	// <512=> 512
+	// <1024=> 1024
+	// <2048=> 2048
+	// <4096=> 4096
+// <id> min_sector_size
+#ifndef _MIN_SS
+#   define _MIN_SS 512
+#endif
+
+// <o> Maximum Sector Size 
+// <i> Maximum sector size to be handled. Always set 512 for memory card and hard disk but a larger value may be required for on-board flash memory, floppy disk and optical disk.
+	// <512=> 512
+	// <1024=> 1024
+	// <2048=> 2048
+	// <4096=> 4096
+// <id> max_sector_size
+#ifndef _MAX_SS
+#   define _MAX_SS 512
+#endif
+
+// <q> String Volume ID feature Enable
+// <i>  When this feature is enabled, pre-defined strings can be used as drive number in the path name. _VOLUME_STRS defines the drive ID strings for each logical drives. Number of items must be equal to number of volumes. Valid characters for the drive ID strings are: A-Z and 0-9.
+// <id> string_volume_enable
+#ifndef _STR_VOLUME_ID
+#   define _STR_VOLUME_ID 0
+#endif
+
+#define _VOLUME_STRS	"RAM","NAND","CF","SD1","SD2","USB1","USB2","USB3"
+
+// <q> ATA-TRIM feature Enable
+// <i>  This option switches ATA-TRIM feature.
+// <id> trim_feature_enable
+#ifndef _USE_TRIM
+#   define _USE_TRIM 0
+#endif
+
+// <q> Free Space Info feature Enable
+// <i>  If you need to know correct free space on the FAT32 volume disable the feature so that f_getfree() function at first time after volume mount will force a full FAT scan. When enabled, controls the use of last allocated cluster number.
+// <id> free_space_info_enable
+#ifndef _FS_NOFSINFO
+#   define _FS_NOFSINFO 0
+#endif
+
+// <q> Multiple Partition Enable
+// <i>  When this is disabled, each volume is bound to the same physical drive number and it can mount only first primary partition and when enabled each volume is tied to the partitions listed in VolToPart[].
+// <id> multiple_partition_enable
+#ifndef _MULTI_PARTITION
+#   define _MULTI_PARTITION 0
+#endif
+
+// <q> Sector Erase Feature Enable
+// <i> This enables sector erase feature
+// <id> sectore_erase_enable
+#ifndef _USE_ERASE
+#   define _USE_ERASE 0
+#endif
+
+// </h>
+
+// <h> Locale and Namespace Configurations
+/*---------------------------------------------------------------------------/
+/ Locale and Namespace Configurations
+/----------------------------------------------------------------------------*/
+
+// <o> OEM Code Page
+// <i> The _CODE_PAGE specifies the OEM code page to be used on the target system. Incorrect setting of the code page can cause a file open failure.
+	// <1=> ASCII only (Valid for non LFN cfg.)
+	// <437=> U.S. (OEM)
+	// <720=> Arabic (OEM)
+	// <737=> Greek (OEM)
+	// <775=> Baltic (OEM)
+	// <850=> Multilingual Latin 1 (OEM)
+	// <852=> Latin 2 (OEM)
+	// <855=> Cyrillic (OEM)
+	// <857=> Turkish (OEM)
+	// <858=> Multilingual Latin 1 + Euro (OEM)
+	// <862=> Hebrew (OEM))
+	// <866=> Russian (OEM)
+	// <874=> Thai (OEM, Windows)
+	// <932=> Japanese Shift-JIS (DBCS, OEM, Windows) 
+	// <936=> Simplified Chinese GBK (DBCS, OEM, Windows)
+	// <949=> Korean (DBCS, OEM, Windows)
+	// <950=> Traditional Chinese Big5 (DBCS, OEM, Windows)
+	// <1250=> Central Europe (Windows)
+	// <1251=> Cyrillic (Windows)
+	// <1252=> Latin 1 (Windows)
+	// <1253=> Greek (Windows)
+	// <1254=> Turkish (Windows)
+	// <1255=> Hebrew (Windows)
+	// <1256=> Arabic (Windows)
+	// <1257=> Baltic (Windows)
+	// <1258=> Vietnam (OEM, Windows)
+// <id> code_page
+#ifndef _CODE_PAGE
+#   define _CODE_PAGE 850
+#endif
+
+// <o> LFN Feature
+// <i> The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. To enable LFN, Unicode handling functions ff_convert() and ff_wtoupper() must be added to the project. When enable to use heap, memory control functions ff_memalloc() and ff_memfree() must be added to the project.
+	// <0x0=> 0 - Disable LFN feature. _MAX_LFN and _LFN_UNICODE have no effect.
+	// <0x1=> 1 - Enable LFN with static working buffer on the BSS. Always NOT reentrant.
+	// <0x2=> 2 - Enable LFN with dynamic working buffer on the STACK.
+	// <0x3=> 3 - Enable LFN with dynamic working buffer on the HEAP.
+// <id> lfn_feature
+#ifndef _USE_LFN
+#   define _USE_LFN 0
+#endif
+
+// <o> Maximum LFN length to handle <12-255>
+// <i> Maximum LFN length to handle (12 to 255)
+// <id> max_lfn_length
+#ifndef _MAX_LFN
+#   define _MAX_LFN 255
+#endif
+
+// <o> Character Code Set
+// <i>  To switch the character code set on FatFs API to Unicode, enable LFN feature.
+	// <0x0=> 0 - ANSI/OEM
+	// <0x1=> 1 - Unicode
+// <id> character_code_set
+#ifndef _LFN_UNICODE
+#   define _LFN_UNICODE 0
+#endif
+
+// <o> Character Encoding
+// <i> When character code is selected as Unicode, this option selects the character encoding on the file to be read/written via string I/O functions, f_gets(), f_putc(), f_puts and f_printf().
+	// <0x0=> ANSI/OEM
+	// <0x1=> UTF-16LE
+	// <0x2=> UTF-16BE
+	// <0x3=> UTF-8
+// <id> character_encoding
+#ifndef _STRF_ENCODE
+#   define _STRF_ENCODE 3
+#endif
+
+// <o> Relative Path Feature
+// <i> The relative path feature is configured here.
+	// <0x0=> 0 - Disable relative path feature and remove related functions.
+	// <0x1=> 1 - Enable relative path. f_chdrive() and f_chdir() are available.
+	// <0x2=> 2 - f_getcwd() is available in addition to 1.
+// <id> relative_path_enable 
+#ifndef _FS_RPATH
+#   define _FS_RPATH 2
+#endif
+// </h>
+
+// <h> System Configurations
+/*---------------------------------------------------------------------------/
+/ System Configurations
+/----------------------------------------------------------------------------*/
+
+// <q> Time Stamp Feature Enable
+// <i> This option switches timestamp feature. If the system does not have an RTC function or valid timestamp is not needed, disable this feature.
+// <id> time_stamp_enable
+#ifndef _FS_NORTC
+#   define _FS_NORTC 0
+#endif
+
+#define _NORTC_MON	1
+#define _NORTC_MDAY	1
+#define _NORTC_YEAR	2015
+
+// <o> File Lock Feature <0-100>
+// <i> This option switches file lock feature to control duplicated file open and illegal operation to open objects. This option must not be enabled (value to be 0) if it is a read only filesystem. To avoid volume corruption, application program should avoid illegal open, remove and rename to the open objects. If value is greater tha 0, it defines how many files/sub-directories can be opened simultaneously under file lock control. Note that the file lock feature is independent of re-entrancy.
+// <id> file_lock_enable
+#ifndef _FS_LOCK
+#   define _FS_LOCK 0
+#endif
+
+// <q> Tiny File System Enable
+// <i> When this feature is enabled FatFs uses the sector buffer in the file system object instead of the sector buffer in the individual file object for file data transfer. This reduces memory consumption 512 bytes each file object.
+// <id> tiny_fs_enable
+#ifndef _FS_TINY
+#   define _FS_TINY 0
+#endif
+
+// <q> Word Access Enable
+// <i> This option defines which access method is used to the word data on the FAT volume. When the byte order on the memory is big-endian or address miss-aligned word access results incorrect behavior, this option should be disabled. If it is not the case, feature can be enabled to improve the performance and code size.
+// <id> word_access_enable 
+#ifndef _WORD_ACCESS
+#   define _WORD_ACCESS 0
+#endif
+
+// <q> Reentrancy (Thread Safe) Enable
+// <i> Enabling the feature adds synchronization handlers, ff_req_grant, ff_rel_grant, ff_del_syncobj and ff_cre_syncobj functions.
+// <id> reentrant_enable 
+#ifndef _FS_REENTRANT
+#   define _FS_REENTRANT 0
+#endif
+
+// <o> File System Timeout <1-100000>
+// <i> Timeout period in unit of time ticks (1 - 100000)
+// <id> config_fs_timeout
+#ifndef _FS_TIMEOUT
+#   define _FS_TIMEOUT 1000
+#endif
+
+// <s> Synch Handler Name
+// <i> This string will be sent to console
+// <id> synch_handler
+#ifndef _SYNC_t
+#   define _SYNC_t "HANDLE"
+#endif
+
+// <o> File Sharing Feature <0-100>
+// <i> To enable file sharing feature, set the value to 1 or greater. The value defines how many files can be opened simultaneously.
+// <id> file_share_count
+#ifndef _FS_SHARE
+#   define _FS_SHARE 0
+#endif
+
+// </h>
+
+        // <<< end of configuration section >>>
+
+        #endif // CONF_FATFS_H
+        
diff --git a/fatfs/src/ff.c b/fatfs/src/ff.c
new file mode 100644
index 0000000..102613c
--- /dev/null
+++ b/fatfs/src/ff.c
@@ -0,0 +1,4412 @@
+/*----------------------------------------------------------------------------/
+/  FatFs - FAT file system module  R0.11a                (C)ChaN, 2015        /
+/-----------------------------------------------------------------------------/
+/ FatFs module is a free software that opened under license policy of
+/ following conditions.
+/
+/ Copyright (C) 2015, ChaN, all right reserved.
+/
+/ 1. Redistributions of source code must retain the above copyright notice,
+/    this condition and the following disclaimer.
+/
+/ This software is provided by the copyright holder and contributors "AS IS"
+/ and any warranties related to this software are DISCLAIMED.
+/ The copyright owner or contributors be NOT LIABLE for any damages caused
+/ by use of this software.
+/----------------------------------------------------------------------------*/
+
+#include "ff.h"			/* Declarations of FatFs API */
+#include "diskio.h"		/* Declarations of disk I/O functions */
+
+/*--------------------------------------------------------------------------
+
+   Module Private Definitions
+
+---------------------------------------------------------------------------*/
+
+#if _FATFS != 64180	/* Revision ID */
+#error Wrong include file (ff.h).
+#endif
+
+/* Reentrancy related */
+#if _FS_REENTRANT
+#if _USE_LFN == 1
+#error Static LFN work area cannot be used at thread-safe configuration
+#endif
+#define	ENTER_FF(fs)		{ if (!lock_fs(fs)) return FR_TIMEOUT; }
+#define	LEAVE_FF(fs, res)	{ unlock_fs(fs, res); return res; }
+#else
+#define	ENTER_FF(fs)
+#define LEAVE_FF(fs, res)	return res
+#endif
+
+#define	ABORT(fs, res)		{ fp->err = (BYTE)(res); LEAVE_FF(fs, res); }
+
+/* Definitions of sector size */
+#if (_MAX_SS < _MIN_SS) || (_MAX_SS != 512 && _MAX_SS != 1024 && _MAX_SS != 2048 && _MAX_SS != 4096) || (_MIN_SS != 512 && _MIN_SS != 1024 && _MIN_SS != 2048 && _MIN_SS != 4096)
+#error Wrong sector size configuration
+#endif
+#if _MAX_SS == _MIN_SS
+#define	SS(fs)	((UINT)_MAX_SS)	/* Fixed sector size */
+#else
+#define	SS(fs)	((fs)->ssize)	/* Variable sector size */
+#endif
+
+/* Timestamp feature */
+#if _FS_NORTC == 1
+#if _NORTC_YEAR < 1980 || _NORTC_YEAR > 2107 || _NORTC_MON < 1 || _NORTC_MON > 12 || _NORTC_MDAY < 1 || _NORTC_MDAY > 31
+#error Invalid _FS_NORTC settings
+#endif
+#define GET_FATTIME()	((DWORD)(_NORTC_YEAR - 1980) << 25 | (DWORD)_NORTC_MON << 21 | (DWORD)_NORTC_MDAY << 16)
+#else
+#define GET_FATTIME()	get_fattime()
+#endif
+
+/* File access control feature */
+#if _FS_LOCK
+#if _FS_READONLY
+#error _FS_LOCK must be 0 at read-only configuration
+#endif
+typedef struct {
+	FATFS *fs;		/* Object ID 1, volume (NULL:blank entry) */
+	DWORD clu;		/* Object ID 2, directory (0:root) */
+	WORD idx;		/* Object ID 3, directory index */
+	WORD ctr;		/* Object open counter, 0:none, 0x01..0xFF:read mode open count, 0x100:write mode */
+} FILESEM;
+#endif
+
+/* DBCS code ranges and SBCS upper conversion tables */
+
+#if _CODE_PAGE == 932	/* Japanese Shift-JIS */
+#define _DF1S	0x81	/* DBC 1st byte range 1 start */
+#define _DF1E	0x9F	/* DBC 1st byte range 1 end */
+#define _DF2S	0xE0	/* DBC 1st byte range 2 start */
+#define _DF2E	0xFC	/* DBC 1st byte range 2 end */
+#define _DS1S	0x40	/* DBC 2nd byte range 1 start */
+#define _DS1E	0x7E	/* DBC 2nd byte range 1 end */
+#define _DS2S	0x80	/* DBC 2nd byte range 2 start */
+#define _DS2E	0xFC	/* DBC 2nd byte range 2 end */
+
+#elif _CODE_PAGE == 936	/* Simplified Chinese GBK */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x40
+#define _DS1E	0x7E
+#define _DS2S	0x80
+#define _DS2E	0xFE
+
+#elif _CODE_PAGE == 949	/* Korean */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x41
+#define _DS1E	0x5A
+#define _DS2S	0x61
+#define _DS2E	0x7A
+#define _DS3S	0x81
+#define _DS3E	0xFE
+
+#elif _CODE_PAGE == 950	/* Traditional Chinese Big5 */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x40
+#define _DS1E	0x7E
+#define _DS2S	0xA1
+#define _DS2E	0xFE
+
+#elif _CODE_PAGE == 437	/* U.S. */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x45,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \
+				0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 720	/* Arabic */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+				0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 737	/* Greek */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+				0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \
+				0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xEF,0xF5,0xF0,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 771	/* KBL */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+				0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDC,0xDE,0xDE, \
+				0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFE,0xFF}
+
+#elif _CODE_PAGE == 775	/* Baltic */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F, \
+				0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 850	/* Latin 1 */
+#define _DF1S	0
+#define _EXCVT {0x43,0x55,0x45,0x41,0x41,0x41,0x41,0x43,0x45,0x45,0x45,0x49,0x49,0x49,0x41,0x41, \
+				0x45,0x92,0x92,0x4F,0x4F,0x4F,0x55,0x55,0x59,0x4F,0x55,0x4F,0x9C,0x4F,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0x41,0x41,0x41,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0x41,0x41,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD1,0xD1,0x45,0x45,0x45,0x49,0x49,0x49,0x49,0xD9,0xDA,0xDB,0xDC,0xDD,0x49,0xDF, \
+				0x4F,0xE1,0x4F,0x4F,0x4F,0x4F,0xE6,0xE8,0xE8,0x55,0x55,0x55,0x59,0x59,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 852	/* Latin 2 */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F, \
+				0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0xAC, \
+				0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF}
+
+#elif _CODE_PAGE == 855	/* Cyrillic */
+#define _DF1S	0
+#define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F, \
+				0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \
+				0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \
+				0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF, \
+				0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 857	/* Turkish */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x49,0x8E,0x8F, \
+				0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \
+				0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0x49,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 860	/* Portuguese */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0x8F,0x8E,0x91,0x86,0x80,0x89,0x89,0x92,0x8B,0x8C,0x98,0x8E,0x8F, \
+				0x90,0x91,0x92,0x8C,0x99,0xA9,0x96,0x9D,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x86,0x8B,0x9F,0x96,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 861	/* Icelandic */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x8B,0x8B,0x8D,0x8E,0x8F, \
+				0x90,0x92,0x92,0x4F,0x99,0x8D,0x55,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+				0xA4,0xA5,0xA6,0xA7,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 862	/* Hebrew */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+				0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 863	/* Canadian-French */
+#define _DF1S	0
+#define _EXCVT {0x43,0x55,0x45,0x41,0x41,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x41,0x8F, \
+				0x45,0x45,0x45,0x4F,0x45,0x49,0x55,0x55,0x98,0x4F,0x55,0x9B,0x9C,0x55,0x55,0x9F, \
+				0xA0,0xA1,0x4F,0x55,0xA4,0xA5,0xA6,0xA7,0x49,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 864	/* Arabic */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x45,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \
+				0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 865	/* Nordic */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \
+				0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 866	/* Russian */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+				0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0x90,0x91,0x92,0x93,0x9d,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 869	/* Greek 2 */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+				0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x86,0x9C,0x8D,0x8F,0x90, \
+				0x91,0x90,0x92,0x95,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xA4,0xA5,0xA6,0xD9,0xDA,0xDB,0xDC,0xA7,0xA8,0xDF, \
+				0xA9,0xAA,0xAC,0xAD,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xCF,0xCF,0xD0,0xEF, \
+				0xF0,0xF1,0xD1,0xD2,0xD3,0xF5,0xD4,0xF7,0xF8,0xF9,0xD5,0x96,0x95,0x98,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1	/* ASCII (for only non-LFN cfg) */
+#if _USE_LFN
+#error Cannot use LFN feature without valid code page.
+#endif
+#define _DF1S	0
+
+#else
+#error Unknown code page
+
+#endif
+
+/* Character code support macros */
+#define IsUpper(c)	(((c)>='A')&&((c)<='Z'))
+#define IsLower(c)	(((c)>='a')&&((c)<='z'))
+#define IsDigit(c)	(((c)>='0')&&((c)<='9'))
+
+#if _DF1S		/* Code page is DBCS */
+
+#ifdef _DF2S	/* Two 1st byte areas */
+#define IsDBCS1(c)	(((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) || ((BYTE)(c) >= _DF2S && (BYTE)(c) <= _DF2E))
+#else			/* One 1st byte area */
+#define IsDBCS1(c)	((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E)
+#endif
+
+#ifdef _DS3S	/* Three 2nd byte areas */
+#define IsDBCS2(c)	(((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E) || ((BYTE)(c) >= _DS3S && (BYTE)(c) <= _DS3E))
+#else			/* Two 2nd byte areas */
+#define IsDBCS2(c)	(((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E))
+#endif
+
+#else			/* Code page is SBCS */
+
+#define IsDBCS1(c)	0
+#define IsDBCS2(c)	0
+
+#endif /* _DF1S */
+
+/* Name status flags */
+#define NSFLAG		11		/* Index of name status byte in fn[] */
+#define NS_LOSS		0x01	/* Out of 8.3 format */
+#define NS_LFN		0x02	/* Force to create LFN entry */
+#define NS_LAST		0x04	/* Last segment */
+#define NS_BODY		0x08	/* Lower case flag (body) */
+#define NS_EXT		0x10	/* Lower case flag (ext) */
+#define NS_DOT		0x20	/* Dot entry */
+
+/* FAT sub-type boundaries (Differ from specs but correct for real DOS/Windows) */
+#define MIN_FAT16	4086U	/* Minimum number of clusters of FAT16 */
+#define	MIN_FAT32	65526U	/* Minimum number of clusters of FAT32 */
+
+/* FatFs refers the members in the FAT structures as byte array instead of
+/ structure members because the structure is not binary compatible between
+/ different platforms */
+
+#define BS_jmpBoot			0		/* x86 jump instruction (3) */
+#define BS_OEMName			3		/* OEM name (8) */
+#define BPB_BytsPerSec		11		/* Sector size [byte] (2) */
+#define BPB_SecPerClus		13		/* Cluster size [sector] (1) */
+#define BPB_RsvdSecCnt		14		/* Size of reserved area [sector] (2) */
+#define BPB_NumFATs			16		/* Number of FAT copies (1) */
+#define BPB_RootEntCnt		17		/* Number of root directory entries for FAT12/16 (2) */
+#define BPB_TotSec16		19		/* Volume size [sector] (2) */
+#define BPB_Media			21		/* Media descriptor (1) */
+#define BPB_FATSz16			22		/* FAT size [sector] (2) */
+#define BPB_SecPerTrk		24		/* Track size [sector] (2) */
+#define BPB_NumHeads		26		/* Number of heads (2) */
+#define BPB_HiddSec			28		/* Number of special hidden sectors (4) */
+#define BPB_TotSec32		32		/* Volume size [sector] (4) */
+#define BS_DrvNum			36		/* Physical drive number (1) */
+#define BS_NTres			37		/* Error flag (1) */
+#define BS_BootSig			38		/* Extended boot signature (1) */
+#define BS_VolID			39		/* Volume serial number (4) */
+#define BS_VolLab			43		/* Volume label (8) */
+#define BS_FilSysType		54		/* File system type (1) */
+#define BPB_FATSz32			36		/* FAT size [sector] (4) */
+#define BPB_ExtFlags		40		/* Extended flags (2) */
+#define BPB_FSVer			42		/* File system version (2) */
+#define BPB_RootClus		44		/* Root directory first cluster (4) */
+#define BPB_FSInfo			48		/* Offset of FSINFO sector (2) */
+#define BPB_BkBootSec		50		/* Offset of backup boot sector (2) */
+#define BS_DrvNum32			64		/* Physical drive number (1) */
+#define BS_NTres32			65		/* Error flag (1) */
+#define BS_BootSig32		66		/* Extended boot signature (1) */
+#define BS_VolID32			67		/* Volume serial number (4) */
+#define BS_VolLab32			71		/* Volume label (8) */
+#define BS_FilSysType32		82		/* File system type (1) */
+#define	FSI_LeadSig			0		/* FSI: Leading signature (4) */
+#define	FSI_StrucSig		484		/* FSI: Structure signature (4) */
+#define	FSI_Free_Count		488		/* FSI: Number of free clusters (4) */
+#define	FSI_Nxt_Free		492		/* FSI: Last allocated cluster (4) */
+#define MBR_Table			446		/* MBR: Partition table offset (2) */
+#define	SZ_PTE				16		/* MBR: Size of a partition table entry */
+#define BS_55AA				510		/* Signature word (2) */
+
+#define	DIR_Name			0		/* Short file name (11) */
+#define	DIR_Attr			11		/* Attribute (1) */
+#define	DIR_NTres			12		/* Lower case flag (1) */
+#define DIR_CrtTimeTenth	13		/* Created time sub-second (1) */
+#define	DIR_CrtTime			14		/* Created time (2) */
+#define	DIR_CrtDate			16		/* Created date (2) */
+#define DIR_LstAccDate		18		/* Last accessed date (2) */
+#define	DIR_FstClusHI		20		/* Higher 16-bit of first cluster (2) */
+#define	DIR_WrtTime			22		/* Modified time (2) */
+#define	DIR_WrtDate			24		/* Modified date (2) */
+#define	DIR_FstClusLO		26		/* Lower 16-bit of first cluster (2) */
+#define	DIR_FileSize		28		/* File size (4) */
+#define	LDIR_Ord			0		/* LFN entry order and LLE flag (1) */
+#define	LDIR_Attr			11		/* LFN attribute (1) */
+#define	LDIR_Type			12		/* LFN type (1) */
+#define	LDIR_Chksum			13		/* Checksum of corresponding SFN entry */
+#define	LDIR_FstClusLO		26		/* Must be zero (0) */
+#define	SZ_DIRE				32		/* Size of a directory entry */
+#define	LLEF				0x40	/* Last long entry flag in LDIR_Ord */
+#define	DDEM				0xE5	/* Deleted directory entry mark at DIR_Name[0] */
+#define	RDDEM				0x05	/* Replacement of the character collides with DDEM */
+
+/*--------------------------------------------------------------------------
+
+   Module Private Work Area
+
+---------------------------------------------------------------------------*/
+
+/* Remark: Uninitialized variables with static duration are guaranteed
+/  zero/null at start-up. If not, either the linker or start-up routine
+/  being used is not compliance with ANSI-C standard.
+*/
+
+#if _VOLUMES < 1 || _VOLUMES > 9
+#error Wrong _VOLUMES setting
+#endif
+static FATFS *FatFs[_VOLUMES];	/* Pointer to the file system objects (logical drives) */
+static WORD Fsid;				/* File system mount ID */
+
+#if _FS_RPATH && _VOLUMES >= 2
+static BYTE CurrVol;			/* Current drive */
+#endif
+
+#if _FS_LOCK
+static FILESEM Files[_FS_LOCK];	/* Open object lock semaphores */
+#endif
+
+#if _USE_LFN == 0			/* Non LFN feature */
+#define	DEFINE_NAMEBUF		BYTE sfn[12]
+#define INIT_BUF(dobj)		(dobj).fn = sfn
+#define	FREE_BUF()
+#else
+#if _MAX_LFN < 12 || _MAX_LFN > 255
+#error Wrong _MAX_LFN setting
+#endif
+#if _USE_LFN == 1			/* LFN feature with static working buffer */
+static WCHAR LfnBuf[_MAX_LFN + 1];
+#define	DEFINE_NAMEBUF		BYTE sfn[12]
+#define INIT_BUF(dobj)		{ (dobj).fn = sfn; (dobj).lfn = LfnBuf; }
+#define	FREE_BUF()
+#elif _USE_LFN == 2 		/* LFN feature with dynamic working buffer on the stack */
+#define	DEFINE_NAMEBUF		BYTE sfn[12]; WCHAR lbuf[_MAX_LFN + 1]
+#define INIT_BUF(dobj)		{ (dobj).fn = sfn; (dobj).lfn = lbuf; }
+#define	FREE_BUF()
+#elif _USE_LFN == 3 		/* LFN feature with dynamic working buffer on the heap */
+#define	DEFINE_NAMEBUF		BYTE sfn[12]; WCHAR *lfn
+#define INIT_BUF(dobj)		{ lfn = ff_memalloc((_MAX_LFN + 1) * 2); if (!lfn) LEAVE_FF((dobj).fs, FR_NOT_ENOUGH_CORE); (dobj).lfn = lfn; (dobj).fn = sfn; }
+#define	FREE_BUF()			ff_memfree(lfn)
+#else
+#error Wrong _USE_LFN setting
+#endif
+#endif
+
+#ifdef _EXCVT
+static const BYTE ExCvt[] = _EXCVT;	/* Upper conversion table for SBCS extended characters */
+#endif
+
+/*--------------------------------------------------------------------------
+
+   Module Private Functions
+
+---------------------------------------------------------------------------*/
+
+/*-----------------------------------------------------------------------*/
+/* String functions                                                      */
+/*-----------------------------------------------------------------------*/
+
+/* Copy memory to memory */
+static
+void mem_cpy (void* dst, const void* src, UINT cnt) {
+	BYTE *d = (BYTE*)dst;
+	const BYTE *s = (const BYTE*)src;
+
+#if _WORD_ACCESS == 1
+	while (cnt >= sizeof (int)) {
+		*(int*)d = *(int*)s;
+		d += sizeof (int); s += sizeof (int);
+		cnt -= sizeof (int);
+	}
+#endif
+	while (cnt--)
+		*d++ = *s++;
+}
+
+/* Fill memory */
+static
+void mem_set (void* dst, int val, UINT cnt) {
+	BYTE *d = (BYTE*)dst;
+
+	while (cnt--)
+		*d++ = (BYTE)val;
+}
+
+/* Compare memory to memory */
+static
+int mem_cmp (const void* dst, const void* src, UINT cnt) {
+	const BYTE *d = (const BYTE *)dst, *s = (const BYTE *)src;
+	int r = 0;
+
+	while (cnt-- && (r = *d++ - *s++) == 0) ;
+	return r;
+}
+
+/* Check if chr is contained in the string */
+static
+int chk_chr (const char* str, int chr) {
+	while (*str && *str != chr) str++;
+	return *str;
+}
+
+/*-----------------------------------------------------------------------*/
+/* Request/Release grant to access the volume                            */
+/*-----------------------------------------------------------------------*/
+#if _FS_REENTRANT
+static
+int lock_fs (
+	FATFS* fs		/* File system object */
+)
+{
+	return ff_req_grant(fs->sobj);
+}
+
+static
+void unlock_fs (
+	FATFS* fs,		/* File system object */
+	FRESULT res		/* Result code to be returned */
+)
+{
+	if (fs &&
+		res != FR_NOT_ENABLED &&
+		res != FR_INVALID_DRIVE &&
+		res != FR_INVALID_OBJECT &&
+		res != FR_TIMEOUT) {
+		ff_rel_grant(fs->sobj);
+	}
+}
+#endif
+
+/*-----------------------------------------------------------------------*/
+/* File lock control functions                                           */
+/*-----------------------------------------------------------------------*/
+#if _FS_LOCK
+
+static
+FRESULT chk_lock (	/* Check if the file can be accessed */
+	DIR* dp,		/* Directory object pointing the file to be checked */
+	int acc			/* Desired access type (0:Read, 1:Write, 2:Delete/Rename) */
+)
+{
+	UINT i, be;
+
+	/* Search file semaphore table */
+	for (i = be = 0; i < _FS_LOCK; i++) {
+		if (Files[i].fs) {	/* Existing entry */
+			if (Files[i].fs == dp->fs &&	 	/* Check if the object matched with an open object */
+				Files[i].clu == dp->sclust &&
+				Files[i].idx == dp->index) break;
+		} else {			/* Blank entry */
+			be = 1;
+		}
+	}
+	if (i == _FS_LOCK)	/* The object is not opened */
+		return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES;	/* Is there a blank entry for new object? */
+
+	/* The object has been opened. Reject any open against writing file and all write mode open */
+	return (acc || Files[i].ctr == 0x100) ? FR_LOCKED : FR_OK;
+}
+
+static
+int enq_lock (void)	/* Check if an entry is available for a new object */
+{
+	UINT i;
+
+	for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ;
+	return (i == _FS_LOCK) ? 0 : 1;
+}
+
+static
+UINT inc_lock (	/* Increment object open counter and returns its index (0:Internal error) */
+	DIR* dp,	/* Directory object pointing the file to register or increment */
+	int acc		/* Desired access (0:Read, 1:Write, 2:Delete/Rename) */
+)
+{
+	UINT i;
+
+	for (i = 0; i < _FS_LOCK; i++) {	/* Find the object */
+		if (Files[i].fs == dp->fs &&
+			Files[i].clu == dp->sclust &&
+			Files[i].idx == dp->index) break;
+	}
+
+	if (i == _FS_LOCK) {				/* Not opened. Register it as new. */
+		for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ;
+		if (i == _FS_LOCK) return 0;	/* No free entry to register (int err) */
+		Files[i].fs = dp->fs;
+		Files[i].clu = dp->sclust;
+		Files[i].idx = dp->index;
+		Files[i].ctr = 0;
+	}
+
+	if (acc && Files[i].ctr) return 0;	/* Access violation (int err) */
+
+	Files[i].ctr = acc ? 0x100 : Files[i].ctr + 1;	/* Set semaphore value */
+
+	return i + 1;
+}
+
+static
+FRESULT dec_lock (	/* Decrement object open counter */
+	UINT i			/* Semaphore index (1..) */
+)
+{
+	WORD n;
+	FRESULT res;
+
+	if (--i < _FS_LOCK) {	/* Shift index number origin from 0 */
+		n = Files[i].ctr;
+		if (n == 0x100) n = 0;		/* If write mode open, delete the entry */
+		if (n) n--;					/* Decrement read mode open count */
+		Files[i].ctr = n;
+		if (!n) Files[i].fs = 0;	/* Delete the entry if open count gets zero */
+		res = FR_OK;
+	} else {
+		res = FR_INT_ERR;			/* Invalid index nunber */
+	}
+	return res;
+}
+
+static
+void clear_lock (	/* Clear lock entries of the volume */
+	FATFS *fs
+)
+{
+	UINT i;
+
+	for (i = 0; i < _FS_LOCK; i++) {
+		if (Files[i].fs == fs) Files[i].fs = 0;
+	}
+}
+#endif
+
+/*-----------------------------------------------------------------------*/
+/* Move/Flush disk access window in the file system object               */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY
+static
+FRESULT sync_window (	/* FR_OK:succeeded, !=0:error */
+	FATFS* fs		/* File system object */
+)
+{
+	DWORD wsect;
+	UINT nf;
+	FRESULT res = FR_OK;
+
+	if (fs->wflag) {	/* Write back the sector if it is dirty */
+		wsect = fs->winsect;	/* Current sector number */
+		if (disk_write(fs->drv, fs->win, wsect, 1) != RES_OK) {
+			res = FR_DISK_ERR;
+		} else {
+			fs->wflag = 0;
+			if (wsect - fs->fatbase < fs->fsize) {		/* Is it in the FAT area? */
+				for (nf = fs->n_fats; nf >= 2; nf--) {	/* Reflect the change to all FAT copies */
+					wsect += fs->fsize;
+					disk_write(fs->drv, fs->win, wsect, 1);
+				}
+			}
+		}
+	}
+	return res;
+}
+#endif
+
+static
+FRESULT move_window (	/* FR_OK(0):succeeded, !=0:error */
+	FATFS* fs,		/* File system object */
+	DWORD sector	/* Sector number to make appearance in the fs->win[] */
+)
+{
+	FRESULT res = FR_OK;
+
+	if (sector != fs->winsect) {	/* Window offset changed? */
+#if !_FS_READONLY
+		res = sync_window(fs);		/* Write-back changes */
+#endif
+		if (res == FR_OK) {			/* Fill sector window with new data */
+			if (disk_read(fs->drv, fs->win, sector, 1) != RES_OK) {
+				sector = 0xFFFFFFFF;	/* Invalidate window if data is not reliable */
+				res = FR_DISK_ERR;
+			}
+			fs->winsect = sector;
+		}
+	}
+	return res;
+}
+
+/*-----------------------------------------------------------------------*/
+/* Synchronize file system and strage device                             */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY
+static
+FRESULT sync_fs (	/* FR_OK:succeeded, !=0:error */
+	FATFS* fs		/* File system object */
+)
+{
+	FRESULT res;
+
+	res = sync_window(fs);
+	if (res == FR_OK) {
+		/* Update FSInfo sector if needed */
+		if (fs->fs_type == FS_FAT32 && fs->fsi_flag == 1) {
+			/* Create FSInfo structure */
+			mem_set(fs->win, 0, SS(fs));
+			ST_WORD(fs->win + BS_55AA, 0xAA55);
+			ST_DWORD(fs->win + FSI_LeadSig, 0x41615252);
+			ST_DWORD(fs->win + FSI_StrucSig, 0x61417272);
+			ST_DWORD(fs->win + FSI_Free_Count, fs->free_clust);
+			ST_DWORD(fs->win + FSI_Nxt_Free, fs->last_clust);
+			/* Write it into the FSInfo sector */
+			fs->winsect = fs->volbase + 1;
+			disk_write(fs->drv, fs->win, fs->winsect, 1);
+			fs->fsi_flag = 0;
+		}
+		/* Make sure that no pending write process in the physical drive */
+		if (disk_ioctl(fs->drv, CTRL_SYNC, 0) != RES_OK)
+			res = FR_DISK_ERR;
+	}
+
+	return res;
+}
+#endif
+
+/*-----------------------------------------------------------------------*/
+/* Get sector# from cluster#                                             */
+/*-----------------------------------------------------------------------*/
+/* Hidden API for hacks and disk tools */
+
+DWORD clust2sect (	/* !=0:Sector number, 0:Failed (invalid cluster#) */
+	FATFS* fs,		/* File system object */
+	DWORD clst		/* Cluster# to be converted */
+)
+{
+	clst -= 2;
+	if (clst >= fs->n_fatent - 2) return 0;		/* Invalid cluster# */
+	return clst * fs->csize + fs->database;
+}
+
+/*-----------------------------------------------------------------------*/
+/* FAT access - Read value of a FAT entry                                */
+/*-----------------------------------------------------------------------*/
+/* Hidden API for hacks and disk tools */
+
+DWORD get_fat (	/* 0xFFFFFFFF:Disk error, 1:Internal error, 2..0x0FFFFFFF:Cluster status */
+	FATFS* fs,	/* File system object */
+	DWORD clst	/* FAT index number (cluster number) to get the value */
+)
+{
+	UINT wc, bc;
+	BYTE *p;
+	DWORD val;
+
+	if (clst < 2 || clst >= fs->n_fatent) {	/* Check if in valid range */
+		val = 1;	/* Internal error */
+
+	} else {
+		val = 0xFFFFFFFF;	/* Default value falls on disk error */
+
+		switch (fs->fs_type) {
+		case FS_FAT12 :
+			bc = (UINT)clst; bc += bc / 2;
+			if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break;
+			wc = fs->win[bc++ % SS(fs)];
+			if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break;
+			wc |= fs->win[bc % SS(fs)] << 8;
+			val = clst & 1 ? wc >> 4 : (wc & 0xFFF);
+			break;
+
+		case FS_FAT16 :
+			if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))) != FR_OK) break;
+			p = &fs->win[clst * 2 % SS(fs)];
+			val = LD_WORD(p);
+			break;
+
+		case FS_FAT32 :
+			if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break;
+			p = &fs->win[clst * 4 % SS(fs)];
+			val = LD_DWORD(p) & 0x0FFFFFFF;
+			break;
+
+		default:
+			val = 1;	/* Internal error */
+		}
+	}
+
+	return val;
+}
+
+/*-----------------------------------------------------------------------*/
+/* FAT access - Change value of a FAT entry                              */
+/*-----------------------------------------------------------------------*/
+/* Hidden API for hacks and disk tools */
+
+#if !_FS_READONLY
+FRESULT put_fat (	/* FR_OK(0):succeeded, !=0:error */
+	FATFS* fs,		/* File system object */
+	DWORD clst,		/* FAT index number (cluster number) to be changed */
+	DWORD val		/* New value to be set to the entry */
+)
+{
+	UINT bc;
+	BYTE *p;
+	FRESULT res;
+
+	if (clst < 2 || clst >= fs->n_fatent) {	/* Check if in valid range */
+		res = FR_INT_ERR;
+
+	} else {
+		switch (fs->fs_type) {
+		case FS_FAT12 :
+			bc = (UINT)clst; bc += bc / 2;
+			res = move_window(fs, fs->fatbase + (bc / SS(fs)));
+			if (res != FR_OK) break;
+			p = &fs->win[bc++ % SS(fs)];
+			*p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val;
+			fs->wflag = 1;
+			res = move_window(fs, fs->fatbase + (bc / SS(fs)));
+			if (res != FR_OK) break;
+			p = &fs->win[bc % SS(fs)];
+			*p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F));
+			fs->wflag = 1;
+			break;
+
+		case FS_FAT16 :
+			res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2)));
+			if (res != FR_OK) break;
+			p = &fs->win[clst * 2 % SS(fs)];
+			ST_WORD(p, (WORD)val);
+			fs->wflag = 1;
+			break;
+
+		case FS_FAT32 :
+			res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4)));
+			if (res != FR_OK) break;
+			p = &fs->win[clst * 4 % SS(fs)];
+			val |= LD_DWORD(p) & 0xF0000000;
+			ST_DWORD(p, val);
+			fs->wflag = 1;
+			break;
+
+		default :
+			res = FR_INT_ERR;
+		}
+	}
+
+	return res;
+}
+#endif /* !_FS_READONLY */
+
+/*-----------------------------------------------------------------------*/
+/* FAT handling - Remove a cluster chain                                 */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY
+static
+FRESULT remove_chain (	/* FR_OK(0):succeeded, !=0:error */
+	FATFS* fs,			/* File system object */
+	DWORD clst			/* Cluster# to remove a chain from */
+)
+{
+	FRESULT res;
+	DWORD nxt;
+#if _USE_TRIM
+	DWORD scl = clst, ecl = clst, rt[2];
+#endif
+
+	if (clst < 2 || clst >= fs->n_fatent) {	/* Check if in valid range */
+		res = FR_INT_ERR;
+
+	} else {
+		res = FR_OK;
+		while (clst < fs->n_fatent) {			/* Not a last link? */
+			nxt = get_fat(fs, clst);			/* Get cluster status */
+			if (nxt == 0) break;				/* Empty cluster? */
+			if (nxt == 1) { res = FR_INT_ERR; break; }	/* Internal error? */
+			if (nxt == 0xFFFFFFFF) { res = FR_DISK_ERR; break; }	/* Disk error? */
+			res = put_fat(fs, clst, 0);			/* Mark the cluster "empty" */
+			if (res != FR_OK) break;
+			if (fs->free_clust != 0xFFFFFFFF) {	/* Update FSINFO */
+				fs->free_clust++;
+				fs->fsi_flag |= 1;
+			}
+#if _USE_TRIM
+			if (ecl + 1 == nxt) {	/* Is next cluster contiguous? */
+				ecl = nxt;
+			} else {				/* End of contiguous clusters */ 
+				rt[0] = clust2sect(fs, scl);					/* Start sector */
+				rt[1] = clust2sect(fs, ecl) + fs->csize - 1;	/* End sector */
+				disk_ioctl(fs->drv, CTRL_TRIM, rt);				/* Erase the block */
+				scl = ecl = nxt;
+			}
+#endif
+			clst = nxt;	/* Next cluster */
+		}
+	}
+
+	return res;
+}
+#endif
+
+/*-----------------------------------------------------------------------*/
+/* FAT handling - Stretch or Create a cluster chain                      */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY
+static
+DWORD create_chain (	/* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */
+	FATFS* fs,			/* File system object */
+	DWORD clst			/* Cluster# to stretch, 0:Create a new chain */
+)
+{
+	DWORD cs, ncl, scl;
+	FRESULT res;
+
+	if (clst == 0) {		/* Create a new chain */
+		scl = fs->last_clust;			/* Get suggested start point */
+		if (!scl || scl >= fs->n_fatent) scl = 1;
+	}
+	else {					/* Stretch the current chain */
+		cs = get_fat(fs, clst);			/* Check the cluster status */
+		if (cs < 2) return 1;			/* Invalid value */
+		if (cs == 0xFFFFFFFF) return cs;	/* A disk error occurred */
+		if (cs < fs->n_fatent) return cs;	/* It is already followed by next cluster */
+		scl = clst;
+	}
+
+	ncl = scl;				/* Start cluster */
+	for (;;) {
+		ncl++;							/* Next cluster */
+		if (ncl >= fs->n_fatent) {		/* Check wrap around */
+			ncl = 2;
+			if (ncl > scl) return 0;	/* No free cluster */
+		}
+		cs = get_fat(fs, ncl);			/* Get the cluster status */
+		if (cs == 0) break;				/* Found a free cluster */
+		if (cs == 0xFFFFFFFF || cs == 1)/* An error occurred */
+			return cs;
+		if (ncl == scl) return 0;		/* No free cluster */
+	}
+
+	res = put_fat(fs, ncl, 0x0FFFFFFF);	/* Mark the new cluster "last link" */
+	if (res == FR_OK && clst != 0) {
+		res = put_fat(fs, clst, ncl);	/* Link it to the previous one if needed */
+	}
+	if (res == FR_OK) {
+		fs->last_clust = ncl;			/* Update FSINFO */
+		if (fs->free_clust != 0xFFFFFFFF) {
+			fs->free_clust--;
+			fs->fsi_flag |= 1;
+		}
+	} else {
+		ncl = (res == FR_DISK_ERR) ? 0xFFFFFFFF : 1;
+	}
+
+	return ncl;		/* Return new cluster number or error code */
+}
+#endif /* !_FS_READONLY */
+
+/*-----------------------------------------------------------------------*/
+/* FAT handling - Convert offset into cluster with link map table        */
+/*-----------------------------------------------------------------------*/
+
+#if _USE_FASTSEEK
+static
+DWORD clmt_clust (	/* <2:Error, >=2:Cluster number */
+	FIL* fp,		/* Pointer to the file object */
+	DWORD ofs		/* File offset to be converted to cluster# */
+)
+{
+	DWORD cl, ncl, *tbl;
+
+	tbl = fp->cltbl + 1;	/* Top of CLMT */
+	cl = ofs / SS(fp->fs) / fp->fs->csize;	/* Cluster order from top of the file */
+	for (;;) {
+		ncl = *tbl++;			/* Number of cluters in the fragment */
+		if (!ncl) return 0;		/* End of table? (error) */
+		if (cl < ncl) break;	/* In this fragment? */
+		cl -= ncl; tbl++;		/* Next fragment */
+	}
+	return cl + *tbl;	/* Return the cluster number */
+}
+#endif	/* _USE_FASTSEEK */
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Set directory index                              */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_sdi (	/* FR_OK(0):succeeded, !=0:error */
+	DIR* dp,		/* Pointer to directory object */
+	UINT idx		/* Index of directory table */
+)
+{
+	DWORD clst, sect;
+	UINT ic;
+
+	dp->index = (WORD)idx;	/* Current index */
+	clst = dp->sclust;		/* Table start cluster (0:root) */
+	if (clst == 1 || clst >= dp->fs->n_fatent)	/* Check start cluster range */
+		return FR_INT_ERR;
+	if (!clst && dp->fs->fs_type == FS_FAT32)	/* Replace cluster# 0 with root cluster# if in FAT32 */
+		clst = dp->fs->dirbase;
+
+	if (clst == 0) {	/* Static table (root-directory in FAT12/16) */
+		if (idx >= dp->fs->n_rootdir)	/* Is index out of range? */
+			return FR_INT_ERR;
+		sect = dp->fs->dirbase;
+	}
+	else {				/* Dynamic table (root-directory in FAT32 or sub-directory) */
+		ic = SS(dp->fs) / SZ_DIRE * dp->fs->csize;	/* Entries per cluster */
+		while (idx >= ic) {	/* Follow cluster chain */
+			clst = get_fat(dp->fs, clst);				/* Get next cluster */
+			if (clst == 0xFFFFFFFF) return FR_DISK_ERR;	/* Disk error */
+			if (clst < 2 || clst >= dp->fs->n_fatent)	/* Reached to end of table or internal error */
+				return FR_INT_ERR;
+			idx -= ic;
+		}
+		sect = clust2sect(dp->fs, clst);
+	}
+	dp->clust = clst;	/* Current cluster# */
+	if (!sect) return FR_INT_ERR;
+	dp->sect = sect + idx / (SS(dp->fs) / SZ_DIRE);					/* Sector# of the directory entry */
+	dp->dir = dp->fs->win + (idx % (SS(dp->fs) / SZ_DIRE)) * SZ_DIRE;	/* Ptr to the entry in the sector */
+
+	return FR_OK;
+}
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Move directory table index next                  */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_next (	/* FR_OK(0):succeeded, FR_NO_FILE:End of table, FR_DENIED:Could not stretch */
+	DIR* dp,		/* Pointer to the directory object */
+	int stretch		/* 0: Do not stretch table, 1: Stretch table if needed */
+)
+{
+	DWORD clst;
+	UINT i;
+#if !_FS_READONLY
+	UINT c;
+#endif
+
+	i = dp->index + 1;
+	if (!(i & 0xFFFF) || !dp->sect)	/* Report EOT when index has reached 65535 */
+		return FR_NO_FILE;
+
+	if (!(i % (SS(dp->fs) / SZ_DIRE))) {	/* Sector changed? */
+		dp->sect++;					/* Next sector */
+
+		if (!dp->clust) {		/* Static table */
+			if (i >= dp->fs->n_rootdir)	/* Report EOT if it reached end of static table */
+				return FR_NO_FILE;
+		}
+		else {					/* Dynamic table */
+			if (((i / (SS(dp->fs) / SZ_DIRE)) & (dp->fs->csize - 1)) == 0) {	/* Cluster changed? */
+				clst = get_fat(dp->fs, dp->clust);				/* Get next cluster */
+				if (clst <= 1) return FR_INT_ERR;
+				if (clst == 0xFFFFFFFF) return FR_DISK_ERR;
+				if (clst >= dp->fs->n_fatent) {					/* If it reached end of dynamic table, */
+#if !_FS_READONLY
+					if (!stretch) return FR_NO_FILE;			/* If do not stretch, report EOT */
+					clst = create_chain(dp->fs, dp->clust);		/* Stretch cluster chain */
+					if (clst == 0) return FR_DENIED;			/* No free cluster */
+					if (clst == 1) return FR_INT_ERR;
+					if (clst == 0xFFFFFFFF) return FR_DISK_ERR;
+					/* Clean-up stretched table */
+					if (sync_window(dp->fs)) return FR_DISK_ERR;/* Flush disk access window */
+					mem_set(dp->fs->win, 0, SS(dp->fs));		/* Clear window buffer */
+					dp->fs->winsect = clust2sect(dp->fs, clst);	/* Cluster start sector */
+					for (c = 0; c < dp->fs->csize; c++) {		/* Fill the new cluster with 0 */
+						dp->fs->wflag = 1;
+						if (sync_window(dp->fs)) return FR_DISK_ERR;
+						dp->fs->winsect++;
+					}
+					dp->fs->winsect -= c;						/* Rewind window offset */
+#else
+					if (!stretch) return FR_NO_FILE;			/* If do not stretch, report EOT (this is to suppress warning) */
+					return FR_NO_FILE;							/* Report EOT */
+#endif
+				}
+				dp->clust = clst;				/* Initialize data for new cluster */
+				dp->sect = clust2sect(dp->fs, clst);
+			}
+		}
+	}
+
+	dp->index = (WORD)i;	/* Current index */
+	dp->dir = dp->fs->win + (i % (SS(dp->fs) / SZ_DIRE)) * SZ_DIRE;	/* Current entry in the window */
+
+	return FR_OK;
+}
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Reserve directory entry                          */
+/*-----------------------------------------------------------------------*/
+
+#if !_FS_READONLY
+static
+FRESULT dir_alloc (	/* FR_OK(0):succeeded, !=0:error */
+	DIR* dp,		/* Pointer to the directory object */
+	UINT nent		/* Number of contiguous entries to allocate (1-21) */
+)
+{
+	FRESULT res;
+	UINT n;
+
+	res = dir_sdi(dp, 0);
+	if (res == FR_OK) {
+		n = 0;
+		do {
+			res = move_window(dp->fs, dp->sect);
+			if (res != FR_OK) break;
+			if (dp->dir[0] == DDEM || dp->dir[0] == 0) {	/* Is it a free entry? */
+				if (++n == nent) break;	/* A block of contiguous free entries is found */
+			} else {
+				n = 0;					/* Not a blank entry. Restart to search */
+			}
+			res = dir_next(dp, 1);		/* Next entry with table stretch enabled */
+		} while (res == FR_OK);
+	}
+	if (res == FR_NO_FILE) res = FR_DENIED;	/* No directory entry to allocate */
+	return res;
+}
+#endif
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Load/Store start cluster number                  */
+/*-----------------------------------------------------------------------*/
+
+static
+DWORD ld_clust (	/* Returns the top cluster value of the SFN entry */
+	FATFS* fs,		/* Pointer to the fs object */
+	const BYTE* dir	/* Pointer to the SFN entry */
+)
+{
+	DWORD cl;
+
+	cl = LD_WORD(dir + DIR_FstClusLO);
+	if (fs->fs_type == FS_FAT32)
+		cl |= (DWORD)LD_WORD(dir + DIR_FstClusHI) << 16;
+
+	return cl;
+}
+
+#if !_FS_READONLY
+static
+void st_clust (
+	BYTE* dir,	/* Pointer to the SFN entry */
+	DWORD cl	/* Value to be set */
+)
+{
+	ST_WORD(dir + DIR_FstClusLO, cl);
+	ST_WORD(dir + DIR_FstClusHI, cl >> 16);
+}
+#endif
+
+/*-----------------------------------------------------------------------*/
+/* LFN handling - Test/Pick/Fit an LFN segment from/to directory entry   */
+/*-----------------------------------------------------------------------*/
+#if _USE_LFN
+static
+const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30};	/* Offset of LFN characters in the directory entry */
+
+static
+int cmp_lfn (			/* 1:matched, 0:not matched */
+	WCHAR* lfnbuf,		/* Pointer to the LFN working buffer to be compared */
+	BYTE* dir			/* Pointer to the directory entry containing the part of LFN */
+)
+{
+	UINT i, s;
+	WCHAR wc, uc;
+
+	if (LD_WORD(dir + LDIR_FstClusLO) != 0) return 0;	/* Check LDIR_FstClusLO */
+
+	i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13;	/* Offset in the LFN buffer */
+
+	for (wc = 1, s = 0; s < 13; s++) {		/* Process all characters in the entry */
+		uc = LD_WORD(dir + LfnOfs[s]);		/* Pick an LFN character */
+		if (wc) {
+			if (i >= _MAX_LFN || ff_wtoupper(uc) != ff_wtoupper(lfnbuf[i++]))	/* Compare it */
+				return 0;					/* Not matched */
+			wc = uc;
+		} else {
+			if (uc != 0xFFFF) return 0;		/* Check filler */
+		}
+	}
+
+	if ((dir[LDIR_Ord] & LLEF) && wc && lfnbuf[i])	/* Last segment matched but different length */
+		return 0;
+
+	return 1;		/* The part of LFN matched */
+}
+
+static
+int pick_lfn (			/* 1:succeeded, 0:buffer overflow or invalid LFN entry */
+	WCHAR* lfnbuf,		/* Pointer to the LFN working buffer */
+	BYTE* dir			/* Pointer to the LFN entry */
+)
+{
+	UINT i, s;
+	WCHAR wc, uc;
+
+	if (LD_WORD(dir + LDIR_FstClusLO) != 0) return 0;	/* Check LDIR_FstClusLO */
+
+	i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13;	/* Offset in the LFN buffer */
+
+	for (wc = 1, s = 0; s < 13; s++) {		/* Process all characters in the entry */
+		uc = LD_WORD(dir + LfnOfs[s]);		/* Pick an LFN character */
+		if (wc) {
+			if (i >= _MAX_LFN) return 0;	/* Buffer overflow? */
+			lfnbuf[i++] = wc = uc;			/* Store it */
+		} else {
+			if (uc != 0xFFFF) return 0;		/* Check filler */
+		}
+	}
+
+	if (dir[LDIR_Ord] & LLEF) {				/* Put terminator if it is the last LFN part */
+		if (i >= _MAX_LFN) return 0;		/* Buffer overflow? */
+		lfnbuf[i] = 0;
+	}
+
+	return 1;		/* The part of LFN is valid */
+}
+
+#if !_FS_READONLY
+static
+void fit_lfn (
+	const WCHAR* lfnbuf,	/* Pointer to the LFN working buffer */
+	BYTE* dir,				/* Pointer to the LFN entry to be processed */
+	BYTE ord,				/* LFN order (1-20) */
+	BYTE sum				/* Checksum of the corresponding SFN */
+)
+{
+	UINT i, s;
+	WCHAR wc;
+
+	dir[LDIR_Chksum] = sum;			/* Set checksum */
+	dir[LDIR_Attr] = AM_LFN;		/* Set attribute. LFN entry */
+	dir[LDIR_Type] = 0;
+	ST_WORD(dir + LDIR_FstClusLO, 0);
+
+	i = (ord - 1) * 13;				/* Get offset in the LFN working buffer */
+	s = wc = 0;
+	do {
+		if (wc != 0xFFFF) wc = lfnbuf[i++];	/* Get an effective character */
+		ST_WORD(dir+LfnOfs[s], wc);	/* Put it */
+		if (!wc) wc = 0xFFFF;		/* Padding characters following last character */
+	} while (++s < 13);
+	if (wc == 0xFFFF || !lfnbuf[i]) ord |= LLEF;	/* Bottom LFN part is the start of LFN sequence */
+	dir[LDIR_Ord] = ord;			/* Set the LFN order */
+}
+
+#endif
+#endif
+
+/*-----------------------------------------------------------------------*/
+/* Create numbered name                                                  */
+/*-----------------------------------------------------------------------*/
+#if _USE_LFN
+static
+void gen_numname (
+	BYTE* dst,			/* Pointer to the buffer to store numbered SFN */
+	const BYTE* src,	/* Pointer to SFN */
+	const WCHAR* lfn,	/* Pointer to LFN */
+	UINT seq			/* Sequence number */
+)
+{
+	BYTE ns[8], c;
+	UINT i, j;
+	WCHAR wc;
+	DWORD sr;
+
+	mem_cpy(dst, src, 11);
+
+	if (seq > 5) {	/* On many collisions, generate a hash number instead of sequential number */
+		sr = seq;
+		while (*lfn) {	/* Create a CRC */
+			wc = *lfn++;
+			for (i = 0; i < 16; i++) {
+				sr = (sr << 1) + (wc & 1);
+				wc >>= 1;
+				if (sr & 0x10000) sr ^= 0x11021;
+			}
+		}
+		seq = (UINT)sr;
+	}
+
+	/* itoa (hexdecimal) */
+	i = 7;
+	do {
+		c = (seq % 16) + '0';
+		if (c > '9') c += 7;
+		ns[i--] = c;
+		seq /= 16;
+	} while (seq);
+	ns[i] = '~';
+
+	/* Append the number */
+	for (j = 0; j < i && dst[j] != ' '; j++) {
+		if (IsDBCS1(dst[j])) {
+			if (j == i - 1) break;
+			j++;
+		}
+	}
+	do {
+		dst[j++] = (i < 8) ? ns[i++] : ' ';
+	} while (j < 8);
+}
+#endif
+
+/*-----------------------------------------------------------------------*/
+/* Calculate checksum of an SFN entry                                    */
+/*-----------------------------------------------------------------------*/
+#if _USE_LFN
+static
+BYTE sum_sfn (
+	const BYTE* dir		/* Pointer to the SFN entry */
+)
+{
+	BYTE sum = 0;
+	UINT n = 11;
+
+	do sum = (sum >> 1) + (sum << 7) + *dir++; while (--n);
+	return sum;
+}
+#endif
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Find an object in the directory                  */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_find (	/* FR_OK(0):succeeded, !=0:error */
+	DIR* dp			/* Pointer to the directory object linked to the file name */
+)
+{
+	FRESULT res;
+	BYTE c, *dir;
+#if _USE_LFN
+	BYTE a, ord, sum;
+#endif
+
+	res = dir_sdi(dp, 0);			/* Rewind directory object */
+	if (res != FR_OK) return res;
+
+#if _USE_LFN
+	ord = sum = 0xFF; dp->lfn_idx = 0xFFFF;	/* Reset LFN sequence */
+#endif
+	do {
+		res = move_window(dp->fs, dp->sect);
+		if (res != FR_OK) break;
+		dir = dp->dir;					/* Ptr to the directory entry of current index */
+		c = dir[DIR_Name];
+		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
+#if _USE_LFN	/* LFN configuration */
+		a = dir[DIR_Attr] & AM_MASK;
+		if (c == DDEM || ((a & AM_VOL) && a != AM_LFN)) {	/* An entry without valid data */
+			ord = 0xFF; dp->lfn_idx = 0xFFFF;	/* Reset LFN sequence */
+		} else {
+			if (a == AM_LFN) {			/* An LFN entry is found */
+				if (dp->lfn) {
+					if (c & LLEF) {		/* Is it start of LFN sequence? */
+						sum = dir[LDIR_Chksum];
+						c &= ~LLEF; ord = c;	/* LFN start order */
+						dp->lfn_idx = dp->index;	/* Start index of LFN */
+					}
+					/* Check validity of the LFN entry and compare it with given name */
+					ord = (c == ord && sum == dir[LDIR_Chksum] && cmp_lfn(dp->lfn, dir)) ? ord - 1 : 0xFF;
+				}
+			} else {					/* An SFN entry is found */
+				if (!ord && sum == sum_sfn(dir)) break;	/* LFN matched? */
+				if (!(dp->fn[NSFLAG] & NS_LOSS) && !mem_cmp(dir, dp->fn, 11)) break;	/* SFN matched? */
+				ord = 0xFF; dp->lfn_idx = 0xFFFF;	/* Reset LFN sequence */
+			}
+		}
+#else		/* Non LFN configuration */
+		if (!(dir[DIR_Attr] & AM_VOL) && !mem_cmp(dir, dp->fn, 11)) /* Is it a valid entry? */
+			break;
+#endif
+		res = dir_next(dp, 0);		/* Next entry */
+	} while (res == FR_OK);
+
+	return res;
+}
+
+/*-----------------------------------------------------------------------*/
+/* Read an object from the directory                                     */
+/*-----------------------------------------------------------------------*/
+#if _FS_MINIMIZE <= 1 || _USE_LABEL || _FS_RPATH >= 2
+static
+FRESULT dir_read (
+	DIR* dp,		/* Pointer to the directory object */
+	int vol			/* Filtered by 0:file/directory or 1:volume label */
+)
+{
+	FRESULT res;
+	BYTE a, c, *dir;
+#if _USE_LFN
+	BYTE ord = 0xFF, sum = 0xFF;
+#endif
+
+	res = FR_NO_FILE;
+	while (dp->sect) {
+		res = move_window(dp->fs, dp->sect);
+		if (res != FR_OK) break;
+		dir = dp->dir;					/* Ptr to the directory entry of current index */
+		c = dir[DIR_Name];
+		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
+		a = dir[DIR_Attr] & AM_MASK;
+#if _USE_LFN	/* LFN configuration */
+		if (c == DDEM || (!_FS_RPATH && c == '.') || (int)((a & ~AM_ARC) == AM_VOL) != vol) {	/* An entry without valid data */
+			ord = 0xFF;
+		} else {
+			if (a == AM_LFN) {			/* An LFN entry is found */
+				if (c & LLEF) {			/* Is it start of LFN sequence? */
+					sum = dir[LDIR_Chksum];
+					c &= ~LLEF; ord = c;
+					dp->lfn_idx = dp->index;
+				}
+				/* Check LFN validity and capture it */
+				ord = (c == ord && sum == dir[LDIR_Chksum] && pick_lfn(dp->lfn, dir)) ? ord - 1 : 0xFF;
+			} else {					/* An SFN entry is found */
+				if (ord || sum != sum_sfn(dir))	/* Is there a valid LFN? */
+					dp->lfn_idx = 0xFFFF;		/* It has no LFN. */
+				break;
+			}
+		}
+#else		/* Non LFN configuration */
+		if (c != DDEM && (_FS_RPATH || c != '.') && a != AM_LFN && (int)((a & ~AM_ARC) == AM_VOL) == vol)	/* Is it a valid entry? */
+			break;
+#endif
+		res = dir_next(dp, 0);				/* Next entry */
+		if (res != FR_OK) break;
+	}
+
+	if (res != FR_OK) dp->sect = 0;
+
+	return res;
+}
+#endif	/* _FS_MINIMIZE <= 1 || _USE_LABEL || _FS_RPATH >= 2 */
+
+/*-----------------------------------------------------------------------*/
+/* Register an object to the directory                                   */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY
+static
+FRESULT dir_register (	/* FR_OK:succeeded, FR_DENIED:no free entry or too many SFN collision, FR_DISK_ERR:disk error */
+	DIR* dp				/* Target directory with object name to be created */
+)
+{
+	FRESULT res;
+#if _USE_LFN	/* LFN configuration */
+	UINT n, nent;
+	BYTE sn[12], *fn, sum;
+	WCHAR *lfn;
+
+	fn = dp->fn; lfn = dp->lfn;
+	mem_cpy(sn, fn, 12);
+
+	if (_FS_RPATH && (sn[NSFLAG] & NS_DOT))		/* Cannot create dot entry */
+		return FR_INVALID_NAME;
+
+	if (sn[NSFLAG] & NS_LOSS) {			/* When LFN is out of 8.3 format, generate a numbered name */
+		fn[NSFLAG] = 0; dp->lfn = 0;			/* Find only SFN */
+		for (n = 1; n < 100; n++) {
+			gen_numname(fn, sn, lfn, n);	/* Generate a numbered name */
+			res = dir_find(dp);				/* Check if the name collides with existing SFN */
+			if (res != FR_OK) break;
+		}
+		if (n == 100) return FR_DENIED;		/* Abort if too many collisions */
+		if (res != FR_NO_FILE) return res;	/* Abort if the result is other than 'not collided' */
+		fn[NSFLAG] = sn[NSFLAG]; dp->lfn = lfn;
+	}
+
+	if (sn[NSFLAG] & NS_LFN) {			/* When LFN is to be created, allocate entries for an SFN + LFNs. */
+		for (n = 0; lfn[n]; n++) ;
+		nent = (n + 25) / 13;
+	} else {						/* Otherwise allocate an entry for an SFN  */
+		nent = 1;
+	}
+	res = dir_alloc(dp, nent);		/* Allocate entries */
+
+	if (res == FR_OK && --nent) {	/* Set LFN entry if needed */
+		res = dir_sdi(dp, dp->index - nent);
+		if (res == FR_OK) {
+			sum = sum_sfn(dp->fn);	/* Checksum value of the SFN tied to the LFN */
+			do {					/* Store LFN entries in bottom first */
+				res = move_window(dp->fs, dp->sect);
+				if (res != FR_OK) break;
+				fit_lfn(dp->lfn, dp->dir, (BYTE)nent, sum);
+				dp->fs->wflag = 1;
+				res = dir_next(dp, 0);	/* Next entry */
+			} while (res == FR_OK && --nent);
+		}
+	}
+#else	/* Non LFN configuration */
+	res = dir_alloc(dp, 1);		/* Allocate an entry for SFN */
+#endif
+
+	if (res == FR_OK) {				/* Set SFN entry */
+		res = move_window(dp->fs, dp->sect);
+		if (res == FR_OK) {
+			mem_set(dp->dir, 0, SZ_DIRE);	/* Clean the entry */
+			mem_cpy(dp->dir, dp->fn, 11);	/* Put SFN */
+#if _USE_LFN
+			dp->dir[DIR_NTres] = dp->fn[NSFLAG] & (NS_BODY | NS_EXT);	/* Put NT flag */
+#endif
+			dp->fs->wflag = 1;
+		}
+	}
+
+	return res;
+}
+#endif /* !_FS_READONLY */
+
+/*-----------------------------------------------------------------------*/
+/* Remove an object from the directory                                   */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY && !_FS_MINIMIZE
+static
+FRESULT dir_remove (	/* FR_OK:Succeeded, FR_DISK_ERR:A disk error */
+	DIR* dp				/* Directory object pointing the entry to be removed */
+)
+{
+	FRESULT res;
+#if _USE_LFN	/* LFN configuration */
+	UINT i;
+
+	i = dp->index;	/* SFN index */
+	res = dir_sdi(dp, (dp->lfn_idx == 0xFFFF) ? i : dp->lfn_idx);	/* Goto the SFN or top of the LFN entries */
+	if (res == FR_OK) {
+		do {
+			res = move_window(dp->fs, dp->sect);
+			if (res != FR_OK) break;
+			mem_set(dp->dir, 0, SZ_DIRE);	/* Clear and mark the entry "deleted" */
+			*dp->dir = DDEM;
+			dp->fs->wflag = 1;
+			if (dp->index >= i) break;	/* When reached SFN, all entries of the object has been deleted. */
+			res = dir_next(dp, 0);		/* Next entry */
+		} while (res == FR_OK);
+		if (res == FR_NO_FILE) res = FR_INT_ERR;
+	}
+
+#else			/* Non LFN configuration */
+	res = dir_sdi(dp, dp->index);
+	if (res == FR_OK) {
+		res = move_window(dp->fs, dp->sect);
+		if (res == FR_OK) {
+			mem_set(dp->dir, 0, SZ_DIRE);	/* Clear and mark the entry "deleted" */
+			*dp->dir = DDEM;
+			dp->fs->wflag = 1;
+		}
+	}
+#endif
+
+	return res;
+}
+#endif /* !_FS_READONLY */
+
+/*-----------------------------------------------------------------------*/
+/* Get file information from directory entry                             */
+/*-----------------------------------------------------------------------*/
+#if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2
+static
+void get_fileinfo (		/* No return code */
+	DIR* dp,			/* Pointer to the directory object */
+	FILINFO* fno	 	/* Pointer to the file information to be filled */
+)
+{
+	UINT i;
+	TCHAR *p, c;
+	BYTE *dir;
+#if _USE_LFN
+	WCHAR w, *lfn;
+#endif
+
+	p = fno->fname;
+	if (dp->sect) {		/* Get SFN */
+		dir = dp->dir;
+		i = 0;
+		while (i < 11) {		/* Copy name body and extension */
+			c = (TCHAR)dir[i++];
+			if (c == ' ') continue;				/* Skip padding spaces */
+			if (c == RDDEM) c = (TCHAR)DDEM;	/* Restore replaced DDEM character */
+			if (i == 9) *p++ = '.';				/* Insert a . if extension is exist */
+#if _USE_LFN
+			if (IsUpper(c) && (dir[DIR_NTres] & (i >= 9 ? NS_EXT : NS_BODY)))
+				c += 0x20;			/* To lower */
+#if _LFN_UNICODE
+			if (IsDBCS1(c) && i != 8 && i != 11 && IsDBCS2(dir[i]))
+				c = c << 8 | dir[i++];
+			c = ff_convert(c, 1);	/* OEM -> Unicode */
+			if (!c) c = '?';
+#endif
+#endif
+			*p++ = c;
+		}
+		fno->fattrib = dir[DIR_Attr];				/* Attribute */
+		fno->fsize = LD_DWORD(dir + DIR_FileSize);	/* Size */
+		fno->fdate = LD_WORD(dir + DIR_WrtDate);	/* Date */
+		fno->ftime = LD_WORD(dir + DIR_WrtTime);	/* Time */
+	}
+	*p = 0;		/* Terminate SFN string by a \0 */
+
+#if _USE_LFN
+	if (fno->lfname) {
+		i = 0; p = fno->lfname;
+		if (dp->sect && fno->lfsize && dp->lfn_idx != 0xFFFF) {	/* Get LFN if available */
+			lfn = dp->lfn;
+			while ((w = *lfn++) != 0) {		/* Get an LFN character */
+#if !_LFN_UNICODE
+				w = ff_convert(w, 0);		/* Unicode -> OEM */
+				if (!w) { i = 0; break; }	/* No LFN if it could not be converted */
+				if (_DF1S && w >= 0x100)	/* Put 1st byte if it is a DBC (always false on SBCS cfg) */
+					p[i++] = (TCHAR)(w >> 8);
+#endif
+				if (i >= fno->lfsize - 1) { i = 0; break; }	/* No LFN if buffer overflow */
+				p[i++] = (TCHAR)w;
+			}
+		}
+		p[i] = 0;	/* Terminate LFN string by a \0 */
+	}
+#endif
+}
+#endif /* _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 */
+
+/*-----------------------------------------------------------------------*/
+/* Pattern matching                                                      */
+/*-----------------------------------------------------------------------*/
+#if _USE_FIND && _FS_MINIMIZE <= 1
+static
+WCHAR get_achar (		/* Get a character and advances ptr 1 or 2 */
+	const TCHAR** ptr	/* Pointer to pointer to the SBCS/DBCS/Unicode string */
+)
+{
+	WCHAR chr;
+
+#if !_LFN_UNICODE
+	chr = (BYTE)*(*ptr)++;					/* Get a byte */
+	if (IsLower(chr)) chr -= 0x20;			/* To upper ASCII char */
+	if (IsDBCS1(chr) && IsDBCS2(**ptr))		/* Get DBC 2nd byte if needed */
+		chr = chr << 8 | (BYTE)*(*ptr)++;
+#ifdef _EXCVT
+	if (chr >= 0x80) chr = ExCvt[chr - 0x80];	/* To upper SBCS extended char */
+#endif
+#else
+	chr = ff_wtoupper(*(*ptr)++);			/* Get a word and to upper */
+#endif
+	return chr;
+}
+
+static
+int pattern_matching (	/* 0:mismatched, 1:matched */
+	const TCHAR* pat,	/* Matching pattern */
+	const TCHAR* nam,	/* String to be tested */
+	int skip,			/* Number of pre-skip chars (number of ?s) */
+	int inf				/* Infinite search (* specified) */
+)
+{
+	const TCHAR *pp, *np;
+	WCHAR pc, nc;
+	int nm, nx;
+
+	while (skip--) {				/* Pre-skip name chars */
+		if (!get_achar(&nam)) return 0;	/* Branch mismatched if less name chars */
+	}
+	if (!*pat && inf) return 1;		/* (short circuit) */
+
+	do {
+		pp = pat; np = nam;			/* Top of pattern and name to match */
+		for (;;) {
+			if (*pp == '?' || *pp == '*') {	/* Wildcard? */
+				nm = nx = 0;
+				do {				/* Analyze the wildcard chars */
+					if (*pp++ == '?') nm++; else nx = 1;
+				} while (*pp == '?' || *pp == '*');
+				if (pattern_matching(pp, np, nm, nx)) return 1;	/* Test new branch (recurs upto number of wildcard blocks in the pattern) */
+				nc = *np; break;	/* Branch mismatched */
+			}
+			pc = get_achar(&pp);	/* Get a pattern char */
+			nc = get_achar(&np);	/* Get a name char */
+			if (pc != nc) break;	/* Branch mismatched? */
+			if (!pc) return 1;		/* Branch matched? (matched at end of both strings) */
+		}
+		get_achar(&nam);			/* nam++ */
+	} while (inf && nc);			/* Retry until end of name if infinite search is specified */
+
+	return 0;
+}
+#endif /* _USE_FIND && _FS_MINIMIZE <= 1 */
+
+/*-----------------------------------------------------------------------*/
+/* Pick a top segment and create the object name in directory form       */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT create_name (	/* FR_OK: successful, FR_INVALID_NAME: could not create */
+	DIR* dp,			/* Pointer to the directory object */
+	const TCHAR** path	/* Pointer to pointer to the segment in the path string */
+)
+{
+#if _USE_LFN	/* LFN configuration */
+	BYTE b, cf;
+	WCHAR w, *lfn;
+	UINT i, ni, si, di;
+	const TCHAR *p;
+
+	/* Create LFN in Unicode */
+	for (p = *path; *p == '/' || *p == '\\'; p++) ;	/* Strip duplicated separator */
+	lfn = dp->lfn;
+	si = di = 0;
+	for (;;) {
+		w = p[si++];					/* Get a character */
+		if (w < ' ' || w == '/' || w == '\\') break;	/* Break on end of segment */
+		if (di >= _MAX_LFN)				/* Reject too long name */
+			return FR_INVALID_NAME;
+#if !_LFN_UNICODE
+		w &= 0xFF;
+		if (IsDBCS1(w)) {				/* Check if it is a DBC 1st byte (always false on SBCS cfg) */
+			b = (BYTE)p[si++];			/* Get 2nd byte */
+			w = (w << 8) + b;			/* Create a DBC */
+			if (!IsDBCS2(b))
+				return FR_INVALID_NAME;	/* Reject invalid sequence */
+		}
+		w = ff_convert(w, 1);			/* Convert ANSI/OEM to Unicode */
+		if (!w) return FR_INVALID_NAME;	/* Reject invalid code */
+#endif
+		if (w < 0x80 && chk_chr("\"*:<>\?|\x7F", w)) /* Reject illegal characters for LFN */
+			return FR_INVALID_NAME;
+		lfn[di++] = w;					/* Store the Unicode character */
+	}
+	*path = &p[si];						/* Return pointer to the next segment */
+	cf = (w < ' ') ? NS_LAST : 0;		/* Set last segment flag if end of path */
+#if _FS_RPATH
+	if ((di == 1 && lfn[di - 1] == '.') ||
+		(di == 2 && lfn[di - 1] == '.' && lfn[di - 2] == '.')) {	/* Is this segment a dot entry? */
+		lfn[di] = 0;
+		for (i = 0; i < 11; i++)		/* Create dot name for SFN entry */
+			dp->fn[i] = (i < di) ? '.' : ' ';
+		dp->fn[i] = cf | NS_DOT;		/* This is a dot entry */
+		return FR_OK;
+	}
+#endif
+	while (di) {						/* Snip off trailing spaces and dots if exist */
+		w = lfn[di - 1];
+		if (w != ' ' && w != '.') break;
+		di--;
+	}
+	if (!di) return FR_INVALID_NAME;	/* Reject nul string */
+	lfn[di] = 0;						/* LFN is created */
+
+	/* Create SFN in directory form */
+	mem_set(dp->fn, ' ', 11);
+	for (si = 0; lfn[si] == ' ' || lfn[si] == '.'; si++) ;	/* Strip leading spaces and dots */
+	if (si) cf |= NS_LOSS | NS_LFN;
+	while (di && lfn[di - 1] != '.') di--;	/* Find extension (di<=si: no extension) */
+
+	b = i = 0; ni = 8;
+	for (;;) {
+		w = lfn[si++];					/* Get an LFN character */
+		if (!w) break;					/* Break on end of the LFN */
+		if (w == ' ' || (w == '.' && si != di)) {	/* Remove spaces and dots */
+			cf |= NS_LOSS | NS_LFN; continue;
+		}
+
+		if (i >= ni || si == di) {		/* Extension or end of SFN */
+			if (ni == 11) {				/* Long extension */
+				cf |= NS_LOSS | NS_LFN; break;
+			}
+			if (si != di) cf |= NS_LOSS | NS_LFN;	/* Out of 8.3 format */
+			if (si > di) break;			/* No extension */
+			si = di; i = 8; ni = 11;	/* Enter extension section */
+			b <<= 2; continue;
+		}
+
+		if (w >= 0x80) {				/* Non ASCII character */
+#ifdef _EXCVT
+			w = ff_convert(w, 0);		/* Unicode -> OEM code */
+			if (w) w = ExCvt[w - 0x80];	/* Convert extended character to upper (SBCS) */
+#else
+			w = ff_convert(ff_wtoupper(w), 0);	/* Upper converted Unicode -> OEM code */
+#endif
+			cf |= NS_LFN;				/* Force create LFN entry */
+		}
+
+		if (_DF1S && w >= 0x100) {		/* Is this DBC? (always false at SBCS cfg) */
+			if (i >= ni - 1) {
+				cf |= NS_LOSS | NS_LFN; i = ni; continue;
+			}
+			dp->fn[i++] = (BYTE)(w >> 8);
+		} else {						/* SBC */
+			if (!w || chk_chr("+,;=[]", w)) {	/* Replace illegal characters for SFN */
+				w = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */
+			} else {
+				if (IsUpper(w)) {		/* ASCII large capital */
+					b |= 2;
+				} else {
+					if (IsLower(w)) {	/* ASCII small capital */
+						b |= 1; w -= 0x20;
+					}
+				}
+			}
+		}
+		dp->fn[i++] = (BYTE)w;
+	}
+
+	if (dp->fn[0] == DDEM) dp->fn[0] = RDDEM;	/* If the first character collides with DDEM, replace it with RDDEM */
+
+	if (ni == 8) b <<= 2;
+	if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03)	/* Create LFN entry when there are composite capitals */
+		cf |= NS_LFN;
+	if (!(cf & NS_LFN)) {						/* When LFN is in 8.3 format without extended character, NT flags are created */
+		if ((b & 0x03) == 0x01) cf |= NS_EXT;	/* NT flag (Extension has only small capital) */
+		if ((b & 0x0C) == 0x04) cf |= NS_BODY;	/* NT flag (Filename has only small capital) */
+	}
+
+	dp->fn[NSFLAG] = cf;	/* SFN is created */
+
+	return FR_OK;
+
+#else	/* Non-LFN configuration */
+	BYTE b, c, d, *sfn;
+	UINT ni, si, i;
+	const char *p;
+
+	/* Create file name in directory form */
+	for (p = *path; *p == '/' || *p == '\\'; p++) ;	/* Skip duplicated separator */
+	sfn = dp->fn;
+	mem_set(sfn, ' ', 11);
+	si = i = b = 0; ni = 8;
+#if _FS_RPATH
+	if (p[si] == '.') { /* Is this a dot entry? */
+		for (;;) {
+			c = (BYTE)p[si++];
+			if (c != '.' || si >= 3) break;
+			sfn[i++] = c;
+		}
+		if (c != '/' && c != '\\' && c > ' ') return FR_INVALID_NAME;
+		*path = &p[si];									/* Return pointer to the next segment */
+		sfn[NSFLAG] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT;	/* Set last segment flag if end of path */
+		return FR_OK;
+	}
+#endif
+	for (;;) {
+		c = (BYTE)p[si++];
+		if (c <= ' ' || c == '/' || c == '\\') break;	/* Break on end of segment */
+		if (c == '.' || i >= ni) {
+			if (ni != 8 || c != '.') return FR_INVALID_NAME;
+			i = 8; ni = 11;
+			b <<= 2; continue;
+		}
+		if (c >= 0x80) {				/* Extended character? */
+			b |= 3;						/* Eliminate NT flag */
+#ifdef _EXCVT
+			c = ExCvt[c - 0x80];		/* To upper extended characters (SBCS cfg) */
+#else
+#if !_DF1S
+			return FR_INVALID_NAME;		/* Reject extended characters (ASCII cfg) */
+#endif
+#endif
+		}
+		if (IsDBCS1(c)) {				/* Check if it is a DBC 1st byte (always false at SBCS cfg.) */
+			d = (BYTE)p[si++];			/* Get 2nd byte */
+			if (!IsDBCS2(d) || i >= ni - 1)	/* Reject invalid DBC */
+				return FR_INVALID_NAME;
+			sfn[i++] = c;
+			sfn[i++] = d;
+		} else {						/* SBC */
+			if (chk_chr("\"*+,:;<=>\?[]|\x7F", c))	/* Reject illegal chrs for SFN */
+				return FR_INVALID_NAME;
+			if (IsUpper(c)) {			/* ASCII large capital? */
+				b |= 2;
+			} else {
+				if (IsLower(c)) {		/* ASCII small capital? */
+					b |= 1; c -= 0x20;
+				}
+			}
+			sfn[i++] = c;
+		}
+	}
+	*path = &p[si];						/* Return pointer to the next segment */
+	c = (c <= ' ') ? NS_LAST : 0;		/* Set last segment flag if end of path */
+
+	if (!i) return FR_INVALID_NAME;		/* Reject nul string */
+	if (sfn[0] == DDEM) sfn[0] = RDDEM;	/* When first character collides with DDEM, replace it with RDDEM */
+
+	if (ni == 8) b <<= 2;
+	if ((b & 0x03) == 0x01) c |= NS_EXT;	/* NT flag (Name extension has only small capital) */
+	if ((b & 0x0C) == 0x04) c |= NS_BODY;	/* NT flag (Name body has only small capital) */
+
+	sfn[NSFLAG] = c;		/* Store NT flag, File name is created */
+
+	return FR_OK;
+#endif
+}
+
+/*-----------------------------------------------------------------------*/
+/* Follow a file path                                                    */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT follow_path (	/* FR_OK(0): successful, !=0: error code */
+	DIR* dp,			/* Directory object to return last directory and found object */
+	const TCHAR* path	/* Full-path string to find a file or directory */
+)
+{
+	FRESULT res;
+	BYTE *dir, ns;
+
+#if _FS_RPATH
+	if (*path == '/' || *path == '\\') {	/* There is a heading separator */
+		path++;	dp->sclust = 0;				/* Strip it and start from the root directory */
+	} else {								/* No heading separator */
+		dp->sclust = dp->fs->cdir;			/* Start from the current directory */
+	}
+#else
+	if (*path == '/' || *path == '\\')		/* Strip heading separator if exist */
+		path++;
+	dp->sclust = 0;							/* Always start from the root directory */
+#endif
+
+	if ((UINT)*path < ' ') {				/* Null path name is the origin directory itself */
+		res = dir_sdi(dp, 0);
+		dp->dir = 0;
+	} else {								/* Follow path */
+		for (;;) {
+			res = create_name(dp, &path);	/* Get a segment name of the path */
+			if (res != FR_OK) break;
+			res = dir_find(dp);				/* Find an object with the sagment name */
+			ns = dp->fn[NSFLAG];
+			if (res != FR_OK) {				/* Failed to find the object */
+				if (res == FR_NO_FILE) {	/* Object is not found */
+					if (_FS_RPATH && (ns & NS_DOT)) {	/* If dot entry is not exist, */
+						dp->sclust = 0; dp->dir = 0;	/* it is the root directory and stay there */
+						if (!(ns & NS_LAST)) continue;	/* Continue to follow if not last segment */
+						res = FR_OK;					/* Ended at the root directroy. Function completed. */
+					} else {							/* Could not find the object */
+						if (!(ns & NS_LAST)) res = FR_NO_PATH;	/* Adjust error code if not last segment */
+					}
+				}
+				break;
+			}
+			if (ns & NS_LAST) break;			/* Last segment matched. Function completed. */
+			dir = dp->dir;						/* Follow the sub-directory */
+			if (!(dir[DIR_Attr] & AM_DIR)) {	/* It is not a sub-directory and cannot follow */
+				res = FR_NO_PATH; break;
+			}
+			dp->sclust = ld_clust(dp->fs, dir);
+		}
+	}
+
+	return res;
+}
+
+/*-----------------------------------------------------------------------*/
+/* Get logical drive number from path name                               */
+/*-----------------------------------------------------------------------*/
+
+static
+int get_ldnumber (		/* Returns logical drive number (-1:invalid drive) */
+	const TCHAR** path	/* Pointer to pointer to the path name */
+)
+{
+	const TCHAR *tp, *tt;
+	UINT i;
+	int vol = -1;
+#if _STR_VOLUME_ID		/* Find string drive id */
+	static const char* const str[] = {_VOLUME_STRS};
+	const char *sp;
+	char c;
+	TCHAR tc;
+#endif
+
+	if (*path) {	/* If the pointer is not a null */
+		for (tt = *path; (UINT)*tt >= (_USE_LFN ? ' ' : '!') && *tt != ':'; tt++) ;	/* Find ':' in the path */
+		if (*tt == ':') {	/* If a ':' is exist in the path name */
+			tp = *path;
+			i = *tp++ - '0'; 
+			if (i < 10 && tp == tt) {	/* Is there a numeric drive id? */
+				if (i < _VOLUMES) {	/* If a drive id is found, get the value and strip it */
+					vol = (int)i;
+					*path = ++tt;
+				}
+			}
+#if _STR_VOLUME_ID
+			 else {	/* No numeric drive number, find string drive id */
+				i = 0; tt++;
+				do {
+					sp = str[i]; tp = *path;
+					do {	/* Compare a string drive id with path name */
+						c = *sp++; tc = *tp++;
+						if (IsLower(tc)) tc -= 0x20;
+					} while (c && (TCHAR)c == tc);
+				} while ((c || tp != tt) && ++i < _VOLUMES);	/* Repeat for each id until pattern match */
+				if (i < _VOLUMES) {	/* If a drive id is found, get the value and strip it */
+					vol = (int)i;
+					*path = tt;
+				}
+			}
+#endif
+			return vol;
+		}
+#if _FS_RPATH && _VOLUMES >= 2
+		vol = CurrVol;	/* Current drive */
+#else
+		vol = 0;		/* Drive 0 */
+#endif
+	}
+	return vol;
+}
+
+/*-----------------------------------------------------------------------*/
+/* Load a sector and check if it is an FAT boot sector                   */
+/*-----------------------------------------------------------------------*/
+
+static
+BYTE check_fs (	/* 0:Valid FAT-BS, 1:Valid BS but not FAT, 2:Not a BS, 3:Disk error */
+	FATFS* fs,	/* File system object */
+	DWORD sect	/* Sector# (lba) to check if it is an FAT boot record or not */
+)
+{
+	fs->wflag = 0; fs->winsect = 0xFFFFFFFF;	/* Invaidate window */
+	if (move_window(fs, sect) != FR_OK)			/* Load boot record */
+		return 3;
+
+	if (LD_WORD(&fs->win[BS_55AA]) != 0xAA55)	/* Check boot record signature (always placed at offset 510 even if the sector size is >512) */
+		return 2;
+
+	if ((LD_DWORD(&fs->win[BS_FilSysType]) & 0xFFFFFF) == 0x544146)		/* Check "FAT" string */
+		return 0;
+	if ((LD_DWORD(&fs->win[BS_FilSysType32]) & 0xFFFFFF) == 0x544146)	/* Check "FAT" string */
+		return 0;
+
+	return 1;
+}
+
+/*-----------------------------------------------------------------------*/
+/* Find logical drive and check if the volume is mounted                 */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT find_volume (	/* FR_OK(0): successful, !=0: any error occurred */
+	FATFS** rfs,		/* Pointer to pointer to the found file system object */
+	const TCHAR** path,	/* Pointer to pointer to the path name (drive number) */
+	BYTE wmode			/* !=0: Check write protection for write access */
+)
+{
+	BYTE fmt, *pt;
+	int vol;
+	DSTATUS stat;
+	DWORD bsect, fasize, tsect, sysect, nclst, szbfat, br[4];
+	WORD nrsv;
+	FATFS *fs;
+	UINT i;
+
+	/* Get logical drive number from the path name */
+	*rfs = 0;
+	vol = get_ldnumber(path);
+	if (vol < 0) return FR_INVALID_DRIVE;
+
+	/* Check if the file system object is valid or not */
+	fs = FatFs[vol];					/* Get pointer to the file system object */
+	if (!fs) return FR_NOT_ENABLED;		/* Is the file system object available? */
+
+	ENTER_FF(fs);						/* Lock the volume */
+	*rfs = fs;							/* Return pointer to the file system object */
+
+	if (fs->fs_type) {					/* If the volume has been mounted */
+		stat = disk_status(fs->drv);
+		if (!(stat & STA_NOINIT)) {		/* and the physical drive is kept initialized */
+			if (!_FS_READONLY && wmode && (stat & STA_PROTECT))	/* Check write protection if needed */
+				return FR_WRITE_PROTECTED;
+			return FR_OK;				/* The file system object is valid */
+		}
+	}
+
+	/* The file system object is not valid. */
+	/* Following code attempts to mount the volume. (analyze BPB and initialize the fs object) */
+
+	fs->fs_type = 0;					/* Clear the file system object */
+	fs->drv = LD2PD(vol);				/* Bind the logical drive and a physical drive */
+	stat = disk_initialize(fs->drv);	/* Initialize the physical drive */
+	if (stat & STA_NOINIT)				/* Check if the initialization succeeded */
+		return FR_NOT_READY;			/* Failed to initialize due to no medium or hard error */
+	if (!_FS_READONLY && wmode && (stat & STA_PROTECT))	/* Check disk write protection if needed */
+		return FR_WRITE_PROTECTED;
+#if _MAX_SS != _MIN_SS						/* Get sector size (multiple sector size cfg only) */
+	if (disk_ioctl(fs->drv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK
+		|| SS(fs) < _MIN_SS || SS(fs) > _MAX_SS) return FR_DISK_ERR;
+#endif
+	/* Find an FAT partition on the drive. Supports only generic partitioning, FDISK and SFD. */
+	bsect = 0;
+	fmt = check_fs(fs, bsect);					/* Load sector 0 and check if it is an FAT boot sector as SFD */
+	if (fmt == 1 || (!fmt && (LD2PT(vol)))) {	/* Not an FAT boot sector or forced partition number */
+		for (i = 0; i < 4; i++) {			/* Get partition offset */
+			pt = fs->win + MBR_Table + i * SZ_PTE;
+			br[i] = pt[4] ? LD_DWORD(&pt[8]) : 0;
+		}
+		i = LD2PT(vol);						/* Partition number: 0:auto, 1-4:forced */
+		if (i) i--;
+		do {								/* Find an FAT volume */
+			bsect = br[i];
+			fmt = bsect ? check_fs(fs, bsect) : 2;	/* Check the partition */
+		} while (!LD2PT(vol) && fmt && ++i < 4);
+	}
+	if (fmt == 3) return FR_DISK_ERR;		/* An error occured in the disk I/O layer */
+	if (fmt) return FR_NO_FILESYSTEM;		/* No FAT volume is found */
+
+	/* An FAT volume is found. Following code initializes the file system object */
+
+	if (LD_WORD(fs->win + BPB_BytsPerSec) != SS(fs))	/* (BPB_BytsPerSec must be equal to the physical sector size) */
+		return FR_NO_FILESYSTEM;
+
+	fasize = LD_WORD(fs->win + BPB_FATSz16);			/* Number of sectors per FAT */
+	if (!fasize) fasize = LD_DWORD(fs->win + BPB_FATSz32);
+	fs->fsize = fasize;
+
+	fs->n_fats = fs->win[BPB_NumFATs];					/* Number of FAT copies */
+	if (fs->n_fats != 1 && fs->n_fats != 2)				/* (Must be 1 or 2) */
+		return FR_NO_FILESYSTEM;
+	fasize *= fs->n_fats;								/* Number of sectors for FAT area */
+
+	fs->csize = fs->win[BPB_SecPerClus];				/* Number of sectors per cluster */
+	if (!fs->csize || (fs->csize & (fs->csize - 1)))	/* (Must be power of 2) */
+		return FR_NO_FILESYSTEM;
+
+	fs->n_rootdir = LD_WORD(fs->win + BPB_RootEntCnt);	/* Number of root directory entries */
+	if (fs->n_rootdir % (SS(fs) / SZ_DIRE))				/* (Must be sector aligned) */
+		return FR_NO_FILESYSTEM;
+
+	tsect = LD_WORD(fs->win + BPB_TotSec16);			/* Number of sectors on the volume */
+	if (!tsect) tsect = LD_DWORD(fs->win + BPB_TotSec32);
+
+	nrsv = LD_WORD(fs->win + BPB_RsvdSecCnt);			/* Number of reserved sectors */
+	if (!nrsv) return FR_NO_FILESYSTEM;					/* (Must not be 0) */
+
+	/* Determine the FAT sub type */
+	sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / SZ_DIRE);	/* RSV + FAT + DIR */
+	if (tsect < sysect) return FR_NO_FILESYSTEM;		/* (Invalid volume size) */
+	nclst = (tsect - sysect) / fs->csize;				/* Number of clusters */
+	if (!nclst) return FR_NO_FILESYSTEM;				/* (Invalid volume size) */
+	fmt = FS_FAT12;
+	if (nclst >= MIN_FAT16) fmt = FS_FAT16;
+	if (nclst >= MIN_FAT32) fmt = FS_FAT32;
+
+	/* Boundaries and Limits */
+	fs->n_fatent = nclst + 2;							/* Number of FAT entries */
+	fs->volbase = bsect;								/* Volume start sector */
+	fs->fatbase = bsect + nrsv; 						/* FAT start sector */
+	fs->database = bsect + sysect;						/* Data start sector */
+	if (fmt == FS_FAT32) {
+		if (fs->n_rootdir) return FR_NO_FILESYSTEM;		/* (BPB_RootEntCnt must be 0) */
+		fs->dirbase = LD_DWORD(fs->win + BPB_RootClus);	/* Root directory start cluster */
+		szbfat = fs->n_fatent * 4;						/* (Needed FAT size) */
+	} else {
+		if (!fs->n_rootdir)	return FR_NO_FILESYSTEM;	/* (BPB_RootEntCnt must not be 0) */
+		fs->dirbase = fs->fatbase + fasize;				/* Root directory start sector */
+		szbfat = (fmt == FS_FAT16) ?					/* (Needed FAT size) */
+			fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1);
+	}
+	if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs))	/* (BPB_FATSz must not be less than the size needed) */
+		return FR_NO_FILESYSTEM;
+
+#if !_FS_READONLY
+	/* Initialize cluster allocation information */
+	fs->last_clust = fs->free_clust = 0xFFFFFFFF;
+
+	/* Get fsinfo if available */
+	fs->fsi_flag = 0x80;
+#if (_FS_NOFSINFO & 3) != 3
+	if (fmt == FS_FAT32				/* Enable FSINFO only if FAT32 and BPB_FSInfo == 1 */
+		&& LD_WORD(fs->win + BPB_FSInfo) == 1
+		&& move_window(fs, bsect + 1) == FR_OK)
+	{
+		fs->fsi_flag = 0;
+		if (LD_WORD(fs->win + BS_55AA) == 0xAA55	/* Load FSINFO data if available */
+			&& LD_DWORD(fs->win + FSI_LeadSig) == 0x41615252
+			&& LD_DWORD(fs->win + FSI_StrucSig) == 0x61417272)
+		{
+#if (_FS_NOFSINFO & 1) == 0
+			fs->free_clust = LD_DWORD(fs->win + FSI_Free_Count);
+#endif
+#if (_FS_NOFSINFO & 2) == 0
+			fs->last_clust = LD_DWORD(fs->win + FSI_Nxt_Free);
+#endif
+		}
+	}
+#endif
+#endif
+	fs->fs_type = fmt;	/* FAT sub-type */
+	fs->id = ++Fsid;	/* File system mount ID */
+#if _FS_RPATH
+	fs->cdir = 0;		/* Set current directory to root */
+#endif
+#if _FS_LOCK			/* Clear file lock semaphores */
+	clear_lock(fs);
+#endif
+
+	return FR_OK;
+}
+
+/*-----------------------------------------------------------------------*/
+/* Check if the file/directory object is valid or not                    */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT validate (	/* FR_OK(0): The object is valid, !=0: Invalid */
+	void* obj		/* Pointer to the object FIL/DIR to check validity */
+)
+{
+	FIL *fil = (FIL*)obj;	/* Assuming offset of .fs and .id in the FIL/DIR structure is identical */
+
+	if (!fil || !fil->fs || !fil->fs->fs_type || fil->fs->id != fil->id || (disk_status(fil->fs->drv) & STA_NOINIT))
+		return FR_INVALID_OBJECT;
+
+	ENTER_FF(fil->fs);		/* Lock file system */
+
+	return FR_OK;
+}
+
+/*--------------------------------------------------------------------------
+
+   Public Functions
+
+---------------------------------------------------------------------------*/
+
+/*-----------------------------------------------------------------------*/
+/* Mount/Unmount a Logical Drive                                         */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_mount (
+	FATFS* fs,			/* Pointer to the file system object (NULL:unmount)*/
+	const TCHAR* path,	/* Logical drive number to be mounted/unmounted */
+	BYTE opt			/* 0:Do not mount (delayed mount), 1:Mount immediately */
+)
+{
+	FATFS *cfs;
+	int vol;
+	FRESULT res;
+	const TCHAR *rp = path;
+
+	vol = get_ldnumber(&rp);
+	if (vol < 0) return FR_INVALID_DRIVE;
+	cfs = FatFs[vol];					/* Pointer to fs object */
+
+	if (cfs) {
+#if _FS_LOCK
+		clear_lock(cfs);
+#endif
+#if _FS_REENTRANT						/* Discard sync object of the current volume */
+		if (!ff_del_syncobj(cfs->sobj)) return FR_INT_ERR;
+#endif
+		cfs->fs_type = 0;				/* Clear old fs object */
+	}
+
+	if (fs) {
+		fs->fs_type = 0;				/* Clear new fs object */
+#if _FS_REENTRANT						/* Create sync object for the new volume */
+		if (!ff_cre_syncobj((BYTE)vol, &fs->sobj)) return FR_INT_ERR;
+#endif
+	}
+	FatFs[vol] = fs;					/* Register new fs object */
+
+	if (!fs || opt != 1) return FR_OK;	/* Do not mount now, it will be mounted later */
+
+	res = find_volume(&fs, &path, 0);	/* Force mounted the volume */
+	LEAVE_FF(fs, res);
+}
+
+/*-----------------------------------------------------------------------*/
+/* Open or Create a File                                                 */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_open (
+	FIL* fp,			/* Pointer to the blank file object */
+	const TCHAR* path,	/* Pointer to the file name */
+	BYTE mode			/* Access mode and file open mode flags */
+)
+{
+	FRESULT res;
+	DIR dj;
+	BYTE *dir;
+	DEFINE_NAMEBUF;
+#if !_FS_READONLY
+	DWORD dw, cl;
+#endif
+
+	if (!fp) return FR_INVALID_OBJECT;
+	fp->fs = 0;			/* Clear file object */
+
+	/* Get logical drive number */
+#if !_FS_READONLY
+	mode &= FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW;
+	res = find_volume(&dj.fs, &path, (BYTE)(mode & ~FA_READ));
+#else
+	mode &= FA_READ;
+	res = find_volume(&dj.fs, &path, 0);
+#endif
+	if (res == FR_OK) {
+		INIT_BUF(dj);
+		res = follow_path(&dj, path);	/* Follow the file path */
+		dir = dj.dir;
+#if !_FS_READONLY	/* R/W configuration */
+		if (res == FR_OK) {
+			if (!dir)	/* Default directory itself */
+				res = FR_INVALID_NAME;
+#if _FS_LOCK
+			else
+				res = chk_lock(&dj, (mode & ~FA_READ) ? 1 : 0);
+#endif
+		}
+		/* Create or Open a file */
+		if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) {
+			if (res != FR_OK) {					/* No file, create new */
+				if (res == FR_NO_FILE)			/* There is no file to open, create a new entry */
+#if _FS_LOCK
+					res = enq_lock() ? dir_register(&dj) : FR_TOO_MANY_OPEN_FILES;
+#else
+					res = dir_register(&dj);
+#endif
+				mode |= FA_CREATE_ALWAYS;		/* File is created */
+				dir = dj.dir;					/* New entry */
+			}
+			else {								/* Any object is already existing */
+				if (dir[DIR_Attr] & (AM_RDO | AM_DIR)) {	/* Cannot overwrite it (R/O or DIR) */
+					res = FR_DENIED;
+				} else {
+					if (mode & FA_CREATE_NEW)	/* Cannot create as new file */
+						res = FR_EXIST;
+				}
+			}
+			if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) {	/* Truncate it if overwrite mode */
+				dw = GET_FATTIME();
+				ST_DWORD(dir + DIR_CrtTime, dw);/* Set created time */
+				ST_DWORD(dir + DIR_WrtTime, dw);/* Set modified time */
+				dir[DIR_Attr] = 0;				/* Reset attribute */
+				ST_DWORD(dir + DIR_FileSize, 0);/* Reset file size */
+				cl = ld_clust(dj.fs, dir);		/* Get cluster chain */
+				st_clust(dir, 0);				/* Reset cluster */
+				dj.fs->wflag = 1;
+				if (cl) {						/* Remove the cluster chain if exist */
+					dw = dj.fs->winsect;
+					res = remove_chain(dj.fs, cl);
+					if (res == FR_OK) {
+						dj.fs->last_clust = cl - 1;	/* Reuse the cluster hole */
+						res = move_window(dj.fs, dw);
+					}
+				}
+			}
+		}
+		else {	/* Open an existing file */
+			if (res == FR_OK) {					/* Following succeeded */
+				if (dir[DIR_Attr] & AM_DIR) {	/* It is a directory */
+					res = FR_NO_FILE;
+				} else {
+					if ((mode & FA_WRITE) && (dir[DIR_Attr] & AM_RDO)) /* R/O violation */
+						res = FR_DENIED;
+				}
+			}
+		}
+		if (res == FR_OK) {
+			if (mode & FA_CREATE_ALWAYS)		/* Set file change flag if created or overwritten */
+				mode |= FA__WRITTEN;
+			fp->dir_sect = dj.fs->winsect;		/* Pointer to the directory entry */
+			fp->dir_ptr = dir;
+#if _FS_LOCK
+			fp->lockid = inc_lock(&dj, (mode & ~FA_READ) ? 1 : 0);
+			if (!fp->lockid) res = FR_INT_ERR;
+#endif
+		}
+
+#else				/* R/O configuration */
+		if (res == FR_OK) {					/* Follow succeeded */
+			dir = dj.dir;
+			if (!dir) {						/* Current directory itself */
+				res = FR_INVALID_NAME;
+			} else {
+				if (dir[DIR_Attr] & AM_DIR)	/* It is a directory */
+					res = FR_NO_FILE;
+			}
+		}
+#endif
+		FREE_BUF();
+
+		if (res == FR_OK) {
+			fp->flag = mode;					/* File access mode */
+			fp->err = 0;						/* Clear error flag */
+			fp->sclust = ld_clust(dj.fs, dir);	/* File start cluster */
+			fp->fsize = LD_DWORD(dir + DIR_FileSize);	/* File size */
+			fp->fptr = 0;						/* File pointer */
+			fp->dsect = 0;
+#if _USE_FASTSEEK
+			fp->cltbl = 0;						/* Normal seek mode */
+#endif
+			fp->fs = dj.fs;	 					/* Validate file object */
+			fp->id = fp->fs->id;
+		}
+	}
+
+	LEAVE_FF(dj.fs, res);
+}
+
+/*-----------------------------------------------------------------------*/
+/* Read File                                                             */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_read (
+	FIL* fp, 		/* Pointer to the file object */
+	void* buff,		/* Pointer to data buffer */
+	UINT btr,		/* Number of bytes to read */
+	UINT* br		/* Pointer to number of bytes read */
+)
+{
+	FRESULT res;
+	DWORD clst, sect, remain;
+	UINT rcnt, cc;
+	BYTE csect, *rbuff = (BYTE*)buff;
+
+	*br = 0;	/* Clear read byte counter */
+
+	res = validate(fp);							/* Check validity */
+	if (res != FR_OK) LEAVE_FF(fp->fs, res);
+	if (fp->err)								/* Check error */
+		LEAVE_FF(fp->fs, (FRESULT)fp->err);
+	if (!(fp->flag & FA_READ)) 					/* Check access mode */
+		LEAVE_FF(fp->fs, FR_DENIED);
+	remain = fp->fsize - fp->fptr;
+	if (btr > remain) btr = (UINT)remain;		/* Truncate btr by remaining bytes */
+
+	for ( ;  btr;								/* Repeat until all data read */
+		rbuff += rcnt, fp->fptr += rcnt, *br += rcnt, btr -= rcnt) {
+		if ((fp->fptr % SS(fp->fs)) == 0) {		/* On the sector boundary? */
+			csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1));	/* Sector offset in the cluster */
+			if (!csect) {						/* On the cluster boundary? */
+				if (fp->fptr == 0) {			/* On the top of the file? */
+					clst = fp->sclust;			/* Follow from the origin */
+				} else {						/* Middle or end of the file */
+#if _USE_FASTSEEK
+					if (fp->cltbl)
+						clst = clmt_clust(fp, fp->fptr);	/* Get cluster# from the CLMT */
+					else
+#endif
+						clst = get_fat(fp->fs, fp->clust);	/* Follow cluster chain on the FAT */
+				}
+				if (clst < 2) ABORT(fp->fs, FR_INT_ERR);
+				if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
+				fp->clust = clst;				/* Update current cluster */
+			}
+			sect = clust2sect(fp->fs, fp->clust);	/* Get current sector */
+			if (!sect) ABORT(fp->fs, FR_INT_ERR);
+			sect += csect;
+			cc = btr / SS(fp->fs);				/* When remaining bytes >= sector size, */
+			if (cc) {							/* Read maximum contiguous sectors directly */
+				if (csect + cc > fp->fs->csize)	/* Clip at cluster boundary */
+					cc = fp->fs->csize - csect;
+				if (disk_read(fp->fs->drv, rbuff, sect, cc) != RES_OK)
+					ABORT(fp->fs, FR_DISK_ERR);
+#if !_FS_READONLY && _FS_MINIMIZE <= 2			/* Replace one of the read sectors with cached data if it contains a dirty sector */
+#if _FS_TINY
+				if (fp->fs->wflag && fp->fs->winsect - sect < cc)
+					mem_cpy(rbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), fp->fs->win, SS(fp->fs));
+#else
+				if ((fp->flag & FA__DIRTY) && fp->dsect - sect < cc)
+					mem_cpy(rbuff + ((fp->dsect - sect) * SS(fp->fs)), fp->buf, SS(fp->fs));
+#endif
+#endif
+				rcnt = SS(fp->fs) * cc;			/* Number of bytes transferred */
+				continue;
+			}
+#if !_FS_TINY
+			if (fp->dsect != sect) {			/* Load data sector if not in cache */
+#if !_FS_READONLY
+				if (fp->flag & FA__DIRTY) {		/* Write-back dirty sector cache */
+					if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
+						ABORT(fp->fs, FR_DISK_ERR);
+					fp->flag &= ~FA__DIRTY;
+				}
+#endif
+				if (disk_read(fp->fs->drv, fp->buf, sect, 1) != RES_OK)	/* Fill sector cache */
+					ABORT(fp->fs, FR_DISK_ERR);
+			}
+#endif
+			fp->dsect = sect;
+		}
+		rcnt = SS(fp->fs) - ((UINT)fp->fptr % SS(fp->fs));	/* Get partial sector data from sector buffer */
+		if (rcnt > btr) rcnt = btr;
+#if _FS_TINY
+		if (move_window(fp->fs, fp->dsect) != FR_OK)		/* Move sector window */
+			ABORT(fp->fs, FR_DISK_ERR);
+		mem_cpy(rbuff, &fp->fs->win[fp->fptr % SS(fp->fs)], rcnt);	/* Pick partial sector */
+#else
+		mem_cpy(rbuff, &fp->buf[fp->fptr % SS(fp->fs)], rcnt);	/* Pick partial sector */
+#endif
+	}
+
+	LEAVE_FF(fp->fs, FR_OK);
+}
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Write File                                                            */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_write (
+	FIL* fp,			/* Pointer to the file object */
+	const void *buff,	/* Pointer to the data to be written */
+	UINT btw,			/* Number of bytes to write */
+	UINT* bw			/* Pointer to number of bytes written */
+)
+{
+	FRESULT res;
+	DWORD clst, sect;
+	UINT wcnt, cc;
+	const BYTE *wbuff = (const BYTE*)buff;
+	BYTE csect;
+
+	*bw = 0;	/* Clear write byte counter */
+
+	res = validate(fp);						/* Check validity */
+	if (res != FR_OK) LEAVE_FF(fp->fs, res);
+	if (fp->err)							/* Check error */
+		LEAVE_FF(fp->fs, (FRESULT)fp->err);
+	if (!(fp->flag & FA_WRITE))				/* Check access mode */
+		LEAVE_FF(fp->fs, FR_DENIED);
+	if (fp->fptr + btw < fp->fptr) btw = 0;	/* File size cannot reach 4GB */
+
+	for ( ;  btw;							/* Repeat until all data written */
+		wbuff += wcnt, fp->fptr += wcnt, *bw += wcnt, btw -= wcnt) {
+		if ((fp->fptr % SS(fp->fs)) == 0) {	/* On the sector boundary? */
+			csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1));	/* Sector offset in the cluster */
+			if (!csect) {					/* On the cluster boundary? */
+				if (fp->fptr == 0) {		/* On the top of the file? */
+					clst = fp->sclust;		/* Follow from the origin */
+					if (clst == 0)			/* When no cluster is allocated, */
+						clst = create_chain(fp->fs, 0);	/* Create a new cluster chain */
+				} else {					/* Middle or end of the file */
+#if _USE_FASTSEEK
+					if (fp->cltbl)
+						clst = clmt_clust(fp, fp->fptr);	/* Get cluster# from the CLMT */
+					else
+#endif
+						clst = create_chain(fp->fs, fp->clust);	/* Follow or stretch cluster chain on the FAT */
+				}
+				if (clst == 0) break;		/* Could not allocate a new cluster (disk full) */
+				if (clst == 1) ABORT(fp->fs, FR_INT_ERR);
+				if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
+				fp->clust = clst;			/* Update current cluster */
+				if (fp->sclust == 0) fp->sclust = clst;	/* Set start cluster if the first write */
+			}
+#if _FS_TINY
+			if (fp->fs->winsect == fp->dsect && sync_window(fp->fs))	/* Write-back sector cache */
+				ABORT(fp->fs, FR_DISK_ERR);
+#else
+			if (fp->flag & FA__DIRTY) {		/* Write-back sector cache */
+				if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
+					ABORT(fp->fs, FR_DISK_ERR);
+				fp->flag &= ~FA__DIRTY;
+			}
+#endif
+			sect = clust2sect(fp->fs, fp->clust);	/* Get current sector */
+			if (!sect) ABORT(fp->fs, FR_INT_ERR);
+			sect += csect;
+			cc = btw / SS(fp->fs);			/* When remaining bytes >= sector size, */
+			if (cc) {						/* Write maximum contiguous sectors directly */
+				if (csect + cc > fp->fs->csize)	/* Clip at cluster boundary */
+					cc = fp->fs->csize - csect;
+				if (disk_write(fp->fs->drv, wbuff, sect, cc) != RES_OK)
+					ABORT(fp->fs, FR_DISK_ERR);
+#if _FS_MINIMIZE <= 2
+#if _FS_TINY
+				if (fp->fs->winsect - sect < cc) {	/* Refill sector cache if it gets invalidated by the direct write */
+					mem_cpy(fp->fs->win, wbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), SS(fp->fs));
+					fp->fs->wflag = 0;
+				}
+#else
+				if (fp->dsect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */
+					mem_cpy(fp->buf, wbuff + ((fp->dsect - sect) * SS(fp->fs)), SS(fp->fs));
+					fp->flag &= ~FA__DIRTY;
+				}
+#endif
+#endif
+				wcnt = SS(fp->fs) * cc;		/* Number of bytes transferred */
+				continue;
+			}
+#if _FS_TINY
+			if (fp->fptr >= fp->fsize) {	/* Avoid silly cache filling at growing edge */
+				if (sync_window(fp->fs)) ABORT(fp->fs, FR_DISK_ERR);
+				fp->fs->winsect = sect;
+			}
+#else
+			if (fp->dsect != sect) {		/* Fill sector cache with file data */
+				if (fp->fptr < fp->fsize &&
+					disk_read(fp->fs->drv, fp->buf, sect, 1) != RES_OK)
+						ABORT(fp->fs, FR_DISK_ERR);
+			}
+#endif
+			fp->dsect = sect;
+		}
+		wcnt = SS(fp->fs) - ((UINT)fp->fptr % SS(fp->fs));/* Put partial sector into file I/O buffer */
+		if (wcnt > btw) wcnt = btw;
+#if _FS_TINY
+		if (move_window(fp->fs, fp->dsect) != FR_OK)	/* Move sector window */
+			ABORT(fp->fs, FR_DISK_ERR);
+		mem_cpy(&fp->fs->win[fp->fptr % SS(fp->fs)], wbuff, wcnt);	/* Fit partial sector */
+		fp->fs->wflag = 1;
+#else
+		mem_cpy(&fp->buf[fp->fptr % SS(fp->fs)], wbuff, wcnt);	/* Fit partial sector */
+		fp->flag |= FA__DIRTY;
+#endif
+	}
+
+	if (fp->fptr > fp->fsize) fp->fsize = fp->fptr;	/* Update file size if needed */
+	fp->flag |= FA__WRITTEN;						/* Set file change flag */
+
+	LEAVE_FF(fp->fs, FR_OK);
+}
+
+/*-----------------------------------------------------------------------*/
+/* Synchronize the File                                                  */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_sync (
+	FIL* fp		/* Pointer to the file object */
+)
+{
+	FRESULT res;
+	DWORD tm;
+	BYTE *dir;
+
+	res = validate(fp);					/* Check validity of the object */
+	if (res == FR_OK) {
+		if (fp->flag & FA__WRITTEN) {	/* Is there any change to the file? */
+#if !_FS_TINY
+			if (fp->flag & FA__DIRTY) {	/* Write-back cached data if needed */
+				if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
+					LEAVE_FF(fp->fs, FR_DISK_ERR);
+				fp->flag &= ~FA__DIRTY;
+			}
+#endif
+			/* Update the directory entry */
+			res = move_window(fp->fs, fp->dir_sect);
+			if (res == FR_OK) {
+				dir = fp->dir_ptr;
+				dir[DIR_Attr] |= AM_ARC;					/* Set archive bit */
+				ST_DWORD(dir + DIR_FileSize, fp->fsize);	/* Update file size */
+				st_clust(dir, fp->sclust);					/* Update start cluster */
+				tm = GET_FATTIME();							/* Update modified time */
+				ST_DWORD(dir + DIR_WrtTime, tm);
+				ST_WORD(dir + DIR_LstAccDate, 0);
+				fp->flag &= ~FA__WRITTEN;
+				fp->fs->wflag = 1;
+				res = sync_fs(fp->fs);
+			}
+		}
+	}
+
+	LEAVE_FF(fp->fs, res);
+}
+
+#endif /* !_FS_READONLY */
+
+/*-----------------------------------------------------------------------*/
+/* Close File                                                            */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_close (
+	FIL *fp		/* Pointer to the file object to be closed */
+)
+{
+	FRESULT res;
+
+#if !_FS_READONLY
+	res = f_sync(fp);					/* Flush cached data */
+	if (res == FR_OK)
+#endif
+	{
+		res = validate(fp);				/* Lock volume */
+		if (res == FR_OK) {
+#if _FS_REENTRANT
+			FATFS *fs = fp->fs;
+#endif
+#if _FS_LOCK
+			res = dec_lock(fp->lockid);	/* Decrement file open counter */
+			if (res == FR_OK)
+#endif
+				fp->fs = 0;				/* Invalidate file object */
+#if _FS_REENTRANT
+			unlock_fs(fs, FR_OK);		/* Unlock volume */
+#endif
+		}
+	}
+	return res;
+}
+
+/*-----------------------------------------------------------------------*/
+/* Change Current Directory or Current Drive, Get Current Directory      */
+/*-----------------------------------------------------------------------*/
+
+#if _FS_RPATH >= 1
+#if _VOLUMES >= 2
+FRESULT f_chdrive (
+	const TCHAR* path		/* Drive number */
+)
+{
+	int vol;
+
+	vol = get_ldnumber(&path);
+	if (vol < 0) return FR_INVALID_DRIVE;
+
+	CurrVol = (BYTE)vol;
+
+	return FR_OK;
+}
+#endif
+
+FRESULT f_chdir (
+	const TCHAR* path	/* Pointer to the directory path */
+)
+{
+	FRESULT res;
+	DIR dj;
+	DEFINE_NAMEBUF;
+
+	/* Get logical drive number */
+	res = find_volume(&dj.fs, &path, 0);
+	if (res == FR_OK) {
+		INIT_BUF(dj);
+		res = follow_path(&dj, path);		/* Follow the path */
+		FREE_BUF();
+		if (res == FR_OK) {					/* Follow completed */
+			if (!dj.dir) {
+				dj.fs->cdir = dj.sclust;	/* Start directory itself */
+			} else {
+				if (dj.dir[DIR_Attr] & AM_DIR)	/* Reached to the directory */
+					dj.fs->cdir = ld_clust(dj.fs, dj.dir);
+				else
+					res = FR_NO_PATH;		/* Reached but a file */
+			}
+		}
+		if (res == FR_NO_FILE) res = FR_NO_PATH;
+	}
+
+	LEAVE_FF(dj.fs, res);
+}
+
+#if _FS_RPATH >= 2
+FRESULT f_getcwd (
+	TCHAR* buff,	/* Pointer to the directory path */
+	UINT len		/* Size of path */
+)
+{
+	FRESULT res;
+	DIR dj;
+	UINT i, n;
+	DWORD ccl;
+	TCHAR *tp;
+	FILINFO fno;
+	DEFINE_NAMEBUF;
+
+	*buff = 0;
+	/* Get logical drive number */
+	res = find_volume(&dj.fs, (const TCHAR**)&buff, 0);	/* Get current volume */
+	if (res == FR_OK) {
+		INIT_BUF(dj);
+		i = len;			/* Bottom of buffer (directory stack base) */
+		dj.sclust = dj.fs->cdir;			/* Start to follow upper directory from current directory */
+		while ((ccl = dj.sclust) != 0) {	/* Repeat while current directory is a sub-directory */
+			res = dir_sdi(&dj, 1);			/* Get parent directory */
+			if (res != FR_OK) break;
+			res = dir_read(&dj, 0);
+			if (res != FR_OK) break;
+			dj.sclust = ld_clust(dj.fs, dj.dir);	/* Goto parent directory */
+			res = dir_sdi(&dj, 0);
+			if (res != FR_OK) break;
+			do {							/* Find the entry links to the child directory */
+				res = dir_read(&dj, 0);
+				if (res != FR_OK) break;
+				if (ccl == ld_clust(dj.fs, dj.dir)) break;	/* Found the entry */
+				res = dir_next(&dj, 0);	
+			} while (res == FR_OK);
+			if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */
+			if (res != FR_OK) break;
+#if _USE_LFN
+			fno.lfname = buff;
+			fno.lfsize = i;
+#endif
+			get_fileinfo(&dj, &fno);		/* Get the directory name and push it to the buffer */
+			tp = fno.fname;
+#if _USE_LFN
+			if (*buff) tp = buff;
+#endif
+			for (n = 0; tp[n]; n++) ;
+			if (i < n + 3) {
+				res = FR_NOT_ENOUGH_CORE; break;
+			}
+			while (n) buff[--i] = tp[--n];
+			buff[--i] = '/';
+		}
+		tp = buff;
+		if (res == FR_OK) {
+#if _VOLUMES >= 2
+			*tp++ = '0' + CurrVol;			/* Put drive number */
+			*tp++ = ':';
+#endif
+			if (i == len) {					/* Root-directory */
+				*tp++ = '/';
+			} else {						/* Sub-directroy */
+				do		/* Add stacked path str */
+					*tp++ = buff[i++];
+				while (i < len);
+			}
+		}
+		*tp = 0;
+		FREE_BUF();
+	}
+
+	LEAVE_FF(dj.fs, res);
+}
+#endif /* _FS_RPATH >= 2 */
+#endif /* _FS_RPATH >= 1 */
+
+#if _FS_MINIMIZE <= 2
+/*-----------------------------------------------------------------------*/
+/* Seek File R/W Pointer                                                 */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_lseek (
+	FIL* fp,		/* Pointer to the file object */
+	DWORD ofs		/* File pointer from top of file */
+)
+{
+	FRESULT res;
+	DWORD clst, bcs, nsect, ifptr;
+#if _USE_FASTSEEK
+	DWORD cl, pcl, ncl, tcl, dsc, tlen, ulen, *tbl;
+#endif
+
+	res = validate(fp);					/* Check validity of the object */
+	if (res != FR_OK) LEAVE_FF(fp->fs, res);
+	if (fp->err)						/* Check error */
+		LEAVE_FF(fp->fs, (FRESULT)fp->err);
+
+#if _USE_FASTSEEK
+	if (fp->cltbl) {	/* Fast seek */
+		if (ofs == CREATE_LINKMAP) {	/* Create CLMT */
+			tbl = fp->cltbl;
+			tlen = *tbl++; ulen = 2;	/* Given table size and required table size */
+			cl = fp->sclust;			/* Top of the chain */
+			if (cl) {
+				do {
+					/* Get a fragment */
+					tcl = cl; ncl = 0; ulen += 2;	/* Top, length and used items */
+					do {
+						pcl = cl; ncl++;
+						cl = get_fat(fp->fs, cl);
+						if (cl <= 1) ABORT(fp->fs, FR_INT_ERR);
+						if (cl == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
+					} while (cl == pcl + 1);
+					if (ulen <= tlen) {		/* Store the length and top of the fragment */
+						*tbl++ = ncl; *tbl++ = tcl;
+					}
+				} while (cl < fp->fs->n_fatent);	/* Repeat until end of chain */
+			}
+			*fp->cltbl = ulen;	/* Number of items used */
+			if (ulen <= tlen)
+				*tbl = 0;		/* Terminate table */
+			else
+				res = FR_NOT_ENOUGH_CORE;	/* Given table size is smaller than required */
+
+		} else {						/* Fast seek */
+			if (ofs > fp->fsize)		/* Clip offset at the file size */
+				ofs = fp->fsize;
+			fp->fptr = ofs;				/* Set file pointer */
+			if (ofs) {
+				fp->clust = clmt_clust(fp, ofs - 1);
+				dsc = clust2sect(fp->fs, fp->clust);
+				if (!dsc) ABORT(fp->fs, FR_INT_ERR);
+				dsc += (ofs - 1) / SS(fp->fs) & (fp->fs->csize - 1);
+				if (fp->fptr % SS(fp->fs) && dsc != fp->dsect) {	/* Refill sector cache if needed */
+#if !_FS_TINY
+#if !_FS_READONLY
+					if (fp->flag & FA__DIRTY) {		/* Write-back dirty sector cache */
+						if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
+							ABORT(fp->fs, FR_DISK_ERR);
+						fp->flag &= ~FA__DIRTY;
+					}
+#endif
+					if (disk_read(fp->fs->drv, fp->buf, dsc, 1) != RES_OK)	/* Load current sector */
+						ABORT(fp->fs, FR_DISK_ERR);
+#endif
+					fp->dsect = dsc;
+				}
+			}
+		}
+	} else
+#endif
+
+	/* Normal Seek */
+	{
+		if (ofs > fp->fsize					/* In read-only mode, clip offset with the file size */
+#if !_FS_READONLY
+			 && !(fp->flag & FA_WRITE)
+#endif
+			) ofs = fp->fsize;
+
+		ifptr = fp->fptr;
+		fp->fptr = nsect = 0;
+		if (ofs) {
+			bcs = (DWORD)fp->fs->csize * SS(fp->fs);	/* Cluster size (byte) */
+			if (ifptr > 0 &&
+				(ofs - 1) / bcs >= (ifptr - 1) / bcs) {	/* When seek to same or following cluster, */
+				fp->fptr = (ifptr - 1) & ~(bcs - 1);	/* start from the current cluster */
+				ofs -= fp->fptr;
+				clst = fp->clust;
+			} else {									/* When seek to back cluster, */
+				clst = fp->sclust;						/* start from the first cluster */
+#if !_FS_READONLY
+				if (clst == 0) {						/* If no cluster chain, create a new chain */
+					clst = create_chain(fp->fs, 0);
+					if (clst == 1) ABORT(fp->fs, FR_INT_ERR);
+					if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
+					fp->sclust = clst;
+				}
+#endif
+				fp->clust = clst;
+			}
+			if (clst != 0) {
+				while (ofs > bcs) {						/* Cluster following loop */
+#if !_FS_READONLY
+					if (fp->flag & FA_WRITE) {			/* Check if in write mode or not */
+						clst = create_chain(fp->fs, clst);	/* Force stretch if in write mode */
+						if (clst == 0) {				/* When disk gets full, clip file size */
+							ofs = bcs; break;
+						}
+					} else
+#endif
+						clst = get_fat(fp->fs, clst);	/* Follow cluster chain if not in write mode */
+					if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
+					if (clst <= 1 || clst >= fp->fs->n_fatent) ABORT(fp->fs, FR_INT_ERR);
+					fp->clust = clst;
+					fp->fptr += bcs;
+					ofs -= bcs;
+				}
+				fp->fptr += ofs;
+				if (ofs % SS(fp->fs)) {
+					nsect = clust2sect(fp->fs, clst);	/* Current sector */
+					if (!nsect) ABORT(fp->fs, FR_INT_ERR);
+					nsect += ofs / SS(fp->fs);
+				}
+			}
+		}
+		if (fp->fptr % SS(fp->fs) && nsect != fp->dsect) {	/* Fill sector cache if needed */
+#if !_FS_TINY
+#if !_FS_READONLY
+			if (fp->flag & FA__DIRTY) {			/* Write-back dirty sector cache */
+				if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
+					ABORT(fp->fs, FR_DISK_ERR);
+				fp->flag &= ~FA__DIRTY;
+			}
+#endif
+			if (disk_read(fp->fs->drv, fp->buf, nsect, 1) != RES_OK)	/* Fill sector cache */
+				ABORT(fp->fs, FR_DISK_ERR);
+#endif
+			fp->dsect = nsect;
+		}
+#if !_FS_READONLY
+		if (fp->fptr > fp->fsize) {			/* Set file change flag if the file size is extended */
+			fp->fsize = fp->fptr;
+			fp->flag |= FA__WRITTEN;
+		}
+#endif
+	}
+
+	LEAVE_FF(fp->fs, res);
+}
+
+#if _FS_MINIMIZE <= 1
+/*-----------------------------------------------------------------------*/
+/* Create a Directory Object                                             */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_opendir (
+	DIR* dp,			/* Pointer to directory object to create */
+	const TCHAR* path	/* Pointer to the directory path */
+)
+{
+	FRESULT res;
+	FATFS* fs;
+	DEFINE_NAMEBUF;
+
+	if (!dp) return FR_INVALID_OBJECT;
+
+	/* Get logical drive number */
+	res = find_volume(&fs, &path, 0);
+	if (res == FR_OK) {
+		dp->fs = fs;
+		INIT_BUF(*dp);
+		res = follow_path(dp, path);			/* Follow the path to the directory */
+		FREE_BUF();
+		if (res == FR_OK) {						/* Follow completed */
+			if (dp->dir) {						/* It is not the origin directory itself */
+				if (dp->dir[DIR_Attr] & AM_DIR)	/* The object is a sub directory */
+					dp->sclust = ld_clust(fs, dp->dir);
+				else							/* The object is a file */
+					res = FR_NO_PATH;
+			}
+			if (res == FR_OK) {
+				dp->id = fs->id;
+				res = dir_sdi(dp, 0);			/* Rewind directory */
+#if _FS_LOCK
+				if (res == FR_OK) {
+					if (dp->sclust) {
+						dp->lockid = inc_lock(dp, 0);	/* Lock the sub directory */
+						if (!dp->lockid)
+							res = FR_TOO_MANY_OPEN_FILES;
+					} else {
+						dp->lockid = 0;	/* Root directory need not to be locked */
+					}
+				}
+#endif
+			}
+		}
+		if (res == FR_NO_FILE) res = FR_NO_PATH;
+	}
+	if (res != FR_OK) dp->fs = 0;		/* Invalidate the directory object if function faild */
+
+	LEAVE_FF(fs, res);
+}
+
+/*-----------------------------------------------------------------------*/
+/* Close Directory                                                       */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_closedir (
+	DIR *dp		/* Pointer to the directory object to be closed */
+)
+{
+	FRESULT res;
+
+	res = validate(dp);
+	if (res == FR_OK) {
+#if _FS_REENTRANT
+		FATFS *fs = dp->fs;
+#endif
+#if _FS_LOCK
+		if (dp->lockid)				/* Decrement sub-directory open counter */
+			res = dec_lock(dp->lockid);
+		if (res == FR_OK)
+#endif
+			dp->fs = 0;				/* Invalidate directory object */
+#if _FS_REENTRANT
+		unlock_fs(fs, FR_OK);		/* Unlock volume */
+#endif
+	}
+	return res;
+}
+
+/*-----------------------------------------------------------------------*/
+/* Read Directory Entries in Sequence                                    */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_readdir (
+	DIR* dp,			/* Pointer to the open directory object */
+	FILINFO* fno		/* Pointer to file information to return */
+)
+{
+	FRESULT res;
+	DEFINE_NAMEBUF;
+
+	res = validate(dp);						/* Check validity of the object */
+	if (res == FR_OK) {
+		if (!fno) {
+			res = dir_sdi(dp, 0);			/* Rewind the directory object */
+		} else {
+			INIT_BUF(*dp);
+			res = dir_read(dp, 0);			/* Read an item */
+			if (res == FR_NO_FILE) {		/* Reached end of directory */
+				dp->sect = 0;
+				res = FR_OK;
+			}
+			if (res == FR_OK) {				/* A valid entry is found */
+				get_fileinfo(dp, fno);		/* Get the object information */
+				res = dir_next(dp, 0);		/* Increment index for next */
+				if (res == FR_NO_FILE) {
+					dp->sect = 0;
+					res = FR_OK;
+				}
+			}
+			FREE_BUF();
+		}
+	}
+
+	LEAVE_FF(dp->fs, res);
+}
+
+#if _USE_FIND
+/*-----------------------------------------------------------------------*/
+/* Find next file                                                        */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_findnext (
+	DIR* dp,		/* Pointer to the open directory object */
+	FILINFO* fno	/* Pointer to the file information structure */
+)
+{
+	FRESULT res;
+
+	for (;;) {
+		res = f_readdir(dp, fno);		/* Get a directory item */
+		if (res != FR_OK || !fno || !fno->fname[0]) break;	/* Terminate if any error or end of directory */
+#if _USE_LFN
+		if (fno->lfname && pattern_matching(dp->pat, fno->lfname, 0, 0)) break;	/* Test for LFN if exist */
+#endif
+		if (pattern_matching(dp->pat, fno->fname, 0, 0)) break;	/* Test for SFN */
+	}
+	return res;
+
+}
+
+/*-----------------------------------------------------------------------*/
+/* Find first file                                                       */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_findfirst (
+	DIR* dp,				/* Pointer to the blank directory object */
+	FILINFO* fno,			/* Pointer to the file information structure */
+	const TCHAR* path,		/* Pointer to the directory to open */
+	const TCHAR* pattern	/* Pointer to the matching pattern */
+)
+{
+	FRESULT res;
+
+	dp->pat = pattern;		/* Save pointer to pattern string */
+	res = f_opendir(dp, path);		/* Open the target directory */
+	if (res == FR_OK)
+		res = f_findnext(dp, fno);	/* Find the first item */
+	return res;
+}
+
+#endif	/* _USE_FIND */
+
+#if _FS_MINIMIZE == 0
+/*-----------------------------------------------------------------------*/
+/* Get File Status                                                       */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_stat (
+	const TCHAR* path,	/* Pointer to the file path */
+	FILINFO* fno		/* Pointer to file information to return */
+)
+{
+	FRESULT res;
+	DIR dj;
+	DEFINE_NAMEBUF;
+
+	/* Get logical drive number */
+	res = find_volume(&dj.fs, &path, 0);
+	if (res == FR_OK) {
+		INIT_BUF(dj);
+		res = follow_path(&dj, path);	/* Follow the file path */
+		if (res == FR_OK) {				/* Follow completed */
+			if (dj.dir) {		/* Found an object */
+				if (fno) get_fileinfo(&dj, fno);
+			} else {			/* It is root directory */
+				res = FR_INVALID_NAME;
+			}
+		}
+		FREE_BUF();
+	}
+
+	LEAVE_FF(dj.fs, res);
+}
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Get Number of Free Clusters                                           */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_getfree (
+	const TCHAR* path,	/* Path name of the logical drive number */
+	DWORD* nclst,		/* Pointer to a variable to return number of free clusters */
+	FATFS** fatfs		/* Pointer to return pointer to corresponding file system object */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD nfree, clst, sect, stat;
+	UINT i;
+	BYTE fat, *p;
+
+	/* Get logical drive number */
+	res = find_volume(fatfs, &path, 0);
+	fs = *fatfs;
+	if (res == FR_OK) {
+		/* If free_clust is valid, return it without full cluster scan */
+		if (fs->free_clust <= fs->n_fatent - 2) {
+			*nclst = fs->free_clust;
+		} else {
+			/* Get number of free clusters */
+			fat = fs->fs_type;
+			nfree = 0;
+			if (fat == FS_FAT12) {	/* Sector unalighed entries: Search FAT via regular routine. */
+				clst = 2;
+				do {
+					stat = get_fat(fs, clst);
+					if (stat == 0xFFFFFFFF) { res = FR_DISK_ERR; break; }
+					if (stat == 1) { res = FR_INT_ERR; break; }
+					if (stat == 0) nfree++;
+				} while (++clst < fs->n_fatent);
+			} else {				/* Sector alighed entries: Accelerate the FAT search. */
+				clst = fs->n_fatent; sect = fs->fatbase;
+				i = 0; p = 0;
+				do {
+					if (!i) {
+						res = move_window(fs, sect++);
+						if (res != FR_OK) break;
+						p = fs->win;
+						i = SS(fs);
+					}
+					if (fat == FS_FAT16) {
+						if (LD_WORD(p) == 0) nfree++;
+						p += 2; i -= 2;
+					} else {
+						if ((LD_DWORD(p) & 0x0FFFFFFF) == 0) nfree++;
+						p += 4; i -= 4;
+					}
+				} while (--clst);
+			}
+			fs->free_clust = nfree;	/* free_clust is valid */
+			fs->fsi_flag |= 1;		/* FSInfo is to be updated */
+			*nclst = nfree;			/* Return the free clusters */
+		}
+	}
+	LEAVE_FF(fs, res);
+}
+
+/*-----------------------------------------------------------------------*/
+/* Truncate File                                                         */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_truncate (
+	FIL* fp		/* Pointer to the file object */
+)
+{
+	FRESULT res;
+	DWORD ncl;
+
+	res = validate(fp);						/* Check validity of the object */
+	if (res == FR_OK) {
+		if (fp->err) {						/* Check error */
+			res = (FRESULT)fp->err;
+		} else {
+			if (!(fp->flag & FA_WRITE))		/* Check access mode */
+				res = FR_DENIED;
+		}
+	}
+	if (res == FR_OK) {
+		if (fp->fsize > fp->fptr) {
+			fp->fsize = fp->fptr;	/* Set file size to current R/W point */
+			fp->flag |= FA__WRITTEN;
+			if (fp->fptr == 0) {	/* When set file size to zero, remove entire cluster chain */
+				res = remove_chain(fp->fs, fp->sclust);
+				fp->sclust = 0;
+			} else {				/* When truncate a part of the file, remove remaining clusters */
+				ncl = get_fat(fp->fs, fp->clust);
+				res = FR_OK;
+				if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR;
+				if (ncl == 1) res = FR_INT_ERR;
+				if (res == FR_OK && ncl < fp->fs->n_fatent) {
+					res = put_fat(fp->fs, fp->clust, 0x0FFFFFFF);
+					if (res == FR_OK) res = remove_chain(fp->fs, ncl);
+				}
+			}
+#if !_FS_TINY
+			if (res == FR_OK && (fp->flag & FA__DIRTY)) {
+				if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
+					res = FR_DISK_ERR;
+				else
+					fp->flag &= ~FA__DIRTY;
+			}
+#endif
+		}
+		if (res != FR_OK) fp->err = (FRESULT)res;
+	}
+
+	LEAVE_FF(fp->fs, res);
+}
+
+/*-----------------------------------------------------------------------*/
+/* Delete a File or Directory                                            */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_unlink (
+	const TCHAR* path		/* Pointer to the file or directory path */
+)
+{
+	FRESULT res;
+	DIR dj, sdj;
+	BYTE *dir;
+	DWORD dclst = 0;
+	DEFINE_NAMEBUF;
+
+	/* Get logical drive number */
+	res = find_volume(&dj.fs, &path, 1);
+	if (res == FR_OK) {
+		INIT_BUF(dj);
+		res = follow_path(&dj, path);		/* Follow the file path */
+		if (_FS_RPATH && res == FR_OK && (dj.fn[NSFLAG] & NS_DOT))
+			res = FR_INVALID_NAME;			/* Cannot remove dot entry */
+#if _FS_LOCK
+		if (res == FR_OK) res = chk_lock(&dj, 2);	/* Cannot remove open object */
+#endif
+		if (res == FR_OK) {					/* The object is accessible */
+			dir = dj.dir;
+			if (!dir) {
+				res = FR_INVALID_NAME;		/* Cannot remove the origin directory */
+			} else {
+				if (dir[DIR_Attr] & AM_RDO)
+					res = FR_DENIED;		/* Cannot remove R/O object */
+			}
+			if (res == FR_OK) {
+				dclst = ld_clust(dj.fs, dir);
+				if (dclst && (dir[DIR_Attr] & AM_DIR)) {	/* Is it a sub-directory ? */
+#if _FS_RPATH
+					if (dclst == dj.fs->cdir) {		 		/* Is it the current directory? */
+						res = FR_DENIED;
+					} else
+#endif
+					{
+						mem_cpy(&sdj, &dj, sizeof (DIR));	/* Open the sub-directory */
+						sdj.sclust = dclst;
+						res = dir_sdi(&sdj, 2);
+						if (res == FR_OK) {
+							res = dir_read(&sdj, 0);			/* Read an item (excluding dot entries) */
+							if (res == FR_OK) res = FR_DENIED;	/* Not empty? (cannot remove) */
+							if (res == FR_NO_FILE) res = FR_OK;	/* Empty? (can remove) */
+						}
+					}
+				}
+			}
+			if (res == FR_OK) {
+				res = dir_remove(&dj);		/* Remove the directory entry */
+				if (res == FR_OK && dclst)	/* Remove the cluster chain if exist */
+					res = remove_chain(dj.fs, dclst);
+				if (res == FR_OK) res = sync_fs(dj.fs);
+			}
+		}
+		FREE_BUF();
+	}
+
+	LEAVE_FF(dj.fs, res);
+}
+
+/*-----------------------------------------------------------------------*/
+/* Create a Directory                                                    */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_mkdir (
+	const TCHAR* path		/* Pointer to the directory path */
+)
+{
+	FRESULT res;
+	DIR dj;
+	BYTE *dir, n;
+	DWORD dsc, dcl, pcl, tm = GET_FATTIME();
+	DEFINE_NAMEBUF;
+
+	/* Get logical drive number */
+	res = find_volume(&dj.fs, &path, 1);
+	if (res == FR_OK) {
+		INIT_BUF(dj);
+		res = follow_path(&dj, path);			/* Follow the file path */
+		if (res == FR_OK) res = FR_EXIST;		/* Any object with same name is already existing */
+		if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NSFLAG] & NS_DOT))
+			res = FR_INVALID_NAME;
+		if (res == FR_NO_FILE) {				/* Can create a new directory */
+			dcl = create_chain(dj.fs, 0);		/* Allocate a cluster for the new directory table */
+			res = FR_OK;
+			if (dcl == 0) res = FR_DENIED;		/* No space to allocate a new cluster */
+			if (dcl == 1) res = FR_INT_ERR;
+			if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR;
+			if (res == FR_OK)					/* Flush FAT */
+				res = sync_window(dj.fs);
+			if (res == FR_OK) {					/* Initialize the new directory table */
+				dsc = clust2sect(dj.fs, dcl);
+				dir = dj.fs->win;
+				mem_set(dir, 0, SS(dj.fs));
+				mem_set(dir + DIR_Name, ' ', 11);	/* Create "." entry */
+				dir[DIR_Name] = '.';
+				dir[DIR_Attr] = AM_DIR;
+				ST_DWORD(dir + DIR_WrtTime, tm);
+				st_clust(dir, dcl);
+				mem_cpy(dir + SZ_DIRE, dir, SZ_DIRE); 	/* Create ".." entry */
+				dir[SZ_DIRE + 1] = '.'; pcl = dj.sclust;
+				if (dj.fs->fs_type == FS_FAT32 && pcl == dj.fs->dirbase)
+					pcl = 0;
+				st_clust(dir + SZ_DIRE, pcl);
+				for (n = dj.fs->csize; n; n--) {	/* Write dot entries and clear following sectors */
+					dj.fs->winsect = dsc++;
+					dj.fs->wflag = 1;
+					res = sync_window(dj.fs);
+					if (res != FR_OK) break;
+					mem_set(dir, 0, SS(dj.fs));
+				}
+			}
+			if (res == FR_OK) res = dir_register(&dj);	/* Register the object to the directoy */
+			if (res != FR_OK) {
+				remove_chain(dj.fs, dcl);			/* Could not register, remove cluster chain */
+			} else {
+				dir = dj.dir;
+				dir[DIR_Attr] = AM_DIR;				/* Attribute */
+				ST_DWORD(dir + DIR_WrtTime, tm);	/* Created time */
+				st_clust(dir, dcl);					/* Table start cluster */
+				dj.fs->wflag = 1;
+				res = sync_fs(dj.fs);
+			}
+		}
+		FREE_BUF();
+	}
+
+	LEAVE_FF(dj.fs, res);
+}
+
+/*-----------------------------------------------------------------------*/
+/* Change Attribute                                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_chmod (
+	const TCHAR* path,	/* Pointer to the file path */
+	BYTE attr,			/* Attribute bits */
+	BYTE mask			/* Attribute mask to change */
+)
+{
+	FRESULT res;
+	DIR dj;
+	BYTE *dir;
+	DEFINE_NAMEBUF;
+
+	res = find_volume(&dj.fs, &path, 1);	/* Get logical drive number */
+	if (res == FR_OK) {
+		INIT_BUF(dj);
+		res = follow_path(&dj, path);		/* Follow the file path */
+		FREE_BUF();
+		if (_FS_RPATH && res == FR_OK && (dj.fn[NSFLAG] & NS_DOT))
+			res = FR_INVALID_NAME;
+		if (res == FR_OK) {
+			dir = dj.dir;
+			if (!dir) {						/* Is it a root directory? */
+				res = FR_INVALID_NAME;
+			} else {						/* File or sub directory */
+				mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC;	/* Valid attribute mask */
+				dir[DIR_Attr] = (attr & mask) | (dir[DIR_Attr] & (BYTE)~mask);	/* Apply attribute change */
+				dj.fs->wflag = 1;
+				res = sync_fs(dj.fs);
+			}
+		}
+	}
+
+	LEAVE_FF(dj.fs, res);
+}
+
+/*-----------------------------------------------------------------------*/
+/* Rename File/Directory                                                 */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_rename (
+	const TCHAR* path_old,	/* Pointer to the object to be renamed */
+	const TCHAR* path_new	/* Pointer to the new name */
+)
+{
+	FRESULT res;
+	DIR djo, djn;
+	BYTE buf[21], *dir;
+	DWORD dw;
+	DEFINE_NAMEBUF;
+
+	/* Get logical drive number of the source object */
+	res = find_volume(&djo.fs, &path_old, 1);
+	if (res == FR_OK) {
+		djn.fs = djo.fs;
+		INIT_BUF(djo);
+		res = follow_path(&djo, path_old);		/* Check old object */
+		if (_FS_RPATH && res == FR_OK && (djo.fn[NSFLAG] & NS_DOT))
+			res = FR_INVALID_NAME;
+#if _FS_LOCK
+		if (res == FR_OK) res = chk_lock(&djo, 2);
+#endif
+		if (res == FR_OK) {						/* Old object is found */
+			if (!djo.dir) {						/* Is root dir? */
+				res = FR_NO_FILE;
+			} else {
+				mem_cpy(buf, djo.dir + DIR_Attr, 21);	/* Save information about object except name */
+				mem_cpy(&djn, &djo, sizeof (DIR));		/* Duplicate the directory object */
+				if (get_ldnumber(&path_new) >= 0)		/* Snip drive number off and ignore it */
+					res = follow_path(&djn, path_new);	/* and make sure if new object name is not conflicting */
+				else
+					res = FR_INVALID_DRIVE;
+				if (res == FR_OK) res = FR_EXIST;		/* The new object name is already existing */
+				if (res == FR_NO_FILE) { 				/* It is a valid path and no name collision */
+					res = dir_register(&djn);			/* Register the new entry */
+					if (res == FR_OK) {
+/* Start of critical section where any interruption can cause a cross-link */
+						dir = djn.dir;					/* Copy information about object except name */
+						mem_cpy(dir + 13, buf + 2, 19);
+						dir[DIR_Attr] = buf[0] | AM_ARC;
+						djo.fs->wflag = 1;
+						if ((dir[DIR_Attr] & AM_DIR) && djo.sclust != djn.sclust) {	/* Update .. entry in the sub-directory if needed */
+							dw = clust2sect(djo.fs, ld_clust(djo.fs, dir));
+							if (!dw) {
+								res = FR_INT_ERR;
+							} else {
+								res = move_window(djo.fs, dw);
+								dir = djo.fs->win + SZ_DIRE * 1;	/* Ptr to .. entry */
+								if (res == FR_OK && dir[1] == '.') {
+									st_clust(dir, djn.sclust);
+									djo.fs->wflag = 1;
+								}
+							}
+						}
+						if (res == FR_OK) {
+							res = dir_remove(&djo);		/* Remove old entry */
+							if (res == FR_OK)
+								res = sync_fs(djo.fs);
+						}
+/* End of critical section */
+					}
+				}
+			}
+		}
+		FREE_BUF();
+	}
+
+	LEAVE_FF(djo.fs, res);
+}
+
+/*-----------------------------------------------------------------------*/
+/* Change Timestamp                                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_utime (
+	const TCHAR* path,	/* Pointer to the file/directory name */
+	const FILINFO* fno	/* Pointer to the time stamp to be set */
+)
+{
+	FRESULT res;
+	DIR dj;
+	BYTE *dir;
+	DEFINE_NAMEBUF;
+
+	/* Get logical drive number */
+	res = find_volume(&dj.fs, &path, 1);
+	if (res == FR_OK) {
+		INIT_BUF(dj);
+		res = follow_path(&dj, path);	/* Follow the file path */
+		FREE_BUF();
+		if (_FS_RPATH && res == FR_OK && (dj.fn[NSFLAG] & NS_DOT))
+			res = FR_INVALID_NAME;
+		if (res == FR_OK) {
+			dir = dj.dir;
+			if (!dir) {					/* Root directory */
+				res = FR_INVALID_NAME;
+			} else {					/* File or sub-directory */
+				ST_WORD(dir + DIR_WrtTime, fno->ftime);
+				ST_WORD(dir + DIR_WrtDate, fno->fdate);
+				dj.fs->wflag = 1;
+				res = sync_fs(dj.fs);
+			}
+		}
+	}
+
+	LEAVE_FF(dj.fs, res);
+}
+
+#endif /* !_FS_READONLY */
+#endif /* _FS_MINIMIZE == 0 */
+#endif /* _FS_MINIMIZE <= 1 */
+#endif /* _FS_MINIMIZE <= 2 */
+
+#if _USE_LABEL
+/*-----------------------------------------------------------------------*/
+/* Get volume label                                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_getlabel (
+	const TCHAR* path,	/* Path name of the logical drive number */
+	TCHAR* label,		/* Pointer to a buffer to return the volume label */
+	DWORD* vsn			/* Pointer to a variable to return the volume serial number */
+)
+{
+	FRESULT res;
+	DIR dj;
+	UINT i, j;
+#if _USE_LFN && _LFN_UNICODE
+	WCHAR w;
+#endif
+
+	/* Get logical drive number */
+	res = find_volume(&dj.fs, &path, 0);
+
+	/* Get volume label */
+	if (res == FR_OK && label) {
+		dj.sclust = 0;					/* Open root directory */
+		res = dir_sdi(&dj, 0);
+		if (res == FR_OK) {
+			res = dir_read(&dj, 1);		/* Get an entry with AM_VOL */
+			if (res == FR_OK) {			/* A volume label is exist */
+#if _USE_LFN && _LFN_UNICODE
+				i = j = 0;
+				do {
+					w = (i < 11) ? dj.dir[i++] : ' ';
+					if (IsDBCS1(w) && i < 11 && IsDBCS2(dj.dir[i]))
+						w = w << 8 | dj.dir[i++];
+					label[j++] = ff_convert(w, 1);	/* OEM -> Unicode */
+				} while (j < 11);
+#else
+				mem_cpy(label, dj.dir, 11);
+#endif
+				j = 11;
+				do {
+					label[j] = 0;
+					if (!j) break;
+				} while (label[--j] == ' ');
+			}
+			if (res == FR_NO_FILE) {	/* No label, return nul string */
+				label[0] = 0;
+				res = FR_OK;
+			}
+		}
+	}
+
+	/* Get volume serial number */
+	if (res == FR_OK && vsn) {
+		res = move_window(dj.fs, dj.fs->volbase);
+		if (res == FR_OK) {
+			i = dj.fs->fs_type == FS_FAT32 ? BS_VolID32 : BS_VolID;
+			*vsn = LD_DWORD(&dj.fs->win[i]);
+		}
+	}
+
+	LEAVE_FF(dj.fs, res);
+}
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Set volume label                                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_setlabel (
+	const TCHAR* label	/* Pointer to the volume label to set */
+)
+{
+	FRESULT res;
+	DIR dj;
+	BYTE vn[11];
+	UINT i, j, sl;
+	WCHAR w;
+	DWORD tm;
+
+	/* Get logical drive number */
+	res = find_volume(&dj.fs, &label, 1);
+	if (res) LEAVE_FF(dj.fs, res);
+
+	/* Create a volume label in directory form */
+	vn[0] = 0;
+	for (sl = 0; label[sl]; sl++) ;				/* Get name length */
+	for ( ; sl && label[sl - 1] == ' '; sl--) ;	/* Remove trailing spaces */
+	if (sl) {	/* Create volume label in directory form */
+		i = j = 0;
+		do {
+#if _USE_LFN && _LFN_UNICODE
+			w = ff_convert(ff_wtoupper(label[i++]), 0);
+#else
+			w = (BYTE)label[i++];
+			if (IsDBCS1(w))
+				w = (j < 10 && i < sl && IsDBCS2(label[i])) ? w << 8 | (BYTE)label[i++] : 0;
+#if _USE_LFN
+			w = ff_convert(ff_wtoupper(ff_convert(w, 1)), 0);
+#else
+			if (IsLower(w)) w -= 0x20;			/* To upper ASCII characters */
+#ifdef _EXCVT
+			if (w >= 0x80) w = ExCvt[w - 0x80];	/* To upper extended characters (SBCS cfg) */
+#else
+			if (!_DF1S && w >= 0x80) w = 0;		/* Reject extended characters (ASCII cfg) */
+#endif
+#endif
+#endif
+			if (!w || chk_chr("\"*+,.:;<=>\?[]|\x7F", w) || j >= (UINT)((w >= 0x100) ? 10 : 11)) /* Reject invalid characters for volume label */
+				LEAVE_FF(dj.fs, FR_INVALID_NAME);
+			if (w >= 0x100) vn[j++] = (BYTE)(w >> 8);
+			vn[j++] = (BYTE)w;
+		} while (i < sl);
+		while (j < 11) vn[j++] = ' ';	/* Fill remaining name field */
+		if (vn[0] == DDEM) LEAVE_FF(dj.fs, FR_INVALID_NAME);	/* Reject illegal name (heading DDEM) */
+	}
+
+	/* Set volume label */
+	dj.sclust = 0;					/* Open root directory */
+	res = dir_sdi(&dj, 0);
+	if (res == FR_OK) {
+		res = dir_read(&dj, 1);		/* Get an entry with AM_VOL */
+		if (res == FR_OK) {			/* A volume label is found */
+			if (vn[0]) {
+				mem_cpy(dj.dir, vn, 11);	/* Change the volume label name */
+				tm = GET_FATTIME();
+				ST_DWORD(dj.dir + DIR_WrtTime, tm);
+			} else {
+				dj.dir[0] = DDEM;			/* Remove the volume label */
+			}
+			dj.fs->wflag = 1;
+			res = sync_fs(dj.fs);
+		} else {					/* No volume label is found or error */
+			if (res == FR_NO_FILE) {
+				res = FR_OK;
+				if (vn[0]) {				/* Create volume label as new */
+					res = dir_alloc(&dj, 1);	/* Allocate an entry for volume label */
+					if (res == FR_OK) {
+						mem_set(dj.dir, 0, SZ_DIRE);	/* Set volume label */
+						mem_cpy(dj.dir, vn, 11);
+						dj.dir[DIR_Attr] = AM_VOL;
+						tm = GET_FATTIME();
+						ST_DWORD(dj.dir + DIR_WrtTime, tm);
+						dj.fs->wflag = 1;
+						res = sync_fs(dj.fs);
+					}
+				}
+			}
+		}
+	}
+
+	LEAVE_FF(dj.fs, res);
+}
+
+#endif /* !_FS_READONLY */
+#endif /* _USE_LABEL */
+
+/*-----------------------------------------------------------------------*/
+/* Forward data to the stream directly (available on only tiny cfg)      */
+/*-----------------------------------------------------------------------*/
+#if _USE_FORWARD && _FS_TINY
+
+FRESULT f_forward (
+	FIL* fp, 						/* Pointer to the file object */
+	UINT (*func)(const BYTE*,UINT),	/* Pointer to the streaming function */
+	UINT btf,						/* Number of bytes to forward */
+	UINT* bf						/* Pointer to number of bytes forwarded */
+)
+{
+	FRESULT res;
+	DWORD remain, clst, sect;
+	UINT rcnt;
+	BYTE csect;
+
+	*bf = 0;	/* Clear transfer byte counter */
+
+	res = validate(fp);								/* Check validity of the object */
+	if (res != FR_OK) LEAVE_FF(fp->fs, res);
+	if (fp->err)									/* Check error */
+		LEAVE_FF(fp->fs, (FRESULT)fp->err);
+	if (!(fp->flag & FA_READ))						/* Check access mode */
+		LEAVE_FF(fp->fs, FR_DENIED);
+
+	remain = fp->fsize - fp->fptr;
+	if (btf > remain) btf = (UINT)remain;			/* Truncate btf by remaining bytes */
+
+	for ( ;  btf && (*func)(0, 0);					/* Repeat until all data transferred or stream becomes busy */
+		fp->fptr += rcnt, *bf += rcnt, btf -= rcnt) {
+		csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1));	/* Sector offset in the cluster */
+		if ((fp->fptr % SS(fp->fs)) == 0) {			/* On the sector boundary? */
+			if (!csect) {							/* On the cluster boundary? */
+				clst = (fp->fptr == 0) ?			/* On the top of the file? */
+					fp->sclust : get_fat(fp->fs, fp->clust);
+				if (clst <= 1) ABORT(fp->fs, FR_INT_ERR);
+				if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
+				fp->clust = clst;					/* Update current cluster */
+			}
+		}
+		sect = clust2sect(fp->fs, fp->clust);		/* Get current data sector */
+		if (!sect) ABORT(fp->fs, FR_INT_ERR);
+		sect += csect;
+		if (move_window(fp->fs, sect) != FR_OK)		/* Move sector window */
+			ABORT(fp->fs, FR_DISK_ERR);
+		fp->dsect = sect;
+		rcnt = SS(fp->fs) - (WORD)(fp->fptr % SS(fp->fs));	/* Forward data from sector window */
+		if (rcnt > btf) rcnt = btf;
+		rcnt = (*func)(&fp->fs->win[(WORD)fp->fptr % SS(fp->fs)], rcnt);
+		if (!rcnt) ABORT(fp->fs, FR_INT_ERR);
+	}
+
+	LEAVE_FF(fp->fs, FR_OK);
+}
+#endif /* _USE_FORWARD */
+
+#if _USE_MKFS && !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Create file system on the logical drive                               */
+/*-----------------------------------------------------------------------*/
+#define N_ROOTDIR	512		/* Number of root directory entries for FAT12/16 */
+#define N_FATS		1		/* Number of FATs (1 or 2) */
+
+FRESULT f_mkfs (
+	const TCHAR* path,	/* Logical drive number */
+	BYTE sfd,			/* Partitioning rule 0:FDISK, 1:SFD */
+	UINT au				/* Size of allocation unit in unit of byte or sector */
+)
+{
+	static const WORD vst[] = { 1024,   512,  256,  128,   64,    32,   16,    8,    4,    2,   0};
+	static const WORD cst[] = {32768, 16384, 8192, 4096, 2048, 16384, 8192, 4096, 2048, 1024, 512};
+	int vol;
+	BYTE fmt, md, sys, *tbl, pdrv, part;
+	DWORD n_clst, vs, n, wsect;
+	UINT i;
+	DWORD b_vol, b_fat, b_dir, b_data;	/* LBA */
+	DWORD n_vol, n_rsv, n_fat, n_dir;	/* Size */
+	FATFS *fs;
+	DSTATUS stat;
+#if _USE_TRIM
+	DWORD eb[2];
+#endif
+
+	/* Check mounted drive and clear work area */
+	if (sfd > 1) return FR_INVALID_PARAMETER;
+	vol = get_ldnumber(&path);
+	if (vol < 0) return FR_INVALID_DRIVE;
+	fs = FatFs[vol];
+	if (!fs) return FR_NOT_ENABLED;
+	fs->fs_type = 0;
+	pdrv = LD2PD(vol);	/* Physical drive */
+	part = LD2PT(vol);	/* Partition (0:auto detect, 1-4:get from partition table)*/
+
+	/* Get disk statics */
+	stat = disk_initialize(pdrv);
+	if (stat & STA_NOINIT) return FR_NOT_READY;
+	if (stat & STA_PROTECT) return FR_WRITE_PROTECTED;
+#if _MAX_SS != _MIN_SS		/* Get disk sector size */
+	if (disk_ioctl(pdrv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK || SS(fs) > _MAX_SS || SS(fs) < _MIN_SS)
+		return FR_DISK_ERR;
+#endif
+	if (_MULTI_PARTITION && part) {
+		/* Get partition information from partition table in the MBR */
+		if (disk_read(pdrv, fs->win, 0, 1) != RES_OK) return FR_DISK_ERR;
+		if (LD_WORD(fs->win + BS_55AA) != 0xAA55) return FR_MKFS_ABORTED;
+		tbl = &fs->win[MBR_Table + (part - 1) * SZ_PTE];
+		if (!tbl[4]) return FR_MKFS_ABORTED;	/* No partition? */
+		b_vol = LD_DWORD(tbl + 8);	/* Volume start sector */
+		n_vol = LD_DWORD(tbl + 12);	/* Volume size */
+	} else {
+		/* Create a partition in this function */
+		if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &n_vol) != RES_OK || n_vol < 128)
+			return FR_DISK_ERR;
+		b_vol = (sfd) ? 0 : 63;		/* Volume start sector */
+		n_vol -= b_vol;				/* Volume size */
+	}
+
+	if (au & (au - 1)) au = 0;
+	if (!au) {						/* AU auto selection */
+		vs = n_vol / (2000 / (SS(fs) / 512));
+		for (i = 0; vs < vst[i]; i++) ;
+		au = cst[i];
+	}
+	if (au >= _MIN_SS) au /= SS(fs);	/* Number of sectors per cluster */
+	if (!au) au = 1;
+	if (au > 128) au = 128;
+
+	/* Pre-compute number of clusters and FAT sub-type */
+	n_clst = n_vol / au;
+	fmt = FS_FAT12;
+	if (n_clst >= MIN_FAT16) fmt = FS_FAT16;
+	if (n_clst >= MIN_FAT32) fmt = FS_FAT32;
+
+	/* Determine offset and size of FAT structure */
+	if (fmt == FS_FAT32) {
+		n_fat = ((n_clst * 4) + 8 + SS(fs) - 1) / SS(fs);
+		n_rsv = 32;
+		n_dir = 0;
+	} else {
+		n_fat = (fmt == FS_FAT12) ? (n_clst * 3 + 1) / 2 + 3 : (n_clst * 2) + 4;
+		n_fat = (n_fat + SS(fs) - 1) / SS(fs);
+		n_rsv = 1;
+		n_dir = (DWORD)N_ROOTDIR * SZ_DIRE / SS(fs);
+	}
+	b_fat = b_vol + n_rsv;				/* FAT area start sector */
+	b_dir = b_fat + n_fat * N_FATS;		/* Directory area start sector */
+	b_data = b_dir + n_dir;				/* Data area start sector */
+	if (n_vol < b_data + au - b_vol) return FR_MKFS_ABORTED;	/* Too small volume */
+
+	/* Align data start sector to erase block boundary (for flash memory media) */
+	if (disk_ioctl(pdrv, GET_BLOCK_SIZE, &n) != RES_OK || !n || n > 32768) n = 1;
+	n = (b_data + n - 1) & ~(n - 1);	/* Next nearest erase block from current data start */
+	n = (n - b_data) / N_FATS;
+	if (fmt == FS_FAT32) {		/* FAT32: Move FAT offset */
+		n_rsv += n;
+		b_fat += n;
+	} else {					/* FAT12/16: Expand FAT size */
+		n_fat += n;
+	}
+
+	/* Determine number of clusters and final check of validity of the FAT sub-type */
+	n_clst = (n_vol - n_rsv - n_fat * N_FATS - n_dir) / au;
+	if (   (fmt == FS_FAT16 && n_clst < MIN_FAT16)
+		|| (fmt == FS_FAT32 && n_clst < MIN_FAT32))
+		return FR_MKFS_ABORTED;
+
+	/* Determine system ID in the partition table */
+	if (fmt == FS_FAT32) {
+		sys = 0x0C;		/* FAT32X */
+	} else {
+		if (fmt == FS_FAT12 && n_vol < 0x10000) {
+			sys = 0x01;	/* FAT12(<65536) */
+		} else {
+			sys = (n_vol < 0x10000) ? 0x04 : 0x06;	/* FAT16(<65536) : FAT12/16(>=65536) */
+		}
+	}
+
+	if (_MULTI_PARTITION && part) {
+		/* Update system ID in the partition table */
+		tbl = &fs->win[MBR_Table + (part - 1) * SZ_PTE];
+		tbl[4] = sys;
+		if (disk_write(pdrv, fs->win, 0, 1) != RES_OK)	/* Write it to teh MBR */
+			return FR_DISK_ERR;
+		md = 0xF8;
+	} else {
+		if (sfd) {	/* No partition table (SFD) */
+			md = 0xF0;
+		} else {	/* Create partition table (FDISK) */
+			mem_set(fs->win, 0, SS(fs));
+			tbl = fs->win + MBR_Table;	/* Create partition table for single partition in the drive */
+			tbl[1] = 1;						/* Partition start head */
+			tbl[2] = 1;						/* Partition start sector */
+			tbl[3] = 0;						/* Partition start cylinder */
+			tbl[4] = sys;					/* System type */
+			tbl[5] = 254;					/* Partition end head */
+			n = (b_vol + n_vol) / 63 / 255;
+			tbl[6] = (BYTE)(n >> 2 | 63);	/* Partition end sector */
+			tbl[7] = (BYTE)n;				/* End cylinder */
+			ST_DWORD(tbl + 8, 63);			/* Partition start in LBA */
+			ST_DWORD(tbl + 12, n_vol);		/* Partition size in LBA */
+			ST_WORD(fs->win + BS_55AA, 0xAA55);	/* MBR signature */
+			if (disk_write(pdrv, fs->win, 0, 1) != RES_OK)	/* Write it to the MBR */
+				return FR_DISK_ERR;
+			md = 0xF8;
+		}
+	}
+
+	/* Create BPB in the VBR */
+	tbl = fs->win;							/* Clear sector */
+	mem_set(tbl, 0, SS(fs));
+	mem_cpy(tbl, "\xEB\xFE\x90" "MSDOS5.0", 11);/* Boot jump code, OEM name */
+	i = SS(fs);								/* Sector size */
+	ST_WORD(tbl + BPB_BytsPerSec, i);
+	tbl[BPB_SecPerClus] = (BYTE)au;			/* Sectors per cluster */
+	ST_WORD(tbl + BPB_RsvdSecCnt, n_rsv);	/* Reserved sectors */
+	tbl[BPB_NumFATs] = N_FATS;				/* Number of FATs */
+	i = (fmt == FS_FAT32) ? 0 : N_ROOTDIR;	/* Number of root directory entries */
+	ST_WORD(tbl + BPB_RootEntCnt, i);
+	if (n_vol < 0x10000) {					/* Number of total sectors */
+		ST_WORD(tbl + BPB_TotSec16, n_vol);
+	} else {
+		ST_DWORD(tbl + BPB_TotSec32, n_vol);
+	}
+	tbl[BPB_Media] = md;					/* Media descriptor */
+	ST_WORD(tbl + BPB_SecPerTrk, 63);		/* Number of sectors per track */
+	ST_WORD(tbl + BPB_NumHeads, 255);		/* Number of heads */
+	ST_DWORD(tbl + BPB_HiddSec, b_vol);		/* Hidden sectors */
+	n = GET_FATTIME();						/* Use current time as VSN */
+	if (fmt == FS_FAT32) {
+		ST_DWORD(tbl + BS_VolID32, n);		/* VSN */
+		ST_DWORD(tbl + BPB_FATSz32, n_fat);	/* Number of sectors per FAT */
+		ST_DWORD(tbl + BPB_RootClus, 2);	/* Root directory start cluster (2) */
+		ST_WORD(tbl + BPB_FSInfo, 1);		/* FSINFO record offset (VBR + 1) */
+		ST_WORD(tbl + BPB_BkBootSec, 6);	/* Backup boot record offset (VBR + 6) */
+		tbl[BS_DrvNum32] = 0x80;			/* Drive number */
+		tbl[BS_BootSig32] = 0x29;			/* Extended boot signature */
+		mem_cpy(tbl + BS_VolLab32, "NO NAME    " "FAT32   ", 19);	/* Volume label, FAT signature */
+	} else {
+		ST_DWORD(tbl + BS_VolID, n);		/* VSN */
+		ST_WORD(tbl + BPB_FATSz16, n_fat);	/* Number of sectors per FAT */
+		tbl[BS_DrvNum] = 0x80;				/* Drive number */
+		tbl[BS_BootSig] = 0x29;				/* Extended boot signature */
+		mem_cpy(tbl + BS_VolLab, "NO NAME    " "FAT     ", 19);	/* Volume label, FAT signature */
+	}
+	ST_WORD(tbl + BS_55AA, 0xAA55);			/* Signature (Offset is fixed here regardless of sector size) */
+	if (disk_write(pdrv, tbl, b_vol, 1) != RES_OK)	/* Write it to the VBR sector */
+		return FR_DISK_ERR;
+	if (fmt == FS_FAT32)					/* Write it to the backup VBR if needed (VBR + 6) */
+		disk_write(pdrv, tbl, b_vol + 6, 1);
+
+	/* Initialize FAT area */
+	wsect = b_fat;
+	for (i = 0; i < N_FATS; i++) {		/* Initialize each FAT copy */
+		mem_set(tbl, 0, SS(fs));			/* 1st sector of the FAT  */
+		n = md;								/* Media descriptor byte */
+		if (fmt != FS_FAT32) {
+			n |= (fmt == FS_FAT12) ? 0x00FFFF00 : 0xFFFFFF00;
+			ST_DWORD(tbl + 0, n);			/* Reserve cluster #0-1 (FAT12/16) */
+		} else {
+			n |= 0xFFFFFF00;
+			ST_DWORD(tbl + 0, n);			/* Reserve cluster #0-1 (FAT32) */
+			ST_DWORD(tbl + 4, 0xFFFFFFFF);
+			ST_DWORD(tbl + 8, 0x0FFFFFFF);	/* Reserve cluster #2 for root directory */
+		}
+		if (disk_write(pdrv, tbl, wsect++, 1) != RES_OK)
+			return FR_DISK_ERR;
+		mem_set(tbl, 0, SS(fs));			/* Fill following FAT entries with zero */
+		for (n = 1; n < n_fat; n++) {		/* This loop may take a time on FAT32 volume due to many single sector writes */
+			if (disk_write(pdrv, tbl, wsect++, 1) != RES_OK)
+				return FR_DISK_ERR;
+		}
+	}
+
+	/* Initialize root directory */
+	i = (fmt == FS_FAT32) ? au : (UINT)n_dir;
+	do {
+		if (disk_write(pdrv, tbl, wsect++, 1) != RES_OK)
+			return FR_DISK_ERR;
+	} while (--i);
+
+#if _USE_TRIM	/* Erase data area if needed */
+	{
+		eb[0] = wsect; eb[1] = wsect + (n_clst - ((fmt == FS_FAT32) ? 1 : 0)) * au - 1;
+		disk_ioctl(pdrv, CTRL_TRIM, eb);
+	}
+#endif
+
+	/* Create FSINFO if needed */
+	if (fmt == FS_FAT32) {
+		ST_DWORD(tbl + FSI_LeadSig, 0x41615252);
+		ST_DWORD(tbl + FSI_StrucSig, 0x61417272);
+		ST_DWORD(tbl + FSI_Free_Count, n_clst - 1);	/* Number of free clusters */
+		ST_DWORD(tbl + FSI_Nxt_Free, 2);			/* Last allocated cluster# */
+		ST_WORD(tbl + BS_55AA, 0xAA55);
+		disk_write(pdrv, tbl, b_vol + 1, 1);	/* Write original (VBR + 1) */
+		disk_write(pdrv, tbl, b_vol + 7, 1);	/* Write backup (VBR + 7) */
+	}
+
+	return (disk_ioctl(pdrv, CTRL_SYNC, 0) == RES_OK) ? FR_OK : FR_DISK_ERR;
+}
+
+#if _MULTI_PARTITION
+/*-----------------------------------------------------------------------*/
+/* Create partition table on the physical drive                          */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_fdisk (
+	BYTE pdrv,			/* Physical drive number */
+	const DWORD szt[],	/* Pointer to the size table for each partitions */
+	void* work			/* Pointer to the working buffer */
+)
+{
+	UINT i, n, sz_cyl, tot_cyl, b_cyl, e_cyl, p_cyl;
+	BYTE s_hd, e_hd, *p, *buf = (BYTE*)work;
+	DSTATUS stat;
+	DWORD sz_disk, sz_part, s_part;
+
+	stat = disk_initialize(pdrv);
+	if (stat & STA_NOINIT) return FR_NOT_READY;
+	if (stat & STA_PROTECT) return FR_WRITE_PROTECTED;
+	if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_disk)) return FR_DISK_ERR;
+
+	/* Determine CHS in the table regardless of the drive geometry */
+	for (n = 16; n < 256 && sz_disk / n / 63 > 1024; n *= 2) ;
+	if (n == 256) n--;
+	e_hd = n - 1;
+	sz_cyl = 63 * n;
+	tot_cyl = sz_disk / sz_cyl;
+
+	/* Create partition table */
+	mem_set(buf, 0, _MAX_SS);
+	p = buf + MBR_Table; b_cyl = 0;
+	for (i = 0; i < 4; i++, p += SZ_PTE) {
+		p_cyl = (szt[i] <= 100U) ? (DWORD)tot_cyl * szt[i] / 100 : szt[i] / sz_cyl;
+		if (!p_cyl) continue;
+		s_part = (DWORD)sz_cyl * b_cyl;
+		sz_part = (DWORD)sz_cyl * p_cyl;
+		if (i == 0) {	/* Exclude first track of cylinder 0 */
+			s_hd = 1;
+			s_part += 63; sz_part -= 63;
+		} else {
+			s_hd = 0;
+		}
+		e_cyl = b_cyl + p_cyl - 1;
+		if (e_cyl >= tot_cyl) return FR_INVALID_PARAMETER;
+
+		/* Set partition table */
+		p[1] = s_hd;						/* Start head */
+		p[2] = (BYTE)((b_cyl >> 2) + 1);	/* Start sector */
+		p[3] = (BYTE)b_cyl;					/* Start cylinder */
+		p[4] = 0x06;						/* System type (temporary setting) */
+		p[5] = e_hd;						/* End head */
+		p[6] = (BYTE)((e_cyl >> 2) + 63);	/* End sector */
+		p[7] = (BYTE)e_cyl;					/* End cylinder */
+		ST_DWORD(p + 8, s_part);			/* Start sector in LBA */
+		ST_DWORD(p + 12, sz_part);			/* Partition size */
+
+		/* Next partition */
+		b_cyl += p_cyl;
+	}
+	ST_WORD(p, 0xAA55);
+
+	/* Write it to the MBR */
+	return (disk_write(pdrv, buf, 0, 1) != RES_OK || disk_ioctl(pdrv, CTRL_SYNC, 0) != RES_OK) ? FR_DISK_ERR : FR_OK;
+}
+
+#endif /* _MULTI_PARTITION */
+#endif /* _USE_MKFS && !_FS_READONLY */
+
+#if _USE_STRFUNC
+/*-----------------------------------------------------------------------*/
+/* Get a string from the file                                            */
+/*-----------------------------------------------------------------------*/
+
+TCHAR* f_gets (
+	TCHAR* buff,	/* Pointer to the string buffer to read */
+	int len,		/* Size of string buffer (characters) */
+	FIL* fp			/* Pointer to the file object */
+)
+{
+	int n = 0;
+	TCHAR c, *p = buff;
+	BYTE s[2];
+	UINT rc;
+
+	while (n < len - 1) {	/* Read characters until buffer gets filled */
+#if _USE_LFN && _LFN_UNICODE
+#if _STRF_ENCODE == 3		/* Read a character in UTF-8 */
+		f_read(fp, s, 1, &rc);
+		if (rc != 1) break;
+		c = s[0];
+		if (c >= 0x80) {
+			if (c < 0xC0) continue;	/* Skip stray trailer */
+			if (c < 0xE0) {			/* Two-byte sequence */
+				f_read(fp, s, 1, &rc);
+				if (rc != 1) break;
+				c = (c & 0x1F) << 6 | (s[0] & 0x3F);
+				if (c < 0x80) c = '?';
+			} else {
+				if (c < 0xF0) {		/* Three-byte sequence */
+					f_read(fp, s, 2, &rc);
+					if (rc != 2) break;
+					c = c << 12 | (s[0] & 0x3F) << 6 | (s[1] & 0x3F);
+					if (c < 0x800) c = '?';
+				} else {			/* Reject four-byte sequence */
+					c = '?';
+				}
+			}
+		}
+#elif _STRF_ENCODE == 2		/* Read a character in UTF-16BE */
+		f_read(fp, s, 2, &rc);
+		if (rc != 2) break;
+		c = s[1] + (s[0] << 8);
+#elif _STRF_ENCODE == 1		/* Read a character in UTF-16LE */
+		f_read(fp, s, 2, &rc);
+		if (rc != 2) break;
+		c = s[0] + (s[1] << 8);
+#else						/* Read a character in ANSI/OEM */
+		f_read(fp, s, 1, &rc);
+		if (rc != 1) break;
+		c = s[0];
+		if (IsDBCS1(c)) {
+			f_read(fp, s, 1, &rc);
+			if (rc != 1) break;
+			c = (c << 8) + s[0];
+		}
+		c = ff_convert(c, 1);	/* OEM -> Unicode */
+		if (!c) c = '?';
+#endif
+#else						/* Read a character without conversion */
+		f_read(fp, s, 1, &rc);
+		if (rc != 1) break;
+		c = s[0];
+#endif
+		if (_USE_STRFUNC == 2 && c == '\r') continue;	/* Strip '\r' */
+		*p++ = c;
+		n++;
+		if (c == '\n') break;		/* Break on EOL */
+	}
+	*p = 0;
+	return n ? buff : 0;			/* When no data read (eof or error), return with error. */
+}
+
+#if !_FS_READONLY
+#include <stdarg.h>
+/*-----------------------------------------------------------------------*/
+/* Put a character to the file                                           */
+/*-----------------------------------------------------------------------*/
+
+typedef struct {
+	FIL* fp;
+	int idx, nchr;
+	BYTE buf[64];
+} putbuff;
+
+static
+void putc_bfd (
+	putbuff* pb,
+	TCHAR c
+)
+{
+	UINT bw;
+	int i;
+
+	if (_USE_STRFUNC == 2 && c == '\n')	 /* LF -> CRLF conversion */
+		putc_bfd(pb, '\r');
+
+	i = pb->idx;	/* Buffer write index (-1:error) */
+	if (i < 0) return;
+
+#if _USE_LFN && _LFN_UNICODE
+#if _STRF_ENCODE == 3			/* Write a character in UTF-8 */
+	if (c < 0x80) {				/* 7-bit */
+		pb->buf[i++] = (BYTE)c;
+	} else {
+		if (c < 0x800) {		/* 11-bit */
+			pb->buf[i++] = (BYTE)(0xC0 | c >> 6);
+		} else {				/* 16-bit */
+			pb->buf[i++] = (BYTE)(0xE0 | c >> 12);
+			pb->buf[i++] = (BYTE)(0x80 | (c >> 6 & 0x3F));
+		}
+		pb->buf[i++] = (BYTE)(0x80 | (c & 0x3F));
+	}
+#elif _STRF_ENCODE == 2			/* Write a character in UTF-16BE */
+	pb->buf[i++] = (BYTE)(c >> 8);
+	pb->buf[i++] = (BYTE)c;
+#elif _STRF_ENCODE == 1			/* Write a character in UTF-16LE */
+	pb->buf[i++] = (BYTE)c;
+	pb->buf[i++] = (BYTE)(c >> 8);
+#else							/* Write a character in ANSI/OEM */
+	c = ff_convert(c, 0);	/* Unicode -> OEM */
+	if (!c) c = '?';
+	if (c >= 0x100)
+		pb->buf[i++] = (BYTE)(c >> 8);
+	pb->buf[i++] = (BYTE)c;
+#endif
+#else							/* Write a character without conversion */
+	pb->buf[i++] = (BYTE)c;
+#endif
+
+	if (i >= (int)(sizeof pb->buf) - 3) {	/* Write buffered characters to the file */
+		f_write(pb->fp, pb->buf, (UINT)i, &bw);
+		i = (bw == (UINT)i) ? 0 : -1;
+	}
+	pb->idx = i;
+	pb->nchr++;
+}
+
+int f_putc (
+	TCHAR c,	/* A character to be output */
+	FIL* fp		/* Pointer to the file object */
+)
+{
+	putbuff pb;
+	UINT nw;
+
+	pb.fp = fp;			/* Initialize output buffer */
+	pb.nchr = pb.idx = 0;
+
+	putc_bfd(&pb, c);	/* Put a character */
+
+	if (   pb.idx >= 0	/* Flush buffered characters to the file */
+		&& f_write(pb.fp, pb.buf, (UINT)pb.idx, &nw) == FR_OK
+		&& (UINT)pb.idx == nw) return pb.nchr;
+	return EOF;
+}
+
+/*-----------------------------------------------------------------------*/
+/* Put a string to the file                                              */
+/*-----------------------------------------------------------------------*/
+
+int f_puts (
+	const TCHAR* str,	/* Pointer to the string to be output */
+	FIL* fp				/* Pointer to the file object */
+)
+{
+	putbuff pb;
+	UINT nw;
+
+	pb.fp = fp;				/* Initialize output buffer */
+	pb.nchr = pb.idx = 0;
+
+	while (*str)			/* Put the string */
+		putc_bfd(&pb, *str++);
+
+	if (   pb.idx >= 0		/* Flush buffered characters to the file */
+		&& f_write(pb.fp, pb.buf, (UINT)pb.idx, &nw) == FR_OK
+		&& (UINT)pb.idx == nw) return pb.nchr;
+	return EOF;
+}
+
+/*-----------------------------------------------------------------------*/
+/* Put a formatted string to the file                                    */
+/*-----------------------------------------------------------------------*/
+
+int f_printf (
+	FIL* fp,			/* Pointer to the file object */
+	const TCHAR* fmt,	/* Pointer to the format string */
+	...					/* Optional arguments... */
+)
+{
+	va_list arp;
+	BYTE f, r;
+	UINT nw, i, j, w;
+	DWORD v;
+	TCHAR c, d, s[16], *p;
+	putbuff pb;
+
+	pb.fp = fp;				/* Initialize output buffer */
+	pb.nchr = pb.idx = 0;
+
+	va_start(arp, fmt);
+
+	for (;;) {
+		c = *fmt++;
+		if (c == 0) break;			/* End of string */
+		if (c != '%') {				/* Non escape character */
+			putc_bfd(&pb, c);
+			continue;
+		}
+		w = f = 0;
+		c = *fmt++;
+		if (c == '0') {				/* Flag: '0' padding */
+			f = 1; c = *fmt++;
+		} else {
+			if (c == '-') {			/* Flag: left justified */
+				f = 2; c = *fmt++;
+			}
+		}
+		while (IsDigit(c)) {		/* Precision */
+			w = w * 10 + c - '0';
+			c = *fmt++;
+		}
+		if (c == 'l' || c == 'L') {	/* Prefix: Size is long int */
+			f |= 4; c = *fmt++;
+		}
+		if (!c) break;
+		d = c;
+		if (IsLower(d)) d -= 0x20;
+		switch (d) {				/* Type is... */
+		case 'S' :					/* String */
+			p = va_arg(arp, TCHAR*);
+			for (j = 0; p[j]; j++) ;
+			if (!(f & 2)) {
+				while (j++ < w) putc_bfd(&pb, ' ');
+			}
+			while (*p) putc_bfd(&pb, *p++);
+			while (j++ < w) putc_bfd(&pb, ' ');
+			continue;
+		case 'C' :					/* Character */
+			putc_bfd(&pb, (TCHAR)va_arg(arp, int)); continue;
+		case 'B' :					/* Binary */
+			r = 2; break;
+		case 'O' :					/* Octal */
+			r = 8; break;
+		case 'D' :					/* Signed decimal */
+		case 'U' :					/* Unsigned decimal */
+			r = 10; break;
+		case 'X' :					/* Hexdecimal */
+			r = 16; break;
+		default:					/* Unknown type (pass-through) */
+			putc_bfd(&pb, c); continue;
+		}
+
+		/* Get an argument and put it in numeral */
+		v = (f & 4) ? (DWORD)va_arg(arp, long) : ((d == 'D') ? (DWORD)(long)va_arg(arp, int) : (DWORD)va_arg(arp, unsigned int));
+		if (d == 'D' && (v & 0x80000000)) {
+			v = 0 - v;
+			f |= 8;
+		}
+		i = 0;
+		do {
+			d = (TCHAR)(v % r); v /= r;
+			if (d > 9) d += (c == 'x') ? 0x27 : 0x07;
+			s[i++] = d + '0';
+		} while (v && i < sizeof s / sizeof s[0]);
+		if (f & 8) s[i++] = '-';
+		j = i; d = (f & 1) ? '0' : ' ';
+		while (!(f & 2) && j++ < w) putc_bfd(&pb, d);
+		do putc_bfd(&pb, s[--i]); while (i);
+		while (j++ < w) putc_bfd(&pb, d);
+	}
+
+	va_end(arp);
+
+	if (   pb.idx >= 0		/* Flush buffered characters to the file */
+		&& f_write(pb.fp, pb.buf, (UINT)pb.idx, &nw) == FR_OK
+		&& (UINT)pb.idx == nw) return pb.nchr;
+	return EOF;
+}
+
+#endif /* !_FS_READONLY */
+#endif /* _USE_STRFUNC */
diff --git a/fatfs/src/ff.h b/fatfs/src/ff.h
new file mode 100644
index 0000000..7b4af7e
--- /dev/null
+++ b/fatfs/src/ff.h
@@ -0,0 +1,321 @@
+/*---------------------------------------------------------------------------/
+/  FatFs - FAT file system module include R0.11a    (C)ChaN, 2015
+/----------------------------------------------------------------------------/
+/ FatFs module is a free software that opened under license policy of
+/ following conditions.
+/
+/ Copyright (C) 2015, ChaN, all right reserved.
+/
+/ 1. Redistributions of source code must retain the above copyright notice,
+/    this condition and the following disclaimer.
+/
+/ This software is provided by the copyright holder and contributors "AS IS"
+/ and any warranties related to this software are DISCLAIMED.
+/ The copyright owner or contributors be NOT LIABLE for any damages caused
+/ by use of this software.
+/---------------------------------------------------------------------------*/
+
+#ifndef _FATFS
+#define _FATFS	64180	/* Revision ID */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ffconf.h"		/* FatFs configuration options */
+#include "integer.h"	/* Basic integer types */
+#if _FATFS != _FFCONF
+#error Wrong configuration file (ffconf.h).
+#endif
+
+/* Definitions of volume management */
+
+#if _MULTI_PARTITION		/* Multiple partition configuration */
+typedef struct {
+	BYTE pd;	/* Physical drive number */
+	BYTE pt;	/* Partition: 0:Auto detect, 1-4:Forced partition) */
+} PARTITION;
+extern PARTITION VolToPart[];	/* Volume - Partition resolution table */
+#define LD2PD(vol) (VolToPart[vol].pd)	/* Get physical drive number */
+#define LD2PT(vol) (VolToPart[vol].pt)	/* Get partition index */
+
+#else							/* Single partition configuration */
+#define LD2PD(vol) (BYTE)(vol)	/* Each logical drive is bound to the same physical drive number */
+#define LD2PT(vol) 0			/* Find first valid partition or in SFD */
+
+#endif
+
+/* Type of path name strings on FatFs API */
+
+#if _LFN_UNICODE			/* Unicode string */
+#if !_USE_LFN
+#error _LFN_UNICODE must be 0 at non-LFN cfg.
+#endif
+#ifndef _INC_TCHAR
+typedef WCHAR TCHAR;
+#define _T(x) L ## x
+#define _TEXT(x) L ## x
+#endif
+
+#else						/* ANSI/OEM string */
+#ifndef _INC_TCHAR
+typedef char TCHAR;
+#define _T(x) x
+#define _TEXT(x) x
+#endif
+
+#endif
+
+/* File system object structure (FATFS) */
+
+typedef struct {
+	BYTE	fs_type;		/* FAT sub-type (0:Not mounted) */
+	BYTE	drv;			/* Physical drive number */
+	BYTE	csize;			/* Sectors per cluster (1,2,4...128) */
+	BYTE	n_fats;			/* Number of FAT copies (1 or 2) */
+	BYTE	wflag;			/* win[] flag (b0:dirty) */
+	BYTE	fsi_flag;		/* FSINFO flags (b7:disabled, b0:dirty) */
+	WORD	id;				/* File system mount ID */
+	WORD	n_rootdir;		/* Number of root directory entries (FAT12/16) */
+#if _MAX_SS != _MIN_SS
+	WORD	ssize;			/* Bytes per sector (512, 1024, 2048 or 4096) */
+#endif
+#if _FS_REENTRANT
+	_SYNC_t	sobj;			/* Identifier of sync object */
+#endif
+#if !_FS_READONLY
+	DWORD	last_clust;		/* Last allocated cluster */
+	DWORD	free_clust;		/* Number of free clusters */
+#endif
+#if _FS_RPATH
+	DWORD	cdir;			/* Current directory start cluster (0:root) */
+#endif
+	DWORD	n_fatent;		/* Number of FAT entries, = number of clusters + 2 */
+	DWORD	fsize;			/* Sectors per FAT */
+	DWORD	volbase;		/* Volume start sector */
+	DWORD	fatbase;		/* FAT start sector */
+	DWORD	dirbase;		/* Root directory start sector (FAT32:Cluster#) */
+	DWORD	database;		/* Data start sector */
+	DWORD	winsect;		/* Current sector appearing in the win[] */
+	BYTE	win[_MAX_SS];	/* Disk access window for Directory, FAT (and file data at tiny cfg) */
+} FATFS;
+
+/* File object structure (FIL) */
+
+typedef struct {
+	FATFS*	fs;				/* Pointer to the related file system object (**do not change order**) */
+	WORD	id;				/* Owner file system mount ID (**do not change order**) */
+	BYTE	flag;			/* Status flags */
+	BYTE	err;			/* Abort flag (error code) */
+	DWORD	fptr;			/* File read/write pointer (Zeroed on file open) */
+	DWORD	fsize;			/* File size */
+	DWORD	sclust;			/* File start cluster (0:no cluster chain, always 0 when fsize is 0) */
+	DWORD	clust;			/* Current cluster of fpter (not valid when fprt is 0) */
+	DWORD	dsect;			/* Sector number appearing in buf[] (0:invalid) */
+#if !_FS_READONLY
+	DWORD	dir_sect;		/* Sector number containing the directory entry */
+	BYTE*	dir_ptr;		/* Pointer to the directory entry in the win[] */
+#endif
+#if _USE_FASTSEEK
+	DWORD*	cltbl;			/* Pointer to the cluster link map table (Nulled on file open) */
+#endif
+#if _FS_LOCK
+	UINT	lockid;			/* File lock ID origin from 1 (index of file semaphore table Files[]) */
+#endif
+#if !_FS_TINY
+	BYTE	buf[_MAX_SS];	/* File private data read/write window */
+#endif
+} FIL;
+
+/* Directory object structure (DIR) */
+
+typedef struct {
+	FATFS*	fs;				/* Pointer to the owner file system object (**do not change order**) */
+	WORD	id;				/* Owner file system mount ID (**do not change order**) */
+	WORD	index;			/* Current read/write index number */
+	DWORD	sclust;			/* Table start cluster (0:Root dir) */
+	DWORD	clust;			/* Current cluster */
+	DWORD	sect;			/* Current sector */
+	BYTE*	dir;			/* Pointer to the current SFN entry in the win[] */
+	BYTE*	fn;				/* Pointer to the SFN (in/out) {file[8],ext[3],status[1]} */
+#if _FS_LOCK
+	UINT	lockid;			/* File lock ID (index of file semaphore table Files[]) */
+#endif
+#if _USE_LFN
+	WCHAR*	lfn;			/* Pointer to the LFN working buffer */
+	WORD	lfn_idx;		/* Last matched LFN index number (0xFFFF:No LFN) */
+#endif
+#if _USE_FIND
+	const TCHAR*	pat;	/* Pointer to the name matching pattern */
+#endif
+} DIR;
+
+/* File information structure (FILINFO) */
+
+typedef struct {
+	DWORD	fsize;			/* File size */
+	WORD	fdate;			/* Last modified date */
+	WORD	ftime;			/* Last modified time */
+	BYTE	fattrib;		/* Attribute */
+	TCHAR	fname[13];		/* Short file name (8.3 format) */
+#if _USE_LFN
+	TCHAR*	lfname;			/* Pointer to the LFN buffer */
+	UINT 	lfsize;			/* Size of LFN buffer in TCHAR */
+#endif
+} FILINFO;
+
+/* File function return code (FRESULT) */
+
+typedef enum {
+	FR_OK = 0,				/* (0) Succeeded */
+	FR_DISK_ERR,			/* (1) A hard error occurred in the low level disk I/O layer */
+	FR_INT_ERR,				/* (2) Assertion failed */
+	FR_NOT_READY,			/* (3) The physical drive cannot work */
+	FR_NO_FILE,				/* (4) Could not find the file */
+	FR_NO_PATH,				/* (5) Could not find the path */
+	FR_INVALID_NAME,		/* (6) The path name format is invalid */
+	FR_DENIED,				/* (7) Access denied due to prohibited access or directory full */
+	FR_EXIST,				/* (8) Access denied due to prohibited access */
+	FR_INVALID_OBJECT,		/* (9) The file/directory object is invalid */
+	FR_WRITE_PROTECTED,		/* (10) The physical drive is write protected */
+	FR_INVALID_DRIVE,		/* (11) The logical drive number is invalid */
+	FR_NOT_ENABLED,			/* (12) The volume has no work area */
+	FR_NO_FILESYSTEM,		/* (13) There is no valid FAT volume */
+	FR_MKFS_ABORTED,		/* (14) The f_mkfs() aborted due to any parameter error */
+	FR_TIMEOUT,				/* (15) Could not get a grant to access the volume within defined period */
+	FR_LOCKED,				/* (16) The operation is rejected according to the file sharing policy */
+	FR_NOT_ENOUGH_CORE,		/* (17) LFN working buffer could not be allocated */
+	FR_TOO_MANY_OPEN_FILES,	/* (18) Number of open files > _FS_LOCK */
+	FR_INVALID_PARAMETER	/* (19) Given parameter is invalid */
+} FRESULT;
+
+/*--------------------------------------------------------------*/
+/* FatFs module application interface                           */
+
+FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode);				/* Open or create a file */
+FRESULT f_close (FIL* fp);											/* Close an open file object */
+FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br);			/* Read data from a file */
+FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw);	/* Write data to a file */
+FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf);	/* Forward data to the stream */
+FRESULT f_lseek (FIL* fp, DWORD ofs);								/* Move file pointer of a file object */
+FRESULT f_truncate (FIL* fp);										/* Truncate file */
+FRESULT f_sync (FIL* fp);											/* Flush cached data of a writing file */
+FRESULT f_opendir (DIR* dp, const TCHAR* path);						/* Open a directory */
+FRESULT f_closedir (DIR* dp);										/* Close an open directory */
+FRESULT f_readdir (DIR* dp, FILINFO* fno);							/* Read a directory item */
+FRESULT f_findfirst (DIR* dp, FILINFO* fno, const TCHAR* path, const TCHAR* pattern);	/* Find first file */
+FRESULT f_findnext (DIR* dp, FILINFO* fno);							/* Find next file */
+FRESULT f_mkdir (const TCHAR* path);								/* Create a sub directory */
+FRESULT f_unlink (const TCHAR* path);								/* Delete an existing file or directory */
+FRESULT f_rename (const TCHAR* path_old, const TCHAR* path_new);	/* Rename/Move a file or directory */
+FRESULT f_stat (const TCHAR* path, FILINFO* fno);					/* Get file status */
+FRESULT f_chmod (const TCHAR* path, BYTE attr, BYTE mask);			/* Change attribute of the file/dir */
+FRESULT f_utime (const TCHAR* path, const FILINFO* fno);			/* Change times-tamp of the file/dir */
+FRESULT f_chdir (const TCHAR* path);								/* Change current directory */
+FRESULT f_chdrive (const TCHAR* path);								/* Change current drive */
+FRESULT f_getcwd (TCHAR* buff, UINT len);							/* Get current directory */
+FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs);	/* Get number of free clusters on the drive */
+FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* vsn);	/* Get volume label */
+FRESULT f_setlabel (const TCHAR* label);							/* Set volume label */
+FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt);			/* Mount/Unmount a logical drive */
+FRESULT f_mkfs (const TCHAR* path, BYTE sfd, UINT au);				/* Create a file system on the volume */
+FRESULT f_fdisk (BYTE pdrv, const DWORD szt[], void* work);			/* Divide a physical drive into some partitions */
+int f_putc (TCHAR c, FIL* fp);										/* Put a character to the file */
+int f_puts (const TCHAR* str, FIL* cp);								/* Put a string to the file */
+int f_printf (FIL* fp, const TCHAR* str, ...);						/* Put a formatted string to the file */
+TCHAR* f_gets (TCHAR* buff, int len, FIL* fp);						/* Get a string from the file */
+
+#define f_eof(fp) ((int)((fp)->fptr == (fp)->fsize))
+#define f_error(fp) ((fp)->err)
+#define f_tell(fp) ((fp)->fptr)
+#define f_size(fp) ((fp)->fsize)
+#define f_rewind(fp) f_lseek((fp), 0)
+#define f_rewinddir(dp) f_readdir((dp), 0)
+
+#ifndef EOF
+#define EOF (-1)
+#endif
+
+/*--------------------------------------------------------------*/
+/* Additional user defined functions                            */
+
+/* RTC function */
+#if !_FS_READONLY && !_FS_NORTC
+DWORD get_fattime (void);
+#endif
+
+/* Unicode support functions */
+#if _USE_LFN							/* Unicode - OEM code conversion */
+WCHAR ff_convert (WCHAR chr, UINT dir);	/* OEM-Unicode bidirectional conversion */
+WCHAR ff_wtoupper (WCHAR chr);			/* Unicode upper-case conversion */
+#if _USE_LFN == 3						/* Memory functions */
+void* ff_memalloc (UINT msize);			/* Allocate memory block */
+void ff_memfree (void* mblock);			/* Free memory block */
+#endif
+#endif
+
+/* Sync functions */
+#if _FS_REENTRANT
+int ff_cre_syncobj (BYTE vol, _SYNC_t* sobj);	/* Create a sync object */
+int ff_req_grant (_SYNC_t sobj);				/* Lock sync object */
+void ff_rel_grant (_SYNC_t sobj);				/* Unlock sync object */
+int ff_del_syncobj (_SYNC_t sobj);				/* Delete a sync object */
+#endif
+
+/*--------------------------------------------------------------*/
+/* Flags and offset address                                     */
+
+/* File access control and file status flags (FIL.flag) */
+
+#define	FA_READ				0x01
+#define	FA_OPEN_EXISTING	0x00
+
+#if !_FS_READONLY
+#define	FA_WRITE			0x02
+#define	FA_CREATE_NEW		0x04
+#define	FA_CREATE_ALWAYS	0x08
+#define	FA_OPEN_ALWAYS		0x10
+#define FA__WRITTEN			0x20
+#define FA__DIRTY			0x40
+#endif
+
+/* FAT sub type (FATFS.fs_type) */
+
+#define FS_FAT12	1
+#define FS_FAT16	2
+#define FS_FAT32	3
+
+/* File attribute bits for directory entry */
+
+#define	AM_RDO	0x01	/* Read only */
+#define	AM_HID	0x02	/* Hidden */
+#define	AM_SYS	0x04	/* System */
+#define	AM_VOL	0x08	/* Volume label */
+#define AM_LFN	0x0F	/* LFN entry */
+#define AM_DIR	0x10	/* Directory */
+#define AM_ARC	0x20	/* Archive */
+#define AM_MASK	0x3F	/* Mask of defined bits */
+
+/* Fast seek feature */
+#define CREATE_LINKMAP	0xFFFFFFFF
+
+/*--------------------------------*/
+/* Multi-byte word access macros  */
+
+#if _WORD_ACCESS == 1	/* Enable word access to the FAT structure */
+#define	LD_WORD(ptr)		(WORD)(*(WORD*)(BYTE*)(ptr))
+#define	LD_DWORD(ptr)		(DWORD)(*(DWORD*)(BYTE*)(ptr))
+#define	ST_WORD(ptr,val)	*(WORD*)(BYTE*)(ptr)=(WORD)(val)
+#define	ST_DWORD(ptr,val)	*(DWORD*)(BYTE*)(ptr)=(DWORD)(val)
+#else					/* Use byte-by-byte access to the FAT structure */
+#define	LD_WORD(ptr)		(WORD)(((WORD)*((BYTE*)(ptr)+1)<<8)|(WORD)*(BYTE*)(ptr))
+#define	LD_DWORD(ptr)		(DWORD)(((DWORD)*((BYTE*)(ptr)+3)<<24)|((DWORD)*((BYTE*)(ptr)+2)<<16)|((WORD)*((BYTE*)(ptr)+1)<<8)|*(BYTE*)(ptr))
+#define	ST_WORD(ptr,val)	*(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8)
+#define	ST_DWORD(ptr,val)	*(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8); *((BYTE*)(ptr)+2)=(BYTE)((DWORD)(val)>>16); *((BYTE*)(ptr)+3)=(BYTE)((DWORD)(val)>>24)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FATFS */
diff --git a/fatfs/src/ffconf.h b/fatfs/src/ffconf.h
new file mode 100644
index 0000000..1ac0ea9
--- /dev/null
+++ b/fatfs/src/ffconf.h
@@ -0,0 +1,253 @@
+/*---------------------------------------------------------------------------/
+/  FatFs - FAT file system module configuration file  R0.11a (C)ChaN, 2015
+/---------------------------------------------------------------------------*/
+#include "conf_fatfs.h"
+#ifdef DEFAULT_CONFIG
+#define _FFCONF 64180	/* Revision ID */
+
+/*---------------------------------------------------------------------------/
+/ Function Configurations
+/---------------------------------------------------------------------------*/
+
+#define _FS_READONLY	0
+/* This option switches read-only configuration. (0:Read/Write or 1:Read-only)
+/  Read-only configuration removes writing API functions, f_write(), f_sync(),
+/  f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree()
+/  and optional writing functions as well. */
+
+#define _FS_MINIMIZE	0
+/* This option defines minimization level to remove some basic API functions.
+/
+/   0: All basic functions are enabled.
+/   1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_chmod(), f_utime(),
+/      f_truncate() and f_rename() function are removed.
+/   2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1.
+/   3: f_lseek() function is removed in addition to 2. */
+
+#define	_USE_STRFUNC	1
+/* This option switches string functions, f_gets(), f_putc(), f_puts() and
+/  f_printf().
+/
+/  0: Disable string functions.
+/  1: Enable without LF-CRLF conversion.
+/  2: Enable with LF-CRLF conversion. */
+
+#define _USE_FIND		1
+/* This option switches filtered directory read feature and related functions,
+/  f_findfirst() and f_findnext(). (0:Disable or 1:Enable) */
+
+#define	_USE_MKFS		1
+/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */
+
+#define	_USE_FASTSEEK	0
+/* This option switches fast seek feature. (0:Disable or 1:Enable) */
+
+#define _USE_LABEL		1
+/* This option switches volume label functions, f_getlabel() and f_setlabel().
+/  (0:Disable or 1:Enable) */
+
+#define	_USE_FORWARD	1
+/* This option switches f_forward() function. (0:Disable or 1:Enable)
+/  To enable it, also _FS_TINY need to be set to 1. */
+
+/*---------------------------------------------------------------------------/
+/ Locale and Namespace Configurations
+/---------------------------------------------------------------------------*/
+
+#define _CODE_PAGE	932
+/* This option specifies the OEM code page to be used on the target system.
+/  Incorrect setting of the code page can cause a file open failure.
+/
+/   1   - ASCII (No extended character. Non-LFN cfg. only)
+/   437 - U.S.
+/   720 - Arabic
+/   737 - Greek
+/   771 - KBL
+/   775 - Baltic
+/   850 - Latin 1
+/   852 - Latin 2
+/   855 - Cyrillic
+/   857 - Turkish
+/   860 - Portuguese
+/   861 - Icelandic
+/   862 - Hebrew
+/   863 - Canadian French
+/   864 - Arabic
+/   865 - Nordic
+/   866 - Russian
+/   869 - Greek 2
+/   932 - Japanese (DBCS)
+/   936 - Simplified Chinese (DBCS)
+/   949 - Korean (DBCS)
+/   950 - Traditional Chinese (DBCS)
+*/
+
+#define	_USE_LFN	0	
+#define	_MAX_LFN	255
+/* The _USE_LFN option switches the LFN feature.
+/
+/   0: Disable LFN feature. _MAX_LFN has no effect.
+/   1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe.
+/   2: Enable LFN with dynamic working buffer on the STACK.
+/   3: Enable LFN with dynamic working buffer on the HEAP.
+/
+/  When enable the LFN feature, Unicode handling functions (option/unicode.c) must
+/  be added to the project. The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes.
+/  When use stack for the working buffer, take care on stack overflow. When use heap
+/  memory for the working buffer, memory management functions, ff_memalloc() and
+/  ff_memfree(), must be added to the project. */
+
+#define	_LFN_UNICODE	0
+/* This option switches character encoding on the API. (0:ANSI/OEM or 1:Unicode)
+/  To use Unicode string for the path name, enable LFN feature and set _LFN_UNICODE
+/  to 1. This option also affects behavior of string I/O functions. */
+
+#define _STRF_ENCODE	3
+/* When _LFN_UNICODE is 1, this option selects the character encoding on the file to
+/  be read/written via string I/O functions, f_gets(), f_putc(), f_puts and f_printf().
+/
+/  0: ANSI/OEM
+/  1: UTF-16LE
+/  2: UTF-16BE
+/  3: UTF-8
+/
+/  When _LFN_UNICODE is 0, this option has no effect. */
+
+#define _FS_RPATH	2
+/* This option configures relative path feature.
+/
+/   0: Disable relative path feature and remove related functions.
+/   1: Enable relative path feature. f_chdir() and f_chdrive() are available.
+/   2: f_getcwd() function is available in addition to 1.
+/
+/  Note that directory items read via f_readdir() are affected by this option. */
+
+/*---------------------------------------------------------------------------/
+/ Drive/Volume Configurations
+/---------------------------------------------------------------------------*/
+
+#define _VOLUMES	1
+/* Number of volumes (logical drives) to be used. */
+
+#define _STR_VOLUME_ID	0
+#define _VOLUME_STRS	"RAM","NAND","CF","SD1","SD2","USB1","USB2","USB3"
+/* _STR_VOLUME_ID option switches string volume ID feature.
+/  When _STR_VOLUME_ID is set to 1, also pre-defined strings can be used as drive
+/  number in the path name. _VOLUME_STRS defines the drive ID strings for each
+/  logical drives. Number of items must be equal to _VOLUMES. Valid characters for
+/  the drive ID strings are: A-Z and 0-9. */
+
+#define	_MULTI_PARTITION	0
+/* This option switches multi-partition feature. By default (0), each logical drive
+/  number is bound to the same physical drive number and only an FAT volume found on
+/  the physical drive will be mounted. When multi-partition feature is enabled (1),
+/  each logical drive number is bound to arbitrary physical drive and partition
+/  listed in the VolToPart[]. Also f_fdisk() funciton will be available. */
+
+#define	_MIN_SS		512
+#define	_MAX_SS		512
+/* These options configure the range of sector size to be supported. (512, 1024,
+/  2048 or 4096) Always set both 512 for most systems, all type of memory cards and
+/  harddisk. But a larger value may be required for on-board flash memory and some
+/  type of optical media. When _MAX_SS is larger than _MIN_SS, FatFs is configured
+/  to variable sector size and GET_SECTOR_SIZE command must be implemented to the
+/  disk_ioctl() function. */
+
+#define	_USE_TRIM	0
+/* This option switches ATA-TRIM feature. (0:Disable or 1:Enable)
+/  To enable Trim feature, also CTRL_TRIM command should be implemented to the
+/  disk_ioctl() function. */
+
+#define _FS_NOFSINFO	0
+/* If you need to know correct free space on the FAT32 volume, set bit 0 of this
+/  option, and f_getfree() function at first time after volume mount will force
+/  a full FAT scan. Bit 1 controls the use of last allocated cluster number.
+/
+/  bit0=0: Use free cluster count in the FSINFO if available.
+/  bit0=1: Do not trust free cluster count in the FSINFO.
+/  bit1=0: Use last allocated cluster number in the FSINFO if available.
+/  bit1=1: Do not trust last allocated cluster number in the FSINFO.
+*/
+
+/*---------------------------------------------------------------------------/
+/ System Configurations
+/---------------------------------------------------------------------------*/
+
+#define	_FS_TINY	1
+/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny)
+/  At the tiny configuration, size of the file object (FIL) is reduced _MAX_SS
+/  bytes. Instead of private sector buffer eliminated from the file object,
+/  common sector buffer in the file system object (FATFS) is used for the file
+/  data transfer. */
+
+#define _FS_NORTC	0
+#define _NORTC_MON	1
+#define _NORTC_MDAY	1
+#define _NORTC_YEAR	2015
+/* The _FS_NORTC option switches timestamp feature. If the system does not have
+/  an RTC function or valid timestamp is not needed, set _FS_NORTC to 1 to disable
+/  the timestamp feature. All objects modified by FatFs will have a fixed timestamp
+/  defined by _NORTC_MON, _NORTC_MDAY and _NORTC_YEAR.
+/  When timestamp feature is enabled (_FS_NORTC == 0), get_fattime() function need
+/  to be added to the project to read current time form RTC. _NORTC_MON,
+/  _NORTC_MDAY and _NORTC_YEAR have no effect. 
+/  These options have no effect at read-only configuration (_FS_READONLY == 1). */
+
+#define	_FS_LOCK	0
+/* The _FS_LOCK option switches file lock feature to control duplicated file open
+/  and illegal operation to open objects. This option must be 0 when _FS_READONLY
+/  is 1.
+/
+/  0:  Disable file lock feature. To avoid volume corruption, application program
+/      should avoid illegal open, remove and rename to the open objects.
+/  >0: Enable file lock feature. The value defines how many files/sub-directories
+/      can be opened simultaneously under file lock control. Note that the file
+/      lock feature is independent of re-entrancy. */
+
+#define _FS_REENTRANT	0
+#define _FS_TIMEOUT		1000
+#define	_SYNC_t			HANDLE
+/* The _FS_REENTRANT option switches the re-entrancy (thread safe) of the FatFs
+/  module itself. Note that regardless of this option, file access to different
+/  volume is always re-entrant and volume control functions, f_mount(), f_mkfs()
+/  and f_fdisk() function, are always not re-entrant. Only file/directory access
+/  to the same volume is under control of this feature.
+/
+/   0: Disable re-entrancy. _FS_TIMEOUT and _SYNC_t have no effect.
+/   1: Enable re-entrancy. Also user provided synchronization handlers,
+/      ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj()
+/      function, must be added to the project. Samples are available in
+/      option/syscall.c.
+/
+/  The _FS_TIMEOUT defines timeout period in unit of time tick.
+/  The _SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*,
+/  SemaphoreHandle_t and etc.. A header file for O/S definitions needs to be
+/  included somewhere in the scope of ff.c. */
+
+#define _WORD_ACCESS	0
+/* The _WORD_ACCESS option is an only platform dependent option. It defines
+/  which access method is used to the word data on the FAT volume.
+/
+/   0: Byte-by-byte access. Always compatible with all platforms.
+/   1: Word access. Do not choose this unless under both the following conditions.
+/
+/  * Address misaligned memory access is always allowed to ALL instructions.
+/  * Byte order on the memory is little-endian.
+/
+/  If it is the case, _WORD_ACCESS can also be set to 1 to reduce code size.
+/  Following table shows allowable settings of some type of processors.
+/
+/  ARM7TDMI   0   *2          ColdFire   0    *1         V850E      0    *2
+/  Cortex-M3  0   *3          Z80        0/1             V850ES     0/1
+/  Cortex-M0  0   *2          x86        0/1             TLCS-870   0/1
+/  AVR        0/1             RX600(LE)  0/1             TLCS-900   0/1
+/  AVR32      0   *1          RL78       0    *2         R32C       0    *2
+/  PIC18      0/1             SH-2       0    *1         M16C       0/1
+/  PIC24      0   *2          H8S        0    *1         MSP430     0    *2
+/  PIC32      0   *1          H8/300H    0    *1         8051       0/1
+/
+/  *1:Big-endian.
+/  *2:Unaligned memory access is not supported.
+/  *3:Some compilers generate LDM/STM for mem_cpy function.
+*/
+#endif
diff --git a/fatfs/src/integer.h b/fatfs/src/integer.h
new file mode 100644
index 0000000..d04bbf3
--- /dev/null
+++ b/fatfs/src/integer.h
@@ -0,0 +1,33 @@
+/*-------------------------------------------*/
+/* Integer type definitions for FatFs module */
+/*-------------------------------------------*/
+
+#ifndef _FF_INTEGER
+#define _FF_INTEGER
+
+#ifdef _WIN32	/* Development platform */
+
+#include <tchar.h>
+#include <windows.h>
+
+#else			/* Embedded platform */
+
+/* This type MUST be 8-bit */
+typedef unsigned char	BYTE;
+
+/* These types MUST be 16-bit */
+typedef short			SHORT;
+typedef unsigned short	WORD;
+typedef unsigned short	WCHAR;
+
+/* These types MUST be 16-bit or 32-bit */
+typedef int				INT;
+typedef unsigned int	UINT;
+
+/* These types MUST be 32-bit */
+typedef long			LONG;
+typedef unsigned long	DWORD;
+
+#endif
+
+#endif
diff --git a/fatfs_main.c b/fatfs_main.c
new file mode 100644
index 0000000..06ef575
--- /dev/null
+++ b/fatfs_main.c
@@ -0,0 +1,44 @@
+/*
+ * Code generated from Atmel Start.
+ *
+ * This file will be overwritten when reconfiguring your Atmel Start project.
+ * Please copy examples or other code you want to keep to a separate file or main.c
+ * to avoid loosing it when reconfiguring.
+ */
+
+#include "fatfs_main.h"
+
+/**
+ * \brief Current time returned is packed into a DWORD value.
+ *
+ * The bit field is as follows:
+ *
+ * bit31:25  Year from 1980 (0..127)
+ *
+ * bit24:21  Month (1..12)
+ *
+ * bit20:16  Day in month(1..31)
+ *
+ * bit15:11  Hour (0..23)
+ *
+ * bit10:5   Minute (0..59)
+ *
+ * bit4:0    Second (0..59)
+ *
+ * \return Current time.
+ */
+DWORD get_fattime(void)
+{
+	uint32_t                  ul_time;
+	struct calendar_date_time datetime;
+	calendar_get_date_time(&CALENDER_INTERFACE, &datetime);
+
+	ul_time = ((datetime.date.year - 1980) << 25) | (datetime.date.month << 21) | (datetime.date.day << 16)
+	          | (datetime.time.hour << 11) | (datetime.time.min << 5) | (datetime.time.sec << 0);
+	return ul_time;
+}
+
+void fatfs_app_init(void)
+{
+	/*Low layer module initialisation to be added*/
+}
diff --git a/fatfs_main.h b/fatfs_main.h
new file mode 100644
index 0000000..6134569
--- /dev/null
+++ b/fatfs_main.h
@@ -0,0 +1,31 @@
+/*
+ * Code generated from Atmel Start.
+ *
+ * This file will be overwritten when reconfiguring your Atmel Start project.
+ * Please copy examples or other code you want to keep to a separate file or main.c
+ * to avoid loosing it when reconfiguring.
+ */
+#ifndef FATFS_MAIN_H
+#define FATFS_MAIN_H
+
+#include "atmel_start.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif // __cplusplus
+
+#include <string.h>
+#include <hal_calendar.h>
+#include "ff.h"
+
+extern struct calendar_descriptor CALENDER_INTERFACE;
+
+DWORD get_fattime(void);
+
+void fatfs_app_init(void);
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif // FATFS_MAIN_H
diff --git a/hal/documentation/calendar.rst b/hal/documentation/calendar.rst
new file mode 100644
index 0000000..8a3de6e
--- /dev/null
+++ b/hal/documentation/calendar.rst
@@ -0,0 +1,72 @@
+===============================
+The Calendar driver (bare-bone)
+===============================
+
+The Calendar driver provides means to set and get current date and time.
+After enabling, an instance of the driver starts counting time from the base date with
+the resolution of one second. The default base date is 00:00:00 1st of January 1970.
+Only the base year of the base date can be changed via the driver API.
+
+The current date and time is kept internally in a relative form as the difference between
+current date and time and the base date and time. This means that changing the base year changes
+current date.
+
+The base date and time defines time "zero" or the earliest possible point in time that the calender driver can describe,
+this means that current time and alarms can not be set to anything earlier than this time.
+
+The Calendar driver provides alarm functionality.
+An alarm is a software trigger which fires on particular date and time with particular periodicity.
+Upon firing the given callback function is called.
+
+An alarm can be in single-shot mode, firing only once at matching time; or in repeating mode, meaning that it will
+reschedule a new alarm automatically based on repeating mode configuration.
+In single-shot mode an alarm is removed from the alarm queue before its callback is called. It allows an application to
+reuse the memory of expired alarm in the callback.
+
+An alarm can be triggered on the following events: match on second, minute, hour, day, month or year.
+Matching on second means that the alarm is triggered when the value of seconds of the current time is equal to
+the alarm's value of seconds. This means repeating alarm with match on seconds is triggered with the period of a minute.
+Matching on minute means that the calendars minute and seconds values has to match the alarms, the rest of the date-time
+value is ignored. In repeating mode this means a new alarm every hour.
+The same logic is applied to match on hour, day, month and year.
+
+Each instance of the Calendar driver supports infinite amount of software alarms, only limited by the amount of RAM available.
+
+Features
+--------
+* Initialization and de-initialization
+* Enabling and disabling
+* Date and time operations
+* Software alarms
+
+Applications
+------------
+* A source of current date and time for an embedded system.
+* Periodical functionality in low-power applications since the driver is designed to use 1Hz clock.
+* Periodical function calls in case if it is more convenient to operate with absolute time.
+
+Dependencies
+------------
+* This driver expects a counter to be increased by one every second to count date and time correctly.
+* Each instance of the driver requires separate hardware timer.
+
+Concurrency
+-----------
+The Calendar driver is an interrupt driven driver.This means that the interrupt that triggers an alarm may occur during
+the process of adding or removing an alarm via the driver's API. In such case the interrupt processing is postponed
+until the alarm adding or removing is complete.
+
+The alarm queue is not protected from the access by interrupts not used by the driver. Due to this
+it is not recommended to add or remove an alarm from such interrupts: in case if a higher priority interrupt supersedes
+the driver's interrupt, adding or removing an alarm may cause unpredictable behavior of the driver.
+
+Limitations
+-----------
+* Only years divisible by 4 are deemed a leap year, this gives a correct result between the years 1901 to 2099.
+* The driver is designed to work outside of an operating system environment, the software alarm queue is therefore processed in interrupt context which may delay execution of other interrupts.
+* If there are a lot of frequently called interrupts with the priority higher than the driver's one, it may cause delay in alarm's triggering.
+* Changing the base year or setting current date or time does not shift alarms' date and time accordingly or expires alarms.
+
+Knows issues and workarounds
+----------------------------
+Not applicable
diff --git a/hal/documentation/mci_sync.rst b/hal/documentation/mci_sync.rst
new file mode 100644
index 0000000..5c37c23
--- /dev/null
+++ b/hal/documentation/mci_sync.rst
@@ -0,0 +1,39 @@
+The MCI Synchronous Driver
+============================
+
+The MCI (Multimedia Card / Memory Card Interface) synchronous driver is used for a high
+level stack implementation, which supports MultiMedia Card (MMC) Specification V4.3,
+the SD Memory Card Specification V2.0, and the SDIO V2.0 specification.
+
+Features
+--------
+
+* Initialization/de-initialization
+* Device selection/de-selection
+* Sending command on the selected slot
+* Data transfer: reading, writing
+
+Applications
+------------
+
+They are commonly used in an application for reading and writing SD/MMC/SDIO type card.
+
+Dependencies
+------------
+
+Multimedia Card / Memory Card Interface capable hardware.
+
+Concurrency
+-----------
+
+N.A
+
+Limitations
+-----------
+
+N.A
+
+Known issues and workarounds
+----------------------------
+
+N/A
diff --git a/hal/include/hal_calendar.h b/hal/include/hal_calendar.h
new file mode 100644
index 0000000..26949a5
--- /dev/null
+++ b/hal/include/hal_calendar.h
@@ -0,0 +1,159 @@
+/**
+ * \file
+ *
+ * \brief Generic CALENDAR functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HAL_CALENDER_H_INCLUDED
+#define _HAL_CALENDER_H_INCLUDED
+
+#include "hpl_calendar.h"
+#include <utils_list.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_calendar_async
+ *
+ *@{
+ */
+
+/** \brief Prototype of callback on alarm match
+ *  \param calendar Pointer to the HAL Calendar instance.
+ */
+typedef void (*calendar_cb_alarm_t)(struct calendar_descriptor *const calendar);
+
+/** \brief Struct for alarm time
+ */
+struct calendar_alarm {
+	struct list_element    elem;
+	struct _calendar_alarm cal_alarm;
+	calendar_cb_alarm_t    callback;
+};
+
+/** \brief Initialize the Calendar HAL instance and hardware
+ *
+ *  \param calendar Pointer to the HAL Calendar instance.
+ *  \param hw       Pointer to the hardware instance.
+ *  \return Operation status of init
+ *  \retval 0       Completed successfully.
+ */
+int32_t calendar_init(struct calendar_descriptor *const calendar, const void *hw);
+
+/** \brief Reset the Calendar HAL instance and hardware
+ *
+ *  Reset Calendar instance to hardware defaults.
+ *
+ *  \param calendar Pointer to the HAL Calendar instance.
+ *  \return Operation status of reset.
+ *  \retval 0       Completed successfully.
+ */
+int32_t calendar_deinit(struct calendar_descriptor *const calendar);
+
+/** \brief Enable the Calendar HAL instance and hardware
+ *
+ *  \param calendar Pointer to the HAL Calendar instance.
+ *  \return Operation status of init
+ *  \retval 0       Completed successfully.
+ */
+int32_t calendar_enable(struct calendar_descriptor *const calendar);
+
+/** \brief Disable the Calendar HAL instance and hardware
+ *
+ *  Disable Calendar instance to hardware defaults.
+ *
+ *  \param calendar Pointer to the HAL Calendar instance.
+ *  \return Operation status of reset.
+ *  \retval 0       Completed successfully.
+ */
+int32_t calendar_disable(struct calendar_descriptor *const calendar);
+
+/** \brief Configure the base year for calendar HAL instance and hardware
+ *
+ *  \param calendar Pointer to the HAL Calendar instance.
+ *  \param p_base_year The desired base year.
+ *  \retval 0       Completed successfully.
+ */
+int32_t calendar_set_baseyear(struct calendar_descriptor *const calendar, const uint32_t p_base_year);
+
+/** \brief Configure the time for calendar HAL instance and hardware
+ *
+ *  \param calendar Pointer to the HAL Calendar instance.
+ *  \param p_calendar_time Pointer to the time configuration.
+ *  \retval 0       Completed successfully.
+ */
+int32_t calendar_set_time(struct calendar_descriptor *const calendar, struct calendar_time *const p_calendar_time);
+
+/** \brief Configure the date for calendar HAL instance and hardware
+ *
+ *  \param calendar Pointer to the HAL Calendar instance.
+ *  \param p_calendar_date Pointer to the date configuration.
+ *  \return Operation status of time set.
+ *  \retval 0       Completed successfully.
+ */
+int32_t calendar_set_date(struct calendar_descriptor *const calendar, struct calendar_date *const p_calendar_date);
+
+/** \brief Get the time for calendar HAL instance and hardware
+ *
+ *  \param calendar Pointer to the HAL Calendar instance.
+ *  \param date_time Pointer to the value that will be filled with the current time.
+ *  \return Operation status of time retrieve.
+ *  \retval 0       Completed successfully.
+ */
+int32_t calendar_get_date_time(struct calendar_descriptor *const calendar, struct calendar_date_time *const date_time);
+
+/** \brief Config the alarm time for calendar HAL instance and hardware
+ *
+ *  Set the alarm time to calendar instance. If the callback is NULL, remove
+ *  the alarm if the alarm is already added, otherwise, ignore the alarm.
+ *
+ *  \param calendar Pointer to the HAL Calendar instance.
+ *  \param alarm Pointer to the configuration.
+ *  \param callback Pointer to the callback function.
+ *  \return Operation status of alarm time set.
+ *  \retval 0       Completed successfully.
+ */
+int32_t calendar_set_alarm(struct calendar_descriptor *const calendar, struct calendar_alarm *const alarm,
+                           calendar_cb_alarm_t callback);
+
+/** \brief Retrieve the current driver version
+ *  \return Current driver version.
+ */
+uint32_t calendar_get_version(void);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HAL_CALENDER_H_INCLUDED */
diff --git a/hal/include/hal_mci_sync.h b/hal/include/hal_mci_sync.h
new file mode 100644
index 0000000..0202335
--- /dev/null
+++ b/hal/include/hal_mci_sync.h
@@ -0,0 +1,241 @@
+/**
+ * \file
+ *
+ * \brief Multimedia Card/ Memory Card Interface related functionality declaration.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HAL_MCI_INCLUDED
+#define _HAL_MCI_INCLUDED
+
+#include <hpl_mci_sync.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_mci_sync
+ *
+ *@{
+ */
+
+/**
+ * \brief MCI descriptor structure
+ */
+struct mci_sync_desc {
+	struct _mci_sync_device device;
+};
+
+/**
+ *  \brief Initialize MCI low level driver.
+ *
+ *  \return Operation status.
+ *  \retval 0 Success.
+ *  \retval <0 Error code.
+ */
+int32_t mci_sync_init(struct mci_sync_desc *mci, void *hw);
+
+/**
+ *  \brief Deinitialize MCI low level driver.
+ *
+ *  \return Operation status.
+ *  \retval 0 Success.
+ *  \retval <0 Error code.
+ */
+int32_t mci_sync_deinit(struct mci_sync_desc *mci);
+
+/**
+ *  \brief Select a device and initialize it
+ *
+ *  \param[in] slot    Selected slot
+ *  \param[in] clock   Maximum clock to use (Hz)
+ *  \param[in] bus_width  Bus width to use (1, 4, or 8)
+ *  \param[in] high_speed True, to enable high speed mode
+ *  \return Operation status.
+ *  \retval 0 Success.
+ *  \retval <0 Error code.
+ */
+int32_t mci_sync_select_device(struct mci_sync_desc *mci, uint8_t slot, uint32_t clock, uint8_t bus_width,
+                               bool high_speed);
+
+/**
+ *  \brief Deselect a device by an assigned slot
+ *
+ *  \param[in] slot    Selected slot
+ *  \return Operation status.
+ *  \retval 0 Success.
+ *  \retval <0 Error code.
+ */
+int32_t mci_sync_deselect_device(struct mci_sync_desc *mci, uint8_t slot);
+
+/**
+ *  \brief Get the maximum bus width of a device
+ *         by a selected slot
+ *
+ *  \param[in] slot    Selected slot
+ *  \return Bus width.
+ */
+uint8_t mci_sync_get_bus_width(struct mci_sync_desc *mci, uint8_t slot);
+
+/**
+ *  \brief Get the high-speed capability of the device.
+ *
+ *  \return True, if the high-speed is supported.
+ */
+bool mci_sync_is_high_speed_capable(struct mci_sync_desc *mci);
+
+/**
+ *  \brief Send 74 clock cycles on the line.
+ *   Note: It is required after card plug and before card install.
+ */
+void mci_sync_send_clock(struct mci_sync_desc *mci);
+
+/**
+ *  \brief Send a command on the selected slot
+ *
+ *  \param[in] cmd    Command definition
+ *  \param[in] arg    Argument of the command
+ *  \return True if success, otherwise false
+ */
+bool mci_sync_send_cmd(struct mci_sync_desc *mci, uint32_t cmd, uint32_t arg);
+
+/**
+ *  \brief Get 32-bits response of the last command.
+ *
+ *  \return 32-bits response.
+ */
+uint32_t mci_sync_get_response(struct mci_sync_desc *mci);
+
+/**
+ *  \brief Get 128-bits response of the last command.
+ *
+ *  \param[in] response   Pointer on the array to fill
+ *                        with the 128-bits response.
+ */
+void mci_sync_get_response_128(struct mci_sync_desc *mci, uint8_t *response);
+
+/**
+ *  \brief Send an ADTC command on the selected slot.
+ *         An ADTC (Addressed Data Transfer Commands)
+ *         command is used for read/write access.
+ *
+ *  \param[in] cmd          Command definition.
+ *  \param[in] arg          Argument of the command.
+ *  \param[in] block_size   Block size used for the transfer.
+ *  \param[in] nb_block     Total number of blocks for this transfer
+ *  \param[in] access_block If true, the x_read_blocks() and x_write_blocks()
+ *                          functions must be used after this function.
+ *                          If false, the mci_read_word() and mci_write_word()
+ *                          functions must be used after this function.
+ *
+ * \return True if success, otherwise false
+ */
+bool mci_sync_adtc_start(struct mci_sync_desc *mci, uint32_t cmd, uint32_t arg, uint16_t block_size, uint16_t nb_block,
+                         bool access_block);
+
+/**
+ *  \brief Send a command to stop an ADTC command on the selected slot.
+ *
+ * \param[in] cmd    Command definition
+ * \param[in] arg    Argument of the command
+ *
+ * \return True if success, otherwise false
+ */
+bool mci_sync_adtc_stop(struct mci_sync_desc *mci, uint32_t cmd, uint32_t arg);
+
+/**
+ *  \brief Read a word on the line.
+ *
+ *  \param[in] value  Pointer on a word to fill.
+ *
+ *  \return True if success, otherwise false
+ */
+bool mci_sync_read_word(struct mci_sync_desc *mci, uint32_t *value);
+
+/**
+ *  \brief Write a word on the line
+ *
+ *  \param[in] value  Word to send
+ *
+ *  \return True if success, otherwise false
+ */
+bool mci_sync_write_word(struct mci_sync_desc *mci, uint32_t value);
+
+/**
+ *  \brief Start a read blocks transfer on the line
+ *
+ *  Note: The driver will use the DMA available to speed up the transfer.
+ *
+ *  \param[in] dst        Pointer on the buffer to fill
+ *  \param[in] nb_block   Number of block to transfer
+ *
+ *  \return True if started, otherwise false
+ */
+bool mci_sync_start_read_blocks(struct mci_sync_desc *mci, void *dst, uint16_t nb_block);
+
+/**
+ *  \brief Start a write blocks transfer on the line
+ *
+ *  Note: The driver will use the DMA available to speed up the transfer.
+ *
+ *  \param[in] src        Pointer on the buffer to send
+ *  \param[in] nb_block   Number of block to transfer
+ *
+ *  \return True if started, otherwise false
+ */
+bool mci_sync_start_write_blocks(struct mci_sync_desc *mci, const void *src, uint16_t nb_block);
+
+/**
+ *  \brief Wait for the end of transfer to be initiated by the mci_start_read_blocks()
+ *
+ *  \return True if success, otherwise false
+ */
+bool mci_sync_wait_end_of_read_blocks(struct mci_sync_desc *mci);
+
+/**
+ *  \brief Wait for the end of transfer to be initiated by the mci_start_write_blocks()
+ *
+ *  \return True if success, otherwise false
+ */
+bool mci_sync_wait_end_of_write_blocks(struct mci_sync_desc *mci);
+
+/**
+ *  \brief Retrieve the current driver version
+ *  \return Current driver version.
+ */
+uint32_t mci_sync_get_version(void);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HAL_MCI_INCLUDED */
diff --git a/hal/include/hpl_calendar.h b/hal/include/hpl_calendar.h
new file mode 100644
index 0000000..16601d3
--- /dev/null
+++ b/hal/include/hpl_calendar.h
@@ -0,0 +1,318 @@
+/**
+ * \file
+ *
+ * \brief Generic CALENDAR functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+#ifndef _HPL_CALENDER_H_INCLUDED
+#define _HPL_CALENDER_H_INCLUDED
+
+#include <compiler.h>
+#include <utils_list.h>
+#include "hpl_irq.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Calendar structure
+ *
+ * The Calendar structure forward declaration.
+ */
+struct calendar_dev;
+
+/**
+ * \brief Available mask options for alarms.
+ *
+ * Available mask options for alarms.
+ */
+enum calendar_alarm_option {
+	/** Alarm disabled. */
+	CALENDAR_ALARM_MATCH_DISABLED = 0,
+	/** Alarm match on second. */
+	CALENDAR_ALARM_MATCH_SEC,
+	/** Alarm match on second and minute. */
+	CALENDAR_ALARM_MATCH_MIN,
+	/** Alarm match on second, minute, and hour. */
+	CALENDAR_ALARM_MATCH_HOUR,
+	/** Alarm match on second, minute, hour, and day. */
+	CALENDAR_ALARM_MATCH_DAY,
+	/** Alarm match on second, minute, hour, day, and month. */
+	CALENDAR_ALARM_MATCH_MONTH,
+	/** Alarm match on second, minute, hour, day, month and year. */
+	CALENDAR_ALARM_MATCH_YEAR
+};
+
+/**
+ * \brief Available mode for alarms.
+ */
+enum calendar_alarm_mode { ONESHOT = 1, REPEAT };
+/**
+ * \brief Prototype of callback on alarm match
+ */
+typedef void (*calendar_drv_cb_alarm_t)(struct calendar_dev *const dev);
+
+/**
+ * \brief Prototype of callback on tamper detect
+ */
+typedef void (*tamper_drv_cb_t)(struct calendar_dev *const dev);
+
+/**
+ * \brief Structure of Calendar instance
+ */
+struct calendar_dev {
+	/** Pointer to the hardware base */
+	void *hw;
+	/** Alarm match callback */
+	calendar_drv_cb_alarm_t callback;
+	/** Tamper callback */
+	tamper_drv_cb_t callback_tamper;
+	/** IRQ struct */
+	struct _irq_descriptor irq;
+};
+/**
+ * \brief Time struct for calendar
+ */
+struct calendar_time {
+	/*range from 0 to 59*/
+	uint8_t sec;
+	/*range from 0 to 59*/
+	uint8_t min;
+	/*range from 0 to 23*/
+	uint8_t hour;
+};
+
+/**
+ * \brief Time struct for calendar
+ */
+struct calendar_date {
+	/*range from 1 to 28/29/30/31*/
+	uint8_t day;
+	/*range from 1 to 12*/
+	uint8_t month;
+	/*absolute year>= 1970(such as 2000)*/
+	uint16_t year;
+};
+
+/** \brief Calendar driver struct
+ *
+ */
+struct calendar_descriptor {
+	struct calendar_dev    device;
+	struct list_descriptor alarms;
+	/*base date/time = base_year/1/1/0/0/0(year/month/day/hour/min/sec)*/
+	uint32_t base_year;
+	uint8_t  flags;
+};
+
+/** \brief Date&Time struct for calendar
+ */
+struct calendar_date_time {
+	struct calendar_time time;
+	struct calendar_date date;
+};
+
+/** \brief struct for alarm time
+ */
+struct _calendar_alarm {
+	struct calendar_date_time  datetime;
+	uint32_t                   timestamp;
+	enum calendar_alarm_option option;
+	enum calendar_alarm_mode   mode;
+};
+
+/** \enum for tamper detection mode
+ */
+enum tamper_detection_mode { TAMPER_MODE_OFF = 0U, TAMPER_MODE_WAKE, TAMPER_MODE_CAPTURE, TAMPER_MODE_ACTL };
+
+/** \enum for tamper detection mode
+ */
+enum tamper_id { TAMPID0 = 0U, TAMPID1, TAMPID2, TAMPID3, TAMPID4 };
+/**
+ * \brief Initialize Calendar instance
+ *
+ * \param[in] dev The pointer to calendar device struct
+ *
+ * \return ERR_NONE on success, or an error code on failure.
+ */
+int32_t _calendar_init(struct calendar_dev *const dev);
+
+/**
+ * \brief Deinitialize Calendar instance
+ *
+ * \param[in] dev The pointer to calendar device struct
+ *
+ * \return ERR_NONE on success, or an error code on failure.
+ */
+int32_t _calendar_deinit(struct calendar_dev *const dev);
+
+/**
+ * \brief Enable Calendar instance
+ *
+ * \param[in] dev The pointer to calendar device struct
+ *
+ * \return ERR_NONE on success, or an error code on failure.
+ */
+int32_t _calendar_enable(struct calendar_dev *const dev);
+
+/**
+ * \brief Disable Calendar instance
+ *
+ * \param[in] dev The pointer to calendar device struct
+ *
+ * \return ERR_NONE on success, or an error code on failure.
+ */
+int32_t _calendar_disable(struct calendar_dev *const dev);
+/**
+ * \brief Set counter for calendar
+ *
+ * \param[in] dev The pointer to calendar device struct
+ * \param[in] counter The counter for set
+ *
+ * \return ERR_NONE on success, or an error code on failure.
+ */
+int32_t _calendar_set_counter(struct calendar_dev *const dev, const uint32_t counter);
+
+/**
+ * \brief Get counter for calendar
+ *
+ * \param[in] dev The pointer to calendar device struct
+ *
+ * \return return current counter value
+ */
+uint32_t _calendar_get_counter(struct calendar_dev *const dev);
+
+/**
+ * \brief Set compare value for calendar
+ *
+ * \param[in] dev The pointer to calendar device struct
+ * \param[in] comp The compare value for set
+ *
+ * \return ERR_NONE on success, or an error code on failure.
+ */
+int32_t _calendar_set_comp(struct calendar_dev *const dev, const uint32_t comp);
+
+/**
+ * \brief Get compare value for calendar
+ *
+ * \param[in] dev The pointer to calendar device struct
+ *
+ * \return return current compare value
+ */
+uint32_t _calendar_get_comp(struct calendar_dev *const dev);
+
+/**
+ * \brief Register callback for calendar alarm
+ *
+ * \param[in] dev The pointer to calendar device struct
+ * \param[in] callback The pointer to callback function
+ *
+ * \return ERR_NONE on success, or an error code on failure.
+ */
+int32_t _calendar_register_callback(struct calendar_dev *const dev, calendar_drv_cb_alarm_t callback);
+
+/**
+ * \brief Set calendar IRQ
+ *
+ * \param[in] dev The pointer to calendar device struct
+ */
+void _calendar_set_irq(struct calendar_dev *const dev);
+
+/**
+ * \brief Register callback for tamper detection
+ *
+ * \param[in] dev The pointer to calendar device struct
+ * \param[in] callback The pointer to callback function
+ *
+ * \return ERR_NONE on success, or an error code on failure.
+ */
+int32_t _tamper_register_callback(struct calendar_dev *const dev, tamper_drv_cb_t callback_tamper);
+
+/**
+ * \brief Find tamper is detected on specified pin
+ *
+ * \param[in] dev The pointer to calendar device struct
+ * \param[in] enum Tamper ID number
+ *
+ * \return true on detection success and false on failure.
+ */
+bool _is_tamper_detected(struct calendar_dev *const dev, enum tamper_id tamper_id_pin);
+
+/**
+ * \brief brief Clear the Tamper ID flag
+ *
+ * \param[in] dev The pointer to calendar device struct
+ * \param[in] enum Tamper ID number
+ *
+ * \return ERR_NONE
+ */
+int32_t _tamper_clear_tampid_flag(struct calendar_dev *const dev, enum tamper_id tamper_id_pin);
+
+/**
+ * \brief Enable Debounce Asynchronous Feature
+ *
+ * \param[in] dev The pointer to calendar device struct
+ *
+ * \return ERR_NONE on success, or an error code on failure.
+ */
+int32_t _tamper_enable_debounce_asynchronous(struct calendar_dev *const dev);
+
+/**
+ * \brief Disable Tamper Debounce Asynchronous Feature
+ *
+ * \param[in] dev The pointer to calendar device struct
+ *
+ * \return ERR_NONE on success, or an error code on failure.
+ */
+int32_t _tamper_disable_debounce_asynchronous(struct calendar_dev *const dev);
+
+/**
+ * \brief Enable Tamper Debounce Majority Feature
+ *
+ * \param[in] dev The pointer to calendar device struct
+ *
+ * \return ERR_NONE on success, or an error code on failure.
+ */
+int32_t _tamper_enable_debounce_majority(struct calendar_dev *const dev);
+
+/**
+ * \brief Enable Tamper Debounce Majority Feature
+ *
+ * \param[in] dev The pointer to calendar device struct
+ *
+ * \return ERR_NONE on success, or an error code on failure.
+ */
+int32_t _tamper_disable_debounce_majority(struct calendar_dev *const dev);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HPL_RTC_H_INCLUDED */
diff --git a/hal/include/hpl_mci_sync.h b/hal/include/hpl_mci_sync.h
new file mode 100644
index 0000000..339d7ac
--- /dev/null
+++ b/hal/include/hpl_mci_sync.h
@@ -0,0 +1,255 @@
+/**
+ * \file
+ *
+ * \brief SAM MCI HPL
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_MCI_H_INCLUDED
+#define _HPL_MCI_H_INCLUDED
+
+#include <compiler.h>
+#include <utils.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//! \name Flags used to define MCI parser for SD/MMC command
+//! @{
+//! Have response
+#define MCI_RESP_PRESENT (1lu << 8)
+//! 136 bit response
+#define MCI_RESP_136 (1lu << 11)
+//! Expect valid crc
+#define MCI_RESP_CRC (1lu << 12)
+//! Card may send busy
+#define MCI_RESP_BUSY (1lu << 13)
+//! Open drain for a braodcast command
+#define MCI_CMD_OPENDRAIN (1lu << 14)
+//! To signal a data write operation
+#define MCI_CMD_WRITE (1lu << 15)
+//! To signal a SDIO tranfer in multi byte mode
+#define MCI_CMD_SDIO_BYTE (1lu << 16)
+//! To signal a SDIO tranfer in block mode
+#define MCI_CMD_SDIO_BLOCK (1lu << 17)
+//! To signal a data transfer in stream mode
+#define MCI_CMD_STREAM (1lu << 18)
+//! To signal a data transfer in single block mode
+#define MCI_CMD_SINGLE_BLOCK (1lu << 19)
+//! To signal a data transfer in multi block mode
+#define MCI_CMD_MULTI_BLOCK (1lu << 20)
+//! @}
+
+/**
+ * \brief mci sync device structure
+ */
+struct _mci_sync_device {
+	void *   hw;
+	uint64_t mci_sync_trans_pos;
+	uint16_t mci_sync_block_size;
+	uint16_t mci_sync_nb_block;
+};
+
+/**
+ *  \brief Initialize MCI low level driver.
+ *
+ *  \return Operation status.
+ *  \retval 0 Success.
+ *  \retval <0 Error code.
+ */
+int32_t _mci_sync_init(struct _mci_sync_device *const mci_dev, void *const hw);
+
+/**
+ *  \brief Deinitialize MCI low level driver.
+ *
+ *  \return Operation status.
+ *  \retval 0 Success.
+ *  \retval <0 Error code.
+ */
+int32_t _mci_sync_deinit(struct _mci_sync_device *const mci_dev);
+
+/**
+ *  \brief Select a device and initialize it
+ *
+ *  \param[in] slot    Selected slot
+ *  \param[in] clock   Maximum clock to use (Hz)
+ *  \param[in] bus_width  Bus width to use (1, 4 or 8)
+ *  \param[in] high_speed true, to enable high speed mode
+ *  \return Operation status.
+ *  \retval 0 Success.
+ *  \retval <0 Error code.
+ */
+int32_t _mci_sync_select_device(struct _mci_sync_device *const mci_dev, uint8_t slot, uint32_t clock, uint8_t bus_width,
+                                bool high_speed);
+
+/**
+ *  \brief Deselect a device by an assigned slot
+ *
+ *  \param[in] slot    Selected slot
+ *  \return Operation status.
+ *  \retval 0 Success.
+ *  \retval <0 Error code.
+ */
+int32_t _mci_sync_deselect_device(struct _mci_sync_device *const mci_dev, uint8_t slot);
+
+/**
+ *  \brief Get the maximum bus width of a device
+ *         by a selected slot
+ *
+ *  \param[in] slot    Selected slot
+ *  \return bus width.
+ */
+uint8_t _mci_sync_get_bus_width(struct _mci_sync_device *const mci_dev, uint8_t slot);
+
+/**
+ *  \brief Get the high speed capability of the device.
+ *
+ *  \return true, if the high speed is supported.
+ */
+bool _mci_sync_is_high_speed_capable(struct _mci_sync_device *const mci_dev);
+
+/**
+ *  \brief Send 74 clock cycles on the line.
+ *   Note: It is required after card plug and before card install.
+ */
+void _mci_sync_send_clock(struct _mci_sync_device *const mci_dev);
+
+/**
+ *  \brief Send a command on the selected slot
+ *
+ *  \param[in] cmd        Command definition
+ *  \param[in] arg        Argument of the command
+ *  \return true if success, otherwise false
+ */
+bool _mci_sync_send_cmd(struct _mci_sync_device *const mci_dev, uint32_t cmd, uint32_t arg);
+
+/**
+ *  \brief Get 32 bits response of the last command.
+ *
+ *  \return 32 bits response.
+ */
+uint32_t _mci_sync_get_response(struct _mci_sync_device *const mci_dev);
+
+/**
+ *  \brief Get 128 bits response of the last command.
+ *
+ *  \param[in] response   Pointer on the array to fill
+ *                        with the 128 bits response.
+ */
+void _mci_sync_get_response_128(struct _mci_sync_device *const mci_dev, uint8_t *response);
+
+/**
+ *  \brief Send an ADTC command on the selected slot
+ *         An ADTC (Addressed Data Transfer Commands)
+ *         command is used for read/write access..
+ *
+ *  \param[in] cmd          Command definition.
+ *  \param[in] arg          Argument of the command.
+ *  \param[in] block_size   Block size used for the transfer.
+ *  \param[in] nb_block     Total number of block for this transfer
+ *  \param[in] access_block if true, the x_read_blocks() and x_write_blocks()
+ *                          functions must be used after this function.
+ *                          If false, the mci_read_word() and mci_write_word()
+ *                          functions must be used after this function.
+ *
+ * \return true if success, otherwise false
+ */
+bool _mci_sync_adtc_start(struct _mci_sync_device *const mci_dev, uint32_t cmd, uint32_t arg, uint16_t block_size,
+                          uint16_t nb_block, bool access_block);
+
+/**
+ *  \brief Send a command to stop an ADTC command on the selected slot.
+ *
+ * \param[in] cmd        Command definition
+ * \param[in] arg        Argument of the command
+ *
+ * \return true if success, otherwise false
+ */
+bool _mci_sync_adtc_stop(struct _mci_sync_device *const mci_dev, uint32_t cmd, uint32_t arg);
+
+/**
+ *  \brief Read a word on the line.
+ *
+ *  \param[in] value  Pointer on a word to fill.
+ *
+ *  \return true if success, otherwise false
+ */
+bool _mci_sync_read_word(struct _mci_sync_device *const mci_dev, uint32_t *value);
+
+/**
+ *  \brief Write a word on the line
+ *
+ *  \param[in] value  Word to send
+ *
+ *  \return true if success, otherwise false
+ */
+bool _mci_sync_write_word(struct _mci_sync_device *const mci_dev, uint32_t value);
+
+/**
+ *  \brief Start a read blocks transfer on the line
+ *  Note: The driver will use the DMA available to speed up the transfer.
+ *
+ *  \param[in] dst        Pointer on the buffer to fill
+ *  \param[in] nb_block   Number of block to transfer
+ *
+ *  \return true if started, otherwise false
+ */
+bool _mci_sync_start_read_blocks(struct _mci_sync_device *const mci_dev, void *dst, uint16_t nb_block);
+
+/**
+ *  \brief Start a write blocks transfer on the line
+ *  Note: The driver will use the DMA available to speed up the transfer.
+ *
+ *  \param[in] src        Pointer on the buffer to send
+ *  \param[in] nb_block   Number of block to transfer
+ *
+ *  \return true if started, otherwise false
+ */
+bool _mci_sync_start_write_blocks(struct _mci_sync_device *const mci_dev, const void *src, uint16_t nb_block);
+
+/**
+ *  \brief Wait the end of transfer initiated by mci_start_read_blocks()
+ *
+ *  \return true if success, otherwise false
+ */
+bool _mci_sync_wait_end_of_read_blocks(struct _mci_sync_device *const mci_dev);
+
+/**
+ *  \brief Wait the end of transfer initiated by mci_start_write_blocks()
+ *
+ *  \return true if success, otherwise false
+ */
+bool _mci_sync_wait_end_of_write_blocks(struct _mci_sync_device *const mci_dev);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HPL_MCI_H_INCLUDED */
diff --git a/hal/include/hpl_timer.h b/hal/include/hpl_timer.h
new file mode 100644
index 0000000..9bdfbb7
--- /dev/null
+++ b/hal/include/hpl_timer.h
@@ -0,0 +1,160 @@
+/**
+ * \file
+ *
+ * \brief Timer related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_TIMER_H_INCLUDED
+#define _HPL_TIMER_H_INCLUDED
+
+/**
+ * \addtogroup HPL Timer
+ *
+ * \section hpl_timer_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include <compiler.h>
+#include <hpl_irq.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Timer device structure
+ *
+ * The Timer device structure forward declaration.
+ */
+struct _timer_device;
+
+/**
+ * \brief Timer interrupt callbacks
+ */
+struct _timer_callbacks {
+	void (*period_expired)(struct _timer_device *device);
+};
+
+/**
+ * \brief Timer device structure
+ */
+struct _timer_device {
+	struct _timer_callbacks timer_cb;
+	struct _irq_descriptor  irq;
+	void *                  hw;
+};
+
+/**
+ * \brief Timer functions, pointers to low-level functions
+ */
+struct _timer_hpl_interface {
+	int32_t (*init)(struct _timer_device *const device, void *const hw);
+	void (*deinit)(struct _timer_device *const device);
+	void (*start_timer)(struct _timer_device *const device);
+	void (*stop_timer)(struct _timer_device *const device);
+	void (*set_timer_period)(struct _timer_device *const device, const uint32_t clock_cycles);
+	uint32_t (*get_period)(const struct _timer_device *const device);
+	bool (*is_timer_started)(const struct _timer_device *const device);
+	void (*set_timer_irq)(struct _timer_device *const device);
+};
+/**
+ * \brief Initialize TCC
+ *
+ * This function does low level TCC configuration.
+ *
+ * \param[in] device The pointer to timer device instance
+ * \param[in] hw The pointer to hardware instance
+ *
+ * \return Initialization status.
+ */
+int32_t _timer_init(struct _timer_device *const device, void *const hw);
+
+/**
+ * \brief Deinitialize TCC
+ *
+ * \param[in] device The pointer to timer device instance
+ */
+void _timer_deinit(struct _timer_device *const device);
+
+/**
+ * \brief Start hardware timer
+ *
+ * \param[in] device The pointer to timer device instance
+ */
+void _timer_start(struct _timer_device *const device);
+
+/**
+ * \brief Stop hardware timer
+ *
+ * \param[in] device The pointer to timer device instance
+ */
+void _timer_stop(struct _timer_device *const device);
+
+/**
+ * \brief Set timer period
+ *
+ * \param[in] device The pointer to timer device instance
+ */
+void _timer_set_period(struct _timer_device *const device, const uint32_t clock_cycles);
+
+/**
+ * \brief Retrieve timer period
+ *
+ * \param[in] device The pointer to timer device instance
+ *
+ * \return Timer period
+ */
+uint32_t _timer_get_period(const struct _timer_device *const device);
+
+/**
+ * \brief Check if timer is running
+ *
+ * \param[in] device The pointer to timer device instance
+ *
+ * \return Check status.
+ * \retval true The given timer is running
+ * \retval false The given timer is not running
+ */
+bool _timer_is_started(const struct _timer_device *const device);
+
+/**
+ * \brief Set timer IRQ
+ *
+ * \param[in] device The pointer to timer device instance
+ */
+void _timer_set_irq(struct _timer_device *const device);
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_TIMER_H_INCLUDED */
diff --git a/hal/src/hal_calendar.c b/hal/src/hal_calendar.c
new file mode 100644
index 0000000..842cfb8
--- /dev/null
+++ b/hal/src/hal_calendar.c
@@ -0,0 +1,643 @@
+/**
+ * \file
+ *
+ * \brief Generic CALENDAR functionality implementation.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "hal_calendar.h"
+#include <utils.h>
+#include <utils_assert.h>
+#include <hal_atomic.h>
+
+#define CALENDAR_VERSION 0x00000001u
+#define SECS_IN_LEAP_YEAR 31622400
+#define SECS_IN_NON_LEAP_YEAR 31536000
+#define SECS_IN_31DAYS 2678400
+#define SECS_IN_30DAYS 2592000
+#define SECS_IN_29DAYS 2505600
+#define SECS_IN_28DAYS 2419200
+#define SECS_IN_DAY 86400
+#define SECS_IN_HOUR 3600
+#define SECS_IN_MINUTE 60
+#define DEFAULT_BASE_YEAR 1970
+
+#define SET_ALARM_BUSY 1
+#define PROCESS_ALARM_BUSY 2
+
+/** \brief leap year check
+ *  \retval false  not leap year.
+ *  \retval true  leap year.
+ */
+static bool leap_year(uint16_t year)
+{
+	if (year & 3) {
+		return false;
+	} else {
+		return true;
+	}
+}
+
+/** \brief calculate the seconds in specified year/month
+ *  \retval 0  month error.
+ */
+static uint32_t get_secs_in_month(uint32_t year, uint8_t month)
+{
+	uint32_t sec_in_month = 0;
+
+	if (leap_year(year)) {
+		switch (month) {
+		case 1:
+		case 3:
+		case 5:
+		case 7:
+		case 8:
+		case 10:
+		case 12:
+			sec_in_month = SECS_IN_31DAYS;
+			break;
+		case 2:
+			sec_in_month = SECS_IN_29DAYS;
+			break;
+		case 4:
+		case 6:
+		case 9:
+		case 11:
+			sec_in_month = SECS_IN_30DAYS;
+			break;
+		default:
+			break;
+		}
+	} else {
+		switch (month) {
+		case 1:
+		case 3:
+		case 5:
+		case 7:
+		case 8:
+		case 10:
+		case 12:
+			sec_in_month = SECS_IN_31DAYS;
+			break;
+		case 2:
+			sec_in_month = SECS_IN_28DAYS;
+			break;
+		case 4:
+		case 6:
+		case 9:
+		case 11:
+			sec_in_month = SECS_IN_30DAYS;
+			break;
+		default:
+			break;
+		}
+	}
+
+	return sec_in_month;
+}
+
+/** \brief convert timestamp to date/time
+ */
+static int32_t convert_timestamp_to_datetime(struct calendar_descriptor *const calendar, uint32_t ts,
+                                             struct calendar_date_time *dt)
+{
+	uint32_t tmp, sec_in_year, sec_in_month;
+	uint32_t tmp_year    = calendar->base_year;
+	uint8_t  tmp_month   = 1;
+	uint8_t  tmp_day     = 1;
+	uint8_t  tmp_hour    = 0;
+	uint8_t  tmp_minutes = 0;
+
+	tmp = ts;
+
+	/* Find year */
+	while (true) {
+		sec_in_year = leap_year(tmp_year) ? SECS_IN_LEAP_YEAR : SECS_IN_NON_LEAP_YEAR;
+
+		if (tmp >= sec_in_year) {
+			tmp -= sec_in_year;
+			tmp_year++;
+		} else {
+			break;
+		}
+	}
+	/* Find month of year */
+	while (true) {
+		sec_in_month = get_secs_in_month(tmp_year, tmp_month);
+
+		if (tmp >= sec_in_month) {
+			tmp -= sec_in_month;
+			tmp_month++;
+		} else {
+			break;
+		}
+	}
+	/* Find day of month */
+	while (true) {
+		if (tmp >= SECS_IN_DAY) {
+			tmp -= SECS_IN_DAY;
+			tmp_day++;
+		} else {
+			break;
+		}
+	}
+	/* Find hour of day */
+	while (true) {
+		if (tmp >= SECS_IN_HOUR) {
+			tmp -= SECS_IN_HOUR;
+			tmp_hour++;
+		} else {
+			break;
+		}
+	}
+	/* Find minute in hour */
+	while (true) {
+		if (tmp >= SECS_IN_MINUTE) {
+			tmp -= SECS_IN_MINUTE;
+			tmp_minutes++;
+		} else {
+			break;
+		}
+	}
+
+	dt->date.year  = tmp_year;
+	dt->date.month = tmp_month;
+	dt->date.day   = tmp_day;
+	dt->time.hour  = tmp_hour;
+	dt->time.min   = tmp_minutes;
+	dt->time.sec   = tmp;
+
+	return ERR_NONE;
+}
+
+/** \brief convert date/time to timestamp
+ *  \return timestamp
+ */
+static uint32_t convert_datetime_to_timestamp(struct calendar_descriptor *const calendar, struct calendar_date_time *dt)
+{
+	uint32_t tmp = 0;
+	uint32_t i   = 0;
+	uint8_t  year, month, day, hour, minutes, seconds;
+
+	year    = dt->date.year - calendar->base_year;
+	month   = dt->date.month;
+	day     = dt->date.day;
+	hour    = dt->time.hour;
+	minutes = dt->time.min;
+	seconds = dt->time.sec;
+
+	/* tot up year field */
+	for (i = 0; i < year; ++i) {
+		if (leap_year(calendar->base_year + i)) {
+			tmp += SECS_IN_LEAP_YEAR;
+		} else {
+			tmp += SECS_IN_NON_LEAP_YEAR;
+		}
+	}
+
+	/* tot up month field */
+	for (i = 1; i < month; ++i) {
+		tmp += get_secs_in_month(dt->date.year, i);
+	}
+
+	/* tot up day/hour/minute/second fields */
+	tmp += (day - 1) * SECS_IN_DAY;
+	tmp += hour * SECS_IN_HOUR;
+	tmp += minutes * SECS_IN_MINUTE;
+	tmp += seconds;
+
+	return tmp;
+}
+
+/** \brief calibrate timestamp to make desired timestamp ahead of current timestamp
+ */
+static void calibrate_timestamp(struct calendar_descriptor *const calendar, struct calendar_alarm *alarm,
+                                struct calendar_alarm *current_dt)
+{
+	uint32_t alarm_ts;
+	uint32_t current_ts = current_dt->cal_alarm.timestamp;
+
+	alarm_ts = alarm->cal_alarm.timestamp;
+
+	/* calibrate timestamp */
+	switch (alarm->cal_alarm.option) {
+	case CALENDAR_ALARM_MATCH_SEC:
+
+		if (alarm_ts <= current_ts) {
+			alarm_ts += SECS_IN_MINUTE;
+		}
+
+		break;
+	case CALENDAR_ALARM_MATCH_MIN:
+
+		if (alarm_ts <= current_ts) {
+			alarm_ts += SECS_IN_HOUR;
+		}
+
+		break;
+	case CALENDAR_ALARM_MATCH_HOUR:
+
+		if (alarm_ts <= current_ts) {
+			alarm_ts += SECS_IN_DAY;
+		}
+
+		break;
+	case CALENDAR_ALARM_MATCH_DAY:
+
+		if (alarm_ts <= current_ts) {
+			alarm_ts += get_secs_in_month(current_dt->cal_alarm.datetime.date.year,
+			                              current_dt->cal_alarm.datetime.date.month);
+		}
+
+		break;
+	case CALENDAR_ALARM_MATCH_MONTH:
+
+		if (alarm_ts <= current_ts) {
+			if (leap_year(current_dt->cal_alarm.datetime.date.year)) {
+				alarm_ts += SECS_IN_LEAP_YEAR;
+			} else {
+				alarm_ts += SECS_IN_NON_LEAP_YEAR;
+			}
+		}
+
+		break;
+	/* do nothing for year match */
+	case CALENDAR_ALARM_MATCH_YEAR:
+	default:
+		break;
+	}
+
+	/* desired timestamp after calibration */
+	alarm->cal_alarm.timestamp = alarm_ts;
+}
+
+/** \brief complete alarm to absolute date/time, then fill up the timestamp
+ */
+static void fill_alarm(struct calendar_descriptor *const calendar, struct calendar_alarm *alarm)
+{
+	struct calendar_alarm current_dt;
+	uint32_t              tmp, current_ts;
+
+	/* get current date/time */
+	current_ts = _calendar_get_counter(&calendar->device);
+	convert_timestamp_to_datetime(calendar, current_ts, &current_dt.cal_alarm.datetime);
+
+	current_dt.cal_alarm.timestamp = current_ts;
+
+	/* complete alarm */
+	switch (alarm->cal_alarm.option) {
+	case CALENDAR_ALARM_MATCH_SEC:
+		alarm->cal_alarm.datetime.date.year  = current_dt.cal_alarm.datetime.date.year;
+		alarm->cal_alarm.datetime.date.month = current_dt.cal_alarm.datetime.date.month;
+		alarm->cal_alarm.datetime.date.day   = current_dt.cal_alarm.datetime.date.day;
+		alarm->cal_alarm.datetime.time.hour  = current_dt.cal_alarm.datetime.time.hour;
+		alarm->cal_alarm.datetime.time.min   = current_dt.cal_alarm.datetime.time.min;
+		break;
+	case CALENDAR_ALARM_MATCH_MIN:
+		alarm->cal_alarm.datetime.date.year  = current_dt.cal_alarm.datetime.date.year;
+		alarm->cal_alarm.datetime.date.month = current_dt.cal_alarm.datetime.date.month;
+		alarm->cal_alarm.datetime.date.day   = current_dt.cal_alarm.datetime.date.day;
+		alarm->cal_alarm.datetime.time.hour  = current_dt.cal_alarm.datetime.time.hour;
+		break;
+	case CALENDAR_ALARM_MATCH_HOUR:
+		alarm->cal_alarm.datetime.date.year  = current_dt.cal_alarm.datetime.date.year;
+		alarm->cal_alarm.datetime.date.month = current_dt.cal_alarm.datetime.date.month;
+		alarm->cal_alarm.datetime.date.day   = current_dt.cal_alarm.datetime.date.day;
+		break;
+	case CALENDAR_ALARM_MATCH_DAY:
+		alarm->cal_alarm.datetime.date.year  = current_dt.cal_alarm.datetime.date.year;
+		alarm->cal_alarm.datetime.date.month = current_dt.cal_alarm.datetime.date.month;
+		break;
+	case CALENDAR_ALARM_MATCH_MONTH:
+		alarm->cal_alarm.datetime.date.year = current_dt.cal_alarm.datetime.date.year;
+		break;
+	case CALENDAR_ALARM_MATCH_YEAR:
+		break;
+	default:
+		break;
+	}
+
+	/* fill up the timestamp */
+	tmp                        = convert_datetime_to_timestamp(calendar, &alarm->cal_alarm.datetime);
+	alarm->cal_alarm.timestamp = tmp;
+
+	/* calibrate the timestamp */
+	calibrate_timestamp(calendar, alarm, &current_dt);
+	convert_timestamp_to_datetime(calendar, alarm->cal_alarm.timestamp, &alarm->cal_alarm.datetime);
+}
+
+/** \brief add new alarm into the list in ascending order
+ */
+static int32_t calendar_add_new_alarm(struct list_descriptor *list, struct calendar_alarm *alarm)
+{
+	struct calendar_descriptor *calendar = CONTAINER_OF(list, struct calendar_descriptor, alarms);
+	struct calendar_alarm *     head, *it, *prev = NULL;
+
+	/*get the head of alarms list*/
+	head = (struct calendar_alarm *)list_get_head(list);
+
+	/*if head is null, insert new alarm as head*/
+	if (!head) {
+		list_insert_as_head(list, alarm);
+		_calendar_set_comp(&calendar->device, alarm->cal_alarm.timestamp);
+		return ERR_NONE;
+	}
+
+	/*insert the new alarm in accending order, the head will be invoked firstly */
+	for (it = head; it; it = (struct calendar_alarm *)list_get_next_element(it)) {
+		if (alarm->cal_alarm.timestamp <= it->cal_alarm.timestamp) {
+			break;
+		}
+
+		prev = it;
+	}
+
+	/*insert new alarm into the list */
+	if (it == head) {
+		list_insert_as_head(list, alarm);
+		/*get the head and set it into register*/
+		_calendar_set_comp(&calendar->device, alarm->cal_alarm.timestamp);
+
+	} else {
+		list_insert_after(prev, alarm);
+	}
+
+	return ERR_NONE;
+}
+
+/** \brief callback for alarm
+ */
+static void calendar_alarm(struct calendar_dev *const dev)
+{
+	struct calendar_descriptor *calendar = CONTAINER_OF(dev, struct calendar_descriptor, device);
+
+	struct calendar_alarm *head, *it, current_dt;
+
+	if ((calendar->flags & SET_ALARM_BUSY) || (calendar->flags & PROCESS_ALARM_BUSY)) {
+		calendar->flags |= PROCESS_ALARM_BUSY;
+		return;
+	}
+
+	/* get current timestamp */
+	current_dt.cal_alarm.timestamp = _calendar_get_counter(dev);
+
+	/* get the head */
+	head = (struct calendar_alarm *)list_get_head(&calendar->alarms);
+	ASSERT(head);
+
+	/* remove all alarms and invoke them*/
+	for (it = head; it; it = (struct calendar_alarm *)list_get_head(&calendar->alarms)) {
+		/* check the timestamp with current timestamp*/
+		if (it->cal_alarm.timestamp <= current_dt.cal_alarm.timestamp) {
+			list_remove_head(&calendar->alarms);
+			it->callback(calendar);
+
+			if (it->cal_alarm.mode == REPEAT) {
+				calibrate_timestamp(calendar, it, &current_dt);
+				convert_timestamp_to_datetime(calendar, it->cal_alarm.timestamp, &it->cal_alarm.datetime);
+				calendar_add_new_alarm(&calendar->alarms, it);
+			}
+		} else {
+			break;
+		}
+	}
+
+	/*if no alarm in the list, register null */
+	if (!it) {
+		_calendar_register_callback(&calendar->device, NULL);
+		return;
+	}
+
+	/*put the new head into register */
+	_calendar_set_comp(&calendar->device, it->cal_alarm.timestamp);
+}
+
+/** \brief Initialize Calendar
+ */
+int32_t calendar_init(struct calendar_descriptor *const calendar, const void *hw)
+{
+	int32_t ret = 0;
+
+	/* Sanity check arguments */
+	ASSERT(calendar);
+
+	if (calendar->device.hw == hw) {
+		/* Already initialized with current configuration */
+		return ERR_NONE;
+	} else if (calendar->device.hw != NULL) {
+		/* Initialized with another configuration */
+		return ERR_ALREADY_INITIALIZED;
+	}
+	calendar->device.hw = (void *)hw;
+	ret                 = _calendar_init(&calendar->device);
+	calendar->base_year = DEFAULT_BASE_YEAR;
+
+	return ret;
+}
+
+/** \brief Reset the Calendar
+ */
+int32_t calendar_deinit(struct calendar_descriptor *const calendar)
+{
+	/* Sanity check arguments */
+	ASSERT(calendar);
+
+	if (calendar->device.hw == NULL) {
+		return ERR_NOT_INITIALIZED;
+	}
+	_calendar_deinit(&calendar->device);
+	calendar->device.hw = NULL;
+
+	return ERR_NONE;
+}
+
+/** \brief Enable the Calendar
+ */
+int32_t calendar_enable(struct calendar_descriptor *const calendar)
+{
+	/* Sanity check arguments */
+	ASSERT(calendar);
+
+	_calendar_enable(&calendar->device);
+
+	return ERR_NONE;
+}
+
+/** \brief Disable the Calendar
+ */
+int32_t calendar_disable(struct calendar_descriptor *const calendar)
+{
+	/* Sanity check arguments */
+	ASSERT(calendar);
+
+	_calendar_disable(&calendar->device);
+
+	return ERR_NONE;
+}
+
+/** \brief Set base year for calendar
+ */
+int32_t calendar_set_baseyear(struct calendar_descriptor *const calendar, const uint32_t p_base_year)
+{
+	/* Sanity check arguments */
+	ASSERT(calendar);
+
+	calendar->base_year = p_base_year;
+
+	return ERR_NONE;
+}
+
+/** \brief Set time for calendar
+ */
+int32_t calendar_set_time(struct calendar_descriptor *const calendar, struct calendar_time *const p_calendar_time)
+{
+	struct calendar_date_time dt;
+	uint32_t                  current_ts, new_ts;
+
+	/* Sanity check arguments */
+	ASSERT(calendar);
+
+	/* convert time to timestamp */
+	current_ts = _calendar_get_counter(&calendar->device);
+	convert_timestamp_to_datetime(calendar, current_ts, &dt);
+	dt.time.sec  = p_calendar_time->sec;
+	dt.time.min  = p_calendar_time->min;
+	dt.time.hour = p_calendar_time->hour;
+
+	new_ts = convert_datetime_to_timestamp(calendar, &dt);
+
+	_calendar_set_counter(&calendar->device, new_ts);
+
+	return ERR_NONE;
+}
+
+/** \brief Set date for calendar
+ */
+int32_t calendar_set_date(struct calendar_descriptor *const calendar, struct calendar_date *const p_calendar_date)
+{
+	struct calendar_date_time dt;
+	uint32_t                  current_ts, new_ts;
+
+	/* Sanity check arguments */
+	ASSERT(calendar);
+
+	/* convert date to timestamp */
+	current_ts = _calendar_get_counter(&calendar->device);
+	convert_timestamp_to_datetime(calendar, current_ts, &dt);
+	dt.date.day   = p_calendar_date->day;
+	dt.date.month = p_calendar_date->month;
+	dt.date.year  = p_calendar_date->year;
+
+	new_ts = convert_datetime_to_timestamp(calendar, &dt);
+
+	_calendar_set_counter(&calendar->device, new_ts);
+
+	return ERR_NONE;
+}
+
+/** \brief Get date/time for calendar
+ */
+int32_t calendar_get_date_time(struct calendar_descriptor *const calendar, struct calendar_date_time *const date_time)
+{
+	uint32_t current_ts;
+
+	/* Sanity check arguments */
+	ASSERT(calendar);
+
+	/* convert current timestamp to date/time */
+	current_ts = _calendar_get_counter(&calendar->device);
+	convert_timestamp_to_datetime(calendar, current_ts, date_time);
+
+	return ERR_NONE;
+}
+
+/** \brief Set alarm for calendar
+ */
+int32_t calendar_set_alarm(struct calendar_descriptor *const calendar, struct calendar_alarm *const alarm,
+                           calendar_cb_alarm_t callback)
+{
+	struct calendar_alarm *head;
+
+	/* Sanity check arguments */
+	ASSERT(calendar);
+	ASSERT(alarm);
+
+	alarm->callback = callback;
+
+	fill_alarm(calendar, alarm);
+
+	calendar->flags |= SET_ALARM_BUSY;
+
+	head = (struct calendar_alarm *)list_get_head(&calendar->alarms);
+
+	if (head != NULL) {
+		/* already added */
+		if (is_list_element(&calendar->alarms, alarm)) {
+			if (callback == NULL) {
+				/* remove alarm */
+				list_delete_element(&calendar->alarms, alarm);
+
+				if (!list_get_head(&calendar->alarms)) {
+					_calendar_register_callback(&calendar->device, NULL);
+				}
+			} else {
+				/* re-add */
+				list_delete_element(&calendar->alarms, alarm);
+				calendar_add_new_alarm(&calendar->alarms, alarm);
+			}
+		} else if (callback != NULL) {
+			calendar_add_new_alarm(&calendar->alarms, alarm);
+		}
+
+		calendar->flags &= ~SET_ALARM_BUSY;
+
+		if (calendar->flags & PROCESS_ALARM_BUSY) {
+			CRITICAL_SECTION_ENTER()
+			calendar->flags &= ~PROCESS_ALARM_BUSY;
+			_calendar_set_irq(&calendar->device);
+			CRITICAL_SECTION_LEAVE()
+		}
+	} else if (callback != NULL) {
+		/* if head is NULL, Register callback*/
+		_calendar_register_callback(&calendar->device, calendar_alarm);
+		calendar_add_new_alarm(&calendar->alarms, alarm);
+	}
+
+	calendar->flags &= ~SET_ALARM_BUSY;
+
+	return ERR_NONE;
+}
+
+/** \brief Retrieve driver version
+ *  \return Current driver version
+ */
+uint32_t calendar_get_version(void)
+{
+	return CALENDAR_VERSION;
+}
diff --git a/hal/src/hal_mci_sync.c b/hal/src/hal_mci_sync.c
new file mode 100644
index 0000000..d3322fc
--- /dev/null
+++ b/hal/src/hal_mci_sync.c
@@ -0,0 +1,223 @@
+/**
+ * \file
+ *
+ * \brief Multimedia Card/ Memory Card Interface HAL.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "hal_mci_sync.h"
+#include <utils_assert.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** MCI HAL driver version. */
+#define DRIVER_VERSION 0x00000001u
+
+/**
+ *  \brief Initialize MCI low level driver.
+ */
+int32_t mci_sync_init(struct mci_sync_desc *mci, void *hw)
+{
+	ASSERT(mci && hw);
+	return _mci_sync_init(&mci->device, hw);
+}
+
+/**
+ *  \brief Deinitialize MCI low level driver.
+ */
+int32_t mci_sync_deinit(struct mci_sync_desc *mci)
+{
+	ASSERT(mci);
+	return _mci_sync_deinit(&mci->device);
+}
+
+/**
+ *  \brief Select a device and initialize it
+ */
+int32_t mci_sync_select_device(struct mci_sync_desc *mci, uint8_t slot, uint32_t clock, uint8_t bus_width,
+                               bool high_speed)
+{
+	ASSERT(mci);
+	return _mci_sync_select_device(&mci->device, slot, clock, bus_width, high_speed);
+}
+
+/**
+ *  \brief Deselect a device by an assigned slot
+ */
+int32_t mci_sync_deselect_device(struct mci_sync_desc *mci, uint8_t slot)
+{
+	ASSERT(mci);
+	return _mci_sync_deselect_device(&mci->device, slot);
+}
+
+/**
+ *  \brief Get the maximum bus width of a device by a selected slot
+ */
+uint8_t mci_sync_get_bus_width(struct mci_sync_desc *mci, uint8_t slot)
+{
+	ASSERT(mci);
+	return _mci_sync_get_bus_width(&mci->device, slot);
+}
+
+/**
+ *  \brief Get the high speed capability of the device.
+ *
+ */
+bool mci_sync_is_high_speed_capable(struct mci_sync_desc *mci)
+{
+	ASSERT(mci);
+	return _mci_sync_is_high_speed_capable(&mci->device);
+}
+
+/**
+ *  \brief Send 74 clock cycles on the line.
+ */
+void mci_sync_send_clock(struct mci_sync_desc *mci)
+{
+	ASSERT(mci);
+	_mci_sync_send_clock(&mci->device);
+}
+
+/**
+ *  \brief Send a command on the selected slot
+ */
+bool mci_sync_send_cmd(struct mci_sync_desc *mci, uint32_t cmd, uint32_t arg)
+{
+	ASSERT(mci);
+	return _mci_sync_send_cmd(&mci->device, cmd, arg);
+}
+
+/**
+ *  \brief Get 32 bits response of the last command.
+ */
+uint32_t mci_sync_get_response(struct mci_sync_desc *mci)
+{
+	ASSERT(mci);
+	return _mci_sync_get_response(&mci->device);
+}
+
+/**
+ *  \brief Get 128 bits response of the last command.
+ */
+void mci_sync_get_response_128(struct mci_sync_desc *mci, uint8_t *response)
+{
+	ASSERT(mci && response);
+	_mci_sync_get_response_128(&mci->device, response);
+}
+
+/**
+ *  \brief Send an ADTC command on the selected slot
+ *         An ADTC (Addressed Data Transfer Commands)
+ *         command is used for read/write access.
+ */
+bool mci_sync_adtc_start(struct mci_sync_desc *mci, uint32_t cmd, uint32_t arg, uint16_t block_size, uint16_t nb_block,
+                         bool access_block)
+{
+	ASSERT(mci);
+	return _mci_sync_adtc_start(&mci->device, cmd, arg, block_size, nb_block, access_block);
+}
+
+/**
+ *  \brief Send a command to stop an ADTC command on the selected slot.
+ */
+bool mci_sync_adtc_stop(struct mci_sync_desc *mci, uint32_t cmd, uint32_t arg)
+{
+	ASSERT(mci);
+	return _mci_sync_adtc_stop(&mci->device, cmd, arg);
+}
+
+/**
+ *  \brief Read a word on the line.
+ */
+bool mci_sync_read_word(struct mci_sync_desc *mci, uint32_t *value)
+{
+	ASSERT(mci && value);
+	return _mci_sync_read_word(&mci->device, value);
+}
+
+/**
+ *  \brief Write a word on the line
+ */
+bool mci_sync_write_word(struct mci_sync_desc *mci, uint32_t value)
+{
+	ASSERT(mci);
+	return _mci_sync_write_word(&mci->device, value);
+}
+
+/**
+ *  \brief Start a read blocks transfer on the line
+ *  Note: The driver will use the DMA available to speed up the transfer.
+ */
+bool mci_sync_start_read_blocks(struct mci_sync_desc *mci, void *dst, uint16_t nb_block)
+{
+	ASSERT(mci && dst);
+	return _mci_sync_start_read_blocks(&mci->device, dst, nb_block);
+}
+
+/**
+ *  \brief Start a write blocks transfer on the line
+ */
+bool mci_sync_start_write_blocks(struct mci_sync_desc *mci, const void *src, uint16_t nb_block)
+{
+	ASSERT(mci && src);
+	return _mci_sync_start_write_blocks(&mci->device, src, nb_block);
+}
+
+/**
+ *  \brief Wait the end of transfer initiated by mci_start_read_blocks()
+ */
+bool mci_sync_wait_end_of_read_blocks(struct mci_sync_desc *mci)
+{
+	ASSERT(mci);
+	return _mci_sync_wait_end_of_read_blocks(&mci->device);
+}
+
+/**
+ *  \brief Wait the end of transfer initiated by mci_start_write_blocks()
+ */
+bool mci_sync_wait_end_of_write_blocks(struct mci_sync_desc *mci)
+{
+	ASSERT(mci);
+	return _mci_sync_wait_end_of_write_blocks(&mci->device);
+}
+
+/**
+ *  \brief Retrieve the current driver version
+ *  \return Current driver version
+ */
+uint32_t mci_sync_get_version(void)
+{
+	return DRIVER_VERSION;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/hal/utils/include/compiler.h b/hal/utils/include/compiler.h
index f35db3d..80ecb4f 100644
--- a/hal/utils/include/compiler.h
+++ b/hal/utils/include/compiler.h
@@ -52,6 +52,83 @@ extern "C" {
 #include <stdint.h>
 #include <stdbool.h>
 
+#define UNUSED(v) (void)(v)
+typedef uint16_t le16_t;
+typedef uint32_t le32_t;
+typedef uint16_t be16_t;
+typedef uint32_t be32_t;
+
+#if (defined __GNUC__) || (defined __CC_ARM)
+#define is_constant(exp) __builtin_constant_p(exp)
+#else
+#define is_constant(exp) (0)
+#endif
+
+/*! \brief Toggles the endianism of \a u16 (by swapping its bytes).
+ *
+ * \param u16 U16 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u16 with toggled endianism.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define swap_u16(u16) ((uint16_t)(((uint16_t)(u16) >> 8) | ((uint16_t)(u16) << 8)))
+
+/*! \brief Toggles the endianism of \a u32 (by swapping its bytes).
+ *
+ * \param u32 U32 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u32 with toggled endianism.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#if (defined __GNUC__)
+#define swap_u32(u32)                                                                                                  \
+	(is_constant(u32)                                                                                                  \
+	     ? ((uint32_t)(((uint32_t)swap_u16((uint32_t)(u32) >> 16)) | ((uint32_t)swap_u16((uint32_t)(u32)) << 16)))     \
+	     : ((uint32_t)__builtin_bswap32((uint32_t)(u32))))
+#else
+#define swap_u32(u32)                                                                                                  \
+	((uint32_t)(((uint32_t)swap_u16((uint32_t)(u32) >> 16)) | ((uint32_t)swap_u16((uint32_t)(u32)) << 16)))
+#endif
+
+/** Get a value from/to LE16 data */
+#define LE16(x) (x)
+/** Get a value from/to LE32 data */
+#define LE32(x) (x)
+/** Get a value from/to BE16 data */
+#define BE16(x) swap_u16(x)
+/** Get a value from/to BE32 data */
+#define BE32(x) swap_u32(x)
+
+/** Get byte 0 for BE 16-bit value */
+#define BE16B0(a) ((uint8_t)((a) >> 8))
+/** Get byte 1 for BE 16-bit value */
+#define BE16B1(a) ((uint8_t)((a) >> 0))
+
+/** Get byte 0 for BE 32-bit value */
+#define BE32B0(a) ((uint8_t)((a) >> 24))
+/** Get byte 1 for BE 32-bit value */
+#define BE32B1(a) ((uint8_t)((a) >> 16))
+/** Get byte 2 for BE 32-bit value */
+#define BE32B2(a) ((uint8_t)((a) >> 8))
+/** Get byte 3 for BE 32-bit value */
+#define BE32B3(a) ((uint8_t)((a) >> 0))
+
+/** Get byte 0 for LE 16-bit value */
+#define LE16B0(a) ((uint8_t)((a) >> 0))
+/** Get byte 1 for LE 16-bit value */
+#define LE16B1(a) ((uint8_t)((a) >> 8))
+
+/** Get byte 0 for LE 32-bit value */
+#define LE32B0(a) ((uint8_t)((a) >> 0))
+/** Get byte 1 for LE 32-bit value */
+#define LE32B1(a) ((uint8_t)((a) >> 8))
+/** Get byte 2 for LE 32-bit value */
+#define LE32B2(a) ((uint8_t)((a) >> 16))
+/** Get byte 3 for LE 32-bit value */
+#define LE32B3(a) ((uint8_t)((a) >> 24))
+
 #ifndef _UNIT_TEST_
 #include "parts.h"
 #endif
diff --git a/hal/utils/include/utils_decrement_macro.h b/hal/utils/include/utils_decrement_macro.h
new file mode 100644
index 0000000..2b52469
--- /dev/null
+++ b/hal/utils/include/utils_decrement_macro.h
@@ -0,0 +1,309 @@
+/**
+ * \file
+ *
+ * \brief Decrement macro.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _UTILS_DECREMENT_MACRO_H
+#define _UTILS_DECREMENT_MACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Compile time decrement, result value is entire integer literal
+ *
+ * \param[in] val - value to be decremented
+ */
+#define DEC_VALUE(val) DEC_##val
+
+// Preprocessor increment implementation
+#define DEC_256 255
+#define DEC_255 254
+#define DEC_254 253
+#define DEC_253 252
+#define DEC_252 251
+#define DEC_251 250
+#define DEC_250 249
+#define DEC_249 248
+#define DEC_248 247
+#define DEC_247 246
+#define DEC_246 245
+#define DEC_245 244
+#define DEC_244 243
+#define DEC_243 242
+#define DEC_242 241
+#define DEC_241 240
+#define DEC_240 239
+#define DEC_239 238
+#define DEC_238 237
+#define DEC_237 236
+#define DEC_236 235
+#define DEC_235 234
+#define DEC_234 233
+#define DEC_233 232
+#define DEC_232 231
+#define DEC_231 230
+#define DEC_230 229
+#define DEC_229 228
+#define DEC_228 227
+#define DEC_227 226
+#define DEC_226 225
+#define DEC_225 224
+#define DEC_224 223
+#define DEC_223 222
+#define DEC_222 221
+#define DEC_221 220
+#define DEC_220 219
+#define DEC_219 218
+#define DEC_218 217
+#define DEC_217 216
+#define DEC_216 215
+#define DEC_215 214
+#define DEC_214 213
+#define DEC_213 212
+#define DEC_212 211
+#define DEC_211 210
+#define DEC_210 209
+#define DEC_209 208
+#define DEC_208 207
+#define DEC_207 206
+#define DEC_206 205
+#define DEC_205 204
+#define DEC_204 203
+#define DEC_203 202
+#define DEC_202 201
+#define DEC_201 200
+#define DEC_200 199
+#define DEC_199 198
+#define DEC_198 197
+#define DEC_197 196
+#define DEC_196 195
+#define DEC_195 194
+#define DEC_194 193
+#define DEC_193 192
+#define DEC_192 191
+#define DEC_191 190
+#define DEC_190 189
+#define DEC_189 188
+#define DEC_188 187
+#define DEC_187 186
+#define DEC_186 185
+#define DEC_185 184
+#define DEC_184 183
+#define DEC_183 182
+#define DEC_182 181
+#define DEC_181 180
+#define DEC_180 179
+#define DEC_179 178
+#define DEC_178 177
+#define DEC_177 176
+#define DEC_176 175
+#define DEC_175 174
+#define DEC_174 173
+#define DEC_173 172
+#define DEC_172 171
+#define DEC_171 170
+#define DEC_170 169
+#define DEC_169 168
+#define DEC_168 167
+#define DEC_167 166
+#define DEC_166 165
+#define DEC_165 164
+#define DEC_164 163
+#define DEC_163 162
+#define DEC_162 161
+#define DEC_161 160
+#define DEC_160 159
+#define DEC_159 158
+#define DEC_158 157
+#define DEC_157 156
+#define DEC_156 155
+#define DEC_155 154
+#define DEC_154 153
+#define DEC_153 152
+#define DEC_152 151
+#define DEC_151 150
+#define DEC_150 149
+#define DEC_149 148
+#define DEC_148 147
+#define DEC_147 146
+#define DEC_146 145
+#define DEC_145 144
+#define DEC_144 143
+#define DEC_143 142
+#define DEC_142 141
+#define DEC_141 140
+#define DEC_140 139
+#define DEC_139 138
+#define DEC_138 137
+#define DEC_137 136
+#define DEC_136 135
+#define DEC_135 134
+#define DEC_134 133
+#define DEC_133 132
+#define DEC_132 131
+#define DEC_131 130
+#define DEC_130 129
+#define DEC_129 128
+#define DEC_128 127
+#define DEC_127 126
+#define DEC_126 125
+#define DEC_125 124
+#define DEC_124 123
+#define DEC_123 122
+#define DEC_122 121
+#define DEC_121 120
+#define DEC_120 119
+#define DEC_119 118
+#define DEC_118 117
+#define DEC_117 116
+#define DEC_116 115
+#define DEC_115 114
+#define DEC_114 113
+#define DEC_113 112
+#define DEC_112 111
+#define DEC_111 110
+#define DEC_110 109
+#define DEC_109 108
+#define DEC_108 107
+#define DEC_107 106
+#define DEC_106 105
+#define DEC_105 104
+#define DEC_104 103
+#define DEC_103 102
+#define DEC_102 101
+#define DEC_101 100
+#define DEC_100 99
+#define DEC_99 98
+#define DEC_98 97
+#define DEC_97 96
+#define DEC_96 95
+#define DEC_95 94
+#define DEC_94 93
+#define DEC_93 92
+#define DEC_92 91
+#define DEC_91 90
+#define DEC_90 89
+#define DEC_89 88
+#define DEC_88 87
+#define DEC_87 86
+#define DEC_86 85
+#define DEC_85 84
+#define DEC_84 83
+#define DEC_83 82
+#define DEC_82 81
+#define DEC_81 80
+#define DEC_80 79
+#define DEC_79 78
+#define DEC_78 77
+#define DEC_77 76
+#define DEC_76 75
+#define DEC_75 74
+#define DEC_74 73
+#define DEC_73 72
+#define DEC_72 71
+#define DEC_71 70
+#define DEC_70 69
+#define DEC_69 68
+#define DEC_68 67
+#define DEC_67 66
+#define DEC_66 65
+#define DEC_65 64
+#define DEC_64 63
+#define DEC_63 62
+#define DEC_62 61
+#define DEC_61 60
+#define DEC_60 59
+#define DEC_59 58
+#define DEC_58 57
+#define DEC_57 56
+#define DEC_56 55
+#define DEC_55 54
+#define DEC_54 53
+#define DEC_53 52
+#define DEC_52 51
+#define DEC_51 50
+#define DEC_50 49
+#define DEC_49 48
+#define DEC_48 47
+#define DEC_47 46
+#define DEC_46 45
+#define DEC_45 44
+#define DEC_44 43
+#define DEC_43 42
+#define DEC_42 41
+#define DEC_41 40
+#define DEC_40 39
+#define DEC_39 38
+#define DEC_38 37
+#define DEC_37 36
+#define DEC_36 35
+#define DEC_35 34
+#define DEC_34 33
+#define DEC_33 32
+#define DEC_32 31
+#define DEC_31 30
+#define DEC_30 29
+#define DEC_29 28
+#define DEC_28 27
+#define DEC_27 26
+#define DEC_26 25
+#define DEC_25 24
+#define DEC_24 23
+#define DEC_23 22
+#define DEC_22 21
+#define DEC_21 20
+#define DEC_20 19
+#define DEC_19 18
+#define DEC_18 17
+#define DEC_17 16
+#define DEC_16 15
+#define DEC_15 14
+#define DEC_14 13
+#define DEC_13 12
+#define DEC_12 11
+#define DEC_11 10
+#define DEC_10 9
+#define DEC_9 8
+#define DEC_8 7
+#define DEC_7 6
+#define DEC_6 5
+#define DEC_5 4
+#define DEC_4 3
+#define DEC_3 2
+#define DEC_2 1
+#define DEC_1 0
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _UTILS_DECREMENT_MACRO_H */
diff --git a/hal/utils/include/utils_recursion_macro.h b/hal/utils/include/utils_recursion_macro.h
new file mode 100644
index 0000000..294314c
--- /dev/null
+++ b/hal/utils/include/utils_recursion_macro.h
@@ -0,0 +1,69 @@
+/**
+ * \file
+ *
+ * \brief Recursion macro.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _UTILS_RECURSION_MACRO_H
+#define _UTILS_RECURSION_MACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * \brief Macro recursion
+ *
+ * \param[in] macro Macro to be repeated recursively
+ * \param[in] arg A recursive threshold, building on this to decline by times
+ *                defined with parameter n
+ * \param[in] n The number of repetitious calls to macro
+ */
+#define RECURSION_MACRO(macro, arg, n) RECURSION_MACRO_I(macro, arg, n)
+
+/*
+ * \brief Second level is needed to get integer literal from "n" if it is
+ *        defined as macro
+ */
+#define RECURSION_MACRO_I(macro, arg, n) RECURSION##n(macro, arg)
+
+#define RECURSION0(macro, arg)
+#define RECURSION1(macro, arg) RECURSION0(macro, DEC_VALUE(arg)) macro(arg, 0)
+#define RECURSION2(macro, arg) RECURSION1(macro, DEC_VALUE(arg)) macro(arg, 1)
+#define RECURSION3(macro, arg) RECURSION2(macro, DEC_VALUE(arg)) macro(arg, 2)
+#define RECURSION4(macro, arg) RECURSION3(macro, DEC_VALUE(arg)) macro(arg, 3)
+#define RECURSION5(macro, arg) RECURSION4(macro, DEC_VALUE(arg)) macro(arg, 4)
+
+#ifdef __cplusplus
+}
+#endif
+
+#include <utils_decrement_macro.h>
+#endif /* _UTILS_RECURSION_MACRO_H */
diff --git a/hpl/core/hpl_init.c b/hpl/core/hpl_init.c
index 705397d..be0db93 100644
--- a/hpl/core/hpl_init.c
+++ b/hpl/core/hpl_init.c
@@ -42,11 +42,10 @@
 #include <hal_cache.h>
 
 /* Referenced GCLKs (out of 0~11), should be initialized firstly
- * - GCLK 3 for DFLL
  */
-#define _GCLK_INIT_1ST 0x00000008
+#define _GCLK_INIT_1ST 0x00000000
 /* Not referenced GCLKs, initialized last */
-#define _GCLK_INIT_LAST 0x00000FF7
+#define _GCLK_INIT_LAST 0x00000FFF
 
 /**
  * \brief Initialize the hardware abstraction layer
diff --git a/hpl/rtc/hpl_rtc.c b/hpl/rtc/hpl_rtc.c
new file mode 100644
index 0000000..0575de6
--- /dev/null
+++ b/hpl/rtc/hpl_rtc.c
@@ -0,0 +1,399 @@
+
+/**
+ * \file
+ *
+ * \brief RTC Driver
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <hpl_calendar.h>
+#include <utils_assert.h>
+#include <hpl_rtc_config.h>
+
+/*!< Pointer to hpl device */
+static struct calendar_dev *_rtc_dev = NULL;
+
+/**
+ * \brief Initializes the RTC module with given configurations.
+ */
+int32_t _calendar_init(struct calendar_dev *const dev)
+{
+	ASSERT(dev && dev->hw);
+
+	_rtc_dev = dev;
+
+	if (hri_rtcmode0_get_CTRLA_ENABLE_bit(dev->hw)) {
+#if !CONF_RTC_INIT_RESET
+		return ERR_DENIED;
+#else
+		hri_rtcmode0_clear_CTRLA_ENABLE_bit(dev->hw);
+		hri_rtcmode0_wait_for_sync(dev->hw, RTC_MODE0_SYNCBUSY_ENABLE);
+#endif
+	}
+	hri_rtcmode0_set_CTRLA_SWRST_bit(dev->hw);
+	hri_rtcmode0_wait_for_sync(dev->hw, RTC_MODE0_SYNCBUSY_SWRST);
+
+#if CONF_RTC_EVENT_CONTROL_ENABLE == 1
+	hri_rtcmode0_write_EVCTRL_reg(
+	    dev->hw,
+	    (CONF_RTC_PEREO0 << RTC_MODE0_EVCTRL_PEREO0_Pos) | (CONF_RTC_PEREO1 << RTC_MODE0_EVCTRL_PEREO1_Pos)
+	        | (CONF_RTC_PEREO2 << RTC_MODE0_EVCTRL_PEREO2_Pos) | (CONF_RTC_PEREO3 << RTC_MODE0_EVCTRL_PEREO3_Pos)
+	        | (CONF_RTC_PEREO4 << RTC_MODE0_EVCTRL_PEREO4_Pos) | (CONF_RTC_PEREO5 << RTC_MODE0_EVCTRL_PEREO5_Pos)
+	        | (CONF_RTC_PEREO6 << RTC_MODE0_EVCTRL_PEREO6_Pos) | (CONF_RTC_PEREO7 << RTC_MODE0_EVCTRL_PEREO7_Pos)
+	        | (CONF_RTC_COMPE0 << RTC_MODE0_EVCTRL_CMPEO_Pos) | (CONF_RTC_COMPE1 << RTC_MODE0_EVCTRL_CMPEO1_Pos)
+	        | (CONF_RTC_TAMPEREO << RTC_MODE0_EVCTRL_TAMPEREO_Pos)
+	        | (CONF_RTC_TAMPEVEI << RTC_MODE0_EVCTRL_TAMPEVEI_Pos) | (CONF_RTC_OVFEO << RTC_MODE0_EVCTRL_OVFEO_Pos));
+#endif
+
+	hri_rtcmode0_write_CTRLA_reg(dev->hw, RTC_MODE0_CTRLA_PRESCALER(CONF_RTC_PRESCALER) | RTC_MODE0_CTRLA_COUNTSYNC);
+
+	hri_rtc_write_TAMPCTRL_reg(
+	    dev->hw,
+	    (CONF_RTC_TAMPER_INACT_0 << RTC_TAMPCTRL_IN0ACT_Pos) | (CONF_RTC_TAMPER_INACT_1 << RTC_TAMPCTRL_IN1ACT_Pos)
+	        | (CONF_RTC_TAMPER_INACT_2 << RTC_TAMPCTRL_IN2ACT_Pos)
+	        | (CONF_RTC_TAMPER_INACT_3 << RTC_TAMPCTRL_IN3ACT_Pos)
+	        | (CONF_RTC_TAMPER_INACT_4 << RTC_TAMPCTRL_IN4ACT_Pos) | (CONF_RTC_TAMP_LVL_0 << RTC_TAMPCTRL_TAMLVL0_Pos)
+	        | (CONF_RTC_TAMP_LVL_1 << RTC_TAMPCTRL_TAMLVL1_Pos) | (CONF_RTC_TAMP_LVL_2 << RTC_TAMPCTRL_TAMLVL2_Pos)
+	        | (CONF_RTC_TAMP_LVL_3 << RTC_TAMPCTRL_TAMLVL3_Pos) | (CONF_RTC_TAMP_LVL_4 << RTC_TAMPCTRL_TAMLVL4_Pos)
+	        | (CONF_RTC_TAMP_DEBNC_0 << RTC_TAMPCTRL_DEBNC0_Pos) | (CONF_RTC_TAMP_DEBNC_1 << RTC_TAMPCTRL_DEBNC1_Pos)
+	        | (CONF_RTC_TAMP_DEBNC_2 << RTC_TAMPCTRL_DEBNC2_Pos) | (CONF_RTC_TAMP_DEBNC_3 << RTC_TAMPCTRL_DEBNC3_Pos)
+	        | (CONF_RTC_TAMP_DEBNC_4 << RTC_TAMPCTRL_DEBNC4_Pos));
+
+	if ((CONF_RTC_TAMPER_INACT_0 == TAMPER_MODE_ACTL) | (CONF_RTC_TAMPER_INACT_1 == TAMPER_MODE_ACTL)
+	    | (CONF_RTC_TAMPER_INACT_2 == TAMPER_MODE_ACTL) | (CONF_RTC_TAMPER_INACT_3 == TAMPER_MODE_ACTL)
+	    | (CONF_RTC_TAMPER_INACT_4 == TAMPER_MODE_ACTL)) {
+		hri_rtcmode0_set_CTRLB_RTCOUT_bit(dev->hw);
+	}
+	return ERR_NONE;
+}
+
+/**
+ * \brief Deinit the RTC module
+ */
+int32_t _calendar_deinit(struct calendar_dev *const dev)
+{
+	ASSERT(dev && dev->hw);
+
+	NVIC_DisableIRQ(RTC_IRQn);
+	dev->callback = NULL;
+
+	hri_rtcmode0_clear_CTRLA_ENABLE_bit(dev->hw);
+	hri_rtcmode0_set_CTRLA_SWRST_bit(dev->hw);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Enable the RTC module
+ */
+int32_t _calendar_enable(struct calendar_dev *const dev)
+{
+	ASSERT(dev && dev->hw);
+
+	hri_rtcmode0_set_CTRLA_ENABLE_bit(dev->hw);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Disable the RTC module
+ */
+int32_t _calendar_disable(struct calendar_dev *const dev)
+{
+	ASSERT(dev && dev->hw);
+
+	hri_rtcmode0_clear_CTRLA_ENABLE_bit(dev->hw);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set the current calendar time to desired time.
+ */
+int32_t _calendar_set_counter(struct calendar_dev *const dev, const uint32_t counter)
+{
+	ASSERT(dev && dev->hw);
+
+	hri_rtcmode0_write_COUNT_reg(dev->hw, counter);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Get current counter
+ */
+uint32_t _calendar_get_counter(struct calendar_dev *const dev)
+{
+	ASSERT(dev && dev->hw);
+
+	return hri_rtcmode0_read_COUNT_reg(dev->hw);
+}
+
+/**
+ * \brief Set the compare for the specified value.
+ */
+int32_t _calendar_set_comp(struct calendar_dev *const dev, const uint32_t comp)
+{
+	ASSERT(dev && dev->hw);
+
+	hri_rtcmode0_write_COMP_reg(dev->hw, 0, comp);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Get the compare value
+ */
+uint32_t _calendar_get_comp(struct calendar_dev *const dev)
+{
+	ASSERT(dev && dev->hw);
+
+	return hri_rtcmode0_read_COMP_reg(dev->hw, 0);
+}
+
+/**
+ * \brief Find tamper is detected on specified pin
+ */
+bool _is_tamper_detected(struct calendar_dev *const dev, enum tamper_id tamper_id_pin)
+{
+	bool value;
+
+	ASSERT(dev && dev->hw);
+
+	value = ((hri_rtc_read_TAMPID_reg(dev->hw) >> tamper_id_pin) & 0x01);
+	return value;
+}
+
+/**
+ * \brief Clear the Tamper ID flag
+ */
+int32_t _tamper_clear_tampid_flag(struct calendar_dev *const dev, enum tamper_id tamper_id_pin)
+{
+	ASSERT(dev && dev->hw);
+
+	hri_rtc_write_TAMPID_reg(dev->hw, (true << tamper_id_pin));
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Enable Tamper Debounce Asynchronous Feature
+ */
+int32_t _tamper_enable_debounce_asynchronous(struct calendar_dev *const dev)
+{
+	int32_t return_value;
+
+	hri_rtcmode0_write_CTRLA_ENABLE_bit(dev->hw, false);
+
+	while (hri_rtcmode0_read_SYNCBUSY_reg(dev->hw) & RTC_MODE2_CTRLA_ENABLE) {
+	}
+
+	if (hri_rtcmode0_read_CTRLA_reg(dev->hw) & RTC_MODE2_CTRLA_ENABLE) {
+		return_value = ERR_FAILURE;
+	} else {
+		hri_rtcmode0_write_CTRLB_DEBASYNC_bit(dev->hw, true);
+		return_value = ERR_NONE;
+		while (hri_rtcmode0_read_SYNCBUSY_reg(dev->hw) & RTC_MODE2_CTRLA_ENABLE) {
+		}
+		hri_rtcmode0_write_CTRLA_ENABLE_bit(dev->hw, true);
+	}
+
+	return return_value;
+}
+
+/**
+ * \brief Disable Tamper Debounce Asynchronous Feature
+ */
+int32_t _tamper_disable_debounce_asynchronous(struct calendar_dev *const dev)
+{
+	int32_t return_value;
+
+	hri_rtcmode0_write_CTRLA_ENABLE_bit(dev->hw, false);
+
+	while (hri_rtcmode0_read_SYNCBUSY_reg(dev->hw) & RTC_MODE2_CTRLA_ENABLE) {
+	}
+
+	if (hri_rtcmode0_read_CTRLA_reg(dev->hw) & RTC_MODE2_CTRLA_ENABLE) {
+		return_value = ERR_FAILURE;
+	} else {
+		hri_rtcmode0_write_CTRLB_DEBASYNC_bit(dev->hw, false);
+		return_value = ERR_NONE;
+		while (hri_rtcmode0_read_SYNCBUSY_reg(dev->hw) & RTC_MODE2_CTRLA_ENABLE) {
+		}
+		hri_rtcmode0_write_CTRLA_ENABLE_bit(dev->hw, true);
+	}
+
+	return return_value;
+}
+
+/**
+ * \brief Enable Tamper Debounce Majority Feature
+ */
+int32_t _tamper_enable_debounce_majority(struct calendar_dev *const dev)
+{
+	int32_t return_value;
+
+	hri_rtcmode0_write_CTRLA_ENABLE_bit(dev->hw, false);
+
+	while (hri_rtcmode0_read_SYNCBUSY_reg(dev->hw) & RTC_MODE2_CTRLA_ENABLE) {
+	}
+
+	if (hri_rtcmode0_read_CTRLA_reg(dev->hw) & RTC_MODE2_CTRLA_ENABLE) {
+		return_value = ERR_FAILURE;
+	} else {
+		hri_rtcmode0_write_CTRLB_DEBMAJ_bit(dev->hw, true);
+		return_value = ERR_NONE;
+
+		while (hri_rtcmode0_read_SYNCBUSY_reg(dev->hw) & RTC_MODE2_CTRLA_ENABLE) {
+		}
+		hri_rtcmode0_write_CTRLA_ENABLE_bit(dev->hw, true);
+	}
+
+	return return_value;
+}
+
+/**
+ * \brief Disable Tamper Debounce Majority Feature
+ */
+int32_t _tamper_disable_debounce_majority(struct calendar_dev *const dev)
+{
+	int32_t return_value;
+
+	hri_rtcmode0_write_CTRLA_ENABLE_bit(dev->hw, false);
+
+	while (hri_rtcmode0_read_SYNCBUSY_reg(dev->hw) & RTC_MODE2_CTRLA_ENABLE) {
+	}
+
+	if (hri_rtcmode0_read_CTRLA_reg(dev->hw) & RTC_MODE2_CTRLA_ENABLE) {
+		return_value = ERR_FAILURE;
+	} else {
+		hri_rtcmode0_write_CTRLB_DEBMAJ_bit(dev->hw, false);
+		return_value = ERR_NONE;
+
+		while (hri_rtcmode0_read_SYNCBUSY_reg(dev->hw) & RTC_MODE2_CTRLA_ENABLE) {
+		}
+		hri_rtcmode0_write_CTRLA_ENABLE_bit(dev->hw, true);
+	}
+
+	return return_value;
+}
+
+int32_t _tamper_register_callback(struct calendar_dev *const dev, tamper_drv_cb_t callback_tamper)
+{
+	ASSERT(dev && dev->hw);
+
+	/* Check callback */
+	if (callback_tamper != NULL) {
+		/* register the callback */
+		dev->callback_tamper = callback_tamper;
+
+		/* enable RTC_IRQn */
+		NVIC_ClearPendingIRQ(RTC_IRQn);
+		NVIC_EnableIRQ(RTC_IRQn);
+
+		/* enable tamper interrupt */
+		hri_rtcmode0_set_INTEN_TAMPER_bit(dev->hw);
+	} else {
+		/* disable tamper interrupt */
+		hri_rtcmode0_clear_INTEN_TAMPER_bit(dev->hw);
+
+		/* disable RTC_IRQn */
+		NVIC_DisableIRQ(RTC_IRQn);
+	}
+
+	return ERR_NONE;
+}
+/**
+ * \brief Registers callback for the specified callback type
+ */
+int32_t _calendar_register_callback(struct calendar_dev *const dev, calendar_drv_cb_alarm_t callback)
+{
+	ASSERT(dev && dev->hw);
+
+	/* Check callback */
+	if (callback != NULL) {
+		/* register the callback */
+		dev->callback = callback;
+
+		/* enable RTC_IRQn */
+		NVIC_ClearPendingIRQ(RTC_IRQn);
+		NVIC_EnableIRQ(RTC_IRQn);
+
+		/* enable cmp */
+		hri_rtcmode0_set_INTEN_CMP0_bit(dev->hw);
+	} else {
+		/* disable cmp */
+		hri_rtcmode0_clear_INTEN_CMP0_bit(dev->hw);
+
+		/* disable RTC_IRQn */
+		NVIC_DisableIRQ(RTC_IRQn);
+	}
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief RTC interrupt handler
+ *
+ * \param[in] dev The pointer to calendar device struct
+ */
+static void _rtc_interrupt_handler(struct calendar_dev *dev)
+{
+	/* Read and mask interrupt flag register */
+	uint16_t interrupt_status  = hri_rtcmode0_read_INTFLAG_reg(dev->hw);
+	uint16_t interrupt_enabled = hri_rtcmode0_read_INTEN_reg(dev->hw);
+
+	if ((interrupt_status & interrupt_enabled) & RTC_MODE2_INTFLAG_ALARM0) {
+		dev->callback(dev);
+
+		/* Clear interrupt flag */
+		hri_rtcmode0_clear_interrupt_CMP0_bit(dev->hw);
+	} else if ((interrupt_status & interrupt_enabled) & RTC_MODE2_INTFLAG_TAMPER) {
+		dev->callback_tamper(dev);
+
+		/* Clear interrupt flag */
+		hri_rtcmode0_clear_interrupt_TAMPER_bit(dev->hw);
+	}
+}
+/**
+ * \brief Set calendar IRQ
+ */
+void _calendar_set_irq(struct calendar_dev *const dev)
+{
+	(void)dev;
+	NVIC_SetPendingIRQ(RTC_IRQn);
+}
+
+/**
+ * \brief Rtc interrupt handler
+ */
+void RTC_Handler(void)
+{
+	_rtc_interrupt_handler(_rtc_dev);
+}
diff --git a/hpl/rtc/hpl_rtc_base.h b/hpl/rtc/hpl_rtc_base.h
new file mode 100644
index 0000000..06e3bd7
--- /dev/null
+++ b/hpl/rtc/hpl_rtc_base.h
@@ -0,0 +1,52 @@
+/**
+ * \file
+ *
+ * \brief RTC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ */
+
+#ifndef _HPL_RTC2_V200_H_INCLUDED
+#define _HPL_RTC2_V200_H_INCLUDED
+
+#include <hpl_timer.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Retrieve timer helper functions
+ *
+ * \return A pointer to set of timer helper functions
+ */
+struct _timer_hpl_interface *_rtc_get_timer(void);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _HPL_RTC2_V200_H_INCLUDED */
diff --git a/hpl/sdhc/hpl_sdhc.c b/hpl/sdhc/hpl_sdhc.c
new file mode 100644
index 0000000..0eb66ee
--- /dev/null
+++ b/hpl/sdhc/hpl_sdhc.c
@@ -0,0 +1,640 @@
+/**
+ * \file
+ *
+ * \brief SAM SDHC HPL
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <utils_assert.h>
+#include "hpl_mci_sync.h"
+#include <hpl_sdhc_config.h>
+
+#define HSMCI_SLOT_0_SIZE 4
+
+static void _mci_reset(const void *const hw);
+static void _mci_set_speed(const void *const hw, uint32_t speed, uint8_t prog_clock_mode);
+static bool _mci_wait_busy(const void *const hw);
+static bool _mci_send_cmd_execute(const void *const hw, uint32_t cmdr, uint32_t cmd, uint32_t arg);
+
+/**
+ * \brief Reset the SDHC interface
+ *
+ * \param hw The pointer to MCI hardware instance
+ */
+static void _mci_reset(const void *const hw)
+{
+	ASSERT(hw);
+	hri_sdhc_set_SRR_SWRSTCMD_bit(hw);
+}
+
+/**
+ * \brief Set speed of the SDHC clock.
+ *
+ * \param hw       The pointer to MCI hardware instance
+ * \param speed    SDHC clock speed in Hz.
+ * \param prog_clock_mode     Use programmable clock mode
+ */
+static void _mci_set_speed(const void *const hw, uint32_t speed, uint8_t prog_clock_mode)
+{
+	uint32_t div;
+	uint32_t clkbase;
+	uint32_t clkmul;
+
+	if (hri_sdhc_get_CCR_SDCLKEN_bit(hw)) {
+		while (hri_sdhc_read_PSR_reg(hw) & (SDHC_PSR_CMDINHC_CANNOT | SDHC_PSR_CMDINHD_CANNOT))
+			;
+		hri_sdhc_clear_CCR_SDCLKEN_bit(hw);
+	}
+	//	clkbase = hri_sdhc_read_CA0R_BASECLKF_bf(hw);
+	clkbase = CONF_BASE_FREQUENCY;
+	clkmul  = hri_sdhc_read_CA1R_CLKMULT_bf(hw);
+
+	/* If programmable clock mode is enabled, baseclk is divided by 2 */
+	if (clkmul > 0) {
+		clkbase = clkbase / 2;
+	}
+	if (prog_clock_mode == 0) {
+		/* divided clock mode */
+		hri_sdhc_clear_CCR_CLKGSEL_bit(hw);
+		/* speed = Base Clock / 2*div */
+		div = (clkbase / speed) / 2;
+	} else {
+		/* programmable clock mode */
+		hri_sdhc_set_CCR_CLKGSEL_bit(hw);
+		/* Specific constraint for SDHC/SDMMC IP
+		   speed = Base Clock * Multi Clock / (div+1) */
+		div = (clkbase * (clkmul + 1)) / speed;
+		if (div > 0) {
+			div = div - 1;
+		}
+	}
+
+	/* Specific constraint for SDHC/SDMMC IP
+	The clock divider (DIV) in SDMMC_CCR must be set to a value different from 0 when HSEN is 1. */
+	if ((hri_sdhc_get_HC1R_HSEN_bit(hw)) && (div == 0)) {
+		div = 1;
+	}
+
+	/* Set clock divider */
+	hri_sdhc_write_CCR_SDCLKFSEL_bf(hw, div & 0xFF);
+	hri_sdhc_write_CCR_USDCLKFSEL_bf(hw, div >> 8);
+
+	hri_sdhc_set_CCR_INTCLKEN_bit(hw);
+	/* Repeat this step until Clock Stable is 1 */
+	while (hri_sdhc_get_CCR_INTCLKS_bit(hw) == 0)
+		;
+	/* Output the clock to the card -- Set SD Clock Enable */
+	hri_sdhc_set_CCR_SDCLKEN_bit(hw);
+}
+
+/**
+ * \brief Wait the end of busy signal on data line
+ *
+ * \param hw       The pointer to MCI hardware instance
+ * \return true if success, otherwise false
+ */
+static bool _mci_wait_busy(const void *const hw)
+{
+	uint32_t busy_wait = 0xFFFFFFFF;
+	uint32_t psr;
+
+	ASSERT(hw);
+
+	do {
+		psr = hri_sdhc_read_PSR_reg(hw);
+
+		if (busy_wait-- == 0) {
+			_mci_reset(hw);
+			return false;
+		}
+	} while (!(psr & SDHC_PSR_DATLL(1)));
+	return true;
+}
+
+/**
+ * \brief Send a command
+ *
+ * \param hw         The pointer to MCI hardware instance
+ * \param cmdr       CMDR resgister bit to use for this command
+ * \param cmd        Command definition
+ * \param arg        Argument of the command
+ *
+ * \return true if success, otherwise false
+ */
+static bool _mci_send_cmd_execute(const void *const hw, uint32_t cmdr, uint32_t cmd, uint32_t arg)
+{
+	uint32_t sr;
+	ASSERT(hw);
+
+	cmdr |= SDHC_CR_CMDIDX(cmd) | SDHC_CR_CMDTYP_NORMAL;
+
+	if (cmd & MCI_RESP_PRESENT) {
+
+		if (cmd & MCI_RESP_136) {
+			cmdr |= SDHC_CR_RESPTYP_136_BIT;
+		} else if (cmd & MCI_RESP_BUSY) {
+			cmdr |= SDHC_CR_RESPTYP_48_BIT_BUSY;
+		} else {
+			cmdr |= SDHC_CR_RESPTYP_48_BIT;
+		}
+	}
+
+	if (cmd & MCI_CMD_OPENDRAIN) {
+		hri_sdhc_set_MC1R_OPD_bit(hw);
+	} else {
+		hri_sdhc_clear_MC1R_OPD_bit(hw);
+	}
+
+	hri_sdhc_write_ARG1R_reg(hw, arg);
+	hri_sdhc_write_CR_reg(hw, cmdr);
+
+	/* Wait end of command */
+	do {
+		sr = hri_sdhc_read_EISTR_reg(hw);
+
+		if (cmd & MCI_RESP_CRC) {
+			if (sr
+			    & (SDHC_EISTR_CMDTEO | SDHC_EISTR_CMDEND | SDHC_EISTR_CMDIDX | SDHC_EISTR_DATTEO | SDHC_EISTR_DATEND
+			       | SDHC_EISTR_ADMA)) {
+				_mci_reset(hw);
+				hri_sdhc_set_EISTR_reg(hw, SDHC_EISTR_MASK);
+				return false;
+			}
+		} else {
+			if (sr
+			    & (SDHC_EISTR_CMDTEO | SDHC_EISTR_CMDEND | SDHC_EISTR_CMDIDX | SDHC_EISTR_CMDCRC | SDHC_EISTR_DATCRC
+			       | SDHC_EISTR_DATTEO | SDHC_EISTR_DATEND | SDHC_EISTR_ADMA)) {
+				_mci_reset(hw);
+				hri_sdhc_set_EISTR_reg(hw, SDHC_EISTR_MASK);
+				return false;
+			}
+		}
+	} while (!hri_sdhc_get_NISTR_CMDC_bit(hw));
+	if (!(cmdr & SDHC_CR_DPSEL_DATA)) {
+		hri_sdhc_set_NISTR_CMDC_bit(hw);
+	}
+	if (cmd & MCI_RESP_BUSY) {
+		if (!_mci_wait_busy(hw)) {
+			return false;
+		}
+	}
+
+	return true;
+}
+
+/**
+ *  \brief Initialize MCI low level driver.
+ */
+int32_t _mci_sync_init(struct _mci_sync_device *const mci_dev, void *const hw)
+{
+	ASSERT(mci_dev && hw);
+
+	mci_dev->hw = hw;
+
+	hri_sdhc_set_SRR_SWRSTALL_bit(hw);
+	while (hri_sdhc_get_SRR_SWRSTALL_bit(hw))
+		;
+
+	/* Set the Data Timeout Register to 2 Mega Cycles */
+	hri_sdhc_write_TCR_reg(hw, SDHC_TCR_DTCVAL(0xE));
+
+	/* Set 3v3 power supply */
+	hri_sdhc_write_PCR_reg(hw, SDHC_PCR_SDBPWR_ON | SDHC_PCR_SDBVSEL_3V3);
+
+	hri_sdhc_set_NISTER_reg(hw, SDHC_NISTER_MASK);
+	hri_sdhc_set_EISTER_reg(hw, SDHC_EISTER_MASK);
+
+	return ERR_NONE;
+}
+
+/**
+ *  \brief Deinitialize MCI low level driver.
+ */
+int32_t _mci_sync_deinit(struct _mci_sync_device *const mci_dev)
+{
+	ASSERT(mci_dev);
+
+	mci_dev->hw = NULL;
+	return ERR_NONE;
+}
+
+/**
+ *  \brief Select a device and initialize it
+ */
+int32_t _mci_sync_select_device(struct _mci_sync_device *const mci_dev, uint8_t slot, uint32_t clock, uint8_t bus_width,
+                                bool high_speed)
+{
+	(void)(slot);
+	void *hw;
+
+	ASSERT(mci_dev && mci_dev->hw);
+	hw = mci_dev->hw;
+
+	if (high_speed) {
+		hri_sdhc_set_HC1R_HSEN_bit(hw);
+	} else {
+		hri_sdhc_clear_HC1R_HSEN_bit(hw);
+	}
+
+	if (hri_sdhc_get_HC2R_PVALEN_bit(hw) == 0) {
+		_mci_set_speed(hw, clock, CONF_SDHC0_CLK_GEN_SEL);
+	}
+
+	switch (bus_width) {
+	case 1:
+		hri_sdhc_clear_HC1R_DW_bit(hw);
+		break;
+
+	case 4:
+		hri_sdhc_set_HC1R_DW_bit(hw);
+		break;
+
+	default:
+		return ERR_INVALID_ARG;
+	}
+
+	return ERR_NONE;
+}
+
+/**
+ *  \brief Deselect a device by an assigned slot
+ */
+int32_t _mci_sync_deselect_device(struct _mci_sync_device *const mci_dev, uint8_t slot)
+{
+	/* Nothing to do */
+	(void)(mci_dev);
+	(void)(slot);
+
+	return ERR_NONE;
+}
+
+/**
+ *  \brief Get the maximum bus width of a device
+ *         by a selected slot
+ */
+uint8_t _mci_sync_get_bus_width(struct _mci_sync_device *const mci_dev, uint8_t slot)
+{
+	(void)(mci_dev);
+
+	switch (slot) {
+	case 0:
+		return HSMCI_SLOT_0_SIZE;
+
+	default:
+		/* Slot number wrong */
+		return 0;
+	}
+}
+
+/**
+ *  \brief Get the high speed capability of the device.
+ */
+bool _mci_sync_is_high_speed_capable(struct _mci_sync_device *const mci_dev)
+{
+	return hri_sdhc_get_CA0R_HSSUP_bit(mci_dev->hw);
+}
+
+/**
+ *  \brief Send 74 clock cycles on the line.
+ *   Note: It is required after card plug and before card install.
+ */
+void _mci_sync_send_clock(struct _mci_sync_device *const mci_dev)
+{
+	ASSERT(mci_dev);
+
+	volatile uint32_t i;
+	for (i = 0; i < 5000; i++)
+		;
+}
+
+/**
+ *  \brief Send a command on the selected slot
+ */
+bool _mci_sync_send_cmd(struct _mci_sync_device *const mci_dev, uint32_t cmd, uint32_t arg)
+{
+	void *hw;
+	ASSERT(mci_dev && mci_dev->hw);
+	hw = mci_dev->hw;
+
+	/* Check Command Inhibit (CMD) in the Present State register */
+	if (hri_sdhc_get_PSR_CMDINHC_bit(hw)) {
+		return false;
+	}
+
+	hri_sdhc_clear_TMR_DMAEN_bit(hw);
+	hri_sdhc_write_BCR_reg(hw, 0);
+
+	return _mci_send_cmd_execute(hw, 0, cmd, arg);
+}
+
+/**
+ *  \brief Get 32 bits response of the last command.
+ */
+uint32_t _mci_sync_get_response(struct _mci_sync_device *const mci_dev)
+{
+	void *hw;
+	ASSERT(mci_dev && mci_dev->hw);
+	hw = mci_dev->hw;
+
+	return hri_sdhc_read_RR_reg(hw, 0);
+}
+
+/**
+ *  \brief Get 128 bits response of the last command.
+ */
+void _mci_sync_get_response_128(struct _mci_sync_device *const mci_dev, uint8_t *response)
+{
+	uint32_t response_32;
+	void *   hw;
+	ASSERT(mci_dev && mci_dev->hw);
+	hw = mci_dev->hw;
+
+	for (int8_t i = 3; i >= 0; i--) {
+		response_32 = hri_sdhc_read_RR_reg(hw, i);
+		if (i != 3) {
+			*response = (response_32 >> 24) & 0xFF;
+			response++;
+		}
+		*response = (response_32 >> 16) & 0xFF;
+		response++;
+		*response = (response_32 >> 8) & 0xFF;
+		response++;
+		*response = (response_32 >> 0) & 0xFF;
+		response++;
+	}
+}
+
+/**
+ *  \brief Send an ADTC command on the selected slot
+ *         An ADTC (Addressed Data Transfer Commands)
+ *         command is used for read/write access.
+ */
+bool _mci_sync_adtc_start(struct _mci_sync_device *const mci_dev, uint32_t cmd, uint32_t arg, uint16_t block_size,
+                          uint16_t nb_block, bool access_block)
+{
+	uint32_t tmr;
+	void *   hw;
+	ASSERT(mci_dev && mci_dev->hw);
+	hw = mci_dev->hw;
+
+	/* No use without dma support */
+	(void)access_block;
+
+	/* Check Command Inhibit (CMD/DAT) in the Present State register */
+	if (hri_sdhc_get_PSR_CMDINHC_bit(hw) || hri_sdhc_get_PSR_CMDINHD_bit(hw)) {
+		return false;
+	}
+
+	if (cmd & MCI_CMD_WRITE) {
+		tmr = SDHC_TMR_DTDSEL_WRITE;
+	} else {
+		tmr = SDHC_TMR_DTDSEL_READ;
+	}
+
+	if (cmd & MCI_CMD_SDIO_BYTE) {
+		tmr |= SDHC_TMR_MSBSEL_SINGLE;
+	} else if (cmd & MCI_CMD_SDIO_BLOCK) {
+		tmr |= SDHC_TMR_BCEN | SDHC_TMR_MSBSEL_MULTIPLE;
+	} else if (cmd & MCI_CMD_SINGLE_BLOCK) {
+		tmr |= SDHC_TMR_MSBSEL_SINGLE;
+	} else if (cmd & MCI_CMD_MULTI_BLOCK) {
+		tmr |= SDHC_TMR_BCEN | SDHC_TMR_MSBSEL_MULTIPLE;
+	} else {
+		return false;
+	}
+	hri_sdhc_write_TMR_reg(hw, tmr);
+	hri_sdhc_write_BSR_reg(hw, SDHC_BSR_BLOCKSIZE(block_size) | SDHC_BSR_BOUNDARY_4K);
+	hri_sdhc_write_BCR_reg(hw, SDHC_BCR_BCNT(nb_block));
+
+	mci_dev->mci_sync_trans_pos  = 0;
+	mci_dev->mci_sync_block_size = block_size;
+	mci_dev->mci_sync_nb_block   = nb_block;
+
+	return _mci_send_cmd_execute(hw, SDHC_CR_DPSEL_DATA, cmd, arg);
+}
+
+/**
+ *  \brief Send a command to stop an ADTC command on the selected slot.
+ */
+bool _mci_sync_adtc_stop(struct _mci_sync_device *const mci_dev, uint32_t cmd, uint32_t arg)
+{
+	ASSERT(mci_dev && mci_dev->hw);
+	/* Nothing to do */
+	(void)(cmd);
+	(void)(arg);
+
+	return true;
+}
+
+/**
+ *  \brief Read a word on the line.
+ */
+bool _mci_sync_read_word(struct _mci_sync_device *const mci_dev, uint32_t *value)
+{
+	uint32_t sr;
+	uint8_t  nbytes;
+	void *   hw;
+
+	ASSERT(mci_dev && mci_dev->hw);
+	hw = mci_dev->hw;
+
+	/* Wait data available */
+	nbytes = (mci_dev->mci_sync_block_size * mci_dev->mci_sync_nb_block - mci_dev->mci_sync_trans_pos < 4)
+	             ? (mci_dev->mci_sync_block_size % 4)
+	             : 4;
+
+	if (mci_dev->mci_sync_trans_pos % mci_dev->mci_sync_block_size == 0) {
+		do {
+			sr = hri_sdhc_read_EISTR_reg(hw);
+
+			if (sr & (SDHC_EISTR_DATTEO | SDHC_EISTR_DATCRC | SDHC_EISTR_DATEND)) {
+				_mci_reset(hw);
+				return false;
+			}
+		} while (!hri_sdhc_get_NISTR_BRDRDY_bit(hw));
+		hri_sdhc_set_NISTR_BRDRDY_bit(hw);
+	}
+
+	/* Read data */
+	if (nbytes == 4) {
+		*value = hri_sdhc_read_BDPR_reg(hw);
+	} else {
+		sr = hri_sdhc_read_BDPR_reg(hw);
+		switch (nbytes) {
+		case 3:
+			value[0] = sr & 0xFFFFFF;
+		case 2:
+			value[0] = sr & 0xFFFF;
+		case 1:
+			value[0] = sr & 0xFF;
+			break;
+		}
+	}
+	mci_dev->mci_sync_trans_pos += nbytes;
+
+	if (((uint64_t)mci_dev->mci_sync_block_size * mci_dev->mci_sync_nb_block) > mci_dev->mci_sync_trans_pos) {
+		return true;
+	}
+
+	/* Wait end of transfer */
+	do {
+		sr = hri_sdhc_read_EISTR_reg(hw);
+
+		if (sr & (SDHC_EISTR_DATTEO | SDHC_EISTR_DATCRC | SDHC_EISTR_DATEND)) {
+			_mci_reset(hw);
+			return false;
+		}
+	} while (!hri_sdhc_get_NISTR_TRFC_bit(hw));
+	hri_sdhc_set_NISTR_TRFC_bit(hw);
+	return true;
+}
+
+/**
+ *  \brief Write a word on the line
+ */
+bool _mci_sync_write_word(struct _mci_sync_device *const mci_dev, uint32_t value)
+{
+	uint32_t sr;
+	uint8_t  nbytes;
+	void *   hw;
+
+	ASSERT(mci_dev && mci_dev->hw);
+	hw = mci_dev->hw;
+
+	/* Wait data available */
+	nbytes = 4; //( mci_dev->mci_sync_block_size & 0x3 ) ? 1 : 4;
+	if (mci_dev->mci_sync_trans_pos % mci_dev->mci_sync_block_size == 0) {
+		do {
+			sr = hri_sdhc_read_EISTR_reg(hw);
+
+			if (sr & (SDHC_EISTR_DATTEO | SDHC_EISTR_DATCRC | SDHC_EISTR_DATEND)) {
+				_mci_reset(hw);
+				return false;
+			}
+		} while (!hri_sdhc_get_NISTR_BWRRDY_bit(hw));
+		hri_sdhc_set_NISTR_BWRRDY_bit(hw);
+	}
+	/* Write data */
+	hri_sdhc_write_BDPR_reg(hw, value);
+	mci_dev->mci_sync_trans_pos += nbytes;
+
+	if (((uint64_t)mci_dev->mci_sync_block_size * mci_dev->mci_sync_nb_block) > mci_dev->mci_sync_trans_pos) {
+		return true;
+	}
+
+	/* Wait end of transfer */
+	do {
+		sr = hri_sdhc_read_EISTR_reg(hw);
+
+		if (sr & (SDHC_EISTR_DATTEO | SDHC_EISTR_DATCRC | SDHC_EISTR_DATEND)) {
+			_mci_reset(hw);
+			return false;
+		}
+	} while (!hri_sdhc_get_NISTR_TRFC_bit(hw));
+	hri_sdhc_set_NISTR_TRFC_bit(hw);
+	return true;
+}
+
+/**
+ *  \brief Start a read blocks transfer on the line
+ *  Note: The driver will use the DMA available to speed up the transfer.
+ */
+bool _mci_sync_start_read_blocks(struct _mci_sync_device *const mci_dev, void *dst, uint16_t nb_block)
+{
+	uint32_t nb_data;
+	uint8_t *ptr    = (uint8_t *)dst;
+	uint8_t  nbytes = 4;
+
+	ASSERT(mci_dev && mci_dev->hw);
+	ASSERT(nb_block);
+	ASSERT(dst);
+
+	nb_data = nb_block * mci_dev->mci_sync_block_size;
+
+	while (nb_data) {
+		_mci_sync_read_word(mci_dev, (uint32_t *)ptr);
+		if (nb_data < nbytes) {
+			nbytes = mci_dev->mci_sync_block_size % nbytes;
+		}
+		nb_data -= nbytes;
+		ptr += nbytes;
+	}
+
+	return true;
+}
+
+/**
+ *  \brief Start a write blocks transfer on the line
+ *  Note: The driver will use the DMA available to speed up the transfer.
+ */
+bool _mci_sync_start_write_blocks(struct _mci_sync_device *const mci_dev, const void *src, uint16_t nb_block)
+{
+	uint32_t nb_data;
+	uint8_t *ptr    = (uint8_t *)src;
+	uint8_t  nbytes = 4;
+
+	ASSERT(mci_dev && mci_dev->hw);
+	ASSERT(nb_block);
+	ASSERT(src);
+
+	nb_data = nb_block * mci_dev->mci_sync_block_size;
+
+	while (nb_data) {
+		_mci_sync_write_word(mci_dev, *(uint32_t *)ptr);
+		if (nb_data < nbytes) {
+			nbytes = mci_dev->mci_sync_block_size % nbytes;
+		}
+		nb_data -= nbytes;
+		ptr += nbytes;
+	}
+
+	return true;
+}
+
+/**
+ *  \brief Wait the end of transfer initiated by mci_start_read_blocks()
+ */
+bool _mci_sync_wait_end_of_read_blocks(struct _mci_sync_device *const mci_dev)
+{
+	ASSERT(mci_dev && mci_dev->hw);
+
+	/* Always return true for sync read blocks */
+	return true;
+}
+
+/**
+ *  \brief Wait the end of transfer initiated by mci_start_write_blocks()
+ */
+bool _mci_sync_wait_end_of_write_blocks(struct _mci_sync_device *const mci_dev)
+{
+	ASSERT(mci_dev && mci_dev->hw);
+
+	/* Always return true for sync write blocks */
+	return true;
+}
diff --git a/main.c b/main.c
index 4652da4..4da2906 100644
--- a/main.c
+++ b/main.c
@@ -1,10 +1,15 @@
 #include <atmel_start.h>
+#include "pdebug.h"
+#include "sd_mmc_start.h"
 
 int main(void)
 {
 	/* Initializes MCU, drivers and middleware */
 	atmel_start_init();
+	pdebug_init();
+	printf("Hello world\n");
 
+	SDMMC_example();
 	/* Replace with your application code */
 	while (1) {
 	}
diff --git a/sd_mmc/sd_mmc.c b/sd_mmc/sd_mmc.c
new file mode 100644
index 0000000..f4e98a2
--- /dev/null
+++ b/sd_mmc/sd_mmc.c
@@ -0,0 +1,1960 @@
+/**
+ * \file
+ *
+ * \brief Common SD/MMC stack
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#include <string.h>
+
+#include "conf_sd_mmc.h"
+
+#include "hal_spi_m_sync.h"
+#include "sd_mmc_protocol.h"
+#include "sd_mmc.h"
+
+#if CONF_OS_SUPPORT
+#include <hal_rtos.h>
+#endif
+#include <hal_gpio.h>
+#include <utils.h>
+#include <utils_assert.h>
+#include <utils_repeat_macro.h>
+
+#define TPASTE2(a, b) a##b
+#define ATPASTE2(a, b) TPASTE2(a, b)
+
+/**
+ * \ingroup sd_mmc_stack
+ * \defgroup sd_mmc_stack_internal Implementation of SD/MMC/SDIO Stack
+ * @{
+ */
+
+#ifndef CONF_SD_MMC_MEM_CNT
+#define CONF_SD_MMC_MEM_CNT 0
+#endif
+
+/* Macros to switch SD MMC stack to the correct driver (MCI or SPI) */
+#if (CONF_SD_MMC_MEM_CNT != 0)
+#if CONF_MCI_OS_SUPPORT
+#include "hal_mci_os.h"
+#else
+#include "hal_mci_sync.h"
+#endif
+#define driver spi_m
+#include "sd_mmc_spi.h"
+#else
+#error No MCI or HSMCI interfaces are defined for SD MMC stack. \
+     CONF_SD_MMC_MEM_CNT must be added in board.h file.
+#endif
+
+#if CONF_MCI_OS_SUPPORT
+#define driver_select_device ATPASTE2(driver, _os_select_device)
+#define driver_deselect_device ATPASTE2(driver, _os_deselect_device)
+#define driver_get_bus_width ATPASTE2(driver, _os_get_bus_width)
+#define driver_is_high_speed_capable ATPASTE2(driver, _os_is_high_speed_capable)
+#define driver_send_clock ATPASTE2(driver, _os_send_init_sequence)
+#define driver_send_cmd ATPASTE2(driver, _os_send_cmd)
+#define driver_get_response ATPASTE2(driver, _os_get_response)
+#define driver_get_response_128 ATPASTE2(driver, _os_get_response_128)
+#define driver_adtc_start ATPASTE2(driver, _os_adtc_start)
+#define driver_adtc_stop ATPASTE2(driver, _os_send_cmd)
+#define driver_read_word ATPASTE2(driver, _os_read_bytes)
+#define driver_write_word ATPASTE2(driver, _os_write_bytes)
+#define driver_start_read_blocks ATPASTE2(driver, _os_start_read_blocks)
+#define driver_wait_end_of_read_blocks ATPASTE2(driver, _os_wait_end_of_read_blocks)
+#define driver_start_write_blocks ATPASTE2(driver, _os_start_write_blocks)
+#define driver_wait_end_of_write_blocks ATPASTE2(driver, _os_wait_end_of_write_blocks)
+#else
+#define driver_select_device ATPASTE2(driver, _sync_select_device)
+#define driver_deselect_device ATPASTE2(driver, _sync_deselect_device)
+#define driver_get_bus_width ATPASTE2(driver, _sync_get_bus_width)
+#define driver_is_high_speed_capable ATPASTE2(driver, _sync_is_high_speed_capable)
+#define driver_send_clock ATPASTE2(driver, _sync_send_clock)
+#define driver_send_cmd ATPASTE2(driver, _sync_send_cmd)
+#define driver_get_response ATPASTE2(driver, _sync_get_response)
+#define driver_get_response_128 ATPASTE2(driver, _sync_get_response_128)
+#define driver_adtc_start ATPASTE2(driver, _sync_adtc_start)
+#define driver_adtc_stop ATPASTE2(driver, _sync_send_cmd)
+#define driver_read_word ATPASTE2(driver, _sync_read_word)
+#define driver_write_word ATPASTE2(driver, _sync_write_word)
+#define driver_start_read_blocks ATPASTE2(driver, _sync_start_read_blocks)
+#define driver_wait_end_of_read_blocks ATPASTE2(driver, _sync_wait_end_of_read_blocks)
+#define driver_start_write_blocks ATPASTE2(driver, _sync_start_write_blocks)
+#define driver_wait_end_of_write_blocks ATPASTE2(driver, _sync_wait_end_of_write_blocks)
+#endif
+
+#if (CONF_SDIO_SUPPORT == 1)
+#define IS_SDIO() (sd_mmc_card->type & CARD_TYPE_SDIO)
+#else
+#define IS_SDIO() false
+#endif
+
+/** This SD MMC stack supports only the high voltage */
+#define SD_MMC_VOLTAGE_SUPPORT                                                                                         \
+	(OCR_VDD_27_28 | OCR_VDD_28_29 | OCR_VDD_29_30 | OCR_VDD_30_31 | OCR_VDD_31_32 | OCR_VDD_32_33)
+
+/** SD/MMC card states */
+enum card_state {
+	SD_MMC_CARD_STATE_READY    = 0, /**< Ready to use */
+	SD_MMC_CARD_STATE_DEBOUNCE = 1, /**< Debounce on going */
+	SD_MMC_CARD_STATE_INIT     = 2, /**< Initialization on going */
+	SD_MMC_CARD_STATE_UNUSABLE = 3, /**< Unusable card */
+	SD_MMC_CARD_STATE_NO_CARD  = 4  /**< No SD/MMC card inserted */
+};
+
+/** SD/MMC card information structure */
+struct sd_mmc_card {
+	uint32_t        clock;              /**< Card access clock */
+	uint32_t        capacity;           /**< Card capacity in KBytes */
+	uint16_t        rca;                /**< Relative card address */
+	enum card_state state;              /**< Card state */
+	card_type_t     type;               /**< Card type */
+	card_version_t  version;            /**< Card version */
+	uint8_t         bus_width;          /**< Number of DATA lin on bus (MCI only) */
+	uint8_t         csd[CSD_REG_BSIZE]; /**< CSD register */
+	uint8_t         high_speed;         /**< High speed card (1) */
+};
+
+/** Card detect pin */
+static sd_mmc_detect_t *_cd;
+/** Write protect pin */
+static sd_mmc_detect_t *_wp;
+
+/** SD/MMC card list */
+/** Note: Initialize card detect pin fields if present */
+static struct sd_mmc_card sd_mmc_cards[CONF_SD_MMC_MEM_CNT];
+
+/** HAL driver instance */
+static void *sd_mmc_hal;
+/** Index of current slot configurated */
+static uint8_t sd_mmc_slot_sel;
+/** Pointer on current slot configurated */
+static struct sd_mmc_card *sd_mmc_card;
+/** Number of block to read or write on the current transfer */
+static uint16_t sd_mmc_nb_block_to_tranfer = 0;
+/** Number of block remaining to read or write on the current transfer */
+static uint16_t sd_mmc_nb_block_remaining = 0;
+
+/** SD/MMC transfer rate unit codes (10K) list */
+const uint32_t sd_mmc_trans_units[7] = {10, 100, 1000, 10000, 0, 0, 0};
+/** SD transfer multiplier factor codes (1/10) list */
+const uint32_t sd_trans_multipliers[16] = {0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80};
+/** MMC transfer multiplier factor codes (1/10) list */
+const uint32_t mmc_trans_multipliers[16] = {0, 10, 12, 13, 15, 20, 26, 30, 35, 40, 45, 52, 55, 60, 70, 80};
+
+/** \name MMC, SD and SDIO commands process */
+/** @{ */
+#if CONF_MMC_SUPPORT
+static bool mmc_mci_op_cond(void);
+static bool mmc_cmd6_set_bus_width(uint8_t bus_width);
+static bool mmc_cmd6_set_high_speed(void);
+static bool mmc_cmd8(uint8_t *b_authorize_high_speed);
+static void mmc_decode_csd(void);
+#endif
+static bool mmc_spi_op_cond(void);
+static bool sd_spi_op_cond(uint8_t v2);
+static bool sd_mmc_cmd9_spi(void);
+static bool sd_mci_op_cond(uint8_t v2);
+static bool sdio_op_cond(void);
+static bool sdio_get_max_speed(void);
+static bool sdio_cmd52_set_bus_width(void);
+static bool sdio_cmd52_set_high_speed(void);
+static bool sd_cm6_set_high_speed(void);
+static bool sd_cmd8(uint8_t *v2);
+static bool sd_mmc_cmd9_mci(void);
+static void sd_decode_csd(void);
+static bool sd_mmc_cmd13(void);
+#if (CONF_SDIO_SUPPORT == 1)
+static bool sdio_cmd52(uint8_t rw_flag, uint8_t func_nb, uint32_t reg_addr, uint8_t rd_after_wr, uint8_t *io_data);
+static bool sdio_cmd53(uint8_t rw_flag, uint8_t func_nb, uint32_t reg_addr, uint8_t inc_addr, uint32_t size,
+                       bool access_block);
+#endif
+static bool sd_acmd6(void);
+static bool sd_acmd51(void);
+/** @} */
+
+/** \name Internal function to process the initialization and install */
+/** @{ */
+static sd_mmc_err_t sd_mmc_select_slot(uint8_t slot);
+static void         sd_mmc_configure_slot(void);
+static void         sd_mmc_deselect_slot(void);
+static bool		sd_mmc_spi_card_init(void);
+static bool sd_mmc_mci_card_init(void);
+static bool sd_mmc_spi_install_mmc(void);
+
+#if CONF_MMC_SUPPORT
+static bool sd_mmc_mci_install_mmc(void);
+#endif
+/** @} */
+
+/** \name Internal functions to manage a large timeout after a card insertion */
+/** @{ */
+#if CONF_OS_SUPPORT
+#define SD_MMC_START_TIMEOUT() os_sleep(CONF_SD_MMC_DEBOUNCE)
+#else
+#define SD_MMC_START_TIMEOUT()
+#endif
+#define SD_MMC_IS_TIMEOUT() true
+#define SD_MMC_STOP_TIMEOUT()
+/** @} */
+
+/**
+ * \brief Sends operation condition command and read OCR (SPI only)
+ * - CMD1 sends operation condition command
+ * - CMD58 reads OCR
+ *
+ * \return true if success, otherwise false
+ */
+static bool mmc_spi_op_cond(void)
+{
+	uint32_t retry, resp;
+
+	/*
+	 * Timeout 1s = 400KHz / ((6+1)*8) cylces = 7150 retry
+	 * 6 = cmd byte size
+	 * 1 = response byte size
+	 */
+	retry = 7150;
+	do {
+		if (!driver_send_cmd(sd_mmc_hal, MMC_SPI_CMD1_SEND_OP_COND, 0)) {
+			sd_mmc_spi_debug("%s: CMD1 SPI Fail - Busy retry %d\n\r",
+					__func__, (int)(7150 - retry));
+			return false;
+		}
+		// Check busy flag
+		resp = driver_get_response(sd_mmc_hal);
+		if (!(resp & R1_SPI_IDLE)) {
+			break;
+		}
+		if (retry-- == 0) {
+			sd_mmc_spi_debug("%s: CMD1 Timeout on busy\n\r", __func__);
+			return false;
+		}
+	} while (1);
+
+	// Read OCR for SPI mode
+	if (!driver_send_cmd(sd_mmc_hal, SDMMC_SPI_CMD58_READ_OCR, 0)) {
+		sd_mmc_spi_debug("%s: CMD58 Fail\n\r", __func__);
+		return false;
+	}
+	// Check OCR value
+	if ((driver_get_response(sd_mmc_hal) & OCR_ACCESS_MODE_MASK)
+			== OCR_ACCESS_MODE_SECTOR) {
+		sd_mmc_card->type |= CARD_TYPE_HC;
+	}
+	return true;
+}
+
+/**
+ * \brief Ask to all cards to send their operations conditions (SPI only).
+ * - ACMD41 sends operation condition command.
+ * - CMD58 reads OCR
+ *
+ * \param v2   Shall be 1 if it is a SD card V2
+ *
+ * \return true if success, otherwise false
+ */
+static bool sd_spi_op_cond(uint8_t v2)
+{
+	uint32_t arg, retry, resp;
+
+	/*
+	 * Timeout 1s = 400KHz / ((6+1)*8) cylces = 7150 retry
+	 * 6 = cmd byte size
+	 * 1 = response byte size
+	 */
+	retry = 7150;
+	do {
+		// CMD55 - Indicate to the card that the next command is an
+		// application specific command rather than a standard command.
+		if (!driver_send_cmd(sd_mmc_hal, SDMMC_CMD55_APP_CMD, 0)) {
+			sd_mmc_spi_debug("%s: CMD55 Fail\n\r", __func__);
+			return false;
+		}
+
+		// (ACMD41) Sends host OCR register
+		arg =0;
+		if (v2) {
+			arg |= SD_ACMD41_HCS;
+		}
+		// Check response
+		if (!driver_send_cmd(sd_mmc_hal, SD_SPI_ACMD41_SD_SEND_OP_COND, arg)) {
+			sd_mmc_spi_debug("%s: ACMD41 Fail\n\r", __func__);
+			return false;
+		}
+		resp = driver_get_response(sd_mmc_hal);
+		if (!(resp & R1_SPI_IDLE)) {
+			// Card is ready
+			break;
+		}
+		if (retry-- == 0) {
+			sd_mmc_spi_debug("%s: ACMD41 Timeout on busy, resp32 0x%08x \n\r",
+					__func__, resp);
+			return false;
+		}
+	} while (1);
+
+	// Read OCR for SPI mode
+	if (!driver_send_cmd(sd_mmc_hal, SDMMC_SPI_CMD58_READ_OCR, 0)) {
+		sd_mmc_spi_debug("%s: CMD58 Fail\n\r", __func__);
+		return false;
+	}
+	if ((driver_get_response(sd_mmc_hal) & OCR_CCS) != 0) {
+		sd_mmc_card->type |= CARD_TYPE_HC;
+	}
+	return true;
+}
+
+/**
+ * \brief Initialize the SD card in SPI mode.
+ *
+ * \note
+ * This function runs the initialization procedure and the identification
+ * process, then it sets the SD/MMC card in transfer state.
+ * At last, it will automaticly enable maximum bus width and transfer speed.
+ *
+ * \return true if success, otherwise false
+ */
+static bool sd_mmc_spi_card_init(void)
+{
+	uint8_t v2 = 0;
+
+	// In first, try to install SD/SDIO card
+	sd_mmc_card->type = CARD_TYPE_SD;
+	sd_mmc_card->version = CARD_VER_UNKNOWN;
+	sd_mmc_card->rca = 0;
+	sd_mmc_spi_debug("Start SD card install\n\r");
+
+	// Card need of 74 cycles clock minimum to start
+	driver_send_clock(sd_mmc_hal);
+
+	// CMD0 - Reset all cards to idle state.
+	if (!driver_send_cmd(sd_mmc_hal, SDMMC_SPI_CMD0_GO_IDLE_STATE, 0)) {
+		return false;
+	}
+	if (!sd_cmd8(&v2)) {
+		return false;
+	}
+	// Try to get the SDIO card's operating condition
+	if (!sdio_op_cond()) {
+		return false;
+	}
+
+	if (sd_mmc_card->type & CARD_TYPE_SD) {
+		// Try to get the SD card's operating condition
+		if (!sd_spi_op_cond(v2)) {
+			// It is not a SD card
+			sd_mmc_spi_debug("Start MMC Install\n\r");
+			sd_mmc_card->type = CARD_TYPE_MMC;
+			return sd_mmc_spi_install_mmc();
+		}
+
+		/* The CRC on card is disabled by default.
+		 * However, to be sure, the CRC OFF command is send.
+		 * Unfortunately, specific SDIO card does not support it
+		 * (H&D wireless card - HDG104 WiFi SIP)
+		 * and the command is send only on SD card.
+		 */
+		if (!driver_send_cmd(sd_mmc_hal, SDMMC_SPI_CMD59_CRC_ON_OFF, 0)) {
+			return false;
+		}
+	}
+	// SD MEMORY
+	if (sd_mmc_card->type & CARD_TYPE_SD) {
+		// Get the Card-Specific Data
+		if (!sd_mmc_cmd9_spi()) {
+			return false;
+		}
+		sd_decode_csd();
+		// Read the SCR to get card version
+		if (!sd_acmd51()) {
+			return false;
+		}
+	}
+	if (IS_SDIO()) {
+		if (!sdio_get_max_speed()) {
+			return false;
+		}
+	}
+	// SD MEMORY not HC, Set default block size
+	if ((sd_mmc_card->type & CARD_TYPE_SD) &&
+			(0 == (sd_mmc_card->type & CARD_TYPE_HC))) {
+		if (!driver_send_cmd(sd_mmc_hal, SDMMC_CMD16_SET_BLOCKLEN, SD_MMC_BLOCK_SIZE)) {
+			return false;
+		}
+	}
+	// Check communication
+	if (sd_mmc_card->type & CARD_TYPE_SD) {
+		if (!sd_mmc_cmd13()) {
+			return false;
+		}
+	}
+	// Reinitialize the slot with the new speed
+	sd_mmc_configure_slot();
+	return true;
+}
+
+/**
+ * \brief Initialize the MMC card in SPI mode.
+ *
+ * \note
+ * This function runs the initialization procedure and the identification
+ * process, then it sets the SD/MMC card in transfer state.
+ * At last, it will automaticly enable maximum bus width and transfer speed.
+ *
+ * \return true if success, otherwise false
+ */
+static bool sd_mmc_spi_install_mmc(void)
+{
+	uint8_t b_authorize_high_speed;
+
+	// CMD0 - Reset all cards to idle state.
+	if (!driver_send_cmd(sd_mmc_hal, SDMMC_SPI_CMD0_GO_IDLE_STATE, 0)) {
+		return false;
+	}
+
+	if (!mmc_spi_op_cond()) {
+		return false;
+	}
+
+	// Disable CRC check for SPI mode
+	if (!driver_send_cmd(sd_mmc_hal, SDMMC_SPI_CMD59_CRC_ON_OFF, 0)) {
+		return false;
+	}
+	// Get the Card-Specific Data
+	if (!sd_mmc_cmd9_spi()) {
+		return false;
+	}
+	mmc_decode_csd();
+	// For MMC 4.0 Higher version
+	if (sd_mmc_card->version >= CARD_VER_MMC_4) {
+		// Get EXT_CSD
+		if (!mmc_cmd8(&b_authorize_high_speed)) {
+			return false;
+		}
+	}
+	// Set default block size
+	if (!driver_send_cmd(sd_mmc_hal, SDMMC_CMD16_SET_BLOCKLEN, SD_MMC_BLOCK_SIZE)) {
+		return false;
+	}
+	// Check communication
+	if (!sd_mmc_cmd13()) {
+		return false;
+	}
+	// Reinitialize the slot with the new speed
+	sd_mmc_configure_slot();
+	return true;
+}
+
+#if CONF_MMC_SUPPORT
+/**
+ * \brief Sends operation condition command and read OCR (MCI only)
+ * - CMD1 sends operation condition command
+ * - CMD1 reads OCR
+ *
+ * \return true if success, otherwise false
+ */
+static bool mmc_mci_op_cond(void)
+{
+	uint32_t retry, resp;
+
+	/*
+	 * Timeout 1s = 400KHz / ((6+6)*8) cylces = 4200 retry
+	 * 6 = cmd byte size
+	 * 6 = response byte size
+	 */
+	retry = 4200;
+	do {
+		if (!driver_send_cmd(sd_mmc_hal, MMC_MCI_CMD1_SEND_OP_COND, SD_MMC_VOLTAGE_SUPPORT | OCR_ACCESS_MODE_SECTOR)) {
+			return false;
+		}
+		/* Check busy flag */
+		resp = driver_get_response(sd_mmc_hal);
+		if (resp & OCR_POWER_UP_BUSY) {
+			/* Check OCR value */
+			if ((resp & OCR_ACCESS_MODE_MASK) == OCR_ACCESS_MODE_SECTOR) {
+				sd_mmc_card->type |= CARD_TYPE_HC;
+			}
+			break;
+		}
+		if (retry-- == 0) {
+			return false;
+		}
+	} while (1);
+	return true;
+}
+#endif
+
+/**
+ * \brief Ask to all cards to send their operations conditions (MCI only).
+ * - ACMD41 sends operation condition command.
+ * - ACMD41 reads OCR
+ *
+ * \param v2   Shall be 1 if it is a SD card V2
+ *
+ * \return true if success, otherwise false
+ */
+static bool sd_mci_op_cond(uint8_t v2)
+{
+	uint32_t arg, retry, resp;
+
+	/*
+	 * Timeout 1s = 400KHz / ((6+6+6+6)*8) cylces = 2100 retry
+	 * 6 = cmd byte size
+	 * 6 = response byte size
+	 * 6 = cmd byte size
+	 * 6 = response byte size
+	 */
+	retry = 2100;
+	do {
+		/* CMD55 - Indicate to the card that the next command is an
+		 * application specific command rather than a standard command.*/
+		if (!driver_send_cmd(sd_mmc_hal, SDMMC_CMD55_APP_CMD, 0)) {
+			return false;
+		}
+
+		/* (ACMD41) Sends host OCR register */
+		arg = SD_MMC_VOLTAGE_SUPPORT;
+		if (v2) {
+			arg |= SD_ACMD41_HCS;
+		}
+		/* Check response */
+		if (!driver_send_cmd(sd_mmc_hal, SD_MCI_ACMD41_SD_SEND_OP_COND, arg)) {
+			return false;
+		}
+		resp = driver_get_response(sd_mmc_hal);
+		if (resp & OCR_POWER_UP_BUSY) {
+			/* Card is ready */
+			if ((resp & OCR_CCS) != 0) {
+				sd_mmc_card->type |= CARD_TYPE_HC;
+			}
+			break;
+		}
+		if (retry-- == 0) {
+			return false;
+		}
+	} while (1);
+	return true;
+}
+
+#if (CONF_SDIO_SUPPORT == 1)
+/**
+ * \brief Try to get the SDIO card's operating condition
+ * - CMD5 to read OCR NF field
+ * - CMD5 to wait OCR power up busy
+ * - CMD5 to read OCR MP field
+ *   sd_mmc_card->type is updated
+ *
+ * \return true if success, otherwise false
+ */
+static bool sdio_op_cond(void)
+{
+	uint32_t resp;
+
+	/* CMD5 - SDIO send operation condition (OCR) command. */
+	if (!driver_send_cmd(sd_mmc_hal, SDIO_CMD5_SEND_OP_COND, 0)) {
+		return true; /* No error but card type not updated */
+	}
+	resp = driver_get_response(sd_mmc_hal);
+	if ((resp & OCR_SDIO_NF) == 0) {
+		return true; /* No error but card type not updated */
+	}
+
+	/*
+	 * Wait card ready
+	 * Timeout 1s = 400KHz / ((6+4)*8) cylces = 5000 retry
+	 * 6 = cmd byte size
+	 * 4(SPI) 6(MCI) = response byte size
+	 */
+	uint32_t cmd5_retry = 5000;
+	while (1) {
+		/* CMD5 - SDIO send operation condition (OCR) command.*/
+		if (!driver_send_cmd(sd_mmc_hal, SDIO_CMD5_SEND_OP_COND, resp & SD_MMC_VOLTAGE_SUPPORT)) {
+			return false;
+		}
+		resp = driver_get_response(sd_mmc_hal);
+		if ((resp & OCR_POWER_UP_BUSY) == OCR_POWER_UP_BUSY) {
+			break;
+		}
+		if (cmd5_retry-- == 0) {
+			return false;
+		}
+	}
+	/* Update card type at the end of busy */
+	if ((resp & OCR_SDIO_MP) > 0) {
+		sd_mmc_card->type = CARD_TYPE_SD_COMBO;
+	} else {
+		sd_mmc_card->type = CARD_TYPE_SDIO;
+	}
+	return true; /* No error and card type updated with SDIO type */
+}
+
+/**
+ * \brief Get SDIO max transfer speed in Hz.
+ * - CMD53 reads CIS area address in CCCR area.
+ * - Nx CMD53 search Fun0 tuple in CIS area
+ * - CMD53 reads TPLFE_MAX_TRAN_SPEED in Fun0 tuple
+ * - Compute maximum speed of SDIO
+ *   and update sd_mmc_card->clock
+ *
+ * \return true if success, otherwise false
+ */
+static bool sdio_get_max_speed(void)
+{
+	uint32_t addr_new, addr_old;
+	uint8_t  buf[6];
+	uint32_t unit;
+	uint32_t mul;
+	uint8_t  tplfe_max_tran_speed, i;
+	uint8_t  addr_cis[4];
+
+	/* Read CIS area address in CCCR area */
+	addr_old = SDIO_CCCR_CIS_PTR;
+	for (i = 0; i < 4; i++) {
+		sdio_cmd52(SDIO_CMD52_READ_FLAG, SDIO_CIA, addr_old, 0, &addr_cis[i]);
+		addr_old++;
+	}
+	addr_old = addr_cis[0] + (addr_cis[1] << 8) + (addr_cis[2] << 16) + (addr_cis[3] << 24);
+	addr_new = addr_old;
+
+	while (1) {
+		/* Read a sample of CIA area */
+		for (i = 0; i < 3; i++) {
+			sdio_cmd52(SDIO_CMD52_READ_FLAG, SDIO_CIA, addr_new, 0, &buf[i]);
+			addr_new++;
+		}
+		if (buf[0] == SDIO_CISTPL_END) {
+			return false; /* Tuple error */
+		}
+		if (buf[0] == SDIO_CISTPL_FUNCE && buf[2] == 0x00) {
+			break; /* Fun0 tuple found */
+		}
+		if (buf[1] == 0) {
+			return false; /* Tuple error */
+		}
+		/* Next address */
+		addr_new += buf[1] - 1;
+		if (addr_new > (addr_old + 256)) {
+			return false; /* Outoff CIS area */
+		}
+	}
+
+	/* Read all Fun0 tuple fields: fn0_blk_siz & max_tran_speed */
+	addr_new -= 3;
+	for (i = 0; i < 6; i++) {
+		sdio_cmd52(SDIO_CMD52_READ_FLAG, SDIO_CIA, addr_new, 0, &buf[i]);
+		addr_new++;
+	}
+
+	tplfe_max_tran_speed = buf[5];
+	if (tplfe_max_tran_speed > 0x32) {
+		/* Error on SDIO register, the high speed is not activated
+		 * and the clock can not be more than 25MHz.
+		 * This error is present on specific SDIO card
+		 * (H&D wireless card - HDG104 WiFi SIP).
+		 */
+		tplfe_max_tran_speed = 0x32; /* 25Mhz */
+	}
+
+	/* Decode transfer speed in Hz.*/
+	unit               = sd_mmc_trans_units[tplfe_max_tran_speed & 0x7];
+	mul                = sd_trans_multipliers[(tplfe_max_tran_speed >> 3) & 0xF];
+	sd_mmc_card->clock = unit * mul * 1000;
+	/**
+	 * Note: A combo card shall be a Full-Speed SDIO card
+	 * which supports upto 25MHz.
+	 * A SDIO card alone can be:
+	 * - a Low-Speed SDIO card which supports 400Khz minimum
+	 * - a Full-Speed SDIO card which supports upto 25MHz
+	 */
+	return true;
+}
+
+/**
+ * \brief CMD52 for SDIO - Switches the bus width mode to 4
+ *
+ * \note sd_mmc_card->bus_width is updated.
+ *
+ * \return true if success, otherwise false
+ */
+static bool sdio_cmd52_set_bus_width(void)
+{
+	/**
+	 * A SD memory card always supports bus 4bit
+	 * A SD COMBO card always supports bus 4bit
+	 * A SDIO Full-Speed alone always supports 4bit
+	 * A SDIO Low-Speed alone can supports 4bit (Optional)
+	 */
+	uint8_t u8_value;
+
+	/* Check 4bit support in 4BLS of "Card Capability" register */
+	if (!sdio_cmd52(SDIO_CMD52_READ_FLAG, SDIO_CIA, SDIO_CCCR_CAP, 0, &u8_value)) {
+		return false;
+	}
+	if ((u8_value & SDIO_CAP_4BLS) != SDIO_CAP_4BLS) {
+		/* No supported, it is not a protocol error */
+		return true;
+	}
+	/* HS mode possible, then enable */
+	u8_value = SDIO_BUSWIDTH_4B;
+	if (!sdio_cmd52(SDIO_CMD52_WRITE_FLAG, SDIO_CIA, SDIO_CCCR_BUS_CTRL, 1, &u8_value)) {
+		return false;
+	}
+	sd_mmc_card->bus_width = 4;
+	return true;
+}
+
+/**
+ * \brief CMD52 for SDIO - Enable the high speed mode
+ *
+ * \note sd_mmc_card->high_speed is updated.
+ * \note sd_mmc_card->clock is updated.
+ *
+ * \return true if success, otherwise false
+ */
+static bool sdio_cmd52_set_high_speed(void)
+{
+	uint8_t u8_value;
+
+	/* Check CIA.HS */
+	if (!sdio_cmd52(SDIO_CMD52_READ_FLAG, SDIO_CIA, SDIO_CCCR_HS, 0, &u8_value)) {
+		return false;
+	}
+	if ((u8_value & SDIO_SHS) != SDIO_SHS) {
+		/* No supported, it is not a protocol error */
+		return true;
+	}
+	/* HS mode possible, then enable */
+	u8_value = SDIO_EHS;
+	if (!sdio_cmd52(SDIO_CMD52_WRITE_FLAG, SDIO_CIA, SDIO_CCCR_HS, 1, &u8_value)) {
+		return false;
+	}
+	sd_mmc_card->high_speed = 1;
+	sd_mmc_card->clock *= 2;
+	return true;
+}
+
+#else
+static bool sdio_op_cond(void)
+{
+	return true; /* No error but card type not updated */
+}
+static bool sdio_get_max_speed(void)
+{
+	return false;
+}
+static bool sdio_cmd52_set_bus_width(void)
+{
+	return false;
+}
+static bool sdio_cmd52_set_high_speed(void)
+{
+	return false;
+}
+#endif
+
+/**
+ * \brief CMD6 for SD - Switch card in high speed mode
+ *
+ * \note CMD6 for SD is valid under the "trans" state.
+ * \note sd_mmc_card->high_speed is updated.
+ * \note sd_mmc_card->clock is updated.
+ *
+ * \return true if success, otherwise false
+ */
+static bool sd_cm6_set_high_speed(void)
+{
+	uint8_t switch_status[SD_SW_STATUS_BSIZE] = {0};
+
+	if (!driver_adtc_start(sd_mmc_hal,
+	                       SD_CMD6_SWITCH_FUNC,
+	                       SD_CMD6_MODE_SWITCH | SD_CMD6_GRP6_NO_INFLUENCE | SD_CMD6_GRP5_NO_INFLUENCE
+	                           | SD_CMD6_GRP4_NO_INFLUENCE | SD_CMD6_GRP3_NO_INFLUENCE | SD_CMD6_GRP2_DEFAULT
+	                           | SD_CMD6_GRP1_HIGH_SPEED,
+	                       SD_SW_STATUS_BSIZE,
+	                       1,
+	                       true)) {
+		return false;
+	}
+	if (!driver_start_read_blocks(sd_mmc_hal, switch_status, 1)) {
+		return false;
+	}
+	if (!driver_wait_end_of_read_blocks(sd_mmc_hal)) {
+		return false;
+	}
+
+	if (driver_get_response(sd_mmc_hal) & CARD_STATUS_SWITCH_ERROR) {
+		return false;
+	}
+	if (SD_SW_STATUS_FUN_GRP1_RC(switch_status) == SD_SW_STATUS_FUN_GRP_RC_ERROR) {
+		/* No supported, it is not a protocol error */
+		return true;
+	}
+	if (SD_SW_STATUS_FUN_GRP1_BUSY(switch_status)) {
+		return false;
+	}
+	/* CMD6 function switching period is within 8 clocks
+	 * after the end bit of status data.*/
+	driver_send_clock(sd_mmc_hal);
+	sd_mmc_card->high_speed = 1;
+	sd_mmc_card->clock *= 2;
+	return true;
+}
+
+#if CONF_MMC_SUPPORT
+
+/**
+ * \brief CMD6 for MMC - Switches the bus width mode
+ *
+ * \note CMD6 is valid under the "trans" state.
+ * \note sd_mmc_card->bus_width is updated.
+ *
+ * \param bus_width   Bus width to set
+ *
+ * \return true if success, otherwise false
+ */
+static bool mmc_cmd6_set_bus_width(uint8_t bus_width)
+{
+	uint32_t arg;
+
+	switch (bus_width) {
+	case 8:
+		arg = MMC_CMD6_ACCESS_SET_BITS | MMC_CMD6_INDEX_BUS_WIDTH | MMC_CMD6_VALUE_BUS_WIDTH_8BIT;
+		break;
+	case 4:
+		arg = MMC_CMD6_ACCESS_SET_BITS | MMC_CMD6_INDEX_BUS_WIDTH | MMC_CMD6_VALUE_BUS_WIDTH_4BIT;
+		break;
+	default:
+		arg = MMC_CMD6_ACCESS_SET_BITS | MMC_CMD6_INDEX_BUS_WIDTH | MMC_CMD6_VALUE_BUS_WIDTH_1BIT;
+		break;
+	}
+	if (!driver_send_cmd(sd_mmc_hal, MMC_CMD6_SWITCH, arg)) {
+		return false;
+	}
+	if (driver_get_response(sd_mmc_hal) & CARD_STATUS_SWITCH_ERROR) {
+		/* No supported, it is not a protocol error */
+		return false;
+	}
+	sd_mmc_card->bus_width = bus_width;
+	return true;
+}
+
+/**
+ * \brief CMD6 for MMC - Switches in high speed mode
+ *
+ * \note CMD6 is valid under the "trans" state.
+ * \note sd_mmc_card->high_speed is updated.
+ * \note sd_mmc_card->clock is updated.
+ *
+ * \return true if success, otherwise false
+ */
+static bool mmc_cmd6_set_high_speed(void)
+{
+	if (!driver_send_cmd(sd_mmc_hal,
+	                     MMC_CMD6_SWITCH,
+	                     MMC_CMD6_ACCESS_WRITE_BYTE | MMC_CMD6_INDEX_HS_TIMING | MMC_CMD6_VALUE_HS_TIMING_ENABLE)) {
+		return false;
+	}
+	if (driver_get_response(sd_mmc_hal) & CARD_STATUS_SWITCH_ERROR) {
+		/* No supported, it is not a protocol error */
+		return false;
+	}
+	sd_mmc_card->high_speed = 1;
+	sd_mmc_card->clock      = 52000000lu;
+	return true;
+}
+#endif
+
+/**
+ * \brief CMD8 for SD card - Send Interface Condition Command.
+ *
+ * \note
+ * Send SD Memory Card interface condition, which includes host supply
+ * voltage information and asks the card whether card supports voltage.
+ * Should be performed at initialization time to detect the card type.
+ *
+ * \param v2 Pointer to v2 flag to update
+ *
+ * \return true if success, otherwise false
+ *         with a update of \ref sd_mmc_err.
+ */
+static bool sd_cmd8(uint8_t *v2)
+{
+	uint32_t resp;
+
+	*v2 = 0;
+	/* Test for SD version 2 */
+	if (!driver_send_cmd(sd_mmc_hal, SD_CMD8_SEND_IF_COND, SD_CMD8_PATTERN | SD_CMD8_HIGH_VOLTAGE)) {
+		return true; /* It is not a V2 */
+	}
+	/* Check R7 response */
+	resp = driver_get_response(sd_mmc_hal);
+	if (resp == 0xFFFFFFFF) {
+		/* No compliance R7 value */
+		return true; /* It is not a V2 */
+	}
+	if ((resp & (SD_CMD8_MASK_PATTERN | SD_CMD8_MASK_VOLTAGE)) != (SD_CMD8_PATTERN | SD_CMD8_HIGH_VOLTAGE)) {
+		return false;
+	}
+	*v2 = 1;
+	return true;
+}
+
+#if CONF_MMC_SUPPORT
+/**
+ * \brief CMD8 - The card sends its EXT_CSD register as a block of data.
+ *
+ * \param b_authorize_high_speed Pointer to update with the high speed
+ * support information
+ *
+ * \return true if success, otherwise false
+ */
+static bool mmc_cmd8(uint8_t *b_authorize_high_speed)
+{
+	uint16_t i;
+	uint32_t ext_csd;
+	uint32_t sec_count;
+
+	if (!driver_adtc_start(sd_mmc_hal, MMC_CMD8_SEND_EXT_CSD, 0, EXT_CSD_BSIZE, 1, false)) {
+		return false;
+	}
+	/* Read and decode Extended Extended CSD
+	 * Note: The read access is done in byte to avoid a buffer
+	 * of EXT_CSD_BSIZE Byte in stack.*/
+
+	/* Read card type */
+	for (i = 0; i < (EXT_CSD_CARD_TYPE_INDEX + 4) / 4; i++) {
+		if (!driver_read_word(sd_mmc_hal, &ext_csd)) {
+			return false;
+		}
+	}
+	*b_authorize_high_speed = (ext_csd >> ((EXT_CSD_CARD_TYPE_INDEX % 4) * 8)) & MMC_CTYPE_52MHZ;
+
+	if (MMC_CSD_C_SIZE(sd_mmc_card->csd) == 0xFFF) {
+		/* For high capacity SD/MMC card,
+		 * memory capacity = SEC_COUNT * 512 byte */
+		for (; i < (EXT_CSD_SEC_COUNT_INDEX + 4) / 4; i++) {
+			if (!driver_read_word(sd_mmc_hal, &sec_count)) {
+				return false;
+			}
+		}
+		sd_mmc_card->capacity = sec_count / 2;
+	}
+	for (; i < EXT_CSD_BSIZE / 4; i++) {
+		if (!driver_read_word(sd_mmc_hal, &sec_count)) {
+			return false;
+		}
+	}
+	return true;
+}
+
+#endif
+
+/**
+ * \brief CMD9: Addressed card sends its card-specific
+ * data (CSD) on the CMD line mci.
+ *
+ * \return true if success, otherwise false
+ */
+static bool sd_mmc_cmd9_mci(void)
+{
+	if (!driver_send_cmd(sd_mmc_hal, SDMMC_MCI_CMD9_SEND_CSD, (uint32_t)sd_mmc_card->rca << 16)) {
+		return false;
+	}
+	driver_get_response_128(sd_mmc_hal, sd_mmc_card->csd);
+	return true;
+}
+
+#if CONF_MMC_SUPPORT
+/**
+ * \brief Decodes MMC CSD register
+ */
+static void mmc_decode_csd(void)
+{
+	uint32_t unit;
+	uint32_t mul;
+	uint32_t tran_speed;
+
+	/* Get MMC System Specification version supported by the card */
+	switch (MMC_CSD_SPEC_VERS(sd_mmc_card->csd)) {
+	default:
+	case 0:
+		sd_mmc_card->version = CARD_VER_MMC_1_2;
+		break;
+
+	case 1:
+		sd_mmc_card->version = CARD_VER_MMC_1_4;
+		break;
+
+	case 2:
+		sd_mmc_card->version = CARD_VER_MMC_2_2;
+		break;
+
+	case 3:
+		sd_mmc_card->version = CARD_VER_MMC_3;
+		break;
+
+	case 4:
+		sd_mmc_card->version = CARD_VER_MMC_4;
+		break;
+	}
+
+	/* Get MMC memory max transfer speed in Hz.*/
+	tran_speed         = CSD_TRAN_SPEED(sd_mmc_card->csd);
+	unit               = sd_mmc_trans_units[tran_speed & 0x7];
+	mul                = mmc_trans_multipliers[(tran_speed >> 3) & 0xF];
+	sd_mmc_card->clock = unit * mul * 1000;
+
+	/*
+	 * Get card capacity.
+	 * ----------------------------------------------------
+	 * For normal SD/MMC card:
+	 * memory capacity = BLOCKNR * BLOCK_LEN
+	 * Where
+	 * BLOCKNR = (C_SIZE+1) * MULT
+	 * MULT = 2 ^ (C_SIZE_MULT+2)       (C_SIZE_MULT < 8)
+	 * BLOCK_LEN = 2 ^ READ_BL_LEN      (READ_BL_LEN < 12)
+	 * ----------------------------------------------------
+	 * For high capacity SD/MMC card:
+	 * memory capacity = SEC_COUNT * 512 byte
+	 */
+	if (MMC_CSD_C_SIZE(sd_mmc_card->csd) != 0xFFF) {
+		uint32_t blocknr
+		    = ((MMC_CSD_C_SIZE(sd_mmc_card->csd) + 1) * (1 << (MMC_CSD_C_SIZE_MULT(sd_mmc_card->csd) + 2)));
+		sd_mmc_card->capacity = blocknr * (1 << MMC_CSD_READ_BL_LEN(sd_mmc_card->csd)) / 1024;
+	}
+}
+#endif
+
+/**
+ * \brief Decodes SD CSD register
+ */
+static void sd_decode_csd(void)
+{
+	uint32_t unit;
+	uint32_t mul;
+	uint32_t tran_speed;
+
+	/* Get SD memory maximum transfer speed in Hz. */
+	tran_speed         = CSD_TRAN_SPEED(sd_mmc_card->csd);
+	unit               = sd_mmc_trans_units[tran_speed & 0x7];
+	mul                = sd_trans_multipliers[(tran_speed >> 3) & 0xF];
+	sd_mmc_card->clock = unit * mul * 1000;
+
+	/*
+	 * Get card capacity.
+	 * ----------------------------------------------------
+	 * For normal SD/MMC card:
+	 * memory capacity = BLOCKNR * BLOCK_LEN
+	 * Where
+	 * BLOCKNR = (C_SIZE+1) * MULT
+	 * MULT = 2 ^ (C_SIZE_MULT+2)       (C_SIZE_MULT < 8)
+	 * BLOCK_LEN = 2 ^ READ_BL_LEN      (READ_BL_LEN < 12)
+	 * ----------------------------------------------------
+	 * For high capacity SD card:
+	 * memory capacity = (C_SIZE+1) * 512K byte
+	 */
+	if (CSD_STRUCTURE_VERSION(sd_mmc_card->csd) >= SD_CSD_VER_2_0) {
+		sd_mmc_card->capacity = (SD_CSD_2_0_C_SIZE(sd_mmc_card->csd) + 1) * 512;
+	} else {
+		uint32_t blocknr
+		    = ((SD_CSD_1_0_C_SIZE(sd_mmc_card->csd) + 1) * (1 << (SD_CSD_1_0_C_SIZE_MULT(sd_mmc_card->csd) + 2)));
+		sd_mmc_card->capacity = blocknr * (1 << SD_CSD_1_0_READ_BL_LEN(sd_mmc_card->csd)) / 1024;
+	}
+}
+
+/**
+ * \brief CMD13 - Addressed card sends its status register.
+ * This function waits the clear of the busy flag
+ *
+ * \return true if success, otherwise false
+ */
+static bool sd_mmc_cmd13(void)
+{
+	uint32_t nec_timeout;
+
+	/* Wait for data ready status.
+	 * Nec timing: 0 to unlimited
+	 * However a timeout is used.
+	 * 200 000 * 8 cycles
+	 */
+	nec_timeout = 200000;
+	do {
+		if (!driver_send_cmd(sd_mmc_hal, SDMMC_MCI_CMD13_SEND_STATUS, (uint32_t)sd_mmc_card->rca << 16)) {
+			return false;
+		}
+		/* Check busy flag */
+		if (driver_get_response(sd_mmc_hal) & CARD_STATUS_READY_FOR_DATA) {
+			break;
+		}
+		if (nec_timeout-- == 0) {
+			return false;
+		}
+	} while (1);
+
+	return true;
+}
+
+#if (CONF_SDIO_SUPPORT == 1)
+/**
+ * \brief CMD52 - SDIO IO_RW_DIRECT command
+ *
+ * \param rw_flag   Direction, 1:write, 0:read.
+ * \param func_nb   Number of the function.
+ * \param rd_after_wr Read after Write flag.
+ * \param reg_addr  register address.
+ * \param io_data   Pointer to input argument and response buffer.
+ *
+ * \return true if success, otherwise false
+ */
+static bool sdio_cmd52(uint8_t rw_flag, uint8_t func_nb, uint32_t reg_addr, uint8_t rd_after_wr, uint8_t *io_data)
+{
+	assert(io_data != NULL, ">>>");
+	if (!driver_send_cmd(sd_mmc_hal,
+	                     SDIO_CMD52_IO_RW_DIRECT,
+	                     ((uint32_t)*io_data << SDIO_CMD52_WR_DATA) | ((uint32_t)rw_flag << SDIO_CMD52_RW_FLAG)
+	                         | ((uint32_t)func_nb << SDIO_CMD52_FUNCTION_NUM)
+	                         | ((uint32_t)rd_after_wr << SDIO_CMD52_RAW_FLAG)
+	                         | ((uint32_t)reg_addr << SDIO_CMD52_REG_ADRR))) {
+		return false;
+	}
+	*io_data = driver_get_response(sd_mmc_hal) & 0xFF;
+	return true;
+}
+
+/**
+ * \brief CMD53 - SDIO IO_RW_EXTENDED command
+ * This implementation support only the SDIO multi-byte transfer mode which is
+ * similar to the single block transfer on memory.
+ * Note: The SDIO block transfer mode is optional for SDIO card.
+ *
+ * \param rw_flag   Direction, 1:write, 0:read.
+ * \param func_nb   Number of the function.
+ * \param reg_addr  Register address.
+ * \param inc_addr  1:Incrementing address, 0: fixed.
+ * \param size      Transfer data size.
+ * \param access_block  true, if the block access (DMA) is used
+ *
+ * \return true if success, otherwise false
+ */
+static bool sdio_cmd53(uint8_t rw_flag, uint8_t func_nb, uint32_t reg_addr, uint8_t inc_addr, uint32_t size,
+                       bool access_block)
+{
+	assert(size != 0, ">>>");
+	assert(size <= 512, ">>>");
+
+	return driver_adtc_start(
+	    sd_mmc_hal,
+	    (rw_flag == SDIO_CMD53_READ_FLAG) ? SDIO_CMD53_IO_R_BYTE_EXTENDED : SDIO_CMD53_IO_W_BYTE_EXTENDED,
+	    ((size % 512) << SDIO_CMD53_COUNT) | ((uint32_t)reg_addr << SDIO_CMD53_REG_ADDR)
+	        | ((uint32_t)inc_addr << SDIO_CMD53_OP_CODE) | ((uint32_t)0 << SDIO_CMD53_BLOCK_MODE)
+	        | ((uint32_t)func_nb << SDIO_CMD53_FUNCTION_NUM) | ((uint32_t)rw_flag << SDIO_CMD53_RW_FLAG),
+	    size,
+	    1,
+	    access_block);
+}
+#endif
+
+/**
+ * \brief ACMD6 - Define the data bus width to 4 bits bus
+ *
+ * \return true if success, otherwise false
+ */
+static bool sd_acmd6(void)
+{
+	/* CMD55 - Indicate to the card that the next command is an
+	 * application specific command rather than a standard command.*/
+	if (!driver_send_cmd(sd_mmc_hal, SDMMC_CMD55_APP_CMD, (uint32_t)sd_mmc_card->rca << 16)) {
+		return false;
+	}
+	/* 10b = 4 bits bus */
+	if (!driver_send_cmd(sd_mmc_hal, SD_ACMD6_SET_BUS_WIDTH, 0x2)) {
+		return false;
+	}
+	sd_mmc_card->bus_width = 4;
+	return true;
+}
+
+/**
+ * \brief ACMD51 - Read the SD Configuration Register.
+ *
+ * \note
+ * SD Card Configuration Register (SCR) provides information on the SD Memory
+ * Card's special features that were configured into the given card. The size
+ * of SCR register is 64 bits.
+ *
+ *
+ * \return true if success, otherwise false
+ */
+static bool sd_acmd51(void)
+{
+	uint8_t scr[SD_SCR_REG_BSIZE];
+
+	/* CMD55 - Indicate to the card that the next command is an
+	 * application specific command rather than a standard command.*/
+	if (!driver_send_cmd(sd_mmc_hal, SDMMC_CMD55_APP_CMD, (uint32_t)sd_mmc_card->rca << 16)) {
+		return false;
+	}
+	if (!driver_adtc_start(sd_mmc_hal, SD_ACMD51_SEND_SCR, 0, SD_SCR_REG_BSIZE, 1, true)) {
+		return false;
+	}
+	if (!driver_start_read_blocks(sd_mmc_hal, scr, 1)) {
+		return false;
+	}
+	if (!driver_wait_end_of_read_blocks(sd_mmc_hal)) {
+		return false;
+	}
+
+	/* Get SD Memory Card - Spec. Version */
+	switch (SD_SCR_SD_SPEC(scr)) {
+	case SD_SCR_SD_SPEC_1_0_01:
+		sd_mmc_card->version = CARD_VER_SD_1_0;
+		break;
+
+	case SD_SCR_SD_SPEC_1_10:
+		sd_mmc_card->version = CARD_VER_SD_1_10;
+		break;
+
+	case SD_SCR_SD_SPEC_2_00:
+		if (SD_SCR_SD_SPEC3(scr) == SD_SCR_SD_SPEC_3_00) {
+			sd_mmc_card->version = CARD_VER_SD_3_0;
+		} else {
+			sd_mmc_card->version = CARD_VER_SD_2_0;
+		}
+		break;
+
+	default:
+		sd_mmc_card->version = CARD_VER_SD_1_0;
+		break;
+	}
+	return true;
+}
+
+/**
+ * \brief Select a card slot and initialize the associated driver
+ *
+ * \param slot  Card slot number
+ *
+ * \retval SD_MMC_ERR_SLOT     Wrong slot number
+ * \retval SD_MMC_ERR_NO_CARD  No card present on slot
+ * \retval SD_MMC_ERR_UNUSABLE Unusable card
+ * \retval SD_MMC_INIT_ONGOING Card initialization requested
+ * \retval SD_MMC_OK           Card present
+ */
+static sd_mmc_err_t sd_mmc_select_slot(uint8_t slot)
+{
+	if (slot >= CONF_SD_MMC_MEM_CNT) {
+		return SD_MMC_ERR_SLOT;
+	}
+
+	if (_cd && _cd[slot].pin != -1) {
+		/** Card Detect pins */
+		if (gpio_get_pin_level(_cd[slot].pin) != _cd[slot].val) {
+			if (sd_mmc_cards[slot].state == SD_MMC_CARD_STATE_DEBOUNCE) {
+				SD_MMC_STOP_TIMEOUT();
+			}
+			sd_mmc_cards[slot].state = SD_MMC_CARD_STATE_NO_CARD;
+			return SD_MMC_ERR_NO_CARD;
+		}
+		if (sd_mmc_cards[slot].state == SD_MMC_CARD_STATE_NO_CARD) {
+			/* A card plug on going, but this is not initialized */
+			sd_mmc_cards[slot].state = SD_MMC_CARD_STATE_DEBOUNCE;
+			/* Debounce + Power On Setup */
+			SD_MMC_START_TIMEOUT();
+			return SD_MMC_ERR_NO_CARD;
+		}
+		if (sd_mmc_cards[slot].state == SD_MMC_CARD_STATE_DEBOUNCE) {
+			if (!SD_MMC_IS_TIMEOUT()) {
+				/* Debounce on going */
+				return SD_MMC_ERR_NO_CARD;
+			}
+			/* Card is not initialized */
+			sd_mmc_cards[slot].state = SD_MMC_CARD_STATE_INIT;
+			/* Set 1-bit bus width and low clock for initialization */
+			sd_mmc_cards[slot].clock      = SDMMC_CLOCK_INIT;
+			sd_mmc_cards[slot].bus_width  = 1;
+			sd_mmc_cards[slot].high_speed = 0;
+		}
+		if (sd_mmc_cards[slot].state == SD_MMC_CARD_STATE_UNUSABLE) {
+			return SD_MMC_ERR_UNUSABLE;
+		}
+	} else {
+		/* No pin card detection, then always try to install it */
+		if ((sd_mmc_cards[slot].state == SD_MMC_CARD_STATE_NO_CARD)
+		    || (sd_mmc_cards[slot].state == SD_MMC_CARD_STATE_UNUSABLE)) {
+			/* Card is not initialized */
+			sd_mmc_cards[slot].state = SD_MMC_CARD_STATE_INIT;
+			/* Set 1-bit bus width and low clock for initialization */
+			sd_mmc_cards[slot].clock      = SDMMC_CLOCK_INIT;
+			sd_mmc_cards[slot].bus_width  = 1;
+			sd_mmc_cards[slot].high_speed = 0;
+		}
+	}
+
+	assert(!(sd_mmc_slot_sel != slot && sd_mmc_nb_block_remaining != 0), ">>>");
+
+	/* Initialize interface */
+	sd_mmc_slot_sel = slot;
+	sd_mmc_card     = &sd_mmc_cards[slot];
+	sd_mmc_configure_slot();
+	return (sd_mmc_cards[slot].state == SD_MMC_CARD_STATE_INIT) ? SD_MMC_INIT_ONGOING : SD_MMC_OK;
+}
+
+/**
+ * \brief Configures the driver with the selected card configuration
+ */
+static void sd_mmc_configure_slot(void)
+{
+	driver_select_device(
+	    sd_mmc_hal, sd_mmc_slot_sel, sd_mmc_card->clock, sd_mmc_card->bus_width, sd_mmc_card->high_speed);
+}
+
+
+
+/**
+ * \brief Deselect the current card slot
+ */
+static void sd_mmc_deselect_slot(void)
+{
+	if (sd_mmc_slot_sel < CONF_SD_MMC_MEM_CNT) {
+		driver_deselect_device(sd_mmc_hal, sd_mmc_slot_sel);
+	}
+}
+
+/**
+ * \brief Initialize the SD card in MCI mode.
+ *
+ * \note
+ * This function runs the initialization procedure and the identification
+ * process, then it sets the SD/MMC card in transfer state.
+ * At last, it will automaticly enable maximum bus width and transfer speed.
+ *
+ * \return true if success, otherwise false
+ */
+static bool sd_mmc_mci_card_init(void)
+{
+	uint8_t v2 = 0;
+#if (CONF_SDIO_SUPPORT == 1)
+	uint8_t data = 0x08;
+#endif
+
+	/* In first, try to install SD/SDIO card */
+	sd_mmc_card->type    = CARD_TYPE_SD;
+	sd_mmc_card->version = CARD_VER_UNKNOWN;
+	sd_mmc_card->rca     = 0;
+
+	/* Card need of 74 cycles clock minimum to start */
+	driver_send_clock(sd_mmc_hal);
+
+#if (CONF_SDIO_SUPPORT == 1)
+	/* CMD52 Reset SDIO */
+	sdio_cmd52(SDIO_CMD52_WRITE_FLAG, SDIO_CIA, SDIO_CCCR_IOA, 0, &data);
+#endif
+
+	/* CMD0 - Reset all cards to idle state.*/
+	if (!driver_send_cmd(sd_mmc_hal, SDMMC_MCI_CMD0_GO_IDLE_STATE, 0)) {
+		return false;
+	}
+	if (!sd_cmd8(&v2)) {
+		return false;
+	}
+	/* Try to get the SDIO card's operating condition */
+	if (!sdio_op_cond()) {
+		return false;
+	}
+
+	if (sd_mmc_card->type & CARD_TYPE_SD) {
+		/* Try to get the SD card's operating condition */
+		if (!sd_mci_op_cond(v2)) {
+		/* It is not a SD card */
+#if CONF_MMC_SUPPORT
+			sd_mmc_card->type = CARD_TYPE_MMC;
+			return sd_mmc_mci_install_mmc();
+#else
+			sd_mmc_card->type = CARD_TYPE_UNKNOWN;
+			return false;
+#endif
+		}
+	}
+
+	if (sd_mmc_card->type & CARD_TYPE_SD) {
+		/* SD MEMORY, Put the Card in Identify Mode
+		 * Note: The CID is not used in this stack */
+		if (!driver_send_cmd(sd_mmc_hal, SDMMC_CMD2_ALL_SEND_CID, 0)) {
+			return false;
+		}
+	}
+	/* Ask the card to publish a new relative address (RCA).*/
+	if (!driver_send_cmd(sd_mmc_hal, SD_CMD3_SEND_RELATIVE_ADDR, 0)) {
+		return false;
+	}
+	sd_mmc_card->rca = (driver_get_response(sd_mmc_hal) >> 16) & 0xFFFF;
+
+	/* SD MEMORY, Get the Card-Specific Data */
+	if (sd_mmc_card->type & CARD_TYPE_SD) {
+		if (!sd_mmc_cmd9_mci()) {
+			return false;
+		}
+		sd_decode_csd();
+	}
+	/* Select the and put it into Transfer Mode */
+	if (!driver_send_cmd(sd_mmc_hal, SDMMC_CMD7_SELECT_CARD_CMD, (uint32_t)sd_mmc_card->rca << 16)) {
+		return false;
+	}
+	/* SD MEMORY, Read the SCR to get card version */
+	if (sd_mmc_card->type & CARD_TYPE_SD) {
+		if (!sd_acmd51()) {
+			return false;
+		}
+	}
+	if (IS_SDIO()) {
+		if (!sdio_get_max_speed()) {
+			return false;
+		}
+	}
+	if ((4 <= driver_get_bus_width(sd_mmc_hal, sd_mmc_slot_sel))) {
+		/* TRY to enable 4-bit mode */
+		if (IS_SDIO()) {
+			if (!sdio_cmd52_set_bus_width()) {
+				return false;
+			}
+		}
+		if (sd_mmc_card->type & CARD_TYPE_SD) {
+			if (!sd_acmd6()) {
+				return false;
+			}
+		}
+		/* Switch to selected bus mode */
+		sd_mmc_configure_slot();
+	}
+	if (driver_is_high_speed_capable(sd_mmc_hal)) {
+		/* TRY to enable High-Speed Mode */
+		if (IS_SDIO()) {
+			if (!sdio_cmd52_set_high_speed()) {
+				return false;
+			}
+		}
+		if (sd_mmc_card->type & CARD_TYPE_SD) {
+			if (sd_mmc_card->version > CARD_VER_SD_1_0) {
+				if (!sd_cm6_set_high_speed()) {
+					return false;
+				}
+			}
+		}
+		/* Valid new configuration */
+		sd_mmc_configure_slot();
+	}
+	/* SD MEMORY, Set default block size */
+	if (sd_mmc_card->type & CARD_TYPE_SD) {
+		if (!driver_send_cmd(sd_mmc_hal, SDMMC_CMD16_SET_BLOCKLEN, SD_MMC_BLOCK_SIZE)) {
+			return false;
+		}
+	}
+	return true;
+}
+
+/**
+ * \brief CMD9: Addressed card sends its card-specific
+ * data (CSD) on the CMD line spi.
+ *
+ * \return true if success, otherwise false
+ */
+static bool sd_mmc_cmd9_spi(void)
+{
+	if (!driver_adtc_start(sd_mmc_hal, SDMMC_SPI_CMD9_SEND_CSD, (uint32_t)sd_mmc_card->rca << 16,
+						   CSD_REG_BSIZE, 1, true)) {
+		return false;
+	}
+	if (!driver_start_read_blocks(sd_mmc_hal, sd_mmc_card->csd, 1)) {
+		return false;
+	}
+	return driver_wait_end_of_read_blocks(sd_mmc_hal);
+}
+
+
+#if CONF_MMC_SUPPORT
+/**
+ * \brief Initialize the MMC card in MCI mode.
+ *
+ * \note
+ * This function runs the initialization procedure and the identification
+ * process, then it sets the SD/MMC card in transfer state.
+ * At last, it will automaticly enable maximum bus width and transfer speed.
+ *
+ * \return true if success, otherwise false
+ */
+static bool sd_mmc_mci_install_mmc(void)
+{
+	uint8_t b_authorize_high_speed;
+
+	/* CMD0 - Reset all cards to idle state. */
+	if (!driver_send_cmd(sd_mmc_hal, SDMMC_MCI_CMD0_GO_IDLE_STATE, 0)) {
+		return false;
+	}
+
+	if (!mmc_mci_op_cond()) {
+		return false;
+	}
+
+	/* Put the Card in Identify Mode
+	 * Note: The CID is not used in this stack*/
+	if (!driver_send_cmd(sd_mmc_hal, SDMMC_CMD2_ALL_SEND_CID, 0)) {
+		return false;
+	}
+	/* Assign relative address to the card.*/
+	sd_mmc_card->rca = 1;
+	if (!driver_send_cmd(sd_mmc_hal, MMC_CMD3_SET_RELATIVE_ADDR, (uint32_t)sd_mmc_card->rca << 16)) {
+		return false;
+	}
+	/* Get the Card-Specific Data */
+	if (!sd_mmc_cmd9_mci()) {
+		return false;
+	}
+	mmc_decode_csd();
+	/* Select the and put it into Transfer Mode */
+	if (!driver_send_cmd(sd_mmc_hal, SDMMC_CMD7_SELECT_CARD_CMD, (uint32_t)sd_mmc_card->rca << 16)) {
+		return false;
+	}
+	if (sd_mmc_card->version >= CARD_VER_MMC_4) {
+		/* For MMC 4.0 Higher version
+		 * Get EXT_CSD */
+		if (!mmc_cmd8(&b_authorize_high_speed)) {
+			return false;
+		}
+		if (4 <= driver_get_bus_width(sd_mmc_hal, sd_mmc_slot_sel)) {
+			/* Enable more bus width */
+			if (!mmc_cmd6_set_bus_width(driver_get_bus_width(sd_mmc_hal, sd_mmc_slot_sel))) {
+				return false;
+			}
+			/* Reinitialize the slot with the bus width */
+			sd_mmc_configure_slot();
+		}
+		if (driver_is_high_speed_capable(sd_mmc_hal) && b_authorize_high_speed) {
+			/* Enable HS */
+			if (!mmc_cmd6_set_high_speed()) {
+				return false;
+			}
+			/* Reinitialize the slot with the new speed */
+			sd_mmc_configure_slot();
+		}
+	} else {
+		/* Reinitialize the slot with the new speed */
+		sd_mmc_configure_slot();
+	}
+
+	uint8_t retry = 10;
+	while (retry--) {
+		/* Retry is a WORKAROUND for no compliance card (Atmel Internal ref. MMC19):
+		 * These cards seem not ready immediatly
+		 * after the end of busy of mmc_cmd6_set_high_speed()*/
+
+		/* Set default block size */
+		if (driver_send_cmd(sd_mmc_hal, SDMMC_CMD16_SET_BLOCKLEN, SD_MMC_BLOCK_SIZE)) {
+			return true;
+		}
+	}
+	return false;
+}
+#endif
+
+/*--------------------- PUBLIC FUNCTIONS ----------------------------*/
+
+void sd_mmc_init(void *hal, sd_mmc_detect_t *card_detects, sd_mmc_detect_t *wp_detects)
+{
+	/* GPIO will be used to detect card and write protect.
+	 * The related clocks and pinmux must be configurated in good
+	 * condition. */
+
+	for (uint8_t slot = 0; slot < CONF_SD_MMC_MEM_CNT; slot++) {
+		sd_mmc_cards[slot].state = SD_MMC_CARD_STATE_NO_CARD;
+	}
+	sd_mmc_slot_sel = 0xFF; /* No slot configurated */
+	sd_mmc_hal      = hal;
+	_cd             = card_detects;
+	_wp             = wp_detects;
+}
+
+uint8_t sd_mmc_nb_slot(void)
+{
+	return CONF_SD_MMC_MEM_CNT;
+}
+
+sd_mmc_err_t sd_mmc_check(uint8_t slot)
+{
+	sd_mmc_err_t sd_mmc_err;
+
+	sd_mmc_err = sd_mmc_select_slot(slot);
+	if (sd_mmc_err != SD_MMC_INIT_ONGOING) {
+		sd_mmc_deselect_slot();
+		return sd_mmc_err;
+	}
+
+	// SPI MODE
+	/*
+	// Initialization of the card requested
+	if (sd_mmc_mci_card_init()) {
+		sd_mmc_card->state = SD_MMC_CARD_STATE_READY;
+		sd_mmc_deselect_slot();
+		// To notify that the card has been just initialized
+		// It is necessary for USB Device MSC
+		return SD_MMC_INIT_ONGOING;
+	}
+	*/
+	if(sd_mmc_spi_card_init())
+	{
+		sd_mmc_spi_debug("SD/MMC card ready\n\r");
+		sd_mmc_card->state = SD_MMC_CARD_STATE_READY;
+		sd_mmc_deselect_slot();
+		// To notify that the card has been just initialized
+		// It is necessary for USB Device MSC
+		return SD_MMC_INIT_ONGOING;
+	}
+	sd_mmc_card->state = SD_MMC_CARD_STATE_UNUSABLE;
+	sd_mmc_deselect_slot();
+	return SD_MMC_ERR_UNUSABLE;
+}
+
+card_type_t sd_mmc_get_type(uint8_t slot)
+{
+	if (SD_MMC_OK != sd_mmc_select_slot(slot)) {
+		return CARD_TYPE_UNKNOWN;
+	}
+	sd_mmc_deselect_slot();
+	return sd_mmc_card->type;
+}
+
+card_version_t sd_mmc_get_version(uint8_t slot)
+{
+	if (SD_MMC_OK != sd_mmc_select_slot(slot)) {
+		return CARD_VER_UNKNOWN;
+	}
+	sd_mmc_deselect_slot();
+	return sd_mmc_card->version;
+}
+
+uint32_t sd_mmc_get_capacity(uint8_t slot)
+{
+	if (SD_MMC_OK != sd_mmc_select_slot(slot)) {
+		return 0;
+	}
+	sd_mmc_deselect_slot();
+	return sd_mmc_card->capacity;
+}
+
+bool sd_mmc_is_write_protected(uint8_t slot)
+{
+	/* No detection, always writable */
+	if (!_wp || _wp[slot].pin == -1) {
+		return false;
+	}
+	/* Write Protect Detect */
+	if (gpio_get_pin_level(_wp[slot].pin) == _wp[slot].val) {
+		return true;
+	}
+	return false;
+}
+
+sd_mmc_err_t sd_mmc_init_read_blocks(uint8_t slot, uint32_t start, uint16_t nb_block)
+{
+	sd_mmc_err_t sd_mmc_err;
+	uint32_t     cmd, arg, resp;
+
+	sd_mmc_err = sd_mmc_select_slot(slot);
+	if (sd_mmc_err != SD_MMC_OK) {
+		return sd_mmc_err;
+	}
+
+	/* Wait for data ready status */
+	if (!sd_mmc_cmd13()) {
+		sd_mmc_deselect_slot();
+		return SD_MMC_ERR_COMM;
+	}
+
+	if (nb_block > 1) {
+		cmd = SDMMC_CMD18_READ_MULTIPLE_BLOCK;
+	} else {
+		cmd = SDMMC_CMD17_READ_SINGLE_BLOCK;
+	}
+	/*
+	 * SDSC Card (CCS=0) uses byte unit address,
+	 * SDHC and SDXC Cards (CCS=1) use block unit address (512 Bytes unit).
+	 */
+	if (sd_mmc_card->type & CARD_TYPE_HC) {
+		arg = start;
+	} else {
+		arg = (start * SD_MMC_BLOCK_SIZE);
+	}
+
+	if (!driver_adtc_start(sd_mmc_hal, cmd, arg, SD_MMC_BLOCK_SIZE, nb_block, true)) {
+		sd_mmc_deselect_slot();
+		return SD_MMC_ERR_COMM;
+	}
+	/* Check response */
+	resp = driver_get_response(sd_mmc_hal);
+	if (resp & CARD_STATUS_ERR_RD_WR) {
+		sd_mmc_deselect_slot();
+		return SD_MMC_ERR_COMM;
+	}
+
+	sd_mmc_nb_block_remaining  = nb_block;
+	sd_mmc_nb_block_to_tranfer = nb_block;
+	return SD_MMC_OK;
+}
+
+sd_mmc_err_t sd_mmc_start_read_blocks(void *dest, uint16_t nb_block)
+{
+	assert(sd_mmc_nb_block_remaining >= nb_block, ">>>");
+
+	if (!driver_start_read_blocks(sd_mmc_hal, dest, nb_block)) {
+		sd_mmc_nb_block_remaining = 0;
+		return SD_MMC_ERR_COMM;
+	}
+	sd_mmc_nb_block_remaining -= nb_block;
+	return SD_MMC_OK;
+}
+
+sd_mmc_err_t sd_mmc_wait_end_of_read_blocks(bool abort)
+{
+	if (!driver_wait_end_of_read_blocks(sd_mmc_hal)) {
+		return SD_MMC_ERR_COMM;
+	}
+	if (abort) {
+		sd_mmc_nb_block_remaining = 0;
+	} else if (sd_mmc_nb_block_remaining) {
+		return SD_MMC_OK;
+	}
+
+	/* All blocks are transfered then stop read operation */
+	if (sd_mmc_nb_block_to_tranfer == 1) {
+		/* Single block transfer, then nothing to do */
+		sd_mmc_deselect_slot();
+		return SD_MMC_OK;
+	}
+	/* WORKAROUND for no compliance card (Atmel Internal ref. !MMC7 !SD19):
+	 * The errors on this command must be ignored
+	 * and one retry can be necessary in SPI mode for no compliance card.*/
+	if (!driver_adtc_stop(sd_mmc_hal, SDMMC_CMD12_STOP_TRANSMISSION, 0)) {
+		driver_adtc_stop(sd_mmc_hal, SDMMC_CMD12_STOP_TRANSMISSION, 0);
+	}
+	sd_mmc_deselect_slot();
+	return SD_MMC_OK;
+}
+
+sd_mmc_err_t sd_mmc_init_write_blocks(uint8_t slot, uint32_t start, uint16_t nb_block)
+{
+	sd_mmc_err_t sd_mmc_err;
+	uint32_t     cmd, arg, resp;
+
+	sd_mmc_err = sd_mmc_select_slot(slot);
+	if (sd_mmc_err != SD_MMC_OK) {
+		return sd_mmc_err;
+	}
+	if (sd_mmc_is_write_protected(slot)) {
+		sd_mmc_deselect_slot();
+		return SD_MMC_ERR_WP;
+	}
+
+	if (nb_block > 1) {
+		cmd = SDMMC_CMD25_WRITE_MULTIPLE_BLOCK;
+	} else {
+		cmd = SDMMC_CMD24_WRITE_BLOCK;
+	}
+	/*
+	 * SDSC Card (CCS=0) uses byte unit address,
+	 * SDHC and SDXC Cards (CCS=1) use block unit address (512 Bytes unit).
+	 */
+	if (sd_mmc_card->type & CARD_TYPE_HC) {
+		arg = start;
+	} else {
+		arg = (start * SD_MMC_BLOCK_SIZE);
+	}
+	if (!driver_adtc_start(sd_mmc_hal, cmd, arg, SD_MMC_BLOCK_SIZE, nb_block, true)) {
+		sd_mmc_deselect_slot();
+		return SD_MMC_ERR_COMM;
+	}
+	/* Check response */
+	resp = driver_get_response(sd_mmc_hal);
+	if (resp & CARD_STATUS_ERR_RD_WR) {
+		sd_mmc_deselect_slot();
+		return SD_MMC_ERR_COMM;
+	}
+
+	sd_mmc_nb_block_remaining  = nb_block;
+	sd_mmc_nb_block_to_tranfer = nb_block;
+	return SD_MMC_OK;
+}
+
+sd_mmc_err_t sd_mmc_start_write_blocks(const void *src, uint16_t nb_block)
+{
+	assert(sd_mmc_nb_block_remaining >= nb_block, ">>>");
+	if (!driver_start_write_blocks(sd_mmc_hal, src, nb_block)) {
+		sd_mmc_nb_block_remaining = 0;
+		return SD_MMC_ERR_COMM;
+	}
+	sd_mmc_nb_block_remaining -= nb_block;
+	return SD_MMC_OK;
+}
+
+sd_mmc_err_t sd_mmc_wait_end_of_write_blocks(bool abort)
+{
+	if (!driver_wait_end_of_write_blocks(sd_mmc_hal)) {
+		return SD_MMC_ERR_COMM;
+	}
+	if (abort) {
+		sd_mmc_nb_block_remaining = 0;
+	} else if (sd_mmc_nb_block_remaining) {
+		return SD_MMC_OK;
+	}
+
+	/* All blocks are transfered then stop write operation */
+	if (sd_mmc_nb_block_to_tranfer == 1) {
+		/* Single block transfer, then nothing to do */
+		sd_mmc_deselect_slot();
+		return SD_MMC_OK;
+	}
+
+	/* Note: SPI multiblock writes terminate using a special
+	 * token, not a STOP_TRANSMISSION request.*/
+	if (!driver_adtc_stop(sd_mmc_hal, SDMMC_CMD12_STOP_TRANSMISSION, 0)) {
+		sd_mmc_deselect_slot();
+		return SD_MMC_ERR_COMM;
+	}
+
+	sd_mmc_deselect_slot();
+	return SD_MMC_OK;
+}
+
+#if (CONF_SDIO_SUPPORT == 1)
+sd_mmc_err_t sdio_read_direct(uint8_t slot, uint8_t func_num, uint32_t addr, uint8_t *dest)
+{
+	sd_mmc_err_t sd_mmc_err;
+
+	if (dest == NULL) {
+		return SD_MMC_ERR_PARAM;
+	}
+
+	sd_mmc_err = sd_mmc_select_slot(slot);
+	if (sd_mmc_err != SD_MMC_OK) {
+		return sd_mmc_err;
+	}
+
+	if (!sdio_cmd52(SDIO_CMD52_READ_FLAG, func_num, addr, 0, dest)) {
+		sd_mmc_deselect_slot();
+		return SD_MMC_ERR_COMM;
+	}
+	sd_mmc_deselect_slot();
+	return SD_MMC_OK;
+}
+
+sd_mmc_err_t sdio_write_direct(uint8_t slot, uint8_t func_num, uint32_t addr, uint8_t data)
+{
+	sd_mmc_err_t sd_mmc_err;
+
+	sd_mmc_err = sd_mmc_select_slot(slot);
+	if (sd_mmc_err != SD_MMC_OK) {
+		return sd_mmc_err;
+	}
+
+	if (!sdio_cmd52(SDIO_CMD52_WRITE_FLAG, func_num, addr, 0, &data)) {
+		sd_mmc_deselect_slot();
+		return SD_MMC_ERR_COMM;
+	}
+
+	sd_mmc_deselect_slot();
+	return SD_MMC_OK;
+}
+
+sd_mmc_err_t sdio_read_extended(uint8_t slot, uint8_t func_num, uint32_t addr, uint8_t inc_addr, uint8_t *dest,
+                                uint16_t size)
+{
+	sd_mmc_err_t sd_mmc_err;
+
+	if ((size == 0) || (size > 512)) {
+		return SD_MMC_ERR_PARAM;
+	}
+
+	sd_mmc_err = sd_mmc_select_slot(slot);
+	if (sd_mmc_err != SD_MMC_OK) {
+		return sd_mmc_err;
+	}
+
+	if (!sdio_cmd53(SDIO_CMD53_READ_FLAG, func_num, addr, inc_addr, size, true)) {
+		sd_mmc_deselect_slot();
+		return SD_MMC_ERR_COMM;
+	}
+	if (!driver_start_read_blocks(sd_mmc_hal, dest, 1)) {
+		sd_mmc_deselect_slot();
+		return SD_MMC_ERR_COMM;
+	}
+	if (!driver_wait_end_of_read_blocks(sd_mmc_hal)) {
+		sd_mmc_deselect_slot();
+		return SD_MMC_ERR_COMM;
+	}
+
+	sd_mmc_deselect_slot();
+	return SD_MMC_OK;
+}
+
+sd_mmc_err_t sdio_write_extended(uint8_t slot, uint8_t func_num, uint32_t addr, uint8_t inc_addr, uint8_t *src,
+                                 uint16_t size)
+{
+	sd_mmc_err_t sd_mmc_err;
+
+	if ((size == 0) || (size > 512)) {
+		return SD_MMC_ERR_PARAM;
+	}
+
+	sd_mmc_err = sd_mmc_select_slot(slot);
+	if (sd_mmc_err != SD_MMC_OK) {
+		return sd_mmc_err;
+	}
+
+	if (!sdio_cmd53(SDIO_CMD53_WRITE_FLAG, func_num, addr, inc_addr, size, true)) {
+		sd_mmc_deselect_slot();
+		return SD_MMC_ERR_COMM;
+	}
+	if (!driver_start_write_blocks(sd_mmc_hal, src, 1)) {
+		sd_mmc_deselect_slot();
+		return SD_MMC_ERR_COMM;
+	}
+	if (!driver_wait_end_of_write_blocks(sd_mmc_hal)) {
+		sd_mmc_deselect_slot();
+		return SD_MMC_ERR_COMM;
+	}
+
+	sd_mmc_deselect_slot();
+	return SD_MMC_OK;
+}
+#endif
+
+/** @} */
diff --git a/sd_mmc/sd_mmc.h b/sd_mmc/sd_mmc.h
new file mode 100644
index 0000000..1437e5e
--- /dev/null
+++ b/sd_mmc/sd_mmc.h
@@ -0,0 +1,310 @@
+/**
+ * \file
+ *
+ * \brief Common SD/MMC stack header file
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef SD_MMC_H_INCLUDED
+#define SD_MMC_H_INCLUDED
+
+#include "compiler.h"
+#include "conf_sd_mmc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \ingroup common_memory
+ * \defgroup sd_mmc_stack_group SD/MMC/SDIO common stack
+ *
+ * SD/MMC/SDIO basic APIs used by SD/MMC/SDIO memory
+ * APIs (\ref sd_mmc_stack_mem_group).
+ * Also, it can be used by application which use the SDIO card
+ * or specific application which does not need of File System.
+ *
+ * For usual application which use the SD/MMC card in
+ * memory mode with a file system, please refer to
+ * \ref sd_mmc_stack_mem_group.
+ * @{
+ */
+
+typedef uint8_t sd_mmc_err_t; /**< Type of return error code */
+
+/** \name Return error codes */
+/** @{ */
+#define SD_MMC_OK 0           /**< No error */
+#define SD_MMC_INIT_ONGOING 1 /**< Card not initialized */
+#define SD_MMC_ERR_NO_CARD 2  /**< No SD/MMC card inserted */
+#define SD_MMC_ERR_UNUSABLE 3 /**< Unusable card */
+#define SD_MMC_ERR_SLOT 4     /**< Slot unknow */
+#define SD_MMC_ERR_COMM 5     /**< General communication error */
+#define SD_MMC_ERR_PARAM 6    /**< Illeage input parameter */
+#define SD_MMC_ERR_WP 7       /**< Card write protected */
+/** @} */
+
+typedef uint8_t card_type_t; /**< Type of card type */
+
+/** \name Card Types */
+/** @{ */
+#define CARD_TYPE_UNKNOWN (0)   /**< Unknown type card */
+#define CARD_TYPE_SD (1 << 0)   /**< SD card */
+#define CARD_TYPE_MMC (1 << 1)  /**< MMC card */
+#define CARD_TYPE_SDIO (1 << 2) /**< SDIO card */
+#define CARD_TYPE_HC (1 << 3)   /**< High capacity card */
+/** SD combo card (io + memory) */
+#define CARD_TYPE_SD_COMBO (CARD_TYPE_SD | CARD_TYPE_SDIO)
+/** @} */
+
+typedef uint8_t card_version_t; /**< Type of card version */
+
+/** \name Card Versions */
+/** @{ */
+#define CARD_VER_UNKNOWN (0)    /**< Unknown card version */
+#define CARD_VER_SD_1_0 (0x10)  /**< SD version 1.0 and 1.01 */
+#define CARD_VER_SD_1_10 (0x1A) /**< SD version 1.10 */
+#define CARD_VER_SD_2_0 (0X20)  /**< SD version 2.00 */
+#define CARD_VER_SD_3_0 (0X30)  /**< SD version 3.0X */
+#define CARD_VER_MMC_1_2 (0x12) /**< MMC version 1.2 */
+#define CARD_VER_MMC_1_4 (0x14) /**< MMC version 1.4 */
+#define CARD_VER_MMC_2_2 (0x22) /**< MMC version 2.2 */
+#define CARD_VER_MMC_3 (0x30)   /**< MMC version 3 */
+#define CARD_VER_MMC_4 (0x40)   /**< MMC version 4 */
+/** @} */
+
+/** Card detect setting */
+typedef struct sd_mmc_detect {
+	int16_t  pin; /**< Detection pin, -1 if no such pin */
+	uint16_t val; /**< Detection value */
+} sd_mmc_detect_t;
+
+/** This SD MMC stack uses the maximum block size autorized (512 bytes) */
+#define SD_MMC_BLOCK_SIZE 512
+
+/**
+ * \brief Initialize the SD/MMC stack and low level driver required
+ * \param[in] hal Pointer to HAL instance
+ * \param[in] card_detects Pointer to list of card detect settings,
+ *                         list size should be \ref CONF_SD_MMC_MEM_CNT
+ * \param[in] wp_detects Pointer to list of write protect detect settings
+ *                       list size should be \ref CONF_SD_MMC_MEM_CNT
+ */
+void sd_mmc_init(void *hal, sd_mmc_detect_t *card_detects, sd_mmc_detect_t *wp_detects);
+
+/** \brief Return the number of slot available
+ *
+ * \return Number of card slot available
+ */
+uint8_t sd_mmc_nb_slot(void);
+
+/** \brief Performs a card checks
+ *
+ * \param[in] slot     Card slot to use
+ *
+ * \retval SD_MMC_OK           Card ready
+ * \retval SD_MMC_INIT_ONGOING Initialization on going
+ * \retval SD_MMC_ERR_NO_CARD  Card not present in slot
+ * \retval Other value for error cases, see \ref sd_mmc_err_t
+ */
+sd_mmc_err_t sd_mmc_check(uint8_t slot);
+
+/** \brief Get the card type
+ *
+ * \param[in] slot     Card slot
+ *
+ * \return Card type (\ref card_type_t)
+ */
+card_type_t sd_mmc_get_type(uint8_t slot);
+
+/** \brief Get the card version
+ *
+ * \param[in] slot     Card slot
+ *
+ * \return Card version (\ref card_version_t)
+ */
+card_version_t sd_mmc_get_version(uint8_t slot);
+
+/** \brief Get the memory capacity
+ *
+ * \param[in] slot     Card slot
+ *
+ * \return Capacity (unit KB)
+ */
+uint32_t sd_mmc_get_capacity(uint8_t slot);
+
+/** \brief Get the card write protection status
+ *
+ * \param[in] slot     Card slot
+ *
+ * \return true, if write portected
+ */
+bool sd_mmc_is_write_protected(uint8_t slot);
+
+/**
+ * \brief Initialize the read blocks of data from the card.
+ *
+ * \param[in] slot     Card slot to use
+ * \param[in] start    Start block number to to read.
+ * \param[in] nb_block Total number of blocks to be read.
+ *
+ * \return return SD_MMC_OK if success,
+ *         otherwise return an error code (\ref sd_mmc_err_t).
+ */
+sd_mmc_err_t sd_mmc_init_read_blocks(uint8_t slot, uint32_t start, uint16_t nb_block);
+
+/**
+ * \brief Start the read blocks of data from the card.
+ *
+ * \param[out] dest     Pointer to read buffer.
+ * \param[in]  nb_block Number of blocks to be read.
+ *
+ * \return return SD_MMC_OK if started,
+ *         otherwise return an error code (\ref sd_mmc_err_t).
+ */
+sd_mmc_err_t sd_mmc_start_read_blocks(void *dest, uint16_t nb_block);
+
+/**
+ * \brief Wait the end of read blocks of data from the card.
+ *
+ * \param[in] abort Abort reading process initialized by
+ *              \ref sd_mmc_init_read_blocks() after the reading issued by
+ *              \ref sd_mmc_start_read_blocks() is done
+ *
+ * \return return SD_MMC_OK if success,
+ *         otherwise return an error code (\ref sd_mmc_err_t).
+ */
+sd_mmc_err_t sd_mmc_wait_end_of_read_blocks(bool abort);
+
+/**
+ * \brief Initialize the write blocks of data
+ *
+ * \param[in] slot     Card slot to use
+ * \param[in] start    Start block number to be written.
+ * \param[in] nb_block Total number of blocks to be written.
+ *
+ * \return return SD_MMC_OK if success,
+ *         otherwise return an error code (\ref sd_mmc_err_t).
+ */
+sd_mmc_err_t sd_mmc_init_write_blocks(uint8_t slot, uint32_t start, uint16_t nb_block);
+
+/**
+ * \brief Start the write blocks of data
+ *
+ * \param[in] src      Pointer to write buffer.
+ * \param[in] nb_block Number of blocks to be written.
+ *
+ * \return return SD_MMC_OK if started,
+ *         otherwise return an error code (\ref sd_mmc_err_t).
+ */
+sd_mmc_err_t sd_mmc_start_write_blocks(const void *src, uint16_t nb_block);
+
+/**
+ * \brief Wait the end of write blocks of data
+ *
+ * \param[in] abort Abort writing process initialized by
+ *              \ref sd_mmc_init_write_blocks() after the writing issued by
+ *              \ref sd_mmc_start_write_blocks() is done
+ *
+ * \return return SD_MMC_OK if success,
+ *         otherwise return an error code (\ref sd_mmc_err_t).
+ */
+sd_mmc_err_t sd_mmc_wait_end_of_write_blocks(bool abort);
+
+#if (CONF_SDIO_SUPPORT == 1)
+/**
+ * \brief Read one byte from SDIO using RW_DIRECT command.
+ *
+ * \param[in]  slot     Card slot to use
+ * \param[in]  func_num  Function number.
+ * \param[in]  addr      Register address to read from.
+ * \param[out] dest      Pointer to read buffer.
+ *
+ * \return return SD_MMC_OK if success,
+ *         otherwise return an error code (\ref sd_mmc_err_t).
+ */
+sd_mmc_err_t sdio_read_direct(uint8_t slot, uint8_t func_num, uint32_t addr, uint8_t *dest);
+/**
+ * \brief Write one byte to SDIO using RW_DIRECT command.
+ *
+ * \param[in] slot     Card slot to use
+ * \param[in] func_num  Function number.
+ * \param[in] addr      Register address to read from.
+ * \param[in] data      Data to be written.
+ *
+ * \return return SD_MMC_OK if success,
+ *         otherwise return an error code (\ref sd_mmc_err_t).
+ */
+sd_mmc_err_t sdio_write_direct(uint8_t slot, uint8_t func_num, uint32_t addr, uint8_t data);
+
+/**
+ * \brief Read bytes from SDIO using RW_EXTENDED command.
+ *
+ * \param[in] slot     Card slot to use
+ * \param[in] func_num     Function number.
+ * \param[in] addr         First register address to read from.
+ * \param[in] inc_addr     0 - The data address is fixed.
+ *                     1 - The data address increase automatically.
+ * \param[out] dest         Pointer to read buffer.
+ * \param[in] size         Number of bytes to read (1 ~ 512).
+ *
+ * \return return SD_MMC_OK if success,
+ *         otherwise return an error code (\ref sd_mmc_err_t).
+ */
+sd_mmc_err_t sdio_read_extended(uint8_t slot, uint8_t func_num, uint32_t addr, uint8_t inc_addr, uint8_t *dest,
+                                uint16_t size);
+
+/**
+ * \brief Write bytes to SDIO using RW_EXTENDED command.
+ *
+ * \param[in] slot     Card slot to use
+ * \param[in] func_num     Function number.
+ * \param[in] addr         First register address to write to.
+ * \param[in] inc_addr     0 - The data address is fixed.
+ *                     1 - The data address increase automatically.
+ * \param[in] src          Pointer to write buffer.
+ * \param[in] size         Number of bytes to read (1 ~ 512).
+ *
+ * \return return SD_MMC_OK if success,
+ *         otherwise return an error code (\ref sd_mmc_err_t).
+ */
+sd_mmc_err_t sdio_write_extended(uint8_t slot, uint8_t func_num, uint32_t addr, uint8_t inc_addr, uint8_t *src,
+                                 uint16_t size);
+#endif /* SDIO_SUPPORT_ENABLE */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SD_MMC_H_INCLUDED */
diff --git a/sd_mmc/sd_mmc_protocol.h b/sd_mmc/sd_mmc_protocol.h
new file mode 100644
index 0000000..0516e4f
--- /dev/null
+++ b/sd_mmc/sd_mmc_protocol.h
@@ -0,0 +1,1001 @@
+/**
+ * \file
+ *
+ * \brief SD/MMC protocol definitions.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef SD_MMC_PROTOCOL_H_INCLUDED
+#define SD_MMC_PROTOCOL_H_INCLUDED
+
+#include "compiler.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup sd_mmc_protocol SD/MMC Protocol Definition
+ * \ingroup sd_mmc_stack_group
+ * @{
+ */
+
+// SD/MMC/SDIO default clock frequency for initialization (400KHz)
+#define SDMMC_CLOCK_INIT 400000
+
+/**
+ * \name Macros for command definition
+ *
+ * Commands types:
+ * - broadcast commands (bc), no response
+ * - broadcast commands with response (bcr) (Note: No open drain on SD card)
+ * - addressed (point-to-point) commands (ac), no data transfer on DAT lines
+ * - addressed (point-to-point) data transfer commands (adtc), data transfer
+ * on DAT lines
+ *
+ * Specific MMC norms:
+ * CMD1, CMD2 & CMD3 are processed in the open-drain mode.
+ * The CMD line is driven with push-pull drivers.
+ *
+ * Specific SD norms:
+ * There is no open drain mode in SD memory card.
+ *
+ ***************************************
+ * Responses types:
+ *
+ * R1, R3, R4 & R5 use a 48 bits response protected by a 7bit CRC checksum
+ * - R1 receiv data not specified
+ * - R3 receiv OCR
+ * - R4, R5 RCA management (MMC only)
+ * - R6, R7 RCA management (SD only)
+ *
+ * R1b assert the BUSY signal and respond with R1.
+ * If the busy signal is asserted, it is done two clock cycles (Nsr time)
+ * after the end bit of the command. The DAT0 line is driven low.
+ * DAT1-DAT7 lines are driven by the card though their values are not relevant.
+ *
+ * R2 use a 136 bits response protected by a 7bit CRC checksum
+ * The content is CID or CSD
+ *
+ * Specific MMC norms:
+ * - R4 (Fast I/O) return RCA
+ * - R5 (interrupt request) return RCA null
+ *
+ * Specific SD norms:
+ * - R6 (Published RCA) return RCA
+ * - R7 (Card interface condition) return RCA null
+ *
+ * @{
+ */
+
+//! Value to define a SD/MMC/SDIO command
+typedef uint32_t sdmmc_cmd_def_t;
+
+//! \name Flags used to define a SD/MMC/SDIO command
+//! @{
+#define SDMMC_CMD_GET_INDEX(cmd) (cmd & 0x3F)
+//! Have response (MCI only)
+#define SDMMC_RESP_PRESENT (1lu << 8)
+//! 8 bit response (SPI only)
+#define SDMMC_RESP_8 (1lu << 9)
+//! 32 bit response (SPI only)
+#define SDMMC_RESP_32 (1lu << 10)
+//! 136 bit response (MCI only)
+#define SDMMC_RESP_136 (1lu << 11)
+//! Expect valid crc (MCI only)
+#define SDMMC_RESP_CRC (1lu << 12)
+//! Card may send busy
+#define SDMMC_RESP_BUSY (1lu << 13)
+// Open drain for a braodcast command (bc)
+// or to enter in inactive state (MCI only)
+#define SDMMC_CMD_OPENDRAIN (1lu << 14)
+//! To signal a data write operation
+#define SDMMC_CMD_WRITE (1lu << 15)
+//! To signal a SDIO tranfer in multi byte mode
+#define SDMMC_CMD_SDIO_BYTE (1lu << 16)
+//! To signal a SDIO tranfer in block mode
+#define SDMMC_CMD_SDIO_BLOCK (1lu << 17)
+//! To signal a data transfer in stream mode
+#define SDMMC_CMD_STREAM (1lu << 18)
+//! To signal a data transfer in single block mode
+#define SDMMC_CMD_SINGLE_BLOCK (1lu << 19)
+//! To signal a data transfer in multi block mode
+#define SDMMC_CMD_MULTI_BLOCK (1lu << 20)
+//! @}
+
+//! \name Set of flags to define a reponse type
+//! @{
+#define SDMMC_CMD_NO_RESP (0)
+#define SDMMC_CMD_R1 (SDMMC_RESP_PRESENT | SDMMC_RESP_CRC)
+#define SDMMC_CMD_R1B (SDMMC_RESP_PRESENT | SDMMC_RESP_CRC | SDMMC_RESP_BUSY)
+#define SDMMC_CMD_R2 (SDMMC_RESP_PRESENT | SDMMC_RESP_8 | SDMMC_RESP_136 | SDMMC_RESP_CRC)
+#define SDMMC_CMD_R3 (SDMMC_RESP_PRESENT | SDMMC_RESP_32)
+#define SDMMC_CMD_R4 (SDMMC_RESP_PRESENT | SDMMC_RESP_32)
+#define SDMMC_CMD_R5 (SDMMC_RESP_PRESENT | SDMMC_RESP_8 | SDMMC_RESP_CRC)
+#define SDMMC_CMD_R6 (SDMMC_RESP_PRESENT | SDMMC_RESP_CRC)
+#define SDMMC_CMD_R7 (SDMMC_RESP_PRESENT | SDMMC_RESP_32 | SDMMC_RESP_CRC)
+//! @}
+
+//! \name SD/MMC/SDIO command definitions
+//! SDMMC_CMDx are include in SD and MMC norms
+//! MMC_CMDx   are include in MMC norms only
+//! SD_CMDx    are include in SD norms only
+//! SDIO_CMDx  are include in SDIO norms only
+//! @{
+
+/*
+ * --- Basic commands and read-stream command (class 0 and class 1) ---
+ */
+
+/** Cmd0(bc): Reset all cards to idle state */
+#define SDMMC_SPI_CMD0_GO_IDLE_STATE (0 | SDMMC_CMD_R1)
+#define SDMMC_MCI_CMD0_GO_IDLE_STATE (0 | SDMMC_CMD_NO_RESP | SDMMC_CMD_OPENDRAIN)
+/** MMC Cmd1(bcr, R3): Ask the card to send its Operating Conditions */
+#define MMC_SPI_CMD1_SEND_OP_COND (1 | SDMMC_CMD_R1)
+#define MMC_MCI_CMD1_SEND_OP_COND (1 | SDMMC_CMD_R3 | SDMMC_CMD_OPENDRAIN)
+/** Cmd2(bcr, R2): Ask the card to send its CID number (stuff but arg 0 used) */
+#define SDMMC_CMD2_ALL_SEND_CID (2 | SDMMC_CMD_R2 | SDMMC_CMD_OPENDRAIN)
+/** SD Cmd3(bcr, R6): Ask the card to publish a new relative address (RCA) */
+#define SD_CMD3_SEND_RELATIVE_ADDR (3 | SDMMC_CMD_R6 | SDMMC_CMD_OPENDRAIN)
+/** MMC Cmd3(ac, R1): Assigns relative address to the card */
+#define MMC_CMD3_SET_RELATIVE_ADDR (3 | SDMMC_CMD_R1)
+/** Cmd4(bc): Program the DSR of all cards (MCI only) */
+#define SDMMC_CMD4_SET_DSR (4 | SDMMC_CMD_NO_RESP)
+/** MMC Cmd5(ac, R1b): Toggle the card between Sleep state and Standby state. */
+#define MMC_CMD5_SLEEP_AWAKE (5 | SDMMC_CMD_R1B)
+/** Cmd7(ac, R1/R1b): Select/Deselect card
+ * For SD: R1b only from the selected card.
+ * For MMC: R1 while selecting from Stand-By State to Transfer State;
+ *          R1b while selecting from Disconnected State to Programming State.
+ */
+#define SDMMC_CMD7_SELECT_CARD_CMD (7 | SDMMC_CMD_R1B)
+#define SDMMC_CMD7_DESELECT_CARD_CMD (7 | SDMMC_CMD_R1)
+/** MMC Cmd8(adtc, R1): Send EXT_CSD register as a block of data */
+#define MMC_CMD8_SEND_EXT_CSD (8 | SDMMC_CMD_R1 | SDMMC_CMD_SINGLE_BLOCK)
+/** SD Cmd8(bcr, R7) : Send SD Memory Card interface condition */
+#define SD_CMD8_SEND_IF_COND (8 | SDMMC_CMD_R7 | SDMMC_CMD_OPENDRAIN)
+/** Cmd9 SPI (R1): Addressed card sends its card-specific data (CSD) */
+#define SDMMC_SPI_CMD9_SEND_CSD (9 | SDMMC_CMD_R1 | SDMMC_CMD_SINGLE_BLOCK)
+/** Cmd9 MCI (ac, R2): Addressed card sends its card-specific data (CSD) */
+#define SDMMC_MCI_CMD9_SEND_CSD (9 | SDMMC_CMD_R2)
+/** Cmd10(ac, R2): Addressed card sends its card identification (CID) */
+#define SDMMC_CMD10_SEND_CID (10 | SDMMC_CMD_R2)
+/**
+ * MMC Cmd11(adtc, R1): Read data stream from the card, starting at the given
+ * address, until a STOP_TRANSMISSION follows.
+ */
+#define MMC_CMD11_READ_DAT_UNTIL_STOP (11 | SDMMC_CMD_R1)
+/* SD Cmd11 MCI (ac, R1): Voltage switching */
+#define SD_CMD11_READ_DAT_UNTIL_STOP (11 | SDMMC_CMD_R1)
+/** Cmd12(ac, R1b): Force the card to stop transmission */
+#define SDMMC_CMD12_STOP_TRANSMISSION (12 | SDMMC_CMD_R1B)
+/** Cmd13(R2): Addressed card sends its status register. */
+#define SDMMC_SPI_CMD13_SEND_STATUS (13 | SDMMC_CMD_R2)
+/** Cmd13(ac, R1): Addressed card sends its status register. */
+#define SDMMC_MCI_CMD13_SEND_STATUS (13 | SDMMC_CMD_R1)
+/** MMC Cmd14(adtc, R1): Read the reversed bus testing data pattern from a card. */
+#define MMC_CMD14_BUSTEST_R (14 | SDMMC_CMD_R1)
+/** Cmd15(ac): Send an addressed card into the Inactive State. */
+// Note: It is a ac cmd, but it must be send like bc cmd to open drain
+#define SDMMC_CMD15_GO_INACTIVE_STATE (15 | SDMMC_CMD_NO_RESP | SDMMC_CMD_OPENDRAIN)
+/** MMC Cmd19(adtc, R1): Send the bus test data pattern */
+#define MMC_CMD19_BUSTEST_W (19 | SDMMC_CMD_R1)
+/** Cmd58(R3): Reads the OCR register of a card */
+#define SDMMC_SPI_CMD58_READ_OCR (58 | SDMMC_CMD_R3)
+/** Cmd59(R1): Turns the CRC option on or off */
+#define SDMMC_SPI_CMD59_CRC_ON_OFF (59 | SDMMC_CMD_R1)
+
+/*
+ * --- Block-oriented read commands (class 2) ---
+ */
+/** Cmd16(ac, R1): Set the block length (in bytes) */
+#define SDMMC_CMD16_SET_BLOCKLEN (16 | SDMMC_CMD_R1)
+/** Cmd17(adtc, R1): Read single block */
+#define SDMMC_CMD17_READ_SINGLE_BLOCK (17 | SDMMC_CMD_R1 | SDMMC_CMD_SINGLE_BLOCK)
+/** Cmd18(adtc, R1): Read multiple block */
+#define SDMMC_CMD18_READ_MULTIPLE_BLOCK (18 | SDMMC_CMD_R1 | SDMMC_CMD_MULTI_BLOCK)
+
+/*
+ * --- Sequential write commands (class 3) ---
+ */
+
+/**
+ * MMC Cmd20(adtc, R1): Write a data stream from the host, starting at the
+ * given address, until a STOP_TRANSMISSION follows.
+ */
+#define MMC_CMD20_WRITE_DAT_UNTIL_STOP (20 | SDMMC_CMD_R1)
+
+/*
+ * --- Block-oriented write commands (class 4) ---
+ */
+/** MMC Cmd23(ac, R1): Set block count */
+#define MMC_CMD23_SET_BLOCK_COUNT (23 | SDMMC_CMD_R1)
+/** Cmd24(adtc, R1): Write block */
+#define SDMMC_CMD24_WRITE_BLOCK (24 | SDMMC_CMD_R1 | SDMMC_CMD_WRITE | SDMMC_CMD_SINGLE_BLOCK)
+/** Cmd25(adtc, R1): Write multiple block */
+#define SDMMC_CMD25_WRITE_MULTIPLE_BLOCK (25 | SDMMC_CMD_R1 | SDMMC_CMD_WRITE | SDMMC_CMD_MULTI_BLOCK)
+/** MMC Cmd26(adtc, R1): Programming of the card identification register. */
+#define MMC_CMD26_PROGRAM_CID (26 | SDMMC_CMD_R1)
+/** Cmd27(adtc, R1): Programming of the programmable bits of the CSD. */
+#define SDMMC_CMD27_PROGRAM_CSD (27 | SDMMC_CMD_R1)
+
+/*
+ * --- Erase commands  (class 5) ---
+ */
+/** SD Cmd32(ac, R1): */
+#define SD_CMD32_ERASE_WR_BLK_START (32 | SDMMC_CMD_R1)
+/** SD Cmd33(ac, R1): */
+#define SD_CMD33_ERASE_WR_BLK_END (33 | SDMMC_CMD_R1)
+/** MMC Cmd35(ac, R1): */
+#define MMC_CMD35_ERASE_GROUP_START (35 | SDMMC_CMD_R1)
+/** MMC Cmd36(ac, R1): */
+#define MMC_CMD36_ERASE_GROUP_END (36 | SDMMC_CMD_R1)
+/** Cmd38(ac, R1B): */
+#define SDMMC_CMD38_ERASE (38 | SDMMC_CMD_R1B)
+
+/*
+ * --- Block Oriented Write Protection Commands (class 6) ---
+ */
+/** Cmd28(ac, R1b): Set write protection */
+#define SDMMC_CMD28_SET_WRITE_PROT (28 | SDMMC_CMD_R1B)
+/** Cmd29(ac, R1b): Clr write protection */
+#define SDMMC_CMD29_CLR_WRITE_PROT (29 | SDMMC_CMD_R1B)
+/** Cmd30(adtc, R1b): Send write protection */
+#define SDMMC_CMD30_SEND_WRITE_PROT (30 | SDMMC_CMD_R1)
+
+/*
+ * --- Lock Card (class 7) ---
+ */
+/** Cmd42(adtc, R1): Used to set/reset the password or lock/unlock the card. */
+#define SDMMC_CMD42_LOCK_UNLOCK (42 | SDMMC_CMD_R1)
+
+/*
+ * --- Application-specific commands (class 8) ---
+ */
+/**
+ * Cmd55(ac, R1): Indicate to the card that the next command is an application
+ * specific command rather than a standard command.
+ */
+#define SDMMC_CMD55_APP_CMD (55 | SDMMC_CMD_R1)
+/**
+ * Cmd 56(adtc, R1): Used either to transfer a data block to the card or to get
+ * a data block from the card for general purpose/application specific commands.
+ */
+#define SDMMC_CMD56_GEN_CMD (56 | SDMMC_CMD_R1)
+
+/**
+ * MMC Cmd6(ac, R1b) : Switche the mode of operation of the selected card
+ * or modifies the EXT_CSD registers.
+ */
+#define MMC_CMD6_SWITCH (6 | SDMMC_CMD_R1B)
+/**
+ * SD Cmd6(adtc, R1) : Check switchable function (mode 0)
+ * and switch card function (mode 1).
+ */
+#define SD_CMD6_SWITCH_FUNC (6 | SDMMC_CMD_R1 | SDMMC_CMD_SINGLE_BLOCK)
+/** ACMD6(ac, R1): Define the data bus width */
+#define SD_ACMD6_SET_BUS_WIDTH (6 | SDMMC_CMD_R1)
+/** ACMD13(adtc, R1): Send the SD Status. */
+#define SD_ACMD13_SD_STATUS (13 | SDMMC_CMD_R1)
+/**
+ * ACMD22(adtc, R1): Send the number of the written (with-out errors) write
+ * blocks.
+ */
+#define SD_ACMD22_SEND_NUM_WR_BLOCKS (22 | SDMMC_CMD_R1)
+/**
+ * ACMD23(ac, R1): Set the number of write blocks to be pre-erased before
+ * writing
+ */
+#define SD_ACMD23_SET_WR_BLK_ERASE_COUNT (23 | SDMMC_CMD_R1)
+/**
+ * ACMD41(bcr, R3): Send host capacity support information (HCS) and asks the
+ * accessed card to send its operating condition register (OCR) content
+ * in the response
+ */
+#define SD_MCI_ACMD41_SD_SEND_OP_COND (41 | SDMMC_CMD_R3 | SDMMC_CMD_OPENDRAIN)
+/**
+ * ACMD41(R1): Send host capacity support information (HCS) and activates the
+ * card's initilization process
+ */
+#define SD_SPI_ACMD41_SD_SEND_OP_COND (41 | SDMMC_CMD_R1)
+/**
+ * ACMD42(ac, R1): Connect[1]/Disconnect[0] the 50 KOhm pull-up resistor on
+ * CD/DAT3 (pin 1) of the card.
+ */
+#define SD_ACMD42_SET_CLR_CARD_DETECT (42 | SDMMC_CMD_R1)
+/** ACMD51(adtc, R1): Read the SD Configuration Register (SCR). */
+#define SD_ACMD51_SEND_SCR (51 | SDMMC_CMD_R1 | SDMMC_CMD_SINGLE_BLOCK)
+
+/*
+ * --- I/O mode commands (class 9) ---
+ */
+/** MMC Cmd39(ac, R4): Used to write and read 8 bit (register) data fields. */
+#define MMC_CMD39_FAST_IO (39 | SDMMC_CMD_R4)
+/** MMC Cmd40(bcr, R5): Set the system into interrupt mode */
+#define MMC_CMD40_GO_IRQ_STATE (40 | SDMMC_CMD_R5 | SDMMC_CMD_OPENDRAIN)
+/** SDIO Cmd5(R4): Send operation condition */
+#define SDIO_CMD5_SEND_OP_COND (5 | SDMMC_CMD_R4 | SDMMC_CMD_OPENDRAIN)
+/** SDIO CMD52(R5): Direct IO read/write */
+#define SDIO_CMD52_IO_RW_DIRECT (52 | SDMMC_CMD_R5)
+/** SDIO CMD53(R5): Extended IO read/write */
+#define SDIO_CMD53_IO_R_BYTE_EXTENDED (53 | SDMMC_CMD_R5 | SDMMC_CMD_SDIO_BYTE)
+#define SDIO_CMD53_IO_W_BYTE_EXTENDED (53 | SDMMC_CMD_R5 | SDMMC_CMD_SDIO_BYTE | SDMMC_CMD_WRITE)
+#define SDIO_CMD53_IO_R_BLOCK_EXTENDED (53 | SDMMC_CMD_R5 | SDMMC_CMD_SDIO_BLOCK)
+#define SDIO_CMD53_IO_W_BLOCK_EXTENDED (53 | SDMMC_CMD_R5 | SDMMC_CMD_SDIO_BLOCK | SDMMC_CMD_WRITE)
+//! @}
+//! @}
+
+//! \name Macros for command argument definition
+//! @{
+
+//! \name MMC CMD6 argument structure
+//! @{
+//! [31:26] Set to 0
+//! [25:24] Access
+#define MMC_CMD6_ACCESS_COMMAND_SET (0lu << 24)
+#define MMC_CMD6_ACCESS_SET_BITS (1lu << 24)
+#define MMC_CMD6_ACCESS_CLEAR_BITS (2lu << 24)
+#define MMC_CMD6_ACCESS_WRITE_BYTE (3lu << 24)
+//! [23:16] Index for Mode Segment
+#define MMC_CMD6_INDEX_CMD_SET (EXT_CSD_CMD_SET_INDEX << 16)
+#define MMC_CMD6_INDEX_CMD_SET_REV (EXT_CSD_CMD_SET_REV_INDEX << 16)
+#define MMC_CMD6_INDEX_POWER_CLASS (EXT_CSD_POWER_CLASS_INDEX << 16)
+#define MMC_CMD6_INDEX_HS_TIMING (EXT_CSD_HS_TIMING_INDEX << 16)
+#define MMC_CMD6_INDEX_BUS_WIDTH (EXT_CSD_BUS_WIDTH_INDEX << 16)
+#define MMC_CMD6_INDEX_ERASED_MEM_CONT (EXT_CSD_ERASED_MEM_CONT_INDEX << 16)
+#define MMC_CMD6_INDEX_BOOT_CONFIG (EXT_CSD_BOOT_CONFIG_INDEX << 16)
+#define MMC_CMD6_INDEX_BOOT_BUS_WIDTH (EXT_CSD_BOOT_BUS_WIDTH_INDEX << 16)
+#define MMC_CMD6_INDEX_ERASE_GROUP_DEF (EXT_CSD_ERASE_GROUP_DEF_INDEX << 16)
+//! [15:8] Value
+#define MMC_CMD6_VALUE_BUS_WIDTH_1BIT (0x0lu << 8)
+#define MMC_CMD6_VALUE_BUS_WIDTH_4BIT (0x1lu << 8)
+#define MMC_CMD6_VALUE_BUS_WIDTH_8BIT (0x2lu << 8)
+#define MMC_CMD6_VALUE_HS_TIMING_ENABLE (0x1lu << 8)
+#define MMC_CMD6_VALUE_HS_TIMING_DISABLE (0x0lu << 8)
+//! [7:3] Set to 0
+//! [2:0] Cmd Set
+//! @}
+
+//! \name SD CMD6 argument structure
+//! @{
+//! CMD6 arg[ 3: 0] function group 1, access mode
+#define SD_CMD6_GRP1_HIGH_SPEED (0x1lu << 0)
+#define SD_CMD6_GRP1_DEFAULT (0x0lu << 0)
+//! CMD6 arg[ 7: 4] function group 2, command system
+#define SD_CMD6_GRP2_NO_INFLUENCE (0xFlu << 4)
+#define SD_CMD6_GRP2_DEFAULT (0x0lu << 4)
+//! CMD6 arg[11: 8] function group 3, 0xF or 0x0
+#define SD_CMD6_GRP3_NO_INFLUENCE (0xFlu << 8)
+#define SD_CMD6_GRP3_DEFAULT (0x0lu << 8)
+//! CMD6 arg[15:12] function group 4, 0xF or 0x0
+#define SD_CMD6_GRP4_NO_INFLUENCE (0xFlu << 12)
+#define SD_CMD6_GRP4_DEFAULT (0x0lu << 12)
+//! CMD6 arg[19:16] function group 5, 0xF or 0x0
+#define SD_CMD6_GRP5_NO_INFLUENCE (0xFlu << 16)
+#define SD_CMD6_GRP5_DEFAULT (0x0lu << 16)
+//! CMD6 arg[23:20] function group 6, 0xF or 0x0
+#define SD_CMD6_GRP6_NO_INFLUENCE (0xFlu << 20)
+#define SD_CMD6_GRP6_DEFAULT (0x0lu << 20)
+//! CMD6 arg[30:24] reserved 0
+//! CMD6 arg[31   ] Mode, 0: Check, 1: Switch
+#define SD_CMD6_MODE_CHECK (0lu << 31)
+#define SD_CMD6_MODE_SWITCH (1lu << 31)
+//! @}
+
+//! \name SD CMD8 argument structure
+//! @{
+#define SD_CMD8_PATTERN 0xAA
+#define SD_CMD8_MASK_PATTERN 0xFF
+#define SD_CMD8_HIGH_VOLTAGE 0x100
+#define SD_CMD8_MASK_VOLTAGE 0xF00
+//! @}
+
+//! \name SD ACMD41 arguments
+//! @{
+#define SD_ACMD41_HCS (1lu << 30) //!< (SD) Host Capacity Support
+                                  //! @}
+//! @}
+
+//! \name SDIO definitions
+//! @{
+
+//! \name SDIO state (in R5)
+//! @{
+#define SDIO_R5_COM_CRC_ERROR (1lu << 15)                                            /**< CRC check error */
+#define SDIO_R5_ILLEGAL_COMMAND (1lu << 14)                                          /**< Illegal command */
+#define SDIO_R5_STATE (3lu << 12)                                                    /**< SDIO R5 state mask */
+#define SDIO_R5_STATE_DIS (0lu << 12)                                                /**< Disabled */
+#define SDIO_R5_STATE_CMD (1lu << 12)                                                /**< DAT lines free */
+#define SDIO_R5_STATE_TRN (2lu << 12)                                                /**< Transfer */
+#define SDIO_R5_STATE_RFU (3lu << 12)                                                /**< Reserved */
+#define SDIO_R5_ERROR (1lu << 11)                                                    /**< General error */
+#define SDIO_R5_FUNC_NUM (1lu << 9)                                                  /**< Invalid function number */
+#define SDIO_R5_OUT_OF_RANGE (1lu << 8)                                              /**< Argument out of range */
+#define SDIO_R5_STATUS_ERR (SDIO_R5_ERROR | SDIO_R5_FUNC_NUM | SDIO_R5_OUT_OF_RANGE) //!< Errro status bits mask
+                                                                                     //! @}
+
+//! \name SDIO state (in R6)
+//! @{
+/** The CRC check of the previous command failed. */
+#define SDIO_R6_COM_CRC_ERROR (1lu << 15)
+/** Command not legal for the card state. */
+#define SDIO_R6_ILLEGAL_COMMAND (1lu << 14)
+/** A general or an unknown error occurred during the operation. */
+#define SDIO_R6_ERROR (1lu << 13)
+/** Status bits mask for SDIO R6 */
+#define SDIO_STATUS_R6 (SDIO_R6_COM_CRC_ERROR | SDIO_R6_ILLEGAL_COMMAND | SDIO_R6_ERROR)
+//! @}
+
+//! \name SDIO CMD52 argument bit offset
+//! @{
+//! CMD52 arg[ 7: 0] Write data or stuff bits
+#define SDIO_CMD52_WR_DATA 0
+//! CMD52 arg[    8] Reserved
+#define SDIO_CMD52_STUFF0 8
+//! CMD52 arg[25: 9] Register address
+#define SDIO_CMD52_REG_ADRR 9
+//! CMD52 arg[   26] Reserved
+#define SDIO_CMD52_STUFF1 26
+//! CMD52 arg[   27] Read after Write flag
+#define SDIO_CMD52_RAW_FLAG 27
+//! CMD52 arg[30:28] Number of the function
+#define SDIO_CMD52_FUNCTION_NUM 28
+//! CMD52 arg[   31] Direction, 1:write, 0:read.
+#define SDIO_CMD52_RW_FLAG 31
+#define SDIO_CMD52_READ_FLAG 0
+#define SDIO_CMD52_WRITE_FLAG 1
+//! @}
+
+//! \name SDIO CMD53 argument structure
+//! @{
+/**
+ * [ 8: 0] Byte mode: number of bytes to transfer,
+ *                    0 cause 512 bytes transfer.
+ *         Block mode: number of blocks to transfer,
+ *                    0 set count to infinite.
+ */
+#define SDIO_CMD53_COUNT 0
+//! CMD53 arg[25: 9] Start Address I/O register
+#define SDIO_CMD53_REG_ADDR 9
+//! CMD53 arg[   26] 1:Incrementing address, 0: fixed
+#define SDIO_CMD53_OP_CODE 26
+//! CMD53 arg[   27] (Optional) 1:block mode
+#define SDIO_CMD53_BLOCK_MODE 27
+//! CMD53 arg[30:28] Number of the function
+#define SDIO_CMD53_FUNCTION_NUM 28
+//! CMD53 arg[   31] Direction, 1:WR, 0:RD
+#define SDIO_CMD53_RW_FLAG 31
+#define SDIO_CMD53_READ_FLAG 0
+#define SDIO_CMD53_WRITE_FLAG 1
+//! @}
+
+//! \name SDIO Functions
+//! @{
+#define SDIO_CIA 0 /**< SDIO Function 0 (CIA) */
+#define SDIO_FN0 0 /**< SDIO Function 0 */
+#define SDIO_FN1 1 /**< SDIO Function 1 */
+#define SDIO_FN2 2 /**< SDIO Function 2 */
+#define SDIO_FN3 3 /**< SDIO Function 3 */
+#define SDIO_FN4 4 /**< SDIO Function 4 */
+#define SDIO_FN5 5 /**< SDIO Function 5 */
+#define SDIO_FN6 6 /**< SDIO Function 6 */
+#define SDIO_FN7 7 /**< SDIO Function 7 */
+                   //! @}
+
+//! \name SDIO Card Common Control Registers (CCCR)
+//! @{
+#define SDIO_CCCR_SDIO_REV 0x00         /**< CCCR/SDIO revision (RO) */
+#define SDIO_CCCR_REV (0xFlu << 0)      /**< CCCR/FBR Version */
+#define SDIO_CCCR_REV_1_00 (0x0lu << 0) /**< CCCR/FBR Version 1.00 */
+#define SDIO_CCCR_REV_1_10 (0x1lu << 0) /**< CCCR/FBR Version 1.10 */
+#define SDIO_CCCR_REV_2_00 (0x2lu << 0) /**< CCCR/FBR Version 2.00 */
+#define SDIO_CCCR_REV_3_00 (0x3lu << 0) /**< CCCR/FBR Version 3.00 */
+#define SDIO_SDIO_REV (0xFlu << 4)      /**< SDIO Spec */
+#define SDIO_SDIO_REV_1_00 (0x0lu << 4) /**< SDIO Spec 1.00 */
+#define SDIO_SDIO_REV_1_10 (0x1lu << 4) /**< SDIO Spec 1.10 */
+#define SDIO_SDIO_REV_1_20 (0x2lu << 4) /**< SDIO Spec 1.20(unreleased) */
+#define SDIO_SDIO_REV_2_00 (0x3lu << 4) /**< SDIO Spec Version 2.00 */
+#define SDIO_SDIO_REV_3_00 (0x4lu << 4) /**< SDIO Spec Version 3.00 */
+#define SDIO_CCCR_SD_REV 0x01           /**< SD Spec Revision (RO) */
+#define SDIO_SD_REV (0xFlu << 0)        /**< SD Physical Spec */
+#define SDIO_SD_REV_1_01 (0x0lu << 0)   /**< SD 1.01 (Mar 2000) */
+#define SDIO_SD_REV_1_10 (0x1lu << 0)   /**< SD 1.10 (Oct 2004) */
+#define SDIO_SD_REV_2_00 (0x2lu << 0)   /**< SD 2.00 (May 2006) */
+#define SDIO_SD_REV_3_00 (0x3lu << 0)   /**< SD 3.00 */
+#define SDIO_CCCR_IOE 0x02              /**< I/O Enable (R/W) */
+#define SDIO_IOE (0xFElu << 1)          /**< Functions Enable/Disable */
+#define SDIO_IOE_FN1 (0x1lu << 1)       /**< Function 1 Enable/Disable */
+#define SDIO_IOE_FN2 (0x1lu << 2)       /**< Function 2 Enable/Disable */
+#define SDIO_IOE_FN3 (0x1lu << 3)       /**< Function 3 Enable/Disable */
+#define SDIO_IOE_FN4 (0x1lu << 4)       /**< Function 4 Enable/Disable */
+#define SDIO_IOE_FN5 (0x1lu << 5)       /**< Function 5 Enable/Disable */
+#define SDIO_IOE_FN6 (0x1lu << 6)       /**< Function 6 Enable/Disable */
+#define SDIO_IOE_FN7 (0x1lu << 7)       /**< Function 7 Enable/Disable */
+#define SDIO_CCCR_IOR 0x03              /**< I/O Ready (RO) */
+#define SDIO_IOR (0xFElu << 1)          /**< Functions ready */
+#define SDIO_IOR_FN1 (0x1lu << 1)       /**< Function 1 ready */
+#define SDIO_IOR_FN2 (0x1lu << 2)       /**< Function 2 ready */
+#define SDIO_IOR_FN3 (0x1lu << 3)       /**< Function 3 ready */
+#define SDIO_IOR_FN4 (0x1lu << 4)       /**< Function 4 ready */
+#define SDIO_IOR_FN5 (0x1lu << 5)       /**< Function 5 ready */
+#define SDIO_IOR_FN6 (0x1lu << 6)       /**< Function 6 ready */
+#define SDIO_IOR_FN7 (0x1lu << 7)       /**< Function 7 ready */
+#define SDIO_CCCR_IEN 0x04              /**< Int Enable */
+#define SDIO_IENM (0x1lu << 0)          /**< Int Enable Master (R/W) */
+#define SDIO_IEN (0xFElu << 1)          /**< Functions Int Enable */
+#define SDIO_IEN_FN1 (0x1lu << 1)       /**< Function 1 Int Enable */
+#define SDIO_IEN_FN2 (0x1lu << 2)       /**< Function 2 Int Enable */
+#define SDIO_IEN_FN3 (0x1lu << 3)       /**< Function 3 Int Enable */
+#define SDIO_IEN_FN4 (0x1lu << 4)       /**< Function 4 Int Enable */
+#define SDIO_IEN_FN5 (0x1lu << 5)       /**< Function 5 Int Enable */
+#define SDIO_IEN_FN6 (0x1lu << 6)       /**< Function 6 Int Enable */
+#define SDIO_IEN_FN7 (0x1lu << 7)       /**< Function 7 Int Enable */
+#define SDIO_CCCR_INT 0x05              /**< Int Pending */
+#define SDIO_INT (0xFElu << 1)          /**< Functions Int pending */
+#define SDIO_INT_FN1 (0x1lu << 1)       /**< Function 1 Int pending */
+#define SDIO_INT_FN2 (0x1lu << 2)       /**< Function 2 Int pending */
+#define SDIO_INT_FN3 (0x1lu << 3)       /**< Function 3 Int pending */
+#define SDIO_INT_FN4 (0x1lu << 4)       /**< Function 4 Int pending */
+#define SDIO_INT_FN5 (0x1lu << 5)       /**< Function 5 Int pending */
+#define SDIO_INT_FN6 (0x1lu << 6)       /**< Function 6 Int pending */
+#define SDIO_INT_FN7 (0x1lu << 7)       /**< Function 7 Int pending */
+#define SDIO_CCCR_IOA 0x06              /**< I/O Abort */
+#define SDIO_AS (0x7lu << 0)            /**< Abort Select In Order (WO) */
+#define SDIO_AS_FN1 (0x1lu << 0)        /**< Abort function 1 IO */
+#define SDIO_AS_FN2 (0x2lu << 0)        /**< Abort function 2 IO */
+#define SDIO_AS_FN3 (0x3lu << 0)        /**< Abort function 3 IO */
+#define SDIO_AS_FN4 (0x4lu << 0)        /**< Abort function 4 IO */
+#define SDIO_AS_FN5 (0x5lu << 0)        /**< Abort function 5 IO */
+#define SDIO_AS_FN6 (0x6lu << 0)        /**< Abort function 6 IO */
+#define SDIO_AS_FN7 (0x7lu << 0)        /**< Abort function 7 IO */
+#define SDIO_RES (0x1lu << 3)           /**< IO CARD RESET (WO) */
+#define SDIO_CCCR_BUS_CTRL 0x07         /**< Bus Interface Control */
+#define SDIO_BUSWIDTH (0x3lu << 0)      /**< Data bus width (R/W) */
+#define SDIO_BUSWIDTH_1B (0x0lu << 0)   /**< 1-bit data bus */
+#define SDIO_BUSWIDTH_4B (0x2lu << 0)   /**< 4-bit data bus */
+/** Enable Continuous SPI interrupt (R/W) */
+#define SDIO_BUS_ECSI (0x1lu << 5)
+/** Support Continuous SPI interrupt (RO) */
+#define SDIO_BUS_SCSI (0x1lu << 6)
+/** Connect(0)/Disconnect(1) pull-up on CD/DAT[3] (R/W) */
+#define SDIO_BUS_CD_DISABLE (0x1lu << 7)
+#define SDIO_CCCR_CAP 0x08 /**< Card Capability */
+/** Support Direct Commands during data transfer (RO) */
+#define SDIO_CAP_SDC (0x1lu << 0)
+/** Support Multi-Block (RO) */
+#define SDIO_CAP_SMB (0x1lu << 1)
+/** Support Read Wait (RO) */
+#define SDIO_CAP_SRW (0x1lu << 2)
+/** Support Suspend/Resume (RO) */
+#define SDIO_CAP_SBS (0x1lu << 3)
+/** Support interrupt between blocks of data in 4-bit SD mode (RO) */
+#define SDIO_CAP_S4MI (0x1lu << 4)
+/** Enable interrupt between blocks of data in 4-bit SD mode (R/W) */
+#define SDIO_CAP_E4MI (0x1lu << 5)
+/** Low-Speed Card (RO) */
+#define SDIO_CAP_LSC (0x1lu << 6)
+/** 4-bit support for Low-Speed Card (RO) */
+#define SDIO_CAP_4BLS (0x1lu << 7)
+/** Pointer to CIS (3B, LSB first) */
+#define SDIO_CCCR_CIS_PTR 0x09
+/** Bus Suspend */
+#define SDIO_CCCR_BUS_SUSPEND 0x0C
+/** Bus Status (transfer on DAT[x] lines) (RO) */
+#define SDIO_BS (0x1lu << 0)
+/** Bus Release Request/Status (R/W) */
+#define SDIO_BR (0x1lu << 1)
+#define SDIO_CCCR_FUN_SEL 0x0D    /**< Function select */
+#define SDIO_DF (0x1lu << 7)      /**< Resume Data Flag (RO) */
+#define SDIO_FS (0xFlu << 0)      /**< Select Function (R/W) */
+#define SDIO_FS_CIA (0x0lu << 0)  /**< Select CIA (function 0) */
+#define SDIO_FS_FN1 (0x1lu << 0)  /**< Select Function 1 */
+#define SDIO_FS_FN2 (0x2lu << 0)  /**< Select Function 2 */
+#define SDIO_FS_FN3 (0x3lu << 0)  /**< Select Function 3 */
+#define SDIO_FS_FN4 (0x4lu << 0)  /**< Select Function 4 */
+#define SDIO_FS_FN5 (0x5lu << 0)  /**< Select Function 5 */
+#define SDIO_FS_FN6 (0x6lu << 0)  /**< Select Function 6 */
+#define SDIO_FS_FN7 (0x7lu << 0)  /**< Select Function 7 */
+#define SDIO_FS_MEM (0x8lu << 0)  /**< Select memory in combo card */
+#define SDIO_CCCR_EXEC 0x0E       /**< Exec Flags (RO) */
+#define SDIO_EXM (0x1lu << 0)     /**< Executing status of memory */
+#define SDIO_EX (0xFElu << 1)     /**< Executing functions status */
+#define SDIO_EX_FN1 (0x1lu << 1)  /**< Executing status of func 1 */
+#define SDIO_EX_FN2 (0x1lu << 2)  /**< Executing status of func 2 */
+#define SDIO_EX_FN3 (0x1lu << 3)  /**< Executing status of func 3 */
+#define SDIO_EX_FN4 (0x1lu << 4)  /**< Executing status of func 4 */
+#define SDIO_EX_FN5 (0x1lu << 5)  /**< Executing status of func 5 */
+#define SDIO_EX_FN6 (0x1lu << 6)  /**< Executing status of func 6 */
+#define SDIO_EX_FN7 (0x1lu << 7)  /**< Executing status of func 7 */
+#define SDIO_CCCR_READY 0x0F      /**< Ready Flags (RO) */
+#define SDIO_RFM (0x1lu << 0)     /**< Ready Flag for memory */
+#define SDIO_RF (0xFElu)          /**< Ready Flag for functions */
+#define SDIO_RF_FN1 (0x1lu << 1)  /**< Ready Flag for function 1 */
+#define SDIO_RF_FN2 (0x1lu << 2)  /**< Ready Flag for function 2 */
+#define SDIO_RF_FN3 (0x1lu << 3)  /**< Ready Flag for function 3 */
+#define SDIO_RF_FN4 (0x1lu << 4)  /**< Ready Flag for function 4 */
+#define SDIO_RF_FN5 (0x1lu << 5)  /**< Ready Flag for function 5 */
+#define SDIO_RF_FN6 (0x1lu << 6)  /**< Ready Flag for function 6 */
+#define SDIO_RF_FN7 (0x1lu << 7)  /**< Ready Flag for function 7 */
+#define SDIO_CCCR_FN0_BLKSIZ 0x10 /**< FN0 Block Size (2B, LSB first) (R/W) */
+#define SDIO_CCCR_POWER 0x12      /**< Power Control */
+#define SDIO_SMPC (0x1lu << 0)    /**< Support Master Power Control*/
+#define SDIO_EMPC (0x1lu << 1)    /**< Enable Master Power Control */
+#define SDIO_CCCR_HS 0x13         /**< High-Speed */
+#define SDIO_SHS (0x1lu << 0)     /**< Support High-Speed (RO) */
+#define SDIO_EHS (0x1lu << 1)     /**< Enable High-Speed (R/W) */
+                                  //! @}
+
+//! \name SDIO Function Basic Registers (FBR)
+//! @{
+#define SDIO_FBR_ADDR(fn, x) (0x100 * (fn) + (x))
+#define SDIO_FBR_CSA_IF 0x0          /**< CSA and function interface code (RO) */
+#define SDIO_IFC (0xFUL << 0)        /**< Standard SDIO Fun Interface Code */
+#define SDIO_IFC_NO_IF (0x0UL << 0)  /**< No SDIO standard interface */
+#define SDIO_IFC_UART (0x1UL << 0)   /**< UART */
+#define SDIO_IFC_TA_BT (0x2UL << 0)  /**< Type-A Bluetooth */
+#define SDIO_IFC_TB_BT (0x3UL << 0)  /**< Type-B Bluetooth */
+#define SDIO_IFC_GPS (0x4UL << 0)    /**< GPS */
+#define SDIO_IFC_CAMERA (0x5UL << 0) /**< Camera */
+#define SDIO_IFC_PHS (0x6UL << 0)    /**< PHS */
+#define SDIO_IFC_WLAN (0x7UL << 0)   /**< WLAN */
+#define SDIO_IFC_ATA (0x8UL << 0)    /**< Embedded SDIO-ATA */
+#define SDIO_IFC_EXT (0xFUL << 0)    /**< Check EXT interface code */
+#define SDIO_SCSA (0x1UL << 6)       /**< Function supports Code Storage Area (CSA) */
+#define SDIO_FBR_CSA (0x1UL << 7)    /**< Function CSA enable */
+#define SDIO_FBR_EXT_IF 0x1          /**< Extended function interface code (RO) */
+#define SDIO_FBR_PWR 0x2             /**< function power control */
+#define SDIO_SPS (0x1UL << 0)        /**< function support power selection (RO) */
+#define SDIO_EPS (0x1UL << 1)        /**< Low Current Mode/High Current Mode (R/W) */
+#define SDIO_FBR_CIS_PTR 0x9         /**< Address pointer to function CIS (3B, LSB first) (RO) */
+#define SDIO_FBR_CSA_PTR 0xC         /**< Address pointer to CSA (3B, LSB first) (R/W) */
+#define SDIO_FBR_CSA_DATA 0xF        /**< Read/Write fifo to CSA (R/W) */
+#define SDIO_FBR_BLK_SIZ 0x10        /**< Block size (2B, LSB first) (R/W) */
+                                     //! @}
+
+//! \name SDIO Card Metaformat
+//! @{
+/** Null tuple (PCMCIA 3.1.9) */
+#define SDIO_CISTPL_NULL 0x00
+/** Device tuple (PCMCIA 3.2.2) */
+#define SDIO_CISTPL_DEVICE 0x01
+/** Checksum control (PCMCIA 3.1.1) */
+#define SDIO_CISTPL_CHECKSUM 0x10
+/** Level 1 version (PCMCIA 3.2.10) */
+#define SDIO_CISTPL_VERS_1 0x15
+/** Alternate Language String (PCMCIA 3.2.1) */
+#define SDIO_CISTPL_ALTSTR 0x16
+/** Manufacturer Identification String (PCMCIA 3.2.9) */
+#define SDIO_CISTPL_MANFID 0x20
+/** Function Identification (PCMCIA 3.2.7) */
+#define SDIO_CISTPL_FUNCID 0x21
+/** Function Extensions (PCMCIA 3.2.6) */
+#define SDIO_CISTPL_FUNCE 0x22
+/** Additional information for SDIO (PCMCIA 6.1.2) */
+#define SDIO_CISTPL_SDIO_STD 0x91
+/** Reserved for future SDIO (PCMCIA 6.1.3) */
+#define SDIO_CISTPL_SDIO_EXT 0x92
+/** The End-of-chain Tuple (PCMCIA 3.1.2) */
+#define SDIO_CISTPL_END 0xFF
+//! @}
+
+//! @}
+
+//! \name CSD, OCR, SCR, Switch status, extend CSD definitions
+//! @{
+
+/**
+ * \brief Macro function to extract a bits field from a large SD MMC register
+ * Used by : CSD, SCR, Switch status
+ */
+static inline uint32_t SDMMC_UNSTUFF_BITS(uint8_t *reg, uint16_t reg_size, uint16_t pos, uint8_t size)
+{
+	uint32_t value;
+	value = reg[((reg_size - pos + 7) / 8) - 1] >> (pos % 8);
+	if (((pos % 8) + size) > 8) {
+		value |= (uint32_t)reg[((reg_size - pos + 7) / 8) - 2] << (8 - (pos % 8));
+	}
+	if (((pos % 8) + size) > 16) {
+		value |= (uint32_t)reg[((reg_size - pos + 7) / 8) - 3] << (16 - (pos % 8));
+	}
+	if (((pos % 8) + size) > 24) {
+		value |= (uint32_t)reg[((reg_size - pos + 7) / 8) - 3] << (24 - (pos % 8));
+	}
+	value &= ((uint32_t)1 << size) - 1;
+	return value;
+}
+
+	//! \name CSD Fields
+	//! @{
+#define CSD_REG_BIT_SIZE 128                 //!< 128 bits
+#define CSD_REG_BSIZE (CSD_REG_BIT_SIZE / 8) //!< 16 bytes
+#define CSD_STRUCTURE(csd, pos, size) SDMMC_UNSTUFF_BITS(csd, CSD_REG_BIT_SIZE, pos, size)
+#define CSD_STRUCTURE_VERSION(csd) CSD_STRUCTURE(csd, 126, 2)
+#define SD_CSD_VER_1_0 0
+#define SD_CSD_VER_2_0 1
+#define MMC_CSD_VER_1_0 0
+#define MMC_CSD_VER_1_1 1
+#define MMC_CSD_VER_1_2 2
+#define CSD_TRAN_SPEED(csd) CSD_STRUCTURE(csd, 96, 8)
+#define SD_CSD_1_0_C_SIZE(csd) CSD_STRUCTURE(csd, 62, 12)
+#define SD_CSD_1_0_C_SIZE_MULT(csd) CSD_STRUCTURE(csd, 47, 3)
+#define SD_CSD_1_0_READ_BL_LEN(csd) CSD_STRUCTURE(csd, 80, 4)
+#define SD_CSD_2_0_C_SIZE(csd) CSD_STRUCTURE(csd, 48, 22)
+#define MMC_CSD_C_SIZE(csd) CSD_STRUCTURE(csd, 62, 12)
+#define MMC_CSD_C_SIZE_MULT(csd) CSD_STRUCTURE(csd, 47, 3)
+#define MMC_CSD_READ_BL_LEN(csd) CSD_STRUCTURE(csd, 80, 4)
+#define MMC_CSD_SPEC_VERS(csd) CSD_STRUCTURE(csd, 122, 4)
+	//! @}
+
+	//! \name OCR Register Fields
+	//! @{
+#define OCR_REG_BSIZE (32 / 8) /**< 32 bits, 4 bytes */
+#define OCR_VDD_170_195 (1lu << 7)
+#define OCR_VDD_20_21 (1lu << 8)
+#define OCR_VDD_21_22 (1lu << 9)
+#define OCR_VDD_22_23 (1lu << 10)
+#define OCR_VDD_23_24 (1lu << 11)
+#define OCR_VDD_24_25 (1lu << 12)
+#define OCR_VDD_25_26 (1lu << 13)
+#define OCR_VDD_26_27 (1lu << 14)
+#define OCR_VDD_27_28 (1lu << 15)
+#define OCR_VDD_28_29 (1lu << 16)
+#define OCR_VDD_29_30 (1lu << 17)
+#define OCR_VDD_30_31 (1lu << 18)
+#define OCR_VDD_31_32 (1lu << 19)
+#define OCR_VDD_32_33 (1lu << 20)
+#define OCR_VDD_33_34 (1lu << 21)
+#define OCR_VDD_34_35 (1lu << 22)
+#define OCR_VDD_35_36 (1lu << 23)
+#define OCR_SDIO_S18R (1lu << 24)          /**< Switching to 1.8V Accepted */
+#define OCR_SDIO_MP (1lu << 27)            /**< Memory Present */
+#define OCR_SDIO_NF (7lu << 28)            /**< Number of I/O Functions */
+#define OCR_ACCESS_MODE_MASK (3lu << 29)   /**< (MMC) Access mode mask */
+#define OCR_ACCESS_MODE_BYTE (0lu << 29)   /**< (MMC) Byte access mode */
+#define OCR_ACCESS_MODE_SECTOR (2lu << 29) /**< (MMC) Sector access mode */
+#define OCR_CCS (1lu << 30)                /**< (SD) Card Capacity Status */
+#define OCR_POWER_UP_BUSY (1lu << 31)      /**< Card power up status bit */
+	                                       //! @}
+
+	//! \name SD SCR Register Fields
+	//! @{
+#define SD_SCR_REG_BIT_SIZE 64                     //!< 64 bits
+#define SD_SCR_REG_BSIZE (SD_SCR_REG_BIT_SIZE / 8) //!< 8 bytes
+#define SD_SCR_STRUCTURE(scr, pos, size) SDMMC_UNSTUFF_BITS(scr, SD_SCR_REG_BIT_SIZE, pos, size)
+#define SD_SCR_SCR_STRUCTURE(scr) SD_SCR_STRUCTURE(scr, 60, 4)
+#define SD_SCR_SCR_STRUCTURE_1_0 0
+#define SD_SCR_SD_SPEC(scr) SD_SCR_STRUCTURE(scr, 56, 4)
+#define SD_SCR_SD_SPEC_1_0_01 0
+#define SD_SCR_SD_SPEC_1_10 1
+#define SD_SCR_SD_SPEC_2_00 2
+#define SD_SCR_DATA_STATUS_AFTER_ERASE(scr) SD_SCR_STRUCTURE(scr, 55, 1)
+#define SD_SCR_SD_SECURITY(scr) SD_SCR_STRUCTURE(scr, 52, 3)
+#define SD_SCR_SD_SECURITY_NO 0
+#define SD_SCR_SD_SECURITY_NOTUSED 1
+#define SD_SCR_SD_SECURITY_1_01 2
+#define SD_SCR_SD_SECURITY_2_00 3
+#define SD_SCR_SD_SECURITY_3_00 4
+#define SD_SCR_SD_BUS_WIDTHS(scr) SD_SCR_STRUCTURE(scr, 48, 4)
+#define SD_SCR_SD_BUS_WIDTH_1BITS (1lu << 0)
+#define SD_SCR_SD_BUS_WIDTH_4BITS (1lu << 2)
+#define SD_SCR_SD_SPEC3(scr) SD_SCR_STRUCTURE(scr, 47, 1)
+#define SD_SCR_SD_SPEC_3_00 1
+#define SD_SCR_SD_EX_SECURITY(scr) SD_SCR_STRUCTURE(scr, 43, 4)
+#define SD_SCR_SD_CMD_SUPPORT(scr) SD_SCR_STRUCTURE(scr, 32, 2)
+	//! @}
+
+	//! \name SD Switch Status Fields
+	//! @{
+#define SD_SW_STATUS_BIT_SIZE 512                      //!< 512 bits
+#define SD_SW_STATUS_BSIZE (SD_SW_STATUS_BIT_SIZE / 8) //!< 64 bytes
+#define SD_SW_STATUS_STRUCTURE(sd_sw_status, pos, size)                                                                \
+	SDMMC_UNSTUFF_BITS(sd_sw_status, SD_SW_STATUS_BIT_SIZE, pos, size)
+#define SD_SW_STATUS_MAX_CURRENT_CONSUMPTION(status) SD_SW_STATUS_STRUCTURE(status, 496, 16)
+#define SD_SW_STATUS_FUN_GRP6_INFO(status) SD_SW_STATUS_STRUCTURE(status, 480, 16)
+#define SD_SW_STATUS_FUN_GRP5_INFO(status) SD_SW_STATUS_STRUCTURE(status, 464, 16)
+#define SD_SW_STATUS_FUN_GRP4_INFO(status) SD_SW_STATUS_STRUCTURE(status, 448, 16)
+#define SD_SW_STATUS_FUN_GRP3_INFO(status) SD_SW_STATUS_STRUCTURE(status, 432, 16)
+#define SD_SW_STATUS_FUN_GRP2_INFO(status) SD_SW_STATUS_STRUCTURE(status, 416, 16)
+#define SD_SW_STATUS_FUN_GRP1_INFO(status) SD_SW_STATUS_STRUCTURE(status, 400, 16)
+#define SD_SW_STATUS_FUN_GRP6_RC(status) SD_SW_STATUS_STRUCTURE(status, 396, 4)
+#define SD_SW_STATUS_FUN_GRP5_RC(status) SD_SW_STATUS_STRUCTURE(status, 392, 4)
+#define SD_SW_STATUS_FUN_GRP4_RC(status) SD_SW_STATUS_STRUCTURE(status, 388, 4)
+#define SD_SW_STATUS_FUN_GRP3_RC(status) SD_SW_STATUS_STRUCTURE(status, 384, 4)
+#define SD_SW_STATUS_FUN_GRP2_RC(status) SD_SW_STATUS_STRUCTURE(status, 380, 4)
+#define SD_SW_STATUS_FUN_GRP1_RC(status) SD_SW_STATUS_STRUCTURE(status, 376, 4)
+#define SD_SW_STATUS_FUN_GRP_RC_ERROR 0xFU
+#define SD_SW_STATUS_DATA_STRUCT_VER(status) SD_SW_STATUS_STRUCTURE(status, 368, 8)
+#define SD_SW_STATUS_FUN_GRP6_BUSY(status) SD_SW_STATUS_STRUCTURE(status, 352, 16)
+#define SD_SW_STATUS_FUN_GRP5_BUSY(status) SD_SW_STATUS_STRUCTURE(status, 336, 16)
+#define SD_SW_STATUS_FUN_GRP4_BUSY(status) SD_SW_STATUS_STRUCTURE(status, 320, 16)
+#define SD_SW_STATUS_FUN_GRP3_BUSY(status) SD_SW_STATUS_STRUCTURE(status, 304, 16)
+#define SD_SW_STATUS_FUN_GRP2_BUSY(status) SD_SW_STATUS_STRUCTURE(status, 288, 16)
+#define SD_SW_STATUS_FUN_GRP1_BUSY(status) SD_SW_STATUS_STRUCTURE(status, 272, 16)
+	//! @}
+
+	//! \name Card Status Fields
+	//! @{
+#define CARD_STATUS_APP_CMD (1lu << 5)
+#define CARD_STATUS_SWITCH_ERROR (1lu << 7)
+#define CARD_STATUS_READY_FOR_DATA (1lu << 8)
+#define CARD_STATUS_STATE_IDLE (0lu << 9)
+#define CARD_STATUS_STATE_READY (1lu << 9)
+#define CARD_STATUS_STATE_IDENT (2lu << 9)
+#define CARD_STATUS_STATE_STBY (3lu << 9)
+#define CARD_STATUS_STATE_TRAN (4lu << 9)
+#define CARD_STATUS_STATE_DATA (5lu << 9)
+#define CARD_STATUS_STATE_RCV (6lu << 9)
+#define CARD_STATUS_STATE_PRG (7lu << 9)
+#define CARD_STATUS_STATE_DIS (8lu << 9)
+#define CARD_STATUS_STATE (0xFlu << 9)
+#define CARD_STATUS_ERASE_RESET (1lu << 13)
+#define CARD_STATUS_WP_ERASE_SKIP (1lu << 15)
+#define CARD_STATUS_CIDCSD_OVERWRITE (1lu << 16)
+#define CARD_STATUS_OVERRUN (1lu << 17)
+#define CARD_STATUS_UNERRUN (1lu << 18)
+#define CARD_STATUS_ERROR (1lu << 19)
+#define CARD_STATUS_CC_ERROR (1lu << 20)
+#define CARD_STATUS_CARD_ECC_FAILED (1lu << 21)
+#define CARD_STATUS_ILLEGAL_COMMAND (1lu << 22)
+#define CARD_STATUS_COM_CRC_ERROR (1lu << 23)
+#define CARD_STATUS_UNLOCK_FAILED (1lu << 24)
+#define CARD_STATUS_CARD_IS_LOCKED (1lu << 25)
+#define CARD_STATUS_WP_VIOLATION (1lu << 26)
+#define CARD_STATUS_ERASE_PARAM (1lu << 27)
+#define CARD_STATUS_ERASE_SEQ_ERROR (1lu << 28)
+#define CARD_STATUS_BLOCK_LEN_ERROR (1lu << 29)
+#define CARD_STATUS_ADDRESS_MISALIGN (1lu << 30)
+#define CARD_STATUS_ADDR_OUT_OF_RANGE (1lu << 31)
+
+#define CARD_STATUS_ERR_RD_WR                                                                                          \
+	(CARD_STATUS_ADDR_OUT_OF_RANGE | CARD_STATUS_ADDRESS_MISALIGN | CARD_STATUS_BLOCK_LEN_ERROR                        \
+	 | CARD_STATUS_WP_VIOLATION | CARD_STATUS_ILLEGAL_COMMAND | CARD_STATUS_CC_ERROR | CARD_STATUS_ERROR)
+	//! @}
+
+	//! \name SD Status Field
+	//! @{
+#define SD_STATUS_BSIZE (512 / 8) /**< 512 bits, 64bytes */
+	                              //! @}
+
+	//! \name MMC Extended CSD Register Field
+	//! @{
+#define EXT_CSD_BSIZE 512 /**< 512 bytes. */
+/* Below belongs to Properties Segment */
+#define EXT_CSD_S_CMD_SET_INDEX 504lu
+#define EXT_CSD_BOOT_INFO_INDEX 228lu
+#define EXT_CSD_BOOT_SIZE_MULTI_INDEX 226lu
+#define EXT_CSD_ACC_SIZE_INDEX 225lu
+#define EXT_CSD_HC_ERASE_GRP_SIZE_INDEX 224lu
+#define EXT_CSD_ERASE_TIMEOUT_MULT_INDEX 223lu
+#define EXT_CSD_REL_WR_SEC_C_INDEX 222lu
+#define EXT_CSD_HC_WP_GRP_SIZE_INDEX 221lu
+#define EXT_CSD_S_C_VCC_INDEX 220lu
+#define EXT_CSD_S_C_VCCQ_INDEX 219lu
+#define EXT_CSD_S_A_TIMEOUT_INDEX 217lu
+#define EXT_CSD_SEC_COUNT_INDEX 212lu
+#define EXT_CSD_MIN_PERF_W_8_52_INDEX 210lu
+#define EXT_CSD_MIN_PERF_R_8_52_INDEX 209lu
+#define EXT_CSD_MIN_PERF_W_8_26_4_52_INDEX 208lu
+#define EXT_CSD_MIN_PERF_R_8_26_4_52_INDEX 207lu
+#define EXT_CSD_MIN_PERF_W_4_26_INDEX 206lu
+#define EXT_CSD_MIN_PERF_R_4_26_INDEX 205lu
+#define EXT_CSD_PWR_CL_26_360_INDEX 203lu
+#define EXT_CSD_PWR_CL_52_360_INDEX 202lu
+#define EXT_CSD_PWR_CL_26_195_INDEX 201lu
+#define EXT_CSD_PWR_CL_52_195_INDEX 200lu
+#define EXT_CSD_CARD_TYPE_INDEX 196lu
+/* MMC card type */
+#define MMC_CTYPE_26MHZ 0x1
+#define MMC_CTYPE_52MHZ 0x2
+#define EXT_CSD_CSD_STRUCTURE_INDEX 194lu
+#define EXT_CSD_EXT_CSD_REV_INDEX 192lu
+
+/* Below belongs to Mode Segment */
+#define EXT_CSD_CMD_SET_INDEX 191lu
+#define EXT_CSD_CMD_SET_REV_INDEX 189lu
+#define EXT_CSD_POWER_CLASS_INDEX 187lu
+#define EXT_CSD_HS_TIMING_INDEX 185lu
+#define EXT_CSD_BUS_WIDTH_INDEX 183lu
+#define EXT_CSD_ERASED_MEM_CONT_INDEX 181lu
+#define EXT_CSD_BOOT_CONFIG_INDEX 179lu
+#define EXT_CSD_BOOT_BUS_WIDTH_INDEX 177lu
+#define EXT_CSD_ERASE_GROUP_DEF_INDEX 175lu
+	//! @}
+//! @}
+
+//! \name Definition for SPI mode only
+//! @{
+
+//! SPI commands start with a start bit "0" and a transmit bit "1"
+#define SPI_CMD_ENCODE(x) (0x40 | (x & 0x3F))
+
+//! \name Register R1 definition for SPI mode
+//! The R1 register is always send after a command.
+//! @{
+#define R1_SPI_IDLE (1lu << 0)
+#define R1_SPI_ERASE_RESET (1lu << 1)
+#define R1_SPI_ILLEGAL_COMMAND (1lu << 2)
+#define R1_SPI_COM_CRC (1lu << 3)
+#define R1_SPI_ERASE_SEQ (1lu << 4)
+#define R1_SPI_ADDRESS (1lu << 5)
+#define R1_SPI_PARAMETER (1lu << 6)
+// R1 bit 7 is always zero, reuse this bit for error
+#define R1_SPI_ERROR (1lu << 7)
+//! @}
+
+//! \name Register R2 definition for SPI mode
+//! The R2 register can be send after R1 register.
+//! @{
+#define R2_SPI_CARD_LOCKED (1lu << 0)
+#define R2_SPI_WP_ERASE_SKIP (1lu << 1)
+#define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP
+#define R2_SPI_ERROR (1lu << 2)
+#define R2_SPI_CC_ERROR (1lu << 3)
+#define R2_SPI_CARD_ECC_ERROR (1lu << 4)
+#define R2_SPI_WP_VIOLATION (1lu << 5)
+#define R2_SPI_ERASE_PARAM (1lu << 6)
+#define R2_SPI_OUT_OF_RANGE (1lu << 7)
+#define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE
+//! @}
+
+//! \name Control Tokens in SPI Mode
+//! @{
+//! \name Tokens used for a read operation
+//! @{
+#define SPI_TOKEN_SINGLE_MULTI_READ 0xFE
+#define SPI_TOKEN_DATA_ERROR_VALID(token) (((token)&0xF0) == 0)
+#define SPI_TOKEN_DATA_ERROR_ERRORS (0x0F)
+#define SPI_TOKEN_DATA_ERROR_ERROR (1lu << 0)
+#define SPI_TOKEN_DATA_ERROR_CC_ERROR (1lu << 1)
+#define SPI_TOKEN_DATA_ERROR_ECC_ERROR (1lu << 2)
+#define SPI_TOKEN_DATA_ERROR_OUT_RANGE (1lu << 3)
+	//! @}
+	//! \name Tokens used for a write operation
+	//! @{
+#define SPI_TOKEN_SINGLE_WRITE 0xFE
+#define SPI_TOKEN_MULTI_WRITE 0xFC
+#define SPI_TOKEN_STOP_TRAN 0xFD
+#define SPI_TOKEN_DATA_RESP_VALID(token) ((((token) & (1 << 4)) == 0) && (((token) & (1 << 0)) == 1))
+#define SPI_TOKEN_DATA_RESP_CODE(token) ((token)&0x1E)
+#define SPI_TOKEN_DATA_RESP_ACCEPTED (2lu << 1)
+#define SPI_TOKEN_DATA_RESP_CRC_ERR (5lu << 1)
+#define SPI_TOKEN_DATA_RESP_WRITE_ERR (6lu << 1)
+	//! @}
+	//! @}
+	//! @}
+
+	//! @} end of sd_mmc_protocol
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SD_MMC_PROTOCOL_H_INCLUDED */
diff --git a/sd_mmc/sd_mmc_spi.c b/sd_mmc/sd_mmc_spi.c
new file mode 100644
index 0000000..4a82ccc
--- /dev/null
+++ b/sd_mmc/sd_mmc_spi.c
@@ -0,0 +1,521 @@
+#include "sd_mmc_spi.h"
+#include "atmel_start_pins.h"
+#include "hal_io.h"
+#include "hal_spi_m_sync.h"
+#include "sd_mmc_protocol.h"
+
+static inline void sd_mmc_device_enable()
+{
+	PORT->Group[1].OUT.reg &= ~(1 << SPI_CS_PIN);
+}
+
+static inline void sd_mmc_device_disable()
+{
+	PORT->Group[1].OUT.reg |= (1 << SPI_CS_PIN);
+}
+static sd_mmc_spi_errno_t sd_mmc_spi_err;
+
+// 32 bits response of the last command
+static uint32_t sd_mmc_spi_response_32;
+
+// Current position (byte) of the transfer started by spi_m_sync_adtc_start()
+static uint32_t sd_mmc_spi_transfert_pos;
+
+// Size block requested by last spi_m_sync_adtc_start()
+static uint16_t sd_mmc_spi_block_size;
+
+// Total number of block requested by last spi_m_sync_adtc_start()
+static uint16_t sd_mmc_spi_nb_block;
+
+static uint8_t spi_m_sync_crc7(uint8_t * buf, uint8_t size)
+{
+	uint8_t crc, value, i;
+
+	crc = 0;
+	while (size--) {
+		value = *buf++;
+		for (i = 0; i < 8; i++) {
+			crc <<= 1;
+			if ((value & 0x80) ^ (crc & 0x80)) {
+				crc ^= 0x09;
+			}
+			value <<= 1;
+		}
+	}
+	crc = (crc << 1) | 1;
+	return crc;
+}
+
+static bool spi_m_sync_wait_busy(struct spi_m_sync_descriptor* spi)
+{
+	uint8_t line = 0xFF;
+	uint8_t dummy = 0xFF;
+
+	/* Delay before check busy
+	 * Nbr timing minimum = 8 cylces
+	 */
+
+	struct io_descriptor* spi_inst = NULL;
+	spi_m_sync_get_io_descriptor(spi, &spi_inst);
+	io_write(spi_inst, &dummy, 1);
+	io_read(spi_inst, &line, 1);
+	/* Wait end of busy signal
+	 * Nec timing: 0 to unlimited
+	 * However a timeout is used.
+	 * 200 000 * 8 cycles
+	 */
+	uint32_t nec_timeout = 200000;
+	io_write(spi_inst, &dummy, 1);
+	io_read(spi_inst, &line, 1);
+	do {
+		io_write(spi_inst, &dummy, 1);
+		io_read(spi_inst, &line, 1);
+		if (!(nec_timeout--)) {
+			return false;
+		}
+	} while (line != 0xFF);
+	return true;
+}
+
+static void spi_m_sync_start_write_block(struct spi_m_sync_descriptor* spi)
+{
+	struct io_descriptor* spi_inst = NULL;
+	spi_m_sync_get_io_descriptor(spi, &spi_inst);
+	uint8_t dummy = 0xFF;
+	assert(!(sd_mmc_spi_transfert_pos %sd_mmc_spi_block_size), ">>>");
+	// Delay before start writing block:
+	// Nwr timing minimum = 8 cycles
+	io_write(spi_inst, &dummy, 1);
+	// Send start token
+	uint8_t token;
+	if (1 == sd_mmc_spi_nb_block)
+	{
+		token = SPI_TOKEN_SINGLE_WRITE;
+	}
+	else
+	{
+		token = SPI_TOKEN_MULTI_WRITE;
+	}
+	io_write(spi_inst, &token, 1);
+}
+
+static bool spi_m_sync_stop_write_block(struct spi_m_sync_descriptor* spi)
+{
+	struct io_descriptor* spi_inst = NULL;
+	spi_m_sync_get_io_descriptor(spi, &spi_inst);
+	uint8_t resp;
+	uint16_t crc;
+	uint8_t dummy = 0xFF;
+
+	// Send CRC
+	crc = 0xFFFF; /// CRC is disabled in SPI mode
+	io_write(spi_inst, (uint8_t*)&crc, 2);
+	// Receiv data response token
+	io_write(spi_inst, &dummy, 1);
+	io_read(spi_inst, &resp, 1);
+	if (!SPI_TOKEN_DATA_RESP_VALID(resp)) {
+		sd_mmc_spi_err = SD_MMC_SPI_ERR;
+		sd_mmc_spi_debug("%s: Invalid Data Response Token 0x%x\n\r", __func__, resp);
+		return false;
+	}
+	// Check data response
+	switch (SPI_TOKEN_DATA_RESP_CODE(resp)) {
+	case SPI_TOKEN_DATA_RESP_ACCEPTED:
+		break;
+	case SPI_TOKEN_DATA_RESP_CRC_ERR:
+		sd_mmc_spi_err = SD_MMC_SPI_ERR_WRITE_CRC;
+		sd_mmc_spi_debug("%s: Write blocks, SD_MMC_SPI_ERR_CRC, resp 0x%x\n\r",
+				__func__, resp);
+		return false;
+	case SPI_TOKEN_DATA_RESP_WRITE_ERR:
+	default:
+		sd_mmc_spi_err = SD_MMC_SPI_ERR_WRITE;
+		sd_mmc_spi_debug("%s: Write blocks SD_MMC_SPI_ERR_WR, resp 0x%x\n\r",
+				__func__, resp);
+		return false;
+	}
+	return true;
+}
+
+static bool spi_m_sync_stop_multiwrite_block(struct spi_m_sync_descriptor* spi)
+{
+	struct io_descriptor* spi_inst = NULL;
+	spi_m_sync_get_io_descriptor(spi, &spi_inst);
+	uint8_t value;
+
+	if (1 == sd_mmc_spi_nb_block) {
+		return true; // Single block write
+	}
+	if (sd_mmc_spi_nb_block >
+		(sd_mmc_spi_transfert_pos / sd_mmc_spi_block_size)) {
+		return true; // It is not the End of multi write
+	}
+
+	// Delay before start write block:
+	// Nwr timing minimum = 8 cylces
+	value = 0xFF;
+	io_write(spi_inst, &value, 1);
+	// Send stop token
+	value = SPI_TOKEN_STOP_TRAN;
+	io_write(spi_inst, &value, 1);
+	// Wait busy
+	if (!spi_m_sync_wait_busy(spi)) {
+		sd_mmc_spi_err = SD_MMC_SPI_ERR_WRITE_TIMEOUT;
+		sd_mmc_spi_debug("%s: Stop write blocks timeout\n\r",
+						 __func__);
+		return false;
+	}
+	return true;
+}
+
+static bool spi_m_sync_start_read_block(struct spi_m_sync_descriptor* spi)
+{
+	struct io_descriptor* spi_inst = NULL;
+	spi_m_sync_get_io_descriptor(spi, &spi_inst);
+	uint32_t i;
+	uint8_t token;
+	uint8_t dummy = 0xFF;
+
+	assert(!(sd_mmc_spi_transfert_pos % sd_mmc_spi_block_size), ">>>");
+
+	/* Wait for start data token:
+	 * The read timeout is the Nac timing.
+	 * Nac must be computed trough CSD values,
+	 * or it is 100ms for SDHC / SDXC
+	 * Compute the maximum timeout:
+	 * Frequency maximum = 25MHz
+	 * 1 byte = 8 cycles
+	 * 100ms = 312500 x spi_read_buffer_wait() maximum
+	 */
+	token = 0;
+	i = 500000;
+	do {
+		if (i-- == 0) {
+			sd_mmc_spi_err = SD_MMC_SPI_ERR_READ_TIMEOUT;
+			sd_mmc_spi_debug("%s: Read blocks timeout\n\r", __func__);
+			return false;
+		}
+		io_write(spi_inst, &dummy, 1);
+		io_read(spi_inst, &token, 1);
+		if (SPI_TOKEN_DATA_ERROR_VALID(token)) {
+			assert(SPI_TOKEN_DATA_ERROR_ERRORS & token, ">>>");
+			if (token & (SPI_TOKEN_DATA_ERROR_ERROR
+					| SPI_TOKEN_DATA_ERROR_ECC_ERROR
+					| SPI_TOKEN_DATA_ERROR_CC_ERROR)) {
+				sd_mmc_spi_debug("%s: CRC data error token\n\r", __func__);
+				sd_mmc_spi_err = SD_MMC_SPI_ERR_READ_CRC;
+			} else {
+				sd_mmc_spi_debug("%s: Out of range data error token\n\r", __func__);
+				sd_mmc_spi_err = SD_MMC_SPI_ERR_OUT_OF_RANGE;
+			}
+			return false;
+		}
+	} while (token != SPI_TOKEN_SINGLE_MULTI_READ);
+
+	return true;
+}
+
+static void spi_m_sync_stop_read_block(struct spi_m_sync_descriptor* spi)
+{
+	struct io_descriptor* spi_inst = NULL;
+	spi_m_sync_get_io_descriptor(spi, &spi_inst);
+	uint8_t crc[2];
+	uint8_t dummy = 0xFF;
+	// Read 16-bit CRC (not cheked)
+	io_write(spi_inst, &dummy, 1);
+	io_read(spi_inst, crc, 2);
+}
+
+bool spi_m_sync_send_cmd(struct spi_m_sync_descriptor* spi, uint32_t cmd,
+                         uint32_t arg)
+{
+	return spi_m_sync_adtc_start(spi, cmd, arg, 0, 0, false);
+}
+bool spi_m_sync_adtc_start(struct spi_m_sync_descriptor* spi,
+                           uint32_t cmd, uint32_t arg, uint16_t block_size,
+                           uint16_t nb_block, bool access_block)
+{
+	struct io_descriptor* spi_inst = NULL;
+	spi_m_sync_get_io_descriptor(spi, &spi_inst);
+	uint8_t dummy = 0xFF;
+	uint8_t cmd_token[6];
+	uint8_t ncr_timeout;
+	uint8_t r1;
+	uint8_t dummy2 = 0xFF;
+
+	(void)access_block;
+	assert(cmd & SDMMC_RESP_PRESENT, "No SD Card response was present...");
+	sd_mmc_spi_err = SD_MMC_SPI_NO_ERR;
+
+	cmd_token[0] = SPI_CMD_ENCODE(SDMMC_CMD_GET_INDEX(cmd));
+	cmd_token[1] = arg >> 24;
+	cmd_token[2] = arg >> 16;
+	cmd_token[3] = arg >> 8;
+	cmd_token[4] = arg;
+	cmd_token[5] = spi_m_sync_crc7(cmd_token, 5);
+
+
+	// 8 cycles to respect Ncs timing
+	io_write(spi_inst, &dummy, 1);
+	// send command
+	io_write(spi_inst, cmd_token, sizeof(cmd_token));
+
+	// Wait for response
+	// Two retries will be done to manage the Ncr timing between command and response
+	// Ncr: Min. 1x8 clock cycle, Max 8x8 clock cycles
+	// WORKAROUND for no compliance (Atmel Internal ref. SD13)
+	r1 = 0xFF;
+	// Ignore first byte because Ncr min. = 8 clock cycles
+	io_read(spi_inst, &r1, 1);
+	ncr_timeout = 7;
+
+	while(1)
+	{
+		io_read(spi_inst, &r1, 1);
+		if((r1 & R1_SPI_ERROR) == 0)
+		{
+			// Valid response
+			break;
+		}
+		if(--ncr_timeout == 0)
+		{
+			// Here valid r1 response received
+			sd_mmc_spi_debug("%s: cmd %02d, arg 0x%08lX, R1 timeout\r\n",
+							 __func__, (int)SDMMC_CMD_GET_INDEX(cmd), arg);
+			sd_mmc_spi_err = SD_MMC_SPI_ERR_RESP_TIMEOUT;
+			return false;
+		}
+	}
+
+	// Save R1 (specific to spi interface) in 32 bit response
+	// The R1_SPI_IDLE bit can be checked by high level
+	sd_mmc_spi_response_32 = r1;
+
+	// Manage error in R1
+	if (r1 & R1_SPI_COM_CRC)
+	{
+		sd_mmc_spi_debug("%s: cmd %02d, arg 0x%08lx, r1 0x%02x, R1_SPI_COM_CRC\n\r",
+						 __func__, (int)SDMMC_CMD_GET_INDEX(cmd), arg, r1);
+		sd_mmc_spi_err = SD_MMC_SPI_ERR_RESP_CRC;
+		return false;
+	}
+
+	if (r1 & R1_SPI_ILLEGAL_COMMAND)
+	{
+		sd_mmc_spi_debug("%s: cmd %02d, arg 0x%08lx, r1 0x%x, R1 ILLEGAL_COMMAND\n\r",
+						 __func__, (int)SDMMC_CMD_GET_INDEX(cmd), arg, r1);
+		sd_mmc_spi_err = SD_MMC_SPI_ERR_ILLEGAL_COMMAND;
+		return false;
+	}
+
+	if (r1 & ~R1_SPI_IDLE) {
+		// Other error
+		sd_mmc_spi_debug("%s: cmd %02d, arg 0x%08lx, r1 0x%x, R1 error\n\r",
+						 __func__, (int)SDMMC_CMD_GET_INDEX(cmd), arg, r1);
+		sd_mmc_spi_err = SD_MMC_SPI_ERR;
+		return false;
+	}
+
+	// Manage other responses
+	if (cmd & SDMMC_RESP_BUSY) {
+		if (!spi_m_sync_wait_busy(spi)) {
+			sd_mmc_spi_err = SD_MMC_SPI_ERR_RESP_BUSY_TIMEOUT;
+			sd_mmc_spi_debug("%s: cmd %02d, arg 0x%08lx, Busy signal always high\n\r",
+							 __func__, (int)SDMMC_CMD_GET_INDEX(cmd), arg);
+			return false;
+		}
+	}
+	if (cmd & SDMMC_RESP_8) {
+		sd_mmc_spi_response_32 = 0;
+		io_write(spi_inst, &dummy2, 1);
+		io_read(spi_inst, (uint8_t*)&sd_mmc_spi_response_32, 1);
+		sd_mmc_spi_response_32 = LE32(sd_mmc_spi_response_32);
+	}
+	if (cmd & SDMMC_RESP_32) {
+		io_write(spi_inst, &dummy2, 1);
+		io_read(spi_inst, (uint8_t*)&sd_mmc_spi_response_32, 4);
+		sd_mmc_spi_response_32 = BE32(sd_mmc_spi_response_32);
+	}
+
+	sd_mmc_spi_block_size = block_size;
+	sd_mmc_spi_nb_block = nb_block;
+	sd_mmc_spi_transfert_pos = 0;
+	return true;
+}
+bool spi_m_sync_start_read_blocks(struct spi_m_sync_descriptor* spi,
+                                  void *dst, uint16_t nb_block)
+{
+	struct io_descriptor* spi_inst = NULL;
+	spi_m_sync_get_io_descriptor(spi, &spi_inst);
+	uint32_t pos;
+	uint8_t dummy = 0xFF;
+
+	sd_mmc_spi_err = SD_MMC_SPI_NO_ERR;
+	pos = 0;
+	while (nb_block--) {
+		assert(sd_mmc_spi_nb_block >
+			   (sd_mmc_spi_transfert_pos / sd_mmc_spi_block_size), ">>>");
+		if (!spi_m_sync_start_read_block(spi)) {
+			return false;
+		}
+
+		// Read block
+		io_write(spi_inst, &dummy, 1);
+		io_read(spi_inst, &((uint8_t*)dst)[pos], sd_mmc_spi_block_size);
+		pos += sd_mmc_spi_block_size;
+		sd_mmc_spi_transfert_pos += sd_mmc_spi_block_size;
+
+		spi_m_sync_stop_read_block(spi);
+	}
+	return true;
+}
+bool spi_m_sync_start_write_blocks(struct spi_m_sync_descriptor* spi,
+                                   const void *src, uint16_t nb_block)
+{
+	struct io_descriptor* spi_inst = NULL;
+	spi_m_sync_get_io_descriptor(spi, &spi_inst);
+	uint32_t pos;
+
+	sd_mmc_spi_err = SD_MMC_SPI_NO_ERR;
+	pos = 0;
+	while (nb_block--) {
+		assert(sd_mmc_spi_nb_block >
+			   (sd_mmc_spi_transfert_pos / sd_mmc_spi_block_size), ">>>");
+		spi_m_sync_start_write_block(spi);
+
+		// Write block
+		io_write(spi_inst, &((uint8_t*)src)[pos], sd_mmc_spi_block_size);
+		pos += sd_mmc_spi_block_size;
+		sd_mmc_spi_transfert_pos += sd_mmc_spi_block_size;
+
+		if (!spi_m_sync_stop_write_block(spi)) {
+			return false;
+		}
+		// Do not check busy of last block
+		// but delay it to mci_wait_end_of_write_blocks()
+		if (nb_block) {
+			// Wait busy due to data programmation
+			if (!spi_m_sync_wait_busy(spi)) {
+				sd_mmc_spi_err = SD_MMC_SPI_ERR_WRITE_TIMEOUT;
+				sd_mmc_spi_debug("%s: Write blocks timeout\n\r", __func__);
+				return false;
+			}
+		}
+	}
+	return true;
+}
+bool spi_m_sync_wait_end_of_write_blocks(struct spi_m_sync_descriptor* spi)
+{
+	// Wait busy due to data programmation of last block writed
+	if (!spi_m_sync_wait_busy(spi)) {
+		sd_mmc_spi_err = SD_MMC_SPI_ERR_WRITE_TIMEOUT;
+		sd_mmc_spi_debug("%s: Write blocks timeout\n\r", __func__);
+		return false;
+	}
+        return spi_m_sync_stop_multiwrite_block(spi);
+}
+
+bool spi_m_sync_wait_end_of_read_blocks(struct spi_m_sync_descriptor* spi)
+{
+	return true;
+}
+
+bool spi_m_sync_write_word(struct spi_m_sync_descriptor* spi,
+                           uint32_t value)
+{
+	struct io_descriptor* spi_inst = NULL;
+	spi_m_sync_get_io_descriptor(spi, &spi_inst);
+	sd_mmc_spi_err = SD_MMC_SPI_NO_ERR;
+	assert(sd_mmc_spi_nb_block > (sd_mmc_spi_transfert_pos / sd_mmc_spi_block_size), "<<<");
+	if(!(sd_mmc_spi_transfert_pos % sd_mmc_spi_block_size))
+	{
+		spi_m_sync_start_write_block(spi);
+	}
+
+	// Write data
+	value = LE32(value);
+	io_write(spi_inst, (uint8_t*)&value, 4);
+	sd_mmc_spi_transfert_pos += 4;
+
+	if (!(sd_mmc_spi_transfert_pos % sd_mmc_spi_block_size)) {
+		// End of block
+		if (!spi_m_sync_stop_write_block(spi)) {
+			return false;
+		}
+		// Wait busy due to data programmation
+		if (!spi_m_sync_wait_busy(spi)) {
+			sd_mmc_spi_err = SD_MMC_SPI_ERR_WRITE_TIMEOUT;
+			sd_mmc_spi_debug("%s: Write blocks timeout\n\r", __func__);
+			return false;
+		}
+	}
+	return spi_m_sync_stop_multiwrite_block(spi);
+}
+
+bool spi_m_sync_read_word(struct spi_m_sync_descriptor* spi, uint32_t* value)
+{
+	struct io_descriptor* spi_inst = NULL;
+	spi_m_sync_get_io_descriptor(spi, &spi_inst);
+	uint8_t dummy = 0xFF;
+
+	sd_mmc_spi_err = SD_MMC_SPI_NO_ERR;
+	assert(sd_mmc_spi_nb_block >
+		   (sd_mmc_spi_transfert_pos / sd_mmc_spi_block_size),
+		">>>");
+
+	if (!(sd_mmc_spi_transfert_pos % sd_mmc_spi_block_size)) {
+		// New block
+		if (!spi_m_sync_start_read_block(spi)) {
+			return false;
+		}
+	}
+	// Read data
+	io_write(spi_inst, &dummy, 1);
+	io_read(spi_inst, (uint8_t*)&value, 4);
+	*value = LE32(*value);
+	sd_mmc_spi_transfert_pos += 4;
+
+	if (!(sd_mmc_spi_transfert_pos % sd_mmc_spi_block_size)) {
+		// End of block
+		spi_m_sync_stop_read_block(spi);
+	}
+	return true;}
+
+uint32_t spi_m_sync_get_response(struct spi_m_sync_descriptor* spi)
+{
+	return sd_mmc_spi_response_32;
+}
+
+
+void spi_m_sync_send_clock(struct spi_m_sync_descriptor* spi)
+{
+	struct io_descriptor* spi_inst = NULL;
+	spi_m_sync_get_io_descriptor(spi, &spi_inst);
+
+	uint8_t i;
+	uint8_t dummy = 0xFF;
+
+	sd_mmc_spi_err = SD_MMC_SPI_NO_ERR;
+	// Send 80 cycles
+	for(i = 0; i < 10; i++)
+	{
+		io_write(spi_inst, &dummy, 1); // 8 cycles
+	}
+}
+
+int32_t spi_m_sync_select_device(struct spi_m_sync_descriptor* spi, uint8_t slot, uint32_t clock, uint8_t bus_width, bool high_speed)
+{
+	UNUSED(bus_width);
+	UNUSED(high_speed);
+	sd_mmc_spi_err = SD_MMC_SPI_NO_ERR;
+	PORT->Group[SPI_CS_PORT].OUT.reg &= ~(1 << SPI_CS_PIN);
+
+	return 0;
+}
+
+int32_t spi_m_sync_deselect_device(struct spi_m_sync_descriptor* spi, uint8_t slot)
+{
+	sd_mmc_spi_err = SD_MMC_SPI_NO_ERR;
+	PORT->Group[1].OUT.reg |= (1 << SPI_CS_PIN);
+	return 0;
+}
diff --git a/sd_mmc/sd_mmc_spi.h b/sd_mmc/sd_mmc_spi.h
new file mode 100644
index 0000000..0cb7a67
--- /dev/null
+++ b/sd_mmc/sd_mmc_spi.h
@@ -0,0 +1,183 @@
+#ifndef _SPI_M_SYNC_H_
+#define _SPI_M_SYNC_H_
+
+#include "compiler.h"
+#include "sd_mmc_protocol.h"
+#include "hal_spi_m_sync.h"
+#include <stdio.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// lazy define
+#define SD_MMC_SPI_DEBUG (1)
+#ifdef SD_MMC_SPI_DEBUG
+#include "pdebug.h"
+#define sd_mmc_spi_debug(...) printf(__VA_ARGS__)
+#else
+#define sd_mmc_spi_debug(...)
+#endif
+//! Type of return error code
+typedef uint8_t sd_mmc_spi_errno_t;
+//! \name Return error codes
+//! @{
+#define SD_MMC_SPI_NO_ERR                 0 //! No error
+#define SD_MMC_SPI_ERR                    1 //! General or an unknown error
+#define SD_MMC_SPI_ERR_RESP_TIMEOUT       2 //! Timeout during command
+#define SD_MMC_SPI_ERR_RESP_BUSY_TIMEOUT  3 //! Timeout on busy signal of R1B response
+#define SD_MMC_SPI_ERR_READ_TIMEOUT       4 //! Timeout during read operation
+#define SD_MMC_SPI_ERR_WRITE_TIMEOUT      5 //! Timeout during write operation
+#define SD_MMC_SPI_ERR_RESP_CRC           6 //! Command CRC error
+#define SD_MMC_SPI_ERR_READ_CRC           7 //! CRC error during read operation
+#define SD_MMC_SPI_ERR_WRITE_CRC          8 //! CRC error during write operation
+#define SD_MMC_SPI_ERR_ILLEGAL_COMMAND    9 //! Command not supported
+#define SD_MMC_SPI_ERR_WRITE             10 //! Error during write operation
+#define SD_MMC_SPI_ERR_OUT_OF_RANGE      11 //! Data access out of range
+//! @}
+
+
+
+/** \brief Return the maximum bus width of a slot
+ *
+ * \param slot     Selected slot
+ *
+ * \return 1, 4 or 8 lines.
+ */
+static __inline__ uint8_t spi_m_sync_get_bus_width(struct spi_m_sync_descriptor* spi, uint8_t slot) {
+	UNUSED(spi);
+	UNUSED(slot);
+	return 1;
+}
+
+/** \brief Return the high speed capability of the driver
+ *
+ * \return true, if the high speed is supported
+ */
+static __inline__ bool spi_m_sync_is_high_speed_capable(struct spi_m_sync_descriptor* spi) {
+	UNUSED(spi);
+	return false;
+}
+
+static __inline__ void spi_m_sync_get_response_128(struct spi_m_sync_descriptor* spi, uint8_t *resp) {
+	UNUSED(spi);
+	UNUSED(resp);
+	return;
+}
+
+/////// PENGUIN START
+/** \brief Send a command on the selected slot
+ *
+ * \param cmd        Command definition
+ * \param arg        Argument of the command
+ *
+ * \return true if success, otherwise false
+ */
+bool spi_m_sync_send_cmd(struct spi_m_sync_descriptor* spi, uint32_t cmd,
+                         uint32_t arg);
+
+/** \brief Send a adtc command on the selected slot
+ * A adtc command is used for read/write access.
+ *
+ * \param cmd          Command definition
+ * \param arg          Argument of the command
+ * \param block_size   Block size used for the transfer
+ * \param nb_block     Total number of block for this transfer
+ * \param access_block if true, the x_read_blocks() and x_write_blocks()
+ * functions must be used after this function.
+ * If false, the mci_read_word() and mci_write_word()
+ * functions must be used after this function.
+ *
+ * \return true if success, otherwise false
+ */
+bool spi_m_sync_adtc_start(struct spi_m_sync_descriptor *spi, uint32_t cmd,
+                           uint32_t arg, uint16_t block_size, uint16_t nb_block,
+                           bool access_block);
+/** \brief Send a command to stop a adtc command on the selected slot
+ *
+ * \param cmd        Command definition
+ * \param arg        Argument of the command
+ *
+ * \return true if success, otherwise false
+ */
+bool spi_m_sync_adtc_stop(struct spi_m_sync_descriptor* spi, uint32_t cmd, uint32_t arg);
+
+/** \brief Start a read blocks transfer on the line
+ * Note: The driver will use the DMA available to speed up the transfer.
+ *
+ * \param dest       Pointer on the buffer to fill
+ * \param nb_block   Number of block to transfer
+ *
+ * \return true if started, otherwise false
+ */
+bool spi_m_sync_start_read_blocks(struct spi_m_sync_descriptor *spi, void *dst,
+                                  uint16_t nb_block);
+
+/** \brief Start a write blocks transfer on the line
+ * Note: The driver will use the DMA available to speed up the transfer.
+ *
+ * \param src        Pointer on the buffer to send
+ * \param nb_block   Number of block to transfer
+ *
+ * \return true if started, otherwise false
+ */
+bool spi_m_sync_start_write_blocks(struct spi_m_sync_descriptor *spi,
+                                   const void *src, uint16_t nb_block);
+
+/** \brief Wait the end of transfer initiated by mci_start_write_blocks()
+ *
+ * \return true if success, otherwise false
+ */
+bool spi_m_sync_wait_end_of_write_blocks(struct spi_m_sync_descriptor* spi);
+/** \brief Wait the end of transfer initiated by mci_start_read_blocks()
+ *
+ * \return true if success, otherwise false
+ */
+bool spi_m_sync_wait_end_of_read_blocks(struct spi_m_sync_descriptor* spi);
+/** \brief Write a word on the line
+ *
+ * \param value  Word to send
+ *
+ * \return true if success, otherwise false
+ */
+bool spi_m_sync_write_word(struct spi_m_sync_descriptor* spi,
+                           uint32_t value);
+/** \brief Read a word on the line
+ *
+ * \param value  Pointer on a word to fill
+ *
+ * \return true if success, otherwise false
+ */
+bool spi_m_sync_read_word(struct spi_m_sync_descriptor* spi, uint32_t* value);
+
+/** \brief Return the 32 bits response of the last command
+ *
+ * \return 32 bits response
+ */
+uint32_t spi_m_sync_get_response(struct spi_m_sync_descriptor* spi);
+
+/** \brief Send 74 clock cycles on the line of selected slot
+ * Note: It is required after card plug and before card install.
+ */
+void spi_m_sync_send_clock(struct spi_m_sync_descriptor* spi);
+/**
+ * \brief Select a slot and initialize it
+ *
+ * \param slot       Selected slot
+ * \param clock      Maximum clock to use (Hz)
+ * \param bus_width  Bus width to use (1, 4 or 8)
+ * \param high_speed true, to enable high speed mode
+ */
+int32_t spi_m_sync_select_device(struct spi_m_sync_descriptor* spi, uint8_t slot, uint32_t clock, uint8_t bus_width, bool high_speed);
+
+/**
+ * \brief Deselect a slot
+ *
+ * \param slot       Selected slot
+ */
+int32_t spi_m_sync_deselect_device(struct spi_m_sync_descriptor* spi, uint8_t slot);
+
+#ifdef __cpluscplus
+}
+#endif
+
+#endif
diff --git a/sd_mmc_start.c b/sd_mmc_start.c
new file mode 100644
index 0000000..4004a89
--- /dev/null
+++ b/sd_mmc_start.c
@@ -0,0 +1,54 @@
+/*
+ * Code generated from Atmel Start.
+ *
+ * This file will be overwritten when reconfiguring your Atmel Start project.
+ * Please copy examples or other code you want to keep to a separate file or main.c
+ * to avoid loosing it when reconfiguring.
+ */
+
+#include "atmel_start.h"
+#include "sd_mmc.h"
+
+#include "conf_sd_mmc.h"
+
+/* Card Detect (CD) pin settings */
+static sd_mmc_detect_t SDMMC_cd[CONF_SD_MMC_MEM_CNT] = {
+
+    {-1, CONF_SD_MMC_0_CD_DETECT_VALUE},
+};
+
+/* Write Protect (WP) pin settings */
+static sd_mmc_detect_t SDMMC_wp[CONF_SD_MMC_MEM_CNT] = {
+
+    {-1, CONF_SD_MMC_0_WP_DETECT_VALUE},
+};
+
+static uint8_t sd_mmc_block[512];
+
+/*
+ * Example
+ */
+void SDMMC_example(void)
+{
+	while (SD_MMC_OK != sd_mmc_check(0)) {
+		/* Wait card ready. */
+	}
+	if (sd_mmc_get_type(0) & (CARD_TYPE_SD | CARD_TYPE_MMC)) {
+		/* Read card block 0 */
+		sd_mmc_init_read_blocks(0, 0, 1);
+		sd_mmc_start_read_blocks(sd_mmc_block, 1);
+		sd_mmc_wait_end_of_read_blocks(false);
+	}
+#if (CONF_SDIO_SUPPORT == 1)
+	if (sd_mmc_get_type(0) & CARD_TYPE_SDIO) {
+		/* Read 22 bytes from SDIO Function 0 (CIA) */
+		sdio_read_extended(0, 0, 0, 1, sd_mmc_block, 22);
+	}
+#endif
+}
+
+void sd_mmc_stack_init(void)
+{
+
+	sd_mmc_init(&SPI_SD_MMC, SDMMC_cd, SDMMC_wp);
+}
diff --git a/sd_mmc_start.h b/sd_mmc_start.h
new file mode 100644
index 0000000..5c97997
--- /dev/null
+++ b/sd_mmc_start.h
@@ -0,0 +1,28 @@
+/*
+ * Code generated from Atmel Start.
+ *
+ * This file will be overwritten when reconfiguring your Atmel Start project.
+ * Please copy examples or other code you want to keep to a separate file or main.c
+ * to avoid loosing it when reconfiguring.
+ */
+#ifndef SD_MMC_MAIN_H
+#define SD_MMC_MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include <stdio.h>
+
+void SDMMC_example(void);
+
+/**
+ * \brief Initialize SD MMC Stack
+ */
+void sd_mmc_stack_init(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* SD_MMC_MAIN_H */
diff --git a/shared/util/pdebug.h b/shared/util/pdebug.h
index 8cb4edb..9f164c3 100644
--- a/shared/util/pdebug.h
+++ b/shared/util/pdebug.h
@@ -2,6 +2,7 @@
 #define _PDEBUG_H_
 
 #include "atmel_start.h"
+#include <stdio.h>
 int pdebug_init(void);
 
 int pprintf(const char* fmt, ...);