/* Auto-generated config file hpl_sysctrl_config.h */ #ifndef HPL_SYSCTRL_CONFIG_H #define HPL_SYSCTRL_CONFIG_H // <<< Use Configuration Wizard in Context Menu >>> #define CONF_DFLL_OPEN_LOOP_MODE 0 #define CONF_DFLL_CLOSED_LOOP_MODE 1 #define CONF_XOSC_STARTUP_TIME_31MCS 0 #define CONF_XOSC_STARTUP_TIME_61MCS 1 #define CONF_XOSC_STARTUP_TIME_122MCS 2 #define CONF_XOSC_STARTUP_TIME_244MCS 3 #define CONF_XOSC_STARTUP_TIME_488MCS 4 #define CONF_XOSC_STARTUP_TIME_977MCS 5 #define CONF_XOSC_STARTUP_TIME_1953MCS 6 #define CONF_XOSC_STARTUP_TIME_3906MCS 7 #define CONF_XOSC_STARTUP_TIME_7813MCS 8 #define CONF_XOSC_STARTUP_TIME_15625MCS 9 #define CONF_XOSC_STARTUP_TIME_31250MCS 10 #define CONF_XOSC_STARTUP_TIME_62500MCS 11 #define CONF_XOSC_STARTUP_TIME_125000MCS 12 #define CONF_XOSC_STARTUP_TIME_250000MCS 13 #define CONF_XOSC_STARTUP_TIME_500000MCS 14 #define CONF_XOSC_STARTUP_TIME_1000000MCS 15 #define CONF_OSC_STARTUP_TIME_92MCS 0 #define CONF_OSC_STARTUP_TIME_122MCS 1 #define CONF_OSC_STARTUP_TIME_183MCS 2 #define CONF_OSC_STARTUP_TIME_305MCS 3 #define CONF_OSC_STARTUP_TIME_549MCS 4 #define CONF_OSC_STARTUP_TIME_1038MCS 5 #define CONF_OSC_STARTUP_TIME_2014MCS 6 #define CONF_OSC_STARTUP_TIME_3967MCS 7 #define CONF_XOSC32K_STARTUP_TIME_122MCS 0 #define CONF_XOSC32K_STARTUP_TIME_1068MCS 1 #define CONF_XOSC32K_STARTUP_TIME_65592MCS 2 #define CONF_XOSC32K_STARTUP_TIME_125092MCS 3 #define CONF_XOSC32K_STARTUP_TIME_500092MCS 4 #define CONF_XOSC32K_STARTUP_TIME_1000092MCS 5 #define CONF_XOSC32K_STARTUP_TIME_2000092MCS 6 #define CONF_XOSC32K_STARTUP_TIME_4000092MCS 7 // 8MHz Internal Oscillator Configuration // Indicates whether configuration for OSC8M is enabled or not // enable_osc8m #ifndef CONF_OSC8M_CONFIG #define CONF_OSC8M_CONFIG 1 #endif // 8MHz Internal Oscillator (OSC8M) Control // Internal 8M Oscillator Enable // Indicates whether Internal 8 Mhz Oscillator is enabled or not // osc8m_arch_enable #ifndef CONF_OSC8M_ENABLE #define CONF_OSC8M_ENABLE 1 #endif // On Demand Control // Indicates whether On Demand Control is enabled or not. // If enabled, the oscillator will only be running when requested by a peripheral. // If disabled, the oscillator will always be running when enabled. // osc8m_arch_ondemand #ifndef CONF_OSC8M_ONDEMAND #define CONF_OSC8M_ONDEMAND 1 #endif // Run In Standby // Run In standby Mode // If this bit is 0: The oscillator is disabled in standby sleep mode. // If this bit is 1: The oscillator is not stopped in standby sleep mode. // osc8m_arch_runstdby #ifndef CONF_OSC8M_RUNSTDBY #define CONF_OSC8M_RUNSTDBY 0 #endif // Prescaler // 1 // 2 // 4 // 8 // Prescaler for Internal 8Mhz OSC // Default: No Prescaling // osc8m_presc #ifndef CONF_OSC8M_PRESC #define CONF_OSC8M_PRESC SYSCTRL_OSC8M_PRESC_3_Val #endif // Overwrite Default Osc Calibration // Overwrite Default Osc Calibration // osc8m_arch_overwrite_calibration #ifndef CONF_OSC8M_OVERWRITE_CALIBRATION #define CONF_OSC8M_OVERWRITE_CALIBRATION 0 #endif // Osc Calibration Value <0-65535> // Set the Oscillator Calibration Value // Default: 1 // osc8m_arch_calib #ifndef CONF_OSC8M_CALIB #define CONF_OSC8M_CALIB 0 #endif // // // 32kHz Internal Oscillator Configuration // Indicates whether configuration for OSC32K is enabled or not // enable_osc32k #ifndef CONF_OSC32K_CONFIG #define CONF_OSC32K_CONFIG 0 #endif // 32kHz Internal Oscillator (OSC32K) Control // Internal 32K Oscillator Enable // Indicates whether Internal 32K Oscillator is enabled or not // osc32k_arch_enable #ifndef CONF_OSC32K_ENABLE #define CONF_OSC32K_ENABLE 0 #endif // On Demand Control // Enable On Demand // If this bit is 0: The oscillator is always on, if enabled. // If this bit is 1, the oscillator will only be running when requested by a peripheral. // osc32k_arch_ondemand #ifndef CONF_OSC32K_ONDEMAND #define CONF_OSC32K_ONDEMAND 1 #endif // Run In Standby // Run In standby Mode // If this bit is 0: The oscillator is disabled in standby sleep mode. // If this bit is 1: The oscillator is not stopped in standby sleep mode. // osc32k_arch_runstdby #ifndef CONF_OSC32K_RUNSTDBY #define CONF_OSC32K_RUNSTDBY 0 #endif // Enable 32Khz Output // Enable 32 Khz Output // osc32k_arch_en32k #ifndef CONF_OSC32K_EN32K #define CONF_OSC32K_EN32K 0 #endif // Enable 1K // Enable 1K // osc32k_arch_en1k #ifndef CONF_OSC32K_EN1K #define CONF_OSC32K_EN1K 0 #endif // Write Lock // Write Lock // osc32k_arch_wrtlock #ifndef CONF_OSC32K_WRTLOCK #define CONF_OSC32K_WRTLOCK 0 #endif // Start up time for the 32K Oscillator // 3 Clock Cycles (92us) // 4 Clock Cycles (122us) // 6 Clock Cycles (183us) // 10 Clock Cycles (305us) // 18 Clock Cycles (549us) // 34 Clock Cycles (1038us) // 66 Clock Cycles (2014us) // 130 Clock Cycles (3967us) // Start Up Time for the 32K Oscillator // Default: 10 Clock Cycles (305us) // osc32k_arch_startup #ifndef CONF_OSC32K_STARTUP #define CONF_OSC32K_STARTUP CONF_OSC_STARTUP_TIME_92MCS #endif // Overwrite Default Osc Calibration // Overwrite Default Osc Calibration // osc32k_arch_overwrite_calibration #ifndef CONF_OSC32K_OVERWRITE_CALIBRATION #define CONF_OSC32K_OVERWRITE_CALIBRATION 0 #endif // Osc Calibration Value <0-65535> // Set the Oscillator Calibration Value // Default: 0 // osc32k_arch_calib #ifndef CONF_OSC32K_CALIB #define CONF_OSC32K_CALIB 0 #endif // // // 32kHz External Crystal Oscillator Configuration // Indicates whether configuration for External 32K Osc is enabled or not // enable_xosc32k #ifndef CONF_XOSC32K_CONFIG #define CONF_XOSC32K_CONFIG 0 #endif // 32kHz External Crystal Oscillator (XOSC32K) Control // External 32K Oscillator Enable // Indicates whether External 32K Oscillator is enabled or not // xosc32k_arch_enable #ifndef CONF_XOSC32K_ENABLE #define CONF_XOSC32K_ENABLE 0 #endif // On Demand // Enable On Demand. // If this bit is 0: The oscillator is always on, if enabled. // If this bit is 1: the oscillator will only be running when requested by a peripheral. // xosc32k_arch_ondemand #ifndef CONF_XOSC32K_ONDEMAND #define CONF_XOSC32K_ONDEMAND 1 #endif // Run In Standby // Run In standby Mode // If this bit is 0: The oscillator is disabled in standby sleep mode. // If this bit is 1: The oscillator is not stopped in standby sleep mode. // xosc32k_arch_runstdby #ifndef CONF_XOSC32K_RUNSTDBY #define CONF_XOSC32K_RUNSTDBY 0 #endif // Enable 1K // Enable 1K // xosc32k_arch_en1k #ifndef CONF_XOSC32K_EN1K #define CONF_XOSC32K_EN1K 0 #endif // Enable 32Khz Output // Enable 32 Khz Output // xosc32k_arch_en32k #ifndef CONF_XOSC32K_EN32K #define CONF_XOSC32K_EN32K 0 #endif // Enable XTAL // Enable XTAL // xosc32k_arch_xtalen #ifndef CONF_XOSC32K_XTALEN #define CONF_XOSC32K_XTALEN 0 #endif // Write Lock // Write Lock // xosc32k_arch_wrtlock #ifndef CONF_XOSC32K_WRTLOCK #define CONF_XOSC32K_WRTLOCK 0 #endif // Automatic Amplitude Control Enable // Indicates whether Automatic Amplitude Control is Enabled or not // xosc32k_arch_aampen #ifndef CONF_XOSC32K_AAMPEN #define CONF_XOSC32K_AAMPEN 0 #endif // Start up time for the 32K Oscillator // 122 us // 1068 us // 62592 us // 1125092 us // 500092 us // 1000092 us // 2000092 us // 4000092 us // Start Up Time for the 32K Oscillator // Default: 122 us // xosc32k_arch_startup #ifndef CONF_XOSC32K_STARTUP #define CONF_XOSC32K_STARTUP CONF_XOSC32K_STARTUP_TIME_122MCS #endif // // // External Multipurpose Crystal Oscillator Configuration // Indicates whether configuration for External Multipurpose Osc is enabled or not // enable_xosc #ifndef CONF_XOSC_CONFIG #define CONF_XOSC_CONFIG 0 #endif // Frequency <400000-32000000> // Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. // xosc_frequency #ifndef CONF_XOSC_FREQUENCY #define CONF_XOSC_FREQUENCY 400000 #endif // External Multipurpose Crystal Oscillator (XOSC) Control // Enable // Indicates whether External Multipurpose Oscillator is enabled or not // xosc_arch_enable #ifndef CONF_XOSC_ENABLE #define CONF_XOSC_ENABLE 0 #endif // On Demand // Enable On Demand // If this bit is 0: The oscillator is always on, if enabled. // If this bit is 1: the oscillator will only be running when requested by a peripheral. // xosc_arch_ondemand #ifndef CONF_XOSC_ONDEMAND #define CONF_XOSC_ONDEMAND 1 #endif // Run In Standby // Run In standby Mode // If this bit is 0: The oscillator is disabled in standby sleep mode. // If this bit is 1: The oscillator is not stopped in standby sleep mode. // xosc_arch_runstdby #ifndef CONF_XOSC_RUNSTDBY #define CONF_XOSC_RUNSTDBY 0 #endif // Enable XTAL // Enable XTAL // xosc_arch_xtalen #ifndef CONF_XOSC_XTALEN #define CONF_XOSC_XTALEN 0 #endif // Automatic Amplitude Control Enable // Indicates whether Automatic Amplitude Control is Enabled or not // xosc_arch_ampgc #ifndef CONF_XOSC_AMPGC #define CONF_XOSC_AMPGC 0 #endif // Gain of the Oscillator // 2Mhz // 4Mhz // 8Mhz // 16Mhz // 30Mhz // Select the Gain of the oscillator // xosc_arch_gain #ifndef CONF_XOSC_GAIN #define CONF_XOSC_GAIN SYSCTRL_XOSC_GAIN_0_Val #endif // Start up time for the External Oscillator // 31 us // 61 us // 122 us // 244 us // 488 us // 977 us // 1953 us // 3906 us // 7813 us // 15625 us // 31250 us // 62500 us // 125000 us // 250000 us // 500000 us // 1000000 us // Start Up Time for the External Oscillator // Default: 31 us // xosc_arch_startup #ifndef CONF_XOSC_STARTUP #define CONF_XOSC_STARTUP CONF_XOSC_STARTUP_TIME_31MCS #endif // // // 32kHz Ultra Low Power Internal Oscillator Configuration // Indicates whether configuration for OSCULP32K is enabled or not // enable_osculp32k #ifndef CONF_OSCULP32K_CONFIG #define CONF_OSCULP32K_CONFIG 1 #endif // 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control // Write Lock // Locks the OSCULP32K register for future writes to fix the OSCULP32K configuration // osculp32k_arch_wrtlock #ifndef CONF_OSCULP32K_WRTLOCK #define CONF_OSCULP32K_WRTLOCK 0 #endif // Overwrite Default Osc Calibration // Overwrite Default Osc Calibration // osculp32k_arch_overwrite_calibration #ifndef CONF_OSCULP32K_OVERWRITE_CALIBRATION #define CONF_OSCULP32K_OVERWRITE_CALIBRATION 0 #endif // Osc Calibration Value <0-255> // Set the Oscillator Calibration Value // Default: 0 // osculp32k_arch_calib #ifndef CONF_OSCULP32K_CALIB #define CONF_OSCULP32K_CALIB 0 #endif // // // DFLL Configuration // Indicates whether configuration for DFLL is enabled or not // enable_dfll48m #ifndef CONF_DFLL_CONFIG #define CONF_DFLL_CONFIG 0 #endif // Reference Clock Source // Generic clock generator 0 // Generic clock generator 1 // Generic clock generator 2 // Generic clock generator 3 // Generic clock generator 4 // Generic clock generator 5 // Generic clock generator 6 // Generic clock generator 7 // Select the clock source. // dfll48m_ref_clock #ifndef CONF_DFLL_GCLK #define CONF_DFLL_GCLK GCLK_CLKCTRL_GEN_GCLK3_Val #endif // DFLL Control // DFLL Enable // Indicates whether DFLL is enabled or not // dfll48m_arch_enable #ifndef CONF_DFLL_ENABLE #define CONF_DFLL_ENABLE 0 #endif // Wait Lock // Indicates whether Wait Lock is Enables or not // dfll48m_arch_waitlock #ifndef CONF_DFLL_WAITLOCK #define CONF_DFLL_WAITLOCK 0 #endif // Bypass Coarse Lock // Indicates whether Bypass coarse lock is enabled or not // dfll48m_arch_bplckc #ifndef CONF_DFLL_BPLCKC #define CONF_DFLL_BPLCKC 0 #endif // Quick Lock Disable // Quick Lock Disable // dfll48m_arch_qldis #ifndef CONF_DFLL_QLDIS #define CONF_DFLL_QLDIS 0 #endif // Chill Cycle Disable // Chill Cycle Disable // dfll48m_arch_ccdis #ifndef CONF_DFLL_CCDIS #define CONF_DFLL_CCDIS 0 #endif // On Demand // Enable On Demand // If this bit is 0: The DFLL is always on, if enabled. // If this bit is 1: the DFLL will only be running when requested by a peripheral. // dfll48m_arch_ondemand #ifndef CONF_DFLL_ONDEMAND #define CONF_DFLL_ONDEMAND 1 #endif // Run In Standby // Run In standby Mode // If this bit is 0: The DFLL is disabled in standby sleep mode. // If this bit is 1: The DFLL is not stopped in standby sleep mode. // dfll48m_arch_runstdby #ifndef CONF_DFLL_RUNSTDBY #define CONF_DFLL_RUNSTDBY 0 #endif // USB Clock Recovery Mode // USB Clock Recovery Mode // dfll48m_arch_usbcrm #ifndef CONF_DFLL_USBCRM #define CONF_DFLL_USBCRM 0 #endif #if CONF_DFLL_USBCRM == 1 #if CONF_DFLL_QLDIS == 1 #warning QLDIS must be cleared to speed up the lock phase #endif #if CONF_DFLL_CCDIS == 0 #warning CCDIS should be set to speed up the lock phase #endif #endif // Lose Lock After Wake // Lose Lock After Wake // dfll48m_arch_llaw #ifndef CONF_DFLL_LLAW #define CONF_DFLL_LLAW 0 #endif // Stable DFLL Frequency // Stable DFLL Frequency // If 0: FINE calibration tracks changes in output frequency. // If 1: FINE calibration register value will be fixed after a fine lock. // dfll48m_arch_stable #ifndef CONF_DFLL_STABLE #define CONF_DFLL_STABLE 0 #endif // Operating Mode Selection // Open Loop Mode // Closed Loop Mode // Mode // dfll48m_mode #ifndef CONF_DFLL_MODE #define CONF_DFLL_MODE CONF_DFLL_OPEN_LOOP_MODE #endif // Coarse Maximum Step <0x0-0x1F> // dfll_arch_cstep #ifndef CONF_DFLL_CSTEP #define CONF_DFLL_CSTEP 1 #endif // Fine Maximum Step <0x0-0x3FF> // dfll_arch_fstep #ifndef CONF_DFLL_FSTEP #define CONF_DFLL_FSTEP 1 #endif // DFLL Multiply Factor<0-65535> // Set the DFLL Multiply Factor // Default: 0 // dfll48m_mul #ifndef CONF_DFLL_MUL #define CONF_DFLL_MUL 0 #endif // DFLL Calibration Overwrite // Indicates whether Overwrite Calibration value of DFLL // dfll48m_arch_calibration #ifndef CONF_DFLL_OVERWRITE_CALIBRATION #define CONF_DFLL_OVERWRITE_CALIBRATION 0 #endif // Coarse Value <0x0-0x3F> // dfll48m_arch_coarse #ifndef CONF_DFLL_COARSE #define CONF_DFLL_COARSE (0x1f) #endif // Fine Value <0x0-0x3FF> // dfll48m_arch_fine #ifndef CONF_DFLL_FINE #define CONF_DFLL_FINE (0x200) #endif #if CONF_DFLL_OVERWRITE_CALIBRATION == 0 #define CONF_DEFAULT_CORASE \ ((FUSES_DFLL48M_COARSE_CAL_Msk & (*((uint32_t *)FUSES_DFLL48M_COARSE_CAL_ADDR))) >> FUSES_DFLL48M_COARSE_CAL_Pos) #define CONF_DFLLVAL \ SYSCTRL_DFLLVAL_COARSE(((CONF_DEFAULT_CORASE) == 0x3F) ? 0x1F : (CONF_DEFAULT_CORASE)) \ | SYSCTRL_DFLLVAL_FINE(512) #else #define CONF_DFLLVAL SYSCTRL_DFLLVAL_COARSE(CONF_DFLL_COARSE) | SYSCTRL_DFLLVAL_FINE(CONF_DFLL_FINE) #endif // // // // DPLL Configuration // Indicates whether configuration for DPLL is enabled or not // enable_fdpll96m #ifndef CONF_DPLL_CONFIG #define CONF_DPLL_CONFIG 0 #endif // Reference Clock Source // 32kHz External Crystal Oscillator (XOSC32K) // External Crystal Oscillator 0.4-32MHz (XOSC) // Generic clock generator 0 // Generic clock generator 1 // Generic clock generator 2 // Generic clock generator 3 // Generic clock generator 4 // Generic clock generator 5 // Generic clock generator 6 // Generic clock generator 7 // Select the clock source. // fdpll96m_ref_clock #ifndef CONF_DPLL_GCLK #define CONF_DPLL_GCLK GCLK_CLKCTRL_GEN_GCLK3_Val #endif #if (CONF_DPLL_GCLK == GCLK_GENCTRL_SRC_XOSC32K) #define CONF_DPLL_REFCLK SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val #elif (CONF_DPLL_GCLK == GCLK_GENCTRL_SRC_XOSC) #define CONF_DPLL_REFCLK SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val #else #define CONF_DPLL_REFCLK SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val #endif // DPLL Control // ON Demand // Enable On Demand // If this bit is 0: The DFLL is always on, if enabled. // If this bit is 1: the DFLL will only be running when requested by a peripheral. // fdpll96m_arch_ondemand #ifndef CONF_DPLL_ONDEMAND #define CONF_DPLL_ONDEMAND 1 #endif // Run In Standby // Run In standby Mode // If this bit is 0: The DFLL is disabled in standby sleep mode. // If this bit is 1: The DFLL is not stopped in standby sleep mode. // fdpll96m_arch_runstdby #ifndef CONF_DPLL_RUNSTDBY #define CONF_DPLL_RUNSTDBY 0 #endif // DPLL Enable // Indicates whether DPLL is enabled or not // fdpll96m_arch_enable #ifndef CONF_DPLL_ENABLE #define CONF_DPLL_ENABLE 0 #endif // Lock ByPass // Enabling it makes the CLK_FDPLL96M always running otherwise it will be turned off when lock signal is low // fdpll96m_arch_lbypass #ifndef CONF_DPLL_LBYPASS #define CONF_DPLL_LBYPASS 0 #endif // Clock Divider <0-2047> // Clock Division Factor (Applicable if reference clock is XOSC) // fdpll96m_clock_div #ifndef CONF_DPLL_DIV #define CONF_DPLL_DIV 0 #endif // DPLL LDRFRAC<0-15> // Set the fractional part of the frequency multiplier. // fdpll96m_ldrfrac #ifndef CONF_DPLL_LDRFRAC #define CONF_DPLL_LDRFRAC 13 #endif // DPLL LDR <0-4095> // Set the integer part of the frequency multiplier. // fdpll96m_ldr #ifndef CONF_DPLL_LDR #define CONF_DPLL_LDR 1463 #endif // // #define CONF_DPLL_LTIME SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val #define CONF_DPLL_WUF 0 #define CONF_DPLL_LPEN 0 #define CONF_DPLL_FILTER SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val // <<< end of configuration section >>> #endif // HPL_SYSCTRL_CONFIG_H