AtmelStart.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .text 0000155c 00000000 00000000 00010000 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 1 .relocate 00000000 20000000 20000000 0001155c 2**0 CONTENTS 2 .bkupram 00000000 47000000 47000000 0001155c 2**0 CONTENTS 3 .qspi 00000000 04000000 04000000 0001155c 2**0 CONTENTS 4 .bss 000000d8 20000000 20000000 00020000 2**2 ALLOC 5 .stack 00010000 200000d8 200000d8 00020000 2**0 ALLOC 6 .ARM.attributes 0000002e 00000000 00000000 0001155c 2**0 CONTENTS, READONLY 7 .comment 0000001d 00000000 00000000 0001158a 2**0 CONTENTS, READONLY 8 .debug_info 0001ea3a 00000000 00000000 000115a7 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 9 .debug_abbrev 000033fb 00000000 00000000 0002ffe1 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 10 .debug_loc 0000a1c6 00000000 00000000 000333dc 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 11 .debug_aranges 00000a88 00000000 00000000 0003d5a2 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 12 .debug_ranges 000016b0 00000000 00000000 0003e02a 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_macro 0000b4fb 00000000 00000000 0003f6da 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_line 00013c24 00000000 00000000 0004abd5 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_str 00119e76 00000000 00000000 0005e7f9 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_frame 00001bf4 00000000 00000000 00178670 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 00000000 : 0: d8 00 01 20 51 0c 00 00 4d 0c 00 00 4d 0c 00 00 ... Q...M...M... 10: 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 00 00 00 00 M...M...M....... ... 2c: 4d 0c 00 00 4d 0c 00 00 00 00 00 00 4d 0c 00 00 M...M.......M... 3c: 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 M...M...M...M... 4c: 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 M...M...M...M... 5c: 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 M...M...M...M... 6c: 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 M...M...M...M... 7c: 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 M...M...M...M... 8c: 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 M...M...M...M... 9c: 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 M...M...M...M... ac: 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 M...M...M...M... bc: 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 M...M...M...M... cc: 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 M...M...M...M... dc: 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 00 00 00 00 M...M...M....... ... f4: e5 04 00 00 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 ....M...M...M... 104: 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 M...M...M...M... 114: 4d 0c 00 00 a9 0b 00 00 15 0c 00 00 1d 0c 00 00 M............... 124: 25 0c 00 00 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 %...M...M...M... 134: 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 M...M...M...M... 144: 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 M...M...M...M... 154: 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 M...M...M...M... 164: 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 M...M...M...M... 174: 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 M...M...M...M... 184: 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 M...M...M...M... 194: 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 M...M...M...M... 1a4: 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 M...M...M...M... 1b4: 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 M...M...M...M... 1c4: 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 M...M...M...M... 1d4: 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 M...M...M...M... 1e4: 4d 0c 00 00 4d 0c 00 00 7d 13 00 00 4d 0c 00 00 M...M...}...M... 1f4: 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 M...M...M...M... 204: 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 M...M...M...M... 214: 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 M...M...M...M... 224: 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 M...M...M...M... 234: 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 M...M...M...M... 244: 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 M...M...M...M... 254: 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 4d 0c 00 00 M...M...M...M... 00000264 <__do_global_dtors_aux>: 264: b510 push {r4, lr} 266: 4c05 ldr r4, [pc, #20] ; (27c <__do_global_dtors_aux+0x18>) 268: 7822 ldrb r2, [r4, #0] 26a: b932 cbnz r2, 27a <__do_global_dtors_aux+0x16> 26c: 4b04 ldr r3, [pc, #16] ; (280 <__do_global_dtors_aux+0x1c>) 26e: b113 cbz r3, 276 <__do_global_dtors_aux+0x12> 270: 4804 ldr r0, [pc, #16] ; (284 <__do_global_dtors_aux+0x20>) 272: f3af 8000 nop.w 276: 2301 movs r3, #1 278: 7023 strb r3, [r4, #0] 27a: bd10 pop {r4, pc} 27c: 20000000 .word 0x20000000 280: 00000000 .word 0x00000000 284: 0000155c .word 0x0000155c 00000288 : 288: b508 push {r3, lr} 28a: 4b03 ldr r3, [pc, #12] ; (298 ) 28c: b11b cbz r3, 296 28e: 4903 ldr r1, [pc, #12] ; (29c ) 290: 4803 ldr r0, [pc, #12] ; (2a0 ) 292: f3af 8000 nop.w 296: bd08 pop {r3, pc} 298: 00000000 .word 0x00000000 29c: 20000004 .word 0x20000004 2a0: 0000155c .word 0x0000155c 000002a4 : typedef uint8_t hri_eic_ctrla_reg_t; typedef uint8_t hri_eic_nmictrl_reg_t; static inline void hri_eic_wait_for_sync(const void *const hw, hri_eic_syncbusy_reg_t reg) { while (((Eic *)hw)->SYNCBUSY.reg & reg) { 2a4: 4a02 ldr r2, [pc, #8] ; (2b0 ) 2a6: 6853 ldr r3, [r2, #4] 2a8: 4203 tst r3, r0 2aa: d1fc bne.n 2a6 }; } 2ac: 4770 bx lr 2ae: bf00 nop 2b0: 40002800 .word 0x40002800 000002b4 <_ext_irq_init>: static inline bool hri_eic_is_syncing(const void *const hw, hri_eic_syncbusy_reg_t reg) { return ((Eic *)hw)->SYNCBUSY.reg & reg; 2b4: 4918 ldr r1, [pc, #96] ; (318 <_ext_irq_init+0x64>) /** * \brief Initialize external interrupt module */ int32_t _ext_irq_init(void (*cb)(const uint32_t pin)) { 2b6: b538 push {r3, r4, r5, lr} 2b8: 684b ldr r3, [r1, #4] 2ba: 4d18 ldr r5, [pc, #96] ; (31c <_ext_irq_init+0x68>) if (!hri_eic_is_syncing(EIC, EIC_SYNCBUSY_SWRST)) { 2bc: f013 0f01 tst.w r3, #1 2c0: d111 bne.n 2e6 <_ext_irq_init+0x32> } static inline hri_eic_ctrla_reg_t hri_eic_get_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) { uint8_t tmp; hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); 2c2: 2003 movs r0, #3 2c4: 47a8 blx r5 tmp = ((Eic *)hw)->CTRLA.reg; 2c6: 780b ldrb r3, [r1, #0] if (hri_eic_get_CTRLA_reg(EIC, EIC_CTRLA_ENABLE)) { 2c8: 079b lsls r3, r3, #30 2ca: d507 bpl.n 2dc <_ext_irq_init+0x28> ((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_ENABLE; 2cc: 780b ldrb r3, [r1, #0] 2ce: f003 03fd and.w r3, r3, #253 ; 0xfd hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); 2d2: 2003 movs r0, #3 ((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_ENABLE; 2d4: 700b strb r3, [r1, #0] hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); 2d6: 47a8 blx r5 hri_eic_clear_CTRLA_ENABLE_bit(EIC); hri_eic_wait_for_sync(EIC, EIC_SYNCBUSY_ENABLE); 2d8: 2002 movs r0, #2 2da: 47a8 blx r5 } static inline void hri_eic_write_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t data) { EIC_CRITICAL_SECTION_ENTER(); ((Eic *)hw)->CTRLA.reg = data; 2dc: 4b0e ldr r3, [pc, #56] ; (318 <_ext_irq_init+0x64>) 2de: 2201 movs r2, #1 2e0: 701a strb r2, [r3, #0] hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); 2e2: 2003 movs r0, #3 2e4: 47a8 blx r5 } hri_eic_write_CTRLA_reg(EIC, EIC_CTRLA_SWRST); } hri_eic_wait_for_sync(EIC, EIC_SYNCBUSY_SWRST); 2e6: 2001 movs r0, #1 2e8: 47a8 blx r5 tmp = ((Eic *)hw)->CTRLA.reg; 2ea: 490b ldr r1, [pc, #44] ; (318 <_ext_irq_init+0x64>) 2ec: 780b ldrb r3, [r1, #0] tmp &= ~EIC_CTRLA_CKSEL; 2ee: f003 03ef and.w r3, r3, #239 ; 0xef ((Eic *)hw)->CTRLA.reg = tmp; 2f2: 700b strb r3, [r1, #0] hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); 2f4: 2003 movs r0, #3 2f6: 47a8 blx r5 } static inline void hri_eic_write_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t data) { EIC_CRITICAL_SECTION_ENTER(); ((Eic *)hw)->NMICTRL.reg = data; 2f8: 2400 movs r4, #0 2fa: 704c strb r4, [r1, #1] } static inline void hri_eic_write_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t data) { EIC_CRITICAL_SECTION_ENTER(); ((Eic *)hw)->EVCTRL.reg = data; 2fc: 608c str r4, [r1, #8] } static inline void hri_eic_write_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t data) { EIC_CRITICAL_SECTION_ENTER(); ((Eic *)hw)->ASYNCH.reg = data; 2fe: 618c str r4, [r1, #24] } static inline void hri_eic_write_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t data) { EIC_CRITICAL_SECTION_ENTER(); ((Eic *)hw)->DEBOUNCEN.reg = data; 300: 630c str r4, [r1, #48] ; 0x30 } static inline void hri_eic_write_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t data) { EIC_CRITICAL_SECTION_ENTER(); ((Eic *)hw)->DPRESCALER.reg = data; 302: 634c str r4, [r1, #52] ; 0x34 ((Eic *)hw)->CONFIG[index].reg = data; 304: 61cc str r4, [r1, #28] 306: 620c str r4, [r1, #32] ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_ENABLE; 308: 780b ldrb r3, [r1, #0] 30a: f043 0302 orr.w r3, r3, #2 30e: 700b strb r3, [r1, #0] hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); 310: 2003 movs r0, #3 312: 47a8 blx r5 hri_eic_set_CTRLA_ENABLE_bit(EIC); callback = cb; return ERR_NONE; } 314: 4620 mov r0, r4 316: bd38 pop {r3, r4, r5, pc} 318: 40002800 .word 0x40002800 31c: 000002a5 .word 0x000002a5 00000320 : * \param[in] head The pointer to the head of timer task list * \param[in] task The pointer to task to add * \param[in] time Current timer time */ static void timer_add_timer_task(struct list_descriptor *list, struct timer_task *const new_task, const uint32_t time) { 320: b5f0 push {r4, r5, r6, r7, lr} struct timer_task *it, *prev = NULL, *head = (struct timer_task *)list_get_head(list); 322: 6805 ldr r5, [r0, #0] if (!head) { 324: b91d cbnz r5, 32e list_insert_as_head(list, new_task); 326: 4b0f ldr r3, [pc, #60] ; (364 ) if (it == head) { list_insert_as_head(list, new_task); } else { list_insert_after(prev, new_task); } } 328: e8bd 40f0 ldmia.w sp!, {r4, r5, r6, r7, lr} list_insert_after(prev, new_task); 32c: 4718 bx r3 if (time_left >= new_task->interval) 32e: f8d1 c008 ldr.w ip, [r1, #8] 332: 462c mov r4, r5 struct timer_task *it, *prev = NULL, *head = (struct timer_task *)list_get_head(list); 334: 2600 movs r6, #0 time_left = it->interval - (0xFFFFFFFF - it->time_label) - time; 336: f1c2 0e01 rsb lr, r2, #1 if (it->time_label <= time) { 33a: e9d4 3701 ldrd r3, r7, [r4, #4] 33e: 4293 cmp r3, r2 time_left = it->interval - (time - it->time_label); 340: bf95 itete ls 342: 19db addls r3, r3, r7 time_left = it->interval - (0xFFFFFFFF - it->time_label) - time; 344: 4473 addhi r3, lr time_left = it->interval - (time - it->time_label); 346: 1a9b subls r3, r3, r2 time_left = it->interval - (0xFFFFFFFF - it->time_label) - time; 348: 19db addhi r3, r3, r7 if (time_left >= new_task->interval) 34a: 459c cmp ip, r3 34c: d907 bls.n 35e * \return A pointer to the next list element or NULL if there is not next * element */ static inline void *list_get_next_element(const void *const element) { return element ? ((struct list_element *)element)->next : NULL; 34e: 6823 ldr r3, [r4, #0] for (it = head; it; it = (struct timer_task *)list_get_next_element(it)) { 350: 4626 mov r6, r4 352: b913 cbnz r3, 35a list_insert_after(prev, new_task); 354: 4b04 ldr r3, [pc, #16] ; (368 ) 356: 4630 mov r0, r6 358: e7e6 b.n 328 35a: 461c mov r4, r3 35c: e7ed b.n 33a if (it == head) { 35e: 42a5 cmp r5, r4 360: d0e1 beq.n 326 362: e7f7 b.n 354 364: 0000052d .word 0x0000052d 368: 00000559 .word 0x00000559 0000036c : /** * \internal Process interrupts */ static void timer_process_counted(struct _timer_device *device) { 36c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} struct timer_descriptor *timer = CONTAINER_OF(device, struct timer_descriptor, device); struct timer_task * it = (struct timer_task *)list_get_head(&timer->tasks); uint32_t time = ++timer->time; 370: e9d0 6504 ldrd r6, r5, [r0, #16] if ((timer->flags & TIMER_FLAG_QUEUE_IS_TAKEN) || (timer->flags & TIMER_FLAG_INTERRUPT_TRIGERRED)) { 374: 7e03 ldrb r3, [r0, #24] uint32_t time = ++timer->time; 376: 3601 adds r6, #1 if ((timer->flags & TIMER_FLAG_QUEUE_IS_TAKEN) || (timer->flags & TIMER_FLAG_INTERRUPT_TRIGERRED)) { 378: 07da lsls r2, r3, #31 { 37a: 4604 mov r4, r0 uint32_t time = ++timer->time; 37c: 6106 str r6, [r0, #16] if ((timer->flags & TIMER_FLAG_QUEUE_IS_TAKEN) || (timer->flags & TIMER_FLAG_INTERRUPT_TRIGERRED)) { 37e: d41f bmi.n 3c0 380: 7e03 ldrb r3, [r0, #24] 382: 079b lsls r3, r3, #30 384: d41c bmi.n 3c0 } while (it && ((time - it->time_label) >= it->interval)) { struct timer_task *tmp = it; list_remove_head(&timer->tasks); 386: f8df 8044 ldr.w r8, [pc, #68] ; 3cc if (TIMER_TASK_REPEAT == tmp->mode) { tmp->time_label = time; timer_add_timer_task(&timer->tasks, tmp, time); 38a: f8df 9044 ldr.w r9, [pc, #68] ; 3d0 list_remove_head(&timer->tasks); 38e: f100 0714 add.w r7, r0, #20 while (it && ((time - it->time_label) >= it->interval)) { 392: b1cd cbz r5, 3c8 394: 686b ldr r3, [r5, #4] 396: 68aa ldr r2, [r5, #8] 398: 1af3 subs r3, r6, r3 39a: 4293 cmp r3, r2 39c: d314 bcc.n 3c8 list_remove_head(&timer->tasks); 39e: 4638 mov r0, r7 3a0: 47c0 blx r8 if (TIMER_TASK_REPEAT == tmp->mode) { 3a2: 7c2b ldrb r3, [r5, #16] 3a4: 2b01 cmp r3, #1 3a6: d104 bne.n 3b2 tmp->time_label = time; 3a8: 606e str r6, [r5, #4] timer_add_timer_task(&timer->tasks, tmp, time); 3aa: 4632 mov r2, r6 3ac: 4629 mov r1, r5 3ae: 4638 mov r0, r7 3b0: 47c8 blx r9 } it = (struct timer_task *)list_get_head(&timer->tasks); 3b2: f8d4 a014 ldr.w sl, [r4, #20] tmp->cb(tmp); 3b6: 68eb ldr r3, [r5, #12] 3b8: 4628 mov r0, r5 3ba: 4798 blx r3 it = (struct timer_task *)list_get_head(&timer->tasks); 3bc: 4655 mov r5, sl 3be: e7e8 b.n 392 timer->flags |= TIMER_FLAG_INTERRUPT_TRIGERRED; 3c0: 7e23 ldrb r3, [r4, #24] 3c2: f043 0302 orr.w r3, r3, #2 3c6: 7623 strb r3, [r4, #24] } } 3c8: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 3cc: 00000561 .word 0x00000561 3d0: 00000321 .word 0x00000321 000003d4 : { 3d4: b538 push {r3, r4, r5, lr} 3d6: 460d mov r5, r1 ASSERT(descr && hw); 3d8: 4604 mov r4, r0 3da: b110 cbz r0, 3e2 3dc: 1e08 subs r0, r1, #0 3de: bf18 it ne 3e0: 2001 movne r0, #1 3e2: 223b movs r2, #59 ; 0x3b 3e4: 4905 ldr r1, [pc, #20] ; (3fc ) 3e6: 4b06 ldr r3, [pc, #24] ; (400 ) 3e8: 4798 blx r3 _timer_init(&descr->device, hw); 3ea: 4b06 ldr r3, [pc, #24] ; (404 ) 3ec: 4629 mov r1, r5 3ee: 4620 mov r0, r4 3f0: 4798 blx r3 descr->device.timer_cb.period_expired = timer_process_counted; 3f2: 4b05 ldr r3, [pc, #20] ; (408 ) 3f4: 6023 str r3, [r4, #0] descr->time = 0; 3f6: 2000 movs r0, #0 3f8: 6120 str r0, [r4, #16] } 3fa: bd38 pop {r3, r4, r5, pc} 3fc: 000013fc .word 0x000013fc 400: 0000056d .word 0x0000056d 404: 00001231 .word 0x00001231 408: 0000036d .word 0x0000036d 0000040c : /** * \brief Sync version of I2C I/O write */ static int32_t i2c_m_sync_write(struct io_descriptor *io, const uint8_t *buf, const uint16_t n) { 40c: b51f push {r0, r1, r2, r3, r4, lr} struct i2c_m_sync_desc *i2c = CONTAINER_OF(io, struct i2c_m_sync_desc, io); struct _i2c_m_msg msg; int32_t ret; msg.addr = i2c->slave_addr; 40e: 8903 ldrh r3, [r0, #8] 410: f8ad 3004 strh.w r3, [sp, #4] msg.len = n; msg.flags = I2C_M_STOP; 414: f44f 4300 mov.w r3, #32768 ; 0x8000 418: f8ad 3006 strh.w r3, [sp, #6] msg.buffer = (uint8_t *)buf; 41c: 9103 str r1, [sp, #12] ret = _i2c_m_sync_transfer(&i2c->device, &msg); 41e: 4b05 ldr r3, [pc, #20] ; (434 ) msg.len = n; 420: 9202 str r2, [sp, #8] ret = _i2c_m_sync_transfer(&i2c->device, &msg); 422: a901 add r1, sp, #4 424: 3814 subs r0, #20 { 426: 4614 mov r4, r2 ret = _i2c_m_sync_transfer(&i2c->device, &msg); 428: 4798 blx r3 if (ret) { return ret; } return n; } 42a: 2800 cmp r0, #0 42c: bf08 it eq 42e: 4620 moveq r0, r4 430: b004 add sp, #16 432: bd10 pop {r4, pc} 434: 00000a39 .word 0x00000a39 00000438 : { 438: b51f push {r0, r1, r2, r3, r4, lr} msg.addr = i2c->slave_addr; 43a: 8903 ldrh r3, [r0, #8] 43c: f8ad 3004 strh.w r3, [sp, #4] msg.flags = I2C_M_STOP | I2C_M_RD; 440: f248 0301 movw r3, #32769 ; 0x8001 444: f8ad 3006 strh.w r3, [sp, #6] msg.buffer = buf; 448: 9103 str r1, [sp, #12] ret = _i2c_m_sync_transfer(&i2c->device, &msg); 44a: 4b05 ldr r3, [pc, #20] ; (460 ) msg.len = n; 44c: 9202 str r2, [sp, #8] ret = _i2c_m_sync_transfer(&i2c->device, &msg); 44e: a901 add r1, sp, #4 450: 3814 subs r0, #20 { 452: 4614 mov r4, r2 ret = _i2c_m_sync_transfer(&i2c->device, &msg); 454: 4798 blx r3 } 456: 2800 cmp r0, #0 458: bf08 it eq 45a: 4620 moveq r0, r4 45c: b004 add sp, #16 45e: bd10 pop {r4, pc} 460: 00000a39 .word 0x00000a39 00000464 : /** * \brief Sync version of i2c initialize */ int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw) { 464: b538 push {r3, r4, r5, lr} int32_t init_status; ASSERT(i2c); 466: 4604 mov r4, r0 468: 3800 subs r0, #0 46a: bf18 it ne 46c: 2001 movne r0, #1 46e: 4b07 ldr r3, [pc, #28] ; (48c ) { 470: 460d mov r5, r1 ASSERT(i2c); 472: 225e movs r2, #94 ; 0x5e 474: 4906 ldr r1, [pc, #24] ; (490 ) 476: 4798 blx r3 init_status = _i2c_m_sync_init(&i2c->device, hw); 478: 4b06 ldr r3, [pc, #24] ; (494 ) 47a: 4629 mov r1, r5 47c: 4620 mov r0, r4 47e: 4798 blx r3 if (init_status) { 480: b918 cbnz r0, 48a return init_status; } /* Init I/O */ i2c->io.read = i2c_m_sync_read; 482: 4b05 ldr r3, [pc, #20] ; (498 ) 484: 61a3 str r3, [r4, #24] i2c->io.write = i2c_m_sync_write; 486: 4b05 ldr r3, [pc, #20] ; (49c ) 488: 6163 str r3, [r4, #20] return ERR_NONE; } 48a: bd38 pop {r3, r4, r5, pc} 48c: 0000056d .word 0x0000056d 490: 00001413 .word 0x00001413 494: 00000a09 .word 0x00000a09 498: 00000439 .word 0x00000439 49c: 0000040d .word 0x0000040d 000004a0 <_init_chip>: } static inline void hri_nvmctrl_set_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) { NVMCTRL_CRITICAL_SECTION_ENTER(); ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_RWS(mask); 4a0: 4a0a ldr r2, [pc, #40] ; (4cc <_init_chip+0x2c>) 4a2: 8813 ldrh r3, [r2, #0] 4a4: b29b uxth r3, r3 /** * \brief Initialize the hardware abstraction layer */ void _init_chip(void) { 4a6: b510 push {r4, lr} 4a8: f443 63a0 orr.w r3, r3, #1280 ; 0x500 4ac: 8013 strh r3, [r2, #0] hri_nvmctrl_set_CTRLA_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE); _osc32kctrl_init_sources(); 4ae: 4b08 ldr r3, [pc, #32] ; (4d0 <_init_chip+0x30>) 4b0: 4798 blx r3 _oscctrl_init_sources(); 4b2: 4b08 ldr r3, [pc, #32] ; (4d4 <_init_chip+0x34>) 4b4: 4798 blx r3 _mclk_init(); 4b6: 4b08 ldr r3, [pc, #32] ; (4d8 <_init_chip+0x38>) 4b8: 4798 blx r3 #if _GCLK_INIT_1ST _gclk_init_generators_by_fref(_GCLK_INIT_1ST); #endif _oscctrl_init_referenced_generators(); 4ba: 4b08 ldr r3, [pc, #32] ; (4dc <_init_chip+0x3c>) 4bc: 4798 blx r3 #endif #if CONF_CMCC_ENABLE cache_init(); #endif } 4be: e8bd 4010 ldmia.w sp!, {r4, lr} _gclk_init_generators_by_fref(_GCLK_INIT_LAST); 4c2: 4b07 ldr r3, [pc, #28] ; (4e0 <_init_chip+0x40>) 4c4: f640 70ff movw r0, #4095 ; 0xfff 4c8: 4718 bx r3 4ca: bf00 nop 4cc: 41004000 .word 0x41004000 4d0: 00000cd5 .word 0x00000cd5 4d4: 00000573 .word 0x00000573 4d8: 000005b1 .word 0x000005b1 4dc: 00000575 .word 0x00000575 4e0: 00000c2d .word 0x00000c2d 000004e4 : return tmp; } static inline hri_ramecc_intflag_reg_t hri_ramecc_read_INTFLAG_reg(const void *const hw) { return ((Ramecc *)hw)->INTFLAG.reg; 4e4: 4a0b ldr r2, [pc, #44] ; (514 ) 4e6: 7893 ldrb r3, [r2, #2] /** * \internal RAMECC interrupt handler */ void RAMECC_Handler(void) { 4e8: b082 sub sp, #8 4ea: b2db uxtb r3, r3 struct _ramecc_device *dev = (struct _ramecc_device *)&device; volatile uint32_t int_mask = hri_ramecc_read_INTFLAG_reg(RAMECC); 4ec: 9301 str r3, [sp, #4] if (int_mask & RAMECC_INTFLAG_DUALE && dev->ramecc_cb.dual_bit_err) { 4ee: 9b01 ldr r3, [sp, #4] 4f0: 0799 lsls r1, r3, #30 4f2: d505 bpl.n 500 4f4: 4b08 ldr r3, [pc, #32] ; (518 ) 4f6: 681b ldr r3, [r3, #0] 4f8: b113 cbz r3, 500 return tmp; } static inline hri_ramecc_erraddr_reg_t hri_ramecc_read_ERRADDR_reg(const void *const hw) { return ((Ramecc *)hw)->ERRADDR.reg; 4fa: 6850 ldr r0, [r2, #4] } else if (int_mask & RAMECC_INTFLAG_SINGLEE && dev->ramecc_cb.single_bit_err) { dev->ramecc_cb.single_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC)); } else { return; } } 4fc: b002 add sp, #8 dev->ramecc_cb.single_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC)); 4fe: 4718 bx r3 } else if (int_mask & RAMECC_INTFLAG_SINGLEE && dev->ramecc_cb.single_bit_err) { 500: 9b01 ldr r3, [sp, #4] 502: 07db lsls r3, r3, #31 504: d504 bpl.n 510 506: 4b04 ldr r3, [pc, #16] ; (518 ) 508: 685b ldr r3, [r3, #4] 50a: b10b cbz r3, 510 50c: 4a01 ldr r2, [pc, #4] ; (514 ) 50e: e7f4 b.n 4fa } 510: b002 add sp, #8 512: 4770 bx lr 514: 41020000 .word 0x41020000 518: 2000003c .word 0x2000003c 0000051c : * \brief Check whether element belongs to list */ bool is_list_element(const struct list_descriptor *const list, const void *const element) { struct list_element *it; for (it = list->head; it; it = it->next) { 51c: 6800 ldr r0, [r0, #0] 51e: b900 cbnz r0, 522 520: 4770 bx lr if (it == element) { 522: 4288 cmp r0, r1 524: d1fa bne.n 51c return true; 526: 2001 movs r0, #1 } } return false; } 528: 4770 bx lr ... 0000052c : /** * \brief Insert an element as list head */ void list_insert_as_head(struct list_descriptor *const list, void *const element) { 52c: b538 push {r3, r4, r5, lr} ASSERT(!is_list_element(list, element)); 52e: 4b07 ldr r3, [pc, #28] ; (54c ) { 530: 460d mov r5, r1 532: 4604 mov r4, r0 ASSERT(!is_list_element(list, element)); 534: 4798 blx r3 536: f080 0001 eor.w r0, r0, #1 53a: 4b05 ldr r3, [pc, #20] ; (550 ) 53c: 4905 ldr r1, [pc, #20] ; (554 ) 53e: 2239 movs r2, #57 ; 0x39 540: b2c0 uxtb r0, r0 542: 4798 blx r3 ((struct list_element *)element)->next = list->head; 544: 6823 ldr r3, [r4, #0] 546: 602b str r3, [r5, #0] list->head = (struct list_element *)element; 548: 6025 str r5, [r4, #0] } 54a: bd38 pop {r3, r4, r5, pc} 54c: 0000051d .word 0x0000051d 550: 0000056d .word 0x0000056d 554: 0000142f .word 0x0000142f 00000558 : /** * \brief Insert an element after the given list element */ void list_insert_after(void *const after, void *const element) { ((struct list_element *)element)->next = ((struct list_element *)after)->next; 558: 6803 ldr r3, [r0, #0] 55a: 600b str r3, [r1, #0] ((struct list_element *)after)->next = (struct list_element *)element; 55c: 6001 str r1, [r0, #0] } 55e: 4770 bx lr 00000560 : /** * \brief Removes list head */ void *list_remove_head(struct list_descriptor *const list) { if (list->head) { 560: 6803 ldr r3, [r0, #0] 562: b10b cbz r3, 568 struct list_element *tmp = list->head; list->head = list->head->next; 564: 681a ldr r2, [r3, #0] 566: 6002 str r2, [r0, #0] return (void *)tmp; } return NULL; } 568: 4618 mov r0, r3 56a: 4770 bx lr 0000056c : /** * \brief Assert function */ void assert(const bool condition, const char *const file, const int line) { if (!(condition)) { 56c: b900 cbnz r0, 570 __asm("BKPT #0"); 56e: be00 bkpt 0x0000 } (void)file; (void)line; } 570: 4770 bx lr 00000572 <_oscctrl_init_sources>: hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(hw, 1); #endif #endif (void)hw; } 572: 4770 bx lr 00000574 <_oscctrl_init_referenced_generators>: static inline void hri_oscctrl_write_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllratio_reg_t data) { OSCCTRL_CRITICAL_SECTION_ENTER(); ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = data; 574: 4b0c ldr r3, [pc, #48] ; (5a8 <_oscctrl_init_referenced_generators+0x34>) 576: 4a0d ldr r2, [pc, #52] ; (5ac <_oscctrl_init_referenced_generators+0x38>) 578: 635a str r2, [r3, #52] ; 0x34 while (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & reg) { 57a: 6bda ldr r2, [r3, #60] ; 0x3c 57c: f012 0f06 tst.w r2, #6 580: d1fb bne.n 57a <_oscctrl_init_referenced_generators+0x6> static inline void hri_oscctrl_write_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t data) { OSCCTRL_CRITICAL_SECTION_ENTER(); ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = data; 582: f44f 6202 mov.w r2, #2080 ; 0x820 586: 639a str r2, [r3, #56] ; 0x38 ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = data; 588: 2202 movs r2, #2 58a: f883 2030 strb.w r2, [r3, #48] ; 0x30 while (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & reg) { 58e: 4a06 ldr r2, [pc, #24] ; (5a8 <_oscctrl_init_referenced_generators+0x34>) 590: 6bd3 ldr r3, [r2, #60] ; 0x3c 592: 0798 lsls r0, r3, #30 594: d4fc bmi.n 590 <_oscctrl_init_referenced_generators+0x1c> return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK) 596: 4b04 ldr r3, [pc, #16] ; (5a8 <_oscctrl_init_referenced_generators+0x34>) 598: 6c1a ldr r2, [r3, #64] ; 0x40 #endif #endif #if CONF_FDPLL0_CONFIG == 1 #if CONF_FDPLL0_ENABLE == 1 while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw, 0) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw, 0))) 59a: 07d1 lsls r1, r2, #31 59c: d402 bmi.n 5a4 <_oscctrl_init_referenced_generators+0x30> return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY) 59e: 6c1a ldr r2, [r3, #64] ; 0x40 5a0: 0792 lsls r2, r2, #30 5a2: d5f9 bpl.n 598 <_oscctrl_init_referenced_generators+0x24> hri_gclk_write_GENCTRL_SRC_bf(GCLK, 0, CONF_GCLK_GEN_0_SOURCE); while (hri_gclk_get_SYNCBUSY_GENCTRL0_bit(GCLK)) ; #endif (void)hw; } 5a4: 4770 bx lr 5a6: bf00 nop 5a8: 40001000 .word 0x40001000 5ac: 00010e4d .word 0x00010e4d 000005b0 <_mclk_init>: } static inline void hri_mclk_write_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t data) { MCLK_CRITICAL_SECTION_ENTER(); ((Mclk *)hw)->CPUDIV.reg = data; 5b0: 4b01 ldr r3, [pc, #4] ; (5b8 <_mclk_init+0x8>) 5b2: 2201 movs r2, #1 5b4: 715a strb r2, [r3, #5] */ void _mclk_init(void) { void *hw = (void *)MCLK; hri_mclk_write_CPUDIV_reg(hw, MCLK_CPUDIV_DIV(CONF_MCLK_CPUDIV)); } 5b6: 4770 bx lr 5b8: 40000800 .word 0x40000800 000005bc : typedef uint8_t hri_sercomusart_rxerrcnt_reg_t; typedef uint8_t hri_sercomusart_rxpl_reg_t; static inline void hri_sercomi2cm_wait_for_sync(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) { while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) { 5bc: 69c3 ldr r3, [r0, #28] 5be: 420b tst r3, r1 5c0: d1fc bne.n 5bc }; } 5c2: 4770 bx lr 000005c4 : return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg; } static inline void hri_sercomusart_wait_for_sync(const void *const hw, hri_sercomusart_syncbusy_reg_t reg) { while (((Sercom *)hw)->USART.SYNCBUSY.reg & reg) { 5c4: 69c3 ldr r3, [r0, #28] 5c6: 420b tst r3, r1 5c8: d1fc bne.n 5c4 }; } 5ca: 4770 bx lr 000005cc : } static inline void hri_sercomi2cm_clear_CTRLA_ENABLE_bit(const void *const hw) { SERCOM_CRITICAL_SECTION_ENTER(); ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE; 5cc: 6802 ldr r2, [r0, #0] hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); 5ce: 4b03 ldr r3, [pc, #12] ; (5dc ) ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE; 5d0: f022 0202 bic.w r2, r2, #2 5d4: 6002 str r2, [r0, #0] hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); 5d6: 2103 movs r1, #3 5d8: 4718 bx r3 5da: bf00 nop 5dc: 000005bd .word 0x000005bd 000005e0 : } static inline void hri_sercomusart_clear_CTRLA_ENABLE_bit(const void *const hw) { SERCOM_CRITICAL_SECTION_ENTER(); ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE; 5e0: 6802 ldr r2, [r0, #0] hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); 5e2: 4b03 ldr r3, [pc, #12] ; (5f0 ) ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE; 5e4: f022 0202 bic.w r2, r2, #2 5e8: 6002 str r2, [r0, #0] hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); 5ea: 2103 movs r1, #3 5ec: 4718 bx r3 5ee: bf00 nop 5f0: 000005c5 .word 0x000005c5 000005f4 <_sercom_get_hardware_index>: /** * \brief Retrieve ordinal number of the given sercom hardware instance */ static uint8_t _sercom_get_hardware_index(const void *const hw) { 5f4: b570 push {r4, r5, r6, lr} Sercom *const sercom_modules[] = SERCOM_INSTS; 5f6: 4d0c ldr r5, [pc, #48] ; (628 <_sercom_get_hardware_index+0x34>) { 5f8: 4606 mov r6, r0 Sercom *const sercom_modules[] = SERCOM_INSTS; 5fa: cd0f ldmia r5!, {r0, r1, r2, r3} { 5fc: b088 sub sp, #32 Sercom *const sercom_modules[] = SERCOM_INSTS; 5fe: 466c mov r4, sp 600: c40f stmia r4!, {r0, r1, r2, r3} 602: e895 000f ldmia.w r5, {r0, r1, r2, r3} 606: e884 000f stmia.w r4, {r0, r1, r2, r3} /* Find index for SERCOM instance. */ for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) { 60a: 466a mov r2, sp 60c: 2300 movs r3, #0 if ((uint32_t)hw == (uint32_t)sercom_modules[i]) { 60e: f852 1b04 ldr.w r1, [r2], #4 612: 42b1 cmp r1, r6 614: d102 bne.n 61c <_sercom_get_hardware_index+0x28> return i; 616: b2d8 uxtb r0, r3 } } return 0; } 618: b008 add sp, #32 61a: bd70 pop {r4, r5, r6, pc} for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) { 61c: 3301 adds r3, #1 61e: 2b08 cmp r3, #8 620: d1f5 bne.n 60e <_sercom_get_hardware_index+0x1a> return 0; 622: 2000 movs r0, #0 624: e7f8 b.n 618 <_sercom_get_hardware_index+0x24> 626: bf00 nop 628: 00001468 .word 0x00001468 0000062c <_sercom_get_irq_num>: /** * \brief Retrieve IRQ number for the given hardware instance */ static uint8_t _sercom_get_irq_num(const void *const hw) { 62c: b508 push {r3, lr} return SERCOM0_0_IRQn + (_sercom_get_hardware_index(hw) << 2); 62e: 4b03 ldr r3, [pc, #12] ; (63c <_sercom_get_irq_num+0x10>) 630: 4798 blx r3 632: 0080 lsls r0, r0, #2 634: 302e adds r0, #46 ; 0x2e } 636: f000 00fe and.w r0, r0, #254 ; 0xfe 63a: bd08 pop {r3, pc} 63c: 000005f5 .word 0x000005f5 00000640 <__NVIC_EnableIRQ>: */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 640: 0942 lsrs r2, r0, #5 642: 2301 movs r3, #1 644: f000 001f and.w r0, r0, #31 648: fa03 f000 lsl.w r0, r3, r0 64c: 4b01 ldr r3, [pc, #4] ; (654 <__NVIC_EnableIRQ+0x14>) 64e: f843 0022 str.w r0, [r3, r2, lsl #2] } } 652: 4770 bx lr 654: e000e100 .word 0xe000e100 00000658 <__NVIC_DisableIRQ>: */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 658: 0943 lsrs r3, r0, #5 65a: 2201 movs r2, #1 65c: f000 001f and.w r0, r0, #31 660: fa02 f000 lsl.w r0, r2, r0 664: 3320 adds r3, #32 666: 4a04 ldr r2, [pc, #16] ; (678 <__NVIC_DisableIRQ+0x20>) 668: f842 0023 str.w r0, [r2, r3, lsl #2] \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); 66c: f3bf 8f4f dsb sy __ASM volatile ("isb 0xF":::"memory"); 670: f3bf 8f6f isb sy __DSB(); __ISB(); } } 674: 4770 bx lr 676: bf00 nop 678: e000e100 .word 0xe000e100 0000067c <__NVIC_ClearPendingIRQ>: */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 67c: 0943 lsrs r3, r0, #5 67e: 2201 movs r2, #1 680: f000 001f and.w r0, r0, #31 684: fa02 f000 lsl.w r0, r2, r0 688: 3360 adds r3, #96 ; 0x60 68a: 4a02 ldr r2, [pc, #8] ; (694 <__NVIC_ClearPendingIRQ+0x18>) 68c: f842 0023 str.w r0, [r2, r3, lsl #2] } } 690: 4770 bx lr 692: bf00 nop 694: e000e100 .word 0xe000e100 00000698 <_get_i2cm_index>: { 698: b508 push {r3, lr} uint8_t sercom_offset = _sercom_get_hardware_index(hw); 69a: 4b07 ldr r3, [pc, #28] ; (6b8 <_get_i2cm_index+0x20>) 69c: 4798 blx r3 if (_i2cms[i].number == sercom_offset) { 69e: 2803 cmp r0, #3 6a0: d008 beq.n 6b4 <_get_i2cm_index+0x1c> ASSERT(false); 6a2: 2000 movs r0, #0 6a4: 4905 ldr r1, [pc, #20] ; (6bc <_get_i2cm_index+0x24>) 6a6: 4b06 ldr r3, [pc, #24] ; (6c0 <_get_i2cm_index+0x28>) 6a8: f240 32ce movw r2, #974 ; 0x3ce 6ac: 4798 blx r3 6ae: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff } 6b2: bd08 pop {r3, pc} return i; 6b4: 2000 movs r0, #0 6b6: e7fc b.n 6b2 <_get_i2cm_index+0x1a> 6b8: 000005f5 .word 0x000005f5 6bc: 0000144d .word 0x0000144d 6c0: 0000056d .word 0x0000056d 000006c4 <_sercom_i2c_send_stop>: } static inline void hri_sercomi2cm_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) { SERCOM_CRITICAL_SECTION_ENTER(); ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask); 6c4: 6842 ldr r2, [r0, #4] hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); 6c6: 4b03 ldr r3, [pc, #12] ; (6d4 <_sercom_i2c_send_stop+0x10>) ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask); 6c8: f442 3240 orr.w r2, r2, #196608 ; 0x30000 6cc: 6042 str r2, [r0, #4] hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); 6ce: 2104 movs r1, #4 6d0: 4718 bx r3 6d2: bf00 nop 6d4: 000005bd .word 0x000005bd 000006d8 <_sercom_i2c_sync_analyse_flags>: { 6d8: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 6dc: 460e mov r6, r1 6de: 4614 mov r4, r2 ((Sercom *)hw)->I2CM.STATUS.reg |= mask; } static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_reg(const void *const hw) { hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); 6e0: 2104 movs r1, #4 6e2: 4a56 ldr r2, [pc, #344] ; (83c <_sercom_i2c_sync_analyse_flags+0x164>) tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; 6e4: f8d0 8000 ldr.w r8, [r0] 6e8: 4605 mov r5, r0 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); 6ea: 4790 blx r2 return ((Sercom *)hw)->I2CM.STATUS.reg; 6ec: 8b43 ldrh r3, [r0, #26] if (flags & MB_FLAG) { 6ee: f016 0f01 tst.w r6, #1 6f2: b29b uxth r3, r3 6f4: 4617 mov r7, r2 6f6: d064 beq.n 7c2 <_sercom_i2c_sync_analyse_flags+0xea> if (status & SERCOM_I2CM_STATUS_ARBLOST) { 6f8: 079f lsls r7, r3, #30 6fa: d516 bpl.n 72a <_sercom_i2c_sync_analyse_flags+0x52> ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; 6fc: 2201 movs r2, #1 6fe: 7602 strb r2, [r0, #24] msg->flags |= I2C_M_FAIL; 700: 8862 ldrh r2, [r4, #2] 702: b292 uxth r2, r2 704: f442 5280 orr.w r2, r2, #4096 ; 0x1000 708: 8062 strh r2, [r4, #2] msg->flags &= ~I2C_M_BUSY; 70a: 8862 ldrh r2, [r4, #2] if (status & SERCOM_I2CM_STATUS_BUSERR) { 70c: f003 0601 and.w r6, r3, #1 msg->flags &= ~I2C_M_BUSY; 710: f422 7280 bic.w r2, r2, #256 ; 0x100 714: 0412 lsls r2, r2, #16 if (status & SERCOM_I2CM_STATUS_BUSERR) { 716: f1c6 26ff rsb r6, r6, #4278255360 ; 0xff00ff00 msg->flags &= ~I2C_M_BUSY; 71a: 0c12 lsrs r2, r2, #16 if (status & SERCOM_I2CM_STATUS_BUSERR) { 71c: f506 067f add.w r6, r6, #16711680 ; 0xff0000 msg->flags &= ~I2C_M_BUSY; 720: 8062 strh r2, [r4, #2] if (status & SERCOM_I2CM_STATUS_BUSERR) { 722: 36fc adds r6, #252 ; 0xfc } 724: 4630 mov r0, r6 726: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} if (status & SERCOM_I2CM_STATUS_RXNACK) { 72a: f013 0604 ands.w r6, r3, #4 72e: d015 beq.n 75c <_sercom_i2c_sync_analyse_flags+0x84> if (msg->len > 0) { 730: 6863 ldr r3, [r4, #4] 732: 2b00 cmp r3, #0 msg->flags |= I2C_M_FAIL; 734: bfc1 itttt gt 736: 8863 ldrhgt r3, [r4, #2] 738: b29b uxthgt r3, r3 73a: f443 5380 orrgt.w r3, r3, #4096 ; 0x1000 73e: 8063 strhgt r3, [r4, #2] if (msg->flags & I2C_M_STOP) { 740: 8863 ldrh r3, [r4, #2] 742: 041e lsls r6, r3, #16 744: d501 bpl.n 74a <_sercom_i2c_sync_analyse_flags+0x72> _sercom_i2c_send_stop(hw); 746: 4b3e ldr r3, [pc, #248] ; (840 <_sercom_i2c_sync_analyse_flags+0x168>) 748: 4798 blx r3 msg->flags &= ~I2C_M_BUSY; 74a: 8863 ldrh r3, [r4, #2] 74c: f423 7380 bic.w r3, r3, #256 ; 0x100 750: 041b lsls r3, r3, #16 752: 0c1b lsrs r3, r3, #16 754: 8063 strh r3, [r4, #2] return I2C_NACK; 756: f06f 0601 mvn.w r6, #1 75a: e7e3 b.n 724 <_sercom_i2c_sync_analyse_flags+0x4c> if (msg->flags & I2C_M_TEN) { 75c: 8863 ldrh r3, [r4, #2] 75e: f413 6780 ands.w r7, r3, #1024 ; 0x400 762: d015 beq.n 790 <_sercom_i2c_sync_analyse_flags+0xb8> ((((msg->addr & TEN_ADDR_MASK) >> 8) | TEN_ADDR_FRAME) << 1) | I2C_M_RD 764: 8823 ldrh r3, [r4, #0] hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); 766: 2104 movs r1, #4 768: 09db lsrs r3, r3, #7 | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); 76a: f003 0706 and.w r7, r3, #6 76e: 4790 blx r2 return ((Sercom *)hw)->I2CM.ADDR.reg; 770: 6a43 ldr r3, [r0, #36] ; 0x24 772: f403 4380 and.w r3, r3, #16384 ; 0x4000 776: 433b orrs r3, r7 hri_sercomi2cm_write_ADDR_reg(hw, 778: f043 03f1 orr.w r3, r3, #241 ; 0xf1 ((Sercom *)hw)->I2CM.ADDR.reg = data; 77c: 6243 str r3, [r0, #36] ; 0x24 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); 77e: 2104 movs r1, #4 780: 4790 blx r2 msg->flags &= ~I2C_M_TEN; 782: 8863 ldrh r3, [r4, #2] 784: f423 6380 bic.w r3, r3, #1024 ; 0x400 msg->flags &= ~I2C_M_BUSY; 788: 041b lsls r3, r3, #16 78a: 0c1b lsrs r3, r3, #16 78c: 8063 strh r3, [r4, #2] 78e: e7c9 b.n 724 <_sercom_i2c_sync_analyse_flags+0x4c> if (msg->len == 0) { 790: 6866 ldr r6, [r4, #4] 792: b94e cbnz r6, 7a8 <_sercom_i2c_sync_analyse_flags+0xd0> if (msg->flags & I2C_M_STOP) { 794: 8863 ldrh r3, [r4, #2] 796: 0418 lsls r0, r3, #16 798: d502 bpl.n 7a0 <_sercom_i2c_sync_analyse_flags+0xc8> _sercom_i2c_send_stop(hw); 79a: 4b29 ldr r3, [pc, #164] ; (840 <_sercom_i2c_sync_analyse_flags+0x168>) 79c: 4628 mov r0, r5 79e: 4798 blx r3 msg->flags &= ~I2C_M_BUSY; 7a0: 8863 ldrh r3, [r4, #2] 7a2: f423 7380 bic.w r3, r3, #256 ; 0x100 7a6: e7ef b.n 788 <_sercom_i2c_sync_analyse_flags+0xb0> hri_sercomi2cm_write_DATA_reg(hw, *msg->buffer); 7a8: 68a3 ldr r3, [r4, #8] 7aa: 781b ldrb r3, [r3, #0] ((Sercom *)hw)->I2CM.DATA.reg = data; 7ac: 6283 str r3, [r0, #40] ; 0x28 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); 7ae: 2104 movs r1, #4 7b0: 4790 blx r2 msg->buffer++; 7b2: 68a3 ldr r3, [r4, #8] 7b4: 3301 adds r3, #1 7b6: 60a3 str r3, [r4, #8] msg->len--; 7b8: 6863 ldr r3, [r4, #4] 7ba: 3b01 subs r3, #1 7bc: 6063 str r3, [r4, #4] return I2C_OK; 7be: 2600 movs r6, #0 } 7c0: e7b0 b.n 724 <_sercom_i2c_sync_analyse_flags+0x4c> } else if (flags & SB_FLAG) { 7c2: f016 0602 ands.w r6, r6, #2 7c6: d0ad beq.n 724 <_sercom_i2c_sync_analyse_flags+0x4c> if ((msg->len) && !(status & SERCOM_I2CM_STATUS_RXNACK)) { 7c8: 6862 ldr r2, [r4, #4] 7ca: 2a00 cmp r2, #0 7cc: d032 beq.n 834 <_sercom_i2c_sync_analyse_flags+0x15c> 7ce: 0759 lsls r1, r3, #29 7d0: d430 bmi.n 834 <_sercom_i2c_sync_analyse_flags+0x15c> msg->len--; 7d2: 3a01 subs r2, #1 7d4: f3c8 61c0 ubfx r1, r8, #27, #1 7d8: 6062 str r2, [r4, #4] if ((msg->len == 0 && !sclsm) || (msg->len == 1 && sclsm)) { 7da: b99a cbnz r2, 804 <_sercom_i2c_sync_analyse_flags+0x12c> 7dc: b1a9 cbz r1, 80a <_sercom_i2c_sync_analyse_flags+0x132> if (msg->flags & I2C_M_STOP) { 7de: 8863 ldrh r3, [r4, #2] 7e0: 041b lsls r3, r3, #16 7e2: d508 bpl.n 7f6 <_sercom_i2c_sync_analyse_flags+0x11e> ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_SMEN; 7e4: 686b ldr r3, [r5, #4] 7e6: f423 7380 bic.w r3, r3, #256 ; 0x100 7ea: 606b str r3, [r5, #4] hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); 7ec: 2104 movs r1, #4 7ee: 4628 mov r0, r5 7f0: 47b8 blx r7 _sercom_i2c_send_stop(hw); 7f2: 4b13 ldr r3, [pc, #76] ; (840 <_sercom_i2c_sync_analyse_flags+0x168>) 7f4: 4798 blx r3 msg->flags &= ~I2C_M_BUSY; 7f6: 8863 ldrh r3, [r4, #2] 7f8: f423 7380 bic.w r3, r3, #256 ; 0x100 7fc: 041b lsls r3, r3, #16 7fe: 0c1b lsrs r3, r3, #16 800: 8063 strh r3, [r4, #2] 802: e00c b.n 81e <_sercom_i2c_sync_analyse_flags+0x146> if ((msg->len == 0 && !sclsm) || (msg->len == 1 && sclsm)) { 804: 2a01 cmp r2, #1 806: d10a bne.n 81e <_sercom_i2c_sync_analyse_flags+0x146> 808: b149 cbz r1, 81e <_sercom_i2c_sync_analyse_flags+0x146> ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; 80a: 686b ldr r3, [r5, #4] 80c: f443 2380 orr.w r3, r3, #262144 ; 0x40000 810: 606b str r3, [r5, #4] hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); 812: 2104 movs r1, #4 814: 4628 mov r0, r5 816: 47b8 blx r7 if (msg->len == 0) { 818: 6863 ldr r3, [r4, #4] 81a: 2b00 cmp r3, #0 81c: d0df beq.n 7de <_sercom_i2c_sync_analyse_flags+0x106> hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); 81e: 2104 movs r1, #4 820: 4628 mov r0, r5 822: 47b8 blx r7 *msg->buffer++ = hri_sercomi2cm_read_DATA_reg(hw); 824: 68a3 ldr r3, [r4, #8] return ((Sercom *)hw)->I2CM.DATA.reg; 826: 6aaa ldr r2, [r5, #40] ; 0x28 828: 1c59 adds r1, r3, #1 82a: 60a1 str r1, [r4, #8] 82c: 701a strb r2, [r3, #0] ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; 82e: 2302 movs r3, #2 830: 762b strb r3, [r5, #24] 832: e7c4 b.n 7be <_sercom_i2c_sync_analyse_flags+0xe6> 834: 2302 movs r3, #2 836: 762b strb r3, [r5, #24] 838: e78d b.n 756 <_sercom_i2c_sync_analyse_flags+0x7e> 83a: bf00 nop 83c: 000005bd .word 0x000005bd 840: 000006c5 .word 0x000006c5 00000844 <_i2c_m_sync_init_impl>: } return ERR_NONE; } static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw) { 844: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 848: 460c mov r4, r1 uint8_t i = _get_i2cm_index(hw); 84a: 4b22 ldr r3, [pc, #136] ; (8d4 <_i2c_m_sync_init_impl+0x90>) 84c: f8df 9090 ldr.w r9, [pc, #144] ; 8e0 <_i2c_m_sync_init_impl+0x9c> 850: 4d21 ldr r5, [pc, #132] ; (8d8 <_i2c_m_sync_init_impl+0x94>) { 852: 4607 mov r7, r0 uint8_t i = _get_i2cm_index(hw); 854: 4608 mov r0, r1 856: 4798 blx r3 return ((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg; 858: 69e3 ldr r3, [r4, #28] if (!hri_sercomi2cm_is_syncing(hw, SERCOM_I2CM_SYNCBUSY_SWRST)) { 85a: f013 0f01 tst.w r3, #1 85e: fa5f f880 uxtb.w r8, r0 862: d115 bne.n 890 <_i2c_m_sync_init_impl+0x4c> uint32_t mode = _i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_MODE_Msk; 864: 2318 movs r3, #24 866: fb03 9308 mla r3, r3, r8, r9 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); 86a: 2103 movs r1, #3 86c: 4620 mov r0, r4 86e: 6a5e ldr r6, [r3, #36] ; 0x24 870: 47a8 blx r5 tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; 872: 6823 ldr r3, [r4, #0] if (hri_sercomi2cm_get_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_ENABLE)) { 874: 079b lsls r3, r3, #30 uint32_t mode = _i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_MODE_Msk; 876: f006 061c and.w r6, r6, #28 if (hri_sercomi2cm_get_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_ENABLE)) { 87a: d503 bpl.n 884 <_i2c_m_sync_init_impl+0x40> hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); 87c: 4b17 ldr r3, [pc, #92] ; (8dc <_i2c_m_sync_init_impl+0x98>) 87e: 4798 blx r3 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_ENABLE); 880: 2102 movs r1, #2 882: 47a8 blx r5 } hri_sercomi2cm_write_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_SWRST | mode); 884: f046 0601 orr.w r6, r6, #1 ((Sercom *)hw)->I2CM.CTRLA.reg = data; 888: 6026 str r6, [r4, #0] hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); 88a: 2103 movs r1, #3 88c: 4620 mov r0, r4 88e: 47a8 blx r5 } hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); 890: 4620 mov r0, r4 892: 2101 movs r1, #1 894: 47a8 blx r5 hri_sercomi2cm_write_CTRLA_reg(hw, _i2cms[i].ctrl_a); 896: 2218 movs r2, #24 898: fb02 9208 mla r2, r2, r8, r9 89c: 2103 movs r1, #3 89e: 6a56 ldr r6, [r2, #36] ; 0x24 ((Sercom *)hw)->I2CM.CTRLA.reg = data; 8a0: 6026 str r6, [r4, #0] hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); 8a2: 47a8 blx r5 hri_sercomi2cm_write_CTRLB_reg(hw, _i2cms[i].ctrl_b); 8a4: 6a93 ldr r3, [r2, #40] ; 0x28 ((Sercom *)hw)->I2CM.CTRLB.reg = data; 8a6: 6063 str r3, [r4, #4] hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); 8a8: 2104 movs r1, #4 8aa: 47a8 blx r5 hri_sercomi2cm_write_BAUD_reg(hw, _i2cms[i].baud); 8ac: 6ad3 ldr r3, [r2, #44] ; 0x2c ((Sercom *)hw)->I2CM.BAUD.reg = data; 8ae: 60e3 str r3, [r4, #12] service->mode = (_i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos; 8b0: f3c6 6301 ubfx r3, r6, #24, #2 8b4: 81bb strh r3, [r7, #12] tmp = ((Sercom *)hw)->I2CM.ADDR.reg; 8b6: 6a63 ldr r3, [r4, #36] ; 0x24 hri_sercomi2cm_write_ADDR_HS_bit(hw, service->mode < I2C_HS ? 0 : 1); 8b8: f3c6 6640 ubfx r6, r6, #25, #1 tmp &= ~SERCOM_I2CM_ADDR_HS; 8bc: f423 4380 bic.w r3, r3, #16384 ; 0x4000 tmp |= value << SERCOM_I2CM_ADDR_HS_Pos; 8c0: ea43 3386 orr.w r3, r3, r6, lsl #14 ((Sercom *)hw)->I2CM.ADDR.reg = tmp; 8c4: 6263 str r3, [r4, #36] ; 0x24 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); 8c6: 2104 movs r1, #4 8c8: 47a8 blx r5 service->trise = _i2cms[i].trise; 8ca: 8e53 ldrh r3, [r2, #50] ; 0x32 8cc: 81fb strh r3, [r7, #14] return ERR_NONE; } 8ce: 2000 movs r0, #0 8d0: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 8d4: 00000699 .word 0x00000699 8d8: 000005bd .word 0x000005bd 8dc: 000005cd .word 0x000005cd 8e0: 00001468 .word 0x00001468 000008e4 <_usart_init>: { 8e4: b538 push {r3, r4, r5, lr} uint8_t sercom_offset = _sercom_get_hardware_index(hw); 8e6: 4b1a ldr r3, [pc, #104] ; (950 <_usart_init+0x6c>) { 8e8: 4604 mov r4, r0 uint8_t sercom_offset = _sercom_get_hardware_index(hw); 8ea: 4798 blx r3 if (_usarts[i].number == sercom_offset) { 8ec: 2802 cmp r0, #2 8ee: d005 beq.n 8fc <_usart_init+0x18> ASSERT(false); 8f0: 4918 ldr r1, [pc, #96] ; (954 <_usart_init+0x70>) 8f2: 4b19 ldr r3, [pc, #100] ; (958 <_usart_init+0x74>) 8f4: f240 226b movw r2, #619 ; 0x26b 8f8: 2000 movs r0, #0 8fa: 4798 blx r3 return ((Sercom *)hw)->USART.SYNCBUSY.reg & reg; 8fc: 69e3 ldr r3, [r4, #28] 8fe: 4d17 ldr r5, [pc, #92] ; (95c <_usart_init+0x78>) if (!hri_sercomusart_is_syncing(hw, SERCOM_USART_SYNCBUSY_SWRST)) { 900: f013 0f01 tst.w r3, #1 904: d10e bne.n 924 <_usart_init+0x40> hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); 906: 2103 movs r1, #3 908: 4620 mov r0, r4 90a: 47a8 blx r5 tmp = ((Sercom *)hw)->USART.CTRLA.reg; 90c: 6823 ldr r3, [r4, #0] if (hri_sercomusart_get_CTRLA_reg(hw, SERCOM_USART_CTRLA_ENABLE)) { 90e: 079b lsls r3, r3, #30 910: d503 bpl.n 91a <_usart_init+0x36> hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); 912: 4b13 ldr r3, [pc, #76] ; (960 <_usart_init+0x7c>) 914: 4798 blx r3 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); 916: 2102 movs r1, #2 918: 47a8 blx r5 ((Sercom *)hw)->USART.CTRLA.reg = data; 91a: 2305 movs r3, #5 91c: 6023 str r3, [r4, #0] hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); 91e: 2103 movs r1, #3 920: 4620 mov r0, r4 922: 47a8 blx r5 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); 924: 4620 mov r0, r4 926: 2101 movs r1, #1 928: 47a8 blx r5 ((Sercom *)hw)->USART.CTRLA.reg = data; 92a: 4b0e ldr r3, [pc, #56] ; (964 <_usart_init+0x80>) 92c: 6023 str r3, [r4, #0] hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); 92e: 2103 movs r1, #3 930: 47a8 blx r5 ((Sercom *)hw)->USART.CTRLB.reg = data; 932: f44f 3340 mov.w r3, #196608 ; 0x30000 936: 6063 str r3, [r4, #4] hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); 938: 211f movs r1, #31 93a: 47a8 blx r5 ((Sercom *)hw)->USART.CTRLC.reg = data; 93c: 4b0a ldr r3, [pc, #40] ; (968 <_usart_init+0x84>) 93e: 60a3 str r3, [r4, #8] ((Sercom *)hw)->USART.RXPL.reg = data; 940: 2000 movs r0, #0 ((Sercom *)hw)->USART.BAUD.reg = data; 942: f64f 4311 movw r3, #64529 ; 0xfc11 946: 81a3 strh r3, [r4, #12] ((Sercom *)hw)->USART.RXPL.reg = data; 948: 73a0 strb r0, [r4, #14] ((Sercom *)hw)->USART.DBGCTRL.reg = data; 94a: f884 0030 strb.w r0, [r4, #48] ; 0x30 } 94e: bd38 pop {r3, r4, r5, pc} 950: 000005f5 .word 0x000005f5 954: 0000144d .word 0x0000144d 958: 0000056d .word 0x0000056d 95c: 000005c5 .word 0x000005c5 960: 000005e1 .word 0x000005e1 964: 40100004 .word 0x40100004 968: 00700002 .word 0x00700002 0000096c <_usart_async_init>: { 96c: e92d 41f3 stmdb sp!, {r0, r1, r4, r5, r6, r7, r8, lr} ASSERT(device); 970: 4605 mov r5, r0 972: 3800 subs r0, #0 974: bf18 it ne 976: 2001 movne r0, #1 978: 4b14 ldr r3, [pc, #80] ; (9cc <_usart_async_init+0x60>) { 97a: 460c mov r4, r1 ASSERT(device); 97c: 22cb movs r2, #203 ; 0xcb 97e: 4914 ldr r1, [pc, #80] ; (9d0 <_usart_async_init+0x64>) 980: 4798 blx r3 init_status = _usart_init(hw); 982: 4b14 ldr r3, [pc, #80] ; (9d4 <_usart_async_init+0x68>) 984: 4620 mov r0, r4 986: 4798 blx r3 if (init_status) { 988: 4606 mov r6, r0 98a: b9d0 cbnz r0, 9c2 <_usart_async_init+0x56> if (hw == SERCOM2) { 98c: 4b12 ldr r3, [pc, #72] ; (9d8 <_usart_async_init+0x6c>) device->hw = hw; 98e: 61ac str r4, [r5, #24] if (hw == SERCOM2) { 990: 429c cmp r4, r3 _sercom2_dev = (struct _usart_async_device *)dev; 992: bf08 it eq 994: 4b11 ldreq r3, [pc, #68] ; (9dc <_usart_async_init+0x70>) NVIC_DisableIRQ((IRQn_Type)irq); 996: f8df 8054 ldr.w r8, [pc, #84] ; 9ec <_usart_async_init+0x80> _sercom2_dev = (struct _usart_async_device *)dev; 99a: bf08 it eq 99c: 601d streq r5, [r3, #0] uint8_t irq = _sercom_get_irq_num(hw); 99e: 4620 mov r0, r4 9a0: 4b0f ldr r3, [pc, #60] ; (9e0 <_usart_async_init+0x74>) NVIC_ClearPendingIRQ((IRQn_Type)irq); 9a2: 4f10 ldr r7, [pc, #64] ; (9e4 <_usart_async_init+0x78>) NVIC_EnableIRQ((IRQn_Type)irq); 9a4: 4d10 ldr r5, [pc, #64] ; (9e8 <_usart_async_init+0x7c>) uint8_t irq = _sercom_get_irq_num(hw); 9a6: 4798 blx r3 for (uint32_t i = 0; i < 4; i++) { 9a8: 2100 movs r1, #0 uint8_t irq = _sercom_get_irq_num(hw); 9aa: 4604 mov r4, r0 NVIC_DisableIRQ((IRQn_Type)irq); 9ac: 1863 adds r3, r4, r1 9ae: b2d8 uxtb r0, r3 9b0: 9001 str r0, [sp, #4] 9b2: 47c0 blx r8 NVIC_ClearPendingIRQ((IRQn_Type)irq); 9b4: 9801 ldr r0, [sp, #4] 9b6: 47b8 blx r7 NVIC_EnableIRQ((IRQn_Type)irq); 9b8: 9801 ldr r0, [sp, #4] 9ba: 47a8 blx r5 for (uint32_t i = 0; i < 4; i++) { 9bc: 3101 adds r1, #1 9be: 2904 cmp r1, #4 9c0: d1f4 bne.n 9ac <_usart_async_init+0x40> } 9c2: 4630 mov r0, r6 9c4: b002 add sp, #8 9c6: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 9ca: bf00 nop 9cc: 0000056d .word 0x0000056d 9d0: 0000144d .word 0x0000144d 9d4: 000008e5 .word 0x000008e5 9d8: 41012000 .word 0x41012000 9dc: 2000001c .word 0x2000001c 9e0: 0000062d .word 0x0000062d 9e4: 0000067d .word 0x0000067d 9e8: 00000641 .word 0x00000641 9ec: 00000659 .word 0x00000659 000009f0 <_usart_async_write_byte>: hri_sercomusart_write_DATA_reg(device->hw, data); 9f0: 6983 ldr r3, [r0, #24] ((Sercom *)hw)->USART.DATA.reg = data; 9f2: 6299 str r1, [r3, #40] ; 0x28 } 9f4: 4770 bx lr 000009f6 <_usart_async_enable_byte_sent_irq>: hri_sercomusart_set_INTEN_DRE_bit(device->hw); 9f6: 6983 ldr r3, [r0, #24] ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; 9f8: 2201 movs r2, #1 9fa: 759a strb r2, [r3, #22] } 9fc: 4770 bx lr 000009fe <_usart_async_enable_tx_done_irq>: hri_sercomusart_set_INTEN_TXC_bit(device->hw); 9fe: 6983 ldr r3, [r0, #24] ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; a00: 2202 movs r2, #2 a02: 759a strb r2, [r3, #22] } a04: 4770 bx lr ... 00000a08 <_i2c_m_sync_init>: { a08: b570 push {r4, r5, r6, lr} ASSERT(i2c_dev); a0a: 4604 mov r4, r0 a0c: 3800 subs r0, #0 { a0e: 460d mov r5, r1 ASSERT(i2c_dev); a10: 4b06 ldr r3, [pc, #24] ; (a2c <_i2c_m_sync_init+0x24>) a12: 4907 ldr r1, [pc, #28] ; (a30 <_i2c_m_sync_init+0x28>) a14: bf18 it ne a16: 2001 movne r0, #1 a18: f44f 62a8 mov.w r2, #1344 ; 0x540 a1c: 4798 blx r3 i2c_dev->hw = hw; a1e: 6125 str r5, [r4, #16] return _i2c_m_sync_init_impl(&i2c_dev->service, hw); a20: 4629 mov r1, r5 a22: 4620 mov r0, r4 a24: 4b03 ldr r3, [pc, #12] ; (a34 <_i2c_m_sync_init+0x2c>) } a26: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} return _i2c_m_sync_init_impl(&i2c_dev->service, hw); a2a: 4718 bx r3 a2c: 0000056d .word 0x0000056d a30: 0000144d .word 0x0000144d a34: 00000845 .word 0x00000845 00000a38 <_i2c_m_sync_transfer>: { a38: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} a3c: 4604 mov r4, r0 ASSERT(i2c_dev); a3e: f8df 9160 ldr.w r9, [pc, #352] ; ba0 <_i2c_m_sync_transfer+0x168> void * hw = i2c_dev->hw; a42: 6907 ldr r7, [r0, #16] { a44: 460e mov r6, r1 ASSERT(i2c_dev); a46: f44f 62bf mov.w r2, #1528 ; 0x5f8 a4a: 4952 ldr r1, [pc, #328] ; (b94 <_i2c_m_sync_transfer+0x15c>) a4c: 2001 movs r0, #1 a4e: 47c8 blx r9 ASSERT(i2c_dev->hw); a50: 6920 ldr r0, [r4, #16] a52: 4950 ldr r1, [pc, #320] ; (b94 <_i2c_m_sync_transfer+0x15c>) a54: 3800 subs r0, #0 a56: f240 52f9 movw r2, #1529 ; 0x5f9 a5a: bf18 it ne a5c: 2001 movne r0, #1 a5e: 47c8 blx r9 ASSERT(msg); a60: 1e30 subs r0, r6, #0 a62: bf18 it ne a64: 2001 movne r0, #1 a66: 494b ldr r1, [pc, #300] ; (b94 <_i2c_m_sync_transfer+0x15c>) a68: f240 52fa movw r2, #1530 ; 0x5fa a6c: 47c8 blx r9 if (i2c_dev->service.msg.flags & I2C_M_BUSY) { a6e: 8863 ldrh r3, [r4, #2] a70: 05d8 lsls r0, r3, #23 a72: d47c bmi.n b6e <_i2c_m_sync_transfer+0x136> msg->flags |= I2C_M_BUSY; a74: 8873 ldrh r3, [r6, #2] hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); a76: f8df 812c ldr.w r8, [pc, #300] ; ba4 <_i2c_m_sync_transfer+0x16c> a7a: b29b uxth r3, r3 a7c: f443 7380 orr.w r3, r3, #256 ; 0x100 a80: 8073 strh r3, [r6, #2] i2c_dev->service.msg = *msg; a82: e896 0007 ldmia.w r6, {r0, r1, r2} ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_SMEN; a86: 687b ldr r3, [r7, #4] a88: f443 7380 orr.w r3, r3, #256 ; 0x100 a8c: e884 0007 stmia.w r4, {r0, r1, r2} a90: 607b str r3, [r7, #4] hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); a92: 2104 movs r1, #4 a94: 4638 mov r0, r7 a96: 47c0 blx r8 void * hw = i2c_dev->hw; a98: 6925 ldr r5, [r4, #16] ASSERT(i2c_dev); a9a: 493e ldr r1, [pc, #248] ; (b94 <_i2c_m_sync_transfer+0x15c>) tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; a9c: f8d5 a000 ldr.w sl, [r5] aa0: f240 52cd movw r2, #1485 ; 0x5cd aa4: 2001 movs r0, #1 aa6: 47c8 blx r9 if (msg->len == 1 && sclsm) { aa8: 6863 ldr r3, [r4, #4] aaa: 2b01 cmp r3, #1 ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; aac: 686b ldr r3, [r5, #4] aae: d13b bne.n b28 <_i2c_m_sync_transfer+0xf0> ab0: f01a 6f00 tst.w sl, #134217728 ; 0x8000000 ab4: d038 beq.n b28 <_i2c_m_sync_transfer+0xf0> ab6: f443 2380 orr.w r3, r3, #262144 ; 0x40000 ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; aba: 606b str r3, [r5, #4] hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); abc: 2104 movs r1, #4 abe: 4628 mov r0, r5 ac0: 47c0 blx r8 if (msg->addr & I2C_M_TEN) { ac2: 8823 ldrh r3, [r4, #0] ac4: 0559 lsls r1, r3, #21 ac6: ea4f 0243 mov.w r2, r3, lsl #1 aca: d530 bpl.n b2e <_i2c_m_sync_transfer+0xf6> if (msg->flags & I2C_M_RD) { acc: 8863 ldrh r3, [r4, #2] ace: 07db lsls r3, r3, #31 msg->flags |= I2C_M_TEN; ad0: bf41 itttt mi ad2: 8863 ldrhmi r3, [r4, #2] ad4: b29b uxthmi r3, r3 ad6: f443 6380 orrmi.w r3, r3, #1024 ; 0x400 ada: 8063 strhmi r3, [r4, #2] hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); adc: 2104 movs r1, #4 ade: 47c0 blx r8 return ((Sercom *)hw)->I2CM.ADDR.reg; ae0: 6a6b ldr r3, [r5, #36] ; 0x24 | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); ae2: f022 0201 bic.w r2, r2, #1 ae6: 0552 lsls r2, r2, #21 ae8: 0d52 lsrs r2, r2, #21 aea: f403 4380 and.w r3, r3, #16384 ; 0x4000 aee: 431a orrs r2, r3 hri_sercomi2cm_write_ADDR_reg(hw, af0: f442 4200 orr.w r2, r2, #32768 ; 0x8000 ((Sercom *)hw)->I2CM.ADDR.reg = data; af4: 626a str r2, [r5, #36] ; 0x24 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); af6: 2104 movs r1, #4 af8: 4628 mov r0, r5 afa: 47c0 blx r8 void * hw = i2c_dev->hw; afc: 6922 ldr r2, [r4, #16] afe: f44f 3380 mov.w r3, #65536 ; 0x10000 return ((Sercom *)hw)->I2CM.INTFLAG.reg; b02: 7e11 ldrb r1, [r2, #24] if (timeout-- == 0) { b04: 3b01 subs r3, #1 b06: b2c9 uxtb r1, r1 b08: d001 beq.n b0e <_i2c_m_sync_transfer+0xd6> } while (!(*flags & MB_FLAG) && !(*flags & SB_FLAG)); b0a: 0788 lsls r0, r1, #30 b0c: d0f9 beq.n b02 <_i2c_m_sync_transfer+0xca> return _sercom_i2c_sync_analyse_flags(hw, flags, msg); b0e: 4628 mov r0, r5 b10: 4622 mov r2, r4 b12: 4d21 ldr r5, [pc, #132] ; (b98 <_i2c_m_sync_transfer+0x160>) b14: 47a8 blx r5 if (ret) { b16: b1d0 cbz r0, b4e <_i2c_m_sync_transfer+0x116> i2c_dev->service.msg.flags &= ~I2C_M_BUSY; b18: 8863 ldrh r3, [r4, #2] b1a: f423 7380 bic.w r3, r3, #256 ; 0x100 b1e: 041b lsls r3, r3, #16 b20: 0c1b lsrs r3, r3, #16 b22: 8063 strh r3, [r4, #2] } b24: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; b28: f423 2380 bic.w r3, r3, #262144 ; 0x40000 b2c: e7c5 b.n aba <_i2c_m_sync_transfer+0x82> hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); b2e: 2104 movs r1, #4 ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0) b30: f8b4 9002 ldrh.w r9, [r4, #2] b34: 47c0 blx r8 b36: fa1f f989 uxth.w r9, r9 return ((Sercom *)hw)->I2CM.ADDR.reg; b3a: 6a6b ldr r3, [r5, #36] ; 0x24 b3c: b2d2 uxtb r2, r2 b3e: f009 0901 and.w r9, r9, #1 b42: ea42 0209 orr.w r2, r2, r9 | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); b46: f403 4380 and.w r3, r3, #16384 ; 0x4000 hri_sercomi2cm_write_ADDR_reg(hw, b4a: 431a orrs r2, r3 b4c: e7d2 b.n af4 <_i2c_m_sync_transfer+0xbc> while (i2c_dev->service.msg.flags & I2C_M_BUSY) { b4e: 8863 ldrh r3, [r4, #2] b50: 05da lsls r2, r3, #23 b52: d5e7 bpl.n b24 <_i2c_m_sync_transfer+0xec> void * hw = i2c_dev->hw; b54: 6922 ldr r2, [r4, #16] b56: f44f 3380 mov.w r3, #65536 ; 0x10000 return ((Sercom *)hw)->I2CM.INTFLAG.reg; b5a: 7e11 ldrb r1, [r2, #24] if (timeout-- == 0) { b5c: 3b01 subs r3, #1 b5e: b2c9 uxtb r1, r1 b60: d008 beq.n b74 <_i2c_m_sync_transfer+0x13c> } while (!(*flags & MB_FLAG) && !(*flags & SB_FLAG)); b62: 0788 lsls r0, r1, #30 b64: d0f9 beq.n b5a <_i2c_m_sync_transfer+0x122> ret = _sercom_i2c_sync_analyse_flags(hw, flags, &i2c_dev->service.msg); b66: 4622 mov r2, r4 b68: 4638 mov r0, r7 b6a: 47a8 blx r5 b6c: e7ef b.n b4e <_i2c_m_sync_transfer+0x116> return I2C_ERR_BUSY; b6e: f06f 0005 mvn.w r0, #5 b72: e7d7 b.n b24 <_i2c_m_sync_transfer+0xec> if (msg->flags & I2C_M_STOP) { b74: 8873 ldrh r3, [r6, #2] b76: 041b lsls r3, r3, #16 b78: d502 bpl.n b80 <_i2c_m_sync_transfer+0x148> _sercom_i2c_send_stop(hw); b7a: 4b08 ldr r3, [pc, #32] ; (b9c <_i2c_m_sync_transfer+0x164>) b7c: 4638 mov r0, r7 b7e: 4798 blx r3 i2c_dev->service.msg.flags &= ~I2C_M_BUSY; b80: 8863 ldrh r3, [r4, #2] b82: f423 7380 bic.w r3, r3, #256 ; 0x100 b86: 041b lsls r3, r3, #16 b88: 0c1b lsrs r3, r3, #16 b8a: 8063 strh r3, [r4, #2] return ret; b8c: f06f 0004 mvn.w r0, #4 b90: e7c8 b.n b24 <_i2c_m_sync_transfer+0xec> b92: bf00 nop b94: 0000144d .word 0x0000144d b98: 000006d9 .word 0x000006d9 b9c: 000006c5 .word 0x000006c5 ba0: 0000056d .word 0x0000056d ba4: 000005bd .word 0x000005bd 00000ba8 : /** * \internal Sercom interrupt handler */ void SERCOM2_0_Handler(void) { _sercom_usart_interrupt_handler(_sercom2_dev); ba8: 4b19 ldr r3, [pc, #100] ; (c10 ) baa: 6818 ldr r0, [r3, #0] { bac: b510 push {r4, lr} void *hw = device->hw; bae: 6984 ldr r4, [r0, #24] return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; bb0: 7e23 ldrb r3, [r4, #24] if (hri_sercomusart_get_interrupt_DRE_bit(hw) && hri_sercomusart_get_INTEN_DRE_bit(hw)) { bb2: 07da lsls r2, r3, #31 bb4: d508 bpl.n bc8 return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_DRE) >> SERCOM_USART_INTENSET_DRE_Pos; bb6: 7da3 ldrb r3, [r4, #22] bb8: 07db lsls r3, r3, #31 bba: d505 bpl.n bc8 ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; bbc: 2301 movs r3, #1 bbe: 7523 strb r3, [r4, #20] device->usart_cb.tx_byte_sent(device); bc0: 6803 ldr r3, [r0, #0] } bc2: e8bd 4010 ldmia.w sp!, {r4, lr} device->usart_cb.tx_done_cb(device); bc6: 4718 bx r3 return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; bc8: 7e23 ldrb r3, [r4, #24] } else if (hri_sercomusart_get_interrupt_TXC_bit(hw) && hri_sercomusart_get_INTEN_TXC_bit(hw)) { bca: 0799 lsls r1, r3, #30 bcc: d506 bpl.n bdc return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_TXC) >> SERCOM_USART_INTENSET_TXC_Pos; bce: 7da3 ldrb r3, [r4, #22] bd0: 079a lsls r2, r3, #30 bd2: d503 bpl.n bdc ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; bd4: 2302 movs r3, #2 bd6: 7523 strb r3, [r4, #20] device->usart_cb.tx_done_cb(device); bd8: 6883 ldr r3, [r0, #8] bda: e7f2 b.n bc2 return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; bdc: 7e23 ldrb r3, [r4, #24] } else if (hri_sercomusart_get_interrupt_RXC_bit(hw)) { bde: 075b lsls r3, r3, #29 be0: d50c bpl.n bfc return ((Sercom *)hw)->USART.STATUS.reg; be2: 8b63 ldrh r3, [r4, #26] if (hri_sercomusart_read_STATUS_reg(hw) be4: f003 0337 and.w r3, r3, #55 ; 0x37 be8: b113 cbz r3, bf0 ((Sercom *)hw)->USART.STATUS.reg = mask; bea: 23ff movs r3, #255 ; 0xff bec: 8363 strh r3, [r4, #26] } bee: bd10 pop {r4, pc} return ((Sercom *)hw)->USART.DATA.reg; bf0: 6aa1 ldr r1, [r4, #40] ; 0x28 device->usart_cb.rx_done_cb(device, hri_sercomusart_read_DATA_reg(hw)); bf2: 6843 ldr r3, [r0, #4] } bf4: e8bd 4010 ldmia.w sp!, {r4, lr} device->usart_cb.rx_done_cb(device, hri_sercomusart_read_DATA_reg(hw)); bf8: b2c9 uxtb r1, r1 bfa: 4718 bx r3 return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; bfc: 7e23 ldrb r3, [r4, #24] } else if (hri_sercomusart_get_interrupt_ERROR_bit(hw)) { bfe: 09db lsrs r3, r3, #7 c00: d0f5 beq.n bee ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; c02: 2380 movs r3, #128 ; 0x80 c04: 7623 strb r3, [r4, #24] device->usart_cb.error_cb(device); c06: 68c3 ldr r3, [r0, #12] c08: 4798 blx r3 return ((Sercom *)hw)->USART.STATUS.reg; c0a: 8b63 ldrh r3, [r4, #26] c0c: b29b uxth r3, r3 c0e: e7ed b.n bec c10: 2000001c .word 0x2000001c 00000c14 : c14: 4b00 ldr r3, [pc, #0] ; (c18 ) c16: 4718 bx r3 c18: 00000ba9 .word 0x00000ba9 00000c1c : c1c: 4b00 ldr r3, [pc, #0] ; (c20 ) c1e: 4718 bx r3 c20: 00000ba9 .word 0x00000ba9 00000c24 : c24: 4b00 ldr r3, [pc, #0] ; (c28 ) c26: 4718 bx r3 c28: 00000ba9 .word 0x00000ba9 00000c2c <_gclk_init_generators_by_fref>: void _gclk_init_generators_by_fref(uint32_t bm) { #if CONF_GCLK_GENERATOR_0_CONFIG == 1 if (bm & (1ul << 0)) { c2c: 07c3 lsls r3, r0, #31 c2e: d507 bpl.n c40 <_gclk_init_generators_by_fref+0x14> } static inline void hri_gclk_write_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) { GCLK_CRITICAL_SECTION_ENTER(); ((Gclk *)hw)->GENCTRL[index].reg = data; c30: 4b04 ldr r3, [pc, #16] ; (c44 <_gclk_init_generators_by_fref+0x18>) c32: 4a05 ldr r2, [pc, #20] ; (c48 <_gclk_init_generators_by_fref+0x1c>) c34: 621a str r2, [r3, #32] while (((Gclk *)hw)->SYNCBUSY.reg & reg) { c36: f643 72fd movw r2, #16381 ; 0x3ffd c3a: 6859 ldr r1, [r3, #4] c3c: 4211 tst r1, r2 c3e: d1fc bne.n c3a <_gclk_init_generators_by_fref+0xe> | (CONF_GCLK_GEN_11_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_11_OE << GCLK_GENCTRL_OE_Pos) | (CONF_GCLK_GEN_11_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_11_IDC << GCLK_GENCTRL_IDC_Pos) | (CONF_GCLK_GENERATOR_11_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_11_SOURCE); } #endif } c40: 4770 bx lr c42: bf00 nop c44: 40001c00 .word 0x40001c00 c48: 00010107 .word 0x00010107 00000c4c : /** * \brief Default interrupt handler for unused IRQs. */ void Dummy_Handler(void) { while (1) { c4c: e7fe b.n c4c ... 00000c50 : { c50: b508 push {r3, lr} if (pSrc != pDest) { c52: 4a14 ldr r2, [pc, #80] ; (ca4 ) c54: 4b14 ldr r3, [pc, #80] ; (ca8 ) c56: 429a cmp r2, r3 c58: d002 beq.n c60 for (; pDest < &_erelocate;) { c5a: 4914 ldr r1, [pc, #80] ; (cac ) c5c: 428b cmp r3, r1 c5e: d318 bcc.n c92 pSrc = &_etext; c60: 4b13 ldr r3, [pc, #76] ; (cb0 ) for (pDest = &_szero; pDest < &_ezero;) { c62: 4a14 ldr r2, [pc, #80] ; (cb4 ) *pDest++ = 0; c64: 2100 movs r1, #0 for (pDest = &_szero; pDest < &_ezero;) { c66: 4293 cmp r3, r2 c68: d318 bcc.n c9c SCB->VTOR = ((uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk); c6a: 4a13 ldr r2, [pc, #76] ; (cb8 ) c6c: 4b13 ldr r3, [pc, #76] ; (cbc ) c6e: f022 027f bic.w r2, r2, #127 ; 0x7f c72: 609a str r2, [r3, #8] SCB->CPACR |= (0xFu << 20); c74: f8d3 2088 ldr.w r2, [r3, #136] ; 0x88 c78: f442 0270 orr.w r2, r2, #15728640 ; 0xf00000 c7c: f8c3 2088 str.w r2, [r3, #136] ; 0x88 __ASM volatile ("dsb 0xF":::"memory"); c80: f3bf 8f4f dsb sy __ASM volatile ("isb 0xF":::"memory"); c84: f3bf 8f6f isb sy __libc_init_array(); c88: 4b0d ldr r3, [pc, #52] ; (cc0 ) c8a: 4798 blx r3 main(); c8c: 4b0d ldr r3, [pc, #52] ; (cc4 ) c8e: 4798 blx r3 while (1) c90: e7fe b.n c90 *pDest++ = *pSrc++; c92: f852 0b04 ldr.w r0, [r2], #4 c96: f843 0b04 str.w r0, [r3], #4 c9a: e7df b.n c5c *pDest++ = 0; c9c: f843 1b04 str.w r1, [r3], #4 ca0: e7e1 b.n c66 ca2: bf00 nop ca4: 0000155c .word 0x0000155c ca8: 20000000 .word 0x20000000 cac: 20000000 .word 0x20000000 cb0: 20000000 .word 0x20000000 cb4: 200000d8 .word 0x200000d8 cb8: 00000000 .word 0x00000000 cbc: e000ed00 .word 0xe000ed00 cc0: 000013b5 .word 0x000013b5 cc4: 00000cc9 .word 0x00000cc9 00000cc8
: #include int main(void) { cc8: b508 push {r3, lr} /* Initializes MCU, drivers and middleware */ atmel_start_init(); cca: 4b01 ldr r3, [pc, #4] ; (cd0 ) ccc: 4798 blx r3 /* Replace with your application code */ while (1) { cce: e7fe b.n cce cd0: 000011d1 .word 0x000011d1 00000cd4 <_osc32kctrl_init_sources>: } static inline void hri_osc32kctrl_write_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) { OSC32KCTRL_CRITICAL_SECTION_ENTER(); ((Osc32kctrl *)hw)->XOSC32K.reg = data; cd4: 4b06 ldr r3, [pc, #24] ; (cf0 <_osc32kctrl_init_sources+0x1c>) cd6: f242 328e movw r2, #9102 ; 0x238e cda: 829a strh r2, [r3, #20] } static inline void hri_osc32kctrl_write_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t data) { OSC32KCTRL_CRITICAL_SECTION_ENTER(); ((Osc32kctrl *)hw)->CFDCTRL.reg = data; cdc: 2200 movs r2, #0 cde: 759a strb r2, [r3, #22] } static inline void hri_osc32kctrl_write_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t data) { OSC32KCTRL_CRITICAL_SECTION_ENTER(); ((Osc32kctrl *)hw)->EVCTRL.reg = data; ce0: 75da strb r2, [r3, #23] } static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_CALIB_bf(const void *const hw) { uint32_t tmp; tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; ce2: 69da ldr r2, [r3, #28] calib = hri_osc32kctrl_read_OSCULP32K_CALIB_bf(hw); hri_osc32kctrl_write_OSCULP32K_reg(hw, #if CONF_OSCULP32K_CALIB_ENABLE == 1 OSC32KCTRL_OSCULP32K_CALIB(CONF_OSCULP32K_CALIB) #else OSC32KCTRL_OSCULP32K_CALIB(calib) ce4: f402 527c and.w r2, r2, #16128 ; 0x3f00 } static inline void hri_osc32kctrl_write_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data) { OSC32KCTRL_CRITICAL_SECTION_ENTER(); ((Osc32kctrl *)hw)->OSCULP32K.reg = data; ce8: 61da str r2, [r3, #28] ((Osc32kctrl *)hw)->RTCCTRL.reg = data; cea: 2201 movs r2, #1 cec: 741a strb r2, [r3, #16] #endif #endif hri_osc32kctrl_write_RTCCTRL_reg(hw, OSC32KCTRL_RTCCTRL_RTCSEL(CONF_RTCCTRL)); (void)calib; } cee: 4770 bx lr cf0: 40001400 .word 0x40001400 00000cf4 <_gpio_set_pin_function>: /** * \brief Set gpio pin function */ static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function) { uint8_t port = GPIO_PORT(gpio); cf4: 0943 lsrs r3, r0, #5 static inline void hri_port_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, bool value) { uint8_t tmp; PORT_CRITICAL_SECTION_ENTER(); tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; cf6: 01db lsls r3, r3, #7 cf8: f103 4382 add.w r3, r3, #1090519040 ; 0x41000000 { cfc: b530 push {r4, r5, lr} cfe: f503 4300 add.w r3, r3, #32768 ; 0x8000 uint8_t pin = GPIO_PIN(gpio); d02: f000 041f and.w r4, r0, #31 d06: 191d adds r5, r3, r4 d08: eb03 0354 add.w r3, r3, r4, lsr #1 d0c: f895 2040 ldrb.w r2, [r5, #64] ; 0x40 tmp &= ~PORT_PINCFG_PMUXEN; d10: f002 02fe and.w r2, r2, #254 ; 0xfe tmp |= value << PORT_PINCFG_PMUXEN_Pos; d14: f042 0201 orr.w r2, r2, #1 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; d18: f885 2040 strb.w r2, [r5, #64] ; 0x40 hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, false); } else { hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, true); if (pin & 1) { d1c: b2ca uxtb r2, r1 tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; d1e: f893 1030 ldrb.w r1, [r3, #48] ; 0x30 d22: f010 0f01 tst.w r0, #1 tmp &= ~PORT_PMUX_PMUXO_Msk; d26: bf1b ittet ne d28: f001 010f andne.w r1, r1, #15 tmp |= PORT_PMUX_PMUXO(data); d2c: ea41 1102 orrne.w r1, r1, r2, lsl #4 tmp &= ~PORT_PMUX_PMUXE_Msk; d30: f001 01f0 andeq.w r1, r1, #240 ; 0xf0 tmp |= PORT_PMUX_PMUXO(data); d34: b2c9 uxtbne r1, r1 tmp |= PORT_PMUX_PMUXE(data); d36: bf08 it eq d38: 4311 orreq r1, r2 ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; d3a: f883 1030 strb.w r1, [r3, #48] ; 0x30 } else { // Even numbered pin hri_port_write_PMUX_PMUXE_bf(PORT, port, pin >> 1, function & 0xffff); } } } d3e: bd30 pop {r4, r5, pc} 00000d40 : } static inline void hri_gclk_write_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data) { GCLK_CRITICAL_SECTION_ENTER(); ((Gclk *)hw)->PCHCTRL[index].reg = data; d40: 4b05 ldr r3, [pc, #20] ; (d58 ) d42: 2240 movs r2, #64 ; 0x40 d44: f8c3 2090 str.w r2, [r3, #144] ; 0x90 } static inline void hri_mclk_set_APBAMASK_EIC_bit(const void *const hw) { MCLK_CRITICAL_SECTION_ENTER(); ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_EIC; d48: 4a04 ldr r2, [pc, #16] ; (d5c ) d4a: 6953 ldr r3, [r2, #20] d4c: f443 6380 orr.w r3, r3, #1024 ; 0x400 d50: 6153 str r3, [r2, #20] void EXTERNAL_IRQ_0_init(void) { hri_gclk_write_PCHCTRL_reg(GCLK, EIC_GCLK_ID, CONF_GCLK_EIC_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); hri_mclk_set_APBAMASK_EIC_bit(MCLK); ext_irq_init(); d52: 4b03 ldr r3, [pc, #12] ; (d60 ) d54: 4718 bx r3 d56: bf00 nop d58: 40001c00 .word 0x40001c00 d5c: 40000800 .word 0x40000800 d60: 000010cd .word 0x000010cd 00000d64 : d64: 4b06 ldr r3, [pc, #24] ; (d80 ) d66: 2240 movs r2, #64 ; 0x40 d68: f8c3 20dc str.w r2, [r3, #220] ; 0xdc d6c: 2243 movs r2, #67 ; 0x43 d6e: f8c3 208c str.w r2, [r3, #140] ; 0x8c } static inline void hri_mclk_set_APBBMASK_SERCOM2_bit(const void *const hw) { MCLK_CRITICAL_SECTION_ENTER(); ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_SERCOM2; d72: 4a04 ldr r2, [pc, #16] ; (d84 ) d74: 6993 ldr r3, [r2, #24] d76: f443 7300 orr.w r3, r3, #512 ; 0x200 d7a: 6193 str r3, [r2, #24] hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK); } d7c: 4770 bx lr d7e: bf00 nop d80: 40001c00 .word 0x40001c00 d84: 40000800 .word 0x40000800 00000d88 : * \brief USART pinmux initialization function * * Set each required pin to USART functionality */ void USART_0_PORT_init() { d88: b510 push {r4, lr} * found in the header files for the device * */ static inline void gpio_set_pin_function(const uint32_t pin, uint32_t function) { _gpio_set_pin_function(pin, function); d8a: 4c05 ldr r4, [pc, #20] ; (da0 ) d8c: 4905 ldr r1, [pc, #20] ; (da4 ) d8e: 2039 movs r0, #57 ; 0x39 d90: 47a0 blx r4 d92: 4623 mov r3, r4 d94: 4904 ldr r1, [pc, #16] ; (da8 ) gpio_set_pin_function(PB25, PINMUX_PB25D_SERCOM2_PAD0); gpio_set_pin_function(PB24, PINMUX_PB24D_SERCOM2_PAD1); } d96: e8bd 4010 ldmia.w sp!, {r4, lr} d9a: 2038 movs r0, #56 ; 0x38 d9c: 4718 bx r3 d9e: bf00 nop da0: 00000cf5 .word 0x00000cf5 da4: 00390003 .word 0x00390003 da8: 00380003 .word 0x00380003 00000dac : * \brief USART initialization function * * Enables USART peripheral, clocks and initializes USART driver */ void USART_0_init(void) { dac: b513 push {r0, r1, r4, lr} USART_0_CLOCK_init(); dae: 4b07 ldr r3, [pc, #28] ; (dcc ) usart_async_init(&USART_0, SERCOM2, USART_0_buffer, USART_0_BUFFER_SIZE, (void *)NULL); db0: 4c07 ldr r4, [pc, #28] ; (dd0 ) USART_0_CLOCK_init(); db2: 4798 blx r3 usart_async_init(&USART_0, SERCOM2, USART_0_buffer, USART_0_BUFFER_SIZE, (void *)NULL); db4: 2300 movs r3, #0 db6: 9300 str r3, [sp, #0] db8: 4a06 ldr r2, [pc, #24] ; (dd4 ) dba: 4907 ldr r1, [pc, #28] ; (dd8 ) dbc: 4807 ldr r0, [pc, #28] ; (ddc ) dbe: 2310 movs r3, #16 dc0: 47a0 blx r4 USART_0_PORT_init(); dc2: 4b07 ldr r3, [pc, #28] ; (de0 ) } dc4: b002 add sp, #8 dc6: e8bd 4010 ldmia.w sp!, {r4, lr} USART_0_PORT_init(); dca: 4718 bx r3 dcc: 00000d65 .word 0x00000d65 dd0: 00001011 .word 0x00001011 dd4: 20000020 .word 0x20000020 dd8: 41012000 .word 0x41012000 ddc: 2000004c .word 0x2000004c de0: 00000d89 .word 0x00000d89 00000de4 : void I2C_0_PORT_init(void) { de4: b570 push {r4, r5, r6, lr} } static inline void hri_port_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) { PORT_CRITICAL_SECTION_ENTER(); ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; de6: 4c0b ldr r4, [pc, #44] ; (e14 ) de8: 4d0b ldr r5, [pc, #44] ; (e18 ) dea: f894 3056 ldrb.w r3, [r4, #86] ; 0x56 dee: 490b ldr r1, [pc, #44] ; (e1c ) df0: f003 03fb and.w r3, r3, #251 ; 0xfb df4: f884 3056 strb.w r3, [r4, #86] ; 0x56 df8: 2016 movs r0, #22 dfa: 47a8 blx r5 dfc: f894 3057 ldrb.w r3, [r4, #87] ; 0x57 e00: 4907 ldr r1, [pc, #28] ; (e20 ) e02: f003 03fb and.w r3, r3, #251 ; 0xfb e06: f884 3057 strb.w r3, [r4, #87] ; 0x57 e0a: 2017 movs r0, #23 e0c: 462b mov r3, r5 // Pull-up // Pull-down GPIO_PULL_OFF); gpio_set_pin_function(PA23, PINMUX_PA23C_SERCOM3_PAD1); } e0e: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} e12: 4718 bx r3 e14: 41008000 .word 0x41008000 e18: 00000cf5 .word 0x00000cf5 e1c: 00160002 .word 0x00160002 e20: 00170002 .word 0x00170002 00000e24 : e24: 4b06 ldr r3, [pc, #24] ; (e40 ) e26: 2240 movs r2, #64 ; 0x40 e28: f8c3 20e0 str.w r2, [r3, #224] ; 0xe0 e2c: 2243 movs r2, #67 ; 0x43 e2e: f8c3 208c str.w r2, [r3, #140] ; 0x8c } static inline void hri_mclk_set_APBBMASK_SERCOM3_bit(const void *const hw) { MCLK_CRITICAL_SECTION_ENTER(); ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_SERCOM3; e32: 4a04 ldr r2, [pc, #16] ; (e44 ) e34: 6993 ldr r3, [r2, #24] e36: f443 6380 orr.w r3, r3, #1024 ; 0x400 e3a: 6193 str r3, [r2, #24] { hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM3_GCLK_ID_CORE, CONF_GCLK_SERCOM3_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM3_GCLK_ID_SLOW, CONF_GCLK_SERCOM3_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); hri_mclk_set_APBBMASK_SERCOM3_bit(MCLK); } e3c: 4770 bx lr e3e: bf00 nop e40: 40001c00 .word 0x40001c00 e44: 40000800 .word 0x40000800 00000e48 : void I2C_0_init(void) { e48: b510 push {r4, lr} I2C_0_CLOCK_init(); e4a: 4b05 ldr r3, [pc, #20] ; (e60 ) e4c: 4798 blx r3 i2c_m_sync_init(&I2C_0, SERCOM3); e4e: 4b05 ldr r3, [pc, #20] ; (e64 ) e50: 4905 ldr r1, [pc, #20] ; (e68 ) e52: 4806 ldr r0, [pc, #24] ; (e6c ) e54: 4798 blx r3 I2C_0_PORT_init(); } e56: e8bd 4010 ldmia.w sp!, {r4, lr} I2C_0_PORT_init(); e5a: 4b05 ldr r3, [pc, #20] ; (e70 ) e5c: 4718 bx r3 e5e: bf00 nop e60: 00000e25 .word 0x00000e25 e64: 00000465 .word 0x00000465 e68: 41014000 .word 0x41014000 e6c: 2000009c .word 0x2000009c e70: 00000de5 .word 0x00000de5 00000e74 : timer_init(&TIMER_0, TC0, _tc_get_timer()); } void system_init(void) { e74: b510 push {r4, lr} * Currently the following initialization functions are supported: * - System clock initialization */ static inline void init_mcu(void) { _init_chip(); e76: 4b0d ldr r3, [pc, #52] ; (eac ) e78: 4798 blx r3 init_mcu(); EXTERNAL_IRQ_0_init(); e7a: 4b0d ldr r3, [pc, #52] ; (eb0 ) e7c: 4798 blx r3 USART_0_init(); e7e: 4b0d ldr r3, [pc, #52] ; (eb4 ) e80: 4798 blx r3 I2C_0_init(); e82: 4b0d ldr r3, [pc, #52] ; (eb8 ) e84: 4798 blx r3 ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_TC0; e86: 4a0d ldr r2, [pc, #52] ; (ebc ) e88: 6953 ldr r3, [r2, #20] e8a: f443 4380 orr.w r3, r3, #16384 ; 0x4000 e8e: 6153 str r3, [r2, #20] e90: 4b0b ldr r3, [pc, #44] ; (ec0 ) e92: 2240 movs r2, #64 ; 0x40 e94: f8c3 20a4 str.w r2, [r3, #164] ; 0xa4 timer_init(&TIMER_0, TC0, _tc_get_timer()); e98: 4b0a ldr r3, [pc, #40] ; (ec4 ) e9a: 4798 blx r3 TIMER_0_init(); } e9c: e8bd 4010 ldmia.w sp!, {r4, lr} timer_init(&TIMER_0, TC0, _tc_get_timer()); ea0: 4602 mov r2, r0 ea2: 4909 ldr r1, [pc, #36] ; (ec8 ) ea4: 4809 ldr r0, [pc, #36] ; (ecc ) ea6: 4b0a ldr r3, [pc, #40] ; (ed0 ) ea8: 4718 bx r3 eaa: bf00 nop eac: 000004a1 .word 0x000004a1 eb0: 00000d41 .word 0x00000d41 eb4: 00000dad .word 0x00000dad eb8: 00000e49 .word 0x00000e49 ebc: 40000800 .word 0x40000800 ec0: 40001c00 .word 0x40001c00 ec4: 00001379 .word 0x00001379 ec8: 40003800 .word 0x40003800 ecc: 200000bc .word 0x200000bc ed0: 000003d5 .word 0x000003d5 00000ed4 : */ static void usart_transmission_complete(struct _usart_async_device *device) { struct usart_async_descriptor *descr = CONTAINER_OF(device, struct usart_async_descriptor, device); descr->stat = 0; ed4: 2300 movs r3, #0 ed6: 6283 str r3, [r0, #40] ; 0x28 if (descr->usart_cb.tx_done) { ed8: 69c3 ldr r3, [r0, #28] eda: b10b cbz r3, ee0 descr->usart_cb.tx_done(descr); edc: 3808 subs r0, #8 ede: 4718 bx r3 } } ee0: 4770 bx lr 00000ee2 : */ static void usart_error(struct _usart_async_device *device) { struct usart_async_descriptor *descr = CONTAINER_OF(device, struct usart_async_descriptor, device); descr->stat = 0; ee2: 2300 movs r3, #0 ee4: 6283 str r3, [r0, #40] ; 0x28 if (descr->usart_cb.error) { ee6: 6a43 ldr r3, [r0, #36] ; 0x24 ee8: b10b cbz r3, eee descr->usart_cb.error(descr); eea: 3808 subs r0, #8 eec: 4718 bx r3 } } eee: 4770 bx lr 00000ef0 : { ef0: b570 push {r4, r5, r6, lr} ef2: 4604 mov r4, r0 ringbuffer_put(&descr->rx, data); ef4: 4b05 ldr r3, [pc, #20] ; (f0c ) ef6: f1a0 0508 sub.w r5, r0, #8 efa: 302c adds r0, #44 ; 0x2c efc: 4798 blx r3 if (descr->usart_cb.rx_done) { efe: 6a23 ldr r3, [r4, #32] f00: b11b cbz r3, f0a descr->usart_cb.rx_done(descr); f02: 4628 mov r0, r5 } f04: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} descr->usart_cb.rx_done(descr); f08: 4718 bx r3 } f0a: bd70 pop {r4, r5, r6, pc} f0c: 00001169 .word 0x00001169 00000f10 : { f10: b570 push {r4, r5, r6, lr} f12: 460e mov r6, r1 f14: 4615 mov r5, r2 ASSERT(descr && buf && length); f16: 4604 mov r4, r0 f18: b118 cbz r0, f22 f1a: b1d9 cbz r1, f54 f1c: 1e10 subs r0, r2, #0 f1e: bf18 it ne f20: 2001 movne r0, #1 f22: 4b0f ldr r3, [pc, #60] ; (f60 ) f24: 490f ldr r1, [pc, #60] ; (f64 ) f26: f240 123b movw r2, #315 ; 0x13b f2a: 4798 blx r3 if (descr->tx_por != descr->tx_buffer_length) { f2c: f8b4 2044 ldrh.w r2, [r4, #68] ; 0x44 f30: f8b4 304c ldrh.w r3, [r4, #76] ; 0x4c f34: 429a cmp r2, r3 f36: d10f bne.n f58 descr->tx_por = 0; f38: 2300 movs r3, #0 f3a: f8a4 3044 strh.w r3, [r4, #68] ; 0x44 descr->stat = USART_ASYNC_STATUS_BUSY; f3e: 2301 movs r3, #1 f40: 6323 str r3, [r4, #48] ; 0x30 _usart_async_enable_byte_sent_irq(&descr->device); f42: f104 0008 add.w r0, r4, #8 f46: 4b08 ldr r3, [pc, #32] ; (f68 ) descr->tx_buffer = (uint8_t *)buf; f48: 64a6 str r6, [r4, #72] ; 0x48 descr->tx_buffer_length = length; f4a: f8a4 504c strh.w r5, [r4, #76] ; 0x4c _usart_async_enable_byte_sent_irq(&descr->device); f4e: 4798 blx r3 return (int32_t)length; f50: 4628 mov r0, r5 } f52: bd70 pop {r4, r5, r6, pc} ASSERT(descr && buf && length); f54: 4608 mov r0, r1 f56: e7e4 b.n f22 return ERR_NO_RESOURCE; f58: f06f 001b mvn.w r0, #27 f5c: e7f9 b.n f52 f5e: bf00 nop f60: 0000056d .word 0x0000056d f64: 000014b1 .word 0x000014b1 f68: 000009f7 .word 0x000009f7 00000f6c : if (descr->tx_por != descr->tx_buffer_length) { f6c: 8f83 ldrh r3, [r0, #60] ; 0x3c f6e: f8b0 2044 ldrh.w r2, [r0, #68] ; 0x44 f72: 429a cmp r2, r3 { f74: b510 push {r4, lr} f76: 4604 mov r4, r0 if (descr->tx_por != descr->tx_buffer_length) { f78: d00a beq.n f90 _usart_async_write_byte(&descr->device, descr->tx_buffer[descr->tx_por++]); f7a: 6c02 ldr r2, [r0, #64] ; 0x40 f7c: 1c59 adds r1, r3, #1 f7e: 8781 strh r1, [r0, #60] ; 0x3c f80: 5cd1 ldrb r1, [r2, r3] f82: 4b04 ldr r3, [pc, #16] ; (f94 ) f84: 4798 blx r3 _usart_async_enable_byte_sent_irq(&descr->device); f86: 4b04 ldr r3, [pc, #16] ; (f98 ) f88: 4620 mov r0, r4 } f8a: e8bd 4010 ldmia.w sp!, {r4, lr} _usart_async_enable_tx_done_irq(&descr->device); f8e: 4718 bx r3 f90: 4b02 ldr r3, [pc, #8] ; (f9c ) f92: e7fa b.n f8a f94: 000009f1 .word 0x000009f1 f98: 000009f7 .word 0x000009f7 f9c: 000009ff .word 0x000009ff 00000fa0 : { fa0: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr} fa4: 460e mov r6, r1 fa6: 4617 mov r7, r2 ASSERT(descr && buf && length); fa8: 4604 mov r4, r0 faa: b118 cbz r0, fb4 fac: b1e9 cbz r1, fea fae: 1e10 subs r0, r2, #0 fb0: bf18 it ne fb2: 2001 movne r0, #1 fb4: 4910 ldr r1, [pc, #64] ; (ff8 ) fb6: 4b11 ldr r3, [pc, #68] ; (ffc ) ringbuffer_get(&descr->rx, &buf[was_read++]); fb8: f8df 9050 ldr.w r9, [pc, #80] ; 100c ASSERT(descr && buf && length); fbc: f44f 72ac mov.w r2, #344 ; 0x158 fc0: 4798 blx r3 num = ringbuffer_num(&descr->rx); fc2: 3434 adds r4, #52 ; 0x34 CRITICAL_SECTION_ENTER() fc4: 4b0e ldr r3, [pc, #56] ; (1000 ) fc6: a801 add r0, sp, #4 fc8: 4798 blx r3 num = ringbuffer_num(&descr->rx); fca: 4b0e ldr r3, [pc, #56] ; (1004 ) fcc: 4620 mov r0, r4 fce: 4798 blx r3 CRITICAL_SECTION_LEAVE() fd0: 4b0d ldr r3, [pc, #52] ; (1008 ) num = ringbuffer_num(&descr->rx); fd2: 4680 mov r8, r0 CRITICAL_SECTION_LEAVE() fd4: a801 add r0, sp, #4 fd6: 4798 blx r3 while ((was_read < num) && (was_read < length)) { fd8: 2500 movs r5, #0 fda: 45a8 cmp r8, r5 fdc: d001 beq.n fe2 fde: 42bd cmp r5, r7 fe0: d105 bne.n fee } fe2: 4628 mov r0, r5 fe4: b003 add sp, #12 fe6: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} ASSERT(descr && buf && length); fea: 4608 mov r0, r1 fec: e7e2 b.n fb4 ringbuffer_get(&descr->rx, &buf[was_read++]); fee: 1971 adds r1, r6, r5 ff0: 4620 mov r0, r4 ff2: 47c8 blx r9 ff4: 3501 adds r5, #1 ff6: e7f0 b.n fda ff8: 000014b1 .word 0x000014b1 ffc: 0000056d .word 0x0000056d 1000: 00001399 .word 0x00001399 1004: 000011ad .word 0x000011ad 1008: 000013a7 .word 0x000013a7 100c: 00001129 .word 0x00001129 00001010 : { 1010: b5f8 push {r3, r4, r5, r6, r7, lr} 1012: 460d mov r5, r1 1014: 4616 mov r6, r2 1016: 461f mov r7, r3 ASSERT(descr && hw && rx_buffer && rx_buffer_length); 1018: 4604 mov r4, r0 101a: b120 cbz r0, 1026 101c: b309 cbz r1, 1062 101e: b312 cbz r2, 1066 1020: 1e18 subs r0, r3, #0 1022: bf18 it ne 1024: 2001 movne r0, #1 1026: 4912 ldr r1, [pc, #72] ; (1070 ) 1028: 4b12 ldr r3, [pc, #72] ; (1074 ) 102a: 223a movs r2, #58 ; 0x3a 102c: 4798 blx r3 if (ERR_NONE != ringbuffer_init(&descr->rx, rx_buffer, rx_buffer_length)) { 102e: 4b12 ldr r3, [pc, #72] ; (1078 ) 1030: 463a mov r2, r7 1032: 4631 mov r1, r6 1034: f104 0034 add.w r0, r4, #52 ; 0x34 1038: 4798 blx r3 103a: b9b0 cbnz r0, 106a init_status = _usart_async_init(&descr->device, hw); 103c: 4b0f ldr r3, [pc, #60] ; (107c ) 103e: 4629 mov r1, r5 1040: f104 0008 add.w r0, r4, #8 1044: 4798 blx r3 if (init_status) { 1046: b958 cbnz r0, 1060 descr->io.read = usart_async_read; 1048: 4b0d ldr r3, [pc, #52] ; (1080 ) 104a: 6063 str r3, [r4, #4] descr->io.write = usart_async_write; 104c: 4b0d ldr r3, [pc, #52] ; (1084 ) 104e: 6023 str r3, [r4, #0] descr->device.usart_cb.tx_byte_sent = usart_process_byte_sent; 1050: 4b0d ldr r3, [pc, #52] ; (1088 ) 1052: 60a3 str r3, [r4, #8] descr->device.usart_cb.rx_done_cb = usart_fill_rx_buffer; 1054: 4b0d ldr r3, [pc, #52] ; (108c ) 1056: 60e3 str r3, [r4, #12] descr->device.usart_cb.tx_done_cb = usart_transmission_complete; 1058: 4b0d ldr r3, [pc, #52] ; (1090 ) 105a: 6123 str r3, [r4, #16] descr->device.usart_cb.error_cb = usart_error; 105c: 4b0d ldr r3, [pc, #52] ; (1094 ) 105e: 6163 str r3, [r4, #20] } 1060: bdf8 pop {r3, r4, r5, r6, r7, pc} ASSERT(descr && hw && rx_buffer && rx_buffer_length); 1062: 4608 mov r0, r1 1064: e7df b.n 1026 1066: 4610 mov r0, r2 1068: e7dd b.n 1026 return ERR_INVALID_ARG; 106a: f06f 000c mvn.w r0, #12 106e: e7f7 b.n 1060 1070: 000014b1 .word 0x000014b1 1074: 0000056d .word 0x0000056d 1078: 000010ed .word 0x000010ed 107c: 0000096d .word 0x0000096d 1080: 00000fa1 .word 0x00000fa1 1084: 00000f11 .word 0x00000f11 1088: 00000f6d .word 0x00000f6d 108c: 00000ef1 .word 0x00000ef1 1090: 00000ed5 .word 0x00000ed5 1094: 00000ee3 .word 0x00000ee3 00001098 : middle = (upper + lower) >> 1; if (middle >= EXT_IRQ_AMOUNT) { return; } if (ext_irqs[middle].pin == pin) { 1098: 4b0b ldr r3, [pc, #44] ; (10c8 ) { 109a: b430 push {r4, r5} if (ext_irqs[middle].pin == pin) { 109c: 685c ldr r4, [r3, #4] uint8_t lower = 0, middle, upper = EXT_IRQ_AMOUNT; 109e: 2101 movs r1, #1 10a0: 2200 movs r2, #0 while (upper >= lower) { 10a2: 4291 cmp r1, r2 10a4: d201 bcs.n 10aa lower = middle + 1; } else { upper = middle - 1; } } } 10a6: bc30 pop {r4, r5} 10a8: 4770 bx lr middle = (upper + lower) >> 1; 10aa: 188d adds r5, r1, r2 if (middle >= EXT_IRQ_AMOUNT) { 10ac: 086d lsrs r5, r5, #1 10ae: d1fa bne.n 10a6 if (ext_irqs[middle].pin == pin) { 10b0: 4284 cmp r4, r0 10b2: d104 bne.n 10be if (ext_irqs[middle].cb) { 10b4: 681b ldr r3, [r3, #0] 10b6: 2b00 cmp r3, #0 10b8: d0f5 beq.n 10a6 } 10ba: bc30 pop {r4, r5} ext_irqs[middle].cb(); 10bc: 4718 bx r3 upper = middle - 1; 10be: bf2c ite cs 10c0: 21ff movcs r1, #255 ; 0xff lower = middle + 1; 10c2: 2201 movcc r2, #1 10c4: e7ed b.n 10a2 10c6: bf00 nop 10c8: 20000030 .word 0x20000030 000010cc : ext_irqs[i].pin = 0xFFFFFFFF; 10cc: 4b04 ldr r3, [pc, #16] ; (10e0 ) return _ext_irq_init(process_ext_irq); 10ce: 4805 ldr r0, [pc, #20] ; (10e4 ) ext_irqs[i].cb = NULL; 10d0: 2200 movs r2, #0 10d2: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff 10d6: e9c3 2100 strd r2, r1, [r3] return _ext_irq_init(process_ext_irq); 10da: 4b03 ldr r3, [pc, #12] ; (10e8 ) 10dc: 4718 bx r3 10de: bf00 nop 10e0: 20000030 .word 0x20000030 10e4: 00001099 .word 0x00001099 10e8: 000002b5 .word 0x000002b5 000010ec : /** * \brief Ringbuffer init */ int32_t ringbuffer_init(struct ringbuffer *const rb, void *buf, uint32_t size) { 10ec: b570 push {r4, r5, r6, lr} 10ee: 460e mov r6, r1 10f0: 4614 mov r4, r2 ASSERT(rb && buf && size); 10f2: 4605 mov r5, r0 10f4: b118 cbz r0, 10fe 10f6: b189 cbz r1, 111c 10f8: 1e10 subs r0, r2, #0 10fa: bf18 it ne 10fc: 2001 movne r0, #1 10fe: 4908 ldr r1, [pc, #32] ; (1120 ) 1100: 4b08 ldr r3, [pc, #32] ; (1124 ) 1102: 2228 movs r2, #40 ; 0x28 1104: 4798 blx r3 /* * buf size must be aligned to power of 2 */ if ((size & (size - 1)) != 0) { 1106: 1e63 subs r3, r4, #1 1108: ea13 0004 ands.w r0, r3, r4 return ERR_INVALID_ARG; } /* size - 1 is faster in calculation */ rb->size = size - 1; rb->read_index = 0; 110c: bf03 ittte eq 110e: e9c5 3001 strdeq r3, r0, [r5, #4] rb->write_index = rb->read_index; 1112: 60e8 streq r0, [r5, #12] rb->buf = (uint8_t *)buf; 1114: 602e streq r6, [r5, #0] return ERR_INVALID_ARG; 1116: f06f 000c mvnne.w r0, #12 return ERR_NONE; } 111a: bd70 pop {r4, r5, r6, pc} ASSERT(rb && buf && size); 111c: 4608 mov r0, r1 111e: e7ee b.n 10fe 1120: 000014ce .word 0x000014ce 1124: 0000056d .word 0x0000056d 00001128 : /** * \brief Get one byte from ringbuffer * */ int32_t ringbuffer_get(struct ringbuffer *const rb, uint8_t *data) { 1128: b538 push {r3, r4, r5, lr} 112a: 460d mov r5, r1 ASSERT(rb && data); 112c: 4604 mov r4, r0 112e: b110 cbz r0, 1136 1130: 1e08 subs r0, r1, #0 1132: bf18 it ne 1134: 2001 movne r0, #1 1136: 4b0a ldr r3, [pc, #40] ; (1160 ) 1138: 490a ldr r1, [pc, #40] ; (1164 ) 113a: 2240 movs r2, #64 ; 0x40 113c: 4798 blx r3 if (rb->write_index != rb->read_index) { 113e: e9d4 3202 ldrd r3, r2, [r4, #8] 1142: 429a cmp r2, r3 1144: d009 beq.n 115a *data = rb->buf[rb->read_index & rb->size]; 1146: 6862 ldr r2, [r4, #4] 1148: 4013 ands r3, r2 114a: 6822 ldr r2, [r4, #0] 114c: 5cd3 ldrb r3, [r2, r3] 114e: 702b strb r3, [r5, #0] rb->read_index++; 1150: 68a3 ldr r3, [r4, #8] 1152: 3301 adds r3, #1 1154: 60a3 str r3, [r4, #8] return ERR_NONE; 1156: 2000 movs r0, #0 } return ERR_NOT_FOUND; } 1158: bd38 pop {r3, r4, r5, pc} return ERR_NOT_FOUND; 115a: f06f 0009 mvn.w r0, #9 115e: e7fb b.n 1158 1160: 0000056d .word 0x0000056d 1164: 000014ce .word 0x000014ce 00001168 : /** * \brief Put one byte to ringbuffer * */ int32_t ringbuffer_put(struct ringbuffer *const rb, uint8_t data) { 1168: b538 push {r3, r4, r5, lr} ASSERT(rb); 116a: 4604 mov r4, r0 116c: 3800 subs r0, #0 116e: bf18 it ne 1170: 2001 movne r0, #1 { 1172: 460d mov r5, r1 ASSERT(rb); 1174: 4b0b ldr r3, [pc, #44] ; (11a4 ) 1176: 490c ldr r1, [pc, #48] ; (11a8 ) 1178: 2251 movs r2, #81 ; 0x51 117a: 4798 blx r3 rb->buf[rb->write_index & rb->size] = data; 117c: 68e3 ldr r3, [r4, #12] 117e: 6862 ldr r2, [r4, #4] 1180: 4013 ands r3, r2 1182: 6822 ldr r2, [r4, #0] 1184: 54d5 strb r5, [r2, r3] /* * buffer full strategy: new data will overwrite the oldest data in * the buffer */ if ((rb->write_index - rb->read_index) > rb->size) { 1186: e9d4 2101 ldrd r2, r1, [r4, #4] 118a: 68e3 ldr r3, [r4, #12] 118c: 1a59 subs r1, r3, r1 118e: 4291 cmp r1, r2 rb->read_index = rb->write_index - rb->size; 1190: bf88 it hi 1192: 1a9a subhi r2, r3, r2 } rb->write_index++; 1194: f103 0301 add.w r3, r3, #1 rb->read_index = rb->write_index - rb->size; 1198: bf88 it hi 119a: 60a2 strhi r2, [r4, #8] rb->write_index++; 119c: 60e3 str r3, [r4, #12] return ERR_NONE; } 119e: 2000 movs r0, #0 11a0: bd38 pop {r3, r4, r5, pc} 11a2: bf00 nop 11a4: 0000056d .word 0x0000056d 11a8: 000014ce .word 0x000014ce 000011ac : /** * \brief Return the element number of ringbuffer */ uint32_t ringbuffer_num(const struct ringbuffer *const rb) { 11ac: b510 push {r4, lr} ASSERT(rb); 11ae: 4604 mov r4, r0 11b0: 3800 subs r0, #0 11b2: bf18 it ne 11b4: 2001 movne r0, #1 11b6: 4904 ldr r1, [pc, #16] ; (11c8 ) 11b8: 4b04 ldr r3, [pc, #16] ; (11cc ) 11ba: 2267 movs r2, #103 ; 0x67 11bc: 4798 blx r3 return rb->write_index - rb->read_index; 11be: e9d4 3002 ldrd r3, r0, [r4, #8] } 11c2: 1ac0 subs r0, r0, r3 11c4: bd10 pop {r4, pc} 11c6: bf00 nop 11c8: 000014ce .word 0x000014ce 11cc: 0000056d .word 0x0000056d 000011d0 : /** * Initializes MCU, drivers and middleware in the project **/ void atmel_start_init(void) { system_init(); 11d0: 4b00 ldr r3, [pc, #0] ; (11d4 ) 11d2: 4718 bx r3 11d4: 00000e75 .word 0x00000e75 000011d8 : typedef uint8_t hri_tccount8_per_reg_t; typedef uint8_t hri_tccount8_perbuf_reg_t; static inline void hri_tc_wait_for_sync(const void *const hw, hri_tc_syncbusy_reg_t reg) { while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) { 11d8: 6903 ldr r3, [r0, #16] 11da: 420b tst r3, r1 11dc: d1fc bne.n 11d8 }; } 11de: 4770 bx lr 000011e0 : * \param[in] hw The pointer to hardware instance * * \return The index of TC configuration */ static int8_t get_tc_index(const void *const hw) { 11e0: b570 push {r4, r5, r6, lr} * \param[in] hw The pointer to hardware instance */ static inline uint8_t _get_hardware_offset(const void *const hw) { /* List of available TC modules. */ Tc *const tc_modules[TC_INST_NUM] = TC_INSTS; 11e2: 4d10 ldr r5, [pc, #64] ; (1224 ) { 11e4: 4606 mov r6, r0 Tc *const tc_modules[TC_INST_NUM] = TC_INSTS; 11e6: cd0f ldmia r5!, {r0, r1, r2, r3} { 11e8: b088 sub sp, #32 Tc *const tc_modules[TC_INST_NUM] = TC_INSTS; 11ea: 466c mov r4, sp 11ec: c40f stmia r4!, {r0, r1, r2, r3} 11ee: e895 000f ldmia.w r5, {r0, r1, r2, r3} 11f2: e884 000f stmia.w r4, {r0, r1, r2, r3} /* Find index for TC instance. */ for (uint32_t i = 0; i < TC_INST_NUM; i++) { 11f6: 466a mov r2, sp 11f8: 2000 movs r0, #0 if ((uint32_t)hw == (uint32_t)tc_modules[i]) { 11fa: f852 1b04 ldr.w r1, [r2], #4 11fe: 42b1 cmp r1, r6 1200: d102 bne.n 1208 if (_tcs[i].number == index) { 1202: b930 cbnz r0, 1212 } 1204: b008 add sp, #32 1206: bd70 pop {r4, r5, r6, pc} for (uint32_t i = 0; i < TC_INST_NUM; i++) { 1208: 3001 adds r0, #1 120a: 2808 cmp r0, #8 120c: d1f5 bne.n 11fa return i; 120e: 2000 movs r0, #0 1210: e7f8 b.n 1204 ASSERT(false); 1212: 2000 movs r0, #0 1214: 4904 ldr r1, [pc, #16] ; (1228 ) 1216: 4b05 ldr r3, [pc, #20] ; (122c ) 1218: f44f 729e mov.w r2, #316 ; 0x13c 121c: 4798 blx r3 121e: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 1222: e7ef b.n 1204 1224: 00001508 .word 0x00001508 1228: 000014f2 .word 0x000014f2 122c: 0000056d .word 0x0000056d 00001230 <_timer_init>: { 1230: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} int8_t i = get_tc_index(hw); 1234: 4b48 ldr r3, [pc, #288] ; (1358 <_timer_init+0x128>) { 1236: 4681 mov r9, r0 int8_t i = get_tc_index(hw); 1238: 4608 mov r0, r1 { 123a: 460c mov r4, r1 int8_t i = get_tc_index(hw); 123c: 4798 blx r3 ASSERT(ARRAY_SIZE(_tcs)); 123e: 4b47 ldr r3, [pc, #284] ; (135c <_timer_init+0x12c>) 1240: 4947 ldr r1, [pc, #284] ; (1360 <_timer_init+0x130>) device->hw = hw; 1242: f8c9 400c str.w r4, [r9, #12] ASSERT(ARRAY_SIZE(_tcs)); 1246: 228d movs r2, #141 ; 0x8d int8_t i = get_tc_index(hw); 1248: 4606 mov r6, r0 ASSERT(ARRAY_SIZE(_tcs)); 124a: 2001 movs r0, #1 124c: 4798 blx r3 static inline bool hri_tc_is_syncing(const void *const hw, hri_tc_syncbusy_reg_t reg) { return ((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg; 124e: 6923 ldr r3, [r4, #16] 1250: 4a44 ldr r2, [pc, #272] ; (1364 <_timer_init+0x134>) if (!hri_tc_is_syncing(hw, TC_SYNCBUSY_SWRST)) { 1252: f013 0f01 tst.w r3, #1 1256: d112 bne.n 127e <_timer_init+0x4e> } static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) { uint32_t tmp; hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); 1258: 2103 movs r1, #3 125a: 4620 mov r0, r4 125c: 4790 blx r2 tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; 125e: 6823 ldr r3, [r4, #0] if (hri_tc_get_CTRLA_reg(hw, TC_CTRLA_ENABLE)) { 1260: 079b lsls r3, r3, #30 1262: d507 bpl.n 1274 <_timer_init+0x44> ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE; 1264: 6823 ldr r3, [r4, #0] 1266: f023 0302 bic.w r3, r3, #2 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); 126a: 2103 movs r1, #3 ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE; 126c: 6023 str r3, [r4, #0] hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); 126e: 4790 blx r2 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_ENABLE); 1270: 2102 movs r1, #2 1272: 4790 blx r2 } static inline void hri_tc_write_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t data) { TC_CRITICAL_SECTION_ENTER(); ((Tc *)hw)->COUNT16.CTRLA.reg = data; 1274: 2301 movs r3, #1 1276: 6023 str r3, [r4, #0] hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); 1278: 2103 movs r1, #3 127a: 4620 mov r0, r4 127c: 4790 blx r2 hri_tc_write_CTRLA_reg(hw, _tcs[i].ctrl_a); 127e: f8df 80f4 ldr.w r8, [pc, #244] ; 1374 <_timer_init+0x144> 1282: 2514 movs r5, #20 1284: fb05 8506 mla r5, r5, r6, r8 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); 1288: 2101 movs r1, #1 128a: 4620 mov r0, r4 128c: 4790 blx r2 hri_tc_write_CTRLA_reg(hw, _tcs[i].ctrl_a); 128e: 6a6f ldr r7, [r5, #36] ; 0x24 ((Tc *)hw)->COUNT16.CTRLA.reg = data; 1290: 6027 str r7, [r4, #0] hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); 1292: 2103 movs r1, #3 1294: 4790 blx r2 hri_tc_write_DBGCTRL_reg(hw, _tcs[i].dbg_ctrl); 1296: f895 302a ldrb.w r3, [r5, #42] ; 0x2a } static inline void hri_tc_write_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t data) { TC_CRITICAL_SECTION_ENTER(); ((Tc *)hw)->COUNT16.DBGCTRL.reg = data; 129a: 73e3 strb r3, [r4, #15] if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) { 129c: f007 070c and.w r7, r7, #12 hri_tc_write_EVCTRL_reg(hw, _tcs[i].event_ctrl); 12a0: 8d2b ldrh r3, [r5, #40] ; 0x28 ((Tc *)hw)->COUNT16.EVCTRL.reg = data; 12a2: 80e3 strh r3, [r4, #6] if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) { 12a4: 2f08 cmp r7, #8 ((Tc *)hw)->COUNT16.WAVE.reg = data; 12a6: f04f 0301 mov.w r3, #1 12aa: 7323 strb r3, [r4, #12] 12ac: d13c bne.n 1328 <_timer_init+0xf8> hri_tccount32_write_CC_reg(hw, 0, _tcs[i].cc0); 12ae: 6aeb ldr r3, [r5, #44] ; 0x2c } static inline void hri_tccount32_write_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data) { TC_CRITICAL_SECTION_ENTER(); ((Tc *)hw)->COUNT32.CC[index].reg = data; 12b0: 61e3 str r3, [r4, #28] hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); 12b2: 21c0 movs r1, #192 ; 0xc0 12b4: 4790 blx r2 ((Tc *)hw)->COUNT32.CC[index].reg = data; 12b6: 2300 movs r3, #0 12b8: 6223 str r3, [r4, #32] hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); 12ba: 21c0 movs r1, #192 ; 0xc0 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); 12bc: 4620 mov r0, r4 12be: 4790 blx r2 ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF; 12c0: 2301 movs r3, #1 12c2: 7263 strb r3, [r4, #9] if (hw == TC0) { 12c4: 4b28 ldr r3, [pc, #160] ; (1368 <_timer_init+0x138>) 12c6: 429c cmp r4, r3 _tc0_dev = (struct _timer_device *)dev; 12c8: bf04 itt eq 12ca: 4b28 ldreq r3, [pc, #160] ; (136c <_timer_init+0x13c>) 12cc: f8c3 9000 streq.w r9, [r3] NVIC_DisableIRQ(_tcs[i].irq); 12d0: 2314 movs r3, #20 12d2: fb03 8306 mla r3, r3, r6, r8 12d6: f9b3 3022 ldrsh.w r3, [r3, #34] ; 0x22 if ((int32_t)(IRQn) >= 0) 12da: 2b00 cmp r3, #0 12dc: db0d blt.n 12fa <_timer_init+0xca> NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 12de: 095a lsrs r2, r3, #5 12e0: 2101 movs r1, #1 12e2: f003 031f and.w r3, r3, #31 12e6: fa01 f303 lsl.w r3, r1, r3 12ea: 3220 adds r2, #32 12ec: 4920 ldr r1, [pc, #128] ; (1370 <_timer_init+0x140>) 12ee: f841 3022 str.w r3, [r1, r2, lsl #2] __ASM volatile ("dsb 0xF":::"memory"); 12f2: f3bf 8f4f dsb sy __ASM volatile ("isb 0xF":::"memory"); 12f6: f3bf 8f6f isb sy NVIC_ClearPendingIRQ(_tcs[i].irq); 12fa: 2014 movs r0, #20 12fc: fb00 8606 mla r6, r0, r6, r8 1300: f9b6 3022 ldrsh.w r3, [r6, #34] ; 0x22 if ((int32_t)(IRQn) >= 0) 1304: 2b00 cmp r3, #0 1306: db0c blt.n 1322 <_timer_init+0xf2> NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1308: f003 011f and.w r1, r3, #31 130c: 095b lsrs r3, r3, #5 130e: 009b lsls r3, r3, #2 1310: f103 4360 add.w r3, r3, #3758096384 ; 0xe0000000 1314: f503 4361 add.w r3, r3, #57600 ; 0xe100 1318: 2201 movs r2, #1 131a: 408a lsls r2, r1 131c: f8c3 2180 str.w r2, [r3, #384] ; 0x180 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1320: 601a str r2, [r3, #0] } 1322: 2000 movs r0, #0 1324: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} } else if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT16) { 1328: b92f cbnz r7, 1336 <_timer_init+0x106> hri_tccount16_write_CC_reg(hw, 0, (uint16_t)_tcs[i].cc0); 132a: 8dab ldrh r3, [r5, #44] ; 0x2c ((Tc *)hw)->COUNT16.CC[index].reg = data; 132c: 83a3 strh r3, [r4, #28] hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); 132e: 21c0 movs r1, #192 ; 0xc0 1330: 4790 blx r2 ((Tc *)hw)->COUNT16.CC[index].reg = data; 1332: 83e7 strh r7, [r4, #30] 1334: e7c1 b.n 12ba <_timer_init+0x8a> } else if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT8) { 1336: 2f04 cmp r7, #4 1338: d1c2 bne.n 12c0 <_timer_init+0x90> hri_tccount8_write_CC_reg(hw, 0, (uint8_t)_tcs[i].cc0); 133a: f895 302c ldrb.w r3, [r5, #44] ; 0x2c ((Tc *)hw)->COUNT8.CC[index].reg = data; 133e: 7723 strb r3, [r4, #28] hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); 1340: 21c0 movs r1, #192 ; 0xc0 1342: 4790 blx r2 ((Tc *)hw)->COUNT8.CC[index].reg = data; 1344: 2300 movs r3, #0 1346: 7763 strb r3, [r4, #29] hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); 1348: 21c0 movs r1, #192 ; 0xc0 134a: 4790 blx r2 hri_tccount8_write_PER_reg(hw, _tcs[i].per); 134c: f895 302b ldrb.w r3, [r5, #43] ; 0x2b ((Tc *)hw)->COUNT8.PER.reg = data; 1350: 76e3 strb r3, [r4, #27] hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); 1352: 2120 movs r1, #32 1354: e7b2 b.n 12bc <_timer_init+0x8c> 1356: bf00 nop 1358: 000011e1 .word 0x000011e1 135c: 0000056d .word 0x0000056d 1360: 000014f2 .word 0x000014f2 1364: 000011d9 .word 0x000011d9 1368: 40003800 .word 0x40003800 136c: 20000038 .word 0x20000038 1370: e000e100 .word 0xe000e100 1374: 00001508 .word 0x00001508 00001378 <_tc_get_timer>: } 1378: 2000 movs r0, #0 137a: 4770 bx lr 0000137c : tc_interrupt_handler(_tc0_dev); 137c: 4b05 ldr r3, [pc, #20] ; (1394 ) 137e: 6818 ldr r0, [r3, #0] void *const hw = device->hw; 1380: 68c3 ldr r3, [r0, #12] return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; 1382: 7a9a ldrb r2, [r3, #10] if (hri_tc_get_interrupt_OVF_bit(hw)) { 1384: 07d2 lsls r2, r2, #31 1386: d503 bpl.n 1390 ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF; 1388: 2201 movs r2, #1 138a: 729a strb r2, [r3, #10] device->timer_cb.period_expired(device); 138c: 6803 ldr r3, [r0, #0] 138e: 4718 bx r3 } 1390: 4770 bx lr 1392: bf00 nop 1394: 20000038 .word 0x20000038 00001398 : __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 1398: f3ef 8310 mrs r3, PRIMASK /** * \brief Disable interrupts, enter critical section */ void atomic_enter_critical(hal_atomic_t volatile *atomic) { *atomic = __get_PRIMASK(); 139c: 6003 str r3, [r0, #0] __ASM volatile ("cpsid i" : : : "memory"); 139e: b672 cpsid i \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ __STATIC_FORCEINLINE void __DMB(void) { __ASM volatile ("dmb 0xF":::"memory"); 13a0: f3bf 8f5f dmb sy __disable_irq(); __DMB(); } 13a4: 4770 bx lr 000013a6 : 13a6: f3bf 8f5f dmb sy * \brief Exit atomic section */ void atomic_leave_critical(hal_atomic_t volatile *atomic) { __DMB(); __set_PRIMASK(*atomic); 13aa: 6803 ldr r3, [r0, #0] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 13ac: f383 8810 msr PRIMASK, r3 } 13b0: 4770 bx lr ... 000013b4 <__libc_init_array>: 13b4: b570 push {r4, r5, r6, lr} 13b6: 4d0d ldr r5, [pc, #52] ; (13ec <__libc_init_array+0x38>) 13b8: 4c0d ldr r4, [pc, #52] ; (13f0 <__libc_init_array+0x3c>) 13ba: 1b64 subs r4, r4, r5 13bc: 10a4 asrs r4, r4, #2 13be: 2600 movs r6, #0 13c0: 42a6 cmp r6, r4 13c2: d109 bne.n 13d8 <__libc_init_array+0x24> 13c4: 4d0b ldr r5, [pc, #44] ; (13f4 <__libc_init_array+0x40>) 13c6: 4c0c ldr r4, [pc, #48] ; (13f8 <__libc_init_array+0x44>) 13c8: f000 f8b8 bl 153c <_init> 13cc: 1b64 subs r4, r4, r5 13ce: 10a4 asrs r4, r4, #2 13d0: 2600 movs r6, #0 13d2: 42a6 cmp r6, r4 13d4: d105 bne.n 13e2 <__libc_init_array+0x2e> 13d6: bd70 pop {r4, r5, r6, pc} 13d8: f855 3b04 ldr.w r3, [r5], #4 13dc: 4798 blx r3 13de: 3601 adds r6, #1 13e0: e7ee b.n 13c0 <__libc_init_array+0xc> 13e2: f855 3b04 ldr.w r3, [r5], #4 13e6: 4798 blx r3 13e8: 3601 adds r6, #1 13ea: e7f2 b.n 13d2 <__libc_init_array+0x1e> 13ec: 00001548 .word 0x00001548 13f0: 00001548 .word 0x00001548 13f4: 00001548 .word 0x00001548 13f8: 0000154c .word 0x0000154c 13fc: 682f2e2e .word 0x682f2e2e 1400: 732f6c61 .word 0x732f6c61 1404: 682f6372 .word 0x682f6372 1408: 745f6c61 .word 0x745f6c61 140c: 72656d69 .word 0x72656d69 1410: 632e .short 0x632e 1412: 00 .byte 0x00 1413: 2e .byte 0x2e 1414: 61682f2e .word 0x61682f2e 1418: 72732f6c .word 0x72732f6c 141c: 61682f63 .word 0x61682f63 1420: 32695f6c .word 0x32695f6c 1424: 5f6d5f63 .word 0x5f6d5f63 1428: 636e7973 .word 0x636e7973 142c: 632e .short 0x632e 142e: 00 .byte 0x00 142f: 2e .byte 0x2e 1430: 61682f2e .word 0x61682f2e 1434: 74752f6c .word 0x74752f6c 1438: 2f736c69 .word 0x2f736c69 143c: 2f637273 .word 0x2f637273 1440: 6c697475 .word 0x6c697475 1444: 696c5f73 .word 0x696c5f73 1448: 632e7473 .word 0x632e7473 144c: 00 .byte 0x00 144d: 2e .byte 0x2e 144e: 2f2e .short 0x2f2e 1450: 2f6c7068 .word 0x2f6c7068 1454: 63726573 .word 0x63726573 1458: 682f6d6f .word 0x682f6d6f 145c: 735f6c70 .word 0x735f6c70 1460: 6f637265 .word 0x6f637265 1464: 00632e6d .word 0x00632e6d 1468: 40003000 .word 0x40003000 146c: 40003400 .word 0x40003400 1470: 41012000 .word 0x41012000 1474: 41014000 .word 0x41014000 1478: 43000000 .word 0x43000000 147c: 43000400 .word 0x43000400 1480: 43000800 .word 0x43000800 1484: 43000c00 .word 0x43000c00 00001488 <_i2cms>: 1488: 00000003 00200014 00000100 000000ff ...... ......... 1498: 00d70000 07270400 ......'. 000014a0 : ... 14b0: 2f2e2e00 2f6c6168 2f637273 5f6c6168 .../hal/src/hal_ 14c0: 72617375 73615f74 2e636e79 2e2e0063 usart_async.c... 14d0: 6c61682f 6974752f 732f736c 752f6372 /hal/utils/src/u 14e0: 736c6974 6e69725f 66756267 2e726566 tils_ringbuffer. 14f0: 2e2e0063 6c70682f 2f63742f 5f6c7068 c.../hpl/tc/hpl_ 1500: 632e6374 00000000 40003800 40003c00 tc.c.....8.@.<.@ 1510: 4101a000 4101c000 42001400 42001800 ...A...A...B...B 1520: 43001400 43001800 ...C...C 00001528 <_tcs>: 1528: 006b0000 00000308 00000000 00003a97 ..k..........:.. 1538: 00000000 .... 0000153c <_init>: 153c: b5f8 push {r3, r4, r5, r6, r7, lr} 153e: bf00 nop 1540: bcf8 pop {r3, r4, r5, r6, r7} 1542: bc08 pop {r3} 1544: 469e mov lr, r3 1546: 4770 bx lr 00001548 <__frame_dummy_init_array_entry>: 1548: 0289 0000 .... 0000154c <_fini>: 154c: b5f8 push {r3, r4, r5, r6, r7, lr} 154e: bf00 nop 1550: bcf8 pop {r3, r4, r5, r6, r7} 1552: bc08 pop {r3} 1554: 469e mov lr, r3 1556: 4770 bx lr 00001558 <__do_global_dtors_aux_fini_array_entry>: 1558: 0265 0000 e...