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SAMD21-Xplained-ADC-Demo-Using-DMA
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SAMD21-Xplained-ADC-Demo-Us.../D21_ADC_with_DMA/Debug/D21_ADC_with_DMA.lss

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D21_ADC_with_DMA.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 00003960 00000000 00000000 00010000 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .relocate 0000007c 20000000 00003960 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
2 .bss 00000220 20000080 000039e0 0002007c 2**4
ALLOC
3 .stack 00002000 200002a0 00003c00 0002007c 2**0
ALLOC
4 .ARM.attributes 00000028 00000000 00000000 0002007c 2**0
CONTENTS, READONLY
5 .comment 00000059 00000000 00000000 000200a4 2**0
CONTENTS, READONLY
6 .debug_info 0002e296 00000000 00000000 000200fd 2**0
CONTENTS, READONLY, DEBUGGING
7 .debug_abbrev 00004281 00000000 00000000 0004e393 2**0
CONTENTS, READONLY, DEBUGGING
8 .debug_loc 00004e91 00000000 00000000 00052614 2**0
CONTENTS, READONLY, DEBUGGING
9 .debug_aranges 00000548 00000000 00000000 000574a5 2**0
CONTENTS, READONLY, DEBUGGING
10 .debug_ranges 00000610 00000000 00000000 000579ed 2**0
CONTENTS, READONLY, DEBUGGING
11 .debug_macro 0001ca44 00000000 00000000 00057ffd 2**0
CONTENTS, READONLY, DEBUGGING
12 .debug_line 0000e317 00000000 00000000 00074a41 2**0
CONTENTS, READONLY, DEBUGGING
13 .debug_str 00090169 00000000 00000000 00082d58 2**0
CONTENTS, READONLY, DEBUGGING
14 .debug_frame 000014c8 00000000 00000000 00112ec4 2**2
CONTENTS, READONLY, DEBUGGING
Disassembly of section .text:
00000000 <exception_table>:
0: a0 22 00 20 51 1c 00 00 4d 1c 00 00 4d 1c 00 00 .". Q...M...M...
...
2c: 4d 1c 00 00 00 00 00 00 00 00 00 00 4d 1c 00 00 M...........M...
3c: 4d 1c 00 00 4d 1c 00 00 4d 1c 00 00 4d 1c 00 00 M...M...M...M...
4c: 4d 1c 00 00 4d 1c 00 00 4d 1c 00 00 4d 05 00 00 M...M...M...M...
5c: 4d 1c 00 00 4d 1c 00 00 15 15 00 00 25 15 00 00 M...M.......%...
6c: 35 15 00 00 45 15 00 00 55 15 00 00 65 15 00 00 5...E...U...e...
7c: 4d 1c 00 00 4d 1c 00 00 4d 1c 00 00 4d 1c 00 00 M...M...M...M...
8c: 4d 1c 00 00 4d 1c 00 00 4d 1c 00 00 4d 1c 00 00 M...M...M...M...
9c: 4d 1c 00 00 4d 1c 00 00 4d 1c 00 00 4d 1c 00 00 M...M...M...M...
ac: 4d 1c 00 00 00 00 00 00 M.......
000000b4 <__do_global_dtors_aux>:
b4: b510 push {r4, lr}
b6: 4c06 ldr r4, [pc, #24] ; (d0 <__do_global_dtors_aux+0x1c>)
b8: 7823 ldrb r3, [r4, #0]
ba: 2b00 cmp r3, #0
bc: d107 bne.n ce <__do_global_dtors_aux+0x1a>
be: 4b05 ldr r3, [pc, #20] ; (d4 <__do_global_dtors_aux+0x20>)
c0: 2b00 cmp r3, #0
c2: d002 beq.n ca <__do_global_dtors_aux+0x16>
c4: 4804 ldr r0, [pc, #16] ; (d8 <__do_global_dtors_aux+0x24>)
c6: e000 b.n ca <__do_global_dtors_aux+0x16>
c8: bf00 nop
ca: 2301 movs r3, #1
cc: 7023 strb r3, [r4, #0]
ce: bd10 pop {r4, pc}
d0: 20000080 .word 0x20000080
d4: 00000000 .word 0x00000000
d8: 00003960 .word 0x00003960
000000dc <frame_dummy>:
dc: 4b08 ldr r3, [pc, #32] ; (100 <frame_dummy+0x24>)
de: b510 push {r4, lr}
e0: 2b00 cmp r3, #0
e2: d003 beq.n ec <frame_dummy+0x10>
e4: 4907 ldr r1, [pc, #28] ; (104 <frame_dummy+0x28>)
e6: 4808 ldr r0, [pc, #32] ; (108 <frame_dummy+0x2c>)
e8: e000 b.n ec <frame_dummy+0x10>
ea: bf00 nop
ec: 4807 ldr r0, [pc, #28] ; (10c <frame_dummy+0x30>)
ee: 6803 ldr r3, [r0, #0]
f0: 2b00 cmp r3, #0
f2: d100 bne.n f6 <frame_dummy+0x1a>
f4: bd10 pop {r4, pc}
f6: 4b06 ldr r3, [pc, #24] ; (110 <frame_dummy+0x34>)
f8: 2b00 cmp r3, #0
fa: d0fb beq.n f4 <frame_dummy+0x18>
fc: 4798 blx r3
fe: e7f9 b.n f4 <frame_dummy+0x18>
100: 00000000 .word 0x00000000
104: 20000084 .word 0x20000084
108: 00003960 .word 0x00003960
10c: 00003960 .word 0x00003960
110: 00000000 .word 0x00000000
00000114 <adc_get_config_defaults>:
*
* \param[out] config Pointer to configuration struct to initialize to
* default values
*/
void adc_get_config_defaults(struct adc_config *const config)
{
114: b510 push {r4, lr}
Assert(config);
config->clock_source = GCLK_GENERATOR_0;
116: 2200 movs r2, #0
118: 2300 movs r3, #0
11a: 7002 strb r2, [r0, #0]
config->reference = ADC_REFERENCE_INT1V;
11c: 7042 strb r2, [r0, #1]
config->clock_prescaler = ADC_CLOCK_PRESCALER_DIV4;
11e: 2100 movs r1, #0
120: 8042 strh r2, [r0, #2]
config->resolution = ADC_RESOLUTION_12BIT;
122: 7101 strb r1, [r0, #4]
config->window.window_mode = ADC_WINDOW_MODE_DISABLE;
124: 7603 strb r3, [r0, #24]
config->window.window_upper_value = 0;
126: 6202 str r2, [r0, #32]
config->window.window_lower_value = 0;
128: 61c2 str r2, [r0, #28]
config->gain_factor = ADC_GAIN_FACTOR_1X;
12a: 6082 str r2, [r0, #8]
#if SAMR21
config->positive_input = ADC_POSITIVE_INPUT_PIN6 ;
#else
config->positive_input = ADC_POSITIVE_INPUT_PIN0 ;
12c: 7303 strb r3, [r0, #12]
#endif
config->negative_input = ADC_NEGATIVE_INPUT_GND ;
12e: 24c0 movs r4, #192 ; 0xc0
130: 0164 lsls r4, r4, #5
132: 81c4 strh r4, [r0, #14]
config->accumulate_samples = ADC_ACCUMULATE_DISABLE;
134: 7403 strb r3, [r0, #16]
config->divide_result = ADC_DIVIDE_RESULT_DISABLE;
136: 7443 strb r3, [r0, #17]
config->left_adjust = false;
138: 7483 strb r3, [r0, #18]
config->differential_mode = false;
13a: 74c3 strb r3, [r0, #19]
config->freerunning = false;
13c: 7503 strb r3, [r0, #20]
config->event_action = ADC_EVENT_ACTION_DISABLED;
13e: 242a movs r4, #42 ; 0x2a
140: 5503 strb r3, [r0, r4]
config->run_in_standby = false;
142: 7543 strb r3, [r0, #21]
config->reference_compensation_enable = false;
144: 7583 strb r3, [r0, #22]
config->correction.correction_enable = false;
146: 3c06 subs r4, #6
148: 5503 strb r3, [r0, r4]
config->correction.gain_correction = ADC_GAINCORR_RESETVALUE;
14a: 84c2 strh r2, [r0, #38] ; 0x26
config->correction.offset_correction = ADC_OFFSETCORR_RESETVALUE;
14c: 8502 strh r2, [r0, #40] ; 0x28
config->sample_length = 0;
14e: 75c1 strb r1, [r0, #23]
config->pin_scan.offset_start_scan = 0;
150: 232b movs r3, #43 ; 0x2b
152: 54c1 strb r1, [r0, r3]
config->pin_scan.inputs_to_scan = 0;
154: 3301 adds r3, #1
156: 54c1 strb r1, [r0, r3]
}
158: bd10 pop {r4, pc}
...
0000015c <adc_init>:
*/
enum status_code adc_init(
struct adc_module *const module_inst,
Adc *hw,
struct adc_config *config)
{
15c: b5f0 push {r4, r5, r6, r7, lr}
15e: 46d6 mov lr, sl
160: 464f mov r7, r9
162: 4646 mov r6, r8
164: b5c0 push {r6, r7, lr}
166: b096 sub sp, #88 ; 0x58
168: 0007 movs r7, r0
16a: 0016 movs r6, r2
Assert(module_inst);
Assert(hw);
Assert(config);
/* Associate the software module instance with the hardware module */
module_inst->hw = hw;
16c: 6001 str r1, [r0, #0]
case SYSTEM_CLOCK_APB_APBB:
PM->APBBMASK.reg |= mask;
break;
case SYSTEM_CLOCK_APB_APBC:
PM->APBCMASK.reg |= mask;
16e: 4acb ldr r2, [pc, #812] ; (49c <adc_init+0x340>)
170: 6a10 ldr r0, [r2, #32]
172: 2380 movs r3, #128 ; 0x80
174: 025b lsls r3, r3, #9
176: 4303 orrs r3, r0
178: 6213 str r3, [r2, #32]
/* Turn on the digital interface clock */
system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_ADC);
if (hw->CTRLA.reg & ADC_CTRLA_SWRST) {
17a: 780b ldrb r3, [r1, #0]
/* We are in the middle of a reset. Abort. */
return STATUS_BUSY;
17c: 2005 movs r0, #5
if (hw->CTRLA.reg & ADC_CTRLA_SWRST) {
17e: 07db lsls r3, r3, #31
180: d505 bpl.n 18e <adc_init+0x32>
}
#endif
/* Write configuration to module */
return _adc_set_config(module_inst, config);
}
182: b016 add sp, #88 ; 0x58
184: bc1c pop {r2, r3, r4}
186: 4690 mov r8, r2
188: 4699 mov r9, r3
18a: 46a2 mov sl, r4
18c: bdf0 pop {r4, r5, r6, r7, pc}
if (hw->CTRLA.reg & ADC_CTRLA_ENABLE) {
18e: 780b ldrb r3, [r1, #0]
return STATUS_ERR_DENIED;
190: 3017 adds r0, #23
if (hw->CTRLA.reg & ADC_CTRLA_ENABLE) {
192: 079b lsls r3, r3, #30
194: d4f5 bmi.n 182 <adc_init+0x26>
module_inst->reference = config->reference;
196: 7873 ldrb r3, [r6, #1]
198: 713b strb r3, [r7, #4]
if (module_inst->reference == ADC_REFERENCE_INT1V) {
19a: 2b00 cmp r3, #0
19c: d104 bne.n 1a8 <adc_init+0x4c>
case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
SYSCTRL->VREF.reg |= SYSCTRL_VREF_TSEN;
break;
case SYSTEM_VOLTAGE_REFERENCE_BANDGAP:
SYSCTRL->VREF.reg |= SYSCTRL_VREF_BGOUTEN;
19e: 4ac0 ldr r2, [pc, #768] ; (4a0 <adc_init+0x344>)
1a0: 6c13 ldr r3, [r2, #64] ; 0x40
1a2: 2104 movs r1, #4
1a4: 430b orrs r3, r1
1a6: 6413 str r3, [r2, #64] ; 0x40
Adc *const adc_module = module_inst->hw;
1a8: 683b ldr r3, [r7, #0]
1aa: 4698 mov r8, r3
gclk_chan_conf.source_generator = config->clock_source;
1ac: 7833 ldrb r3, [r6, #0]
1ae: 466a mov r2, sp
1b0: 7013 strb r3, [r2, #0]
system_gclk_chan_set_config(ADC_GCLK_ID, &gclk_chan_conf);
1b2: 4669 mov r1, sp
1b4: 201e movs r0, #30
1b6: 4bbb ldr r3, [pc, #748] ; (4a4 <adc_init+0x348>)
1b8: 4798 blx r3
system_gclk_chan_enable(ADC_GCLK_ID);
1ba: 201e movs r0, #30
1bc: 4bba ldr r3, [pc, #744] ; (4a8 <adc_init+0x34c>)
1be: 4798 blx r3
if (config->pin_scan.inputs_to_scan != 0) {
1c0: 232c movs r3, #44 ; 0x2c
1c2: 5cf2 ldrb r2, [r6, r3]
1c4: 2a00 cmp r2, #0
1c6: d054 beq.n 272 <adc_init+0x116>
uint8_t offset = config->pin_scan.offset_start_scan;
1c8: 3b01 subs r3, #1
1ca: 5cf5 ldrb r5, [r6, r3]
uint8_t start_pin =
1cc: 7b33 ldrb r3, [r6, #12]
1ce: 18eb adds r3, r5, r3
1d0: b2db uxtb r3, r3
uint8_t end_pin =
1d2: 18d1 adds r1, r2, r3
while (start_pin < end_pin) {
1d4: b2c9 uxtb r1, r1
1d6: 428b cmp r3, r1
1d8: d221 bcs.n 21e <adc_init+0xc2>
1da: 1952 adds r2, r2, r5
1dc: b2d3 uxtb r3, r2
1de: 4699 mov r9, r3
const uint32_t pinmapping[] = {
1e0: 4bb2 ldr r3, [pc, #712] ; (4ac <adc_init+0x350>)
1e2: 469a mov sl, r3
1e4: e003 b.n 1ee <adc_init+0x92>
offset++;
1e6: 3501 adds r5, #1
1e8: b2ed uxtb r5, r5
while (start_pin < end_pin) {
1ea: 45a9 cmp r9, r5
1ec: d017 beq.n 21e <adc_init+0xc2>
_adc_configure_ain_pin((offset % 16)+(uint8_t)config->positive_input);
1ee: 240f movs r4, #15
1f0: 402c ands r4, r5
1f2: 7b33 ldrb r3, [r6, #12]
1f4: 18e4 adds r4, r4, r3
const uint32_t pinmapping[] = {
1f6: 2250 movs r2, #80 ; 0x50
1f8: 49ad ldr r1, [pc, #692] ; (4b0 <adc_init+0x354>)
1fa: a802 add r0, sp, #8
1fc: 47d0 blx sl
if (pin <= ADC_EXTCHANNEL_MSB) {
1fe: 2c13 cmp r4, #19
200: d8f1 bhi.n 1e6 <adc_init+0x8a>
pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos];
202: 00a4 lsls r4, r4, #2
204: ab02 add r3, sp, #8
206: 58e0 ldr r0, [r4, r3]
/* Sanity check arguments */
Assert(config);
/* Default configuration values */
config->mux_position = SYSTEM_PINMUX_GPIO;
config->direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
208: a901 add r1, sp, #4
20a: 2300 movs r3, #0
20c: 704b strb r3, [r1, #1]
config->input_pull = SYSTEM_PINMUX_PIN_PULL_UP;
config->powersave = false;
20e: 70cb strb r3, [r1, #3]
config.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE;
210: 708b strb r3, [r1, #2]
config.mux_position = 1;
212: 3301 adds r3, #1
214: 700b strb r3, [r1, #0]
system_pinmux_pin_set_config(pin_map_result, &config);
216: b2c0 uxtb r0, r0
218: 4ba6 ldr r3, [pc, #664] ; (4b4 <adc_init+0x358>)
21a: 4798 blx r3
21c: e7e3 b.n 1e6 <adc_init+0x8a>
_adc_configure_ain_pin(config->negative_input);
21e: 89f4 ldrh r4, [r6, #14]
const uint32_t pinmapping[] = {
220: 2250 movs r2, #80 ; 0x50
222: 49a3 ldr r1, [pc, #652] ; (4b0 <adc_init+0x354>)
224: a802 add r0, sp, #8
226: 4ba1 ldr r3, [pc, #644] ; (4ac <adc_init+0x350>)
228: 4798 blx r3
if (pin <= ADC_EXTCHANNEL_MSB) {
22a: 2c13 cmp r4, #19
22c: d913 bls.n 256 <adc_init+0xfa>
adc_module->CTRLA.reg = (config->run_in_standby << ADC_CTRLA_RUNSTDBY_Pos);
22e: 7d73 ldrb r3, [r6, #21]
230: 009b lsls r3, r3, #2
232: b2db uxtb r3, r3
234: 4642 mov r2, r8
236: 7013 strb r3, [r2, #0]
(config->reference_compensation_enable << ADC_REFCTRL_REFCOMP_Pos) |
238: 7db3 ldrb r3, [r6, #22]
23a: 01db lsls r3, r3, #7
23c: 7872 ldrb r2, [r6, #1]
23e: 4313 orrs r3, r2
240: b2db uxtb r3, r3
adc_module->REFCTRL.reg =
242: 4642 mov r2, r8
244: 7053 strb r3, [r2, #1]
switch (config->resolution) {
246: 7933 ldrb r3, [r6, #4]
248: 2b34 cmp r3, #52 ; 0x34
24a: d900 bls.n 24e <adc_init+0xf2>
24c: e178 b.n 540 <adc_init+0x3e4>
24e: 009b lsls r3, r3, #2
250: 4a99 ldr r2, [pc, #612] ; (4b8 <adc_init+0x35c>)
252: 58d3 ldr r3, [r2, r3]
254: 469f mov pc, r3
pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos];
256: 00a4 lsls r4, r4, #2
258: ab02 add r3, sp, #8
25a: 58e0 ldr r0, [r4, r3]
config->direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
25c: a901 add r1, sp, #4
25e: 2300 movs r3, #0
260: 704b strb r3, [r1, #1]
config->powersave = false;
262: 70cb strb r3, [r1, #3]
config.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE;
264: 708b strb r3, [r1, #2]
config.mux_position = 1;
266: 3301 adds r3, #1
268: 700b strb r3, [r1, #0]
system_pinmux_pin_set_config(pin_map_result, &config);
26a: b2c0 uxtb r0, r0
26c: 4b91 ldr r3, [pc, #580] ; (4b4 <adc_init+0x358>)
26e: 4798 blx r3
270: e7dd b.n 22e <adc_init+0xd2>
_adc_configure_ain_pin(config->positive_input);
272: 7b34 ldrb r4, [r6, #12]
const uint32_t pinmapping[] = {
274: 2250 movs r2, #80 ; 0x50
276: 498e ldr r1, [pc, #568] ; (4b0 <adc_init+0x354>)
278: a802 add r0, sp, #8
27a: 4b8c ldr r3, [pc, #560] ; (4ac <adc_init+0x350>)
27c: 4798 blx r3
if (pin <= ADC_EXTCHANNEL_MSB) {
27e: 2c13 cmp r4, #19
280: d915 bls.n 2ae <adc_init+0x152>
_adc_configure_ain_pin(config->negative_input);
282: 89f4 ldrh r4, [r6, #14]
const uint32_t pinmapping[] = {
284: 2250 movs r2, #80 ; 0x50
286: 498a ldr r1, [pc, #552] ; (4b0 <adc_init+0x354>)
288: a802 add r0, sp, #8
28a: 4b88 ldr r3, [pc, #544] ; (4ac <adc_init+0x350>)
28c: 4798 blx r3
if (pin <= ADC_EXTCHANNEL_MSB) {
28e: 2c13 cmp r4, #19
290: d8cd bhi.n 22e <adc_init+0xd2>
pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos];
292: 00a4 lsls r4, r4, #2
294: ab02 add r3, sp, #8
296: 58e0 ldr r0, [r4, r3]
config->direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
298: a901 add r1, sp, #4
29a: 2300 movs r3, #0
29c: 704b strb r3, [r1, #1]
config->powersave = false;
29e: 70cb strb r3, [r1, #3]
config.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE;
2a0: 708b strb r3, [r1, #2]
config.mux_position = 1;
2a2: 3301 adds r3, #1
2a4: 700b strb r3, [r1, #0]
system_pinmux_pin_set_config(pin_map_result, &config);
2a6: b2c0 uxtb r0, r0
2a8: 4b82 ldr r3, [pc, #520] ; (4b4 <adc_init+0x358>)
2aa: 4798 blx r3
2ac: e7bf b.n 22e <adc_init+0xd2>
pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos];
2ae: 00a4 lsls r4, r4, #2
2b0: ab02 add r3, sp, #8
2b2: 58e0 ldr r0, [r4, r3]
config->direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
2b4: a901 add r1, sp, #4
2b6: 2300 movs r3, #0
2b8: 704b strb r3, [r1, #1]
config->powersave = false;
2ba: 70cb strb r3, [r1, #3]
config.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE;
2bc: 708b strb r3, [r1, #2]
config.mux_position = 1;
2be: 3301 adds r3, #1
2c0: 700b strb r3, [r1, #0]
system_pinmux_pin_set_config(pin_map_result, &config);
2c2: b2c0 uxtb r0, r0
2c4: 4b7b ldr r3, [pc, #492] ; (4b4 <adc_init+0x358>)
2c6: 4798 blx r3
2c8: e7db b.n 282 <adc_init+0x126>
accumulate = ADC_ACCUMULATE_SAMPLES_16;
2ca: 2304 movs r3, #4
resolution = ADC_RESOLUTION_16BIT;
2cc: 2410 movs r4, #16
adjres = ADC_DIVIDE_RESULT_4;
2ce: 2102 movs r1, #2
2d0: e01a b.n 308 <adc_init+0x1ac>
adjres = config->divide_result;
2d2: 7c71 ldrb r1, [r6, #17]
accumulate = config->accumulate_samples;
2d4: 7c33 ldrb r3, [r6, #16]
resolution = ADC_RESOLUTION_16BIT;
2d6: 2410 movs r4, #16
2d8: e016 b.n 308 <adc_init+0x1ac>
accumulate = ADC_ACCUMULATE_SAMPLES_64;
2da: 2306 movs r3, #6
resolution = ADC_RESOLUTION_16BIT;
2dc: 2410 movs r4, #16
adjres = ADC_DIVIDE_RESULT_2;
2de: 2101 movs r1, #1
2e0: e012 b.n 308 <adc_init+0x1ac>
accumulate = ADC_ACCUMULATE_SAMPLES_256;
2e2: 2308 movs r3, #8
resolution = ADC_RESOLUTION_16BIT;
2e4: 2410 movs r4, #16
adjres = ADC_DIVIDE_RESULT_DISABLE;
2e6: 2100 movs r1, #0
2e8: e00e b.n 308 <adc_init+0x1ac>
enum adc_accumulate_samples accumulate = ADC_ACCUMULATE_DISABLE;
2ea: 2300 movs r3, #0
resolution = ADC_RESOLUTION_8BIT;
2ec: 2430 movs r4, #48 ; 0x30
uint8_t adjres = 0;
2ee: 2100 movs r1, #0
2f0: e00a b.n 308 <adc_init+0x1ac>
enum adc_accumulate_samples accumulate = ADC_ACCUMULATE_DISABLE;
2f2: 2300 movs r3, #0
resolution = ADC_RESOLUTION_10BIT;
2f4: 2420 movs r4, #32
uint8_t adjres = 0;
2f6: 2100 movs r1, #0
2f8: e006 b.n 308 <adc_init+0x1ac>
enum adc_accumulate_samples accumulate = ADC_ACCUMULATE_DISABLE;
2fa: 2300 movs r3, #0
resolution = ADC_RESOLUTION_12BIT;
2fc: 2400 movs r4, #0
uint8_t adjres = 0;
2fe: 2100 movs r1, #0
300: e002 b.n 308 <adc_init+0x1ac>
accumulate = ADC_ACCUMULATE_SAMPLES_4;
302: 2302 movs r3, #2
resolution = ADC_RESOLUTION_16BIT;
304: 2410 movs r4, #16
adjres = ADC_DIVIDE_RESULT_2;
306: 2101 movs r1, #1
adc_module->AVGCTRL.reg = ADC_AVGCTRL_ADJRES(adjres) | accumulate;
308: 0109 lsls r1, r1, #4
30a: 2270 movs r2, #112 ; 0x70
30c: 400a ands r2, r1
30e: 4313 orrs r3, r2
310: 4642 mov r2, r8
312: 7093 strb r3, [r2, #2]
if (config->sample_length > 63) {
314: 7df3 ldrb r3, [r6, #23]
return STATUS_ERR_INVALID_ARG;
316: 2017 movs r0, #23
if (config->sample_length > 63) {
318: 2b3f cmp r3, #63 ; 0x3f
31a: d900 bls.n 31e <adc_init+0x1c2>
31c: e731 b.n 182 <adc_init+0x26>
adc_module->SAMPCTRL.reg =
31e: 70d3 strb r3, [r2, #3]
struct adc_module *const module_inst)
{
/* Sanity check arguments */
Assert(module_inst);
Adc *const adc_module = module_inst->hw;
320: 683a ldr r2, [r7, #0]
if (adc_module->STATUS.reg & ADC_STATUS_SYNCBUSY) {
322: 7e53 ldrb r3, [r2, #25]
while (adc_is_syncing(module_inst)) {
324: b25b sxtb r3, r3
326: 2b00 cmp r3, #0
328: dbfb blt.n 322 <adc_init+0x1c6>
(config->differential_mode << ADC_CTRLB_DIFFMODE_Pos);
32a: 7cf3 ldrb r3, [r6, #19]
(config->left_adjust << ADC_CTRLB_LEFTADJ_Pos) |
32c: 8872 ldrh r2, [r6, #2]
32e: 4313 orrs r3, r2
(config->correction.correction_enable << ADC_CTRLB_CORREN_Pos) |
330: 2224 movs r2, #36 ; 0x24
332: 5cb2 ldrb r2, [r6, r2]
334: 00d2 lsls r2, r2, #3
(config->left_adjust << ADC_CTRLB_LEFTADJ_Pos) |
336: 4313 orrs r3, r2
(config->freerunning << ADC_CTRLB_FREERUN_Pos) |
338: 7d32 ldrb r2, [r6, #20]
33a: 0092 lsls r2, r2, #2
(config->left_adjust << ADC_CTRLB_LEFTADJ_Pos) |
33c: 4313 orrs r3, r2
33e: 7cb2 ldrb r2, [r6, #18]
340: 0052 lsls r2, r2, #1
342: 4313 orrs r3, r2
344: 4323 orrs r3, r4
adc_module->CTRLB.reg =
346: 4642 mov r2, r8
348: 8093 strh r3, [r2, #4]
if (config->window.window_mode != ADC_WINDOW_MODE_DISABLE) {
34a: 7e33 ldrb r3, [r6, #24]
34c: 2b00 cmp r3, #0
34e: d020 beq.n 392 <adc_init+0x236>
switch (resolution) {
350: 2c10 cmp r4, #16
352: d100 bne.n 356 <adc_init+0x1fa>
354: e0d6 b.n 504 <adc_init+0x3a8>
356: d800 bhi.n 35a <adc_init+0x1fe>
358: e080 b.n 45c <adc_init+0x300>
35a: 2c20 cmp r4, #32
35c: d100 bne.n 360 <adc_init+0x204>
35e: e0b3 b.n 4c8 <adc_init+0x36c>
360: 2c30 cmp r4, #48 ; 0x30
362: d116 bne.n 392 <adc_init+0x236>
if (config->differential_mode &&
364: 7cf2 ldrb r2, [r6, #19]
366: 2a00 cmp r2, #0
368: d00a beq.n 380 <adc_init+0x224>
(config->window.window_lower_value > 127 ||
36a: 69f2 ldr r2, [r6, #28]
36c: 3280 adds r2, #128 ; 0x80
return STATUS_ERR_INVALID_ARG;
36e: 2017 movs r0, #23
if (config->differential_mode &&
370: 2aff cmp r2, #255 ; 0xff
372: d900 bls.n 376 <adc_init+0x21a>
374: e705 b.n 182 <adc_init+0x26>
config->window.window_lower_value < -128 ||
376: 6a32 ldr r2, [r6, #32]
378: 3280 adds r2, #128 ; 0x80
37a: 2aff cmp r2, #255 ; 0xff
37c: d900 bls.n 380 <adc_init+0x224>
37e: e700 b.n 182 <adc_init+0x26>
return STATUS_ERR_INVALID_ARG;
380: 2017 movs r0, #23
} else if (config->window.window_lower_value > 255 ||
382: 69f2 ldr r2, [r6, #28]
384: 2aff cmp r2, #255 ; 0xff
386: dd00 ble.n 38a <adc_init+0x22e>
388: e6fb b.n 182 <adc_init+0x26>
38a: 6a32 ldr r2, [r6, #32]
38c: 2aff cmp r2, #255 ; 0xff
38e: dd00 ble.n 392 <adc_init+0x236>
390: e6f7 b.n 182 <adc_init+0x26>
Adc *const adc_module = module_inst->hw;
392: 6839 ldr r1, [r7, #0]
if (adc_module->STATUS.reg & ADC_STATUS_SYNCBUSY) {
394: 7e4a ldrb r2, [r1, #25]
while (adc_is_syncing(module_inst)) {
396: b252 sxtb r2, r2
398: 2a00 cmp r2, #0
39a: dbfb blt.n 394 <adc_init+0x238>
adc_module->WINCTRL.reg = config->window.window_mode;
39c: 4642 mov r2, r8
39e: 7213 strb r3, [r2, #8]
Adc *const adc_module = module_inst->hw;
3a0: 683a ldr r2, [r7, #0]
if (adc_module->STATUS.reg & ADC_STATUS_SYNCBUSY) {
3a2: 7e53 ldrb r3, [r2, #25]
while (adc_is_syncing(module_inst)) {
3a4: b25b sxtb r3, r3
3a6: 2b00 cmp r3, #0
3a8: dbfb blt.n 3a2 <adc_init+0x246>
adc_module->WINLT.reg =
3aa: 8bb3 ldrh r3, [r6, #28]
3ac: 4642 mov r2, r8
3ae: 8393 strh r3, [r2, #28]
Adc *const adc_module = module_inst->hw;
3b0: 683a ldr r2, [r7, #0]
if (adc_module->STATUS.reg & ADC_STATUS_SYNCBUSY) {
3b2: 7e53 ldrb r3, [r2, #25]
while (adc_is_syncing(module_inst)) {
3b4: b25b sxtb r3, r3
3b6: 2b00 cmp r3, #0
3b8: dbfb blt.n 3b2 <adc_init+0x256>
adc_module->WINUT.reg = config->window.window_upper_value <<
3ba: 8c33 ldrh r3, [r6, #32]
3bc: 4642 mov r2, r8
3be: 8413 strh r3, [r2, #32]
uint8_t inputs_to_scan = config->pin_scan.inputs_to_scan;
3c0: 232c movs r3, #44 ; 0x2c
3c2: 5cf3 ldrb r3, [r6, r3]
if (inputs_to_scan > 0) {
3c4: 2b00 cmp r3, #0
3c6: d005 beq.n 3d4 <adc_init+0x278>
inputs_to_scan--;
3c8: 3b01 subs r3, #1
3ca: b2db uxtb r3, r3
return STATUS_ERR_INVALID_ARG;
3cc: 2017 movs r0, #23
if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) ||
3ce: 2b0f cmp r3, #15
3d0: d900 bls.n 3d4 <adc_init+0x278>
3d2: e6d6 b.n 182 <adc_init+0x26>
config->pin_scan.offset_start_scan > (ADC_INPUTCTRL_INPUTOFFSET_Msk >> ADC_INPUTCTRL_INPUTOFFSET_Pos)) {
3d4: 222b movs r2, #43 ; 0x2b
3d6: 5cb1 ldrb r1, [r6, r2]
return STATUS_ERR_INVALID_ARG;
3d8: 2017 movs r0, #23
if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) ||
3da: 290f cmp r1, #15
3dc: d900 bls.n 3e0 <adc_init+0x284>
3de: e6d0 b.n 182 <adc_init+0x26>
Adc *const adc_module = module_inst->hw;
3e0: 6838 ldr r0, [r7, #0]
if (adc_module->STATUS.reg & ADC_STATUS_SYNCBUSY) {
3e2: 7e42 ldrb r2, [r0, #25]
while (adc_is_syncing(module_inst)) {
3e4: b252 sxtb r2, r2
3e6: 2a00 cmp r2, #0
3e8: dbfb blt.n 3e2 <adc_init+0x286>
config->negative_input |
3ea: 89f2 ldrh r2, [r6, #14]
config->positive_input;
3ec: 7b30 ldrb r0, [r6, #12]
config->negative_input |
3ee: 4302 orrs r2, r0
3f0: 68b0 ldr r0, [r6, #8]
3f2: 4302 orrs r2, r0
(config->pin_scan.offset_start_scan <<
3f4: 0509 lsls r1, r1, #20
config->negative_input |
3f6: 430a orrs r2, r1
(inputs_to_scan << ADC_INPUTCTRL_INPUTSCAN_Pos) |
3f8: 041b lsls r3, r3, #16
config->negative_input |
3fa: 4313 orrs r3, r2
adc_module->INPUTCTRL.reg =
3fc: 4642 mov r2, r8
3fe: 6113 str r3, [r2, #16]
adc_module->EVCTRL.reg = config->event_action;
400: 232a movs r3, #42 ; 0x2a
402: 5cf3 ldrb r3, [r6, r3]
404: 7513 strb r3, [r2, #20]
adc_module->INTENCLR.reg =
406: 230f movs r3, #15
408: 7593 strb r3, [r2, #22]
if (config->correction.correction_enable){
40a: 3315 adds r3, #21
40c: 5cf3 ldrb r3, [r6, r3]
40e: 2b00 cmp r3, #0
410: d012 beq.n 438 <adc_init+0x2dc>
if (config->correction.gain_correction > ADC_GAINCORR_GAINCORR_Msk) {
412: 8cf3 ldrh r3, [r6, #38] ; 0x26
414: 4a29 ldr r2, [pc, #164] ; (4bc <adc_init+0x360>)
return STATUS_ERR_INVALID_ARG;
416: 2017 movs r0, #23
if (config->correction.gain_correction > ADC_GAINCORR_GAINCORR_Msk) {
418: 4293 cmp r3, r2
41a: d900 bls.n 41e <adc_init+0x2c2>
41c: e6b1 b.n 182 <adc_init+0x26>
adc_module->GAINCORR.reg = config->correction.gain_correction <<
41e: 4642 mov r2, r8
420: 8493 strh r3, [r2, #36] ; 0x24
if (config->correction.offset_correction > 2047 ||
422: 8d32 ldrh r2, [r6, #40] ; 0x28
424: 2380 movs r3, #128 ; 0x80
426: 011b lsls r3, r3, #4
428: 18d3 adds r3, r2, r3
42a: 4924 ldr r1, [pc, #144] ; (4bc <adc_init+0x360>)
42c: b29b uxth r3, r3
42e: 428b cmp r3, r1
430: d900 bls.n 434 <adc_init+0x2d8>
432: e6a6 b.n 182 <adc_init+0x26>
adc_module->OFFSETCORR.reg = config->correction.offset_correction <<
434: 4643 mov r3, r8
436: 84da strh r2, [r3, #38] ; 0x26
ADC_CALIB_BIAS_CAL(
438: 4b21 ldr r3, [pc, #132] ; (4c0 <adc_init+0x364>)
43a: 681b ldr r3, [r3, #0]
43c: 015b lsls r3, r3, #5
43e: 22e0 movs r2, #224 ; 0xe0
440: 00d2 lsls r2, r2, #3
442: 4013 ands r3, r2
ADC_CALIB_LINEARITY_CAL(
444: 4a1f ldr r2, [pc, #124] ; (4c4 <adc_init+0x368>)
446: 6851 ldr r1, [r2, #4]
448: 0149 lsls r1, r1, #5
44a: 6812 ldr r2, [r2, #0]
44c: 0ed2 lsrs r2, r2, #27
44e: 430a orrs r2, r1
450: b2d2 uxtb r2, r2
) |
452: 4313 orrs r3, r2
adc_module->CALIB.reg =
454: 4642 mov r2, r8
456: 8513 strh r3, [r2, #40] ; 0x28
return STATUS_OK;
458: 2000 movs r0, #0
45a: e692 b.n 182 <adc_init+0x26>
switch (resolution) {
45c: 2c00 cmp r4, #0
45e: d198 bne.n 392 <adc_init+0x236>
if (config->differential_mode &&
460: 7cf2 ldrb r2, [r6, #19]
462: 2a00 cmp r2, #0
464: d00f beq.n 486 <adc_init+0x32a>
(config->window.window_lower_value > 2047 ||
466: 69f2 ldr r2, [r6, #28]
468: 2180 movs r1, #128 ; 0x80
46a: 0109 lsls r1, r1, #4
46c: 468c mov ip, r1
46e: 4462 add r2, ip
if (config->differential_mode &&
470: 4912 ldr r1, [pc, #72] ; (4bc <adc_init+0x360>)
return STATUS_ERR_INVALID_ARG;
472: 2017 movs r0, #23
if (config->differential_mode &&
474: 428a cmp r2, r1
476: d900 bls.n 47a <adc_init+0x31e>
478: e683 b.n 182 <adc_init+0x26>
config->window.window_lower_value < -2048 ||
47a: 6a32 ldr r2, [r6, #32]
47c: 4462 add r2, ip
47e: 490f ldr r1, [pc, #60] ; (4bc <adc_init+0x360>)
480: 428a cmp r2, r1
482: d900 bls.n 486 <adc_init+0x32a>
484: e67d b.n 182 <adc_init+0x26>
} else if (config->window.window_lower_value > 4095 ||
486: 4a0d ldr r2, [pc, #52] ; (4bc <adc_init+0x360>)
return STATUS_ERR_INVALID_ARG;
488: 2017 movs r0, #23
} else if (config->window.window_lower_value > 4095 ||
48a: 69f1 ldr r1, [r6, #28]
48c: 4291 cmp r1, r2
48e: dd00 ble.n 492 <adc_init+0x336>
490: e677 b.n 182 <adc_init+0x26>
492: 6a31 ldr r1, [r6, #32]
494: 4291 cmp r1, r2
496: dd00 ble.n 49a <adc_init+0x33e>
498: e673 b.n 182 <adc_init+0x26>
49a: e77a b.n 392 <adc_init+0x236>
49c: 40000400 .word 0x40000400
4a0: 40000800 .word 0x40000800
4a4: 00001af5 .word 0x00001af5
4a8: 00001a69 .word 0x00001a69
4ac: 000026c9 .word 0x000026c9
4b0: 000037a4 .word 0x000037a4
4b4: 00001bed .word 0x00001bed
4b8: 000036d0 .word 0x000036d0
4bc: 00000fff .word 0x00000fff
4c0: 00806024 .word 0x00806024
4c4: 00806020 .word 0x00806020
if (config->differential_mode &&
4c8: 7cf2 ldrb r2, [r6, #19]
4ca: 2a00 cmp r2, #0
4cc: d00f beq.n 4ee <adc_init+0x392>
(config->window.window_lower_value > 511 ||
4ce: 69f2 ldr r2, [r6, #28]
4d0: 2180 movs r1, #128 ; 0x80
4d2: 0089 lsls r1, r1, #2
4d4: 468c mov ip, r1
4d6: 4462 add r2, ip
if (config->differential_mode &&
4d8: 491a ldr r1, [pc, #104] ; (544 <adc_init+0x3e8>)
return STATUS_ERR_INVALID_ARG;
4da: 2017 movs r0, #23
if (config->differential_mode &&
4dc: 428a cmp r2, r1
4de: d900 bls.n 4e2 <adc_init+0x386>
4e0: e64f b.n 182 <adc_init+0x26>
config->window.window_lower_value < -512 ||
4e2: 6a32 ldr r2, [r6, #32]
4e4: 4462 add r2, ip
4e6: 4917 ldr r1, [pc, #92] ; (544 <adc_init+0x3e8>)
4e8: 428a cmp r2, r1
4ea: d900 bls.n 4ee <adc_init+0x392>
4ec: e649 b.n 182 <adc_init+0x26>
} else if (config->window.window_lower_value > 1023 ||
4ee: 4a15 ldr r2, [pc, #84] ; (544 <adc_init+0x3e8>)
return STATUS_ERR_INVALID_ARG;
4f0: 2017 movs r0, #23
} else if (config->window.window_lower_value > 1023 ||
4f2: 69f1 ldr r1, [r6, #28]
4f4: 4291 cmp r1, r2
4f6: dd00 ble.n 4fa <adc_init+0x39e>
4f8: e643 b.n 182 <adc_init+0x26>
4fa: 6a31 ldr r1, [r6, #32]
4fc: 4291 cmp r1, r2
4fe: dd00 ble.n 502 <adc_init+0x3a6>
500: e63f b.n 182 <adc_init+0x26>
502: e746 b.n 392 <adc_init+0x236>
if (config->differential_mode &&
504: 7cf2 ldrb r2, [r6, #19]
506: 2a00 cmp r2, #0
508: d00f beq.n 52a <adc_init+0x3ce>
(config->window.window_lower_value > 32767 ||
50a: 69f2 ldr r2, [r6, #28]
50c: 2180 movs r1, #128 ; 0x80
50e: 0209 lsls r1, r1, #8
510: 468c mov ip, r1
512: 4462 add r2, ip
if (config->differential_mode &&
514: 490c ldr r1, [pc, #48] ; (548 <adc_init+0x3ec>)
return STATUS_ERR_INVALID_ARG;
516: 2017 movs r0, #23
if (config->differential_mode &&
518: 428a cmp r2, r1
51a: d900 bls.n 51e <adc_init+0x3c2>
51c: e631 b.n 182 <adc_init+0x26>
config->window.window_lower_value < -32768 ||
51e: 6a32 ldr r2, [r6, #32]
520: 4462 add r2, ip
522: 4909 ldr r1, [pc, #36] ; (548 <adc_init+0x3ec>)
524: 428a cmp r2, r1
526: d900 bls.n 52a <adc_init+0x3ce>
528: e62b b.n 182 <adc_init+0x26>
} else if (config->window.window_lower_value > 65535 ||
52a: 4a07 ldr r2, [pc, #28] ; (548 <adc_init+0x3ec>)
return STATUS_ERR_INVALID_ARG;
52c: 2017 movs r0, #23
} else if (config->window.window_lower_value > 65535 ||
52e: 69f1 ldr r1, [r6, #28]
530: 4291 cmp r1, r2
532: dd00 ble.n 536 <adc_init+0x3da>
534: e625 b.n 182 <adc_init+0x26>
536: 6a31 ldr r1, [r6, #32]
538: 4291 cmp r1, r2
53a: dd00 ble.n 53e <adc_init+0x3e2>
53c: e621 b.n 182 <adc_init+0x26>
53e: e728 b.n 392 <adc_init+0x236>
return STATUS_ERR_INVALID_ARG;
540: 2017 movs r0, #23
542: e61e b.n 182 <adc_init+0x26>
544: 000003ff .word 0x000003ff
548: 0000ffff .word 0x0000ffff
0000054c <DMAC_Handler>:
/**
* \brief DMA interrupt service routine.
*
*/
void DMAC_Handler( void )
{
54c: b510 push {r4, lr}
* are only re-enabled upon leaving the outermost nested critical section.
*
*/
static inline void system_interrupt_enter_critical_section(void)
{
cpu_irq_enter_critical();
54e: 4b26 ldr r3, [pc, #152] ; (5e8 <DMAC_Handler+0x9c>)
550: 4798 blx r3
uint32_t total_size;
system_interrupt_enter_critical_section();
/* Get Pending channel */
active_channel = DMAC->INTPEND.reg & DMAC_INTPEND_ID_Msk;
552: 4926 ldr r1, [pc, #152] ; (5ec <DMAC_Handler+0xa0>)
554: 8c0b ldrh r3, [r1, #32]
556: 220f movs r2, #15
Assert(_dma_active_resource[active_channel]);
/* Get active DMA resource based on channel */
resource = _dma_active_resource[active_channel];
558: 4013 ands r3, r2
55a: 009b lsls r3, r3, #2
55c: 4824 ldr r0, [pc, #144] ; (5f0 <DMAC_Handler+0xa4>)
55e: 5818 ldr r0, [r3, r0]
/* Select the active channel */
DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
560: 7803 ldrb r3, [r0, #0]
562: 401a ands r2, r3
564: 233f movs r3, #63 ; 0x3f
566: 54ca strb r2, [r1, r3]
isr = DMAC->CHINTFLAG.reg;
568: 330f adds r3, #15
56a: 5cca ldrb r2, [r1, r3]
56c: b2d2 uxtb r2, r2
/* Calculate block transfer size of the DMA transfer */
total_size = descriptor_section[resource->channel_id].BTCNT.reg;
56e: 7803 ldrb r3, [r0, #0]
570: 011b lsls r3, r3, #4
572: 4920 ldr r1, [pc, #128] ; (5f4 <DMAC_Handler+0xa8>)
574: 18c9 adds r1, r1, r3
576: 8849 ldrh r1, [r1, #2]
write_size = _write_back_section[resource->channel_id].BTCNT.reg;
578: 4c1f ldr r4, [pc, #124] ; (5f8 <DMAC_Handler+0xac>)
57a: 18e3 adds r3, r4, r3
57c: 885b ldrh r3, [r3, #2]
resource->transfered_size = total_size - write_size;
57e: 1acb subs r3, r1, r3
580: 6143 str r3, [r0, #20]
/* DMA channel interrupt handler */
if (isr & DMAC_CHINTENCLR_TERR) {
582: 07d3 lsls r3, r2, #31
584: d50f bpl.n 5a6 <DMAC_Handler+0x5a>
/* Clear transfer error flag */
DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_TERR;
586: 2101 movs r1, #1
588: 234e movs r3, #78 ; 0x4e
58a: 4a18 ldr r2, [pc, #96] ; (5ec <DMAC_Handler+0xa0>)
58c: 54d1 strb r1, [r2, r3]
/* Set I/O ERROR status */
resource->job_status = STATUS_ERR_IO;
58e: 3b3e subs r3, #62 ; 0x3e
590: 7443 strb r3, [r0, #17]
/* Execute the callback function */
if ((resource->callback_enable & (1<<DMA_CALLBACK_TRANSFER_ERROR)) &&
592: 7c03 ldrb r3, [r0, #16]
594: 07db lsls r3, r3, #31
596: d503 bpl.n 5a0 <DMAC_Handler+0x54>
(resource->callback[DMA_CALLBACK_TRANSFER_ERROR])) {
598: 6843 ldr r3, [r0, #4]
if ((resource->callback_enable & (1<<DMA_CALLBACK_TRANSFER_ERROR)) &&
59a: 2b00 cmp r3, #0
59c: d000 beq.n 5a0 <DMAC_Handler+0x54>
resource->callback[DMA_CALLBACK_TRANSFER_ERROR](resource);
59e: 4798 blx r3
* are only re-enabled upon leaving the outermost nested critical section.
*
*/
static inline void system_interrupt_leave_critical_section(void)
{
cpu_irq_leave_critical();
5a0: 4b16 ldr r3, [pc, #88] ; (5fc <DMAC_Handler+0xb0>)
5a2: 4798 blx r3
resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND](resource);
}
}
system_interrupt_leave_critical_section();
}
5a4: bd10 pop {r4, pc}
} else if (isr & DMAC_CHINTENCLR_TCMPL) {
5a6: 0793 lsls r3, r2, #30
5a8: d50d bpl.n 5c6 <DMAC_Handler+0x7a>
DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_TCMPL;
5aa: 2102 movs r1, #2
5ac: 234e movs r3, #78 ; 0x4e
5ae: 4a0f ldr r2, [pc, #60] ; (5ec <DMAC_Handler+0xa0>)
5b0: 54d1 strb r1, [r2, r3]
resource->job_status = STATUS_OK;
5b2: 2300 movs r3, #0
5b4: 7443 strb r3, [r0, #17]
if ((resource->callback_enable & (1 << DMA_CALLBACK_TRANSFER_DONE)) &&
5b6: 7c03 ldrb r3, [r0, #16]
5b8: 079b lsls r3, r3, #30
5ba: d5f1 bpl.n 5a0 <DMAC_Handler+0x54>
(resource->callback[DMA_CALLBACK_TRANSFER_DONE])) {
5bc: 6883 ldr r3, [r0, #8]
if ((resource->callback_enable & (1 << DMA_CALLBACK_TRANSFER_DONE)) &&
5be: 2b00 cmp r3, #0
5c0: d0ee beq.n 5a0 <DMAC_Handler+0x54>
resource->callback[DMA_CALLBACK_TRANSFER_DONE](resource);
5c2: 4798 blx r3
5c4: e7ec b.n 5a0 <DMAC_Handler+0x54>
} else if (isr & DMAC_CHINTENCLR_SUSP) {
5c6: 0753 lsls r3, r2, #29
5c8: d5ea bpl.n 5a0 <DMAC_Handler+0x54>
DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_SUSP;
5ca: 2104 movs r1, #4
5cc: 234e movs r3, #78 ; 0x4e
5ce: 4a07 ldr r2, [pc, #28] ; (5ec <DMAC_Handler+0xa0>)
5d0: 54d1 strb r1, [r2, r3]
resource->job_status = STATUS_SUSPEND;
5d2: 3b48 subs r3, #72 ; 0x48
5d4: 7443 strb r3, [r0, #17]
if ((resource->callback_enable & (1 << DMA_CALLBACK_CHANNEL_SUSPEND)) &&
5d6: 7c03 ldrb r3, [r0, #16]
5d8: 075b lsls r3, r3, #29
5da: d5e1 bpl.n 5a0 <DMAC_Handler+0x54>
(resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND])){
5dc: 68c3 ldr r3, [r0, #12]
if ((resource->callback_enable & (1 << DMA_CALLBACK_CHANNEL_SUSPEND)) &&
5de: 2b00 cmp r3, #0
5e0: d0de beq.n 5a0 <DMAC_Handler+0x54>
resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND](resource);
5e2: 4798 blx r3
5e4: e7dc b.n 5a0 <DMAC_Handler+0x54>
5e6: 46c0 nop ; (mov r8, r8)
5e8: 000015e1 .word 0x000015e1
5ec: 41004800 .word 0x41004800
5f0: 2000009c .word 0x2000009c
5f4: 200001e0 .word 0x200001e0
5f8: 200000b0 .word 0x200000b0
5fc: 00001621 .word 0x00001621
00000600 <dma_get_config_defaults>:
*/
void dma_get_config_defaults(struct dma_resource_config *config)
{
Assert(config);
/* Set as priority 0 */
config->priority = DMA_PRIORITY_LEVEL_0;
600: 2300 movs r3, #0
602: 7003 strb r3, [r0, #0]
/* Only software/event trigger */
config->peripheral_trigger = 0;
604: 7043 strb r3, [r0, #1]
/* Transaction trigger */
config->trigger_action = DMA_TRIGGER_ACTION_TRANSACTION;
606: 2203 movs r2, #3
608: 7082 strb r2, [r0, #2]
/* Event configurations, no event input/output */
config->event_config.input_action = DMA_EVENT_INPUT_NOACT;
60a: 70c3 strb r3, [r0, #3]
config->event_config.event_output_enable = false;
60c: 7103 strb r3, [r0, #4]
#ifdef FEATURE_DMA_CHANNEL_STANDBY
config->run_in_standby = false;
#endif
}
60e: 4770 bx lr
00000610 <dma_allocate>:
* \retval STATUS_OK The DMA resource was allocated successfully
* \retval STATUS_ERR_NOT_FOUND DMA resource allocation failed
*/
enum status_code dma_allocate(struct dma_resource *resource,
struct dma_resource_config *config)
{
610: b5f8 push {r3, r4, r5, r6, r7, lr}
612: 46ce mov lr, r9
614: 4647 mov r7, r8
616: b580 push {r7, lr}
618: 0005 movs r5, r0
61a: 000e movs r6, r1
cpu_irq_enter_critical();
61c: 4b45 ldr r3, [pc, #276] ; (734 <dma_allocate+0x124>)
61e: 4798 blx r3
Assert(resource);
system_interrupt_enter_critical_section();
if (!_dma_inst._dma_init) {
620: 4b45 ldr r3, [pc, #276] ; (738 <dma_allocate+0x128>)
622: 781b ldrb r3, [r3, #0]
624: 2b00 cmp r3, #0
626: d118 bne.n 65a <dma_allocate+0x4a>
PM->AHBMASK.reg |= ahb_mask;
628: 4b44 ldr r3, [pc, #272] ; (73c <dma_allocate+0x12c>)
62a: 695a ldr r2, [r3, #20]
62c: 2120 movs r1, #32
62e: 430a orrs r2, r1
630: 615a str r2, [r3, #20]
PM->APBBMASK.reg |= mask;
632: 69da ldr r2, [r3, #28]
634: 3910 subs r1, #16
636: 430a orrs r2, r1
638: 61da str r2, [r3, #28]
system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB,
PM_APBBMASK_DMAC);
#endif
/* Perform a software reset before enable DMA controller */
DMAC->CTRL.reg &= ~DMAC_CTRL_DMAENABLE;
63a: 4b41 ldr r3, [pc, #260] ; (740 <dma_allocate+0x130>)
63c: 881a ldrh r2, [r3, #0]
63e: 390e subs r1, #14
640: 438a bics r2, r1
642: 801a strh r2, [r3, #0]
DMAC->CTRL.reg = DMAC_CTRL_SWRST;
644: 2201 movs r2, #1
646: 801a strh r2, [r3, #0]
/* Setup descriptor base address and write back section base
* address */
DMAC->BASEADDR.reg = (uint32_t)descriptor_section;
648: 4a3e ldr r2, [pc, #248] ; (744 <dma_allocate+0x134>)
64a: 635a str r2, [r3, #52] ; 0x34
DMAC->WRBADDR.reg = (uint32_t)_write_back_section;
64c: 4a3e ldr r2, [pc, #248] ; (748 <dma_allocate+0x138>)
64e: 639a str r2, [r3, #56] ; 0x38
/* Enable all priority level at the same time */
DMAC->CTRL.reg = DMAC_CTRL_DMAENABLE | DMAC_CTRL_LVLEN(0xf);
650: 4a3e ldr r2, [pc, #248] ; (74c <dma_allocate+0x13c>)
652: 801a strh r2, [r3, #0]
_dma_inst._dma_init = true;
654: 4b38 ldr r3, [pc, #224] ; (738 <dma_allocate+0x128>)
656: 2201 movs r2, #1
658: 701a strb r2, [r3, #0]
65a: 4b36 ldr r3, [pc, #216] ; (734 <dma_allocate+0x124>)
65c: 4798 blx r3
tmp = _dma_inst.allocated_channels;
65e: 4b36 ldr r3, [pc, #216] ; (738 <dma_allocate+0x128>)
660: 685b ldr r3, [r3, #4]
if (!(tmp & 0x00000001)) {
662: 07da lsls r2, r3, #31
664: d50f bpl.n 686 <dma_allocate+0x76>
tmp = tmp >> 1;
666: 085b lsrs r3, r3, #1
for (count = 0; count < CONF_MAX_USED_CHANNEL_NUM; ++count) {
668: 2401 movs r4, #1
if (!(tmp & 0x00000001)) {
66a: 2201 movs r2, #1
66c: 421a tst r2, r3
66e: d00b beq.n 688 <dma_allocate+0x78>
tmp = tmp >> 1;
670: 085b lsrs r3, r3, #1
for (count = 0; count < CONF_MAX_USED_CHANNEL_NUM; ++count) {
672: 3401 adds r4, #1
674: b2e4 uxtb r4, r4
676: 2c05 cmp r4, #5
678: d1f8 bne.n 66c <dma_allocate+0x5c>
cpu_irq_leave_critical();
67a: 4b35 ldr r3, [pc, #212] ; (750 <dma_allocate+0x140>)
67c: 4798 blx r3
67e: 4b34 ldr r3, [pc, #208] ; (750 <dma_allocate+0x140>)
680: 4798 blx r3
/* If no channel available, return not found */
if (new_channel == DMA_INVALID_CHANNEL) {
system_interrupt_leave_critical_section();
return STATUS_ERR_NOT_FOUND;
682: 2014 movs r0, #20
684: e051 b.n 72a <dma_allocate+0x11a>
for (count = 0; count < CONF_MAX_USED_CHANNEL_NUM; ++count) {
686: 2400 movs r4, #0
_dma_inst.allocated_channels |= 1 << count;
688: 4a2b ldr r2, [pc, #172] ; (738 <dma_allocate+0x128>)
68a: 6851 ldr r1, [r2, #4]
68c: 2301 movs r3, #1
68e: 40a3 lsls r3, r4
690: 430b orrs r3, r1
692: 6053 str r3, [r2, #4]
_dma_inst.free_channels--;
694: 7a13 ldrb r3, [r2, #8]
696: 3b01 subs r3, #1
698: 7213 strb r3, [r2, #8]
69a: 4b2d ldr r3, [pc, #180] ; (750 <dma_allocate+0x140>)
69c: 4798 blx r3
if (new_channel == DMA_INVALID_CHANNEL) {
69e: 2cff cmp r4, #255 ; 0xff
6a0: d0ed beq.n 67e <dma_allocate+0x6e>
}
/* Set the channel */
resource->channel_id = new_channel;
6a2: 702c strb r4, [r5, #0]
/** Perform a reset for the allocated channel */
DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
6a4: 230f movs r3, #15
6a6: 4698 mov r8, r3
6a8: 401c ands r4, r3
6aa: 4f25 ldr r7, [pc, #148] ; (740 <dma_allocate+0x130>)
6ac: 3330 adds r3, #48 ; 0x30
6ae: 4699 mov r9, r3
6b0: 54fc strb r4, [r7, r3]
DMAC->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE;
6b2: 3301 adds r3, #1
6b4: 5cfa ldrb r2, [r7, r3]
6b6: 2102 movs r1, #2
6b8: 438a bics r2, r1
6ba: 54fa strb r2, [r7, r3]
DMAC->CHCTRLA.reg = DMAC_CHCTRLA_SWRST;
6bc: 2401 movs r4, #1
6be: 54fc strb r4, [r7, r3]
cpu_irq_enter_critical();
6c0: 4b1c ldr r3, [pc, #112] ; (734 <dma_allocate+0x124>)
6c2: 4798 blx r3
DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
6c4: 782b ldrb r3, [r5, #0]
6c6: 4642 mov r2, r8
6c8: 4013 ands r3, r2
6ca: 464a mov r2, r9
6cc: 54bb strb r3, [r7, r2]
DMAC->SWTRIGCTRL.reg &= (uint32_t)(~(1 << resource->channel_id));
6ce: 693b ldr r3, [r7, #16]
6d0: 782a ldrb r2, [r5, #0]
6d2: 4094 lsls r4, r2
6d4: 43a3 bics r3, r4
6d6: 613b str r3, [r7, #16]
temp_CHCTRLB_reg = DMAC_CHCTRLB_LVL(resource_config->priority) | \
6d8: 7832 ldrb r2, [r6, #0]
6da: 0152 lsls r2, r2, #5
6dc: 2360 movs r3, #96 ; 0x60
6de: 4013 ands r3, r2
DMAC_CHCTRLB_TRIGSRC(resource_config->peripheral_trigger) | \
6e0: 7872 ldrb r2, [r6, #1]
6e2: 0212 lsls r2, r2, #8
6e4: 21fc movs r1, #252 ; 0xfc
6e6: 0189 lsls r1, r1, #6
6e8: 400a ands r2, r1
temp_CHCTRLB_reg = DMAC_CHCTRLB_LVL(resource_config->priority) | \
6ea: 4313 orrs r3, r2
DMAC_CHCTRLB_TRIGACT(resource_config->trigger_action);
6ec: 78b2 ldrb r2, [r6, #2]
6ee: 0592 lsls r2, r2, #22
6f0: 21c0 movs r1, #192 ; 0xc0
6f2: 0409 lsls r1, r1, #16
6f4: 400a ands r2, r1
temp_CHCTRLB_reg = DMAC_CHCTRLB_LVL(resource_config->priority) | \
6f6: 4313 orrs r3, r2
if(resource_config->event_config.input_action){
6f8: 78f1 ldrb r1, [r6, #3]
6fa: 2900 cmp r1, #0
6fc: d004 beq.n 708 <dma_allocate+0xf8>
temp_CHCTRLB_reg |= DMAC_CHCTRLB_EVIE | DMAC_CHCTRLB_EVACT(
6fe: 2207 movs r2, #7
700: 400a ands r2, r1
702: 2108 movs r1, #8
704: 430a orrs r2, r1
706: 4313 orrs r3, r2
if (resource_config->event_config.event_output_enable) {
708: 7932 ldrb r2, [r6, #4]
70a: 2a00 cmp r2, #0
70c: d001 beq.n 712 <dma_allocate+0x102>
temp_CHCTRLB_reg |= DMAC_CHCTRLB_EVOE;
70e: 2210 movs r2, #16
710: 4313 orrs r3, r2
DMAC->CHCTRLB.reg = temp_CHCTRLB_reg;
712: 4a0b ldr r2, [pc, #44] ; (740 <dma_allocate+0x130>)
714: 6453 str r3, [r2, #68] ; 0x44
cpu_irq_leave_critical();
716: 4c0e ldr r4, [pc, #56] ; (750 <dma_allocate+0x140>)
718: 47a0 blx r4
#endif
/** Configure the DMA control,channel registers and descriptors here */
_dma_set_config(resource, config);
resource->descriptor = NULL;
71a: 2300 movs r3, #0
71c: 61ab str r3, [r5, #24]
/* Log the DMA resource into the internal DMA resource pool */
_dma_active_resource[resource->channel_id] = resource;
71e: 782b ldrb r3, [r5, #0]
720: 009b lsls r3, r3, #2
722: 4a0c ldr r2, [pc, #48] ; (754 <dma_allocate+0x144>)
724: 509d str r5, [r3, r2]
726: 47a0 blx r4
system_interrupt_leave_critical_section();
return STATUS_OK;
728: 2000 movs r0, #0
}
72a: bc0c pop {r2, r3}
72c: 4690 mov r8, r2
72e: 4699 mov r9, r3
730: bdf8 pop {r3, r4, r5, r6, r7, pc}
732: 46c0 nop ; (mov r8, r8)
734: 000015e1 .word 0x000015e1
738: 20000000 .word 0x20000000
73c: 40000400 .word 0x40000400
740: 41004800 .word 0x41004800
744: 200001e0 .word 0x200001e0
748: 200000b0 .word 0x200000b0
74c: 00000f02 .word 0x00000f02
750: 00001621 .word 0x00001621
754: 2000009c .word 0x2000009c
00000758 <dma_start_transfer_job>:
* \retval STATUS_OK The transfer was started successfully
* \retval STATUS_BUSY The DMA resource was busy and the transfer was not started
* \retval STATUS_ERR_INVALID_ARG Transfer size is 0 and transfer was not started
*/
enum status_code dma_start_transfer_job(struct dma_resource *resource)
{
758: b570 push {r4, r5, r6, lr}
75a: 0004 movs r4, r0
cpu_irq_enter_critical();
75c: 4b19 ldr r3, [pc, #100] ; (7c4 <dma_start_transfer_job+0x6c>)
75e: 4798 blx r3
Assert(resource->channel_id != DMA_INVALID_CHANNEL);
system_interrupt_enter_critical_section();
/* Check if resource was busy */
if (resource->job_status == STATUS_BUSY) {
760: 7c63 ldrb r3, [r4, #17]
762: 2b05 cmp r3, #5
764: d008 beq.n 778 <dma_start_transfer_job+0x20>
system_interrupt_leave_critical_section();
return STATUS_BUSY;
}
/* Check if transfer size is valid */
if (resource->descriptor->BTCNT.reg == 0) {
766: 69a3 ldr r3, [r4, #24]
768: 885b ldrh r3, [r3, #2]
76a: b29b uxth r3, r3
76c: 2b00 cmp r3, #0
76e: d107 bne.n 780 <dma_start_transfer_job+0x28>
cpu_irq_leave_critical();
770: 4b15 ldr r3, [pc, #84] ; (7c8 <dma_start_transfer_job+0x70>)
772: 4798 blx r3
system_interrupt_leave_critical_section();
return STATUS_ERR_INVALID_ARG;
774: 2017 movs r0, #23
DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
system_interrupt_leave_critical_section();
return STATUS_OK;
}
776: bd70 pop {r4, r5, r6, pc}
778: 4b13 ldr r3, [pc, #76] ; (7c8 <dma_start_transfer_job+0x70>)
77a: 4798 blx r3
return STATUS_BUSY;
77c: 2005 movs r0, #5
77e: e7fa b.n 776 <dma_start_transfer_job+0x1e>
* \param[in] vector Interrupt vector to enable
*/
static inline void system_interrupt_enable(
const enum system_interrupt_vector vector)
{
NVIC->ISER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f));
780: 2640 movs r6, #64 ; 0x40
782: 4b12 ldr r3, [pc, #72] ; (7cc <dma_start_transfer_job+0x74>)
784: 601e str r6, [r3, #0]
DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
786: 7822 ldrb r2, [r4, #0]
788: 230f movs r3, #15
78a: 4013 ands r3, r2
78c: 4d10 ldr r5, [pc, #64] ; (7d0 <dma_start_transfer_job+0x78>)
78e: 223f movs r2, #63 ; 0x3f
790: 54ab strb r3, [r5, r2]
DMAC->CHINTENSET.reg = (DMAC_CHINTENSET_MASK & g_chan_interrupt_flag[resource->channel_id]);
792: 7823 ldrb r3, [r4, #0]
794: 4a0f ldr r2, [pc, #60] ; (7d4 <dma_start_transfer_job+0x7c>)
796: 5cd2 ldrb r2, [r2, r3]
798: 2307 movs r3, #7
79a: 4013 ands r3, r2
79c: 224d movs r2, #77 ; 0x4d
79e: 54ab strb r3, [r5, r2]
resource->job_status = STATUS_BUSY;
7a0: 2305 movs r3, #5
7a2: 7463 strb r3, [r4, #17]
memcpy(&descriptor_section[resource->channel_id], resource->descriptor,
7a4: 7820 ldrb r0, [r4, #0]
7a6: 0100 lsls r0, r0, #4
7a8: 4b0b ldr r3, [pc, #44] ; (7d8 <dma_start_transfer_job+0x80>)
7aa: 18c0 adds r0, r0, r3
7ac: 69a1 ldr r1, [r4, #24]
7ae: 3a3d subs r2, #61 ; 0x3d
7b0: 4b0a ldr r3, [pc, #40] ; (7dc <dma_start_transfer_job+0x84>)
7b2: 4798 blx r3
DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
7b4: 5dab ldrb r3, [r5, r6]
7b6: 2202 movs r2, #2
7b8: 4313 orrs r3, r2
7ba: 55ab strb r3, [r5, r6]
cpu_irq_leave_critical();
7bc: 4b02 ldr r3, [pc, #8] ; (7c8 <dma_start_transfer_job+0x70>)
7be: 4798 blx r3
return STATUS_OK;
7c0: 2000 movs r0, #0
7c2: e7d8 b.n 776 <dma_start_transfer_job+0x1e>
7c4: 000015e1 .word 0x000015e1
7c8: 00001621 .word 0x00001621
7cc: e000e100 .word 0xe000e100
7d0: 41004800 .word 0x41004800
7d4: 20000100 .word 0x20000100
7d8: 200001e0 .word 0x200001e0
7dc: 000026c9 .word 0x000026c9
000007e0 <dma_descriptor_create>:
* \param[in] config Pointer to the descriptor configuration structure
*
*/
void dma_descriptor_create(DmacDescriptor* descriptor,
struct dma_descriptor_config *config)
{
7e0: b5f0 push {r4, r5, r6, r7, lr}
/* Set block transfer control */
descriptor->BTCTRL.bit.VALID = config->descriptor_valid;
7e2: 780a ldrb r2, [r1, #0]
7e4: 8803 ldrh r3, [r0, #0]
7e6: 2601 movs r6, #1
7e8: 4032 ands r2, r6
7ea: 2401 movs r4, #1
7ec: 43a3 bics r3, r4
7ee: 4313 orrs r3, r2
7f0: 8003 strh r3, [r0, #0]
descriptor->BTCTRL.bit.EVOSEL = config->event_output_selection;
7f2: 784b ldrb r3, [r1, #1]
7f4: 8804 ldrh r4, [r0, #0]
7f6: 2703 movs r7, #3
7f8: 403b ands r3, r7
7fa: 005b lsls r3, r3, #1
7fc: 2206 movs r2, #6
7fe: 4394 bics r4, r2
800: 431c orrs r4, r3
802: 8004 strh r4, [r0, #0]
descriptor->BTCTRL.bit.BLOCKACT = config->block_action;
804: 788d ldrb r5, [r1, #2]
806: 8804 ldrh r4, [r0, #0]
808: 403d ands r5, r7
80a: 00ed lsls r5, r5, #3
80c: 2318 movs r3, #24
80e: 439c bics r4, r3
810: 432c orrs r4, r5
812: 8004 strh r4, [r0, #0]
descriptor->BTCTRL.bit.BEATSIZE = config->beat_size;
814: 78ca ldrb r2, [r1, #3]
816: 8803 ldrh r3, [r0, #0]
818: 403a ands r2, r7
81a: 0212 lsls r2, r2, #8
81c: 4c16 ldr r4, [pc, #88] ; (878 <dma_descriptor_create+0x98>)
81e: 4023 ands r3, r4
820: 4313 orrs r3, r2
822: 8003 strh r3, [r0, #0]
descriptor->BTCTRL.bit.SRCINC = config->src_increment_enable;
824: 790b ldrb r3, [r1, #4]
826: 8804 ldrh r4, [r0, #0]
828: 4033 ands r3, r6
82a: 029b lsls r3, r3, #10
82c: 4a13 ldr r2, [pc, #76] ; (87c <dma_descriptor_create+0x9c>)
82e: 4014 ands r4, r2
830: 431c orrs r4, r3
832: 8004 strh r4, [r0, #0]
descriptor->BTCTRL.bit.DSTINC = config->dst_increment_enable;
834: 794d ldrb r5, [r1, #5]
836: 8804 ldrh r4, [r0, #0]
838: 4035 ands r5, r6
83a: 02ed lsls r5, r5, #11
83c: 4b10 ldr r3, [pc, #64] ; (880 <dma_descriptor_create+0xa0>)
83e: 401c ands r4, r3
840: 432c orrs r4, r5
842: 8004 strh r4, [r0, #0]
descriptor->BTCTRL.bit.STEPSEL = config->step_selection;
844: 798a ldrb r2, [r1, #6]
846: 8803 ldrh r3, [r0, #0]
848: 4032 ands r2, r6
84a: 0312 lsls r2, r2, #12
84c: 4c0d ldr r4, [pc, #52] ; (884 <dma_descriptor_create+0xa4>)
84e: 4023 ands r3, r4
850: 4313 orrs r3, r2
852: 8003 strh r3, [r0, #0]
descriptor->BTCTRL.bit.STEPSIZE = config->step_size;
854: 79cb ldrb r3, [r1, #7]
856: 2207 movs r2, #7
858: 401a ands r2, r3
85a: 8803 ldrh r3, [r0, #0]
85c: 0352 lsls r2, r2, #13
85e: 04db lsls r3, r3, #19
860: 0cdb lsrs r3, r3, #19
862: 4313 orrs r3, r2
864: 8003 strh r3, [r0, #0]
/* Set transfer size, source address and destination address */
descriptor->BTCNT.reg = config->block_transfer_count;
866: 890b ldrh r3, [r1, #8]
868: 8043 strh r3, [r0, #2]
descriptor->SRCADDR.reg = config->source_address;
86a: 68cb ldr r3, [r1, #12]
86c: 6043 str r3, [r0, #4]
descriptor->DSTADDR.reg = config->destination_address;
86e: 690b ldr r3, [r1, #16]
870: 6083 str r3, [r0, #8]
/* Set next transfer descriptor address */
descriptor->DESCADDR.reg = config->next_descriptor_address;
872: 694b ldr r3, [r1, #20]
874: 60c3 str r3, [r0, #12]
}
876: bdf0 pop {r4, r5, r6, r7, pc}
878: fffffcff .word 0xfffffcff
87c: fffffbff .word 0xfffffbff
880: fffff7ff .word 0xfffff7ff
884: ffffefff .word 0xffffefff
00000888 <dma_add_descriptor>:
enum status_code dma_add_descriptor(struct dma_resource *resource,
DmacDescriptor* descriptor)
{
DmacDescriptor* desc = resource->descriptor;
if (resource->job_status == STATUS_BUSY) {
888: 7c42 ldrb r2, [r0, #17]
return STATUS_BUSY;
88a: 2305 movs r3, #5
if (resource->job_status == STATUS_BUSY) {
88c: 2a05 cmp r2, #5
88e: d00b beq.n 8a8 <dma_add_descriptor+0x20>
DmacDescriptor* desc = resource->descriptor;
890: 6983 ldr r3, [r0, #24]
}
/* Look up for an empty space for the descriptor */
if (desc == NULL) {
892: 2b00 cmp r3, #0
894: d00a beq.n 8ac <dma_add_descriptor+0x24>
resource->descriptor = descriptor;
} else {
/* Looking for end of descriptor link */
while(desc->DESCADDR.reg != 0) {
896: 68da ldr r2, [r3, #12]
898: 2a00 cmp r2, #0
89a: d003 beq.n 8a4 <dma_add_descriptor+0x1c>
desc = (DmacDescriptor*)(desc->DESCADDR.reg);
89c: 68db ldr r3, [r3, #12]
while(desc->DESCADDR.reg != 0) {
89e: 68da ldr r2, [r3, #12]
8a0: 2a00 cmp r2, #0
8a2: d1fb bne.n 89c <dma_add_descriptor+0x14>
}
/* Set to the end of descriptor list */
desc->DESCADDR.reg = (uint32_t)descriptor;
8a4: 60d9 str r1, [r3, #12]
}
return STATUS_OK;
8a6: 2300 movs r3, #0
}
8a8: 0018 movs r0, r3
8aa: 4770 bx lr
resource->descriptor = descriptor;
8ac: 6181 str r1, [r0, #24]
return STATUS_OK;
8ae: 2300 movs r3, #0
8b0: e7fa b.n 8a8 <dma_add_descriptor+0x20>
000008b2 <long_division>:
/**
* \internal Calculate 64 bit division, ref can be found in
* http://en.wikipedia.org/wiki/Division_algorithm#Long_division
*/
static uint64_t long_division(uint64_t n, uint64_t d)
{
8b2: b5f0 push {r4, r5, r6, r7, lr}
8b4: 46de mov lr, fp
8b6: 4657 mov r7, sl
8b8: 464e mov r6, r9
8ba: 4645 mov r5, r8
8bc: b5e0 push {r5, r6, r7, lr}
8be: b087 sub sp, #28
8c0: 4680 mov r8, r0
8c2: 9104 str r1, [sp, #16]
8c4: 0016 movs r6, r2
8c6: 001f movs r7, r3
int32_t i;
uint64_t q = 0, r = 0, bit_shift;
8c8: 2200 movs r2, #0
8ca: 2300 movs r3, #0
8cc: 2100 movs r1, #0
8ce: 468b mov fp, r1
for (i = 63; i >= 0; i--) {
8d0: 243f movs r4, #63 ; 0x3f
bit_shift = (uint64_t)1 << i;
8d2: 2001 movs r0, #1
8d4: 0021 movs r1, r4
8d6: 9600 str r6, [sp, #0]
8d8: 9701 str r7, [sp, #4]
8da: 465c mov r4, fp
8dc: 9403 str r4, [sp, #12]
8de: 4644 mov r4, r8
8e0: 9405 str r4, [sp, #20]
8e2: e013 b.n 90c <long_division+0x5a>
8e4: 2420 movs r4, #32
8e6: 1a64 subs r4, r4, r1
8e8: 0005 movs r5, r0
8ea: 40e5 lsrs r5, r4
8ec: 46a8 mov r8, r5
8ee: e014 b.n 91a <long_division+0x68>
if (n & bit_shift) {
r |= 0x01;
}
if (r >= d) {
r = r - d;
8f0: 9c00 ldr r4, [sp, #0]
8f2: 9d01 ldr r5, [sp, #4]
8f4: 1b12 subs r2, r2, r4
8f6: 41ab sbcs r3, r5
q |= bit_shift;
8f8: 465c mov r4, fp
8fa: 464d mov r5, r9
8fc: 432c orrs r4, r5
8fe: 46a3 mov fp, r4
900: 9c03 ldr r4, [sp, #12]
902: 4645 mov r5, r8
904: 432c orrs r4, r5
906: 9403 str r4, [sp, #12]
for (i = 63; i >= 0; i--) {
908: 3901 subs r1, #1
90a: d325 bcc.n 958 <long_division+0xa6>
bit_shift = (uint64_t)1 << i;
90c: 2420 movs r4, #32
90e: 4264 negs r4, r4
910: 190c adds r4, r1, r4
912: d4e7 bmi.n 8e4 <long_division+0x32>
914: 0005 movs r5, r0
916: 40a5 lsls r5, r4
918: 46a8 mov r8, r5
91a: 0004 movs r4, r0
91c: 408c lsls r4, r1
91e: 46a1 mov r9, r4
r = r << 1;
920: 1892 adds r2, r2, r2
922: 415b adcs r3, r3
924: 0014 movs r4, r2
926: 001d movs r5, r3
if (n & bit_shift) {
928: 9e05 ldr r6, [sp, #20]
92a: 464f mov r7, r9
92c: 403e ands r6, r7
92e: 46b4 mov ip, r6
930: 9e04 ldr r6, [sp, #16]
932: 4647 mov r7, r8
934: 403e ands r6, r7
936: 46b2 mov sl, r6
938: 4666 mov r6, ip
93a: 4657 mov r7, sl
93c: 433e orrs r6, r7
93e: d003 beq.n 948 <long_division+0x96>
r |= 0x01;
940: 0006 movs r6, r0
942: 4326 orrs r6, r4
944: 0032 movs r2, r6
946: 002b movs r3, r5
if (r >= d) {
948: 9c00 ldr r4, [sp, #0]
94a: 9d01 ldr r5, [sp, #4]
94c: 429d cmp r5, r3
94e: d8db bhi.n 908 <long_division+0x56>
950: d1ce bne.n 8f0 <long_division+0x3e>
952: 4294 cmp r4, r2
954: d8d8 bhi.n 908 <long_division+0x56>
956: e7cb b.n 8f0 <long_division+0x3e>
958: 9b03 ldr r3, [sp, #12]
}
}
return q;
}
95a: 4658 mov r0, fp
95c: 0019 movs r1, r3
95e: b007 add sp, #28
960: bc3c pop {r2, r3, r4, r5}
962: 4690 mov r8, r2
964: 4699 mov r9, r3
966: 46a2 mov sl, r4
968: 46ab mov fp, r5
96a: bdf0 pop {r4, r5, r6, r7, pc}
0000096c <_sercom_get_sync_baud_val>:
*/
enum status_code _sercom_get_sync_baud_val(
const uint32_t baudrate,
const uint32_t external_clock,
uint16_t *const baudvalue)
{
96c: b510 push {r4, lr}
uint16_t baud_calculated = 0;
uint32_t clock_value = external_clock;
/* Check if baudrate is outside of valid range */
if (baudrate > (external_clock / 2)) {
96e: 0849 lsrs r1, r1, #1
/* Return with error code */
return STATUS_ERR_BAUDRATE_UNAVAILABLE;
970: 2340 movs r3, #64 ; 0x40
972: 2400 movs r4, #0
if (baudrate > (external_clock / 2)) {
974: 4281 cmp r1, r0
976: d202 bcs.n 97e <_sercom_get_sync_baud_val+0x12>
return STATUS_ERR_BAUDRATE_UNAVAILABLE;
} else {
*baudvalue = baud_calculated;
return STATUS_OK;
}
}
978: 0018 movs r0, r3
97a: bd10 pop {r4, pc}
baud_calculated++;
97c: 001c movs r4, r3
clock_value = clock_value - baudrate;
97e: 1a09 subs r1, r1, r0
baud_calculated++;
980: 1c63 adds r3, r4, #1
982: b29b uxth r3, r3
while (clock_value >= baudrate) {
984: 4288 cmp r0, r1
986: d9f9 bls.n 97c <_sercom_get_sync_baud_val+0x10>
return STATUS_ERR_BAUDRATE_UNAVAILABLE;
988: 2340 movs r3, #64 ; 0x40
if (baud_calculated > 0xFF) {
98a: 2cff cmp r4, #255 ; 0xff
98c: d8f4 bhi.n 978 <_sercom_get_sync_baud_val+0xc>
*baudvalue = baud_calculated;
98e: 8014 strh r4, [r2, #0]
return STATUS_OK;
990: 2300 movs r3, #0
992: e7f1 b.n 978 <_sercom_get_sync_baud_val+0xc>
00000994 <_sercom_get_async_baud_val>:
const uint32_t baudrate,
const uint32_t peripheral_clock,
uint16_t *const baudval,
enum sercom_asynchronous_operation_mode mode,
enum sercom_asynchronous_sample_num sample_num)
{
994: b5f0 push {r4, r5, r6, r7, lr}
996: b083 sub sp, #12
998: 000f movs r7, r1
99a: 0016 movs r6, r2
99c: aa08 add r2, sp, #32
99e: 7811 ldrb r1, [r2, #0]
uint8_t baud_fp;
uint32_t baud_int = 0;
uint64_t temp1;
/* Check if the baudrate is outside of valid range */
if ((baudrate * sample_num) > peripheral_clock) {
9a0: 0004 movs r4, r0
9a2: 434c muls r4, r1
/* Return with error code */
return STATUS_ERR_BAUDRATE_UNAVAILABLE;
9a4: 2240 movs r2, #64 ; 0x40
if ((baudrate * sample_num) > peripheral_clock) {
9a6: 42bc cmp r4, r7
9a8: d902 bls.n 9b0 <_sercom_get_async_baud_val+0x1c>
baud_calculated = baud_int | (baud_fp << 13);
}
*baudval = baud_calculated;
return STATUS_OK;
}
9aa: 0010 movs r0, r2
9ac: b003 add sp, #12
9ae: bdf0 pop {r4, r5, r6, r7, pc}
if(mode == SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC) {
9b0: 2b00 cmp r3, #0
9b2: d114 bne.n 9de <_sercom_get_async_baud_val+0x4a>
temp1 = ((sample_num * (uint64_t)baudrate) << SHIFT);
9b4: 0002 movs r2, r0
9b6: 0008 movs r0, r1
9b8: 2100 movs r1, #0
9ba: 4c19 ldr r4, [pc, #100] ; (a20 <_sercom_get_async_baud_val+0x8c>)
9bc: 47a0 blx r4
9be: 0001 movs r1, r0
ratio = long_division(temp1, peripheral_clock);
9c0: 003a movs r2, r7
9c2: 2300 movs r3, #0
9c4: 2000 movs r0, #0
9c6: 4c17 ldr r4, [pc, #92] ; (a24 <_sercom_get_async_baud_val+0x90>)
9c8: 47a0 blx r4
scale = ((uint64_t)1 << SHIFT) - ratio;
9ca: 2200 movs r2, #0
9cc: 2301 movs r3, #1
9ce: 1a12 subs r2, r2, r0
9d0: 418b sbcs r3, r1
baud_calculated = (65536 * scale) >> SHIFT;
9d2: 0c12 lsrs r2, r2, #16
9d4: 041b lsls r3, r3, #16
9d6: 431a orrs r2, r3
*baudval = baud_calculated;
9d8: 8032 strh r2, [r6, #0]
return STATUS_OK;
9da: 2200 movs r2, #0
9dc: e7e5 b.n 9aa <_sercom_get_async_baud_val+0x16>
uint64_t baud_calculated = 0;
9de: 2200 movs r2, #0
} else if(mode == SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL) {
9e0: 2b01 cmp r3, #1
9e2: d1f9 bne.n 9d8 <_sercom_get_async_baud_val+0x44>
temp1 = ((uint64_t)baudrate * sample_num);
9e4: 000a movs r2, r1
9e6: 2300 movs r3, #0
9e8: 2100 movs r1, #0
9ea: 4c0d ldr r4, [pc, #52] ; (a20 <_sercom_get_async_baud_val+0x8c>)
9ec: 47a0 blx r4
9ee: 0002 movs r2, r0
9f0: 000b movs r3, r1
9f2: 9200 str r2, [sp, #0]
9f4: 9301 str r3, [sp, #4]
baud_int = long_division( peripheral_clock, temp1);
9f6: 0038 movs r0, r7
9f8: 2100 movs r1, #0
9fa: 4c0a ldr r4, [pc, #40] ; (a24 <_sercom_get_async_baud_val+0x90>)
9fc: 47a0 blx r4
9fe: 0005 movs r5, r0
if(baud_int > BAUD_INT_MAX) {
a00: 2380 movs r3, #128 ; 0x80
a02: 019b lsls r3, r3, #6
return STATUS_ERR_BAUDRATE_UNAVAILABLE;
a04: 2240 movs r2, #64 ; 0x40
if(baud_int > BAUD_INT_MAX) {
a06: 4298 cmp r0, r3
a08: d8cf bhi.n 9aa <_sercom_get_async_baud_val+0x16>
temp1 = long_division( 8 * (uint64_t)peripheral_clock, temp1);
a0a: 0f79 lsrs r1, r7, #29
a0c: 00f8 lsls r0, r7, #3
a0e: 9a00 ldr r2, [sp, #0]
a10: 9b01 ldr r3, [sp, #4]
a12: 47a0 blx r4
baud_fp = temp1 - 8 * baud_int;
a14: 00ea lsls r2, r5, #3
a16: 1a82 subs r2, r0, r2
baud_calculated = baud_int | (baud_fp << 13);
a18: b2d2 uxtb r2, r2
a1a: 0352 lsls r2, r2, #13
a1c: 432a orrs r2, r5
a1e: e7db b.n 9d8 <_sercom_get_async_baud_val+0x44>
a20: 00001f0d .word 0x00001f0d
a24: 000008b3 .word 0x000008b3
00000a28 <sercom_set_gclk_generator>:
* forced.
*/
enum status_code sercom_set_gclk_generator(
const enum gclk_generator generator_source,
const bool force_change)
{
a28: b510 push {r4, lr}
a2a: b082 sub sp, #8
a2c: 0004 movs r4, r0
/* Check if valid option */
if (!_sercom_config.generator_is_set || force_change) {
a2e: 4b0e ldr r3, [pc, #56] ; (a68 <sercom_set_gclk_generator+0x40>)
a30: 781b ldrb r3, [r3, #0]
a32: 2b00 cmp r3, #0
a34: d007 beq.n a46 <sercom_set_gclk_generator+0x1e>
a36: 2900 cmp r1, #0
a38: d105 bne.n a46 <sercom_set_gclk_generator+0x1e>
/* Save config */
_sercom_config.generator_source = generator_source;
_sercom_config.generator_is_set = true;
return STATUS_OK;
} else if (generator_source == _sercom_config.generator_source) {
a3a: 4b0b ldr r3, [pc, #44] ; (a68 <sercom_set_gclk_generator+0x40>)
a3c: 785b ldrb r3, [r3, #1]
a3e: 4283 cmp r3, r0
a40: d010 beq.n a64 <sercom_set_gclk_generator+0x3c>
/* Return status OK if same config */
return STATUS_OK;
}
/* Return invalid config to already initialized GCLK */
return STATUS_ERR_ALREADY_INITIALIZED;
a42: 201d movs r0, #29
a44: e00c b.n a60 <sercom_set_gclk_generator+0x38>
gclk_chan_conf.source_generator = generator_source;
a46: a901 add r1, sp, #4
a48: 700c strb r4, [r1, #0]
system_gclk_chan_set_config(SERCOM_GCLK_ID, &gclk_chan_conf);
a4a: 2013 movs r0, #19
a4c: 4b07 ldr r3, [pc, #28] ; (a6c <sercom_set_gclk_generator+0x44>)
a4e: 4798 blx r3
system_gclk_chan_enable(SERCOM_GCLK_ID);
a50: 2013 movs r0, #19
a52: 4b07 ldr r3, [pc, #28] ; (a70 <sercom_set_gclk_generator+0x48>)
a54: 4798 blx r3
_sercom_config.generator_source = generator_source;
a56: 4b04 ldr r3, [pc, #16] ; (a68 <sercom_set_gclk_generator+0x40>)
a58: 705c strb r4, [r3, #1]
_sercom_config.generator_is_set = true;
a5a: 2201 movs r2, #1
a5c: 701a strb r2, [r3, #0]
return STATUS_OK;
a5e: 2000 movs r0, #0
}
a60: b002 add sp, #8
a62: bd10 pop {r4, pc}
return STATUS_OK;
a64: 2000 movs r0, #0
a66: e7fb b.n a60 <sercom_set_gclk_generator+0x38>
a68: 20000108 .word 0x20000108
a6c: 00001af5 .word 0x00001af5
a70: 00001a69 .word 0x00001a69
00000a74 <_sercom_get_default_pad>:
*/
uint32_t _sercom_get_default_pad(
Sercom *const sercom_module,
const uint8_t pad)
{
switch ((uintptr_t)sercom_module) {
a74: 4b40 ldr r3, [pc, #256] ; (b78 <_sercom_get_default_pad+0x104>)
a76: 4298 cmp r0, r3
a78: d031 beq.n ade <_sercom_get_default_pad+0x6a>
a7a: d90a bls.n a92 <_sercom_get_default_pad+0x1e>
a7c: 4b3f ldr r3, [pc, #252] ; (b7c <_sercom_get_default_pad+0x108>)
a7e: 4298 cmp r0, r3
a80: d04d beq.n b1e <_sercom_get_default_pad+0xaa>
a82: 4b3f ldr r3, [pc, #252] ; (b80 <_sercom_get_default_pad+0x10c>)
a84: 4298 cmp r0, r3
a86: d05a beq.n b3e <_sercom_get_default_pad+0xca>
a88: 4b3e ldr r3, [pc, #248] ; (b84 <_sercom_get_default_pad+0x110>)
a8a: 4298 cmp r0, r3
a8c: d037 beq.n afe <_sercom_get_default_pad+0x8a>
/* Auto-generate a lookup table for the default SERCOM pad defaults */
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
}
Assert(false);
return 0;
a8e: 2000 movs r0, #0
}
a90: 4770 bx lr
switch ((uintptr_t)sercom_module) {
a92: 4b3d ldr r3, [pc, #244] ; (b88 <_sercom_get_default_pad+0x114>)
a94: 4298 cmp r0, r3
a96: d00c beq.n ab2 <_sercom_get_default_pad+0x3e>
a98: 4b3c ldr r3, [pc, #240] ; (b8c <_sercom_get_default_pad+0x118>)
a9a: 4298 cmp r0, r3
a9c: d1f7 bne.n a8e <_sercom_get_default_pad+0x1a>
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
a9e: 2901 cmp r1, #1
aa0: d017 beq.n ad2 <_sercom_get_default_pad+0x5e>
aa2: 2900 cmp r1, #0
aa4: d05d beq.n b62 <_sercom_get_default_pad+0xee>
aa6: 2902 cmp r1, #2
aa8: d015 beq.n ad6 <_sercom_get_default_pad+0x62>
aaa: 2903 cmp r1, #3
aac: d015 beq.n ada <_sercom_get_default_pad+0x66>
return 0;
aae: 2000 movs r0, #0
ab0: e7ee b.n a90 <_sercom_get_default_pad+0x1c>
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
ab2: 2901 cmp r1, #1
ab4: d007 beq.n ac6 <_sercom_get_default_pad+0x52>
ab6: 2900 cmp r1, #0
ab8: d051 beq.n b5e <_sercom_get_default_pad+0xea>
aba: 2902 cmp r1, #2
abc: d005 beq.n aca <_sercom_get_default_pad+0x56>
abe: 2903 cmp r1, #3
ac0: d005 beq.n ace <_sercom_get_default_pad+0x5a>
return 0;
ac2: 2000 movs r0, #0
ac4: e7e4 b.n a90 <_sercom_get_default_pad+0x1c>
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
ac6: 4832 ldr r0, [pc, #200] ; (b90 <_sercom_get_default_pad+0x11c>)
ac8: e7e2 b.n a90 <_sercom_get_default_pad+0x1c>
aca: 4832 ldr r0, [pc, #200] ; (b94 <_sercom_get_default_pad+0x120>)
acc: e7e0 b.n a90 <_sercom_get_default_pad+0x1c>
ace: 4832 ldr r0, [pc, #200] ; (b98 <_sercom_get_default_pad+0x124>)
ad0: e7de b.n a90 <_sercom_get_default_pad+0x1c>
ad2: 4832 ldr r0, [pc, #200] ; (b9c <_sercom_get_default_pad+0x128>)
ad4: e7dc b.n a90 <_sercom_get_default_pad+0x1c>
ad6: 4832 ldr r0, [pc, #200] ; (ba0 <_sercom_get_default_pad+0x12c>)
ad8: e7da b.n a90 <_sercom_get_default_pad+0x1c>
ada: 4832 ldr r0, [pc, #200] ; (ba4 <_sercom_get_default_pad+0x130>)
adc: e7d8 b.n a90 <_sercom_get_default_pad+0x1c>
ade: 2901 cmp r1, #1
ae0: d007 beq.n af2 <_sercom_get_default_pad+0x7e>
ae2: 2900 cmp r1, #0
ae4: d03f beq.n b66 <_sercom_get_default_pad+0xf2>
ae6: 2902 cmp r1, #2
ae8: d005 beq.n af6 <_sercom_get_default_pad+0x82>
aea: 2903 cmp r1, #3
aec: d005 beq.n afa <_sercom_get_default_pad+0x86>
return 0;
aee: 2000 movs r0, #0
af0: e7ce b.n a90 <_sercom_get_default_pad+0x1c>
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
af2: 482d ldr r0, [pc, #180] ; (ba8 <_sercom_get_default_pad+0x134>)
af4: e7cc b.n a90 <_sercom_get_default_pad+0x1c>
af6: 482d ldr r0, [pc, #180] ; (bac <_sercom_get_default_pad+0x138>)
af8: e7ca b.n a90 <_sercom_get_default_pad+0x1c>
afa: 482d ldr r0, [pc, #180] ; (bb0 <_sercom_get_default_pad+0x13c>)
afc: e7c8 b.n a90 <_sercom_get_default_pad+0x1c>
afe: 2901 cmp r1, #1
b00: d007 beq.n b12 <_sercom_get_default_pad+0x9e>
b02: 2900 cmp r1, #0
b04: d031 beq.n b6a <_sercom_get_default_pad+0xf6>
b06: 2902 cmp r1, #2
b08: d005 beq.n b16 <_sercom_get_default_pad+0xa2>
b0a: 2903 cmp r1, #3
b0c: d005 beq.n b1a <_sercom_get_default_pad+0xa6>
return 0;
b0e: 2000 movs r0, #0
b10: e7be b.n a90 <_sercom_get_default_pad+0x1c>
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
b12: 4828 ldr r0, [pc, #160] ; (bb4 <_sercom_get_default_pad+0x140>)
b14: e7bc b.n a90 <_sercom_get_default_pad+0x1c>
b16: 4828 ldr r0, [pc, #160] ; (bb8 <_sercom_get_default_pad+0x144>)
b18: e7ba b.n a90 <_sercom_get_default_pad+0x1c>
b1a: 4828 ldr r0, [pc, #160] ; (bbc <_sercom_get_default_pad+0x148>)
b1c: e7b8 b.n a90 <_sercom_get_default_pad+0x1c>
b1e: 2901 cmp r1, #1
b20: d007 beq.n b32 <_sercom_get_default_pad+0xbe>
b22: 2900 cmp r1, #0
b24: d023 beq.n b6e <_sercom_get_default_pad+0xfa>
b26: 2902 cmp r1, #2
b28: d005 beq.n b36 <_sercom_get_default_pad+0xc2>
b2a: 2903 cmp r1, #3
b2c: d005 beq.n b3a <_sercom_get_default_pad+0xc6>
return 0;
b2e: 2000 movs r0, #0
b30: e7ae b.n a90 <_sercom_get_default_pad+0x1c>
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
b32: 4823 ldr r0, [pc, #140] ; (bc0 <_sercom_get_default_pad+0x14c>)
b34: e7ac b.n a90 <_sercom_get_default_pad+0x1c>
b36: 4823 ldr r0, [pc, #140] ; (bc4 <_sercom_get_default_pad+0x150>)
b38: e7aa b.n a90 <_sercom_get_default_pad+0x1c>
b3a: 4823 ldr r0, [pc, #140] ; (bc8 <_sercom_get_default_pad+0x154>)
b3c: e7a8 b.n a90 <_sercom_get_default_pad+0x1c>
b3e: 2901 cmp r1, #1
b40: d007 beq.n b52 <_sercom_get_default_pad+0xde>
b42: 2900 cmp r1, #0
b44: d015 beq.n b72 <_sercom_get_default_pad+0xfe>
b46: 2902 cmp r1, #2
b48: d005 beq.n b56 <_sercom_get_default_pad+0xe2>
b4a: 2903 cmp r1, #3
b4c: d005 beq.n b5a <_sercom_get_default_pad+0xe6>
return 0;
b4e: 2000 movs r0, #0
b50: e79e b.n a90 <_sercom_get_default_pad+0x1c>
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
b52: 481e ldr r0, [pc, #120] ; (bcc <_sercom_get_default_pad+0x158>)
b54: e79c b.n a90 <_sercom_get_default_pad+0x1c>
b56: 481e ldr r0, [pc, #120] ; (bd0 <_sercom_get_default_pad+0x15c>)
b58: e79a b.n a90 <_sercom_get_default_pad+0x1c>
b5a: 481e ldr r0, [pc, #120] ; (bd4 <_sercom_get_default_pad+0x160>)
b5c: e798 b.n a90 <_sercom_get_default_pad+0x1c>
b5e: 481e ldr r0, [pc, #120] ; (bd8 <_sercom_get_default_pad+0x164>)
b60: e796 b.n a90 <_sercom_get_default_pad+0x1c>
b62: 2003 movs r0, #3
b64: e794 b.n a90 <_sercom_get_default_pad+0x1c>
b66: 481d ldr r0, [pc, #116] ; (bdc <_sercom_get_default_pad+0x168>)
b68: e792 b.n a90 <_sercom_get_default_pad+0x1c>
b6a: 481d ldr r0, [pc, #116] ; (be0 <_sercom_get_default_pad+0x16c>)
b6c: e790 b.n a90 <_sercom_get_default_pad+0x1c>
b6e: 481d ldr r0, [pc, #116] ; (be4 <_sercom_get_default_pad+0x170>)
b70: e78e b.n a90 <_sercom_get_default_pad+0x1c>
b72: 481d ldr r0, [pc, #116] ; (be8 <_sercom_get_default_pad+0x174>)
b74: e78c b.n a90 <_sercom_get_default_pad+0x1c>
b76: 46c0 nop ; (mov r8, r8)
b78: 42001000 .word 0x42001000
b7c: 42001800 .word 0x42001800
b80: 42001c00 .word 0x42001c00
b84: 42001400 .word 0x42001400
b88: 42000800 .word 0x42000800
b8c: 42000c00 .word 0x42000c00
b90: 00050003 .word 0x00050003
b94: 00060003 .word 0x00060003
b98: 00070003 .word 0x00070003
b9c: 00010003 .word 0x00010003
ba0: 001e0003 .word 0x001e0003
ba4: 001f0003 .word 0x001f0003
ba8: 00090003 .word 0x00090003
bac: 000a0003 .word 0x000a0003
bb0: 000b0003 .word 0x000b0003
bb4: 00110003 .word 0x00110003
bb8: 00120003 .word 0x00120003
bbc: 00130003 .word 0x00130003
bc0: 000d0003 .word 0x000d0003
bc4: 000e0003 .word 0x000e0003
bc8: 000f0003 .word 0x000f0003
bcc: 00170003 .word 0x00170003
bd0: 00180003 .word 0x00180003
bd4: 00190003 .word 0x00190003
bd8: 00040003 .word 0x00040003
bdc: 00080003 .word 0x00080003
be0: 00100003 .word 0x00100003
be4: 000c0003 .word 0x000c0003
be8: 00160003 .word 0x00160003
00000bec <_sercom_get_sercom_inst_index>:
*
* \return Index of given instance.
*/
uint8_t _sercom_get_sercom_inst_index(
Sercom *const sercom_instance)
{
bec: b530 push {r4, r5, lr}
bee: b087 sub sp, #28
/* Save all available SERCOM instances for compare */
Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
bf0: 4b0b ldr r3, [pc, #44] ; (c20 <_sercom_get_sercom_inst_index+0x34>)
bf2: 466a mov r2, sp
bf4: cb32 ldmia r3!, {r1, r4, r5}
bf6: c232 stmia r2!, {r1, r4, r5}
bf8: cb32 ldmia r3!, {r1, r4, r5}
bfa: c232 stmia r2!, {r1, r4, r5}
/* Find index for sercom instance */
for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
bfc: 9b00 ldr r3, [sp, #0]
bfe: 4283 cmp r3, r0
c00: d00b beq.n c1a <_sercom_get_sercom_inst_index+0x2e>
c02: 2301 movs r3, #1
c04: 009a lsls r2, r3, #2
c06: 4669 mov r1, sp
c08: 5852 ldr r2, [r2, r1]
c0a: 4282 cmp r2, r0
c0c: d006 beq.n c1c <_sercom_get_sercom_inst_index+0x30>
for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
c0e: 3301 adds r3, #1
c10: 2b06 cmp r3, #6
c12: d1f7 bne.n c04 <_sercom_get_sercom_inst_index+0x18>
}
}
/* Invalid data given */
Assert(false);
return 0;
c14: 2000 movs r0, #0
}
c16: b007 add sp, #28
c18: bd30 pop {r4, r5, pc}
for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
c1a: 2300 movs r3, #0
return i;
c1c: b2d8 uxtb r0, r3
c1e: e7fa b.n c16 <_sercom_get_sercom_inst_index+0x2a>
c20: 000037f4 .word 0x000037f4
00000c24 <_read>:
int __attribute__((weak))
_read (int file, char * ptr, int len); // Remove GCC compiler warning
int __attribute__((weak))
_read (int file, char * ptr, int len)
{
c24: b5f0 push {r4, r5, r6, r7, lr}
c26: 46c6 mov lr, r8
c28: b500 push {lr}
c2a: 000c movs r4, r1
c2c: 4690 mov r8, r2
int nChars = 0;
if (file != 0) {
c2e: 2800 cmp r0, #0
c30: d10f bne.n c52 <_read+0x2e>
return -1;
}
for (; len > 0; --len) {
c32: 2a00 cmp r2, #0
c34: dd11 ble.n c5a <_read+0x36>
c36: 188f adds r7, r1, r2
ptr_get(stdio_base, ptr);
c38: 4e09 ldr r6, [pc, #36] ; (c60 <_read+0x3c>)
c3a: 4d0a ldr r5, [pc, #40] ; (c64 <_read+0x40>)
c3c: 6830 ldr r0, [r6, #0]
c3e: 0021 movs r1, r4
c40: 682b ldr r3, [r5, #0]
c42: 4798 blx r3
ptr++;
c44: 3401 adds r4, #1
for (; len > 0; --len) {
c46: 42bc cmp r4, r7
c48: d1f8 bne.n c3c <_read+0x18>
nChars++;
}
return nChars;
}
c4a: 4640 mov r0, r8
c4c: bc04 pop {r2}
c4e: 4690 mov r8, r2
c50: bdf0 pop {r4, r5, r6, r7, pc}
return -1;
c52: 2301 movs r3, #1
c54: 425b negs r3, r3
c56: 4698 mov r8, r3
c58: e7f7 b.n c4a <_read+0x26>
for (; len > 0; --len) {
c5a: 4680 mov r8, r0
c5c: e7f5 b.n c4a <_read+0x26>
c5e: 46c0 nop ; (mov r8, r8)
c60: 20000238 .word 0x20000238
c64: 20000230 .word 0x20000230
00000c68 <_write>:
int __attribute__((weak))
_write (int file, char * ptr, int len);
int __attribute__((weak))
_write (int file, char * ptr, int len)
{
c68: b5f0 push {r4, r5, r6, r7, lr}
c6a: 46c6 mov lr, r8
c6c: b500 push {lr}
c6e: 000e movs r6, r1
c70: 0015 movs r5, r2
int nChars = 0;
if ((file != 1) && (file != 2) && (file!=3)) {
c72: 3801 subs r0, #1
c74: 2802 cmp r0, #2
c76: d810 bhi.n c9a <_write+0x32>
return -1;
}
for (; len != 0; --len) {
c78: 2a00 cmp r2, #0
c7a: d011 beq.n ca0 <_write+0x38>
c7c: 2400 movs r4, #0
if (ptr_put(stdio_base, *ptr++) < 0) {
c7e: 4b0c ldr r3, [pc, #48] ; (cb0 <_write+0x48>)
c80: 4698 mov r8, r3
c82: 4f0c ldr r7, [pc, #48] ; (cb4 <_write+0x4c>)
c84: 4643 mov r3, r8
c86: 6818 ldr r0, [r3, #0]
c88: 5d31 ldrb r1, [r6, r4]
c8a: 683b ldr r3, [r7, #0]
c8c: 4798 blx r3
c8e: 2800 cmp r0, #0
c90: db08 blt.n ca4 <_write+0x3c>
return -1;
}
++nChars;
c92: 3401 adds r4, #1
for (; len != 0; --len) {
c94: 42a5 cmp r5, r4
c96: d1f5 bne.n c84 <_write+0x1c>
c98: e006 b.n ca8 <_write+0x40>
return -1;
c9a: 2401 movs r4, #1
c9c: 4264 negs r4, r4
c9e: e003 b.n ca8 <_write+0x40>
for (; len != 0; --len) {
ca0: 0014 movs r4, r2
ca2: e001 b.n ca8 <_write+0x40>
return -1;
ca4: 2401 movs r4, #1
ca6: 4264 negs r4, r4
}
return nChars;
}
ca8: 0020 movs r0, r4
caa: bc04 pop {r2}
cac: 4690 mov r8, r2
cae: bdf0 pop {r4, r5, r6, r7, pc}
cb0: 20000238 .word 0x20000238
cb4: 20000234 .word 0x20000234
00000cb8 <padc_init>:
COMPILER_ALIGNED(16)
DmacDescriptor adc_descriptor SECTION_DMAC_DESCRIPTOR;
void padc_init(void)
{
cb8: b530 push {r4, r5, lr}
cba: b095 sub sp, #84 ; 0x54
// configure adc
struct adc_config adc_conf;
adc_get_config_defaults(&adc_conf);
cbc: ac08 add r4, sp, #32
cbe: 0020 movs r0, r4
cc0: 4b2a ldr r3, [pc, #168] ; (d6c <padc_init+0xb4>)
cc2: 4798 blx r3
adc_conf.gain_factor = P_ADC_GAIN_FACTOR;
cc4: 2300 movs r3, #0
cc6: 60a3 str r3, [r4, #8]
adc_conf.resolution = P_ADC_RESOLUTION;
cc8: 7123 strb r3, [r4, #4]
adc_conf.clock_prescaler = P_ADC_CLOCK_PRESCALAR;
cca: 2280 movs r2, #128 ; 0x80
ccc: 0092 lsls r2, r2, #2
cce: 8062 strh r2, [r4, #2]
adc_conf.reference = P_ADC_VREF;
cd0: 2201 movs r2, #1
cd2: 7062 strb r2, [r4, #1]
adc_conf.positive_input = P_ADC_POSITIVE_INPUT_PIN;
cd4: 2104 movs r1, #4
cd6: 7321 strb r1, [r4, #12]
adc_conf.negative_input = P_ADC_NEGATIVE_INPUT_PIN;
cd8: 21c0 movs r1, #192 ; 0xc0
cda: 0149 lsls r1, r1, #5
cdc: 81e1 strh r1, [r4, #14]
adc_conf.freerunning = true;
cde: 7522 strb r2, [r4, #20]
adc_conf.left_adjust = false;
ce0: 74a3 strb r3, [r4, #18]
adc_init(&adc_mod, ADC, &adc_conf);
ce2: 4d23 ldr r5, [pc, #140] ; (d70 <padc_init+0xb8>)
ce4: 0022 movs r2, r4
ce6: 4923 ldr r1, [pc, #140] ; (d74 <padc_init+0xbc>)
ce8: 0028 movs r0, r5
cea: 4b23 ldr r3, [pc, #140] ; (d78 <padc_init+0xc0>)
cec: 4798 blx r3
struct adc_module *const module_inst)
{
Assert(module_inst);
Assert(module_inst->hw);
Adc *const adc_module = module_inst->hw;
cee: 682a ldr r2, [r5, #0]
cf0: 7e53 ldrb r3, [r2, #25]
while (adc_is_syncing(module_inst)) {
cf2: b25b sxtb r3, r3
cf4: 2b00 cmp r3, #0
cf6: dbfb blt.n cf0 <padc_init+0x38>
system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_ADC);
# endif
#endif
/* Disbale interrupt */
adc_module->INTENCLR.reg = ADC_INTENCLR_MASK;
cf8: 230f movs r3, #15
cfa: 7593 strb r3, [r2, #22]
/* Clear interrupt flag */
adc_module->INTFLAG.reg = ADC_INTFLAG_MASK;
cfc: 7613 strb r3, [r2, #24]
adc_module->CTRLA.reg |= ADC_CTRLA_ENABLE;
cfe: 7813 ldrb r3, [r2, #0]
d00: 2102 movs r1, #2
d02: 430b orrs r3, r1
d04: 7013 strb r3, [r2, #0]
Adc *const adc_module = module_inst->hw;
d06: 4b1a ldr r3, [pc, #104] ; (d70 <padc_init+0xb8>)
d08: 681a ldr r2, [r3, #0]
if (adc_module->STATUS.reg & ADC_STATUS_SYNCBUSY) {
d0a: 7e53 ldrb r3, [r2, #25]
while (adc_is_syncing(module_inst)) {
d0c: b25b sxtb r3, r3
d0e: 2b00 cmp r3, #0
d10: dbfb blt.n d0a <padc_init+0x52>
adc_enable(&adc_mod);
// configure dma resource
struct dma_resource_config dma_resource_conf;
dma_get_config_defaults(&dma_resource_conf);
d12: ac06 add r4, sp, #24
d14: 0020 movs r0, r4
d16: 4b19 ldr r3, [pc, #100] ; (d7c <padc_init+0xc4>)
d18: 4798 blx r3
dma_resource_conf.peripheral_trigger = ADC_DMAC_ID_RESRDY;
d1a: 2327 movs r3, #39 ; 0x27
d1c: 7063 strb r3, [r4, #1]
dma_resource_conf.trigger_action = DMA_TRIGGER_ACTION_BEAT;
d1e: 3b25 subs r3, #37 ; 0x25
d20: 70a3 strb r3, [r4, #2]
// allocate dma resource
dma_allocate(&adc_resource, &dma_resource_conf);
d22: 4d17 ldr r5, [pc, #92] ; (d80 <padc_init+0xc8>)
d24: 0021 movs r1, r4
d26: 0028 movs r0, r5
d28: 4b16 ldr r3, [pc, #88] ; (d84 <padc_init+0xcc>)
d2a: 4798 blx r3
static inline void dma_descriptor_get_config_defaults(struct dma_descriptor_config *config)
{
Assert(config);
/* Set descriptor as valid */
config->descriptor_valid = true;
d2c: 2201 movs r2, #1
d2e: 466b mov r3, sp
d30: 701a strb r2, [r3, #0]
/* Disable event output */
config->event_output_selection = DMA_EVENT_OUTPUT_DISABLE;
d32: 2300 movs r3, #0
d34: 4669 mov r1, sp
d36: 704b strb r3, [r1, #1]
/* No block action */
config->block_action = DMA_BLOCK_ACTION_NOACT;
d38: 708b strb r3, [r1, #2]
/* Set beat size to one byte */
config->beat_size = DMA_BEAT_SIZE_BYTE;
/* Enable source increment */
config->src_increment_enable = true;
/* Enable destination increment */
config->dst_increment_enable = true;
d3a: 714a strb r2, [r1, #5]
/* Step size is applied to the destination address */
config->step_selection = DMA_STEPSEL_DST;
d3c: 718b strb r3, [r1, #6]
/* Address increment is beat size multiplied by 1*/
config->step_size = DMA_ADDRESS_INCREMENT_STEP_SIZE_1;
d3e: 71cb strb r3, [r1, #7]
// setup transfer descriptor
struct dma_descriptor_config dma_desc_conf;
dma_descriptor_get_config_defaults(&dma_desc_conf);
dma_desc_conf.beat_size = DMA_BEAT_SIZE_HWORD; // 16 bit
d40: 70ca strb r2, [r1, #3]
dma_desc_conf.dst_increment_enable = true;
dma_desc_conf.src_increment_enable = false;
d42: 710b strb r3, [r1, #4]
dma_desc_conf.block_transfer_count = sizeof(raw_adc_values) / 2;
d44: 3310 adds r3, #16
d46: 810b strh r3, [r1, #8]
dma_desc_conf.source_address = (uint32_t)(&adc_mod.hw->RESULT.reg);
d48: 4b09 ldr r3, [pc, #36] ; (d70 <padc_init+0xb8>)
d4a: 681b ldr r3, [r3, #0]
d4c: 331a adds r3, #26
d4e: 9303 str r3, [sp, #12]
dma_desc_conf.destination_address = (uint32_t)(raw_adc_values + (sizeof(raw_adc_values) / 2));
d50: 4b0d ldr r3, [pc, #52] ; (d88 <padc_init+0xd0>)
d52: 3320 adds r3, #32
d54: 9304 str r3, [sp, #16]
dma_desc_conf.next_descriptor_address = (uint32_t)&adc_descriptor;
d56: 4c0d ldr r4, [pc, #52] ; (d8c <padc_init+0xd4>)
d58: 9405 str r4, [sp, #20]
dma_descriptor_create(&adc_descriptor, &dma_desc_conf);
d5a: 0020 movs r0, r4
d5c: 4b0c ldr r3, [pc, #48] ; (d90 <padc_init+0xd8>)
d5e: 4798 blx r3
dma_add_descriptor(&adc_resource, &adc_descriptor);
d60: 0021 movs r1, r4
d62: 0028 movs r0, r5
d64: 4b0b ldr r3, [pc, #44] ; (d94 <padc_init+0xdc>)
d66: 4798 blx r3
}
d68: b015 add sp, #84 ; 0x54
d6a: bd30 pop {r4, r5, pc}
d6c: 00000115 .word 0x00000115
d70: 2000010c .word 0x2000010c
d74: 42004000 .word 0x42004000
d78: 0000015d .word 0x0000015d
d7c: 00000601 .word 0x00000601
d80: 20000114 .word 0x20000114
d84: 00000611 .word 0x00000611
d88: 20000130 .word 0x20000130
d8c: 20000240 .word 0x20000240
d90: 000007e1 .word 0x000007e1
d94: 00000889 .word 0x00000889
00000d98 <padc_start>:
void padc_start(void)
{
d98: b510 push {r4, lr}
struct adc_module *const module_inst)
{
Assert(module_inst);
Assert(module_inst->hw);
Adc *const adc_module = module_inst->hw;
d9a: 4b09 ldr r3, [pc, #36] ; (dc0 <padc_start+0x28>)
d9c: 681a ldr r2, [r3, #0]
d9e: 7e53 ldrb r3, [r2, #25]
while (adc_is_syncing(module_inst)) {
da0: b25b sxtb r3, r3
da2: 2b00 cmp r3, #0
da4: dbfb blt.n d9e <padc_start+0x6>
/* Wait for synchronization */
}
adc_module->SWTRIG.reg |= ADC_SWTRIG_START;
da6: 7b13 ldrb r3, [r2, #12]
da8: 2102 movs r1, #2
daa: 430b orrs r3, r1
dac: 7313 strb r3, [r2, #12]
dae: 7e53 ldrb r3, [r2, #25]
while (adc_is_syncing(module_inst)) {
db0: b25b sxtb r3, r3
db2: 2b00 cmp r3, #0
db4: dbfb blt.n dae <padc_start+0x16>
adc_start_conversion(&adc_mod);
dma_start_transfer_job(&adc_resource);
db6: 4803 ldr r0, [pc, #12] ; (dc4 <padc_start+0x2c>)
db8: 4b03 ldr r3, [pc, #12] ; (dc8 <padc_start+0x30>)
dba: 4798 blx r3
}
dbc: bd10 pop {r4, pc}
dbe: 46c0 nop ; (mov r8, r8)
dc0: 2000010c .word 0x2000010c
dc4: 20000114 .word 0x20000114
dc8: 00000759 .word 0x00000759
00000dcc <padc_get_raw>:
uint16_t raw = padc_get_raw();
return (float)((float)raw / 4096.0f * P_ADC_VREF_VAL);
}
uint16_t padc_get_raw(void)
{
dcc: 4b05 ldr r3, [pc, #20] ; (de4 <padc_get_raw+0x18>)
dce: 0019 movs r1, r3
dd0: 3120 adds r1, #32
uint32_t sum = 0;
dd2: 2000 movs r0, #0
for(int ind = 0; ind < P_ADC_OVERSAMPLE_RATE; ind++)
{
sum += (uint32_t)raw_adc_values[ind];
dd4: 881a ldrh r2, [r3, #0]
dd6: 1880 adds r0, r0, r2
dd8: 3302 adds r3, #2
for(int ind = 0; ind < P_ADC_OVERSAMPLE_RATE; ind++)
dda: 428b cmp r3, r1
ddc: d1fa bne.n dd4 <padc_get_raw+0x8>
}
sum /= P_ADC_OVERSAMPLE_RATE;
dde: 0900 lsrs r0, r0, #4
return (uint16_t)sum;
de0: b280 uxth r0, r0
de2: 4770 bx lr
de4: 20000130 .word 0x20000130
00000de8 <padc_get_voltage>:
{
de8: b510 push {r4, lr}
uint16_t raw = padc_get_raw();
dea: 4b05 ldr r3, [pc, #20] ; (e00 <padc_get_voltage+0x18>)
dec: 4798 blx r3
return (float)((float)raw / 4096.0f * P_ADC_VREF_VAL);
dee: 4b05 ldr r3, [pc, #20] ; (e04 <padc_get_voltage+0x1c>)
df0: 4798 blx r3
df2: 4c05 ldr r4, [pc, #20] ; (e08 <padc_get_voltage+0x20>)
df4: 21e6 movs r1, #230 ; 0xe6
df6: 0589 lsls r1, r1, #22
df8: 47a0 blx r4
dfa: 4904 ldr r1, [pc, #16] ; (e0c <padc_get_voltage+0x24>)
dfc: 47a0 blx r4
}
dfe: bd10 pop {r4, pc}
e00: 00000dcd .word 0x00000dcd
e04: 000025b9 .word 0x000025b9
e08: 00001f61 .word 0x00001f61
e0c: 400eb368 .word 0x400eb368
00000e10 <usart_serial_getchar>:
* \param[out] c Destination for the read character.
*/
static inline void usart_serial_getchar(
struct usart_module *const module,
uint8_t *c)
{
e10: b570 push {r4, r5, r6, lr}
e12: b082 sub sp, #8
e14: 0005 movs r5, r0
e16: 000e movs r6, r1
uint16_t temp = 0;
e18: 2200 movs r2, #0
e1a: 466b mov r3, sp
e1c: 80da strh r2, [r3, #6]
while(STATUS_OK != usart_read_wait(module, &temp));
e1e: 4c06 ldr r4, [pc, #24] ; (e38 <usart_serial_getchar+0x28>)
e20: 466b mov r3, sp
e22: 1d99 adds r1, r3, #6
e24: 0028 movs r0, r5
e26: 47a0 blx r4
e28: 2800 cmp r0, #0
e2a: d1f9 bne.n e20 <usart_serial_getchar+0x10>
*c = temp;
e2c: 466b mov r3, sp
e2e: 3306 adds r3, #6
e30: 881b ldrh r3, [r3, #0]
e32: 7033 strb r3, [r6, #0]
}
e34: b002 add sp, #8
e36: bd70 pop {r4, r5, r6, pc}
e38: 000012a7 .word 0x000012a7
00000e3c <usart_serial_putchar>:
{
e3c: b570 push {r4, r5, r6, lr}
e3e: 0005 movs r5, r0
while(STATUS_OK !=usart_write_wait(module, c));
e40: b28c uxth r4, r1
e42: 4e03 ldr r6, [pc, #12] ; (e50 <usart_serial_putchar+0x14>)
e44: 0021 movs r1, r4
e46: 0028 movs r0, r5
e48: 47b0 blx r6
e4a: 2800 cmp r0, #0
e4c: d1fa bne.n e44 <usart_serial_putchar+0x8>
}
e4e: bd70 pop {r4, r5, r6, pc}
e50: 00001281 .word 0x00001281
00000e54 <pusart_init>:
#include "pusart.h"
void pusart_init(void)
{
e54: b5f8 push {r3, r4, r5, r6, r7, lr}
{
/* Sanity check arguments */
Assert(config);
/* Set default config in the config struct */
config->data_order = USART_DATAORDER_LSB;
e56: 4a2c ldr r2, [pc, #176] ; (f08 <pusart_init+0xb4>)
e58: 2380 movs r3, #128 ; 0x80
e5a: 05db lsls r3, r3, #23
e5c: 6013 str r3, [r2, #0]
config->transfer_mode = USART_TRANSFER_ASYNCHRONOUSLY;
e5e: 2300 movs r3, #0
e60: 6053 str r3, [r2, #4]
config->parity = USART_PARITY_NONE;
e62: 21ff movs r1, #255 ; 0xff
e64: 8111 strh r1, [r2, #8]
config->stopbits = USART_STOPBITS_1;
e66: 2100 movs r1, #0
e68: 7293 strb r3, [r2, #10]
config->character_size = USART_CHARACTER_SIZE_8BIT;
e6a: 72d3 strb r3, [r2, #11]
config->baudrate = 9600;
config->receiver_enable = true;
e6c: 2401 movs r4, #1
e6e: 2024 movs r0, #36 ; 0x24
e70: 5414 strb r4, [r2, r0]
config->transmitter_enable = true;
e72: 3001 adds r0, #1
e74: 5414 strb r4, [r2, r0]
config->clock_polarity_inverted = false;
e76: 3001 adds r0, #1
e78: 5413 strb r3, [r2, r0]
config->use_external_clock = false;
e7a: 3001 adds r0, #1
e7c: 5413 strb r3, [r2, r0]
config->ext_clock_freq = 0;
e7e: 6293 str r3, [r2, #40] ; 0x28
config->mux_setting = USART_RX_1_TX_2_XCK_3;
config->run_in_standby = false;
e80: 3005 adds r0, #5
e82: 5413 strb r3, [r2, r0]
config->generator_source = GCLK_GENERATOR_0;
e84: 3001 adds r0, #1
e86: 5413 strb r3, [r2, r0]
config->pinmux_pad0 = PINMUX_DEFAULT;
config->pinmux_pad1 = PINMUX_DEFAULT;
config->pinmux_pad2 = PINMUX_DEFAULT;
config->pinmux_pad3 = PINMUX_DEFAULT;
#ifdef FEATURE_USART_OVER_SAMPLE
config->sample_adjustment = USART_SAMPLE_ADJUSTMENT_7_8_9;
e88: 6153 str r3, [r2, #20]
config->sample_rate = USART_SAMPLE_RATE_16X_ARITHMETIC;
e8a: 8213 strh r3, [r2, #16]
#endif
#ifdef FEATURE_USART_LIN_SLAVE
config->lin_slave_enable = false;
e8c: 76d3 strb r3, [r2, #27]
config->lin_header_delay = LIN_MASTER_HEADER_DELAY_0;
config->lin_break_length = LIN_MASTER_BREAK_LENGTH_13_BIT;
#endif
#ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION
config->immediate_buffer_overflow_notification = false;
e8e: 7611 strb r1, [r2, #24]
#endif
#ifdef FEATURE_USART_START_FRAME_DECTION
config->start_frame_detection_enable = false;
e90: 7711 strb r1, [r2, #28]
#endif
#ifdef FEATURE_USART_IRDA
config->encoding_format_enable = false;
e92: 7651 strb r1, [r2, #25]
config->receive_pulse_length = 19;
e94: 2313 movs r3, #19
e96: 7693 strb r3, [r2, #26]
config->iso7816_config.inhibit_nack = ISO7816_INHIBIT_NACK_DISABLE;
config->iso7816_config.successive_recv_nack = ISO7816_SUCCESSIVE_RECV_NACK_DISABLE;
config->iso7816_config.max_iterations = 7;
#endif
#ifdef FEATURE_USART_COLLISION_DECTION
config->collision_detection_enable = false;
e98: 7751 strb r1, [r2, #29]
static struct usart_config uconf;
usart_get_config_defaults(&uconf);
uconf.pinmux_pad0 = DEBUG_USART_PINMUX_PAD0;
e9a: 4b1c ldr r3, [pc, #112] ; (f0c <pusart_init+0xb8>)
e9c: 6313 str r3, [r2, #48] ; 0x30
uconf.pinmux_pad1 = DEBUG_USART_PINMUX_PAD1;
e9e: 4b1c ldr r3, [pc, #112] ; (f10 <pusart_init+0xbc>)
ea0: 6353 str r3, [r2, #52] ; 0x34
uconf.pinmux_pad2 = DEBUG_USART_PINMUX_PAD2;
ea2: 2301 movs r3, #1
ea4: 425b negs r3, r3
ea6: 6393 str r3, [r2, #56] ; 0x38
uconf.pinmux_pad3 = DEBUG_USART_PINMUX_PAD3;
ea8: 63d3 str r3, [r2, #60] ; 0x3c
uconf.mux_setting = DEBUG_USART_MUX_SETTING;
eaa: 2380 movs r3, #128 ; 0x80
eac: 035b lsls r3, r3, #13
eae: 60d3 str r3, [r2, #12]
uconf.baudrate = DEBUG_USART_BAUDRATE;
eb0: 23e1 movs r3, #225 ; 0xe1
eb2: 025b lsls r3, r3, #9
eb4: 6213 str r3, [r2, #32]
static inline void stdio_serial_init(
struct usart_module *const module,
usart_inst_t const hw,
const struct usart_config *const config)
{
stdio_base = (void *)module;
eb6: 4d17 ldr r5, [pc, #92] ; (f14 <pusart_init+0xc0>)
eb8: 4b17 ldr r3, [pc, #92] ; (f18 <pusart_init+0xc4>)
eba: 601d str r5, [r3, #0]
ptr_put = (int (*)(void volatile*,char))&usart_serial_putchar;
ebc: 4917 ldr r1, [pc, #92] ; (f1c <pusart_init+0xc8>)
ebe: 4b18 ldr r3, [pc, #96] ; (f20 <pusart_init+0xcc>)
ec0: 6019 str r1, [r3, #0]
ptr_get = (void (*)(void volatile*,char*))&usart_serial_getchar;
ec2: 4918 ldr r1, [pc, #96] ; (f24 <pusart_init+0xd0>)
ec4: 4b18 ldr r3, [pc, #96] ; (f28 <pusart_init+0xd4>)
ec6: 6019 str r1, [r3, #0]
if (usart_init(module, hw, config) == STATUS_OK) {
ec8: 4918 ldr r1, [pc, #96] ; (f2c <pusart_init+0xd8>)
eca: 0028 movs r0, r5
ecc: 4b18 ldr r3, [pc, #96] ; (f30 <pusart_init+0xdc>)
ece: 4798 blx r3
usart_serial_init(module, hw, config);
# if defined(__GNUC__)
// Specify that stdout and stdin should not be buffered.
setbuf(stdout, NULL);
ed0: 4f18 ldr r7, [pc, #96] ; (f34 <pusart_init+0xe0>)
ed2: 683b ldr r3, [r7, #0]
ed4: 6898 ldr r0, [r3, #8]
ed6: 2100 movs r1, #0
ed8: 4e17 ldr r6, [pc, #92] ; (f38 <pusart_init+0xe4>)
eda: 47b0 blx r6
setbuf(stdin, NULL);
edc: 683b ldr r3, [r7, #0]
ede: 6858 ldr r0, [r3, #4]
ee0: 2100 movs r1, #0
ee2: 47b0 blx r6
/* Sanity check arguments */
Assert(module);
Assert(module->hw);
/* Get a pointer to the hardware module instance */
SercomUsart *const usart_hw = &(module->hw->USART);
ee4: 682e ldr r6, [r5, #0]
#if USART_CALLBACK_MODE == true
/* Enable Global interrupt for module */
system_interrupt_enable(_sercom_get_interrupt_vector(module->hw));
ee6: 0030 movs r0, r6
ee8: 4b14 ldr r3, [pc, #80] ; (f3c <pusart_init+0xe8>)
eea: 4798 blx r3
NVIC->ISER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f));
eec: 231f movs r3, #31
eee: 4018 ands r0, r3
ef0: 4084 lsls r4, r0
ef2: 4b13 ldr r3, [pc, #76] ; (f40 <pusart_init+0xec>)
ef4: 601c str r4, [r3, #0]
SercomUsart *const usart_hw = &(module->hw->USART);
ef6: 682a ldr r2, [r5, #0]
return (usart_hw->SYNCBUSY.reg);
ef8: 69d3 ldr r3, [r2, #28]
while (usart_is_syncing(module)) {
efa: 2b00 cmp r3, #0
efc: d1fc bne.n ef8 <pusart_init+0xa4>
/* Wait until synchronization is complete */
_usart_wait_for_sync(module);
/* Enable USART module */
usart_hw->CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
efe: 6833 ldr r3, [r6, #0]
f00: 2202 movs r2, #2
f02: 4313 orrs r3, r2
f04: 6033 str r3, [r6, #0]
stdio_serial_init(&umod, DEBUG_USART_MODULE, &uconf);
usart_enable(&umod);
}
f06: bdf8 pop {r3, r4, r5, r6, r7, pc}
f08: 20000150 .word 0x20000150
f0c: 00160002 .word 0x00160002
f10: 00170002 .word 0x00170002
f14: 20000250 .word 0x20000250
f18: 20000238 .word 0x20000238
f1c: 00000e3d .word 0x00000e3d
f20: 20000234 .word 0x20000234
f24: 00000e11 .word 0x00000e11
f28: 20000230 .word 0x20000230
f2c: 42001400 .word 0x42001400
f30: 00000f45 .word 0x00000f45
f34: 20000018 .word 0x20000018
f38: 00002721 .word 0x00002721
f3c: 000014e5 .word 0x000014e5
f40: e000e100 .word 0xe000e100
00000f44 <usart_init>:
*/
enum status_code usart_init(
struct usart_module *const module,
Sercom *const hw,
const struct usart_config *const config)
{
f44: b5f0 push {r4, r5, r6, r7, lr}
f46: 46de mov lr, fp
f48: 4657 mov r7, sl
f4a: 464e mov r6, r9
f4c: 4645 mov r5, r8
f4e: b5e0 push {r5, r6, r7, lr}
f50: b091 sub sp, #68 ; 0x44
f52: 0005 movs r5, r0
f54: 000c movs r4, r1
f56: 0016 movs r6, r2
Assert(config);
enum status_code status_code = STATUS_OK;
/* Assign module pointer to software instance struct */
module->hw = hw;
f58: 6029 str r1, [r5, #0]
/* Get a pointer to the hardware module instance */
SercomUsart *const usart_hw = &(module->hw->USART);
uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
f5a: 0008 movs r0, r1
f5c: 4bba ldr r3, [pc, #744] ; (1248 <usart_init+0x304>)
f5e: 4798 blx r3
f60: 0002 movs r2, r0
#else
pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos;
gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
#endif
if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_SWRST) {
f62: 6823 ldr r3, [r4, #0]
/* The module is busy resetting itself */
return STATUS_BUSY;
f64: 2005 movs r0, #5
if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_SWRST) {
f66: 07db lsls r3, r3, #31
f68: d506 bpl.n f78 <usart_init+0x34>
_sercom_set_handler(instance_index, _usart_interrupt_handler);
_sercom_instances[instance_index] = module;
#endif
return status_code;
}
f6a: b011 add sp, #68 ; 0x44
f6c: bc3c pop {r2, r3, r4, r5}
f6e: 4690 mov r8, r2
f70: 4699 mov r9, r3
f72: 46a2 mov sl, r4
f74: 46ab mov fp, r5
f76: bdf0 pop {r4, r5, r6, r7, pc}
if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_ENABLE) {
f78: 6823 ldr r3, [r4, #0]
return STATUS_ERR_DENIED;
f7a: 3017 adds r0, #23
if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_ENABLE) {
f7c: 079b lsls r3, r3, #30
f7e: d4f4 bmi.n f6a <usart_init+0x26>
PM->APBCMASK.reg |= mask;
f80: 49b2 ldr r1, [pc, #712] ; (124c <usart_init+0x308>)
f82: 6a08 ldr r0, [r1, #32]
pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos;
f84: 1c97 adds r7, r2, #2
system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
f86: 2301 movs r3, #1
f88: 40bb lsls r3, r7
f8a: 4303 orrs r3, r0
f8c: 620b str r3, [r1, #32]
gclk_chan_conf.source_generator = config->generator_source;
f8e: a90f add r1, sp, #60 ; 0x3c
f90: 272d movs r7, #45 ; 0x2d
f92: 5df3 ldrb r3, [r6, r7]
f94: 700b strb r3, [r1, #0]
gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
f96: 3214 adds r2, #20
system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
f98: b2d3 uxtb r3, r2
f9a: 9302 str r3, [sp, #8]
f9c: 0018 movs r0, r3
f9e: 4bac ldr r3, [pc, #688] ; (1250 <usart_init+0x30c>)
fa0: 4798 blx r3
system_gclk_chan_enable(gclk_index);
fa2: 9802 ldr r0, [sp, #8]
fa4: 4bab ldr r3, [pc, #684] ; (1254 <usart_init+0x310>)
fa6: 4798 blx r3
sercom_set_gclk_generator(config->generator_source, false);
fa8: 5df0 ldrb r0, [r6, r7]
faa: 2100 movs r1, #0
fac: 4baa ldr r3, [pc, #680] ; (1258 <usart_init+0x314>)
fae: 4798 blx r3
module->character_size = config->character_size;
fb0: 7af3 ldrb r3, [r6, #11]
fb2: 716b strb r3, [r5, #5]
module->receiver_enabled = config->receiver_enable;
fb4: 2324 movs r3, #36 ; 0x24
fb6: 5cf3 ldrb r3, [r6, r3]
fb8: 71ab strb r3, [r5, #6]
module->transmitter_enabled = config->transmitter_enable;
fba: 2325 movs r3, #37 ; 0x25
fbc: 5cf3 ldrb r3, [r6, r3]
fbe: 71eb strb r3, [r5, #7]
module->lin_slave_enabled = config->lin_slave_enable;
fc0: 7ef3 ldrb r3, [r6, #27]
fc2: 722b strb r3, [r5, #8]
module->start_frame_detection_enabled = config->start_frame_detection_enable;
fc4: 7f33 ldrb r3, [r6, #28]
fc6: 726b strb r3, [r5, #9]
SercomUsart *const usart_hw = &(module->hw->USART);
fc8: 682b ldr r3, [r5, #0]
fca: 4698 mov r8, r3
uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
fcc: 0018 movs r0, r3
fce: 4b9e ldr r3, [pc, #632] ; (1248 <usart_init+0x304>)
fd0: 4798 blx r3
gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
fd2: 3014 adds r0, #20
uint16_t baud = 0;
fd4: 2200 movs r2, #0
fd6: 230e movs r3, #14
fd8: a906 add r1, sp, #24
fda: 468c mov ip, r1
fdc: 4463 add r3, ip
fde: 801a strh r2, [r3, #0]
switch (config->sample_rate) {
fe0: 8a32 ldrh r2, [r6, #16]
fe2: 9202 str r2, [sp, #8]
fe4: 2380 movs r3, #128 ; 0x80
fe6: 01db lsls r3, r3, #7
fe8: 429a cmp r2, r3
fea: d100 bne.n fee <usart_init+0xaa>
fec: e09a b.n 1124 <usart_init+0x1e0>
fee: d90f bls.n 1010 <usart_init+0xcc>
ff0: 23c0 movs r3, #192 ; 0xc0
ff2: 01db lsls r3, r3, #7
ff4: 9a02 ldr r2, [sp, #8]
ff6: 429a cmp r2, r3
ff8: d100 bne.n ffc <usart_init+0xb8>
ffa: e08e b.n 111a <usart_init+0x1d6>
ffc: 2380 movs r3, #128 ; 0x80
ffe: 021b lsls r3, r3, #8
1000: 429a cmp r2, r3
1002: d000 beq.n 1006 <usart_init+0xc2>
1004: e11b b.n 123e <usart_init+0x2fa>
sample_num = SERCOM_ASYNC_SAMPLE_NUM_3;
1006: 2303 movs r3, #3
1008: 9306 str r3, [sp, #24]
mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
100a: 2300 movs r3, #0
100c: 9307 str r3, [sp, #28]
100e: e008 b.n 1022 <usart_init+0xde>
switch (config->sample_rate) {
1010: 2380 movs r3, #128 ; 0x80
1012: 019b lsls r3, r3, #6
1014: 429a cmp r2, r3
1016: d000 beq.n 101a <usart_init+0xd6>
1018: e111 b.n 123e <usart_init+0x2fa>
sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
101a: 2310 movs r3, #16
101c: 9306 str r3, [sp, #24]
mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL;
101e: 3b0f subs r3, #15
1020: 9307 str r3, [sp, #28]
ctrla = (uint32_t)config->data_order |
1022: 6833 ldr r3, [r6, #0]
1024: 9305 str r3, [sp, #20]
(uint32_t)config->mux_setting |
1026: 68f3 ldr r3, [r6, #12]
1028: 469b mov fp, r3
config->sample_adjustment |
102a: 6973 ldr r3, [r6, #20]
102c: 9303 str r3, [sp, #12]
(config->immediate_buffer_overflow_notification << SERCOM_USART_CTRLA_IBON_Pos) |
102e: 7e33 ldrb r3, [r6, #24]
1030: 9304 str r3, [sp, #16]
(config->clock_polarity_inverted << SERCOM_USART_CTRLA_CPOL_Pos);
1032: 2326 movs r3, #38 ; 0x26
1034: 5cf3 ldrb r3, [r6, r3]
1036: 469a mov sl, r3
transfer_mode = (uint32_t)config->transfer_mode;
1038: 6873 ldr r3, [r6, #4]
103a: 4699 mov r9, r3
switch (transfer_mode)
103c: 2b00 cmp r3, #0
103e: d100 bne.n 1042 <usart_init+0xfe>
1040: e09c b.n 117c <usart_init+0x238>
1042: 2380 movs r3, #128 ; 0x80
1044: 055b lsls r3, r3, #21
1046: 4599 cmp r9, r3
1048: d100 bne.n 104c <usart_init+0x108>
104a: e080 b.n 114e <usart_init+0x20a>
if(config->encoding_format_enable) {
104c: 7e73 ldrb r3, [r6, #25]
104e: 2b00 cmp r3, #0
1050: d002 beq.n 1058 <usart_init+0x114>
usart_hw->RXPL.reg = config->receive_pulse_length;
1052: 7eb3 ldrb r3, [r6, #26]
1054: 4642 mov r2, r8
1056: 7393 strb r3, [r2, #14]
usart_hw->BAUD.reg = baud;
1058: 230e movs r3, #14
105a: aa06 add r2, sp, #24
105c: 4694 mov ip, r2
105e: 4463 add r3, ip
1060: 881b ldrh r3, [r3, #0]
1062: 4642 mov r2, r8
1064: 8193 strh r3, [r2, #12]
ctrla |= transfer_mode;
1066: 9b05 ldr r3, [sp, #20]
1068: 465a mov r2, fp
106a: 4313 orrs r3, r2
106c: 9a03 ldr r2, [sp, #12]
106e: 4313 orrs r3, r2
1070: 464a mov r2, r9
1072: 4313 orrs r3, r2
1074: 9f02 ldr r7, [sp, #8]
1076: 431f orrs r7, r3
(config->immediate_buffer_overflow_notification << SERCOM_USART_CTRLA_IBON_Pos) |
1078: 9b04 ldr r3, [sp, #16]
107a: 021b lsls r3, r3, #8
ctrla |= transfer_mode;
107c: 431f orrs r7, r3
(config->clock_polarity_inverted << SERCOM_USART_CTRLA_CPOL_Pos);
107e: 4653 mov r3, sl
1080: 075b lsls r3, r3, #29
ctrla |= transfer_mode;
1082: 431f orrs r7, r3
if (config->use_external_clock == false) {
1084: 2327 movs r3, #39 ; 0x27
1086: 5cf3 ldrb r3, [r6, r3]
1088: 2b00 cmp r3, #0
108a: d101 bne.n 1090 <usart_init+0x14c>
ctrla |= SERCOM_USART_CTRLA_MODE(0x1);
108c: 3304 adds r3, #4
108e: 431f orrs r7, r3
(config->encoding_format_enable << SERCOM_USART_CTRLB_ENC_Pos) |
1090: 7e73 ldrb r3, [r6, #25]
1092: 029b lsls r3, r3, #10
(config->start_frame_detection_enable << SERCOM_USART_CTRLB_SFDE_Pos) |
1094: 7f32 ldrb r2, [r6, #28]
1096: 0252 lsls r2, r2, #9
(config->encoding_format_enable << SERCOM_USART_CTRLB_ENC_Pos) |
1098: 4313 orrs r3, r2
(config->collision_detection_enable << SERCOM_USART_CTRLB_COLDEN_Pos) |
109a: 7f72 ldrb r2, [r6, #29]
109c: 0212 lsls r2, r2, #8
(config->start_frame_detection_enable << SERCOM_USART_CTRLB_SFDE_Pos) |
109e: 4313 orrs r3, r2
(config->receiver_enable << SERCOM_USART_CTRLB_RXEN_Pos) |
10a0: 2224 movs r2, #36 ; 0x24
10a2: 5cb2 ldrb r2, [r6, r2]
10a4: 0452 lsls r2, r2, #17
(config->collision_detection_enable << SERCOM_USART_CTRLB_COLDEN_Pos) |
10a6: 4313 orrs r3, r2
(config->transmitter_enable << SERCOM_USART_CTRLB_TXEN_Pos);
10a8: 2225 movs r2, #37 ; 0x25
10aa: 5cb2 ldrb r2, [r6, r2]
10ac: 0412 lsls r2, r2, #16
(config->receiver_enable << SERCOM_USART_CTRLB_RXEN_Pos) |
10ae: 4313 orrs r3, r2
ctrlb |= (uint32_t)config->character_size;
10b0: 7ab1 ldrb r1, [r6, #10]
10b2: 7af2 ldrb r2, [r6, #11]
10b4: 4311 orrs r1, r2
10b6: 4319 orrs r1, r3
if (config->parity != USART_PARITY_NONE) {
10b8: 8933 ldrh r3, [r6, #8]
10ba: 2bff cmp r3, #255 ; 0xff
10bc: d100 bne.n 10c0 <usart_init+0x17c>
10be: e081 b.n 11c4 <usart_init+0x280>
ctrla |= SERCOM_USART_CTRLA_FORM(1);
10c0: 2280 movs r2, #128 ; 0x80
10c2: 0452 lsls r2, r2, #17
10c4: 4317 orrs r7, r2
ctrlb |= config->parity;
10c6: 4319 orrs r1, r3
if (config->run_in_standby || system_is_debugger_present()) {
10c8: 232c movs r3, #44 ; 0x2c
10ca: 5cf3 ldrb r3, [r6, r3]
10cc: 2b00 cmp r3, #0
10ce: d103 bne.n 10d8 <usart_init+0x194>
* \retval false Debugger is not connected to the system
*
*/
static inline bool system_is_debugger_present(void)
{
return DSU->STATUSB.reg & DSU_STATUSB_DBGPRES;
10d0: 4b62 ldr r3, [pc, #392] ; (125c <usart_init+0x318>)
10d2: 789b ldrb r3, [r3, #2]
10d4: 079b lsls r3, r3, #30
10d6: d501 bpl.n 10dc <usart_init+0x198>
ctrla |= SERCOM_USART_CTRLA_RUNSTDBY;
10d8: 2380 movs r3, #128 ; 0x80
10da: 431f orrs r7, r3
SercomUsart *const usart_hw = &(module->hw->USART);
10dc: 682a ldr r2, [r5, #0]
return (usart_hw->SYNCBUSY.reg);
10de: 69d3 ldr r3, [r2, #28]
while (usart_is_syncing(module)) {
10e0: 2b00 cmp r3, #0
10e2: d1fc bne.n 10de <usart_init+0x19a>
usart_hw->CTRLB.reg = ctrlb;
10e4: 4643 mov r3, r8
10e6: 6059 str r1, [r3, #4]
SercomUsart *const usart_hw = &(module->hw->USART);
10e8: 682a ldr r2, [r5, #0]
return (usart_hw->SYNCBUSY.reg);
10ea: 69d3 ldr r3, [r2, #28]
while (usart_is_syncing(module)) {
10ec: 2b00 cmp r3, #0
10ee: d1fc bne.n 10ea <usart_init+0x1a6>
usart_hw->CTRLA.reg = ctrla;
10f0: 4643 mov r3, r8
10f2: 601f str r7, [r3, #0]
config->mux_position = SYSTEM_PINMUX_GPIO;
10f4: ab0e add r3, sp, #56 ; 0x38
10f6: 2280 movs r2, #128 ; 0x80
10f8: 701a strb r2, [r3, #0]
config->direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
10fa: 2200 movs r2, #0
10fc: 705a strb r2, [r3, #1]
config->powersave = false;
10fe: 70da strb r2, [r3, #3]
pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE;
1100: 709a strb r2, [r3, #2]
uint32_t pad_pinmuxes[] = {
1102: 6b33 ldr r3, [r6, #48] ; 0x30
1104: 930a str r3, [sp, #40] ; 0x28
1106: 6b73 ldr r3, [r6, #52] ; 0x34
1108: 930b str r3, [sp, #44] ; 0x2c
110a: 6bb3 ldr r3, [r6, #56] ; 0x38
110c: 930c str r3, [sp, #48] ; 0x30
110e: 6bf3 ldr r3, [r6, #60] ; 0x3c
1110: 9302 str r3, [sp, #8]
1112: 930d str r3, [sp, #52] ; 0x34
1114: 2700 movs r7, #0
uint32_t current_pinmux = pad_pinmuxes[pad];
1116: ae0a add r6, sp, #40 ; 0x28
1118: e063 b.n 11e2 <usart_init+0x29e>
sample_num = SERCOM_ASYNC_SAMPLE_NUM_8;
111a: 2308 movs r3, #8
111c: 9306 str r3, [sp, #24]
mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL;
111e: 3b07 subs r3, #7
1120: 9307 str r3, [sp, #28]
1122: e77e b.n 1022 <usart_init+0xde>
ctrla = (uint32_t)config->data_order |
1124: 6833 ldr r3, [r6, #0]
1126: 9305 str r3, [sp, #20]
(uint32_t)config->mux_setting |
1128: 68f3 ldr r3, [r6, #12]
112a: 469b mov fp, r3
config->sample_adjustment |
112c: 6973 ldr r3, [r6, #20]
112e: 9303 str r3, [sp, #12]
(config->immediate_buffer_overflow_notification << SERCOM_USART_CTRLA_IBON_Pos) |
1130: 7e33 ldrb r3, [r6, #24]
1132: 9304 str r3, [sp, #16]
(config->clock_polarity_inverted << SERCOM_USART_CTRLA_CPOL_Pos);
1134: 2326 movs r3, #38 ; 0x26
1136: 5cf3 ldrb r3, [r6, r3]
1138: 469a mov sl, r3
transfer_mode = (uint32_t)config->transfer_mode;
113a: 6873 ldr r3, [r6, #4]
113c: 4699 mov r9, r3
switch (transfer_mode)
113e: 2b00 cmp r3, #0
1140: d018 beq.n 1174 <usart_init+0x230>
1142: 2380 movs r3, #128 ; 0x80
1144: 055b lsls r3, r3, #21
1146: 4599 cmp r9, r3
1148: d001 beq.n 114e <usart_init+0x20a>
enum status_code status_code = STATUS_OK;
114a: 2000 movs r0, #0
114c: e025 b.n 119a <usart_init+0x256>
if (!config->use_external_clock) {
114e: 2327 movs r3, #39 ; 0x27
1150: 5cf3 ldrb r3, [r6, r3]
1152: 2b00 cmp r3, #0
1154: d000 beq.n 1158 <usart_init+0x214>
1156: e779 b.n 104c <usart_init+0x108>
status_code = _sercom_get_sync_baud_val(config->baudrate,
1158: 6a33 ldr r3, [r6, #32]
115a: 001f movs r7, r3
115c: b2c0 uxtb r0, r0
115e: 4b40 ldr r3, [pc, #256] ; (1260 <usart_init+0x31c>)
1160: 4798 blx r3
1162: 0001 movs r1, r0
1164: 220e movs r2, #14
1166: ab06 add r3, sp, #24
1168: 469c mov ip, r3
116a: 4462 add r2, ip
116c: 0038 movs r0, r7
116e: 4b3d ldr r3, [pc, #244] ; (1264 <usart_init+0x320>)
1170: 4798 blx r3
1172: e012 b.n 119a <usart_init+0x256>
sample_num = SERCOM_ASYNC_SAMPLE_NUM_8;
1174: 2308 movs r3, #8
1176: 9306 str r3, [sp, #24]
mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
1178: 2300 movs r3, #0
117a: 9307 str r3, [sp, #28]
if (config->use_external_clock) {
117c: 2327 movs r3, #39 ; 0x27
117e: 5cf3 ldrb r3, [r6, r3]
1180: 2b00 cmp r3, #0
1182: d00e beq.n 11a2 <usart_init+0x25e>
status_code =
1184: 9b06 ldr r3, [sp, #24]
1186: 9300 str r3, [sp, #0]
1188: 9b07 ldr r3, [sp, #28]
118a: 220e movs r2, #14
118c: a906 add r1, sp, #24
118e: 468c mov ip, r1
1190: 4462 add r2, ip
1192: 6ab1 ldr r1, [r6, #40] ; 0x28
1194: 6a30 ldr r0, [r6, #32]
1196: 4f34 ldr r7, [pc, #208] ; (1268 <usart_init+0x324>)
1198: 47b8 blx r7
if (status_code != STATUS_OK) {
119a: 2800 cmp r0, #0
119c: d000 beq.n 11a0 <usart_init+0x25c>
119e: e6e4 b.n f6a <usart_init+0x26>
11a0: e754 b.n 104c <usart_init+0x108>
_sercom_get_async_baud_val(config->baudrate,
11a2: 6a33 ldr r3, [r6, #32]
11a4: 001f movs r7, r3
11a6: b2c0 uxtb r0, r0
11a8: 4b2d ldr r3, [pc, #180] ; (1260 <usart_init+0x31c>)
11aa: 4798 blx r3
11ac: 0001 movs r1, r0
status_code =
11ae: 9b06 ldr r3, [sp, #24]
11b0: 9300 str r3, [sp, #0]
11b2: 9b07 ldr r3, [sp, #28]
11b4: 220e movs r2, #14
11b6: a806 add r0, sp, #24
11b8: 4684 mov ip, r0
11ba: 4462 add r2, ip
11bc: 0038 movs r0, r7
11be: 4f2a ldr r7, [pc, #168] ; (1268 <usart_init+0x324>)
11c0: 47b8 blx r7
11c2: e7ea b.n 119a <usart_init+0x256>
if(config->lin_slave_enable) {
11c4: 7ef3 ldrb r3, [r6, #27]
11c6: 2b00 cmp r3, #0
11c8: d100 bne.n 11cc <usart_init+0x288>
11ca: e77d b.n 10c8 <usart_init+0x184>
ctrla |= SERCOM_USART_CTRLA_FORM(0x4);
11cc: 2380 movs r3, #128 ; 0x80
11ce: 04db lsls r3, r3, #19
11d0: 431f orrs r7, r3
11d2: e779 b.n 10c8 <usart_init+0x184>
current_pinmux = _sercom_get_default_pad(hw, pad);
11d4: 0020 movs r0, r4
11d6: 4b25 ldr r3, [pc, #148] ; (126c <usart_init+0x328>)
11d8: 4798 blx r3
11da: e007 b.n 11ec <usart_init+0x2a8>
11dc: 3701 adds r7, #1
for (uint8_t pad = 0; pad < 4; pad++) {
11de: 2f04 cmp r7, #4
11e0: d00d beq.n 11fe <usart_init+0x2ba>
11e2: b2f9 uxtb r1, r7
uint32_t current_pinmux = pad_pinmuxes[pad];
11e4: 00bb lsls r3, r7, #2
11e6: 5998 ldr r0, [r3, r6]
if (current_pinmux == PINMUX_DEFAULT) {
11e8: 2800 cmp r0, #0
11ea: d0f3 beq.n 11d4 <usart_init+0x290>
if (current_pinmux != PINMUX_UNUSED) {
11ec: 1c43 adds r3, r0, #1
11ee: d0f5 beq.n 11dc <usart_init+0x298>
pin_conf.mux_position = current_pinmux & 0xFFFF;
11f0: a90e add r1, sp, #56 ; 0x38
11f2: 7008 strb r0, [r1, #0]
system_pinmux_pin_set_config(current_pinmux >> 16, &pin_conf);
11f4: 0c00 lsrs r0, r0, #16
11f6: b2c0 uxtb r0, r0
11f8: 4b1d ldr r3, [pc, #116] ; (1270 <usart_init+0x32c>)
11fa: 4798 blx r3
11fc: e7ee b.n 11dc <usart_init+0x298>
module->callback[i] = NULL;
11fe: 2300 movs r3, #0
1200: 60eb str r3, [r5, #12]
1202: 612b str r3, [r5, #16]
1204: 616b str r3, [r5, #20]
1206: 61ab str r3, [r5, #24]
1208: 61eb str r3, [r5, #28]
120a: 622b str r3, [r5, #32]
module->tx_buffer_ptr = NULL;
120c: 62ab str r3, [r5, #40] ; 0x28
module->rx_buffer_ptr = NULL;
120e: 626b str r3, [r5, #36] ; 0x24
module->remaining_tx_buffer_length = 0x0000;
1210: 2200 movs r2, #0
1212: 85eb strh r3, [r5, #46] ; 0x2e
module->remaining_rx_buffer_length = 0x0000;
1214: 85ab strh r3, [r5, #44] ; 0x2c
module->callback_reg_mask = 0x00;
1216: 3330 adds r3, #48 ; 0x30
1218: 54ea strb r2, [r5, r3]
module->callback_enable_mask = 0x00;
121a: 3301 adds r3, #1
121c: 54ea strb r2, [r5, r3]
module->rx_status = STATUS_OK;
121e: 3301 adds r3, #1
1220: 54ea strb r2, [r5, r3]
module->tx_status = STATUS_OK;
1222: 3301 adds r3, #1
1224: 54ea strb r2, [r5, r3]
uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw);
1226: 6828 ldr r0, [r5, #0]
1228: 4b07 ldr r3, [pc, #28] ; (1248 <usart_init+0x304>)
122a: 4798 blx r3
122c: 0004 movs r4, r0
_sercom_set_handler(instance_index, _usart_interrupt_handler);
122e: 4911 ldr r1, [pc, #68] ; (1274 <usart_init+0x330>)
1230: 4b11 ldr r3, [pc, #68] ; (1278 <usart_init+0x334>)
1232: 4798 blx r3
_sercom_instances[instance_index] = module;
1234: 00a4 lsls r4, r4, #2
1236: 4b11 ldr r3, [pc, #68] ; (127c <usart_init+0x338>)
1238: 50e5 str r5, [r4, r3]
return status_code;
123a: 2000 movs r0, #0
123c: e695 b.n f6a <usart_init+0x26>
enum sercom_asynchronous_sample_num sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
123e: 2310 movs r3, #16
1240: 9306 str r3, [sp, #24]
enum sercom_asynchronous_operation_mode mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
1242: 2300 movs r3, #0
1244: 9307 str r3, [sp, #28]
1246: e6ec b.n 1022 <usart_init+0xde>
1248: 00000bed .word 0x00000bed
124c: 40000400 .word 0x40000400
1250: 00001af5 .word 0x00001af5
1254: 00001a69 .word 0x00001a69
1258: 00000a29 .word 0x00000a29
125c: 41002000 .word 0x41002000
1260: 00001b11 .word 0x00001b11
1264: 0000096d .word 0x0000096d
1268: 00000995 .word 0x00000995
126c: 00000a75 .word 0x00000a75
1270: 00001bed .word 0x00001bed
1274: 00001311 .word 0x00001311
1278: 000014a9 .word 0x000014a9
127c: 20000284 .word 0x20000284
00001280 <usart_write_wait>:
/* Get a pointer to the hardware module instance */
SercomUsart *const usart_hw = &(module->hw->USART);
/* Check that the transmitter is enabled */
if (!(module->transmitter_enabled)) {
1280: 79c2 ldrb r2, [r0, #7]
return STATUS_ERR_DENIED;
1282: 231c movs r3, #28
if (!(module->transmitter_enabled)) {
1284: 2a00 cmp r2, #0
1286: d101 bne.n 128c <usart_write_wait+0xc>
while (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC)) {
/* Wait until data is sent */
}
return STATUS_OK;
}
1288: 0018 movs r0, r3
128a: 4770 bx lr
if (module->remaining_tx_buffer_length > 0) {
128c: 8dc2 ldrh r2, [r0, #46] ; 0x2e
128e: b292 uxth r2, r2
return STATUS_BUSY;
1290: 3b17 subs r3, #23
if (module->remaining_tx_buffer_length > 0) {
1292: 2a00 cmp r2, #0
1294: d1f8 bne.n 1288 <usart_write_wait+0x8>
SercomUsart *const usart_hw = &(module->hw->USART);
1296: 6802 ldr r2, [r0, #0]
usart_hw->DATA.reg = tx_data;
1298: 8511 strh r1, [r2, #40] ; 0x28
while (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC)) {
129a: 2102 movs r1, #2
129c: 7e13 ldrb r3, [r2, #24]
129e: 420b tst r3, r1
12a0: d0fc beq.n 129c <usart_write_wait+0x1c>
return STATUS_OK;
12a2: 2300 movs r3, #0
12a4: e7f0 b.n 1288 <usart_write_wait+0x8>
000012a6 <usart_read_wait>:
/* Get a pointer to the hardware module instance */
SercomUsart *const usart_hw = &(module->hw->USART);
/* Check that the receiver is enabled */
if (!(module->receiver_enabled)) {
12a6: 7982 ldrb r2, [r0, #6]
return STATUS_ERR_DENIED;
12a8: 231c movs r3, #28
if (!(module->receiver_enabled)) {
12aa: 2a00 cmp r2, #0
12ac: d101 bne.n 12b2 <usart_read_wait+0xc>
/* Read data from USART module */
*rx_data = usart_hw->DATA.reg;
return STATUS_OK;
}
12ae: 0018 movs r0, r3
12b0: 4770 bx lr
if (module->remaining_rx_buffer_length > 0) {
12b2: 8d82 ldrh r2, [r0, #44] ; 0x2c
12b4: b292 uxth r2, r2
return STATUS_BUSY;
12b6: 3b17 subs r3, #23
if (module->remaining_rx_buffer_length > 0) {
12b8: 2a00 cmp r2, #0
12ba: d1f8 bne.n 12ae <usart_read_wait+0x8>
SercomUsart *const usart_hw = &(module->hw->USART);
12bc: 6802 ldr r2, [r0, #0]
if (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC)) {
12be: 7e10 ldrb r0, [r2, #24]
12c0: 0740 lsls r0, r0, #29
12c2: d5f4 bpl.n 12ae <usart_read_wait+0x8>
error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);
12c4: 8b53 ldrh r3, [r2, #26]
12c6: b2db uxtb r3, r3
if (error_code) {
12c8: 0698 lsls r0, r3, #26
12ca: d01d beq.n 1308 <usart_read_wait+0x62>
if (error_code & SERCOM_USART_STATUS_FERR) {
12cc: 0798 lsls r0, r3, #30
12ce: d503 bpl.n 12d8 <usart_read_wait+0x32>
usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR;
12d0: 2302 movs r3, #2
12d2: 8353 strh r3, [r2, #26]
return STATUS_ERR_BAD_FORMAT;
12d4: 3318 adds r3, #24
12d6: e7ea b.n 12ae <usart_read_wait+0x8>
} else if (error_code & SERCOM_USART_STATUS_BUFOVF) {
12d8: 0758 lsls r0, r3, #29
12da: d503 bpl.n 12e4 <usart_read_wait+0x3e>
usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
12dc: 2304 movs r3, #4
12de: 8353 strh r3, [r2, #26]
return STATUS_ERR_OVERFLOW;
12e0: 331a adds r3, #26
12e2: e7e4 b.n 12ae <usart_read_wait+0x8>
} else if (error_code & SERCOM_USART_STATUS_PERR) {
12e4: 07d8 lsls r0, r3, #31
12e6: d503 bpl.n 12f0 <usart_read_wait+0x4a>
usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR;
12e8: 2301 movs r3, #1
12ea: 8353 strh r3, [r2, #26]
return STATUS_ERR_BAD_DATA;
12ec: 3312 adds r3, #18
12ee: e7de b.n 12ae <usart_read_wait+0x8>
else if (error_code & SERCOM_USART_STATUS_ISF) {
12f0: 06d8 lsls r0, r3, #27
12f2: d503 bpl.n 12fc <usart_read_wait+0x56>
usart_hw->STATUS.reg = SERCOM_USART_STATUS_ISF;
12f4: 2310 movs r3, #16
12f6: 8353 strh r3, [r2, #26]
return STATUS_ERR_PROTOCOL;
12f8: 3332 adds r3, #50 ; 0x32
12fa: e7d8 b.n 12ae <usart_read_wait+0x8>
else if (error_code & SERCOM_USART_STATUS_COLL) {
12fc: 069b lsls r3, r3, #26
12fe: d503 bpl.n 1308 <usart_read_wait+0x62>
usart_hw->STATUS.reg = SERCOM_USART_STATUS_COLL;
1300: 2320 movs r3, #32
1302: 8353 strh r3, [r2, #26]
return STATUS_ERR_PACKET_COLLISION;
1304: 3321 adds r3, #33 ; 0x21
1306: e7d2 b.n 12ae <usart_read_wait+0x8>
*rx_data = usart_hw->DATA.reg;
1308: 8d13 ldrh r3, [r2, #40] ; 0x28
130a: 800b strh r3, [r1, #0]
return STATUS_OK;
130c: 2300 movs r3, #0
130e: e7ce b.n 12ae <usart_read_wait+0x8>
00001310 <_usart_interrupt_handler>:
* \param[in] instance ID of the SERCOM instance calling the interrupt
* handler.
*/
void _usart_interrupt_handler(
uint8_t instance)
{
1310: b5f8 push {r3, r4, r5, r6, r7, lr}
uint16_t callback_status;
uint8_t error_code;
/* Get device instance from the look-up table */
struct usart_module *module
1312: 0080 lsls r0, r0, #2
1314: 4b62 ldr r3, [pc, #392] ; (14a0 <_usart_interrupt_handler+0x190>)
1316: 58c5 ldr r5, [r0, r3]
= (struct usart_module *)_sercom_instances[instance];
/* Pointer to the hardware module instance */
SercomUsart *const usart_hw
= &(module->hw->USART);
1318: 682c ldr r4, [r5, #0]
return (usart_hw->SYNCBUSY.reg);
131a: 69e3 ldr r3, [r4, #28]
while (usart_is_syncing(module)) {
131c: 2b00 cmp r3, #0
131e: d1fc bne.n 131a <_usart_interrupt_handler+0xa>
/* Wait for the synchronization to complete */
_usart_wait_for_sync(module);
/* Read and mask interrupt flag register */
interrupt_status = usart_hw->INTFLAG.reg;
1320: 7e23 ldrb r3, [r4, #24]
interrupt_status &= usart_hw->INTENSET.reg;
1322: 7da6 ldrb r6, [r4, #22]
1324: 401e ands r6, r3
callback_status = module->callback_reg_mask &
1326: 2330 movs r3, #48 ; 0x30
1328: 5ceb ldrb r3, [r5, r3]
132a: 2231 movs r2, #49 ; 0x31
132c: 5caf ldrb r7, [r5, r2]
132e: 401f ands r7, r3
module->callback_enable_mask;
/* Check if a DATA READY interrupt has occurred,
* and if there is more to transfer */
if (interrupt_status & SERCOM_USART_INTFLAG_DRE) {
1330: 07f3 lsls r3, r6, #31
1332: d522 bpl.n 137a <_usart_interrupt_handler+0x6a>
if (module->remaining_tx_buffer_length) {
1334: 8deb ldrh r3, [r5, #46] ; 0x2e
1336: b29b uxth r3, r3
1338: 2b00 cmp r3, #0
133a: d01c beq.n 1376 <_usart_interrupt_handler+0x66>
/* Write value will be at least 8-bits long */
uint16_t data_to_send = *(module->tx_buffer_ptr);
133c: 6aaa ldr r2, [r5, #40] ; 0x28
133e: 7813 ldrb r3, [r2, #0]
1340: b2db uxtb r3, r3
/* Increment 8-bit pointer */
(module->tx_buffer_ptr)++;
1342: 1c51 adds r1, r2, #1
1344: 62a9 str r1, [r5, #40] ; 0x28
if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
1346: 7969 ldrb r1, [r5, #5]
1348: 2901 cmp r1, #1
134a: d00e beq.n 136a <_usart_interrupt_handler+0x5a>
uint16_t data_to_send = *(module->tx_buffer_ptr);
134c: b29b uxth r3, r3
data_to_send |= (*(module->tx_buffer_ptr) << 8);
/* Increment 8-bit pointer */
(module->tx_buffer_ptr)++;
}
/* Write the data to send */
usart_hw->DATA.reg = (data_to_send & SERCOM_USART_DATA_MASK);
134e: 05db lsls r3, r3, #23
1350: 0ddb lsrs r3, r3, #23
1352: 8523 strh r3, [r4, #40] ; 0x28
if (--(module->remaining_tx_buffer_length) == 0) {
1354: 8deb ldrh r3, [r5, #46] ; 0x2e
1356: 3b01 subs r3, #1
1358: b29b uxth r3, r3
135a: 85eb strh r3, [r5, #46] ; 0x2e
135c: 2b00 cmp r3, #0
135e: d10c bne.n 137a <_usart_interrupt_handler+0x6a>
/* Disable the Data Register Empty Interrupt */
usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE;
1360: 3301 adds r3, #1
1362: 7523 strb r3, [r4, #20]
/* Enable Transmission Complete interrupt */
usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_TXC;
1364: 3301 adds r3, #1
1366: 75a3 strb r3, [r4, #22]
1368: e007 b.n 137a <_usart_interrupt_handler+0x6a>
data_to_send |= (*(module->tx_buffer_ptr) << 8);
136a: 7851 ldrb r1, [r2, #1]
136c: 0209 lsls r1, r1, #8
136e: 430b orrs r3, r1
(module->tx_buffer_ptr)++;
1370: 3202 adds r2, #2
1372: 62aa str r2, [r5, #40] ; 0x28
1374: e7eb b.n 134e <_usart_interrupt_handler+0x3e>
}
} else {
usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE;
1376: 2301 movs r3, #1
1378: 7523 strb r3, [r4, #20]
}
}
/* Check if the Transmission Complete interrupt has occurred and
* that the transmit buffer is empty */
if (interrupt_status & SERCOM_USART_INTFLAG_TXC) {
137a: 07b3 lsls r3, r6, #30
137c: d506 bpl.n 138c <_usart_interrupt_handler+0x7c>
/* Disable TX Complete Interrupt, and set STATUS_OK */
usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_TXC;
137e: 2302 movs r3, #2
1380: 7523 strb r3, [r4, #20]
module->tx_status = STATUS_OK;
1382: 2200 movs r2, #0
1384: 3331 adds r3, #49 ; 0x31
1386: 54ea strb r2, [r5, r3]
/* Run callback if registered and enabled */
if (callback_status & (1 << USART_CALLBACK_BUFFER_TRANSMITTED)) {
1388: 07fb lsls r3, r7, #31
138a: d41a bmi.n 13c2 <_usart_interrupt_handler+0xb2>
}
}
/* Check if the Receive Complete interrupt has occurred, and that
* there's more data to receive */
if (interrupt_status & SERCOM_USART_INTFLAG_RXC) {
138c: 0773 lsls r3, r6, #29
138e: d565 bpl.n 145c <_usart_interrupt_handler+0x14c>
if (module->remaining_rx_buffer_length) {
1390: 8dab ldrh r3, [r5, #44] ; 0x2c
1392: b29b uxth r3, r3
1394: 2b00 cmp r3, #0
1396: d05f beq.n 1458 <_usart_interrupt_handler+0x148>
/* Read out the status code and mask away all but the 4 LSBs*/
error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);
1398: 8b63 ldrh r3, [r4, #26]
139a: b2db uxtb r3, r3
#if !SAMD20
/* CTS status should not be considered as an error */
if(error_code & SERCOM_USART_STATUS_CTS) {
139c: 071a lsls r2, r3, #28
139e: d414 bmi.n 13ca <_usart_interrupt_handler+0xba>
error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);
13a0: 223f movs r2, #63 ; 0x3f
13a2: 4013 ands r3, r2
if(error_code & SERCOM_USART_STATUS_TXE) {
error_code &= ~SERCOM_USART_STATUS_TXE;
}
#endif
/* Check if an error has occurred during the receiving */
if (error_code) {
13a4: 2b00 cmp r3, #0
13a6: d034 beq.n 1412 <_usart_interrupt_handler+0x102>
/* Check which error occurred */
if (error_code & SERCOM_USART_STATUS_FERR) {
13a8: 079a lsls r2, r3, #30
13aa: d511 bpl.n 13d0 <_usart_interrupt_handler+0xc0>
/* Store the error code and clear flag by writing 1 to it */
module->rx_status = STATUS_ERR_BAD_FORMAT;
13ac: 221a movs r2, #26
13ae: 2332 movs r3, #50 ; 0x32
13b0: 54ea strb r2, [r5, r3]
usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR;
13b2: 3b30 subs r3, #48 ; 0x30
13b4: 8363 strh r3, [r4, #26]
usart_hw->STATUS.reg = SERCOM_USART_STATUS_COLL;
}
#endif
/* Run callback if registered and enabled */
if (callback_status
13b6: 077b lsls r3, r7, #29
13b8: d550 bpl.n 145c <_usart_interrupt_handler+0x14c>
& (1 << USART_CALLBACK_ERROR)) {
(*(module->callback[USART_CALLBACK_ERROR]))(module);
13ba: 0028 movs r0, r5
13bc: 696b ldr r3, [r5, #20]
13be: 4798 blx r3
13c0: e04c b.n 145c <_usart_interrupt_handler+0x14c>
(*(module->callback[USART_CALLBACK_BUFFER_TRANSMITTED]))(module);
13c2: 0028 movs r0, r5
13c4: 68eb ldr r3, [r5, #12]
13c6: 4798 blx r3
13c8: e7e0 b.n 138c <_usart_interrupt_handler+0x7c>
error_code &= ~SERCOM_USART_STATUS_CTS;
13ca: 2237 movs r2, #55 ; 0x37
13cc: 4013 ands r3, r2
13ce: e7e9 b.n 13a4 <_usart_interrupt_handler+0x94>
} else if (error_code & SERCOM_USART_STATUS_BUFOVF) {
13d0: 075a lsls r2, r3, #29
13d2: d505 bpl.n 13e0 <_usart_interrupt_handler+0xd0>
module->rx_status = STATUS_ERR_OVERFLOW;
13d4: 221e movs r2, #30
13d6: 2332 movs r3, #50 ; 0x32
13d8: 54ea strb r2, [r5, r3]
usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
13da: 3b2e subs r3, #46 ; 0x2e
13dc: 8363 strh r3, [r4, #26]
13de: e7ea b.n 13b6 <_usart_interrupt_handler+0xa6>
} else if (error_code & SERCOM_USART_STATUS_PERR) {
13e0: 07da lsls r2, r3, #31
13e2: d505 bpl.n 13f0 <_usart_interrupt_handler+0xe0>
module->rx_status = STATUS_ERR_BAD_DATA;
13e4: 2213 movs r2, #19
13e6: 2332 movs r3, #50 ; 0x32
13e8: 54ea strb r2, [r5, r3]
usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR;
13ea: 3b31 subs r3, #49 ; 0x31
13ec: 8363 strh r3, [r4, #26]
13ee: e7e2 b.n 13b6 <_usart_interrupt_handler+0xa6>
else if (error_code & SERCOM_USART_STATUS_ISF) {
13f0: 06da lsls r2, r3, #27
13f2: d505 bpl.n 1400 <_usart_interrupt_handler+0xf0>
module->rx_status = STATUS_ERR_PROTOCOL;
13f4: 2242 movs r2, #66 ; 0x42
13f6: 2332 movs r3, #50 ; 0x32
13f8: 54ea strb r2, [r5, r3]
usart_hw->STATUS.reg = SERCOM_USART_STATUS_ISF;
13fa: 3b22 subs r3, #34 ; 0x22
13fc: 8363 strh r3, [r4, #26]
13fe: e7da b.n 13b6 <_usart_interrupt_handler+0xa6>
else if (error_code & SERCOM_USART_STATUS_COLL) {
1400: 2220 movs r2, #32
1402: 421a tst r2, r3
1404: d0d7 beq.n 13b6 <_usart_interrupt_handler+0xa6>
module->rx_status = STATUS_ERR_PACKET_COLLISION;
1406: 3221 adds r2, #33 ; 0x21
1408: 2332 movs r3, #50 ; 0x32
140a: 54ea strb r2, [r5, r3]
usart_hw->STATUS.reg = SERCOM_USART_STATUS_COLL;
140c: 3b12 subs r3, #18
140e: 8363 strh r3, [r4, #26]
1410: e7d1 b.n 13b6 <_usart_interrupt_handler+0xa6>
} else {
/* Read current packet from DATA register,
* increment buffer pointer and decrement buffer length */
uint16_t received_data = (usart_hw->DATA.reg & SERCOM_USART_DATA_MASK);
1412: 8d23 ldrh r3, [r4, #40] ; 0x28
1414: 05db lsls r3, r3, #23
1416: 0ddb lsrs r3, r3, #23
/* Read value will be at least 8-bits long */
*(module->rx_buffer_ptr) = received_data;
1418: b2da uxtb r2, r3
141a: 6a69 ldr r1, [r5, #36] ; 0x24
141c: 700a strb r2, [r1, #0]
/* Increment 8-bit pointer */
module->rx_buffer_ptr += 1;
141e: 6a6a ldr r2, [r5, #36] ; 0x24
1420: 1c51 adds r1, r2, #1
1422: 6269 str r1, [r5, #36] ; 0x24
if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
1424: 7969 ldrb r1, [r5, #5]
1426: 2901 cmp r1, #1
1428: d010 beq.n 144c <_usart_interrupt_handler+0x13c>
/* Increment 8-bit pointer */
module->rx_buffer_ptr += 1;
}
/* Check if the last character have been received */
if(--(module->remaining_rx_buffer_length) == 0) {
142a: 8dab ldrh r3, [r5, #44] ; 0x2c
142c: 3b01 subs r3, #1
142e: b29b uxth r3, r3
1430: 85ab strh r3, [r5, #44] ; 0x2c
1432: 2b00 cmp r3, #0
1434: d112 bne.n 145c <_usart_interrupt_handler+0x14c>
/* Disable RX Complete Interrupt,
* and set STATUS_OK */
usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC;
1436: 3304 adds r3, #4
1438: 7523 strb r3, [r4, #20]
module->rx_status = STATUS_OK;
143a: 2200 movs r2, #0
143c: 332e adds r3, #46 ; 0x2e
143e: 54ea strb r2, [r5, r3]
/* Run callback if registered and enabled */
if (callback_status
1440: 07bb lsls r3, r7, #30
1442: d50b bpl.n 145c <_usart_interrupt_handler+0x14c>
& (1 << USART_CALLBACK_BUFFER_RECEIVED)) {
(*(module->callback[USART_CALLBACK_BUFFER_RECEIVED]))(module);
1444: 0028 movs r0, r5
1446: 692b ldr r3, [r5, #16]
1448: 4798 blx r3
144a: e007 b.n 145c <_usart_interrupt_handler+0x14c>
*(module->rx_buffer_ptr) = (received_data >> 8);
144c: 0a1b lsrs r3, r3, #8
144e: 7053 strb r3, [r2, #1]
module->rx_buffer_ptr += 1;
1450: 6a6b ldr r3, [r5, #36] ; 0x24
1452: 3301 adds r3, #1
1454: 626b str r3, [r5, #36] ; 0x24
1456: e7e8 b.n 142a <_usart_interrupt_handler+0x11a>
}
}
}
} else {
/* This should not happen. Disable Receive Complete interrupt. */
usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC;
1458: 2304 movs r3, #4
145a: 7523 strb r3, [r4, #20]
}
}
#ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL
if (interrupt_status & SERCOM_USART_INTFLAG_CTSIC) {
145c: 06f3 lsls r3, r6, #27
145e: d504 bpl.n 146a <_usart_interrupt_handler+0x15a>
/* Disable interrupts */
usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_CTSIC;
1460: 2310 movs r3, #16
1462: 7523 strb r3, [r4, #20]
/* Clear interrupt flag */
usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC;
1464: 7623 strb r3, [r4, #24]
/* Run callback if registered and enabled */
if (callback_status & (1 << USART_CALLBACK_CTS_INPUT_CHANGE)) {
1466: 06fb lsls r3, r7, #27
1468: d40e bmi.n 1488 <_usart_interrupt_handler+0x178>
}
}
#endif
#ifdef FEATURE_USART_LIN_SLAVE
if (interrupt_status & SERCOM_USART_INTFLAG_RXBRK) {
146a: 06b3 lsls r3, r6, #26
146c: d504 bpl.n 1478 <_usart_interrupt_handler+0x168>
/* Disable interrupts */
usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXBRK;
146e: 2320 movs r3, #32
1470: 7523 strb r3, [r4, #20]
/* Clear interrupt flag */
usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK;
1472: 7623 strb r3, [r4, #24]
/* Run callback if registered and enabled */
if (callback_status & (1 << USART_CALLBACK_BREAK_RECEIVED)) {
1474: 073b lsls r3, r7, #28
1476: d40b bmi.n 1490 <_usart_interrupt_handler+0x180>
}
}
#endif
#ifdef FEATURE_USART_START_FRAME_DECTION
if (interrupt_status & SERCOM_USART_INTFLAG_RXS) {
1478: 0733 lsls r3, r6, #28
147a: d504 bpl.n 1486 <_usart_interrupt_handler+0x176>
/* Disable interrupts */
usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXS;
147c: 2308 movs r3, #8
147e: 7523 strb r3, [r4, #20]
/* Clear interrupt flag */
usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXS;
1480: 7623 strb r3, [r4, #24]
/* Run callback if registered and enabled */
if (callback_status & (1 << USART_CALLBACK_START_RECEIVED)) {
1482: 06bb lsls r3, r7, #26
1484: d408 bmi.n 1498 <_usart_interrupt_handler+0x188>
(*(module->callback[USART_CALLBACK_START_RECEIVED]))(module);
}
}
#endif
}
1486: bdf8 pop {r3, r4, r5, r6, r7, pc}
(*(module->callback[USART_CALLBACK_CTS_INPUT_CHANGE]))(module);
1488: 0028 movs r0, r5
148a: 69eb ldr r3, [r5, #28]
148c: 4798 blx r3
148e: e7ec b.n 146a <_usart_interrupt_handler+0x15a>
(*(module->callback[USART_CALLBACK_BREAK_RECEIVED]))(module);
1490: 0028 movs r0, r5
1492: 69ab ldr r3, [r5, #24]
1494: 4798 blx r3
1496: e7ef b.n 1478 <_usart_interrupt_handler+0x168>
(*(module->callback[USART_CALLBACK_START_RECEIVED]))(module);
1498: 6a2b ldr r3, [r5, #32]
149a: 0028 movs r0, r5
149c: 4798 blx r3
}
149e: e7f2 b.n 1486 <_usart_interrupt_handler+0x176>
14a0: 20000284 .word 0x20000284
000014a4 <_sercom_default_handler>:
*/
static void _sercom_default_handler(
const uint8_t instance)
{
Assert(false);
}
14a4: 4770 bx lr
...
000014a8 <_sercom_set_handler>:
* \param[in] interrupt_handler Pointer to instance callback handler.
*/
void _sercom_set_handler(
const uint8_t instance,
const sercom_handler_t interrupt_handler)
{
14a8: b5f0 push {r4, r5, r6, r7, lr}
/* Initialize handlers with default handler and device instances with 0 */
if (_handler_table_initialized == false) {
14aa: 4b0a ldr r3, [pc, #40] ; (14d4 <_sercom_set_handler+0x2c>)
14ac: 781b ldrb r3, [r3, #0]
14ae: 2b00 cmp r3, #0
14b0: d10c bne.n 14cc <_sercom_set_handler+0x24>
for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
_sercom_interrupt_handlers[i] = &_sercom_default_handler;
14b2: 4f09 ldr r7, [pc, #36] ; (14d8 <_sercom_set_handler+0x30>)
14b4: 4e09 ldr r6, [pc, #36] ; (14dc <_sercom_set_handler+0x34>)
_sercom_instances[i] = NULL;
14b6: 4d0a ldr r5, [pc, #40] ; (14e0 <_sercom_set_handler+0x38>)
14b8: 2400 movs r4, #0
_sercom_interrupt_handlers[i] = &_sercom_default_handler;
14ba: 51de str r6, [r3, r7]
_sercom_instances[i] = NULL;
14bc: 195a adds r2, r3, r5
14be: 6014 str r4, [r2, #0]
14c0: 3304 adds r3, #4
for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
14c2: 2b18 cmp r3, #24
14c4: d1f9 bne.n 14ba <_sercom_set_handler+0x12>
}
_handler_table_initialized = true;
14c6: 2201 movs r2, #1
14c8: 4b02 ldr r3, [pc, #8] ; (14d4 <_sercom_set_handler+0x2c>)
14ca: 701a strb r2, [r3, #0]
}
/* Save interrupt handler */
_sercom_interrupt_handlers[instance] = interrupt_handler;
14cc: 0080 lsls r0, r0, #2
14ce: 4b02 ldr r3, [pc, #8] ; (14d8 <_sercom_set_handler+0x30>)
14d0: 50c1 str r1, [r0, r3]
}
14d2: bdf0 pop {r4, r5, r6, r7, pc}
14d4: 20000190 .word 0x20000190
14d8: 20000194 .word 0x20000194
14dc: 000014a5 .word 0x000014a5
14e0: 20000284 .word 0x20000284
000014e4 <_sercom_get_interrupt_vector>:
* \retval SYSTEM_INTERRUPT_MODULE_SERCOM6
* \retval SYSTEM_INTERRUPT_MODULE_SERCOM7
*/
enum system_interrupt_vector _sercom_get_interrupt_vector(
Sercom *const sercom_instance)
{
14e4: b500 push {lr}
14e6: b083 sub sp, #12
const uint8_t sercom_int_vectors[SERCOM_INST_NUM] =
14e8: 2309 movs r3, #9
14ea: 466a mov r2, sp
14ec: 7013 strb r3, [r2, #0]
14ee: 3301 adds r3, #1
14f0: 7053 strb r3, [r2, #1]
14f2: 3301 adds r3, #1
14f4: 7093 strb r3, [r2, #2]
14f6: 3301 adds r3, #1
14f8: 70d3 strb r3, [r2, #3]
14fa: 3301 adds r3, #1
14fc: 7113 strb r3, [r2, #4]
14fe: 3301 adds r3, #1
1500: 7153 strb r3, [r2, #5]
{
MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_VECT_NUM, ~)
};
/* Retrieve the index of the SERCOM being requested */
uint8_t instance_index = _sercom_get_sercom_inst_index(sercom_instance);
1502: 4b03 ldr r3, [pc, #12] ; (1510 <_sercom_get_interrupt_vector+0x2c>)
1504: 4798 blx r3
/* Get the vector number from the lookup table for the requested SERCOM */
return (enum system_interrupt_vector)sercom_int_vectors[instance_index];
1506: 466b mov r3, sp
1508: 5618 ldrsb r0, [r3, r0]
}
150a: b003 add sp, #12
150c: bd00 pop {pc}
150e: 46c0 nop ; (mov r8, r8)
1510: 00000bed .word 0x00000bed
00001514 <SERCOM0_Handler>:
/** Auto-generate a set of interrupt handlers for each SERCOM in the device */
MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_HANDLER, ~)
1514: b510 push {r4, lr}
1516: 4b02 ldr r3, [pc, #8] ; (1520 <SERCOM0_Handler+0xc>)
1518: 681b ldr r3, [r3, #0]
151a: 2000 movs r0, #0
151c: 4798 blx r3
151e: bd10 pop {r4, pc}
1520: 20000194 .word 0x20000194
00001524 <SERCOM1_Handler>:
1524: b510 push {r4, lr}
1526: 4b02 ldr r3, [pc, #8] ; (1530 <SERCOM1_Handler+0xc>)
1528: 685b ldr r3, [r3, #4]
152a: 2001 movs r0, #1
152c: 4798 blx r3
152e: bd10 pop {r4, pc}
1530: 20000194 .word 0x20000194
00001534 <SERCOM2_Handler>:
1534: b510 push {r4, lr}
1536: 4b02 ldr r3, [pc, #8] ; (1540 <SERCOM2_Handler+0xc>)
1538: 689b ldr r3, [r3, #8]
153a: 2002 movs r0, #2
153c: 4798 blx r3
153e: bd10 pop {r4, pc}
1540: 20000194 .word 0x20000194
00001544 <SERCOM3_Handler>:
1544: b510 push {r4, lr}
1546: 4b02 ldr r3, [pc, #8] ; (1550 <SERCOM3_Handler+0xc>)
1548: 68db ldr r3, [r3, #12]
154a: 2003 movs r0, #3
154c: 4798 blx r3
154e: bd10 pop {r4, pc}
1550: 20000194 .word 0x20000194
00001554 <SERCOM4_Handler>:
1554: b510 push {r4, lr}
1556: 4b02 ldr r3, [pc, #8] ; (1560 <SERCOM4_Handler+0xc>)
1558: 691b ldr r3, [r3, #16]
155a: 2004 movs r0, #4
155c: 4798 blx r3
155e: bd10 pop {r4, pc}
1560: 20000194 .word 0x20000194
00001564 <SERCOM5_Handler>:
1564: b510 push {r4, lr}
1566: 4b02 ldr r3, [pc, #8] ; (1570 <SERCOM5_Handler+0xc>)
1568: 695b ldr r3, [r3, #20]
156a: 2005 movs r0, #5
156c: 4798 blx r3
156e: bd10 pop {r4, pc}
1570: 20000194 .word 0x20000194
00001574 <delay_init>:
*
* This must be called during start up to initialize the delay routine with
* the current used main clock. It must run any time the main CPU clock is changed.
*/
void delay_init(void)
{
1574: b570 push {r4, r5, r6, lr}
cycles_per_ms = system_gclk_gen_get_hz(0);
1576: 2000 movs r0, #0
1578: 4b08 ldr r3, [pc, #32] ; (159c <delay_init+0x28>)
157a: 4798 blx r3
157c: 0005 movs r5, r0
cycles_per_ms /= 1000;
157e: 4c08 ldr r4, [pc, #32] ; (15a0 <delay_init+0x2c>)
1580: 21fa movs r1, #250 ; 0xfa
1582: 0089 lsls r1, r1, #2
1584: 47a0 blx r4
1586: 4b07 ldr r3, [pc, #28] ; (15a4 <delay_init+0x30>)
1588: 6018 str r0, [r3, #0]
cycles_per_us = cycles_per_ms / 1000;
158a: 4907 ldr r1, [pc, #28] ; (15a8 <delay_init+0x34>)
158c: 0028 movs r0, r5
158e: 47a0 blx r4
1590: 4b06 ldr r3, [pc, #24] ; (15ac <delay_init+0x38>)
1592: 6018 str r0, [r3, #0]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
1594: 2205 movs r2, #5
1596: 4b06 ldr r3, [pc, #24] ; (15b0 <delay_init+0x3c>)
1598: 601a str r2, [r3, #0]
}
159a: bd70 pop {r4, r5, r6, pc}
159c: 000019dd .word 0x000019dd
15a0: 00001df5 .word 0x00001df5
15a4: 2000000c .word 0x2000000c
15a8: 000f4240 .word 0x000f4240
15ac: 20000010 .word 0x20000010
15b0: e000e010 .word 0xe000e010
000015b4 <delay_cycles_ms>:
*
* \param n Number of milliseconds to wait
*/
void delay_cycles_ms(
uint32_t n)
{
15b4: b530 push {r4, r5, lr}
while (n--) {
/* Devide up to blocks of 1ms */
delay_cycles(cycles_per_ms);
15b6: 4b08 ldr r3, [pc, #32] ; (15d8 <delay_cycles_ms+0x24>)
15b8: 681c ldr r4, [r3, #0]
*/
static inline void delay_cycles(
const uint32_t n)
{
if (n > 0) {
SysTick->LOAD = n;
15ba: 4a08 ldr r2, [pc, #32] ; (15dc <delay_cycles_ms+0x28>)
SysTick->VAL = 0;
15bc: 2500 movs r5, #0
while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) {
15be: 2180 movs r1, #128 ; 0x80
15c0: 0249 lsls r1, r1, #9
while (n--) {
15c2: 3801 subs r0, #1
15c4: d307 bcc.n 15d6 <delay_cycles_ms+0x22>
if (n > 0) {
15c6: 2c00 cmp r4, #0
15c8: d0fb beq.n 15c2 <delay_cycles_ms+0xe>
SysTick->LOAD = n;
15ca: 6054 str r4, [r2, #4]
SysTick->VAL = 0;
15cc: 6095 str r5, [r2, #8]
while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) {
15ce: 6813 ldr r3, [r2, #0]
15d0: 420b tst r3, r1
15d2: d0fc beq.n 15ce <delay_cycles_ms+0x1a>
15d4: e7f5 b.n 15c2 <delay_cycles_ms+0xe>
}
}
15d6: bd30 pop {r4, r5, pc}
15d8: 2000000c .word 0x2000000c
15dc: e000e010 .word 0xe000e010
000015e0 <cpu_irq_enter_critical>:
volatile bool g_interrupt_enabled = true;
#endif
void cpu_irq_enter_critical(void)
{
if (cpu_irq_critical_section_counter == 0) {
15e0: 4b0c ldr r3, [pc, #48] ; (1614 <cpu_irq_enter_critical+0x34>)
15e2: 681b ldr r3, [r3, #0]
15e4: 2b00 cmp r3, #0
15e6: d106 bne.n 15f6 <cpu_irq_enter_critical+0x16>
*/
__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
15e8: f3ef 8310 mrs r3, PRIMASK
if (cpu_irq_is_enabled()) {
15ec: 2b00 cmp r3, #0
15ee: d007 beq.n 1600 <cpu_irq_enter_critical+0x20>
cpu_irq_disable();
cpu_irq_prev_interrupt_state = true;
} else {
/* Make sure the to save the prev state as false */
cpu_irq_prev_interrupt_state = false;
15f0: 2200 movs r2, #0
15f2: 4b09 ldr r3, [pc, #36] ; (1618 <cpu_irq_enter_critical+0x38>)
15f4: 701a strb r2, [r3, #0]
}
}
cpu_irq_critical_section_counter++;
15f6: 4a07 ldr r2, [pc, #28] ; (1614 <cpu_irq_enter_critical+0x34>)
15f8: 6813 ldr r3, [r2, #0]
15fa: 3301 adds r3, #1
15fc: 6013 str r3, [r2, #0]
}
15fe: 4770 bx lr
__ASM volatile ("cpsid i" : : : "memory");
1600: b672 cpsid i
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__STATIC_FORCEINLINE void __DMB(void)
{
__ASM volatile ("dmb 0xF":::"memory");
1602: f3bf 8f5f dmb sy
cpu_irq_disable();
1606: 2200 movs r2, #0
1608: 4b04 ldr r3, [pc, #16] ; (161c <cpu_irq_enter_critical+0x3c>)
160a: 701a strb r2, [r3, #0]
cpu_irq_prev_interrupt_state = true;
160c: 3201 adds r2, #1
160e: 4b02 ldr r3, [pc, #8] ; (1618 <cpu_irq_enter_critical+0x38>)
1610: 701a strb r2, [r3, #0]
1612: e7f0 b.n 15f6 <cpu_irq_enter_critical+0x16>
1614: 200001ac .word 0x200001ac
1618: 200001b0 .word 0x200001b0
161c: 20000014 .word 0x20000014
00001620 <cpu_irq_leave_critical>:
void cpu_irq_leave_critical(void)
{
/* Check if the user is trying to leave a critical section when not in a critical section */
Assert(cpu_irq_critical_section_counter > 0);
cpu_irq_critical_section_counter--;
1620: 4b08 ldr r3, [pc, #32] ; (1644 <cpu_irq_leave_critical+0x24>)
1622: 681a ldr r2, [r3, #0]
1624: 3a01 subs r2, #1
1626: 601a str r2, [r3, #0]
/* Only enable global interrupts when the counter reaches 0 and the state of the global interrupt flag
was enabled when entering critical state */
if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
1628: 681b ldr r3, [r3, #0]
162a: 2b00 cmp r3, #0
162c: d109 bne.n 1642 <cpu_irq_leave_critical+0x22>
162e: 4b06 ldr r3, [pc, #24] ; (1648 <cpu_irq_leave_critical+0x28>)
1630: 781b ldrb r3, [r3, #0]
1632: 2b00 cmp r3, #0
1634: d005 beq.n 1642 <cpu_irq_leave_critical+0x22>
cpu_irq_enable();
1636: 2201 movs r2, #1
1638: 4b04 ldr r3, [pc, #16] ; (164c <cpu_irq_leave_critical+0x2c>)
163a: 701a strb r2, [r3, #0]
163c: f3bf 8f5f dmb sy
__ASM volatile ("cpsie i" : : : "memory");
1640: b662 cpsie i
}
}
1642: 4770 bx lr
1644: 200001ac .word 0x200001ac
1648: 200001b0 .word 0x200001b0
164c: 20000014 .word 0x20000014
00001650 <system_board_init>:
void board_init(void);
# pragma weak board_init=system_board_init
#endif
void system_board_init(void)
{
1650: b5f0 push {r4, r5, r6, r7, lr}
1652: b083 sub sp, #12
/* Sanity check arguments */
Assert(config);
/* Default configuration values */
config->direction = PORT_PIN_DIR_INPUT;
config->input_pull = PORT_PIN_PULL_UP;
1654: ac01 add r4, sp, #4
1656: 2501 movs r5, #1
1658: 7065 strb r5, [r4, #1]
config->powersave = false;
165a: 2700 movs r7, #0
165c: 70a7 strb r7, [r4, #2]
struct port_config pin_conf;
port_get_config_defaults(&pin_conf);
/* Configure LEDs as outputs, turn them off */
pin_conf.direction = PORT_PIN_DIR_OUTPUT;
165e: 7025 strb r5, [r4, #0]
port_pin_set_config(LED_0_PIN, &pin_conf);
1660: 0021 movs r1, r4
1662: 203e movs r0, #62 ; 0x3e
1664: 4e06 ldr r6, [pc, #24] ; (1680 <system_board_init+0x30>)
1666: 47b0 blx r6
PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
uint32_t pin_mask = (1UL << (gpio_pin % 32));
/* Set the pin to high or low atomically based on the requested level */
if (level) {
port_base->OUTSET.reg = pin_mask;
1668: 2280 movs r2, #128 ; 0x80
166a: 05d2 lsls r2, r2, #23
166c: 4b05 ldr r3, [pc, #20] ; (1684 <system_board_init+0x34>)
166e: 619a str r2, [r3, #24]
port_pin_set_output_level(LED_0_PIN, LED_0_INACTIVE);
/* Set buttons as inputs */
pin_conf.direction = PORT_PIN_DIR_INPUT;
1670: 7027 strb r7, [r4, #0]
pin_conf.input_pull = PORT_PIN_PULL_UP;
1672: 7065 strb r5, [r4, #1]
port_pin_set_config(BUTTON_0_PIN, &pin_conf);
1674: 0021 movs r1, r4
1676: 200f movs r0, #15
1678: 47b0 blx r6
port_pin_set_output_level(AT86RFX_RST_PIN, true);
port_pin_set_output_level(AT86RFX_SLP_PIN, true);
pin_conf.direction = PORT_PIN_DIR_INPUT;
port_pin_set_config(AT86RFX_SPI_MISO, &pin_conf);
#endif
}
167a: b003 add sp, #12
167c: bdf0 pop {r4, r5, r6, r7, pc}
167e: 46c0 nop ; (mov r8, r8)
1680: 00001689 .word 0x00001689
1684: 41004480 .word 0x41004480
00001688 <port_pin_set_config>:
* \param[in] config Configuration settings for the pin
*/
void port_pin_set_config(
const uint8_t gpio_pin,
const struct port_config *const config)
{
1688: b500 push {lr}
168a: b083 sub sp, #12
config->mux_position = SYSTEM_PINMUX_GPIO;
168c: ab01 add r3, sp, #4
168e: 2280 movs r2, #128 ; 0x80
1690: 701a strb r2, [r3, #0]
struct system_pinmux_config pinmux_config;
system_pinmux_get_config_defaults(&pinmux_config);
pinmux_config.mux_position = SYSTEM_PINMUX_GPIO;
pinmux_config.direction = (enum system_pinmux_pin_dir)config->direction;
1692: 780a ldrb r2, [r1, #0]
1694: 705a strb r2, [r3, #1]
pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->input_pull;
1696: 784a ldrb r2, [r1, #1]
1698: 709a strb r2, [r3, #2]
pinmux_config.powersave = config->powersave;
169a: 788a ldrb r2, [r1, #2]
169c: 70da strb r2, [r3, #3]
system_pinmux_pin_set_config(gpio_pin, &pinmux_config);
169e: 0019 movs r1, r3
16a0: 4b01 ldr r3, [pc, #4] ; (16a8 <port_pin_set_config+0x20>)
16a2: 4798 blx r3
}
16a4: b003 add sp, #12
16a6: bd00 pop {pc}
16a8: 00001bed .word 0x00001bed
000016ac <system_clock_source_get_hz>:
*
* \returns Frequency of the given clock source, in Hz.
*/
uint32_t system_clock_source_get_hz(
const enum system_clock_source clock_source)
{
16ac: b510 push {r4, lr}
switch (clock_source) {
16ae: 2808 cmp r0, #8
16b0: d803 bhi.n 16ba <system_clock_source_get_hz+0xe>
16b2: 0080 lsls r0, r0, #2
16b4: 4b1c ldr r3, [pc, #112] ; (1728 <system_clock_source_get_hz+0x7c>)
16b6: 581b ldr r3, [r3, r0]
16b8: 469f mov pc, r3
return _system_clock_inst.dpll.frequency;
#endif
default:
return 0;
16ba: 2000 movs r0, #0
16bc: e032 b.n 1724 <system_clock_source_get_hz+0x78>
return _system_clock_inst.xosc.frequency;
16be: 4b1b ldr r3, [pc, #108] ; (172c <system_clock_source_get_hz+0x80>)
16c0: 6918 ldr r0, [r3, #16]
16c2: e02f b.n 1724 <system_clock_source_get_hz+0x78>
return 8000000UL >> SYSCTRL->OSC8M.bit.PRESC;
16c4: 4b1a ldr r3, [pc, #104] ; (1730 <system_clock_source_get_hz+0x84>)
16c6: 6a1b ldr r3, [r3, #32]
16c8: 059b lsls r3, r3, #22
16ca: 0f9b lsrs r3, r3, #30
16cc: 4819 ldr r0, [pc, #100] ; (1734 <system_clock_source_get_hz+0x88>)
16ce: 40d8 lsrs r0, r3
16d0: e028 b.n 1724 <system_clock_source_get_hz+0x78>
return _system_clock_inst.xosc32k.frequency;
16d2: 4b16 ldr r3, [pc, #88] ; (172c <system_clock_source_get_hz+0x80>)
16d4: 6958 ldr r0, [r3, #20]
16d6: e025 b.n 1724 <system_clock_source_get_hz+0x78>
if (!(_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_ENABLE))
16d8: 4b14 ldr r3, [pc, #80] ; (172c <system_clock_source_get_hz+0x80>)
16da: 681b ldr r3, [r3, #0]
return 0;
16dc: 2000 movs r0, #0
if (!(_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_ENABLE))
16de: 079b lsls r3, r3, #30
16e0: d520 bpl.n 1724 <system_clock_source_get_hz+0x78>
while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY)) {
16e2: 4913 ldr r1, [pc, #76] ; (1730 <system_clock_source_get_hz+0x84>)
16e4: 2210 movs r2, #16
16e6: 68cb ldr r3, [r1, #12]
16e8: 421a tst r2, r3
16ea: d0fc beq.n 16e6 <system_clock_source_get_hz+0x3a>
switch(_system_clock_inst.dfll.control &
16ec: 4b0f ldr r3, [pc, #60] ; (172c <system_clock_source_get_hz+0x80>)
16ee: 681a ldr r2, [r3, #0]
16f0: 2324 movs r3, #36 ; 0x24
16f2: 4013 ands r3, r2
16f4: 2b04 cmp r3, #4
16f6: d001 beq.n 16fc <system_clock_source_get_hz+0x50>
return 48000000UL;
16f8: 480f ldr r0, [pc, #60] ; (1738 <system_clock_source_get_hz+0x8c>)
16fa: e013 b.n 1724 <system_clock_source_get_hz+0x78>
return system_gclk_chan_get_hz(SYSCTRL_GCLK_ID_DFLL48) *
16fc: 2000 movs r0, #0
16fe: 4b0f ldr r3, [pc, #60] ; (173c <system_clock_source_get_hz+0x90>)
1700: 4798 blx r3
(_system_clock_inst.dfll.mul & 0xffff);
1702: 4b0a ldr r3, [pc, #40] ; (172c <system_clock_source_get_hz+0x80>)
1704: 689b ldr r3, [r3, #8]
1706: 041b lsls r3, r3, #16
1708: 0c1b lsrs r3, r3, #16
return system_gclk_chan_get_hz(SYSCTRL_GCLK_ID_DFLL48) *
170a: 4358 muls r0, r3
170c: e00a b.n 1724 <system_clock_source_get_hz+0x78>
if (!(SYSCTRL->DPLLSTATUS.reg & SYSCTRL_DPLLSTATUS_ENABLE)) {
170e: 2350 movs r3, #80 ; 0x50
1710: 4a07 ldr r2, [pc, #28] ; (1730 <system_clock_source_get_hz+0x84>)
1712: 5cd3 ldrb r3, [r2, r3]
return 0;
1714: 2000 movs r0, #0
if (!(SYSCTRL->DPLLSTATUS.reg & SYSCTRL_DPLLSTATUS_ENABLE)) {
1716: 075b lsls r3, r3, #29
1718: d504 bpl.n 1724 <system_clock_source_get_hz+0x78>
return _system_clock_inst.dpll.frequency;
171a: 4b04 ldr r3, [pc, #16] ; (172c <system_clock_source_get_hz+0x80>)
171c: 68d8 ldr r0, [r3, #12]
171e: e001 b.n 1724 <system_clock_source_get_hz+0x78>
return 32768UL;
1720: 2080 movs r0, #128 ; 0x80
1722: 0200 lsls r0, r0, #8
}
}
1724: bd10 pop {r4, pc}
1726: 46c0 nop ; (mov r8, r8)
1728: 0000380c .word 0x0000380c
172c: 200001b4 .word 0x200001b4
1730: 40000800 .word 0x40000800
1734: 007a1200 .word 0x007a1200
1738: 02dc6c00 .word 0x02dc6c00
173c: 00001b11 .word 0x00001b11
00001740 <system_clock_source_osc8m_set_config>:
*
* \param[in] config OSC8M configuration structure containing the new config
*/
void system_clock_source_osc8m_set_config(
struct system_clock_source_osc8m_config *const config)
{
1740: b570 push {r4, r5, r6, lr}
SYSCTRL_OSC8M_Type temp = SYSCTRL->OSC8M;
1742: 490c ldr r1, [pc, #48] ; (1774 <system_clock_source_osc8m_set_config+0x34>)
1744: 6a0b ldr r3, [r1, #32]
/* Use temporary struct to reduce register access */
temp.bit.PRESC = config->prescaler;
1746: 7804 ldrb r4, [r0, #0]
temp.bit.ONDEMAND = config->on_demand;
1748: 7885 ldrb r5, [r0, #2]
temp.bit.RUNSTDBY = config->run_in_standby;
SYSCTRL->OSC8M = temp;
174a: 7840 ldrb r0, [r0, #1]
174c: 2201 movs r2, #1
174e: 4010 ands r0, r2
1750: 0180 lsls r0, r0, #6
1752: 2640 movs r6, #64 ; 0x40
1754: 43b3 bics r3, r6
1756: 4303 orrs r3, r0
1758: 402a ands r2, r5
175a: 01d2 lsls r2, r2, #7
175c: 2080 movs r0, #128 ; 0x80
175e: 4383 bics r3, r0
1760: 4313 orrs r3, r2
1762: 2203 movs r2, #3
1764: 4022 ands r2, r4
1766: 0212 lsls r2, r2, #8
1768: 4803 ldr r0, [pc, #12] ; (1778 <system_clock_source_osc8m_set_config+0x38>)
176a: 4003 ands r3, r0
176c: 4313 orrs r3, r2
176e: 620b str r3, [r1, #32]
}
1770: bd70 pop {r4, r5, r6, pc}
1772: 46c0 nop ; (mov r8, r8)
1774: 40000800 .word 0x40000800
1778: fffffcff .word 0xfffffcff
0000177c <system_clock_source_enable>:
* device
*/
enum status_code system_clock_source_enable(
const enum system_clock_source clock_source)
{
switch (clock_source) {
177c: 2808 cmp r0, #8
177e: d803 bhi.n 1788 <system_clock_source_enable+0xc>
1780: 0080 lsls r0, r0, #2
1782: 4b25 ldr r3, [pc, #148] ; (1818 <system_clock_source_enable+0x9c>)
1784: 581b ldr r3, [r3, r0]
1786: 469f mov pc, r3
/* Always enabled */
return STATUS_OK;
default:
Assert(false);
return STATUS_ERR_INVALID_ARG;
1788: 2017 movs r0, #23
178a: e044 b.n 1816 <system_clock_source_enable+0x9a>
SYSCTRL->OSC8M.reg |= SYSCTRL_OSC8M_ENABLE;
178c: 4a23 ldr r2, [pc, #140] ; (181c <system_clock_source_enable+0xa0>)
178e: 6a13 ldr r3, [r2, #32]
1790: 2102 movs r1, #2
1792: 430b orrs r3, r1
1794: 6213 str r3, [r2, #32]
return STATUS_OK;
1796: 2000 movs r0, #0
1798: e03d b.n 1816 <system_clock_source_enable+0x9a>
SYSCTRL->OSC32K.reg |= SYSCTRL_OSC32K_ENABLE;
179a: 4a20 ldr r2, [pc, #128] ; (181c <system_clock_source_enable+0xa0>)
179c: 6993 ldr r3, [r2, #24]
179e: 2102 movs r1, #2
17a0: 430b orrs r3, r1
17a2: 6193 str r3, [r2, #24]
}
return STATUS_OK;
17a4: 2000 movs r0, #0
break;
17a6: e036 b.n 1816 <system_clock_source_enable+0x9a>
SYSCTRL->XOSC.reg |= SYSCTRL_XOSC_ENABLE;
17a8: 4a1c ldr r2, [pc, #112] ; (181c <system_clock_source_enable+0xa0>)
17aa: 8a13 ldrh r3, [r2, #16]
17ac: 2102 movs r1, #2
17ae: 430b orrs r3, r1
17b0: 8213 strh r3, [r2, #16]
return STATUS_OK;
17b2: 2000 movs r0, #0
break;
17b4: e02f b.n 1816 <system_clock_source_enable+0x9a>
SYSCTRL->XOSC32K.reg |= SYSCTRL_XOSC32K_ENABLE;
17b6: 4a19 ldr r2, [pc, #100] ; (181c <system_clock_source_enable+0xa0>)
17b8: 8a93 ldrh r3, [r2, #20]
17ba: 2102 movs r1, #2
17bc: 430b orrs r3, r1
17be: 8293 strh r3, [r2, #20]
return STATUS_OK;
17c0: 2000 movs r0, #0
break;
17c2: e028 b.n 1816 <system_clock_source_enable+0x9a>
_system_clock_inst.dfll.control |= SYSCTRL_DFLLCTRL_ENABLE;
17c4: 4916 ldr r1, [pc, #88] ; (1820 <system_clock_source_enable+0xa4>)
17c6: 680b ldr r3, [r1, #0]
17c8: 2202 movs r2, #2
17ca: 4313 orrs r3, r2
17cc: 600b str r3, [r1, #0]
SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_ENABLE;
17ce: 4b13 ldr r3, [pc, #76] ; (181c <system_clock_source_enable+0xa0>)
17d0: 849a strh r2, [r3, #36] ; 0x24
while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY)) {
17d2: 0019 movs r1, r3
17d4: 320e adds r2, #14
17d6: 68cb ldr r3, [r1, #12]
17d8: 421a tst r2, r3
17da: d0fc beq.n 17d6 <system_clock_source_enable+0x5a>
SYSCTRL->DFLLMUL.reg = _system_clock_inst.dfll.mul;
17dc: 4a10 ldr r2, [pc, #64] ; (1820 <system_clock_source_enable+0xa4>)
17de: 6891 ldr r1, [r2, #8]
17e0: 4b0e ldr r3, [pc, #56] ; (181c <system_clock_source_enable+0xa0>)
17e2: 62d9 str r1, [r3, #44] ; 0x2c
SYSCTRL->DFLLVAL.reg = _system_clock_inst.dfll.val;
17e4: 6852 ldr r2, [r2, #4]
17e6: 629a str r2, [r3, #40] ; 0x28
SYSCTRL->DFLLCTRL.reg = 0;
17e8: 2200 movs r2, #0
17ea: 849a strh r2, [r3, #36] ; 0x24
while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY)) {
17ec: 0019 movs r1, r3
17ee: 3210 adds r2, #16
17f0: 68cb ldr r3, [r1, #12]
17f2: 421a tst r2, r3
17f4: d0fc beq.n 17f0 <system_clock_source_enable+0x74>
SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control;
17f6: 4b0a ldr r3, [pc, #40] ; (1820 <system_clock_source_enable+0xa4>)
17f8: 681b ldr r3, [r3, #0]
17fa: b29b uxth r3, r3
17fc: 4a07 ldr r2, [pc, #28] ; (181c <system_clock_source_enable+0xa0>)
17fe: 8493 strh r3, [r2, #36] ; 0x24
return STATUS_OK;
1800: 2000 movs r0, #0
1802: e008 b.n 1816 <system_clock_source_enable+0x9a>
SYSCTRL->DPLLCTRLA.reg |= SYSCTRL_DPLLCTRLA_ENABLE;
1804: 4905 ldr r1, [pc, #20] ; (181c <system_clock_source_enable+0xa0>)
1806: 2244 movs r2, #68 ; 0x44
1808: 5c8b ldrb r3, [r1, r2]
180a: 2002 movs r0, #2
180c: 4303 orrs r3, r0
180e: 548b strb r3, [r1, r2]
return STATUS_OK;
1810: 2000 movs r0, #0
break;
1812: e000 b.n 1816 <system_clock_source_enable+0x9a>
return STATUS_OK;
1814: 2000 movs r0, #0
}
1816: 4770 bx lr
1818: 00003830 .word 0x00003830
181c: 40000800 .word 0x40000800
1820: 200001b4 .word 0x200001b4
00001824 <system_clock_init>:
* \note OSC8M is always enabled and if user selects other clocks for GCLK generators,
* the OSC8M default enable can be disabled after system_clock_init. Make sure the
* clock switch successfully before disabling OSC8M.
*/
void system_clock_init(void)
{
1824: b530 push {r4, r5, lr}
1826: b085 sub sp, #20
/* Various bits in the INTFLAG register can be set to one at startup.
This will ensure that these bits are cleared */
SYSCTRL->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY | SYSCTRL_INTFLAG_BOD33DET |
1828: 22c2 movs r2, #194 ; 0xc2
182a: 00d2 lsls r2, r2, #3
182c: 4b1a ldr r3, [pc, #104] ; (1898 <system_clock_init+0x74>)
182e: 609a str r2, [r3, #8]
static inline void system_flash_set_waitstates(uint8_t wait_states)
{
Assert(NVMCTRL_CTRLB_RWS((uint32_t)wait_states) ==
((uint32_t)wait_states << NVMCTRL_CTRLB_RWS_Pos));
NVMCTRL->CTRLB.bit.RWS = wait_states;
1830: 4a1a ldr r2, [pc, #104] ; (189c <system_clock_init+0x78>)
1832: 6853 ldr r3, [r2, #4]
1834: 211e movs r1, #30
1836: 438b bics r3, r1
1838: 6053 str r3, [r2, #4]
gclk_conf.source_generator = GCLK_GENERATOR_1;
183a: 2301 movs r3, #1
183c: 466a mov r2, sp
183e: 7013 strb r3, [r2, #0]
for (gclk_id = 0; gclk_id < GCLK_NUM; gclk_id++) {
1840: 2400 movs r4, #0
system_gclk_chan_set_config(gclk_id, &gclk_conf);
1842: 4d17 ldr r5, [pc, #92] ; (18a0 <system_clock_init+0x7c>)
1844: b2e0 uxtb r0, r4
1846: 4669 mov r1, sp
1848: 47a8 blx r5
for (gclk_id = 0; gclk_id < GCLK_NUM; gclk_id++) {
184a: 3401 adds r4, #1
184c: 2c25 cmp r4, #37 ; 0x25
184e: d1f9 bne.n 1844 <system_clock_init+0x20>
config->run_in_standby = false;
1850: a803 add r0, sp, #12
1852: 2400 movs r4, #0
1854: 7044 strb r4, [r0, #1]
config->on_demand = true;
1856: 2501 movs r5, #1
1858: 7085 strb r5, [r0, #2]
/* OSC8M */
struct system_clock_source_osc8m_config osc8m_conf;
system_clock_source_osc8m_get_config_defaults(&osc8m_conf);
osc8m_conf.prescaler = CONF_CLOCK_OSC8M_PRESCALER;
185a: 7004 strb r4, [r0, #0]
osc8m_conf.on_demand = CONF_CLOCK_OSC8M_ON_DEMAND;
osc8m_conf.run_in_standby = CONF_CLOCK_OSC8M_RUN_IN_STANDBY;
system_clock_source_osc8m_set_config(&osc8m_conf);
185c: 4b11 ldr r3, [pc, #68] ; (18a4 <system_clock_init+0x80>)
185e: 4798 blx r3
system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC8M);
1860: 2006 movs r0, #6
1862: 4b11 ldr r3, [pc, #68] ; (18a8 <system_clock_init+0x84>)
1864: 4798 blx r3
/* GCLK */
#if CONF_CLOCK_CONFIGURE_GCLK == true
system_gclk_init();
1866: 4b11 ldr r3, [pc, #68] ; (18ac <system_clock_init+0x88>)
1868: 4798 blx r3
PM->CPUSEL.reg = (uint32_t)divider;
186a: 4b11 ldr r3, [pc, #68] ; (18b0 <system_clock_init+0x8c>)
186c: 721c strb r4, [r3, #8]
PM->APBASEL.reg = (uint32_t)divider;
186e: 725c strb r4, [r3, #9]
PM->APBBSEL.reg = (uint32_t)divider;
1870: 729c strb r4, [r3, #10]
PM->APBCSEL.reg = (uint32_t)divider;
1872: 72dc strb r4, [r3, #11]
{
/* Sanity check arguments */
Assert(config);
/* Default configuration values */
config->division_factor = 1;
1874: 9501 str r5, [sp, #4]
config->high_when_disabled = false;
1876: 466b mov r3, sp
1878: 705c strb r4, [r3, #1]
#if SAML21 || SAML22 || SAMR30 || SAMR34 || SAMR35
config->source_clock = GCLK_SOURCE_OSC16M;
#elif (SAMC20) || (SAMC21)
config->source_clock = GCLK_SOURCE_OSC48M;
#else
config->source_clock = GCLK_SOURCE_OSC8M;
187a: 2306 movs r3, #6
187c: 466a mov r2, sp
187e: 7013 strb r3, [r2, #0]
#endif
config->run_in_standby = false;
1880: 7214 strb r4, [r2, #8]
config->output_enable = false;
1882: 7254 strb r4, [r2, #9]
system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBC, CONF_CLOCK_APBC_DIVIDER);
/* GCLK 0 */
#if CONF_CLOCK_CONFIGURE_GCLK == true
/* Configure the main GCLK last as it might depend on other generators */
_CONF_CLOCK_GCLK_CONFIG(0, ~);
1884: 4669 mov r1, sp
1886: 2000 movs r0, #0
1888: 4b0a ldr r3, [pc, #40] ; (18b4 <system_clock_init+0x90>)
188a: 4798 blx r3
188c: 2000 movs r0, #0
188e: 4b0a ldr r3, [pc, #40] ; (18b8 <system_clock_init+0x94>)
1890: 4798 blx r3
#endif
}
1892: b005 add sp, #20
1894: bd30 pop {r4, r5, pc}
1896: 46c0 nop ; (mov r8, r8)
1898: 40000800 .word 0x40000800
189c: 41004000 .word 0x41004000
18a0: 00001af5 .word 0x00001af5
18a4: 00001741 .word 0x00001741
18a8: 0000177d .word 0x0000177d
18ac: 000018bd .word 0x000018bd
18b0: 40000400 .word 0x40000400
18b4: 000018e1 .word 0x000018e1
18b8: 00001999 .word 0x00001999
000018bc <system_gclk_init>:
PM->APBAMASK.reg |= mask;
18bc: 4a06 ldr r2, [pc, #24] ; (18d8 <system_gclk_init+0x1c>)
18be: 6993 ldr r3, [r2, #24]
18c0: 2108 movs r1, #8
18c2: 430b orrs r3, r1
18c4: 6193 str r3, [r2, #24]
{
/* Turn on the digital interface clock */
system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_GCLK);
/* Software reset the module to ensure it is re-initialized correctly */
GCLK->CTRL.reg = GCLK_CTRL_SWRST;
18c6: 2201 movs r2, #1
18c8: 4b04 ldr r3, [pc, #16] ; (18dc <system_gclk_init+0x20>)
18ca: 701a strb r2, [r3, #0]
while (GCLK->CTRL.reg & GCLK_CTRL_SWRST) {
18cc: 0019 movs r1, r3
18ce: 780b ldrb r3, [r1, #0]
18d0: 4213 tst r3, r2
18d2: d1fc bne.n 18ce <system_gclk_init+0x12>
/* Wait for reset to complete */
}
}
18d4: 4770 bx lr
18d6: 46c0 nop ; (mov r8, r8)
18d8: 40000400 .word 0x40000400
18dc: 40000c00 .word 0x40000c00
000018e0 <system_gclk_gen_set_config>:
* \param[in] config Configuration settings for the generator
*/
void system_gclk_gen_set_config(
const uint8_t generator,
struct system_gclk_gen_config *const config)
{
18e0: b570 push {r4, r5, r6, lr}
18e2: 0006 movs r6, r0
/* Sanity check arguments */
Assert(config);
/* Cache new register configurations to minimize sync requirements. */
uint32_t new_genctrl_config = (generator << GCLK_GENCTRL_ID_Pos);
18e4: 0004 movs r4, r0
uint32_t new_gendiv_config = (generator << GCLK_GENDIV_ID_Pos);
/* Select the requested source clock for the generator */
new_genctrl_config |= config->source_clock << GCLK_GENCTRL_SRC_Pos;
18e6: 780d ldrb r5, [r1, #0]
18e8: 022d lsls r5, r5, #8
18ea: 4305 orrs r5, r0
/* Configure the clock to be either high or low when disabled */
if (config->high_when_disabled) {
18ec: 784b ldrb r3, [r1, #1]
18ee: 2b00 cmp r3, #0
18f0: d002 beq.n 18f8 <system_gclk_gen_set_config+0x18>
new_genctrl_config |= GCLK_GENCTRL_OOV;
18f2: 2380 movs r3, #128 ; 0x80
18f4: 02db lsls r3, r3, #11
18f6: 431d orrs r5, r3
}
/* Configure if the clock output to I/O pin should be enabled. */
if (config->output_enable) {
18f8: 7a4b ldrb r3, [r1, #9]
18fa: 2b00 cmp r3, #0
18fc: d002 beq.n 1904 <system_gclk_gen_set_config+0x24>
new_genctrl_config |= GCLK_GENCTRL_OE;
18fe: 2380 movs r3, #128 ; 0x80
1900: 031b lsls r3, r3, #12
1902: 431d orrs r5, r3
}
/* Set division factor */
if (config->division_factor > 1) {
1904: 6848 ldr r0, [r1, #4]
1906: 2801 cmp r0, #1
1908: d910 bls.n 192c <system_gclk_gen_set_config+0x4c>
/* Check if division is a power of two */
if (((config->division_factor & (config->division_factor - 1)) == 0)) {
190a: 1e43 subs r3, r0, #1
190c: 4218 tst r0, r3
190e: d134 bne.n 197a <system_gclk_gen_set_config+0x9a>
* register */
uint32_t div2_count = 0;
uint32_t mask;
for (mask = (1UL << 1); mask < config->division_factor;
1910: 2802 cmp r0, #2
1912: d930 bls.n 1976 <system_gclk_gen_set_config+0x96>
1914: 2302 movs r3, #2
1916: 2200 movs r2, #0
mask <<= 1) {
div2_count++;
1918: 3201 adds r2, #1
mask <<= 1) {
191a: 005b lsls r3, r3, #1
for (mask = (1UL << 1); mask < config->division_factor;
191c: 4298 cmp r0, r3
191e: d8fb bhi.n 1918 <system_gclk_gen_set_config+0x38>
}
/* Set binary divider power of 2 division factor */
new_gendiv_config |= div2_count << GCLK_GENDIV_DIV_Pos;
1920: 0212 lsls r2, r2, #8
1922: 4332 orrs r2, r6
1924: 0014 movs r4, r2
new_genctrl_config |= GCLK_GENCTRL_DIVSEL;
1926: 2380 movs r3, #128 ; 0x80
1928: 035b lsls r3, r3, #13
192a: 431d orrs r5, r3
}
}
/* Enable or disable the clock in standby mode */
if (config->run_in_standby) {
192c: 7a0b ldrb r3, [r1, #8]
192e: 2b00 cmp r3, #0
1930: d002 beq.n 1938 <system_gclk_gen_set_config+0x58>
new_genctrl_config |= GCLK_GENCTRL_RUNSTDBY;
1932: 2380 movs r3, #128 ; 0x80
1934: 039b lsls r3, r3, #14
1936: 431d orrs r5, r3
if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
1938: 4a13 ldr r2, [pc, #76] ; (1988 <system_gclk_gen_set_config+0xa8>)
193a: 7853 ldrb r3, [r2, #1]
}
while (system_gclk_is_syncing()) {
193c: b25b sxtb r3, r3
193e: 2b00 cmp r3, #0
1940: dbfb blt.n 193a <system_gclk_gen_set_config+0x5a>
cpu_irq_enter_critical();
1942: 4b12 ldr r3, [pc, #72] ; (198c <system_gclk_gen_set_config+0xac>)
1944: 4798 blx r3
};
system_interrupt_enter_critical_section();
/* Select the correct generator */
*((uint8_t*)&GCLK->GENDIV.reg) = generator;
1946: 4b12 ldr r3, [pc, #72] ; (1990 <system_gclk_gen_set_config+0xb0>)
1948: 701e strb r6, [r3, #0]
if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
194a: 4a0f ldr r2, [pc, #60] ; (1988 <system_gclk_gen_set_config+0xa8>)
194c: 7853 ldrb r3, [r2, #1]
/* Write the new generator configuration */
while (system_gclk_is_syncing()) {
194e: b25b sxtb r3, r3
1950: 2b00 cmp r3, #0
1952: dbfb blt.n 194c <system_gclk_gen_set_config+0x6c>
/* Wait for synchronization */
};
GCLK->GENDIV.reg = new_gendiv_config;
1954: 4b0c ldr r3, [pc, #48] ; (1988 <system_gclk_gen_set_config+0xa8>)
1956: 609c str r4, [r3, #8]
if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
1958: 001a movs r2, r3
195a: 7853 ldrb r3, [r2, #1]
while (system_gclk_is_syncing()) {
195c: b25b sxtb r3, r3
195e: 2b00 cmp r3, #0
1960: dbfb blt.n 195a <system_gclk_gen_set_config+0x7a>
/* Wait for synchronization */
};
GCLK->GENCTRL.reg = new_genctrl_config | (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN);
1962: 4a09 ldr r2, [pc, #36] ; (1988 <system_gclk_gen_set_config+0xa8>)
1964: 6853 ldr r3, [r2, #4]
1966: 2180 movs r1, #128 ; 0x80
1968: 0249 lsls r1, r1, #9
196a: 400b ands r3, r1
196c: 431d orrs r5, r3
196e: 6055 str r5, [r2, #4]
cpu_irq_leave_critical();
1970: 4b08 ldr r3, [pc, #32] ; (1994 <system_gclk_gen_set_config+0xb4>)
1972: 4798 blx r3
system_interrupt_leave_critical_section();
}
1974: bd70 pop {r4, r5, r6, pc}
for (mask = (1UL << 1); mask < config->division_factor;
1976: 2200 movs r2, #0
1978: e7d2 b.n 1920 <system_gclk_gen_set_config+0x40>
(config->division_factor) << GCLK_GENDIV_DIV_Pos;
197a: 0204 lsls r4, r0, #8
new_gendiv_config |=
197c: 4334 orrs r4, r6
new_genctrl_config |= GCLK_GENCTRL_IDC;
197e: 2380 movs r3, #128 ; 0x80
1980: 029b lsls r3, r3, #10
1982: 431d orrs r5, r3
1984: e7d2 b.n 192c <system_gclk_gen_set_config+0x4c>
1986: 46c0 nop ; (mov r8, r8)
1988: 40000c00 .word 0x40000c00
198c: 000015e1 .word 0x000015e1
1990: 40000c08 .word 0x40000c08
1994: 00001621 .word 0x00001621
00001998 <system_gclk_gen_enable>:
*
* \param[in] generator Generic Clock Generator index to enable
*/
void system_gclk_gen_enable(
const uint8_t generator)
{
1998: b510 push {r4, lr}
199a: 0004 movs r4, r0
if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
199c: 4a0b ldr r2, [pc, #44] ; (19cc <system_gclk_gen_enable+0x34>)
199e: 7853 ldrb r3, [r2, #1]
while (system_gclk_is_syncing()) {
19a0: b25b sxtb r3, r3
19a2: 2b00 cmp r3, #0
19a4: dbfb blt.n 199e <system_gclk_gen_enable+0x6>
cpu_irq_enter_critical();
19a6: 4b0a ldr r3, [pc, #40] ; (19d0 <system_gclk_gen_enable+0x38>)
19a8: 4798 blx r3
};
system_interrupt_enter_critical_section();
/* Select the requested generator */
*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
19aa: 4b0a ldr r3, [pc, #40] ; (19d4 <system_gclk_gen_enable+0x3c>)
19ac: 701c strb r4, [r3, #0]
if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
19ae: 4a07 ldr r2, [pc, #28] ; (19cc <system_gclk_gen_enable+0x34>)
19b0: 7853 ldrb r3, [r2, #1]
while (system_gclk_is_syncing()) {
19b2: b25b sxtb r3, r3
19b4: 2b00 cmp r3, #0
19b6: dbfb blt.n 19b0 <system_gclk_gen_enable+0x18>
/* Wait for synchronization */
};
/* Enable generator */
GCLK->GENCTRL.reg |= GCLK_GENCTRL_GENEN;
19b8: 4a04 ldr r2, [pc, #16] ; (19cc <system_gclk_gen_enable+0x34>)
19ba: 6851 ldr r1, [r2, #4]
19bc: 2380 movs r3, #128 ; 0x80
19be: 025b lsls r3, r3, #9
19c0: 430b orrs r3, r1
19c2: 6053 str r3, [r2, #4]
cpu_irq_leave_critical();
19c4: 4b04 ldr r3, [pc, #16] ; (19d8 <system_gclk_gen_enable+0x40>)
19c6: 4798 blx r3
system_interrupt_leave_critical_section();
}
19c8: bd10 pop {r4, pc}
19ca: 46c0 nop ; (mov r8, r8)
19cc: 40000c00 .word 0x40000c00
19d0: 000015e1 .word 0x000015e1
19d4: 40000c04 .word 0x40000c04
19d8: 00001621 .word 0x00001621
000019dc <system_gclk_gen_get_hz>:
*
* \return The frequency of the generic clock generator, in Hz.
*/
uint32_t system_gclk_gen_get_hz(
const uint8_t generator)
{
19dc: b570 push {r4, r5, r6, lr}
19de: 0004 movs r4, r0
if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
19e0: 4a1a ldr r2, [pc, #104] ; (1a4c <system_gclk_gen_get_hz+0x70>)
19e2: 7853 ldrb r3, [r2, #1]
while (system_gclk_is_syncing()) {
19e4: b25b sxtb r3, r3
19e6: 2b00 cmp r3, #0
19e8: dbfb blt.n 19e2 <system_gclk_gen_get_hz+0x6>
cpu_irq_enter_critical();
19ea: 4b19 ldr r3, [pc, #100] ; (1a50 <system_gclk_gen_get_hz+0x74>)
19ec: 4798 blx r3
};
system_interrupt_enter_critical_section();
/* Select the appropriate generator */
*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
19ee: 4b19 ldr r3, [pc, #100] ; (1a54 <system_gclk_gen_get_hz+0x78>)
19f0: 701c strb r4, [r3, #0]
if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
19f2: 4a16 ldr r2, [pc, #88] ; (1a4c <system_gclk_gen_get_hz+0x70>)
19f4: 7853 ldrb r3, [r2, #1]
while (system_gclk_is_syncing()) {
19f6: b25b sxtb r3, r3
19f8: 2b00 cmp r3, #0
19fa: dbfb blt.n 19f4 <system_gclk_gen_get_hz+0x18>
/* Wait for synchronization */
};
/* Get the frequency of the source connected to the GCLK generator */
uint32_t gen_input_hz = system_clock_source_get_hz(
(enum system_clock_source)GCLK->GENCTRL.bit.SRC);
19fc: 4e13 ldr r6, [pc, #76] ; (1a4c <system_gclk_gen_get_hz+0x70>)
19fe: 6870 ldr r0, [r6, #4]
1a00: 04c0 lsls r0, r0, #19
1a02: 0ec0 lsrs r0, r0, #27
uint32_t gen_input_hz = system_clock_source_get_hz(
1a04: 4b14 ldr r3, [pc, #80] ; (1a58 <system_gclk_gen_get_hz+0x7c>)
1a06: 4798 blx r3
1a08: 0005 movs r5, r0
*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
1a0a: 4b12 ldr r3, [pc, #72] ; (1a54 <system_gclk_gen_get_hz+0x78>)
1a0c: 701c strb r4, [r3, #0]
uint8_t divsel = GCLK->GENCTRL.bit.DIVSEL;
1a0e: 6876 ldr r6, [r6, #4]
1a10: 02f6 lsls r6, r6, #11
1a12: 0ff6 lsrs r6, r6, #31
/* Select the appropriate generator division register */
*((uint8_t*)&GCLK->GENDIV.reg) = generator;
1a14: 4b11 ldr r3, [pc, #68] ; (1a5c <system_gclk_gen_get_hz+0x80>)
1a16: 701c strb r4, [r3, #0]
if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
1a18: 4a0c ldr r2, [pc, #48] ; (1a4c <system_gclk_gen_get_hz+0x70>)
1a1a: 7853 ldrb r3, [r2, #1]
while (system_gclk_is_syncing()) {
1a1c: b25b sxtb r3, r3
1a1e: 2b00 cmp r3, #0
1a20: dbfb blt.n 1a1a <system_gclk_gen_get_hz+0x3e>
/* Wait for synchronization */
};
uint32_t divider = GCLK->GENDIV.bit.DIV;
1a22: 4b0a ldr r3, [pc, #40] ; (1a4c <system_gclk_gen_get_hz+0x70>)
1a24: 689c ldr r4, [r3, #8]
1a26: 0224 lsls r4, r4, #8
1a28: 0c24 lsrs r4, r4, #16
cpu_irq_leave_critical();
1a2a: 4b0d ldr r3, [pc, #52] ; (1a60 <system_gclk_gen_get_hz+0x84>)
1a2c: 4798 blx r3
system_interrupt_leave_critical_section();
/* Check if the generator is using fractional or binary division */
if (!divsel && divider > 1) {
1a2e: 2e00 cmp r6, #0
1a30: d107 bne.n 1a42 <system_gclk_gen_get_hz+0x66>
1a32: 2c01 cmp r4, #1
1a34: d907 bls.n 1a46 <system_gclk_gen_get_hz+0x6a>
gen_input_hz /= divider;
1a36: 0021 movs r1, r4
1a38: 0028 movs r0, r5
1a3a: 4b0a ldr r3, [pc, #40] ; (1a64 <system_gclk_gen_get_hz+0x88>)
1a3c: 4798 blx r3
1a3e: 0005 movs r5, r0
1a40: e001 b.n 1a46 <system_gclk_gen_get_hz+0x6a>
} else if (divsel) {
gen_input_hz >>= (divider+1);
1a42: 3401 adds r4, #1
1a44: 40e5 lsrs r5, r4
}
return gen_input_hz;
}
1a46: 0028 movs r0, r5
1a48: bd70 pop {r4, r5, r6, pc}
1a4a: 46c0 nop ; (mov r8, r8)
1a4c: 40000c00 .word 0x40000c00
1a50: 000015e1 .word 0x000015e1
1a54: 40000c04 .word 0x40000c04
1a58: 000016ad .word 0x000016ad
1a5c: 40000c08 .word 0x40000c08
1a60: 00001621 .word 0x00001621
1a64: 00001df5 .word 0x00001df5
00001a68 <system_gclk_chan_enable>:
*
* \param[in] channel Generic Clock channel to enable
*/
void system_gclk_chan_enable(
const uint8_t channel)
{
1a68: b510 push {r4, lr}
1a6a: 0004 movs r4, r0
cpu_irq_enter_critical();
1a6c: 4b06 ldr r3, [pc, #24] ; (1a88 <system_gclk_chan_enable+0x20>)
1a6e: 4798 blx r3
system_interrupt_enter_critical_section();
/* Select the requested generator channel */
*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
1a70: 4b06 ldr r3, [pc, #24] ; (1a8c <system_gclk_chan_enable+0x24>)
1a72: 701c strb r4, [r3, #0]
/* Enable the generic clock */
GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_CLKEN;
1a74: 4a06 ldr r2, [pc, #24] ; (1a90 <system_gclk_chan_enable+0x28>)
1a76: 8853 ldrh r3, [r2, #2]
1a78: 2180 movs r1, #128 ; 0x80
1a7a: 01c9 lsls r1, r1, #7
1a7c: 430b orrs r3, r1
1a7e: 8053 strh r3, [r2, #2]
cpu_irq_leave_critical();
1a80: 4b04 ldr r3, [pc, #16] ; (1a94 <system_gclk_chan_enable+0x2c>)
1a82: 4798 blx r3
system_interrupt_leave_critical_section();
}
1a84: bd10 pop {r4, pc}
1a86: 46c0 nop ; (mov r8, r8)
1a88: 000015e1 .word 0x000015e1
1a8c: 40000c02 .word 0x40000c02
1a90: 40000c00 .word 0x40000c00
1a94: 00001621 .word 0x00001621
00001a98 <system_gclk_chan_disable>:
*
* \param[in] channel Generic Clock channel to disable
*/
void system_gclk_chan_disable(
const uint8_t channel)
{
1a98: b510 push {r4, lr}
1a9a: 0004 movs r4, r0
cpu_irq_enter_critical();
1a9c: 4b0f ldr r3, [pc, #60] ; (1adc <system_gclk_chan_disable+0x44>)
1a9e: 4798 blx r3
system_interrupt_enter_critical_section();
/* Select the requested generator channel */
*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
1aa0: 4b0f ldr r3, [pc, #60] ; (1ae0 <system_gclk_chan_disable+0x48>)
1aa2: 701c strb r4, [r3, #0]
/* Sanity check WRTLOCK */
Assert(!GCLK->CLKCTRL.bit.WRTLOCK);
/* Switch to known-working source so that the channel can be disabled */
uint32_t prev_gen_id = GCLK->CLKCTRL.bit.GEN;
1aa4: 4a0f ldr r2, [pc, #60] ; (1ae4 <system_gclk_chan_disable+0x4c>)
1aa6: 8853 ldrh r3, [r2, #2]
1aa8: 051b lsls r3, r3, #20
1aaa: 0f18 lsrs r0, r3, #28
GCLK->CLKCTRL.bit.GEN = 0;
1aac: 8853 ldrh r3, [r2, #2]
1aae: 490e ldr r1, [pc, #56] ; (1ae8 <system_gclk_chan_disable+0x50>)
1ab0: 400b ands r3, r1
1ab2: 8053 strh r3, [r2, #2]
/* Disable the generic clock */
GCLK->CLKCTRL.reg &= ~GCLK_CLKCTRL_CLKEN;
1ab4: 8853 ldrh r3, [r2, #2]
1ab6: 490d ldr r1, [pc, #52] ; (1aec <system_gclk_chan_disable+0x54>)
1ab8: 400b ands r3, r1
1aba: 8053 strh r3, [r2, #2]
while (GCLK->CLKCTRL.reg & GCLK_CLKCTRL_CLKEN) {
1abc: 0011 movs r1, r2
1abe: 2280 movs r2, #128 ; 0x80
1ac0: 01d2 lsls r2, r2, #7
1ac2: 884b ldrh r3, [r1, #2]
1ac4: 4213 tst r3, r2
1ac6: d1fc bne.n 1ac2 <system_gclk_chan_disable+0x2a>
/* Wait for clock to become disabled */
}
/* Restore previous configured clock generator */
GCLK->CLKCTRL.bit.GEN = prev_gen_id;
1ac8: 4906 ldr r1, [pc, #24] ; (1ae4 <system_gclk_chan_disable+0x4c>)
1aca: 884a ldrh r2, [r1, #2]
1acc: 0203 lsls r3, r0, #8
1ace: 4806 ldr r0, [pc, #24] ; (1ae8 <system_gclk_chan_disable+0x50>)
1ad0: 4002 ands r2, r0
1ad2: 4313 orrs r3, r2
1ad4: 804b strh r3, [r1, #2]
cpu_irq_leave_critical();
1ad6: 4b06 ldr r3, [pc, #24] ; (1af0 <system_gclk_chan_disable+0x58>)
1ad8: 4798 blx r3
system_interrupt_leave_critical_section();
}
1ada: bd10 pop {r4, pc}
1adc: 000015e1 .word 0x000015e1
1ae0: 40000c02 .word 0x40000c02
1ae4: 40000c00 .word 0x40000c00
1ae8: fffff0ff .word 0xfffff0ff
1aec: ffffbfff .word 0xffffbfff
1af0: 00001621 .word 0x00001621
00001af4 <system_gclk_chan_set_config>:
{
1af4: b510 push {r4, lr}
new_clkctrl_config |= config->source_generator << GCLK_CLKCTRL_GEN_Pos;
1af6: 780c ldrb r4, [r1, #0]
1af8: 0224 lsls r4, r4, #8
1afa: 4304 orrs r4, r0
system_gclk_chan_disable(channel);
1afc: 4b02 ldr r3, [pc, #8] ; (1b08 <system_gclk_chan_set_config+0x14>)
1afe: 4798 blx r3
GCLK->CLKCTRL.reg = new_clkctrl_config;
1b00: b2a4 uxth r4, r4
1b02: 4b02 ldr r3, [pc, #8] ; (1b0c <system_gclk_chan_set_config+0x18>)
1b04: 805c strh r4, [r3, #2]
}
1b06: bd10 pop {r4, pc}
1b08: 00001a99 .word 0x00001a99
1b0c: 40000c00 .word 0x40000c00
00001b10 <system_gclk_chan_get_hz>:
*
* \return The frequency of the generic clock channel, in Hz.
*/
uint32_t system_gclk_chan_get_hz(
const uint8_t channel)
{
1b10: b510 push {r4, lr}
1b12: 0004 movs r4, r0
cpu_irq_enter_critical();
1b14: 4b06 ldr r3, [pc, #24] ; (1b30 <system_gclk_chan_get_hz+0x20>)
1b16: 4798 blx r3
uint8_t gen_id;
system_interrupt_enter_critical_section();
/* Select the requested generic clock channel */
*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
1b18: 4b06 ldr r3, [pc, #24] ; (1b34 <system_gclk_chan_get_hz+0x24>)
1b1a: 701c strb r4, [r3, #0]
gen_id = GCLK->CLKCTRL.bit.GEN;
1b1c: 4b06 ldr r3, [pc, #24] ; (1b38 <system_gclk_chan_get_hz+0x28>)
1b1e: 885c ldrh r4, [r3, #2]
1b20: 0524 lsls r4, r4, #20
1b22: 0f24 lsrs r4, r4, #28
cpu_irq_leave_critical();
1b24: 4b05 ldr r3, [pc, #20] ; (1b3c <system_gclk_chan_get_hz+0x2c>)
1b26: 4798 blx r3
system_interrupt_leave_critical_section();
/* Return the clock speed of the associated GCLK generator */
return system_gclk_gen_get_hz(gen_id);
1b28: 0020 movs r0, r4
1b2a: 4b05 ldr r3, [pc, #20] ; (1b40 <system_gclk_chan_get_hz+0x30>)
1b2c: 4798 blx r3
}
1b2e: bd10 pop {r4, pc}
1b30: 000015e1 .word 0x000015e1
1b34: 40000c02 .word 0x40000c02
1b38: 40000c00 .word 0x40000c00
1b3c: 00001621 .word 0x00001621
1b40: 000019dd .word 0x000019dd
00001b44 <_system_pinmux_config>:
*/
static void _system_pinmux_config(
PortGroup *const port,
const uint32_t pin_mask,
const struct system_pinmux_config *const config)
{
1b44: b530 push {r4, r5, lr}
/* Track the configuration bits into a temporary variable before writing */
uint32_t pin_cfg = 0;
/* Enabled powersave mode, don't create configuration */
if (!config->powersave) {
1b46: 78d3 ldrb r3, [r2, #3]
1b48: 2b00 cmp r3, #0
1b4a: d135 bne.n 1bb8 <_system_pinmux_config+0x74>
/* Enable the pin peripheral MUX flag if non-GPIO selected (pinmux will
* be written later) and store the new MUX mask */
if (config->mux_position != SYSTEM_PINMUX_GPIO) {
1b4c: 7813 ldrb r3, [r2, #0]
1b4e: 2b80 cmp r3, #128 ; 0x80
1b50: d029 beq.n 1ba6 <_system_pinmux_config+0x62>
pin_cfg |= PORT_WRCONFIG_PMUXEN;
pin_cfg |= (config->mux_position << PORT_WRCONFIG_PMUX_Pos);
1b52: 061b lsls r3, r3, #24
1b54: 2480 movs r4, #128 ; 0x80
1b56: 0264 lsls r4, r4, #9
1b58: 4323 orrs r3, r4
}
/* Check if the user has requested that the input buffer be enabled */
if ((config->direction == SYSTEM_PINMUX_PIN_DIR_INPUT) ||
1b5a: 7854 ldrb r4, [r2, #1]
1b5c: 2502 movs r5, #2
1b5e: 43ac bics r4, r5
1b60: d106 bne.n 1b70 <_system_pinmux_config+0x2c>
(config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
/* Enable input buffer flag */
pin_cfg |= PORT_WRCONFIG_INEN;
/* Enable pull-up/pull-down control flag if requested */
if (config->input_pull != SYSTEM_PINMUX_PIN_PULL_NONE) {
1b62: 7894 ldrb r4, [r2, #2]
1b64: 2c00 cmp r4, #0
1b66: d120 bne.n 1baa <_system_pinmux_config+0x66>
pin_cfg |= PORT_WRCONFIG_INEN;
1b68: 2480 movs r4, #128 ; 0x80
1b6a: 02a4 lsls r4, r4, #10
1b6c: 4323 orrs r3, r4
pin_cfg |= PORT_WRCONFIG_PULLEN;
}
/* Clear the port DIR bits to disable the output buffer */
port->DIRCLR.reg = pin_mask;
1b6e: 6041 str r1, [r0, #4]
}
/* Check if the user has requested that the output buffer be enabled */
if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
1b70: 7854 ldrb r4, [r2, #1]
1b72: 3c01 subs r4, #1
1b74: 2c01 cmp r4, #1
1b76: d91c bls.n 1bb2 <_system_pinmux_config+0x6e>
port->DIRCLR.reg = pin_mask;
}
/* The Write Configuration register (WRCONFIG) requires the
* pins to to grouped into two 16-bit half-words - split them out here */
uint32_t lower_pin_mask = (pin_mask & 0xFFFF);
1b78: 040d lsls r5, r1, #16
1b7a: 0c2d lsrs r5, r5, #16
/* Configure the lower 16-bits of the port to the desired configuration,
* including the pin peripheral multiplexer just in case it is enabled */
port->WRCONFIG.reg
= (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG;
1b7c: 24a0 movs r4, #160 ; 0xa0
1b7e: 05e4 lsls r4, r4, #23
1b80: 432c orrs r4, r5
1b82: 431c orrs r4, r3
= (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
1b84: 6284 str r4, [r0, #40] ; 0x28
uint32_t upper_pin_mask = (pin_mask >> 16);
1b86: 0c0d lsrs r5, r1, #16
/* Configure the upper 16-bits of the port to the desired configuration,
* including the pin peripheral multiplexer just in case it is enabled */
port->WRCONFIG.reg
= (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG |
1b88: 24d0 movs r4, #208 ; 0xd0
1b8a: 0624 lsls r4, r4, #24
1b8c: 432c orrs r4, r5
1b8e: 431c orrs r4, r3
= (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
1b90: 6284 str r4, [r0, #40] ; 0x28
PORT_WRCONFIG_HWSEL;
if(!config->powersave) {
1b92: 78d4 ldrb r4, [r2, #3]
1b94: 2c00 cmp r4, #0
1b96: d122 bne.n 1bde <_system_pinmux_config+0x9a>
/* Set the pull-up state once the port pins are configured if one was
* requested and it does not violate the valid set of port
* configurations */
if (pin_cfg & PORT_WRCONFIG_PULLEN) {
1b98: 035b lsls r3, r3, #13
1b9a: d51c bpl.n 1bd6 <_system_pinmux_config+0x92>
/* Set the OUT register bits to enable the pull-up if requested,
* clear to enable pull-down */
if (config->input_pull == SYSTEM_PINMUX_PIN_PULL_UP) {
1b9c: 7893 ldrb r3, [r2, #2]
1b9e: 2b01 cmp r3, #1
1ba0: d01e beq.n 1be0 <_system_pinmux_config+0x9c>
port->OUTSET.reg = pin_mask;
} else {
port->OUTCLR.reg = pin_mask;
1ba2: 6141 str r1, [r0, #20]
1ba4: e017 b.n 1bd6 <_system_pinmux_config+0x92>
uint32_t pin_cfg = 0;
1ba6: 2300 movs r3, #0
1ba8: e7d7 b.n 1b5a <_system_pinmux_config+0x16>
pin_cfg |= PORT_WRCONFIG_PULLEN;
1baa: 24c0 movs r4, #192 ; 0xc0
1bac: 02e4 lsls r4, r4, #11
1bae: 4323 orrs r3, r4
1bb0: e7dd b.n 1b6e <_system_pinmux_config+0x2a>
pin_cfg &= ~PORT_WRCONFIG_PULLEN;
1bb2: 4c0d ldr r4, [pc, #52] ; (1be8 <_system_pinmux_config+0xa4>)
1bb4: 4023 ands r3, r4
1bb6: e7df b.n 1b78 <_system_pinmux_config+0x34>
port->DIRCLR.reg = pin_mask;
1bb8: 6041 str r1, [r0, #4]
uint32_t lower_pin_mask = (pin_mask & 0xFFFF);
1bba: 040c lsls r4, r1, #16
1bbc: 0c24 lsrs r4, r4, #16
pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG;
1bbe: 23a0 movs r3, #160 ; 0xa0
1bc0: 05db lsls r3, r3, #23
1bc2: 4323 orrs r3, r4
= (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
1bc4: 6283 str r3, [r0, #40] ; 0x28
uint32_t upper_pin_mask = (pin_mask >> 16);
1bc6: 0c0c lsrs r4, r1, #16
pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG |
1bc8: 23d0 movs r3, #208 ; 0xd0
1bca: 061b lsls r3, r3, #24
1bcc: 4323 orrs r3, r4
= (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
1bce: 6283 str r3, [r0, #40] ; 0x28
if(!config->powersave) {
1bd0: 78d3 ldrb r3, [r2, #3]
1bd2: 2b00 cmp r3, #0
1bd4: d103 bne.n 1bde <_system_pinmux_config+0x9a>
}
}
/* Check if the user has requested that the output buffer be enabled */
if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
1bd6: 7853 ldrb r3, [r2, #1]
1bd8: 3b01 subs r3, #1
1bda: 2b01 cmp r3, #1
1bdc: d902 bls.n 1be4 <_system_pinmux_config+0xa0>
(config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
/* Set the port DIR bits to enable the output buffer */
port->DIRSET.reg = pin_mask;
}
}
}
1bde: bd30 pop {r4, r5, pc}
port->OUTSET.reg = pin_mask;
1be0: 6181 str r1, [r0, #24]
1be2: e7f8 b.n 1bd6 <_system_pinmux_config+0x92>
port->DIRSET.reg = pin_mask;
1be4: 6081 str r1, [r0, #8]
}
1be6: e7fa b.n 1bde <_system_pinmux_config+0x9a>
1be8: fffbffff .word 0xfffbffff
00001bec <system_pinmux_pin_set_config>:
* \param[in] config Configuration settings for the pin
*/
void system_pinmux_pin_set_config(
const uint8_t gpio_pin,
const struct system_pinmux_config *const config)
{
1bec: b510 push {r4, lr}
1bee: 000a movs r2, r1
uint8_t group_index = (gpio_pin / 32);
/* Array of available ports */
Port *const ports[PORT_INST_NUM] = PORT_INSTS;
if (port_index < PORT_INST_NUM) {
1bf0: 09c1 lsrs r1, r0, #7
return &(ports[port_index]->Group[group_index]);
} else {
Assert(false);
return NULL;
1bf2: 2300 movs r3, #0
if (port_index < PORT_INST_NUM) {
1bf4: 2900 cmp r1, #0
1bf6: d104 bne.n 1c02 <system_pinmux_pin_set_config+0x16>
return &(ports[port_index]->Group[group_index]);
1bf8: 0943 lsrs r3, r0, #5
1bfa: 01db lsls r3, r3, #7
1bfc: 4905 ldr r1, [pc, #20] ; (1c14 <system_pinmux_pin_set_config+0x28>)
1bfe: 468c mov ip, r1
1c00: 4463 add r3, ip
PortGroup *const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
uint32_t pin_mask = (1UL << (gpio_pin % 32));
1c02: 241f movs r4, #31
1c04: 4020 ands r0, r4
1c06: 2101 movs r1, #1
1c08: 4081 lsls r1, r0
_system_pinmux_config(port, pin_mask, config);
1c0a: 0018 movs r0, r3
1c0c: 4b02 ldr r3, [pc, #8] ; (1c18 <system_pinmux_pin_set_config+0x2c>)
1c0e: 4798 blx r3
}
1c10: bd10 pop {r4, pc}
1c12: 46c0 nop ; (mov r8, r8)
1c14: 41004400 .word 0x41004400
1c18: 00001b45 .word 0x00001b45
00001c1c <_system_dummy_init>:
*/
void _system_dummy_init(void);
void _system_dummy_init(void)
{
return;
}
1c1c: 4770 bx lr
...
00001c20 <system_init>:
* - Board hardware initialization (via the Board module)
* - Event system driver initialization (via the EVSYS module)
* - External Interrupt driver initialization (via the EXTINT module)
*/
void system_init(void)
{
1c20: b510 push {r4, lr}
/* Configure GCLK and clock sources according to conf_clocks.h */
system_clock_init();
1c22: 4b05 ldr r3, [pc, #20] ; (1c38 <system_init+0x18>)
1c24: 4798 blx r3
/* Initialize board hardware */
system_board_init();
1c26: 4b05 ldr r3, [pc, #20] ; (1c3c <system_init+0x1c>)
1c28: 4798 blx r3
/* Initialize EVSYS hardware */
_system_events_init();
1c2a: 4b05 ldr r3, [pc, #20] ; (1c40 <system_init+0x20>)
1c2c: 4798 blx r3
/* Initialize External hardware */
_system_extint_init();
1c2e: 4b05 ldr r3, [pc, #20] ; (1c44 <system_init+0x24>)
1c30: 4798 blx r3
/* Initialize DIVAS hardware */
_system_divas_init();
1c32: 4b05 ldr r3, [pc, #20] ; (1c48 <system_init+0x28>)
1c34: 4798 blx r3
}
1c36: bd10 pop {r4, pc}
1c38: 00001825 .word 0x00001825
1c3c: 00001651 .word 0x00001651
1c40: 00001c1d .word 0x00001c1d
1c44: 00001c1d .word 0x00001c1d
1c48: 00001c1d .word 0x00001c1d
00001c4c <Dummy_Handler>:
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
1c4c: e7fe b.n 1c4c <Dummy_Handler>
...
00001c50 <Reset_Handler>:
{
1c50: b5f8 push {r3, r4, r5, r6, r7, lr}
if (pSrc != pDest) {
1c52: 4a2a ldr r2, [pc, #168] ; (1cfc <Reset_Handler+0xac>)
1c54: 4b2a ldr r3, [pc, #168] ; (1d00 <Reset_Handler+0xb0>)
1c56: 429a cmp r2, r3
1c58: d011 beq.n 1c7e <Reset_Handler+0x2e>
for (; pDest < &_erelocate;) {
1c5a: 001a movs r2, r3
1c5c: 4b29 ldr r3, [pc, #164] ; (1d04 <Reset_Handler+0xb4>)
1c5e: 429a cmp r2, r3
1c60: d20d bcs.n 1c7e <Reset_Handler+0x2e>
1c62: 4a29 ldr r2, [pc, #164] ; (1d08 <Reset_Handler+0xb8>)
1c64: 3303 adds r3, #3
1c66: 1a9b subs r3, r3, r2
1c68: 089b lsrs r3, r3, #2
1c6a: 3301 adds r3, #1
1c6c: 009b lsls r3, r3, #2
1c6e: 2200 movs r2, #0
*pDest++ = *pSrc++;
1c70: 4823 ldr r0, [pc, #140] ; (1d00 <Reset_Handler+0xb0>)
1c72: 4922 ldr r1, [pc, #136] ; (1cfc <Reset_Handler+0xac>)
1c74: 588c ldr r4, [r1, r2]
1c76: 5084 str r4, [r0, r2]
1c78: 3204 adds r2, #4
for (; pDest < &_erelocate;) {
1c7a: 429a cmp r2, r3
1c7c: d1fa bne.n 1c74 <Reset_Handler+0x24>
for (pDest = &_szero; pDest < &_ezero;) {
1c7e: 4a23 ldr r2, [pc, #140] ; (1d0c <Reset_Handler+0xbc>)
1c80: 4b23 ldr r3, [pc, #140] ; (1d10 <Reset_Handler+0xc0>)
1c82: 429a cmp r2, r3
1c84: d20a bcs.n 1c9c <Reset_Handler+0x4c>
1c86: 43d3 mvns r3, r2
1c88: 4921 ldr r1, [pc, #132] ; (1d10 <Reset_Handler+0xc0>)
1c8a: 185b adds r3, r3, r1
1c8c: 2103 movs r1, #3
1c8e: 438b bics r3, r1
1c90: 3304 adds r3, #4
1c92: 189b adds r3, r3, r2
*pDest++ = 0;
1c94: 2100 movs r1, #0
1c96: c202 stmia r2!, {r1}
for (pDest = &_szero; pDest < &_ezero;) {
1c98: 4293 cmp r3, r2
1c9a: d1fc bne.n 1c96 <Reset_Handler+0x46>
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
1c9c: 4a1d ldr r2, [pc, #116] ; (1d14 <Reset_Handler+0xc4>)
1c9e: 21ff movs r1, #255 ; 0xff
1ca0: 4b1d ldr r3, [pc, #116] ; (1d18 <Reset_Handler+0xc8>)
1ca2: 438b bics r3, r1
1ca4: 6093 str r3, [r2, #8]
SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2;
1ca6: 39fd subs r1, #253 ; 0xfd
1ca8: 2390 movs r3, #144 ; 0x90
1caa: 005b lsls r3, r3, #1
1cac: 4a1b ldr r2, [pc, #108] ; (1d1c <Reset_Handler+0xcc>)
1cae: 50d1 str r1, [r2, r3]
USB->DEVICE.QOSCTRL.bit.CQOS = 2;
1cb0: 4a1b ldr r2, [pc, #108] ; (1d20 <Reset_Handler+0xd0>)
1cb2: 78d3 ldrb r3, [r2, #3]
1cb4: 2503 movs r5, #3
1cb6: 43ab bics r3, r5
1cb8: 2402 movs r4, #2
1cba: 4323 orrs r3, r4
1cbc: 70d3 strb r3, [r2, #3]
USB->DEVICE.QOSCTRL.bit.DQOS = 2;
1cbe: 78d3 ldrb r3, [r2, #3]
1cc0: 270c movs r7, #12
1cc2: 43bb bics r3, r7
1cc4: 2608 movs r6, #8
1cc6: 4333 orrs r3, r6
1cc8: 70d3 strb r3, [r2, #3]
DMAC->QOSCTRL.bit.DQOS = 2;
1cca: 4b16 ldr r3, [pc, #88] ; (1d24 <Reset_Handler+0xd4>)
1ccc: 7b98 ldrb r0, [r3, #14]
1cce: 2230 movs r2, #48 ; 0x30
1cd0: 4390 bics r0, r2
1cd2: 2220 movs r2, #32
1cd4: 4310 orrs r0, r2
1cd6: 7398 strb r0, [r3, #14]
DMAC->QOSCTRL.bit.FQOS = 2;
1cd8: 7b99 ldrb r1, [r3, #14]
1cda: 43b9 bics r1, r7
1cdc: 4331 orrs r1, r6
1cde: 7399 strb r1, [r3, #14]
DMAC->QOSCTRL.bit.WRBQOS = 2;
1ce0: 7b9a ldrb r2, [r3, #14]
1ce2: 43aa bics r2, r5
1ce4: 4322 orrs r2, r4
1ce6: 739a strb r2, [r3, #14]
NVMCTRL->CTRLB.bit.MANW = 1;
1ce8: 4a0f ldr r2, [pc, #60] ; (1d28 <Reset_Handler+0xd8>)
1cea: 6853 ldr r3, [r2, #4]
1cec: 2180 movs r1, #128 ; 0x80
1cee: 430b orrs r3, r1
1cf0: 6053 str r3, [r2, #4]
__libc_init_array();
1cf2: 4b0e ldr r3, [pc, #56] ; (1d2c <Reset_Handler+0xdc>)
1cf4: 4798 blx r3
main();
1cf6: 4b0e ldr r3, [pc, #56] ; (1d30 <Reset_Handler+0xe0>)
1cf8: 4798 blx r3
1cfa: e7fe b.n 1cfa <Reset_Handler+0xaa>
1cfc: 00003960 .word 0x00003960
1d00: 20000000 .word 0x20000000
1d04: 2000007c .word 0x2000007c
1d08: 20000004 .word 0x20000004
1d0c: 20000080 .word 0x20000080
1d10: 200002a0 .word 0x200002a0
1d14: e000ed00 .word 0xe000ed00
1d18: 00000000 .word 0x00000000
1d1c: 41007000 .word 0x41007000
1d20: 41005000 .word 0x41005000
1d24: 41004800 .word 0x41004800
1d28: 41004000 .word 0x41004000
1d2c: 00002681 .word 0x00002681
1d30: 00001d71 .word 0x00001d71
00001d34 <_sbrk>:
extern void _exit(int status);
extern void _kill(int pid, int sig);
extern int _getpid(void);
extern caddr_t _sbrk(int incr)
{
1d34: 0003 movs r3, r0
static unsigned char *heap = NULL;
unsigned char *prev_heap;
if (heap == NULL) {
1d36: 4a06 ldr r2, [pc, #24] ; (1d50 <_sbrk+0x1c>)
1d38: 6812 ldr r2, [r2, #0]
1d3a: 2a00 cmp r2, #0
1d3c: d004 beq.n 1d48 <_sbrk+0x14>
heap = (unsigned char *)&_end;
}
prev_heap = heap;
1d3e: 4a04 ldr r2, [pc, #16] ; (1d50 <_sbrk+0x1c>)
1d40: 6810 ldr r0, [r2, #0]
heap += incr;
1d42: 18c3 adds r3, r0, r3
1d44: 6013 str r3, [r2, #0]
return (caddr_t) prev_heap;
}
1d46: 4770 bx lr
heap = (unsigned char *)&_end;
1d48: 4902 ldr r1, [pc, #8] ; (1d54 <_sbrk+0x20>)
1d4a: 4a01 ldr r2, [pc, #4] ; (1d50 <_sbrk+0x1c>)
1d4c: 6011 str r1, [r2, #0]
1d4e: e7f6 b.n 1d3e <_sbrk+0xa>
1d50: 200001cc .word 0x200001cc
1d54: 200022a0 .word 0x200022a0
00001d58 <_close>:
}
extern int _close(int file)
{
return -1;
}
1d58: 2001 movs r0, #1
1d5a: 4240 negs r0, r0
1d5c: 4770 bx lr
00001d5e <_fstat>:
extern int _fstat(int file, struct stat *st)
{
st->st_mode = S_IFCHR;
1d5e: 2380 movs r3, #128 ; 0x80
1d60: 019b lsls r3, r3, #6
1d62: 604b str r3, [r1, #4]
return 0;
}
1d64: 2000 movs r0, #0
1d66: 4770 bx lr
00001d68 <_isatty>:
extern int _isatty(int file)
{
return 1;
}
1d68: 2001 movs r0, #1
1d6a: 4770 bx lr
00001d6c <_lseek>:
extern int _lseek(int file, int ptr, int dir)
{
return 0;
}
1d6c: 2000 movs r0, #0
1d6e: 4770 bx lr
00001d70 <main>:
*/
#include <asf.h>
#include "pusart.h"
#include "padc.h"
int main (void)
{
1d70: b5f8 push {r3, r4, r5, r6, r7, lr}
system_init();
1d72: 4b12 ldr r3, [pc, #72] ; (1dbc <main+0x4c>)
1d74: 4798 blx r3
delay_init();
1d76: 4b12 ldr r3, [pc, #72] ; (1dc0 <main+0x50>)
1d78: 4798 blx r3
pusart_init();
1d7a: 4b12 ldr r3, [pc, #72] ; (1dc4 <main+0x54>)
1d7c: 4798 blx r3
padc_init();
1d7e: 4b12 ldr r3, [pc, #72] ; (1dc8 <main+0x58>)
1d80: 4798 blx r3
padc_start();
1d82: 4b12 ldr r3, [pc, #72] ; (1dcc <main+0x5c>)
1d84: 4798 blx r3
for (;;)
{
float voltage = padc_get_voltage();
1d86: 4f12 ldr r7, [pc, #72] ; (1dd0 <main+0x60>)
printf("Voltage: %d.%03d\r\n", (int)voltage, ((int)((voltage - (int)voltage) * 1000)));
1d88: 4e12 ldr r6, [pc, #72] ; (1dd4 <main+0x64>)
float voltage = padc_get_voltage();
1d8a: 47b8 blx r7
1d8c: 1c05 adds r5, r0, #0
printf("Voltage: %d.%03d\r\n", (int)voltage, ((int)((voltage - (int)voltage) * 1000)));
1d8e: 47b0 blx r6
1d90: 0004 movs r4, r0
1d92: 4b11 ldr r3, [pc, #68] ; (1dd8 <main+0x68>)
1d94: 4798 blx r3
1d96: 1c01 adds r1, r0, #0
1d98: 1c28 adds r0, r5, #0
1d9a: 4b10 ldr r3, [pc, #64] ; (1ddc <main+0x6c>)
1d9c: 4798 blx r3
1d9e: 4910 ldr r1, [pc, #64] ; (1de0 <main+0x70>)
1da0: 4b10 ldr r3, [pc, #64] ; (1de4 <main+0x74>)
1da2: 4798 blx r3
1da4: 47b0 blx r6
1da6: 0002 movs r2, r0
1da8: 0021 movs r1, r4
1daa: 480f ldr r0, [pc, #60] ; (1de8 <main+0x78>)
1dac: 4b0f ldr r3, [pc, #60] ; (1dec <main+0x7c>)
1dae: 4798 blx r3
delay_ms(500);
1db0: 20fa movs r0, #250 ; 0xfa
1db2: 0040 lsls r0, r0, #1
1db4: 4b0e ldr r3, [pc, #56] ; (1df0 <main+0x80>)
1db6: 4798 blx r3
1db8: e7e7 b.n 1d8a <main+0x1a>
1dba: 46c0 nop ; (mov r8, r8)
1dbc: 00001c21 .word 0x00001c21
1dc0: 00001575 .word 0x00001575
1dc4: 00000e55 .word 0x00000e55
1dc8: 00000cb9 .word 0x00000cb9
1dcc: 00000d99 .word 0x00000d99
1dd0: 00000de9 .word 0x00000de9
1dd4: 000024d9 .word 0x000024d9
1dd8: 00002519 .word 0x00002519
1ddc: 000021a1 .word 0x000021a1
1de0: 447a0000 .word 0x447a0000
1de4: 00001f61 .word 0x00001f61
1de8: 00003854 .word 0x00003854
1dec: 000026ed .word 0x000026ed
1df0: 000015b5 .word 0x000015b5
00001df4 <__udivsi3>:
1df4: 2200 movs r2, #0
1df6: 0843 lsrs r3, r0, #1
1df8: 428b cmp r3, r1
1dfa: d374 bcc.n 1ee6 <__udivsi3+0xf2>
1dfc: 0903 lsrs r3, r0, #4
1dfe: 428b cmp r3, r1
1e00: d35f bcc.n 1ec2 <__udivsi3+0xce>
1e02: 0a03 lsrs r3, r0, #8
1e04: 428b cmp r3, r1
1e06: d344 bcc.n 1e92 <__udivsi3+0x9e>
1e08: 0b03 lsrs r3, r0, #12
1e0a: 428b cmp r3, r1
1e0c: d328 bcc.n 1e60 <__udivsi3+0x6c>
1e0e: 0c03 lsrs r3, r0, #16
1e10: 428b cmp r3, r1
1e12: d30d bcc.n 1e30 <__udivsi3+0x3c>
1e14: 22ff movs r2, #255 ; 0xff
1e16: 0209 lsls r1, r1, #8
1e18: ba12 rev r2, r2
1e1a: 0c03 lsrs r3, r0, #16
1e1c: 428b cmp r3, r1
1e1e: d302 bcc.n 1e26 <__udivsi3+0x32>
1e20: 1212 asrs r2, r2, #8
1e22: 0209 lsls r1, r1, #8
1e24: d065 beq.n 1ef2 <__udivsi3+0xfe>
1e26: 0b03 lsrs r3, r0, #12
1e28: 428b cmp r3, r1
1e2a: d319 bcc.n 1e60 <__udivsi3+0x6c>
1e2c: e000 b.n 1e30 <__udivsi3+0x3c>
1e2e: 0a09 lsrs r1, r1, #8
1e30: 0bc3 lsrs r3, r0, #15
1e32: 428b cmp r3, r1
1e34: d301 bcc.n 1e3a <__udivsi3+0x46>
1e36: 03cb lsls r3, r1, #15
1e38: 1ac0 subs r0, r0, r3
1e3a: 4152 adcs r2, r2
1e3c: 0b83 lsrs r3, r0, #14
1e3e: 428b cmp r3, r1
1e40: d301 bcc.n 1e46 <__udivsi3+0x52>
1e42: 038b lsls r3, r1, #14
1e44: 1ac0 subs r0, r0, r3
1e46: 4152 adcs r2, r2
1e48: 0b43 lsrs r3, r0, #13
1e4a: 428b cmp r3, r1
1e4c: d301 bcc.n 1e52 <__udivsi3+0x5e>
1e4e: 034b lsls r3, r1, #13
1e50: 1ac0 subs r0, r0, r3
1e52: 4152 adcs r2, r2
1e54: 0b03 lsrs r3, r0, #12
1e56: 428b cmp r3, r1
1e58: d301 bcc.n 1e5e <__udivsi3+0x6a>
1e5a: 030b lsls r3, r1, #12
1e5c: 1ac0 subs r0, r0, r3
1e5e: 4152 adcs r2, r2
1e60: 0ac3 lsrs r3, r0, #11
1e62: 428b cmp r3, r1
1e64: d301 bcc.n 1e6a <__udivsi3+0x76>
1e66: 02cb lsls r3, r1, #11
1e68: 1ac0 subs r0, r0, r3
1e6a: 4152 adcs r2, r2
1e6c: 0a83 lsrs r3, r0, #10
1e6e: 428b cmp r3, r1
1e70: d301 bcc.n 1e76 <__udivsi3+0x82>
1e72: 028b lsls r3, r1, #10
1e74: 1ac0 subs r0, r0, r3
1e76: 4152 adcs r2, r2
1e78: 0a43 lsrs r3, r0, #9
1e7a: 428b cmp r3, r1
1e7c: d301 bcc.n 1e82 <__udivsi3+0x8e>
1e7e: 024b lsls r3, r1, #9
1e80: 1ac0 subs r0, r0, r3
1e82: 4152 adcs r2, r2
1e84: 0a03 lsrs r3, r0, #8
1e86: 428b cmp r3, r1
1e88: d301 bcc.n 1e8e <__udivsi3+0x9a>
1e8a: 020b lsls r3, r1, #8
1e8c: 1ac0 subs r0, r0, r3
1e8e: 4152 adcs r2, r2
1e90: d2cd bcs.n 1e2e <__udivsi3+0x3a>
1e92: 09c3 lsrs r3, r0, #7
1e94: 428b cmp r3, r1
1e96: d301 bcc.n 1e9c <__udivsi3+0xa8>
1e98: 01cb lsls r3, r1, #7
1e9a: 1ac0 subs r0, r0, r3
1e9c: 4152 adcs r2, r2
1e9e: 0983 lsrs r3, r0, #6
1ea0: 428b cmp r3, r1
1ea2: d301 bcc.n 1ea8 <__udivsi3+0xb4>
1ea4: 018b lsls r3, r1, #6
1ea6: 1ac0 subs r0, r0, r3
1ea8: 4152 adcs r2, r2
1eaa: 0943 lsrs r3, r0, #5
1eac: 428b cmp r3, r1
1eae: d301 bcc.n 1eb4 <__udivsi3+0xc0>
1eb0: 014b lsls r3, r1, #5
1eb2: 1ac0 subs r0, r0, r3
1eb4: 4152 adcs r2, r2
1eb6: 0903 lsrs r3, r0, #4
1eb8: 428b cmp r3, r1
1eba: d301 bcc.n 1ec0 <__udivsi3+0xcc>
1ebc: 010b lsls r3, r1, #4
1ebe: 1ac0 subs r0, r0, r3
1ec0: 4152 adcs r2, r2
1ec2: 08c3 lsrs r3, r0, #3
1ec4: 428b cmp r3, r1
1ec6: d301 bcc.n 1ecc <__udivsi3+0xd8>
1ec8: 00cb lsls r3, r1, #3
1eca: 1ac0 subs r0, r0, r3
1ecc: 4152 adcs r2, r2
1ece: 0883 lsrs r3, r0, #2
1ed0: 428b cmp r3, r1
1ed2: d301 bcc.n 1ed8 <__udivsi3+0xe4>
1ed4: 008b lsls r3, r1, #2
1ed6: 1ac0 subs r0, r0, r3
1ed8: 4152 adcs r2, r2
1eda: 0843 lsrs r3, r0, #1
1edc: 428b cmp r3, r1
1ede: d301 bcc.n 1ee4 <__udivsi3+0xf0>
1ee0: 004b lsls r3, r1, #1
1ee2: 1ac0 subs r0, r0, r3
1ee4: 4152 adcs r2, r2
1ee6: 1a41 subs r1, r0, r1
1ee8: d200 bcs.n 1eec <__udivsi3+0xf8>
1eea: 4601 mov r1, r0
1eec: 4152 adcs r2, r2
1eee: 4610 mov r0, r2
1ef0: 4770 bx lr
1ef2: e7ff b.n 1ef4 <__udivsi3+0x100>
1ef4: b501 push {r0, lr}
1ef6: 2000 movs r0, #0
1ef8: f000 f806 bl 1f08 <__aeabi_idiv0>
1efc: bd02 pop {r1, pc}
1efe: 46c0 nop ; (mov r8, r8)
00001f00 <__aeabi_uidivmod>:
1f00: 2900 cmp r1, #0
1f02: d0f7 beq.n 1ef4 <__udivsi3+0x100>
1f04: e776 b.n 1df4 <__udivsi3>
1f06: 4770 bx lr
00001f08 <__aeabi_idiv0>:
1f08: 4770 bx lr
1f0a: 46c0 nop ; (mov r8, r8)
00001f0c <__aeabi_lmul>:
1f0c: b5f0 push {r4, r5, r6, r7, lr}
1f0e: 46ce mov lr, r9
1f10: 4647 mov r7, r8
1f12: 0415 lsls r5, r2, #16
1f14: 0c2d lsrs r5, r5, #16
1f16: 002e movs r6, r5
1f18: b580 push {r7, lr}
1f1a: 0407 lsls r7, r0, #16
1f1c: 0c14 lsrs r4, r2, #16
1f1e: 0c3f lsrs r7, r7, #16
1f20: 4699 mov r9, r3
1f22: 0c03 lsrs r3, r0, #16
1f24: 437e muls r6, r7
1f26: 435d muls r5, r3
1f28: 4367 muls r7, r4
1f2a: 4363 muls r3, r4
1f2c: 197f adds r7, r7, r5
1f2e: 0c34 lsrs r4, r6, #16
1f30: 19e4 adds r4, r4, r7
1f32: 469c mov ip, r3
1f34: 42a5 cmp r5, r4
1f36: d903 bls.n 1f40 <__aeabi_lmul+0x34>
1f38: 2380 movs r3, #128 ; 0x80
1f3a: 025b lsls r3, r3, #9
1f3c: 4698 mov r8, r3
1f3e: 44c4 add ip, r8
1f40: 464b mov r3, r9
1f42: 4351 muls r1, r2
1f44: 4343 muls r3, r0
1f46: 0436 lsls r6, r6, #16
1f48: 0c36 lsrs r6, r6, #16
1f4a: 0c25 lsrs r5, r4, #16
1f4c: 0424 lsls r4, r4, #16
1f4e: 4465 add r5, ip
1f50: 19a4 adds r4, r4, r6
1f52: 1859 adds r1, r3, r1
1f54: 1949 adds r1, r1, r5
1f56: 0020 movs r0, r4
1f58: bc0c pop {r2, r3}
1f5a: 4690 mov r8, r2
1f5c: 4699 mov r9, r3
1f5e: bdf0 pop {r4, r5, r6, r7, pc}
00001f60 <__aeabi_fmul>:
1f60: b5f8 push {r3, r4, r5, r6, r7, lr}
1f62: 4657 mov r7, sl
1f64: 464e mov r6, r9
1f66: 4645 mov r5, r8
1f68: 46de mov lr, fp
1f6a: b5e0 push {r5, r6, r7, lr}
1f6c: 0247 lsls r7, r0, #9
1f6e: 0046 lsls r6, r0, #1
1f70: 4688 mov r8, r1
1f72: 0a7f lsrs r7, r7, #9
1f74: 0e36 lsrs r6, r6, #24
1f76: 0fc4 lsrs r4, r0, #31
1f78: 2e00 cmp r6, #0
1f7a: d047 beq.n 200c <STACK_SIZE+0xc>
1f7c: 2eff cmp r6, #255 ; 0xff
1f7e: d024 beq.n 1fca <__aeabi_fmul+0x6a>
1f80: 00fb lsls r3, r7, #3
1f82: 2780 movs r7, #128 ; 0x80
1f84: 04ff lsls r7, r7, #19
1f86: 431f orrs r7, r3
1f88: 2300 movs r3, #0
1f8a: 4699 mov r9, r3
1f8c: 469a mov sl, r3
1f8e: 3e7f subs r6, #127 ; 0x7f
1f90: 4643 mov r3, r8
1f92: 025d lsls r5, r3, #9
1f94: 0058 lsls r0, r3, #1
1f96: 0fdb lsrs r3, r3, #31
1f98: 0a6d lsrs r5, r5, #9
1f9a: 0e00 lsrs r0, r0, #24
1f9c: 4698 mov r8, r3
1f9e: d043 beq.n 2028 <STACK_SIZE+0x28>
1fa0: 28ff cmp r0, #255 ; 0xff
1fa2: d03b beq.n 201c <STACK_SIZE+0x1c>
1fa4: 00eb lsls r3, r5, #3
1fa6: 2580 movs r5, #128 ; 0x80
1fa8: 2200 movs r2, #0
1faa: 04ed lsls r5, r5, #19
1fac: 431d orrs r5, r3
1fae: 387f subs r0, #127 ; 0x7f
1fb0: 1836 adds r6, r6, r0
1fb2: 1c73 adds r3, r6, #1
1fb4: 4641 mov r1, r8
1fb6: 469b mov fp, r3
1fb8: 464b mov r3, r9
1fba: 4061 eors r1, r4
1fbc: 4313 orrs r3, r2
1fbe: 2b0f cmp r3, #15
1fc0: d864 bhi.n 208c <STACK_SIZE+0x8c>
1fc2: 4875 ldr r0, [pc, #468] ; (2198 <STACK_SIZE+0x198>)
1fc4: 009b lsls r3, r3, #2
1fc6: 58c3 ldr r3, [r0, r3]
1fc8: 469f mov pc, r3
1fca: 2f00 cmp r7, #0
1fcc: d142 bne.n 2054 <STACK_SIZE+0x54>
1fce: 2308 movs r3, #8
1fd0: 4699 mov r9, r3
1fd2: 3b06 subs r3, #6
1fd4: 26ff movs r6, #255 ; 0xff
1fd6: 469a mov sl, r3
1fd8: e7da b.n 1f90 <__aeabi_fmul+0x30>
1fda: 4641 mov r1, r8
1fdc: 2a02 cmp r2, #2
1fde: d028 beq.n 2032 <STACK_SIZE+0x32>
1fe0: 2a03 cmp r2, #3
1fe2: d100 bne.n 1fe6 <__aeabi_fmul+0x86>
1fe4: e0ce b.n 2184 <STACK_SIZE+0x184>
1fe6: 2a01 cmp r2, #1
1fe8: d000 beq.n 1fec <__aeabi_fmul+0x8c>
1fea: e0ac b.n 2146 <STACK_SIZE+0x146>
1fec: 4011 ands r1, r2
1fee: 2000 movs r0, #0
1ff0: 2200 movs r2, #0
1ff2: b2cc uxtb r4, r1
1ff4: 0240 lsls r0, r0, #9
1ff6: 05d2 lsls r2, r2, #23
1ff8: 0a40 lsrs r0, r0, #9
1ffa: 07e4 lsls r4, r4, #31
1ffc: 4310 orrs r0, r2
1ffe: 4320 orrs r0, r4
2000: bc3c pop {r2, r3, r4, r5}
2002: 4690 mov r8, r2
2004: 4699 mov r9, r3
2006: 46a2 mov sl, r4
2008: 46ab mov fp, r5
200a: bdf8 pop {r3, r4, r5, r6, r7, pc}
200c: 2f00 cmp r7, #0
200e: d115 bne.n 203c <STACK_SIZE+0x3c>
2010: 2304 movs r3, #4
2012: 4699 mov r9, r3
2014: 3b03 subs r3, #3
2016: 2600 movs r6, #0
2018: 469a mov sl, r3
201a: e7b9 b.n 1f90 <__aeabi_fmul+0x30>
201c: 20ff movs r0, #255 ; 0xff
201e: 2202 movs r2, #2
2020: 2d00 cmp r5, #0
2022: d0c5 beq.n 1fb0 <__aeabi_fmul+0x50>
2024: 2203 movs r2, #3
2026: e7c3 b.n 1fb0 <__aeabi_fmul+0x50>
2028: 2d00 cmp r5, #0
202a: d119 bne.n 2060 <STACK_SIZE+0x60>
202c: 2000 movs r0, #0
202e: 2201 movs r2, #1
2030: e7be b.n 1fb0 <__aeabi_fmul+0x50>
2032: 2401 movs r4, #1
2034: 22ff movs r2, #255 ; 0xff
2036: 400c ands r4, r1
2038: 2000 movs r0, #0
203a: e7db b.n 1ff4 <__aeabi_fmul+0x94>
203c: 0038 movs r0, r7
203e: f000 fb01 bl 2644 <__clzsi2>
2042: 2676 movs r6, #118 ; 0x76
2044: 1f43 subs r3, r0, #5
2046: 409f lsls r7, r3
2048: 2300 movs r3, #0
204a: 4276 negs r6, r6
204c: 1a36 subs r6, r6, r0
204e: 4699 mov r9, r3
2050: 469a mov sl, r3
2052: e79d b.n 1f90 <__aeabi_fmul+0x30>
2054: 230c movs r3, #12
2056: 4699 mov r9, r3
2058: 3b09 subs r3, #9
205a: 26ff movs r6, #255 ; 0xff
205c: 469a mov sl, r3
205e: e797 b.n 1f90 <__aeabi_fmul+0x30>
2060: 0028 movs r0, r5
2062: f000 faef bl 2644 <__clzsi2>
2066: 1f43 subs r3, r0, #5
2068: 409d lsls r5, r3
206a: 2376 movs r3, #118 ; 0x76
206c: 425b negs r3, r3
206e: 1a18 subs r0, r3, r0
2070: 2200 movs r2, #0
2072: e79d b.n 1fb0 <__aeabi_fmul+0x50>
2074: 2080 movs r0, #128 ; 0x80
2076: 2400 movs r4, #0
2078: 03c0 lsls r0, r0, #15
207a: 22ff movs r2, #255 ; 0xff
207c: e7ba b.n 1ff4 <__aeabi_fmul+0x94>
207e: 003d movs r5, r7
2080: 4652 mov r2, sl
2082: e7ab b.n 1fdc <__aeabi_fmul+0x7c>
2084: 003d movs r5, r7
2086: 0021 movs r1, r4
2088: 4652 mov r2, sl
208a: e7a7 b.n 1fdc <__aeabi_fmul+0x7c>
208c: 0c3b lsrs r3, r7, #16
208e: 469c mov ip, r3
2090: 042a lsls r2, r5, #16
2092: 0c12 lsrs r2, r2, #16
2094: 0c2b lsrs r3, r5, #16
2096: 0014 movs r4, r2
2098: 4660 mov r0, ip
209a: 4665 mov r5, ip
209c: 043f lsls r7, r7, #16
209e: 0c3f lsrs r7, r7, #16
20a0: 437c muls r4, r7
20a2: 4342 muls r2, r0
20a4: 435d muls r5, r3
20a6: 437b muls r3, r7
20a8: 0c27 lsrs r7, r4, #16
20aa: 189b adds r3, r3, r2
20ac: 18ff adds r7, r7, r3
20ae: 42ba cmp r2, r7
20b0: d903 bls.n 20ba <STACK_SIZE+0xba>
20b2: 2380 movs r3, #128 ; 0x80
20b4: 025b lsls r3, r3, #9
20b6: 469c mov ip, r3
20b8: 4465 add r5, ip
20ba: 0424 lsls r4, r4, #16
20bc: 043a lsls r2, r7, #16
20be: 0c24 lsrs r4, r4, #16
20c0: 1912 adds r2, r2, r4
20c2: 0193 lsls r3, r2, #6
20c4: 1e5c subs r4, r3, #1
20c6: 41a3 sbcs r3, r4
20c8: 0c3f lsrs r7, r7, #16
20ca: 0e92 lsrs r2, r2, #26
20cc: 197d adds r5, r7, r5
20ce: 431a orrs r2, r3
20d0: 01ad lsls r5, r5, #6
20d2: 4315 orrs r5, r2
20d4: 012b lsls r3, r5, #4
20d6: d504 bpl.n 20e2 <STACK_SIZE+0xe2>
20d8: 2301 movs r3, #1
20da: 465e mov r6, fp
20dc: 086a lsrs r2, r5, #1
20de: 401d ands r5, r3
20e0: 4315 orrs r5, r2
20e2: 0032 movs r2, r6
20e4: 327f adds r2, #127 ; 0x7f
20e6: 2a00 cmp r2, #0
20e8: dd25 ble.n 2136 <STACK_SIZE+0x136>
20ea: 076b lsls r3, r5, #29
20ec: d004 beq.n 20f8 <STACK_SIZE+0xf8>
20ee: 230f movs r3, #15
20f0: 402b ands r3, r5
20f2: 2b04 cmp r3, #4
20f4: d000 beq.n 20f8 <STACK_SIZE+0xf8>
20f6: 3504 adds r5, #4
20f8: 012b lsls r3, r5, #4
20fa: d503 bpl.n 2104 <STACK_SIZE+0x104>
20fc: 0032 movs r2, r6
20fe: 4b27 ldr r3, [pc, #156] ; (219c <STACK_SIZE+0x19c>)
2100: 3280 adds r2, #128 ; 0x80
2102: 401d ands r5, r3
2104: 2afe cmp r2, #254 ; 0xfe
2106: dc94 bgt.n 2032 <STACK_SIZE+0x32>
2108: 2401 movs r4, #1
210a: 01a8 lsls r0, r5, #6
210c: 0a40 lsrs r0, r0, #9
210e: b2d2 uxtb r2, r2
2110: 400c ands r4, r1
2112: e76f b.n 1ff4 <__aeabi_fmul+0x94>
2114: 2080 movs r0, #128 ; 0x80
2116: 03c0 lsls r0, r0, #15
2118: 4207 tst r7, r0
211a: d007 beq.n 212c <STACK_SIZE+0x12c>
211c: 4205 tst r5, r0
211e: d105 bne.n 212c <STACK_SIZE+0x12c>
2120: 4328 orrs r0, r5
2122: 0240 lsls r0, r0, #9
2124: 0a40 lsrs r0, r0, #9
2126: 4644 mov r4, r8
2128: 22ff movs r2, #255 ; 0xff
212a: e763 b.n 1ff4 <__aeabi_fmul+0x94>
212c: 4338 orrs r0, r7
212e: 0240 lsls r0, r0, #9
2130: 0a40 lsrs r0, r0, #9
2132: 22ff movs r2, #255 ; 0xff
2134: e75e b.n 1ff4 <__aeabi_fmul+0x94>
2136: 2401 movs r4, #1
2138: 1aa3 subs r3, r4, r2
213a: 2b1b cmp r3, #27
213c: dd05 ble.n 214a <STACK_SIZE+0x14a>
213e: 400c ands r4, r1
2140: 2200 movs r2, #0
2142: 2000 movs r0, #0
2144: e756 b.n 1ff4 <__aeabi_fmul+0x94>
2146: 465e mov r6, fp
2148: e7cb b.n 20e2 <STACK_SIZE+0xe2>
214a: 002a movs r2, r5
214c: 2020 movs r0, #32
214e: 40da lsrs r2, r3
2150: 1ac3 subs r3, r0, r3
2152: 409d lsls r5, r3
2154: 002b movs r3, r5
2156: 1e5d subs r5, r3, #1
2158: 41ab sbcs r3, r5
215a: 4313 orrs r3, r2
215c: 075a lsls r2, r3, #29
215e: d004 beq.n 216a <STACK_SIZE+0x16a>
2160: 220f movs r2, #15
2162: 401a ands r2, r3
2164: 2a04 cmp r2, #4
2166: d000 beq.n 216a <STACK_SIZE+0x16a>
2168: 3304 adds r3, #4
216a: 015a lsls r2, r3, #5
216c: d504 bpl.n 2178 <STACK_SIZE+0x178>
216e: 2401 movs r4, #1
2170: 2201 movs r2, #1
2172: 400c ands r4, r1
2174: 2000 movs r0, #0
2176: e73d b.n 1ff4 <__aeabi_fmul+0x94>
2178: 2401 movs r4, #1
217a: 019b lsls r3, r3, #6
217c: 0a58 lsrs r0, r3, #9
217e: 400c ands r4, r1
2180: 2200 movs r2, #0
2182: e737 b.n 1ff4 <__aeabi_fmul+0x94>
2184: 2080 movs r0, #128 ; 0x80
2186: 2401 movs r4, #1
2188: 03c0 lsls r0, r0, #15
218a: 4328 orrs r0, r5
218c: 0240 lsls r0, r0, #9
218e: 0a40 lsrs r0, r0, #9
2190: 400c ands r4, r1
2192: 22ff movs r2, #255 ; 0xff
2194: e72e b.n 1ff4 <__aeabi_fmul+0x94>
2196: 46c0 nop ; (mov r8, r8)
2198: 00003868 .word 0x00003868
219c: f7ffffff .word 0xf7ffffff
000021a0 <__aeabi_fsub>:
21a0: b5f0 push {r4, r5, r6, r7, lr}
21a2: 464f mov r7, r9
21a4: 46d6 mov lr, sl
21a6: 4646 mov r6, r8
21a8: 0044 lsls r4, r0, #1
21aa: b5c0 push {r6, r7, lr}
21ac: 0fc2 lsrs r2, r0, #31
21ae: 0247 lsls r7, r0, #9
21b0: 0248 lsls r0, r1, #9
21b2: 0a40 lsrs r0, r0, #9
21b4: 4684 mov ip, r0
21b6: 4666 mov r6, ip
21b8: 0a7b lsrs r3, r7, #9
21ba: 0048 lsls r0, r1, #1
21bc: 0fc9 lsrs r1, r1, #31
21be: 469a mov sl, r3
21c0: 0e24 lsrs r4, r4, #24
21c2: 0015 movs r5, r2
21c4: 00db lsls r3, r3, #3
21c6: 0e00 lsrs r0, r0, #24
21c8: 4689 mov r9, r1
21ca: 00f6 lsls r6, r6, #3
21cc: 28ff cmp r0, #255 ; 0xff
21ce: d100 bne.n 21d2 <__aeabi_fsub+0x32>
21d0: e08f b.n 22f2 <__aeabi_fsub+0x152>
21d2: 2101 movs r1, #1
21d4: 464f mov r7, r9
21d6: 404f eors r7, r1
21d8: 0039 movs r1, r7
21da: 4291 cmp r1, r2
21dc: d066 beq.n 22ac <__aeabi_fsub+0x10c>
21de: 1a22 subs r2, r4, r0
21e0: 2a00 cmp r2, #0
21e2: dc00 bgt.n 21e6 <__aeabi_fsub+0x46>
21e4: e09d b.n 2322 <__aeabi_fsub+0x182>
21e6: 2800 cmp r0, #0
21e8: d13d bne.n 2266 <__aeabi_fsub+0xc6>
21ea: 2e00 cmp r6, #0
21ec: d100 bne.n 21f0 <__aeabi_fsub+0x50>
21ee: e08b b.n 2308 <__aeabi_fsub+0x168>
21f0: 1e51 subs r1, r2, #1
21f2: 2900 cmp r1, #0
21f4: d000 beq.n 21f8 <__aeabi_fsub+0x58>
21f6: e0b5 b.n 2364 <__aeabi_fsub+0x1c4>
21f8: 2401 movs r4, #1
21fa: 1b9b subs r3, r3, r6
21fc: 015a lsls r2, r3, #5
21fe: d544 bpl.n 228a <__aeabi_fsub+0xea>
2200: 019b lsls r3, r3, #6
2202: 099f lsrs r7, r3, #6
2204: 0038 movs r0, r7
2206: f000 fa1d bl 2644 <__clzsi2>
220a: 3805 subs r0, #5
220c: 4087 lsls r7, r0
220e: 4284 cmp r4, r0
2210: dd00 ble.n 2214 <__aeabi_fsub+0x74>
2212: e096 b.n 2342 <__aeabi_fsub+0x1a2>
2214: 1b04 subs r4, r0, r4
2216: 003a movs r2, r7
2218: 2020 movs r0, #32
221a: 3401 adds r4, #1
221c: 40e2 lsrs r2, r4
221e: 1b04 subs r4, r0, r4
2220: 40a7 lsls r7, r4
2222: 003b movs r3, r7
2224: 1e5f subs r7, r3, #1
2226: 41bb sbcs r3, r7
2228: 2400 movs r4, #0
222a: 4313 orrs r3, r2
222c: 075a lsls r2, r3, #29
222e: d004 beq.n 223a <__aeabi_fsub+0x9a>
2230: 220f movs r2, #15
2232: 401a ands r2, r3
2234: 2a04 cmp r2, #4
2236: d000 beq.n 223a <__aeabi_fsub+0x9a>
2238: 3304 adds r3, #4
223a: 015a lsls r2, r3, #5
223c: d527 bpl.n 228e <__aeabi_fsub+0xee>
223e: 3401 adds r4, #1
2240: 2cff cmp r4, #255 ; 0xff
2242: d100 bne.n 2246 <__aeabi_fsub+0xa6>
2244: e079 b.n 233a <__aeabi_fsub+0x19a>
2246: 2201 movs r2, #1
2248: 019b lsls r3, r3, #6
224a: 0a5b lsrs r3, r3, #9
224c: b2e4 uxtb r4, r4
224e: 402a ands r2, r5
2250: 025b lsls r3, r3, #9
2252: 05e4 lsls r4, r4, #23
2254: 0a58 lsrs r0, r3, #9
2256: 07d2 lsls r2, r2, #31
2258: 4320 orrs r0, r4
225a: 4310 orrs r0, r2
225c: bc1c pop {r2, r3, r4}
225e: 4690 mov r8, r2
2260: 4699 mov r9, r3
2262: 46a2 mov sl, r4
2264: bdf0 pop {r4, r5, r6, r7, pc}
2266: 2cff cmp r4, #255 ; 0xff
2268: d0e0 beq.n 222c <__aeabi_fsub+0x8c>
226a: 2180 movs r1, #128 ; 0x80
226c: 04c9 lsls r1, r1, #19
226e: 430e orrs r6, r1
2270: 2a1b cmp r2, #27
2272: dc7b bgt.n 236c <__aeabi_fsub+0x1cc>
2274: 0031 movs r1, r6
2276: 2020 movs r0, #32
2278: 40d1 lsrs r1, r2
227a: 1a82 subs r2, r0, r2
227c: 4096 lsls r6, r2
227e: 1e72 subs r2, r6, #1
2280: 4196 sbcs r6, r2
2282: 430e orrs r6, r1
2284: 1b9b subs r3, r3, r6
2286: 015a lsls r2, r3, #5
2288: d4ba bmi.n 2200 <__aeabi_fsub+0x60>
228a: 075a lsls r2, r3, #29
228c: d1d0 bne.n 2230 <__aeabi_fsub+0x90>
228e: 2201 movs r2, #1
2290: 08df lsrs r7, r3, #3
2292: 402a ands r2, r5
2294: 2cff cmp r4, #255 ; 0xff
2296: d133 bne.n 2300 <__aeabi_fsub+0x160>
2298: 2f00 cmp r7, #0
229a: d100 bne.n 229e <__aeabi_fsub+0xfe>
229c: e0a8 b.n 23f0 <__aeabi_fsub+0x250>
229e: 2380 movs r3, #128 ; 0x80
22a0: 03db lsls r3, r3, #15
22a2: 433b orrs r3, r7
22a4: 025b lsls r3, r3, #9
22a6: 0a5b lsrs r3, r3, #9
22a8: 24ff movs r4, #255 ; 0xff
22aa: e7d1 b.n 2250 <__aeabi_fsub+0xb0>
22ac: 1a21 subs r1, r4, r0
22ae: 2900 cmp r1, #0
22b0: dd4c ble.n 234c <__aeabi_fsub+0x1ac>
22b2: 2800 cmp r0, #0
22b4: d02a beq.n 230c <__aeabi_fsub+0x16c>
22b6: 2cff cmp r4, #255 ; 0xff
22b8: d0b8 beq.n 222c <__aeabi_fsub+0x8c>
22ba: 2080 movs r0, #128 ; 0x80
22bc: 04c0 lsls r0, r0, #19
22be: 4306 orrs r6, r0
22c0: 291b cmp r1, #27
22c2: dd00 ble.n 22c6 <__aeabi_fsub+0x126>
22c4: e0af b.n 2426 <__aeabi_fsub+0x286>
22c6: 0030 movs r0, r6
22c8: 2720 movs r7, #32
22ca: 40c8 lsrs r0, r1
22cc: 1a79 subs r1, r7, r1
22ce: 408e lsls r6, r1
22d0: 1e71 subs r1, r6, #1
22d2: 418e sbcs r6, r1
22d4: 4306 orrs r6, r0
22d6: 199b adds r3, r3, r6
22d8: 0159 lsls r1, r3, #5
22da: d5d6 bpl.n 228a <__aeabi_fsub+0xea>
22dc: 3401 adds r4, #1
22de: 2cff cmp r4, #255 ; 0xff
22e0: d100 bne.n 22e4 <__aeabi_fsub+0x144>
22e2: e085 b.n 23f0 <__aeabi_fsub+0x250>
22e4: 2201 movs r2, #1
22e6: 497a ldr r1, [pc, #488] ; (24d0 <__aeabi_fsub+0x330>)
22e8: 401a ands r2, r3
22ea: 085b lsrs r3, r3, #1
22ec: 400b ands r3, r1
22ee: 4313 orrs r3, r2
22f0: e79c b.n 222c <__aeabi_fsub+0x8c>
22f2: 2e00 cmp r6, #0
22f4: d000 beq.n 22f8 <__aeabi_fsub+0x158>
22f6: e770 b.n 21da <__aeabi_fsub+0x3a>
22f8: e76b b.n 21d2 <__aeabi_fsub+0x32>
22fa: 1e3b subs r3, r7, #0
22fc: d1c5 bne.n 228a <__aeabi_fsub+0xea>
22fe: 2200 movs r2, #0
2300: 027b lsls r3, r7, #9
2302: 0a5b lsrs r3, r3, #9
2304: b2e4 uxtb r4, r4
2306: e7a3 b.n 2250 <__aeabi_fsub+0xb0>
2308: 0014 movs r4, r2
230a: e78f b.n 222c <__aeabi_fsub+0x8c>
230c: 2e00 cmp r6, #0
230e: d04d beq.n 23ac <__aeabi_fsub+0x20c>
2310: 1e48 subs r0, r1, #1
2312: 2800 cmp r0, #0
2314: d157 bne.n 23c6 <__aeabi_fsub+0x226>
2316: 199b adds r3, r3, r6
2318: 2401 movs r4, #1
231a: 015a lsls r2, r3, #5
231c: d5b5 bpl.n 228a <__aeabi_fsub+0xea>
231e: 2402 movs r4, #2
2320: e7e0 b.n 22e4 <__aeabi_fsub+0x144>
2322: 2a00 cmp r2, #0
2324: d125 bne.n 2372 <__aeabi_fsub+0x1d2>
2326: 1c62 adds r2, r4, #1
2328: b2d2 uxtb r2, r2
232a: 2a01 cmp r2, #1
232c: dd72 ble.n 2414 <__aeabi_fsub+0x274>
232e: 1b9f subs r7, r3, r6
2330: 017a lsls r2, r7, #5
2332: d535 bpl.n 23a0 <__aeabi_fsub+0x200>
2334: 1af7 subs r7, r6, r3
2336: 000d movs r5, r1
2338: e764 b.n 2204 <__aeabi_fsub+0x64>
233a: 2201 movs r2, #1
233c: 2300 movs r3, #0
233e: 402a ands r2, r5
2340: e786 b.n 2250 <__aeabi_fsub+0xb0>
2342: 003b movs r3, r7
2344: 4a63 ldr r2, [pc, #396] ; (24d4 <__aeabi_fsub+0x334>)
2346: 1a24 subs r4, r4, r0
2348: 4013 ands r3, r2
234a: e76f b.n 222c <__aeabi_fsub+0x8c>
234c: 2900 cmp r1, #0
234e: d16c bne.n 242a <__aeabi_fsub+0x28a>
2350: 1c61 adds r1, r4, #1
2352: b2c8 uxtb r0, r1
2354: 2801 cmp r0, #1
2356: dd4e ble.n 23f6 <__aeabi_fsub+0x256>
2358: 29ff cmp r1, #255 ; 0xff
235a: d049 beq.n 23f0 <__aeabi_fsub+0x250>
235c: 199b adds r3, r3, r6
235e: 085b lsrs r3, r3, #1
2360: 000c movs r4, r1
2362: e763 b.n 222c <__aeabi_fsub+0x8c>
2364: 2aff cmp r2, #255 ; 0xff
2366: d041 beq.n 23ec <__aeabi_fsub+0x24c>
2368: 000a movs r2, r1
236a: e781 b.n 2270 <__aeabi_fsub+0xd0>
236c: 2601 movs r6, #1
236e: 1b9b subs r3, r3, r6
2370: e789 b.n 2286 <__aeabi_fsub+0xe6>
2372: 2c00 cmp r4, #0
2374: d01c beq.n 23b0 <__aeabi_fsub+0x210>
2376: 28ff cmp r0, #255 ; 0xff
2378: d021 beq.n 23be <__aeabi_fsub+0x21e>
237a: 2480 movs r4, #128 ; 0x80
237c: 04e4 lsls r4, r4, #19
237e: 4252 negs r2, r2
2380: 4323 orrs r3, r4
2382: 2a1b cmp r2, #27
2384: dd00 ble.n 2388 <__aeabi_fsub+0x1e8>
2386: e096 b.n 24b6 <__aeabi_fsub+0x316>
2388: 001c movs r4, r3
238a: 2520 movs r5, #32
238c: 40d4 lsrs r4, r2
238e: 1aaa subs r2, r5, r2
2390: 4093 lsls r3, r2
2392: 1e5a subs r2, r3, #1
2394: 4193 sbcs r3, r2
2396: 4323 orrs r3, r4
2398: 1af3 subs r3, r6, r3
239a: 0004 movs r4, r0
239c: 000d movs r5, r1
239e: e72d b.n 21fc <__aeabi_fsub+0x5c>
23a0: 2f00 cmp r7, #0
23a2: d000 beq.n 23a6 <__aeabi_fsub+0x206>
23a4: e72e b.n 2204 <__aeabi_fsub+0x64>
23a6: 2200 movs r2, #0
23a8: 2400 movs r4, #0
23aa: e7a9 b.n 2300 <__aeabi_fsub+0x160>
23ac: 000c movs r4, r1
23ae: e73d b.n 222c <__aeabi_fsub+0x8c>
23b0: 2b00 cmp r3, #0
23b2: d058 beq.n 2466 <__aeabi_fsub+0x2c6>
23b4: 43d2 mvns r2, r2
23b6: 2a00 cmp r2, #0
23b8: d0ee beq.n 2398 <__aeabi_fsub+0x1f8>
23ba: 28ff cmp r0, #255 ; 0xff
23bc: d1e1 bne.n 2382 <__aeabi_fsub+0x1e2>
23be: 0033 movs r3, r6
23c0: 24ff movs r4, #255 ; 0xff
23c2: 000d movs r5, r1
23c4: e732 b.n 222c <__aeabi_fsub+0x8c>
23c6: 29ff cmp r1, #255 ; 0xff
23c8: d010 beq.n 23ec <__aeabi_fsub+0x24c>
23ca: 0001 movs r1, r0
23cc: e778 b.n 22c0 <__aeabi_fsub+0x120>
23ce: 2b00 cmp r3, #0
23d0: d06e beq.n 24b0 <__aeabi_fsub+0x310>
23d2: 24ff movs r4, #255 ; 0xff
23d4: 2e00 cmp r6, #0
23d6: d100 bne.n 23da <__aeabi_fsub+0x23a>
23d8: e728 b.n 222c <__aeabi_fsub+0x8c>
23da: 2280 movs r2, #128 ; 0x80
23dc: 4651 mov r1, sl
23de: 03d2 lsls r2, r2, #15
23e0: 4211 tst r1, r2
23e2: d003 beq.n 23ec <__aeabi_fsub+0x24c>
23e4: 4661 mov r1, ip
23e6: 4211 tst r1, r2
23e8: d100 bne.n 23ec <__aeabi_fsub+0x24c>
23ea: 0033 movs r3, r6
23ec: 24ff movs r4, #255 ; 0xff
23ee: e71d b.n 222c <__aeabi_fsub+0x8c>
23f0: 24ff movs r4, #255 ; 0xff
23f2: 2300 movs r3, #0
23f4: e72c b.n 2250 <__aeabi_fsub+0xb0>
23f6: 2c00 cmp r4, #0
23f8: d1e9 bne.n 23ce <__aeabi_fsub+0x22e>
23fa: 2b00 cmp r3, #0
23fc: d063 beq.n 24c6 <__aeabi_fsub+0x326>
23fe: 2e00 cmp r6, #0
2400: d100 bne.n 2404 <__aeabi_fsub+0x264>
2402: e713 b.n 222c <__aeabi_fsub+0x8c>
2404: 199b adds r3, r3, r6
2406: 015a lsls r2, r3, #5
2408: d400 bmi.n 240c <__aeabi_fsub+0x26c>
240a: e73e b.n 228a <__aeabi_fsub+0xea>
240c: 4a31 ldr r2, [pc, #196] ; (24d4 <__aeabi_fsub+0x334>)
240e: 000c movs r4, r1
2410: 4013 ands r3, r2
2412: e70b b.n 222c <__aeabi_fsub+0x8c>
2414: 2c00 cmp r4, #0
2416: d11e bne.n 2456 <__aeabi_fsub+0x2b6>
2418: 2b00 cmp r3, #0
241a: d12f bne.n 247c <__aeabi_fsub+0x2dc>
241c: 2e00 cmp r6, #0
241e: d04f beq.n 24c0 <__aeabi_fsub+0x320>
2420: 0033 movs r3, r6
2422: 000d movs r5, r1
2424: e702 b.n 222c <__aeabi_fsub+0x8c>
2426: 2601 movs r6, #1
2428: e755 b.n 22d6 <__aeabi_fsub+0x136>
242a: 2c00 cmp r4, #0
242c: d11f bne.n 246e <__aeabi_fsub+0x2ce>
242e: 2b00 cmp r3, #0
2430: d043 beq.n 24ba <__aeabi_fsub+0x31a>
2432: 43c9 mvns r1, r1
2434: 2900 cmp r1, #0
2436: d00b beq.n 2450 <__aeabi_fsub+0x2b0>
2438: 28ff cmp r0, #255 ; 0xff
243a: d039 beq.n 24b0 <__aeabi_fsub+0x310>
243c: 291b cmp r1, #27
243e: dc44 bgt.n 24ca <__aeabi_fsub+0x32a>
2440: 001c movs r4, r3
2442: 2720 movs r7, #32
2444: 40cc lsrs r4, r1
2446: 1a79 subs r1, r7, r1
2448: 408b lsls r3, r1
244a: 1e59 subs r1, r3, #1
244c: 418b sbcs r3, r1
244e: 4323 orrs r3, r4
2450: 199b adds r3, r3, r6
2452: 0004 movs r4, r0
2454: e740 b.n 22d8 <__aeabi_fsub+0x138>
2456: 2b00 cmp r3, #0
2458: d11a bne.n 2490 <__aeabi_fsub+0x2f0>
245a: 2e00 cmp r6, #0
245c: d124 bne.n 24a8 <__aeabi_fsub+0x308>
245e: 2780 movs r7, #128 ; 0x80
2460: 2200 movs r2, #0
2462: 03ff lsls r7, r7, #15
2464: e71b b.n 229e <__aeabi_fsub+0xfe>
2466: 0033 movs r3, r6
2468: 0004 movs r4, r0
246a: 000d movs r5, r1
246c: e6de b.n 222c <__aeabi_fsub+0x8c>
246e: 28ff cmp r0, #255 ; 0xff
2470: d01e beq.n 24b0 <__aeabi_fsub+0x310>
2472: 2480 movs r4, #128 ; 0x80
2474: 04e4 lsls r4, r4, #19
2476: 4249 negs r1, r1
2478: 4323 orrs r3, r4
247a: e7df b.n 243c <__aeabi_fsub+0x29c>
247c: 2e00 cmp r6, #0
247e: d100 bne.n 2482 <__aeabi_fsub+0x2e2>
2480: e6d4 b.n 222c <__aeabi_fsub+0x8c>
2482: 1b9f subs r7, r3, r6
2484: 017a lsls r2, r7, #5
2486: d400 bmi.n 248a <__aeabi_fsub+0x2ea>
2488: e737 b.n 22fa <__aeabi_fsub+0x15a>
248a: 1af3 subs r3, r6, r3
248c: 000d movs r5, r1
248e: e6cd b.n 222c <__aeabi_fsub+0x8c>
2490: 24ff movs r4, #255 ; 0xff
2492: 2e00 cmp r6, #0
2494: d100 bne.n 2498 <__aeabi_fsub+0x2f8>
2496: e6c9 b.n 222c <__aeabi_fsub+0x8c>
2498: 2280 movs r2, #128 ; 0x80
249a: 4650 mov r0, sl
249c: 03d2 lsls r2, r2, #15
249e: 4210 tst r0, r2
24a0: d0a4 beq.n 23ec <__aeabi_fsub+0x24c>
24a2: 4660 mov r0, ip
24a4: 4210 tst r0, r2
24a6: d1a1 bne.n 23ec <__aeabi_fsub+0x24c>
24a8: 0033 movs r3, r6
24aa: 000d movs r5, r1
24ac: 24ff movs r4, #255 ; 0xff
24ae: e6bd b.n 222c <__aeabi_fsub+0x8c>
24b0: 0033 movs r3, r6
24b2: 24ff movs r4, #255 ; 0xff
24b4: e6ba b.n 222c <__aeabi_fsub+0x8c>
24b6: 2301 movs r3, #1
24b8: e76e b.n 2398 <__aeabi_fsub+0x1f8>
24ba: 0033 movs r3, r6
24bc: 0004 movs r4, r0
24be: e6b5 b.n 222c <__aeabi_fsub+0x8c>
24c0: 2700 movs r7, #0
24c2: 2200 movs r2, #0
24c4: e71c b.n 2300 <__aeabi_fsub+0x160>
24c6: 0033 movs r3, r6
24c8: e6b0 b.n 222c <__aeabi_fsub+0x8c>
24ca: 2301 movs r3, #1
24cc: e7c0 b.n 2450 <__aeabi_fsub+0x2b0>
24ce: 46c0 nop ; (mov r8, r8)
24d0: 7dffffff .word 0x7dffffff
24d4: fbffffff .word 0xfbffffff
000024d8 <__aeabi_f2iz>:
24d8: 0241 lsls r1, r0, #9
24da: 0043 lsls r3, r0, #1
24dc: 0fc2 lsrs r2, r0, #31
24de: 0a49 lsrs r1, r1, #9
24e0: 0e1b lsrs r3, r3, #24
24e2: 2000 movs r0, #0
24e4: 2b7e cmp r3, #126 ; 0x7e
24e6: dd0d ble.n 2504 <__aeabi_f2iz+0x2c>
24e8: 2b9d cmp r3, #157 ; 0x9d
24ea: dc0c bgt.n 2506 <__aeabi_f2iz+0x2e>
24ec: 2080 movs r0, #128 ; 0x80
24ee: 0400 lsls r0, r0, #16
24f0: 4301 orrs r1, r0
24f2: 2b95 cmp r3, #149 ; 0x95
24f4: dc0a bgt.n 250c <__aeabi_f2iz+0x34>
24f6: 2096 movs r0, #150 ; 0x96
24f8: 1ac3 subs r3, r0, r3
24fa: 40d9 lsrs r1, r3
24fc: 4248 negs r0, r1
24fe: 2a00 cmp r2, #0
2500: d100 bne.n 2504 <__aeabi_f2iz+0x2c>
2502: 0008 movs r0, r1
2504: 4770 bx lr
2506: 4b03 ldr r3, [pc, #12] ; (2514 <__aeabi_f2iz+0x3c>)
2508: 18d0 adds r0, r2, r3
250a: e7fb b.n 2504 <__aeabi_f2iz+0x2c>
250c: 3b96 subs r3, #150 ; 0x96
250e: 4099 lsls r1, r3
2510: e7f4 b.n 24fc <__aeabi_f2iz+0x24>
2512: 46c0 nop ; (mov r8, r8)
2514: 7fffffff .word 0x7fffffff
00002518 <__aeabi_i2f>:
2518: b570 push {r4, r5, r6, lr}
251a: 2800 cmp r0, #0
251c: d030 beq.n 2580 <__aeabi_i2f+0x68>
251e: 17c3 asrs r3, r0, #31
2520: 18c4 adds r4, r0, r3
2522: 405c eors r4, r3
2524: 0fc5 lsrs r5, r0, #31
2526: 0020 movs r0, r4
2528: f000 f88c bl 2644 <__clzsi2>
252c: 239e movs r3, #158 ; 0x9e
252e: 1a1b subs r3, r3, r0
2530: 2b96 cmp r3, #150 ; 0x96
2532: dc0d bgt.n 2550 <__aeabi_i2f+0x38>
2534: 2296 movs r2, #150 ; 0x96
2536: 1ad2 subs r2, r2, r3
2538: 4094 lsls r4, r2
253a: 002a movs r2, r5
253c: 0264 lsls r4, r4, #9
253e: 0a64 lsrs r4, r4, #9
2540: b2db uxtb r3, r3
2542: 0264 lsls r4, r4, #9
2544: 05db lsls r3, r3, #23
2546: 0a60 lsrs r0, r4, #9
2548: 07d2 lsls r2, r2, #31
254a: 4318 orrs r0, r3
254c: 4310 orrs r0, r2
254e: bd70 pop {r4, r5, r6, pc}
2550: 2b99 cmp r3, #153 ; 0x99
2552: dc19 bgt.n 2588 <__aeabi_i2f+0x70>
2554: 2299 movs r2, #153 ; 0x99
2556: 1ad2 subs r2, r2, r3
2558: 2a00 cmp r2, #0
255a: dd29 ble.n 25b0 <__aeabi_i2f+0x98>
255c: 4094 lsls r4, r2
255e: 0022 movs r2, r4
2560: 4c14 ldr r4, [pc, #80] ; (25b4 <__aeabi_i2f+0x9c>)
2562: 4014 ands r4, r2
2564: 0751 lsls r1, r2, #29
2566: d004 beq.n 2572 <__aeabi_i2f+0x5a>
2568: 210f movs r1, #15
256a: 400a ands r2, r1
256c: 2a04 cmp r2, #4
256e: d000 beq.n 2572 <__aeabi_i2f+0x5a>
2570: 3404 adds r4, #4
2572: 0162 lsls r2, r4, #5
2574: d413 bmi.n 259e <__aeabi_i2f+0x86>
2576: 01a4 lsls r4, r4, #6
2578: 0a64 lsrs r4, r4, #9
257a: b2db uxtb r3, r3
257c: 002a movs r2, r5
257e: e7e0 b.n 2542 <__aeabi_i2f+0x2a>
2580: 2200 movs r2, #0
2582: 2300 movs r3, #0
2584: 2400 movs r4, #0
2586: e7dc b.n 2542 <__aeabi_i2f+0x2a>
2588: 2205 movs r2, #5
258a: 0021 movs r1, r4
258c: 1a12 subs r2, r2, r0
258e: 40d1 lsrs r1, r2
2590: 22b9 movs r2, #185 ; 0xb9
2592: 1ad2 subs r2, r2, r3
2594: 4094 lsls r4, r2
2596: 1e62 subs r2, r4, #1
2598: 4194 sbcs r4, r2
259a: 430c orrs r4, r1
259c: e7da b.n 2554 <__aeabi_i2f+0x3c>
259e: 4b05 ldr r3, [pc, #20] ; (25b4 <__aeabi_i2f+0x9c>)
25a0: 002a movs r2, r5
25a2: 401c ands r4, r3
25a4: 239f movs r3, #159 ; 0x9f
25a6: 01a4 lsls r4, r4, #6
25a8: 1a1b subs r3, r3, r0
25aa: 0a64 lsrs r4, r4, #9
25ac: b2db uxtb r3, r3
25ae: e7c8 b.n 2542 <__aeabi_i2f+0x2a>
25b0: 0022 movs r2, r4
25b2: e7d5 b.n 2560 <__aeabi_i2f+0x48>
25b4: fbffffff .word 0xfbffffff
000025b8 <__aeabi_ui2f>:
25b8: b510 push {r4, lr}
25ba: 1e04 subs r4, r0, #0
25bc: d027 beq.n 260e <__aeabi_ui2f+0x56>
25be: f000 f841 bl 2644 <__clzsi2>
25c2: 239e movs r3, #158 ; 0x9e
25c4: 1a1b subs r3, r3, r0
25c6: 2b96 cmp r3, #150 ; 0x96
25c8: dc0a bgt.n 25e0 <__aeabi_ui2f+0x28>
25ca: 2296 movs r2, #150 ; 0x96
25cc: 1ad2 subs r2, r2, r3
25ce: 4094 lsls r4, r2
25d0: 0264 lsls r4, r4, #9
25d2: 0a64 lsrs r4, r4, #9
25d4: b2db uxtb r3, r3
25d6: 0264 lsls r4, r4, #9
25d8: 05db lsls r3, r3, #23
25da: 0a60 lsrs r0, r4, #9
25dc: 4318 orrs r0, r3
25de: bd10 pop {r4, pc}
25e0: 2b99 cmp r3, #153 ; 0x99
25e2: dc17 bgt.n 2614 <__aeabi_ui2f+0x5c>
25e4: 2299 movs r2, #153 ; 0x99
25e6: 1ad2 subs r2, r2, r3
25e8: 2a00 cmp r2, #0
25ea: dd27 ble.n 263c <__aeabi_ui2f+0x84>
25ec: 4094 lsls r4, r2
25ee: 0022 movs r2, r4
25f0: 4c13 ldr r4, [pc, #76] ; (2640 <__aeabi_ui2f+0x88>)
25f2: 4014 ands r4, r2
25f4: 0751 lsls r1, r2, #29
25f6: d004 beq.n 2602 <__aeabi_ui2f+0x4a>
25f8: 210f movs r1, #15
25fa: 400a ands r2, r1
25fc: 2a04 cmp r2, #4
25fe: d000 beq.n 2602 <__aeabi_ui2f+0x4a>
2600: 3404 adds r4, #4
2602: 0162 lsls r2, r4, #5
2604: d412 bmi.n 262c <__aeabi_ui2f+0x74>
2606: 01a4 lsls r4, r4, #6
2608: 0a64 lsrs r4, r4, #9
260a: b2db uxtb r3, r3
260c: e7e3 b.n 25d6 <__aeabi_ui2f+0x1e>
260e: 2300 movs r3, #0
2610: 2400 movs r4, #0
2612: e7e0 b.n 25d6 <__aeabi_ui2f+0x1e>
2614: 22b9 movs r2, #185 ; 0xb9
2616: 0021 movs r1, r4
2618: 1ad2 subs r2, r2, r3
261a: 4091 lsls r1, r2
261c: 000a movs r2, r1
261e: 1e51 subs r1, r2, #1
2620: 418a sbcs r2, r1
2622: 2105 movs r1, #5
2624: 1a09 subs r1, r1, r0
2626: 40cc lsrs r4, r1
2628: 4314 orrs r4, r2
262a: e7db b.n 25e4 <__aeabi_ui2f+0x2c>
262c: 4b04 ldr r3, [pc, #16] ; (2640 <__aeabi_ui2f+0x88>)
262e: 401c ands r4, r3
2630: 239f movs r3, #159 ; 0x9f
2632: 01a4 lsls r4, r4, #6
2634: 1a1b subs r3, r3, r0
2636: 0a64 lsrs r4, r4, #9
2638: b2db uxtb r3, r3
263a: e7cc b.n 25d6 <__aeabi_ui2f+0x1e>
263c: 0022 movs r2, r4
263e: e7d7 b.n 25f0 <__aeabi_ui2f+0x38>
2640: fbffffff .word 0xfbffffff
00002644 <__clzsi2>:
2644: 211c movs r1, #28
2646: 2301 movs r3, #1
2648: 041b lsls r3, r3, #16
264a: 4298 cmp r0, r3
264c: d301 bcc.n 2652 <__clzsi2+0xe>
264e: 0c00 lsrs r0, r0, #16
2650: 3910 subs r1, #16
2652: 0a1b lsrs r3, r3, #8
2654: 4298 cmp r0, r3
2656: d301 bcc.n 265c <__clzsi2+0x18>
2658: 0a00 lsrs r0, r0, #8
265a: 3908 subs r1, #8
265c: 091b lsrs r3, r3, #4
265e: 4298 cmp r0, r3
2660: d301 bcc.n 2666 <__clzsi2+0x22>
2662: 0900 lsrs r0, r0, #4
2664: 3904 subs r1, #4
2666: a202 add r2, pc, #8 ; (adr r2, 2670 <__clzsi2+0x2c>)
2668: 5c10 ldrb r0, [r2, r0]
266a: 1840 adds r0, r0, r1
266c: 4770 bx lr
266e: 46c0 nop ; (mov r8, r8)
2670: 02020304 .word 0x02020304
2674: 01010101 .word 0x01010101
...
00002680 <__libc_init_array>:
2680: b570 push {r4, r5, r6, lr}
2682: 2600 movs r6, #0
2684: 4d0c ldr r5, [pc, #48] ; (26b8 <__libc_init_array+0x38>)
2686: 4c0d ldr r4, [pc, #52] ; (26bc <__libc_init_array+0x3c>)
2688: 1b64 subs r4, r4, r5
268a: 10a4 asrs r4, r4, #2
268c: 42a6 cmp r6, r4
268e: d109 bne.n 26a4 <__libc_init_array+0x24>
2690: 2600 movs r6, #0
2692: f001 f955 bl 3940 <_init>
2696: 4d0a ldr r5, [pc, #40] ; (26c0 <__libc_init_array+0x40>)
2698: 4c0a ldr r4, [pc, #40] ; (26c4 <__libc_init_array+0x44>)
269a: 1b64 subs r4, r4, r5
269c: 10a4 asrs r4, r4, #2
269e: 42a6 cmp r6, r4
26a0: d105 bne.n 26ae <__libc_init_array+0x2e>
26a2: bd70 pop {r4, r5, r6, pc}
26a4: 00b3 lsls r3, r6, #2
26a6: 58eb ldr r3, [r5, r3]
26a8: 4798 blx r3
26aa: 3601 adds r6, #1
26ac: e7ee b.n 268c <__libc_init_array+0xc>
26ae: 00b3 lsls r3, r6, #2
26b0: 58eb ldr r3, [r5, r3]
26b2: 4798 blx r3
26b4: 3601 adds r6, #1
26b6: e7f2 b.n 269e <__libc_init_array+0x1e>
26b8: 0000394c .word 0x0000394c
26bc: 0000394c .word 0x0000394c
26c0: 0000394c .word 0x0000394c
26c4: 00003950 .word 0x00003950
000026c8 <memcpy>:
26c8: 2300 movs r3, #0
26ca: b510 push {r4, lr}
26cc: 429a cmp r2, r3
26ce: d100 bne.n 26d2 <memcpy+0xa>
26d0: bd10 pop {r4, pc}
26d2: 5ccc ldrb r4, [r1, r3]
26d4: 54c4 strb r4, [r0, r3]
26d6: 3301 adds r3, #1
26d8: e7f8 b.n 26cc <memcpy+0x4>
000026da <memset>:
26da: 0003 movs r3, r0
26dc: 1882 adds r2, r0, r2
26de: 4293 cmp r3, r2
26e0: d100 bne.n 26e4 <memset+0xa>
26e2: 4770 bx lr
26e4: 7019 strb r1, [r3, #0]
26e6: 3301 adds r3, #1
26e8: e7f9 b.n 26de <memset+0x4>
...
000026ec <iprintf>:
26ec: b40f push {r0, r1, r2, r3}
26ee: 4b0b ldr r3, [pc, #44] ; (271c <iprintf+0x30>)
26f0: b513 push {r0, r1, r4, lr}
26f2: 681c ldr r4, [r3, #0]
26f4: 2c00 cmp r4, #0
26f6: d005 beq.n 2704 <iprintf+0x18>
26f8: 69a3 ldr r3, [r4, #24]
26fa: 2b00 cmp r3, #0
26fc: d102 bne.n 2704 <iprintf+0x18>
26fe: 0020 movs r0, r4
2700: f000 f9bc bl 2a7c <__sinit>
2704: ab05 add r3, sp, #20
2706: 9a04 ldr r2, [sp, #16]
2708: 68a1 ldr r1, [r4, #8]
270a: 0020 movs r0, r4
270c: 9301 str r3, [sp, #4]
270e: f000 fb91 bl 2e34 <_vfiprintf_r>
2712: bc16 pop {r1, r2, r4}
2714: bc08 pop {r3}
2716: b004 add sp, #16
2718: 4718 bx r3
271a: 46c0 nop ; (mov r8, r8)
271c: 20000018 .word 0x20000018
00002720 <setbuf>:
2720: 424a negs r2, r1
2722: 414a adcs r2, r1
2724: 2380 movs r3, #128 ; 0x80
2726: b510 push {r4, lr}
2728: 0052 lsls r2, r2, #1
272a: 00db lsls r3, r3, #3
272c: f000 f802 bl 2734 <setvbuf>
2730: bd10 pop {r4, pc}
...
00002734 <setvbuf>:
2734: b5f0 push {r4, r5, r6, r7, lr}
2736: 001d movs r5, r3
2738: 4b4f ldr r3, [pc, #316] ; (2878 <setvbuf+0x144>)
273a: b085 sub sp, #20
273c: 681e ldr r6, [r3, #0]
273e: 0004 movs r4, r0
2740: 000f movs r7, r1
2742: 9200 str r2, [sp, #0]
2744: 2e00 cmp r6, #0
2746: d005 beq.n 2754 <setvbuf+0x20>
2748: 69b3 ldr r3, [r6, #24]
274a: 2b00 cmp r3, #0
274c: d102 bne.n 2754 <setvbuf+0x20>
274e: 0030 movs r0, r6
2750: f000 f994 bl 2a7c <__sinit>
2754: 4b49 ldr r3, [pc, #292] ; (287c <setvbuf+0x148>)
2756: 429c cmp r4, r3
2758: d150 bne.n 27fc <setvbuf+0xc8>
275a: 6874 ldr r4, [r6, #4]
275c: 9b00 ldr r3, [sp, #0]
275e: 2b02 cmp r3, #2
2760: d005 beq.n 276e <setvbuf+0x3a>
2762: 2b01 cmp r3, #1
2764: d900 bls.n 2768 <setvbuf+0x34>
2766: e084 b.n 2872 <setvbuf+0x13e>
2768: 2d00 cmp r5, #0
276a: da00 bge.n 276e <setvbuf+0x3a>
276c: e081 b.n 2872 <setvbuf+0x13e>
276e: 0021 movs r1, r4
2770: 0030 movs r0, r6
2772: f000 f915 bl 29a0 <_fflush_r>
2776: 6b61 ldr r1, [r4, #52] ; 0x34
2778: 2900 cmp r1, #0
277a: d008 beq.n 278e <setvbuf+0x5a>
277c: 0023 movs r3, r4
277e: 3344 adds r3, #68 ; 0x44
2780: 4299 cmp r1, r3
2782: d002 beq.n 278a <setvbuf+0x56>
2784: 0030 movs r0, r6
2786: f000 fa85 bl 2c94 <_free_r>
278a: 2300 movs r3, #0
278c: 6363 str r3, [r4, #52] ; 0x34
278e: 2300 movs r3, #0
2790: 61a3 str r3, [r4, #24]
2792: 6063 str r3, [r4, #4]
2794: 89a3 ldrh r3, [r4, #12]
2796: 061b lsls r3, r3, #24
2798: d503 bpl.n 27a2 <setvbuf+0x6e>
279a: 6921 ldr r1, [r4, #16]
279c: 0030 movs r0, r6
279e: f000 fa79 bl 2c94 <_free_r>
27a2: 89a3 ldrh r3, [r4, #12]
27a4: 4a36 ldr r2, [pc, #216] ; (2880 <setvbuf+0x14c>)
27a6: 4013 ands r3, r2
27a8: 81a3 strh r3, [r4, #12]
27aa: 9b00 ldr r3, [sp, #0]
27ac: 2b02 cmp r3, #2
27ae: d05a beq.n 2866 <setvbuf+0x132>
27b0: ab03 add r3, sp, #12
27b2: aa02 add r2, sp, #8
27b4: 0021 movs r1, r4
27b6: 0030 movs r0, r6
27b8: f000 f9f6 bl 2ba8 <__swhatbuf_r>
27bc: 89a3 ldrh r3, [r4, #12]
27be: 4318 orrs r0, r3
27c0: 81a0 strh r0, [r4, #12]
27c2: 2d00 cmp r5, #0
27c4: d124 bne.n 2810 <setvbuf+0xdc>
27c6: 9d02 ldr r5, [sp, #8]
27c8: 0028 movs r0, r5
27ca: f000 fa59 bl 2c80 <malloc>
27ce: 9501 str r5, [sp, #4]
27d0: 1e07 subs r7, r0, #0
27d2: d142 bne.n 285a <setvbuf+0x126>
27d4: 9b02 ldr r3, [sp, #8]
27d6: 9301 str r3, [sp, #4]
27d8: 42ab cmp r3, r5
27da: d139 bne.n 2850 <setvbuf+0x11c>
27dc: 2001 movs r0, #1
27de: 4240 negs r0, r0
27e0: 2302 movs r3, #2
27e2: 89a2 ldrh r2, [r4, #12]
27e4: 4313 orrs r3, r2
27e6: 81a3 strh r3, [r4, #12]
27e8: 2300 movs r3, #0
27ea: 60a3 str r3, [r4, #8]
27ec: 0023 movs r3, r4
27ee: 3347 adds r3, #71 ; 0x47
27f0: 6023 str r3, [r4, #0]
27f2: 6123 str r3, [r4, #16]
27f4: 2301 movs r3, #1
27f6: 6163 str r3, [r4, #20]
27f8: b005 add sp, #20
27fa: bdf0 pop {r4, r5, r6, r7, pc}
27fc: 4b21 ldr r3, [pc, #132] ; (2884 <setvbuf+0x150>)
27fe: 429c cmp r4, r3
2800: d101 bne.n 2806 <setvbuf+0xd2>
2802: 68b4 ldr r4, [r6, #8]
2804: e7aa b.n 275c <setvbuf+0x28>
2806: 4b20 ldr r3, [pc, #128] ; (2888 <setvbuf+0x154>)
2808: 429c cmp r4, r3
280a: d1a7 bne.n 275c <setvbuf+0x28>
280c: 68f4 ldr r4, [r6, #12]
280e: e7a5 b.n 275c <setvbuf+0x28>
2810: 2f00 cmp r7, #0
2812: d0d9 beq.n 27c8 <setvbuf+0x94>
2814: 69b3 ldr r3, [r6, #24]
2816: 2b00 cmp r3, #0
2818: d102 bne.n 2820 <setvbuf+0xec>
281a: 0030 movs r0, r6
281c: f000 f92e bl 2a7c <__sinit>
2820: 9b00 ldr r3, [sp, #0]
2822: 2b01 cmp r3, #1
2824: d103 bne.n 282e <setvbuf+0xfa>
2826: 89a3 ldrh r3, [r4, #12]
2828: 9a00 ldr r2, [sp, #0]
282a: 431a orrs r2, r3
282c: 81a2 strh r2, [r4, #12]
282e: 2008 movs r0, #8
2830: 89a3 ldrh r3, [r4, #12]
2832: 6027 str r7, [r4, #0]
2834: 6127 str r7, [r4, #16]
2836: 6165 str r5, [r4, #20]
2838: 4018 ands r0, r3
283a: d018 beq.n 286e <setvbuf+0x13a>
283c: 2001 movs r0, #1
283e: 4018 ands r0, r3
2840: 2300 movs r3, #0
2842: 4298 cmp r0, r3
2844: d011 beq.n 286a <setvbuf+0x136>
2846: 426d negs r5, r5
2848: 60a3 str r3, [r4, #8]
284a: 61a5 str r5, [r4, #24]
284c: 0018 movs r0, r3
284e: e7d3 b.n 27f8 <setvbuf+0xc4>
2850: 9801 ldr r0, [sp, #4]
2852: f000 fa15 bl 2c80 <malloc>
2856: 1e07 subs r7, r0, #0
2858: d0c0 beq.n 27dc <setvbuf+0xa8>
285a: 2380 movs r3, #128 ; 0x80
285c: 89a2 ldrh r2, [r4, #12]
285e: 9d01 ldr r5, [sp, #4]
2860: 4313 orrs r3, r2
2862: 81a3 strh r3, [r4, #12]
2864: e7d6 b.n 2814 <setvbuf+0xe0>
2866: 2000 movs r0, #0
2868: e7ba b.n 27e0 <setvbuf+0xac>
286a: 60a5 str r5, [r4, #8]
286c: e7c4 b.n 27f8 <setvbuf+0xc4>
286e: 60a0 str r0, [r4, #8]
2870: e7c2 b.n 27f8 <setvbuf+0xc4>
2872: 2001 movs r0, #1
2874: 4240 negs r0, r0
2876: e7bf b.n 27f8 <setvbuf+0xc4>
2878: 20000018 .word 0x20000018
287c: 000038cc .word 0x000038cc
2880: fffff35c .word 0xfffff35c
2884: 000038ec .word 0x000038ec
2888: 000038ac .word 0x000038ac
0000288c <__sflush_r>:
288c: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
288e: 898a ldrh r2, [r1, #12]
2890: 0005 movs r5, r0
2892: 000c movs r4, r1
2894: 0713 lsls r3, r2, #28
2896: d460 bmi.n 295a <__sflush_r+0xce>
2898: 684b ldr r3, [r1, #4]
289a: 2b00 cmp r3, #0
289c: dc04 bgt.n 28a8 <__sflush_r+0x1c>
289e: 6c0b ldr r3, [r1, #64] ; 0x40
28a0: 2b00 cmp r3, #0
28a2: dc01 bgt.n 28a8 <__sflush_r+0x1c>
28a4: 2000 movs r0, #0
28a6: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc}
28a8: 6ae7 ldr r7, [r4, #44] ; 0x2c
28aa: 2f00 cmp r7, #0
28ac: d0fa beq.n 28a4 <__sflush_r+0x18>
28ae: 2300 movs r3, #0
28b0: 682e ldr r6, [r5, #0]
28b2: 602b str r3, [r5, #0]
28b4: 2380 movs r3, #128 ; 0x80
28b6: 015b lsls r3, r3, #5
28b8: 401a ands r2, r3
28ba: d034 beq.n 2926 <__sflush_r+0x9a>
28bc: 6d60 ldr r0, [r4, #84] ; 0x54
28be: 89a3 ldrh r3, [r4, #12]
28c0: 075b lsls r3, r3, #29
28c2: d506 bpl.n 28d2 <__sflush_r+0x46>
28c4: 6863 ldr r3, [r4, #4]
28c6: 1ac0 subs r0, r0, r3
28c8: 6b63 ldr r3, [r4, #52] ; 0x34
28ca: 2b00 cmp r3, #0
28cc: d001 beq.n 28d2 <__sflush_r+0x46>
28ce: 6c23 ldr r3, [r4, #64] ; 0x40
28d0: 1ac0 subs r0, r0, r3
28d2: 0002 movs r2, r0
28d4: 6a21 ldr r1, [r4, #32]
28d6: 2300 movs r3, #0
28d8: 0028 movs r0, r5
28da: 6ae7 ldr r7, [r4, #44] ; 0x2c
28dc: 47b8 blx r7
28de: 89a1 ldrh r1, [r4, #12]
28e0: 1c43 adds r3, r0, #1
28e2: d106 bne.n 28f2 <__sflush_r+0x66>
28e4: 682b ldr r3, [r5, #0]
28e6: 2b1d cmp r3, #29
28e8: d831 bhi.n 294e <__sflush_r+0xc2>
28ea: 4a2c ldr r2, [pc, #176] ; (299c <__sflush_r+0x110>)
28ec: 40da lsrs r2, r3
28ee: 07d3 lsls r3, r2, #31
28f0: d52d bpl.n 294e <__sflush_r+0xc2>
28f2: 2300 movs r3, #0
28f4: 6063 str r3, [r4, #4]
28f6: 6923 ldr r3, [r4, #16]
28f8: 6023 str r3, [r4, #0]
28fa: 04cb lsls r3, r1, #19
28fc: d505 bpl.n 290a <__sflush_r+0x7e>
28fe: 1c43 adds r3, r0, #1
2900: d102 bne.n 2908 <__sflush_r+0x7c>
2902: 682b ldr r3, [r5, #0]
2904: 2b00 cmp r3, #0
2906: d100 bne.n 290a <__sflush_r+0x7e>
2908: 6560 str r0, [r4, #84] ; 0x54
290a: 6b61 ldr r1, [r4, #52] ; 0x34
290c: 602e str r6, [r5, #0]
290e: 2900 cmp r1, #0
2910: d0c8 beq.n 28a4 <__sflush_r+0x18>
2912: 0023 movs r3, r4
2914: 3344 adds r3, #68 ; 0x44
2916: 4299 cmp r1, r3
2918: d002 beq.n 2920 <__sflush_r+0x94>
291a: 0028 movs r0, r5
291c: f000 f9ba bl 2c94 <_free_r>
2920: 2000 movs r0, #0
2922: 6360 str r0, [r4, #52] ; 0x34
2924: e7bf b.n 28a6 <__sflush_r+0x1a>
2926: 2301 movs r3, #1
2928: 6a21 ldr r1, [r4, #32]
292a: 0028 movs r0, r5
292c: 47b8 blx r7
292e: 1c43 adds r3, r0, #1
2930: d1c5 bne.n 28be <__sflush_r+0x32>
2932: 682b ldr r3, [r5, #0]
2934: 2b00 cmp r3, #0
2936: d0c2 beq.n 28be <__sflush_r+0x32>
2938: 2b1d cmp r3, #29
293a: d001 beq.n 2940 <__sflush_r+0xb4>
293c: 2b16 cmp r3, #22
293e: d101 bne.n 2944 <__sflush_r+0xb8>
2940: 602e str r6, [r5, #0]
2942: e7af b.n 28a4 <__sflush_r+0x18>
2944: 2340 movs r3, #64 ; 0x40
2946: 89a2 ldrh r2, [r4, #12]
2948: 4313 orrs r3, r2
294a: 81a3 strh r3, [r4, #12]
294c: e7ab b.n 28a6 <__sflush_r+0x1a>
294e: 2340 movs r3, #64 ; 0x40
2950: 430b orrs r3, r1
2952: 2001 movs r0, #1
2954: 81a3 strh r3, [r4, #12]
2956: 4240 negs r0, r0
2958: e7a5 b.n 28a6 <__sflush_r+0x1a>
295a: 690f ldr r7, [r1, #16]
295c: 2f00 cmp r7, #0
295e: d0a1 beq.n 28a4 <__sflush_r+0x18>
2960: 680b ldr r3, [r1, #0]
2962: 600f str r7, [r1, #0]
2964: 1bdb subs r3, r3, r7
2966: 9301 str r3, [sp, #4]
2968: 2300 movs r3, #0
296a: 0792 lsls r2, r2, #30
296c: d100 bne.n 2970 <__sflush_r+0xe4>
296e: 694b ldr r3, [r1, #20]
2970: 60a3 str r3, [r4, #8]
2972: 9b01 ldr r3, [sp, #4]
2974: 2b00 cmp r3, #0
2976: dc00 bgt.n 297a <__sflush_r+0xee>
2978: e794 b.n 28a4 <__sflush_r+0x18>
297a: 9b01 ldr r3, [sp, #4]
297c: 003a movs r2, r7
297e: 6a21 ldr r1, [r4, #32]
2980: 0028 movs r0, r5
2982: 6aa6 ldr r6, [r4, #40] ; 0x28
2984: 47b0 blx r6
2986: 2800 cmp r0, #0
2988: dc03 bgt.n 2992 <__sflush_r+0x106>
298a: 2340 movs r3, #64 ; 0x40
298c: 89a2 ldrh r2, [r4, #12]
298e: 4313 orrs r3, r2
2990: e7df b.n 2952 <__sflush_r+0xc6>
2992: 9b01 ldr r3, [sp, #4]
2994: 183f adds r7, r7, r0
2996: 1a1b subs r3, r3, r0
2998: 9301 str r3, [sp, #4]
299a: e7ea b.n 2972 <__sflush_r+0xe6>
299c: 20400001 .word 0x20400001
000029a0 <_fflush_r>:
29a0: 690b ldr r3, [r1, #16]
29a2: b570 push {r4, r5, r6, lr}
29a4: 0005 movs r5, r0
29a6: 000c movs r4, r1
29a8: 2b00 cmp r3, #0
29aa: d101 bne.n 29b0 <_fflush_r+0x10>
29ac: 2000 movs r0, #0
29ae: bd70 pop {r4, r5, r6, pc}
29b0: 2800 cmp r0, #0
29b2: d004 beq.n 29be <_fflush_r+0x1e>
29b4: 6983 ldr r3, [r0, #24]
29b6: 2b00 cmp r3, #0
29b8: d101 bne.n 29be <_fflush_r+0x1e>
29ba: f000 f85f bl 2a7c <__sinit>
29be: 4b0b ldr r3, [pc, #44] ; (29ec <_fflush_r+0x4c>)
29c0: 429c cmp r4, r3
29c2: d109 bne.n 29d8 <_fflush_r+0x38>
29c4: 686c ldr r4, [r5, #4]
29c6: 220c movs r2, #12
29c8: 5ea3 ldrsh r3, [r4, r2]
29ca: 2b00 cmp r3, #0
29cc: d0ee beq.n 29ac <_fflush_r+0xc>
29ce: 0021 movs r1, r4
29d0: 0028 movs r0, r5
29d2: f7ff ff5b bl 288c <__sflush_r>
29d6: e7ea b.n 29ae <_fflush_r+0xe>
29d8: 4b05 ldr r3, [pc, #20] ; (29f0 <_fflush_r+0x50>)
29da: 429c cmp r4, r3
29dc: d101 bne.n 29e2 <_fflush_r+0x42>
29de: 68ac ldr r4, [r5, #8]
29e0: e7f1 b.n 29c6 <_fflush_r+0x26>
29e2: 4b04 ldr r3, [pc, #16] ; (29f4 <_fflush_r+0x54>)
29e4: 429c cmp r4, r3
29e6: d1ee bne.n 29c6 <_fflush_r+0x26>
29e8: 68ec ldr r4, [r5, #12]
29ea: e7ec b.n 29c6 <_fflush_r+0x26>
29ec: 000038cc .word 0x000038cc
29f0: 000038ec .word 0x000038ec
29f4: 000038ac .word 0x000038ac
000029f8 <_cleanup_r>:
29f8: b510 push {r4, lr}
29fa: 4902 ldr r1, [pc, #8] ; (2a04 <_cleanup_r+0xc>)
29fc: f000 f8b2 bl 2b64 <_fwalk_reent>
2a00: bd10 pop {r4, pc}
2a02: 46c0 nop ; (mov r8, r8)
2a04: 000029a1 .word 0x000029a1
00002a08 <std.isra.0>:
2a08: 2300 movs r3, #0
2a0a: b510 push {r4, lr}
2a0c: 0004 movs r4, r0
2a0e: 6003 str r3, [r0, #0]
2a10: 6043 str r3, [r0, #4]
2a12: 6083 str r3, [r0, #8]
2a14: 8181 strh r1, [r0, #12]
2a16: 6643 str r3, [r0, #100] ; 0x64
2a18: 81c2 strh r2, [r0, #14]
2a1a: 6103 str r3, [r0, #16]
2a1c: 6143 str r3, [r0, #20]
2a1e: 6183 str r3, [r0, #24]
2a20: 0019 movs r1, r3
2a22: 2208 movs r2, #8
2a24: 305c adds r0, #92 ; 0x5c
2a26: f7ff fe58 bl 26da <memset>
2a2a: 4b05 ldr r3, [pc, #20] ; (2a40 <std.isra.0+0x38>)
2a2c: 6224 str r4, [r4, #32]
2a2e: 6263 str r3, [r4, #36] ; 0x24
2a30: 4b04 ldr r3, [pc, #16] ; (2a44 <std.isra.0+0x3c>)
2a32: 62a3 str r3, [r4, #40] ; 0x28
2a34: 4b04 ldr r3, [pc, #16] ; (2a48 <std.isra.0+0x40>)
2a36: 62e3 str r3, [r4, #44] ; 0x2c
2a38: 4b04 ldr r3, [pc, #16] ; (2a4c <std.isra.0+0x44>)
2a3a: 6323 str r3, [r4, #48] ; 0x30
2a3c: bd10 pop {r4, pc}
2a3e: 46c0 nop ; (mov r8, r8)
2a40: 000033a1 .word 0x000033a1
2a44: 000033c9 .word 0x000033c9
2a48: 00003401 .word 0x00003401
2a4c: 0000342d .word 0x0000342d
00002a50 <__sfmoreglue>:
2a50: b570 push {r4, r5, r6, lr}
2a52: 2568 movs r5, #104 ; 0x68
2a54: 1e4a subs r2, r1, #1
2a56: 4355 muls r5, r2
2a58: 000e movs r6, r1
2a5a: 0029 movs r1, r5
2a5c: 3174 adds r1, #116 ; 0x74
2a5e: f000 f963 bl 2d28 <_malloc_r>
2a62: 1e04 subs r4, r0, #0
2a64: d008 beq.n 2a78 <__sfmoreglue+0x28>
2a66: 2100 movs r1, #0
2a68: 002a movs r2, r5
2a6a: 6001 str r1, [r0, #0]
2a6c: 6046 str r6, [r0, #4]
2a6e: 300c adds r0, #12
2a70: 60a0 str r0, [r4, #8]
2a72: 3268 adds r2, #104 ; 0x68
2a74: f7ff fe31 bl 26da <memset>
2a78: 0020 movs r0, r4
2a7a: bd70 pop {r4, r5, r6, pc}
00002a7c <__sinit>:
2a7c: 6983 ldr r3, [r0, #24]
2a7e: b513 push {r0, r1, r4, lr}
2a80: 0004 movs r4, r0
2a82: 2b00 cmp r3, #0
2a84: d128 bne.n 2ad8 <__sinit+0x5c>
2a86: 6483 str r3, [r0, #72] ; 0x48
2a88: 64c3 str r3, [r0, #76] ; 0x4c
2a8a: 6503 str r3, [r0, #80] ; 0x50
2a8c: 4b13 ldr r3, [pc, #76] ; (2adc <__sinit+0x60>)
2a8e: 4a14 ldr r2, [pc, #80] ; (2ae0 <__sinit+0x64>)
2a90: 681b ldr r3, [r3, #0]
2a92: 6282 str r2, [r0, #40] ; 0x28
2a94: 9301 str r3, [sp, #4]
2a96: 4298 cmp r0, r3
2a98: d101 bne.n 2a9e <__sinit+0x22>
2a9a: 2301 movs r3, #1
2a9c: 6183 str r3, [r0, #24]
2a9e: 0020 movs r0, r4
2aa0: f000 f820 bl 2ae4 <__sfp>
2aa4: 6060 str r0, [r4, #4]
2aa6: 0020 movs r0, r4
2aa8: f000 f81c bl 2ae4 <__sfp>
2aac: 60a0 str r0, [r4, #8]
2aae: 0020 movs r0, r4
2ab0: f000 f818 bl 2ae4 <__sfp>
2ab4: 2200 movs r2, #0
2ab6: 60e0 str r0, [r4, #12]
2ab8: 2104 movs r1, #4
2aba: 6860 ldr r0, [r4, #4]
2abc: f7ff ffa4 bl 2a08 <std.isra.0>
2ac0: 2201 movs r2, #1
2ac2: 2109 movs r1, #9
2ac4: 68a0 ldr r0, [r4, #8]
2ac6: f7ff ff9f bl 2a08 <std.isra.0>
2aca: 2202 movs r2, #2
2acc: 2112 movs r1, #18
2ace: 68e0 ldr r0, [r4, #12]
2ad0: f7ff ff9a bl 2a08 <std.isra.0>
2ad4: 2301 movs r3, #1
2ad6: 61a3 str r3, [r4, #24]
2ad8: bd13 pop {r0, r1, r4, pc}
2ada: 46c0 nop ; (mov r8, r8)
2adc: 000038a8 .word 0x000038a8
2ae0: 000029f9 .word 0x000029f9
00002ae4 <__sfp>:
2ae4: b5f8 push {r3, r4, r5, r6, r7, lr}
2ae6: 4b1e ldr r3, [pc, #120] ; (2b60 <__sfp+0x7c>)
2ae8: 0007 movs r7, r0
2aea: 681e ldr r6, [r3, #0]
2aec: 69b3 ldr r3, [r6, #24]
2aee: 2b00 cmp r3, #0
2af0: d102 bne.n 2af8 <__sfp+0x14>
2af2: 0030 movs r0, r6
2af4: f7ff ffc2 bl 2a7c <__sinit>
2af8: 3648 adds r6, #72 ; 0x48
2afa: 68b4 ldr r4, [r6, #8]
2afc: 6873 ldr r3, [r6, #4]
2afe: 3b01 subs r3, #1
2b00: d504 bpl.n 2b0c <__sfp+0x28>
2b02: 6833 ldr r3, [r6, #0]
2b04: 2b00 cmp r3, #0
2b06: d007 beq.n 2b18 <__sfp+0x34>
2b08: 6836 ldr r6, [r6, #0]
2b0a: e7f6 b.n 2afa <__sfp+0x16>
2b0c: 220c movs r2, #12
2b0e: 5ea5 ldrsh r5, [r4, r2]
2b10: 2d00 cmp r5, #0
2b12: d00d beq.n 2b30 <__sfp+0x4c>
2b14: 3468 adds r4, #104 ; 0x68
2b16: e7f2 b.n 2afe <__sfp+0x1a>
2b18: 2104 movs r1, #4
2b1a: 0038 movs r0, r7
2b1c: f7ff ff98 bl 2a50 <__sfmoreglue>
2b20: 6030 str r0, [r6, #0]
2b22: 2800 cmp r0, #0
2b24: d1f0 bne.n 2b08 <__sfp+0x24>
2b26: 230c movs r3, #12
2b28: 0004 movs r4, r0
2b2a: 603b str r3, [r7, #0]
2b2c: 0020 movs r0, r4
2b2e: bdf8 pop {r3, r4, r5, r6, r7, pc}
2b30: 2301 movs r3, #1
2b32: 0020 movs r0, r4
2b34: 425b negs r3, r3
2b36: 81e3 strh r3, [r4, #14]
2b38: 3302 adds r3, #2
2b3a: 81a3 strh r3, [r4, #12]
2b3c: 6665 str r5, [r4, #100] ; 0x64
2b3e: 6025 str r5, [r4, #0]
2b40: 60a5 str r5, [r4, #8]
2b42: 6065 str r5, [r4, #4]
2b44: 6125 str r5, [r4, #16]
2b46: 6165 str r5, [r4, #20]
2b48: 61a5 str r5, [r4, #24]
2b4a: 2208 movs r2, #8
2b4c: 0029 movs r1, r5
2b4e: 305c adds r0, #92 ; 0x5c
2b50: f7ff fdc3 bl 26da <memset>
2b54: 6365 str r5, [r4, #52] ; 0x34
2b56: 63a5 str r5, [r4, #56] ; 0x38
2b58: 64a5 str r5, [r4, #72] ; 0x48
2b5a: 64e5 str r5, [r4, #76] ; 0x4c
2b5c: e7e6 b.n 2b2c <__sfp+0x48>
2b5e: 46c0 nop ; (mov r8, r8)
2b60: 000038a8 .word 0x000038a8
00002b64 <_fwalk_reent>:
2b64: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
2b66: 0004 movs r4, r0
2b68: 0007 movs r7, r0
2b6a: 2600 movs r6, #0
2b6c: 9101 str r1, [sp, #4]
2b6e: 3448 adds r4, #72 ; 0x48
2b70: 2c00 cmp r4, #0
2b72: d101 bne.n 2b78 <_fwalk_reent+0x14>
2b74: 0030 movs r0, r6
2b76: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc}
2b78: 6863 ldr r3, [r4, #4]
2b7a: 68a5 ldr r5, [r4, #8]
2b7c: 9300 str r3, [sp, #0]
2b7e: 9b00 ldr r3, [sp, #0]
2b80: 3b01 subs r3, #1
2b82: 9300 str r3, [sp, #0]
2b84: d501 bpl.n 2b8a <_fwalk_reent+0x26>
2b86: 6824 ldr r4, [r4, #0]
2b88: e7f2 b.n 2b70 <_fwalk_reent+0xc>
2b8a: 89ab ldrh r3, [r5, #12]
2b8c: 2b01 cmp r3, #1
2b8e: d908 bls.n 2ba2 <_fwalk_reent+0x3e>
2b90: 220e movs r2, #14
2b92: 5eab ldrsh r3, [r5, r2]
2b94: 3301 adds r3, #1
2b96: d004 beq.n 2ba2 <_fwalk_reent+0x3e>
2b98: 0029 movs r1, r5
2b9a: 0038 movs r0, r7
2b9c: 9b01 ldr r3, [sp, #4]
2b9e: 4798 blx r3
2ba0: 4306 orrs r6, r0
2ba2: 3568 adds r5, #104 ; 0x68
2ba4: e7eb b.n 2b7e <_fwalk_reent+0x1a>
...
00002ba8 <__swhatbuf_r>:
2ba8: b570 push {r4, r5, r6, lr}
2baa: 000e movs r6, r1
2bac: 001d movs r5, r3
2bae: 230e movs r3, #14
2bb0: 5ec9 ldrsh r1, [r1, r3]
2bb2: b090 sub sp, #64 ; 0x40
2bb4: 0014 movs r4, r2
2bb6: 2900 cmp r1, #0
2bb8: da07 bge.n 2bca <__swhatbuf_r+0x22>
2bba: 2300 movs r3, #0
2bbc: 602b str r3, [r5, #0]
2bbe: 89b3 ldrh r3, [r6, #12]
2bc0: 061b lsls r3, r3, #24
2bc2: d411 bmi.n 2be8 <__swhatbuf_r+0x40>
2bc4: 2380 movs r3, #128 ; 0x80
2bc6: 00db lsls r3, r3, #3
2bc8: e00f b.n 2bea <__swhatbuf_r+0x42>
2bca: aa01 add r2, sp, #4
2bcc: f000 fd26 bl 361c <_fstat_r>
2bd0: 2800 cmp r0, #0
2bd2: dbf2 blt.n 2bba <__swhatbuf_r+0x12>
2bd4: 22f0 movs r2, #240 ; 0xf0
2bd6: 9b02 ldr r3, [sp, #8]
2bd8: 0212 lsls r2, r2, #8
2bda: 4013 ands r3, r2
2bdc: 4a05 ldr r2, [pc, #20] ; (2bf4 <__swhatbuf_r+0x4c>)
2bde: 189b adds r3, r3, r2
2be0: 425a negs r2, r3
2be2: 4153 adcs r3, r2
2be4: 602b str r3, [r5, #0]
2be6: e7ed b.n 2bc4 <__swhatbuf_r+0x1c>
2be8: 2340 movs r3, #64 ; 0x40
2bea: 2000 movs r0, #0
2bec: 6023 str r3, [r4, #0]
2bee: b010 add sp, #64 ; 0x40
2bf0: bd70 pop {r4, r5, r6, pc}
2bf2: 46c0 nop ; (mov r8, r8)
2bf4: ffffe000 .word 0xffffe000
00002bf8 <__smakebuf_r>:
2bf8: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
2bfa: 2602 movs r6, #2
2bfc: 898b ldrh r3, [r1, #12]
2bfe: 0005 movs r5, r0
2c00: 000c movs r4, r1
2c02: 4233 tst r3, r6
2c04: d006 beq.n 2c14 <__smakebuf_r+0x1c>
2c06: 0023 movs r3, r4
2c08: 3347 adds r3, #71 ; 0x47
2c0a: 6023 str r3, [r4, #0]
2c0c: 6123 str r3, [r4, #16]
2c0e: 2301 movs r3, #1
2c10: 6163 str r3, [r4, #20]
2c12: bdf7 pop {r0, r1, r2, r4, r5, r6, r7, pc}
2c14: ab01 add r3, sp, #4
2c16: 466a mov r2, sp
2c18: f7ff ffc6 bl 2ba8 <__swhatbuf_r>
2c1c: 9900 ldr r1, [sp, #0]
2c1e: 0007 movs r7, r0
2c20: 0028 movs r0, r5
2c22: f000 f881 bl 2d28 <_malloc_r>
2c26: 2800 cmp r0, #0
2c28: d108 bne.n 2c3c <__smakebuf_r+0x44>
2c2a: 220c movs r2, #12
2c2c: 5ea3 ldrsh r3, [r4, r2]
2c2e: 059a lsls r2, r3, #22
2c30: d4ef bmi.n 2c12 <__smakebuf_r+0x1a>
2c32: 2203 movs r2, #3
2c34: 4393 bics r3, r2
2c36: 431e orrs r6, r3
2c38: 81a6 strh r6, [r4, #12]
2c3a: e7e4 b.n 2c06 <__smakebuf_r+0xe>
2c3c: 4b0f ldr r3, [pc, #60] ; (2c7c <__smakebuf_r+0x84>)
2c3e: 62ab str r3, [r5, #40] ; 0x28
2c40: 2380 movs r3, #128 ; 0x80
2c42: 89a2 ldrh r2, [r4, #12]
2c44: 6020 str r0, [r4, #0]
2c46: 4313 orrs r3, r2
2c48: 81a3 strh r3, [r4, #12]
2c4a: 9b00 ldr r3, [sp, #0]
2c4c: 6120 str r0, [r4, #16]
2c4e: 6163 str r3, [r4, #20]
2c50: 9b01 ldr r3, [sp, #4]
2c52: 2b00 cmp r3, #0
2c54: d00d beq.n 2c72 <__smakebuf_r+0x7a>
2c56: 230e movs r3, #14
2c58: 5ee1 ldrsh r1, [r4, r3]
2c5a: 0028 movs r0, r5
2c5c: f000 fcf0 bl 3640 <_isatty_r>
2c60: 2800 cmp r0, #0
2c62: d006 beq.n 2c72 <__smakebuf_r+0x7a>
2c64: 2203 movs r2, #3
2c66: 89a3 ldrh r3, [r4, #12]
2c68: 4393 bics r3, r2
2c6a: 001a movs r2, r3
2c6c: 2301 movs r3, #1
2c6e: 4313 orrs r3, r2
2c70: 81a3 strh r3, [r4, #12]
2c72: 89a0 ldrh r0, [r4, #12]
2c74: 4338 orrs r0, r7
2c76: 81a0 strh r0, [r4, #12]
2c78: e7cb b.n 2c12 <__smakebuf_r+0x1a>
2c7a: 46c0 nop ; (mov r8, r8)
2c7c: 000029f9 .word 0x000029f9
00002c80 <malloc>:
2c80: b510 push {r4, lr}
2c82: 4b03 ldr r3, [pc, #12] ; (2c90 <malloc+0x10>)
2c84: 0001 movs r1, r0
2c86: 6818 ldr r0, [r3, #0]
2c88: f000 f84e bl 2d28 <_malloc_r>
2c8c: bd10 pop {r4, pc}
2c8e: 46c0 nop ; (mov r8, r8)
2c90: 20000018 .word 0x20000018
00002c94 <_free_r>:
2c94: b570 push {r4, r5, r6, lr}
2c96: 0005 movs r5, r0
2c98: 2900 cmp r1, #0
2c9a: d010 beq.n 2cbe <_free_r+0x2a>
2c9c: 1f0c subs r4, r1, #4
2c9e: 6823 ldr r3, [r4, #0]
2ca0: 2b00 cmp r3, #0
2ca2: da00 bge.n 2ca6 <_free_r+0x12>
2ca4: 18e4 adds r4, r4, r3
2ca6: 0028 movs r0, r5
2ca8: f000 fcfb bl 36a2 <__malloc_lock>
2cac: 4a1d ldr r2, [pc, #116] ; (2d24 <_free_r+0x90>)
2cae: 6813 ldr r3, [r2, #0]
2cb0: 2b00 cmp r3, #0
2cb2: d105 bne.n 2cc0 <_free_r+0x2c>
2cb4: 6063 str r3, [r4, #4]
2cb6: 6014 str r4, [r2, #0]
2cb8: 0028 movs r0, r5
2cba: f000 fcf3 bl 36a4 <__malloc_unlock>
2cbe: bd70 pop {r4, r5, r6, pc}
2cc0: 42a3 cmp r3, r4
2cc2: d909 bls.n 2cd8 <_free_r+0x44>
2cc4: 6821 ldr r1, [r4, #0]
2cc6: 1860 adds r0, r4, r1
2cc8: 4283 cmp r3, r0
2cca: d1f3 bne.n 2cb4 <_free_r+0x20>
2ccc: 6818 ldr r0, [r3, #0]
2cce: 685b ldr r3, [r3, #4]
2cd0: 1841 adds r1, r0, r1
2cd2: 6021 str r1, [r4, #0]
2cd4: e7ee b.n 2cb4 <_free_r+0x20>
2cd6: 0013 movs r3, r2
2cd8: 685a ldr r2, [r3, #4]
2cda: 2a00 cmp r2, #0
2cdc: d001 beq.n 2ce2 <_free_r+0x4e>
2cde: 42a2 cmp r2, r4
2ce0: d9f9 bls.n 2cd6 <_free_r+0x42>
2ce2: 6819 ldr r1, [r3, #0]
2ce4: 1858 adds r0, r3, r1
2ce6: 42a0 cmp r0, r4
2ce8: d10b bne.n 2d02 <_free_r+0x6e>
2cea: 6820 ldr r0, [r4, #0]
2cec: 1809 adds r1, r1, r0
2cee: 1858 adds r0, r3, r1
2cf0: 6019 str r1, [r3, #0]
2cf2: 4282 cmp r2, r0
2cf4: d1e0 bne.n 2cb8 <_free_r+0x24>
2cf6: 6810 ldr r0, [r2, #0]
2cf8: 6852 ldr r2, [r2, #4]
2cfa: 1841 adds r1, r0, r1
2cfc: 6019 str r1, [r3, #0]
2cfe: 605a str r2, [r3, #4]
2d00: e7da b.n 2cb8 <_free_r+0x24>
2d02: 42a0 cmp r0, r4
2d04: d902 bls.n 2d0c <_free_r+0x78>
2d06: 230c movs r3, #12
2d08: 602b str r3, [r5, #0]
2d0a: e7d5 b.n 2cb8 <_free_r+0x24>
2d0c: 6821 ldr r1, [r4, #0]
2d0e: 1860 adds r0, r4, r1
2d10: 4282 cmp r2, r0
2d12: d103 bne.n 2d1c <_free_r+0x88>
2d14: 6810 ldr r0, [r2, #0]
2d16: 6852 ldr r2, [r2, #4]
2d18: 1841 adds r1, r0, r1
2d1a: 6021 str r1, [r4, #0]
2d1c: 6062 str r2, [r4, #4]
2d1e: 605c str r4, [r3, #4]
2d20: e7ca b.n 2cb8 <_free_r+0x24>
2d22: 46c0 nop ; (mov r8, r8)
2d24: 200001d0 .word 0x200001d0
00002d28 <_malloc_r>:
2d28: 2303 movs r3, #3
2d2a: b570 push {r4, r5, r6, lr}
2d2c: 1ccd adds r5, r1, #3
2d2e: 439d bics r5, r3
2d30: 3508 adds r5, #8
2d32: 0006 movs r6, r0
2d34: 2d0c cmp r5, #12
2d36: d21e bcs.n 2d76 <_malloc_r+0x4e>
2d38: 250c movs r5, #12
2d3a: 42a9 cmp r1, r5
2d3c: d81d bhi.n 2d7a <_malloc_r+0x52>
2d3e: 0030 movs r0, r6
2d40: f000 fcaf bl 36a2 <__malloc_lock>
2d44: 4a25 ldr r2, [pc, #148] ; (2ddc <_malloc_r+0xb4>)
2d46: 6814 ldr r4, [r2, #0]
2d48: 0021 movs r1, r4
2d4a: 2900 cmp r1, #0
2d4c: d119 bne.n 2d82 <_malloc_r+0x5a>
2d4e: 4c24 ldr r4, [pc, #144] ; (2de0 <_malloc_r+0xb8>)
2d50: 6823 ldr r3, [r4, #0]
2d52: 2b00 cmp r3, #0
2d54: d103 bne.n 2d5e <_malloc_r+0x36>
2d56: 0030 movs r0, r6
2d58: f000 fb10 bl 337c <_sbrk_r>
2d5c: 6020 str r0, [r4, #0]
2d5e: 0029 movs r1, r5
2d60: 0030 movs r0, r6
2d62: f000 fb0b bl 337c <_sbrk_r>
2d66: 1c43 adds r3, r0, #1
2d68: d12c bne.n 2dc4 <_malloc_r+0x9c>
2d6a: 230c movs r3, #12
2d6c: 0030 movs r0, r6
2d6e: 6033 str r3, [r6, #0]
2d70: f000 fc98 bl 36a4 <__malloc_unlock>
2d74: e003 b.n 2d7e <_malloc_r+0x56>
2d76: 2d00 cmp r5, #0
2d78: dadf bge.n 2d3a <_malloc_r+0x12>
2d7a: 230c movs r3, #12
2d7c: 6033 str r3, [r6, #0]
2d7e: 2000 movs r0, #0
2d80: bd70 pop {r4, r5, r6, pc}
2d82: 680b ldr r3, [r1, #0]
2d84: 1b5b subs r3, r3, r5
2d86: d41a bmi.n 2dbe <_malloc_r+0x96>
2d88: 2b0b cmp r3, #11
2d8a: d903 bls.n 2d94 <_malloc_r+0x6c>
2d8c: 600b str r3, [r1, #0]
2d8e: 18cc adds r4, r1, r3
2d90: 6025 str r5, [r4, #0]
2d92: e003 b.n 2d9c <_malloc_r+0x74>
2d94: 428c cmp r4, r1
2d96: d10e bne.n 2db6 <_malloc_r+0x8e>
2d98: 6863 ldr r3, [r4, #4]
2d9a: 6013 str r3, [r2, #0]
2d9c: 0030 movs r0, r6
2d9e: f000 fc81 bl 36a4 <__malloc_unlock>
2da2: 0020 movs r0, r4
2da4: 2207 movs r2, #7
2da6: 300b adds r0, #11
2da8: 1d23 adds r3, r4, #4
2daa: 4390 bics r0, r2
2dac: 1ac3 subs r3, r0, r3
2dae: d0e7 beq.n 2d80 <_malloc_r+0x58>
2db0: 425a negs r2, r3
2db2: 50e2 str r2, [r4, r3]
2db4: e7e4 b.n 2d80 <_malloc_r+0x58>
2db6: 684b ldr r3, [r1, #4]
2db8: 6063 str r3, [r4, #4]
2dba: 000c movs r4, r1
2dbc: e7ee b.n 2d9c <_malloc_r+0x74>
2dbe: 000c movs r4, r1
2dc0: 6849 ldr r1, [r1, #4]
2dc2: e7c2 b.n 2d4a <_malloc_r+0x22>
2dc4: 2303 movs r3, #3
2dc6: 1cc4 adds r4, r0, #3
2dc8: 439c bics r4, r3
2dca: 42a0 cmp r0, r4
2dcc: d0e0 beq.n 2d90 <_malloc_r+0x68>
2dce: 1a21 subs r1, r4, r0
2dd0: 0030 movs r0, r6
2dd2: f000 fad3 bl 337c <_sbrk_r>
2dd6: 1c43 adds r3, r0, #1
2dd8: d1da bne.n 2d90 <_malloc_r+0x68>
2dda: e7c6 b.n 2d6a <_malloc_r+0x42>
2ddc: 200001d0 .word 0x200001d0
2de0: 200001d4 .word 0x200001d4
00002de4 <__sfputc_r>:
2de4: 6893 ldr r3, [r2, #8]
2de6: b510 push {r4, lr}
2de8: 3b01 subs r3, #1
2dea: 6093 str r3, [r2, #8]
2dec: 2b00 cmp r3, #0
2dee: da05 bge.n 2dfc <__sfputc_r+0x18>
2df0: 6994 ldr r4, [r2, #24]
2df2: 42a3 cmp r3, r4
2df4: db08 blt.n 2e08 <__sfputc_r+0x24>
2df6: b2cb uxtb r3, r1
2df8: 2b0a cmp r3, #10
2dfa: d005 beq.n 2e08 <__sfputc_r+0x24>
2dfc: 6813 ldr r3, [r2, #0]
2dfe: 1c58 adds r0, r3, #1
2e00: 6010 str r0, [r2, #0]
2e02: 7019 strb r1, [r3, #0]
2e04: b2c8 uxtb r0, r1
2e06: bd10 pop {r4, pc}
2e08: f000 fb16 bl 3438 <__swbuf_r>
2e0c: e7fb b.n 2e06 <__sfputc_r+0x22>
00002e0e <__sfputs_r>:
2e0e: b5f8 push {r3, r4, r5, r6, r7, lr}
2e10: 0006 movs r6, r0
2e12: 000f movs r7, r1
2e14: 0014 movs r4, r2
2e16: 18d5 adds r5, r2, r3
2e18: 42ac cmp r4, r5
2e1a: d101 bne.n 2e20 <__sfputs_r+0x12>
2e1c: 2000 movs r0, #0
2e1e: e007 b.n 2e30 <__sfputs_r+0x22>
2e20: 7821 ldrb r1, [r4, #0]
2e22: 003a movs r2, r7
2e24: 0030 movs r0, r6
2e26: f7ff ffdd bl 2de4 <__sfputc_r>
2e2a: 3401 adds r4, #1
2e2c: 1c43 adds r3, r0, #1
2e2e: d1f3 bne.n 2e18 <__sfputs_r+0xa>
2e30: bdf8 pop {r3, r4, r5, r6, r7, pc}
...
00002e34 <_vfiprintf_r>:
2e34: b5f0 push {r4, r5, r6, r7, lr}
2e36: b09f sub sp, #124 ; 0x7c
2e38: 0006 movs r6, r0
2e3a: 000f movs r7, r1
2e3c: 0014 movs r4, r2
2e3e: 9305 str r3, [sp, #20]
2e40: 2800 cmp r0, #0
2e42: d004 beq.n 2e4e <_vfiprintf_r+0x1a>
2e44: 6983 ldr r3, [r0, #24]
2e46: 2b00 cmp r3, #0
2e48: d101 bne.n 2e4e <_vfiprintf_r+0x1a>
2e4a: f7ff fe17 bl 2a7c <__sinit>
2e4e: 4b7f ldr r3, [pc, #508] ; (304c <_vfiprintf_r+0x218>)
2e50: 429f cmp r7, r3
2e52: d15c bne.n 2f0e <_vfiprintf_r+0xda>
2e54: 6877 ldr r7, [r6, #4]
2e56: 89bb ldrh r3, [r7, #12]
2e58: 071b lsls r3, r3, #28
2e5a: d562 bpl.n 2f22 <_vfiprintf_r+0xee>
2e5c: 693b ldr r3, [r7, #16]
2e5e: 2b00 cmp r3, #0
2e60: d05f beq.n 2f22 <_vfiprintf_r+0xee>
2e62: 2300 movs r3, #0
2e64: ad06 add r5, sp, #24
2e66: 616b str r3, [r5, #20]
2e68: 3320 adds r3, #32
2e6a: 766b strb r3, [r5, #25]
2e6c: 3310 adds r3, #16
2e6e: 76ab strb r3, [r5, #26]
2e70: 9402 str r4, [sp, #8]
2e72: 9c02 ldr r4, [sp, #8]
2e74: 7823 ldrb r3, [r4, #0]
2e76: 2b00 cmp r3, #0
2e78: d15d bne.n 2f36 <_vfiprintf_r+0x102>
2e7a: 9b02 ldr r3, [sp, #8]
2e7c: 1ae3 subs r3, r4, r3
2e7e: 9304 str r3, [sp, #16]
2e80: d00d beq.n 2e9e <_vfiprintf_r+0x6a>
2e82: 9b04 ldr r3, [sp, #16]
2e84: 9a02 ldr r2, [sp, #8]
2e86: 0039 movs r1, r7
2e88: 0030 movs r0, r6
2e8a: f7ff ffc0 bl 2e0e <__sfputs_r>
2e8e: 1c43 adds r3, r0, #1
2e90: d100 bne.n 2e94 <_vfiprintf_r+0x60>
2e92: e0cc b.n 302e <_vfiprintf_r+0x1fa>
2e94: 696a ldr r2, [r5, #20]
2e96: 9b04 ldr r3, [sp, #16]
2e98: 4694 mov ip, r2
2e9a: 4463 add r3, ip
2e9c: 616b str r3, [r5, #20]
2e9e: 7823 ldrb r3, [r4, #0]
2ea0: 2b00 cmp r3, #0
2ea2: d100 bne.n 2ea6 <_vfiprintf_r+0x72>
2ea4: e0c3 b.n 302e <_vfiprintf_r+0x1fa>
2ea6: 2201 movs r2, #1
2ea8: 2300 movs r3, #0
2eaa: 4252 negs r2, r2
2eac: 606a str r2, [r5, #4]
2eae: a902 add r1, sp, #8
2eb0: 3254 adds r2, #84 ; 0x54
2eb2: 1852 adds r2, r2, r1
2eb4: 3401 adds r4, #1
2eb6: 602b str r3, [r5, #0]
2eb8: 60eb str r3, [r5, #12]
2eba: 60ab str r3, [r5, #8]
2ebc: 7013 strb r3, [r2, #0]
2ebe: 65ab str r3, [r5, #88] ; 0x58
2ec0: 7821 ldrb r1, [r4, #0]
2ec2: 2205 movs r2, #5
2ec4: 4862 ldr r0, [pc, #392] ; (3050 <_vfiprintf_r+0x21c>)
2ec6: f000 fbe1 bl 368c <memchr>
2eca: 1c63 adds r3, r4, #1
2ecc: 469c mov ip, r3
2ece: 2800 cmp r0, #0
2ed0: d135 bne.n 2f3e <_vfiprintf_r+0x10a>
2ed2: 6829 ldr r1, [r5, #0]
2ed4: 06cb lsls r3, r1, #27
2ed6: d504 bpl.n 2ee2 <_vfiprintf_r+0xae>
2ed8: 2353 movs r3, #83 ; 0x53
2eda: aa02 add r2, sp, #8
2edc: 3020 adds r0, #32
2ede: 189b adds r3, r3, r2
2ee0: 7018 strb r0, [r3, #0]
2ee2: 070b lsls r3, r1, #28
2ee4: d504 bpl.n 2ef0 <_vfiprintf_r+0xbc>
2ee6: 2353 movs r3, #83 ; 0x53
2ee8: 202b movs r0, #43 ; 0x2b
2eea: aa02 add r2, sp, #8
2eec: 189b adds r3, r3, r2
2eee: 7018 strb r0, [r3, #0]
2ef0: 7823 ldrb r3, [r4, #0]
2ef2: 2b2a cmp r3, #42 ; 0x2a
2ef4: d02c beq.n 2f50 <_vfiprintf_r+0x11c>
2ef6: 2000 movs r0, #0
2ef8: 210a movs r1, #10
2efa: 9b09 ldr r3, [sp, #36] ; 0x24
2efc: 7822 ldrb r2, [r4, #0]
2efe: 3a30 subs r2, #48 ; 0x30
2f00: 2a09 cmp r2, #9
2f02: d800 bhi.n 2f06 <_vfiprintf_r+0xd2>
2f04: e06b b.n 2fde <_vfiprintf_r+0x1aa>
2f06: 2800 cmp r0, #0
2f08: d02a beq.n 2f60 <_vfiprintf_r+0x12c>
2f0a: 9309 str r3, [sp, #36] ; 0x24
2f0c: e028 b.n 2f60 <_vfiprintf_r+0x12c>
2f0e: 4b51 ldr r3, [pc, #324] ; (3054 <_vfiprintf_r+0x220>)
2f10: 429f cmp r7, r3
2f12: d101 bne.n 2f18 <_vfiprintf_r+0xe4>
2f14: 68b7 ldr r7, [r6, #8]
2f16: e79e b.n 2e56 <_vfiprintf_r+0x22>
2f18: 4b4f ldr r3, [pc, #316] ; (3058 <_vfiprintf_r+0x224>)
2f1a: 429f cmp r7, r3
2f1c: d19b bne.n 2e56 <_vfiprintf_r+0x22>
2f1e: 68f7 ldr r7, [r6, #12]
2f20: e799 b.n 2e56 <_vfiprintf_r+0x22>
2f22: 0039 movs r1, r7
2f24: 0030 movs r0, r6
2f26: f000 faf1 bl 350c <__swsetup_r>
2f2a: 2800 cmp r0, #0
2f2c: d099 beq.n 2e62 <_vfiprintf_r+0x2e>
2f2e: 2001 movs r0, #1
2f30: 4240 negs r0, r0
2f32: b01f add sp, #124 ; 0x7c
2f34: bdf0 pop {r4, r5, r6, r7, pc}
2f36: 2b25 cmp r3, #37 ; 0x25
2f38: d09f beq.n 2e7a <_vfiprintf_r+0x46>
2f3a: 3401 adds r4, #1
2f3c: e79a b.n 2e74 <_vfiprintf_r+0x40>
2f3e: 4b44 ldr r3, [pc, #272] ; (3050 <_vfiprintf_r+0x21c>)
2f40: 6829 ldr r1, [r5, #0]
2f42: 1ac0 subs r0, r0, r3
2f44: 2301 movs r3, #1
2f46: 4083 lsls r3, r0
2f48: 430b orrs r3, r1
2f4a: 602b str r3, [r5, #0]
2f4c: 4664 mov r4, ip
2f4e: e7b7 b.n 2ec0 <_vfiprintf_r+0x8c>
2f50: 9b05 ldr r3, [sp, #20]
2f52: 1d18 adds r0, r3, #4
2f54: 681b ldr r3, [r3, #0]
2f56: 9005 str r0, [sp, #20]
2f58: 2b00 cmp r3, #0
2f5a: db3a blt.n 2fd2 <_vfiprintf_r+0x19e>
2f5c: 9309 str r3, [sp, #36] ; 0x24
2f5e: 4664 mov r4, ip
2f60: 7823 ldrb r3, [r4, #0]
2f62: 2b2e cmp r3, #46 ; 0x2e
2f64: d10b bne.n 2f7e <_vfiprintf_r+0x14a>
2f66: 7863 ldrb r3, [r4, #1]
2f68: 1c62 adds r2, r4, #1
2f6a: 2b2a cmp r3, #42 ; 0x2a
2f6c: d13f bne.n 2fee <_vfiprintf_r+0x1ba>
2f6e: 9b05 ldr r3, [sp, #20]
2f70: 3402 adds r4, #2
2f72: 1d1a adds r2, r3, #4
2f74: 681b ldr r3, [r3, #0]
2f76: 9205 str r2, [sp, #20]
2f78: 2b00 cmp r3, #0
2f7a: db35 blt.n 2fe8 <_vfiprintf_r+0x1b4>
2f7c: 9307 str r3, [sp, #28]
2f7e: 7821 ldrb r1, [r4, #0]
2f80: 2203 movs r2, #3
2f82: 4836 ldr r0, [pc, #216] ; (305c <_vfiprintf_r+0x228>)
2f84: f000 fb82 bl 368c <memchr>
2f88: 2800 cmp r0, #0
2f8a: d007 beq.n 2f9c <_vfiprintf_r+0x168>
2f8c: 4b33 ldr r3, [pc, #204] ; (305c <_vfiprintf_r+0x228>)
2f8e: 682a ldr r2, [r5, #0]
2f90: 1ac0 subs r0, r0, r3
2f92: 2340 movs r3, #64 ; 0x40
2f94: 4083 lsls r3, r0
2f96: 4313 orrs r3, r2
2f98: 602b str r3, [r5, #0]
2f9a: 3401 adds r4, #1
2f9c: 7821 ldrb r1, [r4, #0]
2f9e: 1c63 adds r3, r4, #1
2fa0: 2206 movs r2, #6
2fa2: 482f ldr r0, [pc, #188] ; (3060 <_vfiprintf_r+0x22c>)
2fa4: 9302 str r3, [sp, #8]
2fa6: 7629 strb r1, [r5, #24]
2fa8: f000 fb70 bl 368c <memchr>
2fac: 2800 cmp r0, #0
2fae: d044 beq.n 303a <_vfiprintf_r+0x206>
2fb0: 4b2c ldr r3, [pc, #176] ; (3064 <_vfiprintf_r+0x230>)
2fb2: 2b00 cmp r3, #0
2fb4: d12f bne.n 3016 <_vfiprintf_r+0x1e2>
2fb6: 6829 ldr r1, [r5, #0]
2fb8: 9b05 ldr r3, [sp, #20]
2fba: 2207 movs r2, #7
2fbc: 05c9 lsls r1, r1, #23
2fbe: d528 bpl.n 3012 <_vfiprintf_r+0x1de>
2fc0: 189b adds r3, r3, r2
2fc2: 4393 bics r3, r2
2fc4: 3308 adds r3, #8
2fc6: 9305 str r3, [sp, #20]
2fc8: 696b ldr r3, [r5, #20]
2fca: 9a03 ldr r2, [sp, #12]
2fcc: 189b adds r3, r3, r2
2fce: 616b str r3, [r5, #20]
2fd0: e74f b.n 2e72 <_vfiprintf_r+0x3e>
2fd2: 425b negs r3, r3
2fd4: 60eb str r3, [r5, #12]
2fd6: 2302 movs r3, #2
2fd8: 430b orrs r3, r1
2fda: 602b str r3, [r5, #0]
2fdc: e7bf b.n 2f5e <_vfiprintf_r+0x12a>
2fde: 434b muls r3, r1
2fe0: 3401 adds r4, #1
2fe2: 189b adds r3, r3, r2
2fe4: 2001 movs r0, #1
2fe6: e789 b.n 2efc <_vfiprintf_r+0xc8>
2fe8: 2301 movs r3, #1
2fea: 425b negs r3, r3
2fec: e7c6 b.n 2f7c <_vfiprintf_r+0x148>
2fee: 2300 movs r3, #0
2ff0: 0014 movs r4, r2
2ff2: 200a movs r0, #10
2ff4: 001a movs r2, r3
2ff6: 606b str r3, [r5, #4]
2ff8: 7821 ldrb r1, [r4, #0]
2ffa: 3930 subs r1, #48 ; 0x30
2ffc: 2909 cmp r1, #9
2ffe: d903 bls.n 3008 <_vfiprintf_r+0x1d4>
3000: 2b00 cmp r3, #0
3002: d0bc beq.n 2f7e <_vfiprintf_r+0x14a>
3004: 9207 str r2, [sp, #28]
3006: e7ba b.n 2f7e <_vfiprintf_r+0x14a>
3008: 4342 muls r2, r0
300a: 3401 adds r4, #1
300c: 1852 adds r2, r2, r1
300e: 2301 movs r3, #1
3010: e7f2 b.n 2ff8 <_vfiprintf_r+0x1c4>
3012: 3307 adds r3, #7
3014: e7d5 b.n 2fc2 <_vfiprintf_r+0x18e>
3016: ab05 add r3, sp, #20
3018: 9300 str r3, [sp, #0]
301a: 003a movs r2, r7
301c: 4b12 ldr r3, [pc, #72] ; (3068 <_vfiprintf_r+0x234>)
301e: 0029 movs r1, r5
3020: 0030 movs r0, r6
3022: e000 b.n 3026 <_vfiprintf_r+0x1f2>
3024: bf00 nop
3026: 9003 str r0, [sp, #12]
3028: 9b03 ldr r3, [sp, #12]
302a: 3301 adds r3, #1
302c: d1cc bne.n 2fc8 <_vfiprintf_r+0x194>
302e: 89bb ldrh r3, [r7, #12]
3030: 065b lsls r3, r3, #25
3032: d500 bpl.n 3036 <_vfiprintf_r+0x202>
3034: e77b b.n 2f2e <_vfiprintf_r+0xfa>
3036: 980b ldr r0, [sp, #44] ; 0x2c
3038: e77b b.n 2f32 <_vfiprintf_r+0xfe>
303a: ab05 add r3, sp, #20
303c: 9300 str r3, [sp, #0]
303e: 003a movs r2, r7
3040: 4b09 ldr r3, [pc, #36] ; (3068 <_vfiprintf_r+0x234>)
3042: 0029 movs r1, r5
3044: 0030 movs r0, r6
3046: f000 f87f bl 3148 <_printf_i>
304a: e7ec b.n 3026 <_vfiprintf_r+0x1f2>
304c: 000038cc .word 0x000038cc
3050: 0000390c .word 0x0000390c
3054: 000038ec .word 0x000038ec
3058: 000038ac .word 0x000038ac
305c: 00003912 .word 0x00003912
3060: 00003916 .word 0x00003916
3064: 00000000 .word 0x00000000
3068: 00002e0f .word 0x00002e0f
0000306c <_printf_common>:
306c: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
306e: 0015 movs r5, r2
3070: 9301 str r3, [sp, #4]
3072: 688a ldr r2, [r1, #8]
3074: 690b ldr r3, [r1, #16]
3076: 9000 str r0, [sp, #0]
3078: 000c movs r4, r1
307a: 4293 cmp r3, r2
307c: da00 bge.n 3080 <_printf_common+0x14>
307e: 0013 movs r3, r2
3080: 0022 movs r2, r4
3082: 602b str r3, [r5, #0]
3084: 3243 adds r2, #67 ; 0x43
3086: 7812 ldrb r2, [r2, #0]
3088: 2a00 cmp r2, #0
308a: d001 beq.n 3090 <_printf_common+0x24>
308c: 3301 adds r3, #1
308e: 602b str r3, [r5, #0]
3090: 6823 ldr r3, [r4, #0]
3092: 069b lsls r3, r3, #26
3094: d502 bpl.n 309c <_printf_common+0x30>
3096: 682b ldr r3, [r5, #0]
3098: 3302 adds r3, #2
309a: 602b str r3, [r5, #0]
309c: 2706 movs r7, #6
309e: 6823 ldr r3, [r4, #0]
30a0: 401f ands r7, r3
30a2: d027 beq.n 30f4 <_printf_common+0x88>
30a4: 0023 movs r3, r4
30a6: 3343 adds r3, #67 ; 0x43
30a8: 781b ldrb r3, [r3, #0]
30aa: 1e5a subs r2, r3, #1
30ac: 4193 sbcs r3, r2
30ae: 6822 ldr r2, [r4, #0]
30b0: 0692 lsls r2, r2, #26
30b2: d430 bmi.n 3116 <_printf_common+0xaa>
30b4: 0022 movs r2, r4
30b6: 9901 ldr r1, [sp, #4]
30b8: 3243 adds r2, #67 ; 0x43
30ba: 9800 ldr r0, [sp, #0]
30bc: 9e08 ldr r6, [sp, #32]
30be: 47b0 blx r6
30c0: 1c43 adds r3, r0, #1
30c2: d025 beq.n 3110 <_printf_common+0xa4>
30c4: 2306 movs r3, #6
30c6: 6820 ldr r0, [r4, #0]
30c8: 682a ldr r2, [r5, #0]
30ca: 68e1 ldr r1, [r4, #12]
30cc: 4003 ands r3, r0
30ce: 2500 movs r5, #0
30d0: 2b04 cmp r3, #4
30d2: d103 bne.n 30dc <_printf_common+0x70>
30d4: 1a8d subs r5, r1, r2
30d6: 43eb mvns r3, r5
30d8: 17db asrs r3, r3, #31
30da: 401d ands r5, r3
30dc: 68a3 ldr r3, [r4, #8]
30de: 6922 ldr r2, [r4, #16]
30e0: 4293 cmp r3, r2
30e2: dd01 ble.n 30e8 <_printf_common+0x7c>
30e4: 1a9b subs r3, r3, r2
30e6: 18ed adds r5, r5, r3
30e8: 2700 movs r7, #0
30ea: 42bd cmp r5, r7
30ec: d120 bne.n 3130 <_printf_common+0xc4>
30ee: 2000 movs r0, #0
30f0: e010 b.n 3114 <_printf_common+0xa8>
30f2: 3701 adds r7, #1
30f4: 68e3 ldr r3, [r4, #12]
30f6: 682a ldr r2, [r5, #0]
30f8: 1a9b subs r3, r3, r2
30fa: 429f cmp r7, r3
30fc: dad2 bge.n 30a4 <_printf_common+0x38>
30fe: 0022 movs r2, r4
3100: 2301 movs r3, #1
3102: 3219 adds r2, #25
3104: 9901 ldr r1, [sp, #4]
3106: 9800 ldr r0, [sp, #0]
3108: 9e08 ldr r6, [sp, #32]
310a: 47b0 blx r6
310c: 1c43 adds r3, r0, #1
310e: d1f0 bne.n 30f2 <_printf_common+0x86>
3110: 2001 movs r0, #1
3112: 4240 negs r0, r0
3114: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc}
3116: 2030 movs r0, #48 ; 0x30
3118: 18e1 adds r1, r4, r3
311a: 3143 adds r1, #67 ; 0x43
311c: 7008 strb r0, [r1, #0]
311e: 0021 movs r1, r4
3120: 1c5a adds r2, r3, #1
3122: 3145 adds r1, #69 ; 0x45
3124: 7809 ldrb r1, [r1, #0]
3126: 18a2 adds r2, r4, r2
3128: 3243 adds r2, #67 ; 0x43
312a: 3302 adds r3, #2
312c: 7011 strb r1, [r2, #0]
312e: e7c1 b.n 30b4 <_printf_common+0x48>
3130: 0022 movs r2, r4
3132: 2301 movs r3, #1
3134: 321a adds r2, #26
3136: 9901 ldr r1, [sp, #4]
3138: 9800 ldr r0, [sp, #0]
313a: 9e08 ldr r6, [sp, #32]
313c: 47b0 blx r6
313e: 1c43 adds r3, r0, #1
3140: d0e6 beq.n 3110 <_printf_common+0xa4>
3142: 3701 adds r7, #1
3144: e7d1 b.n 30ea <_printf_common+0x7e>
...
00003148 <_printf_i>:
3148: b5f0 push {r4, r5, r6, r7, lr}
314a: b08b sub sp, #44 ; 0x2c
314c: 9206 str r2, [sp, #24]
314e: 000a movs r2, r1
3150: 3243 adds r2, #67 ; 0x43
3152: 9307 str r3, [sp, #28]
3154: 9005 str r0, [sp, #20]
3156: 9204 str r2, [sp, #16]
3158: 7e0a ldrb r2, [r1, #24]
315a: 000c movs r4, r1
315c: 9b10 ldr r3, [sp, #64] ; 0x40
315e: 2a6e cmp r2, #110 ; 0x6e
3160: d100 bne.n 3164 <_printf_i+0x1c>
3162: e08f b.n 3284 <_printf_i+0x13c>
3164: d817 bhi.n 3196 <_printf_i+0x4e>
3166: 2a63 cmp r2, #99 ; 0x63
3168: d02c beq.n 31c4 <_printf_i+0x7c>
316a: d808 bhi.n 317e <_printf_i+0x36>
316c: 2a00 cmp r2, #0
316e: d100 bne.n 3172 <_printf_i+0x2a>
3170: e099 b.n 32a6 <_printf_i+0x15e>
3172: 2a58 cmp r2, #88 ; 0x58
3174: d054 beq.n 3220 <_printf_i+0xd8>
3176: 0026 movs r6, r4
3178: 3642 adds r6, #66 ; 0x42
317a: 7032 strb r2, [r6, #0]
317c: e029 b.n 31d2 <_printf_i+0x8a>
317e: 2a64 cmp r2, #100 ; 0x64
3180: d001 beq.n 3186 <_printf_i+0x3e>
3182: 2a69 cmp r2, #105 ; 0x69
3184: d1f7 bne.n 3176 <_printf_i+0x2e>
3186: 6821 ldr r1, [r4, #0]
3188: 681a ldr r2, [r3, #0]
318a: 0608 lsls r0, r1, #24
318c: d523 bpl.n 31d6 <_printf_i+0x8e>
318e: 1d11 adds r1, r2, #4
3190: 6019 str r1, [r3, #0]
3192: 6815 ldr r5, [r2, #0]
3194: e025 b.n 31e2 <_printf_i+0x9a>
3196: 2a73 cmp r2, #115 ; 0x73
3198: d100 bne.n 319c <_printf_i+0x54>
319a: e088 b.n 32ae <_printf_i+0x166>
319c: d808 bhi.n 31b0 <_printf_i+0x68>
319e: 2a6f cmp r2, #111 ; 0x6f
31a0: d029 beq.n 31f6 <_printf_i+0xae>
31a2: 2a70 cmp r2, #112 ; 0x70
31a4: d1e7 bne.n 3176 <_printf_i+0x2e>
31a6: 2220 movs r2, #32
31a8: 6809 ldr r1, [r1, #0]
31aa: 430a orrs r2, r1
31ac: 6022 str r2, [r4, #0]
31ae: e003 b.n 31b8 <_printf_i+0x70>
31b0: 2a75 cmp r2, #117 ; 0x75
31b2: d020 beq.n 31f6 <_printf_i+0xae>
31b4: 2a78 cmp r2, #120 ; 0x78
31b6: d1de bne.n 3176 <_printf_i+0x2e>
31b8: 0022 movs r2, r4
31ba: 2178 movs r1, #120 ; 0x78
31bc: 3245 adds r2, #69 ; 0x45
31be: 7011 strb r1, [r2, #0]
31c0: 4a6c ldr r2, [pc, #432] ; (3374 <_printf_i+0x22c>)
31c2: e030 b.n 3226 <_printf_i+0xde>
31c4: 000e movs r6, r1
31c6: 681a ldr r2, [r3, #0]
31c8: 3642 adds r6, #66 ; 0x42
31ca: 1d11 adds r1, r2, #4
31cc: 6019 str r1, [r3, #0]
31ce: 6813 ldr r3, [r2, #0]
31d0: 7033 strb r3, [r6, #0]
31d2: 2301 movs r3, #1
31d4: e079 b.n 32ca <_printf_i+0x182>
31d6: 0649 lsls r1, r1, #25
31d8: d5d9 bpl.n 318e <_printf_i+0x46>
31da: 1d11 adds r1, r2, #4
31dc: 6019 str r1, [r3, #0]
31de: 2300 movs r3, #0
31e0: 5ed5 ldrsh r5, [r2, r3]
31e2: 2d00 cmp r5, #0
31e4: da03 bge.n 31ee <_printf_i+0xa6>
31e6: 232d movs r3, #45 ; 0x2d
31e8: 9a04 ldr r2, [sp, #16]
31ea: 426d negs r5, r5
31ec: 7013 strb r3, [r2, #0]
31ee: 4b62 ldr r3, [pc, #392] ; (3378 <_printf_i+0x230>)
31f0: 270a movs r7, #10
31f2: 9303 str r3, [sp, #12]
31f4: e02f b.n 3256 <_printf_i+0x10e>
31f6: 6820 ldr r0, [r4, #0]
31f8: 6819 ldr r1, [r3, #0]
31fa: 0605 lsls r5, r0, #24
31fc: d503 bpl.n 3206 <_printf_i+0xbe>
31fe: 1d08 adds r0, r1, #4
3200: 6018 str r0, [r3, #0]
3202: 680d ldr r5, [r1, #0]
3204: e005 b.n 3212 <_printf_i+0xca>
3206: 0640 lsls r0, r0, #25
3208: d5f9 bpl.n 31fe <_printf_i+0xb6>
320a: 680d ldr r5, [r1, #0]
320c: 1d08 adds r0, r1, #4
320e: 6018 str r0, [r3, #0]
3210: b2ad uxth r5, r5
3212: 4b59 ldr r3, [pc, #356] ; (3378 <_printf_i+0x230>)
3214: 2708 movs r7, #8
3216: 9303 str r3, [sp, #12]
3218: 2a6f cmp r2, #111 ; 0x6f
321a: d018 beq.n 324e <_printf_i+0x106>
321c: 270a movs r7, #10
321e: e016 b.n 324e <_printf_i+0x106>
3220: 3145 adds r1, #69 ; 0x45
3222: 700a strb r2, [r1, #0]
3224: 4a54 ldr r2, [pc, #336] ; (3378 <_printf_i+0x230>)
3226: 9203 str r2, [sp, #12]
3228: 681a ldr r2, [r3, #0]
322a: 6821 ldr r1, [r4, #0]
322c: 1d10 adds r0, r2, #4
322e: 6018 str r0, [r3, #0]
3230: 6815 ldr r5, [r2, #0]
3232: 0608 lsls r0, r1, #24
3234: d522 bpl.n 327c <_printf_i+0x134>
3236: 07cb lsls r3, r1, #31
3238: d502 bpl.n 3240 <_printf_i+0xf8>
323a: 2320 movs r3, #32
323c: 4319 orrs r1, r3
323e: 6021 str r1, [r4, #0]
3240: 2710 movs r7, #16
3242: 2d00 cmp r5, #0
3244: d103 bne.n 324e <_printf_i+0x106>
3246: 2320 movs r3, #32
3248: 6822 ldr r2, [r4, #0]
324a: 439a bics r2, r3
324c: 6022 str r2, [r4, #0]
324e: 0023 movs r3, r4
3250: 2200 movs r2, #0
3252: 3343 adds r3, #67 ; 0x43
3254: 701a strb r2, [r3, #0]
3256: 6863 ldr r3, [r4, #4]
3258: 60a3 str r3, [r4, #8]
325a: 2b00 cmp r3, #0
325c: db5c blt.n 3318 <_printf_i+0x1d0>
325e: 2204 movs r2, #4
3260: 6821 ldr r1, [r4, #0]
3262: 4391 bics r1, r2
3264: 6021 str r1, [r4, #0]
3266: 2d00 cmp r5, #0
3268: d158 bne.n 331c <_printf_i+0x1d4>
326a: 9e04 ldr r6, [sp, #16]
326c: 2b00 cmp r3, #0
326e: d064 beq.n 333a <_printf_i+0x1f2>
3270: 0026 movs r6, r4
3272: 9b03 ldr r3, [sp, #12]
3274: 3642 adds r6, #66 ; 0x42
3276: 781b ldrb r3, [r3, #0]
3278: 7033 strb r3, [r6, #0]
327a: e05e b.n 333a <_printf_i+0x1f2>
327c: 0648 lsls r0, r1, #25
327e: d5da bpl.n 3236 <_printf_i+0xee>
3280: b2ad uxth r5, r5
3282: e7d8 b.n 3236 <_printf_i+0xee>
3284: 6809 ldr r1, [r1, #0]
3286: 681a ldr r2, [r3, #0]
3288: 0608 lsls r0, r1, #24
328a: d505 bpl.n 3298 <_printf_i+0x150>
328c: 1d11 adds r1, r2, #4
328e: 6019 str r1, [r3, #0]
3290: 6813 ldr r3, [r2, #0]
3292: 6962 ldr r2, [r4, #20]
3294: 601a str r2, [r3, #0]
3296: e006 b.n 32a6 <_printf_i+0x15e>
3298: 0649 lsls r1, r1, #25
329a: d5f7 bpl.n 328c <_printf_i+0x144>
329c: 1d11 adds r1, r2, #4
329e: 6019 str r1, [r3, #0]
32a0: 6813 ldr r3, [r2, #0]
32a2: 8aa2 ldrh r2, [r4, #20]
32a4: 801a strh r2, [r3, #0]
32a6: 2300 movs r3, #0
32a8: 9e04 ldr r6, [sp, #16]
32aa: 6123 str r3, [r4, #16]
32ac: e054 b.n 3358 <_printf_i+0x210>
32ae: 681a ldr r2, [r3, #0]
32b0: 1d11 adds r1, r2, #4
32b2: 6019 str r1, [r3, #0]
32b4: 6816 ldr r6, [r2, #0]
32b6: 2100 movs r1, #0
32b8: 6862 ldr r2, [r4, #4]
32ba: 0030 movs r0, r6
32bc: f000 f9e6 bl 368c <memchr>
32c0: 2800 cmp r0, #0
32c2: d001 beq.n 32c8 <_printf_i+0x180>
32c4: 1b80 subs r0, r0, r6
32c6: 6060 str r0, [r4, #4]
32c8: 6863 ldr r3, [r4, #4]
32ca: 6123 str r3, [r4, #16]
32cc: 2300 movs r3, #0
32ce: 9a04 ldr r2, [sp, #16]
32d0: 7013 strb r3, [r2, #0]
32d2: e041 b.n 3358 <_printf_i+0x210>
32d4: 6923 ldr r3, [r4, #16]
32d6: 0032 movs r2, r6
32d8: 9906 ldr r1, [sp, #24]
32da: 9805 ldr r0, [sp, #20]
32dc: 9d07 ldr r5, [sp, #28]
32de: 47a8 blx r5
32e0: 1c43 adds r3, r0, #1
32e2: d043 beq.n 336c <_printf_i+0x224>
32e4: 6823 ldr r3, [r4, #0]
32e6: 2500 movs r5, #0
32e8: 079b lsls r3, r3, #30
32ea: d40f bmi.n 330c <_printf_i+0x1c4>
32ec: 9b09 ldr r3, [sp, #36] ; 0x24
32ee: 68e0 ldr r0, [r4, #12]
32f0: 4298 cmp r0, r3
32f2: da3d bge.n 3370 <_printf_i+0x228>
32f4: 0018 movs r0, r3
32f6: e03b b.n 3370 <_printf_i+0x228>
32f8: 0022 movs r2, r4
32fa: 2301 movs r3, #1
32fc: 3219 adds r2, #25
32fe: 9906 ldr r1, [sp, #24]
3300: 9805 ldr r0, [sp, #20]
3302: 9e07 ldr r6, [sp, #28]
3304: 47b0 blx r6
3306: 1c43 adds r3, r0, #1
3308: d030 beq.n 336c <_printf_i+0x224>
330a: 3501 adds r5, #1
330c: 68e3 ldr r3, [r4, #12]
330e: 9a09 ldr r2, [sp, #36] ; 0x24
3310: 1a9b subs r3, r3, r2
3312: 429d cmp r5, r3
3314: dbf0 blt.n 32f8 <_printf_i+0x1b0>
3316: e7e9 b.n 32ec <_printf_i+0x1a4>
3318: 2d00 cmp r5, #0
331a: d0a9 beq.n 3270 <_printf_i+0x128>
331c: 9e04 ldr r6, [sp, #16]
331e: 0028 movs r0, r5
3320: 0039 movs r1, r7
3322: f7fe fded bl 1f00 <__aeabi_uidivmod>
3326: 9b03 ldr r3, [sp, #12]
3328: 3e01 subs r6, #1
332a: 5c5b ldrb r3, [r3, r1]
332c: 0028 movs r0, r5
332e: 7033 strb r3, [r6, #0]
3330: 0039 movs r1, r7
3332: f7fe fd5f bl 1df4 <__udivsi3>
3336: 1e05 subs r5, r0, #0
3338: d1f1 bne.n 331e <_printf_i+0x1d6>
333a: 2f08 cmp r7, #8
333c: d109 bne.n 3352 <_printf_i+0x20a>
333e: 6823 ldr r3, [r4, #0]
3340: 07db lsls r3, r3, #31
3342: d506 bpl.n 3352 <_printf_i+0x20a>
3344: 6863 ldr r3, [r4, #4]
3346: 6922 ldr r2, [r4, #16]
3348: 4293 cmp r3, r2
334a: dc02 bgt.n 3352 <_printf_i+0x20a>
334c: 2330 movs r3, #48 ; 0x30
334e: 3e01 subs r6, #1
3350: 7033 strb r3, [r6, #0]
3352: 9b04 ldr r3, [sp, #16]
3354: 1b9b subs r3, r3, r6
3356: 6123 str r3, [r4, #16]
3358: 9b07 ldr r3, [sp, #28]
335a: aa09 add r2, sp, #36 ; 0x24
335c: 9300 str r3, [sp, #0]
335e: 0021 movs r1, r4
3360: 9b06 ldr r3, [sp, #24]
3362: 9805 ldr r0, [sp, #20]
3364: f7ff fe82 bl 306c <_printf_common>
3368: 1c43 adds r3, r0, #1
336a: d1b3 bne.n 32d4 <_printf_i+0x18c>
336c: 2001 movs r0, #1
336e: 4240 negs r0, r0
3370: b00b add sp, #44 ; 0x2c
3372: bdf0 pop {r4, r5, r6, r7, pc}
3374: 0000392e .word 0x0000392e
3378: 0000391d .word 0x0000391d
0000337c <_sbrk_r>:
337c: 2300 movs r3, #0
337e: b570 push {r4, r5, r6, lr}
3380: 4c06 ldr r4, [pc, #24] ; (339c <_sbrk_r+0x20>)
3382: 0005 movs r5, r0
3384: 0008 movs r0, r1
3386: 6023 str r3, [r4, #0]
3388: f7fe fcd4 bl 1d34 <_sbrk>
338c: 1c43 adds r3, r0, #1
338e: d103 bne.n 3398 <_sbrk_r+0x1c>
3390: 6823 ldr r3, [r4, #0]
3392: 2b00 cmp r3, #0
3394: d000 beq.n 3398 <_sbrk_r+0x1c>
3396: 602b str r3, [r5, #0]
3398: bd70 pop {r4, r5, r6, pc}
339a: 46c0 nop ; (mov r8, r8)
339c: 2000029c .word 0x2000029c
000033a0 <__sread>:
33a0: b570 push {r4, r5, r6, lr}
33a2: 000c movs r4, r1
33a4: 250e movs r5, #14
33a6: 5f49 ldrsh r1, [r1, r5]
33a8: f000 f97e bl 36a8 <_read_r>
33ac: 2800 cmp r0, #0
33ae: db03 blt.n 33b8 <__sread+0x18>
33b0: 6d63 ldr r3, [r4, #84] ; 0x54
33b2: 181b adds r3, r3, r0
33b4: 6563 str r3, [r4, #84] ; 0x54
33b6: bd70 pop {r4, r5, r6, pc}
33b8: 89a3 ldrh r3, [r4, #12]
33ba: 4a02 ldr r2, [pc, #8] ; (33c4 <__sread+0x24>)
33bc: 4013 ands r3, r2
33be: 81a3 strh r3, [r4, #12]
33c0: e7f9 b.n 33b6 <__sread+0x16>
33c2: 46c0 nop ; (mov r8, r8)
33c4: ffffefff .word 0xffffefff
000033c8 <__swrite>:
33c8: b5f8 push {r3, r4, r5, r6, r7, lr}
33ca: 001f movs r7, r3
33cc: 898b ldrh r3, [r1, #12]
33ce: 0005 movs r5, r0
33d0: 000c movs r4, r1
33d2: 0016 movs r6, r2
33d4: 05db lsls r3, r3, #23
33d6: d505 bpl.n 33e4 <__swrite+0x1c>
33d8: 230e movs r3, #14
33da: 5ec9 ldrsh r1, [r1, r3]
33dc: 2200 movs r2, #0
33de: 2302 movs r3, #2
33e0: f000 f940 bl 3664 <_lseek_r>
33e4: 89a3 ldrh r3, [r4, #12]
33e6: 4a05 ldr r2, [pc, #20] ; (33fc <__swrite+0x34>)
33e8: 0028 movs r0, r5
33ea: 4013 ands r3, r2
33ec: 81a3 strh r3, [r4, #12]
33ee: 0032 movs r2, r6
33f0: 230e movs r3, #14
33f2: 5ee1 ldrsh r1, [r4, r3]
33f4: 003b movs r3, r7
33f6: f000 f875 bl 34e4 <_write_r>
33fa: bdf8 pop {r3, r4, r5, r6, r7, pc}
33fc: ffffefff .word 0xffffefff
00003400 <__sseek>:
3400: b570 push {r4, r5, r6, lr}
3402: 000c movs r4, r1
3404: 250e movs r5, #14
3406: 5f49 ldrsh r1, [r1, r5]
3408: f000 f92c bl 3664 <_lseek_r>
340c: 89a3 ldrh r3, [r4, #12]
340e: 1c42 adds r2, r0, #1
3410: d103 bne.n 341a <__sseek+0x1a>
3412: 4a05 ldr r2, [pc, #20] ; (3428 <__sseek+0x28>)
3414: 4013 ands r3, r2
3416: 81a3 strh r3, [r4, #12]
3418: bd70 pop {r4, r5, r6, pc}
341a: 2280 movs r2, #128 ; 0x80
341c: 0152 lsls r2, r2, #5
341e: 4313 orrs r3, r2
3420: 81a3 strh r3, [r4, #12]
3422: 6560 str r0, [r4, #84] ; 0x54
3424: e7f8 b.n 3418 <__sseek+0x18>
3426: 46c0 nop ; (mov r8, r8)
3428: ffffefff .word 0xffffefff
0000342c <__sclose>:
342c: b510 push {r4, lr}
342e: 230e movs r3, #14
3430: 5ec9 ldrsh r1, [r1, r3]
3432: f000 f8e1 bl 35f8 <_close_r>
3436: bd10 pop {r4, pc}
00003438 <__swbuf_r>:
3438: b5f8 push {r3, r4, r5, r6, r7, lr}
343a: 0005 movs r5, r0
343c: 000e movs r6, r1
343e: 0014 movs r4, r2
3440: 2800 cmp r0, #0
3442: d004 beq.n 344e <__swbuf_r+0x16>
3444: 6983 ldr r3, [r0, #24]
3446: 2b00 cmp r3, #0
3448: d101 bne.n 344e <__swbuf_r+0x16>
344a: f7ff fb17 bl 2a7c <__sinit>
344e: 4b22 ldr r3, [pc, #136] ; (34d8 <__swbuf_r+0xa0>)
3450: 429c cmp r4, r3
3452: d12d bne.n 34b0 <__swbuf_r+0x78>
3454: 686c ldr r4, [r5, #4]
3456: 69a3 ldr r3, [r4, #24]
3458: 60a3 str r3, [r4, #8]
345a: 89a3 ldrh r3, [r4, #12]
345c: 071b lsls r3, r3, #28
345e: d531 bpl.n 34c4 <__swbuf_r+0x8c>
3460: 6923 ldr r3, [r4, #16]
3462: 2b00 cmp r3, #0
3464: d02e beq.n 34c4 <__swbuf_r+0x8c>
3466: 6823 ldr r3, [r4, #0]
3468: 6922 ldr r2, [r4, #16]
346a: b2f7 uxtb r7, r6
346c: 1a98 subs r0, r3, r2
346e: 6963 ldr r3, [r4, #20]
3470: b2f6 uxtb r6, r6
3472: 4298 cmp r0, r3
3474: db05 blt.n 3482 <__swbuf_r+0x4a>
3476: 0021 movs r1, r4
3478: 0028 movs r0, r5
347a: f7ff fa91 bl 29a0 <_fflush_r>
347e: 2800 cmp r0, #0
3480: d126 bne.n 34d0 <__swbuf_r+0x98>
3482: 68a3 ldr r3, [r4, #8]
3484: 3001 adds r0, #1
3486: 3b01 subs r3, #1
3488: 60a3 str r3, [r4, #8]
348a: 6823 ldr r3, [r4, #0]
348c: 1c5a adds r2, r3, #1
348e: 6022 str r2, [r4, #0]
3490: 701f strb r7, [r3, #0]
3492: 6963 ldr r3, [r4, #20]
3494: 4298 cmp r0, r3
3496: d004 beq.n 34a2 <__swbuf_r+0x6a>
3498: 89a3 ldrh r3, [r4, #12]
349a: 07db lsls r3, r3, #31
349c: d51a bpl.n 34d4 <__swbuf_r+0x9c>
349e: 2e0a cmp r6, #10
34a0: d118 bne.n 34d4 <__swbuf_r+0x9c>
34a2: 0021 movs r1, r4
34a4: 0028 movs r0, r5
34a6: f7ff fa7b bl 29a0 <_fflush_r>
34aa: 2800 cmp r0, #0
34ac: d012 beq.n 34d4 <__swbuf_r+0x9c>
34ae: e00f b.n 34d0 <__swbuf_r+0x98>
34b0: 4b0a ldr r3, [pc, #40] ; (34dc <__swbuf_r+0xa4>)
34b2: 429c cmp r4, r3
34b4: d101 bne.n 34ba <__swbuf_r+0x82>
34b6: 68ac ldr r4, [r5, #8]
34b8: e7cd b.n 3456 <__swbuf_r+0x1e>
34ba: 4b09 ldr r3, [pc, #36] ; (34e0 <__swbuf_r+0xa8>)
34bc: 429c cmp r4, r3
34be: d1ca bne.n 3456 <__swbuf_r+0x1e>
34c0: 68ec ldr r4, [r5, #12]
34c2: e7c8 b.n 3456 <__swbuf_r+0x1e>
34c4: 0021 movs r1, r4
34c6: 0028 movs r0, r5
34c8: f000 f820 bl 350c <__swsetup_r>
34cc: 2800 cmp r0, #0
34ce: d0ca beq.n 3466 <__swbuf_r+0x2e>
34d0: 2601 movs r6, #1
34d2: 4276 negs r6, r6
34d4: 0030 movs r0, r6
34d6: bdf8 pop {r3, r4, r5, r6, r7, pc}
34d8: 000038cc .word 0x000038cc
34dc: 000038ec .word 0x000038ec
34e0: 000038ac .word 0x000038ac
000034e4 <_write_r>:
34e4: b570 push {r4, r5, r6, lr}
34e6: 0005 movs r5, r0
34e8: 0008 movs r0, r1
34ea: 0011 movs r1, r2
34ec: 2200 movs r2, #0
34ee: 4c06 ldr r4, [pc, #24] ; (3508 <_write_r+0x24>)
34f0: 6022 str r2, [r4, #0]
34f2: 001a movs r2, r3
34f4: f7fd fbb8 bl c68 <_write>
34f8: 1c43 adds r3, r0, #1
34fa: d103 bne.n 3504 <_write_r+0x20>
34fc: 6823 ldr r3, [r4, #0]
34fe: 2b00 cmp r3, #0
3500: d000 beq.n 3504 <_write_r+0x20>
3502: 602b str r3, [r5, #0]
3504: bd70 pop {r4, r5, r6, pc}
3506: 46c0 nop ; (mov r8, r8)
3508: 2000029c .word 0x2000029c
0000350c <__swsetup_r>:
350c: 4b36 ldr r3, [pc, #216] ; (35e8 <__swsetup_r+0xdc>)
350e: b570 push {r4, r5, r6, lr}
3510: 681d ldr r5, [r3, #0]
3512: 0006 movs r6, r0
3514: 000c movs r4, r1
3516: 2d00 cmp r5, #0
3518: d005 beq.n 3526 <__swsetup_r+0x1a>
351a: 69ab ldr r3, [r5, #24]
351c: 2b00 cmp r3, #0
351e: d102 bne.n 3526 <__swsetup_r+0x1a>
3520: 0028 movs r0, r5
3522: f7ff faab bl 2a7c <__sinit>
3526: 4b31 ldr r3, [pc, #196] ; (35ec <__swsetup_r+0xe0>)
3528: 429c cmp r4, r3
352a: d10f bne.n 354c <__swsetup_r+0x40>
352c: 686c ldr r4, [r5, #4]
352e: 230c movs r3, #12
3530: 5ee2 ldrsh r2, [r4, r3]
3532: b293 uxth r3, r2
3534: 0719 lsls r1, r3, #28
3536: d42d bmi.n 3594 <__swsetup_r+0x88>
3538: 06d9 lsls r1, r3, #27
353a: d411 bmi.n 3560 <__swsetup_r+0x54>
353c: 2309 movs r3, #9
353e: 2001 movs r0, #1
3540: 6033 str r3, [r6, #0]
3542: 3337 adds r3, #55 ; 0x37
3544: 4313 orrs r3, r2
3546: 81a3 strh r3, [r4, #12]
3548: 4240 negs r0, r0
354a: bd70 pop {r4, r5, r6, pc}
354c: 4b28 ldr r3, [pc, #160] ; (35f0 <__swsetup_r+0xe4>)
354e: 429c cmp r4, r3
3550: d101 bne.n 3556 <__swsetup_r+0x4a>
3552: 68ac ldr r4, [r5, #8]
3554: e7eb b.n 352e <__swsetup_r+0x22>
3556: 4b27 ldr r3, [pc, #156] ; (35f4 <__swsetup_r+0xe8>)
3558: 429c cmp r4, r3
355a: d1e8 bne.n 352e <__swsetup_r+0x22>
355c: 68ec ldr r4, [r5, #12]
355e: e7e6 b.n 352e <__swsetup_r+0x22>
3560: 075b lsls r3, r3, #29
3562: d513 bpl.n 358c <__swsetup_r+0x80>
3564: 6b61 ldr r1, [r4, #52] ; 0x34
3566: 2900 cmp r1, #0
3568: d008 beq.n 357c <__swsetup_r+0x70>
356a: 0023 movs r3, r4
356c: 3344 adds r3, #68 ; 0x44
356e: 4299 cmp r1, r3
3570: d002 beq.n 3578 <__swsetup_r+0x6c>
3572: 0030 movs r0, r6
3574: f7ff fb8e bl 2c94 <_free_r>
3578: 2300 movs r3, #0
357a: 6363 str r3, [r4, #52] ; 0x34
357c: 2224 movs r2, #36 ; 0x24
357e: 89a3 ldrh r3, [r4, #12]
3580: 4393 bics r3, r2
3582: 81a3 strh r3, [r4, #12]
3584: 2300 movs r3, #0
3586: 6063 str r3, [r4, #4]
3588: 6923 ldr r3, [r4, #16]
358a: 6023 str r3, [r4, #0]
358c: 2308 movs r3, #8
358e: 89a2 ldrh r2, [r4, #12]
3590: 4313 orrs r3, r2
3592: 81a3 strh r3, [r4, #12]
3594: 6923 ldr r3, [r4, #16]
3596: 2b00 cmp r3, #0
3598: d10b bne.n 35b2 <__swsetup_r+0xa6>
359a: 21a0 movs r1, #160 ; 0xa0
359c: 2280 movs r2, #128 ; 0x80
359e: 89a3 ldrh r3, [r4, #12]
35a0: 0089 lsls r1, r1, #2
35a2: 0092 lsls r2, r2, #2
35a4: 400b ands r3, r1
35a6: 4293 cmp r3, r2
35a8: d003 beq.n 35b2 <__swsetup_r+0xa6>
35aa: 0021 movs r1, r4
35ac: 0030 movs r0, r6
35ae: f7ff fb23 bl 2bf8 <__smakebuf_r>
35b2: 2301 movs r3, #1
35b4: 89a2 ldrh r2, [r4, #12]
35b6: 4013 ands r3, r2
35b8: d011 beq.n 35de <__swsetup_r+0xd2>
35ba: 2300 movs r3, #0
35bc: 60a3 str r3, [r4, #8]
35be: 6963 ldr r3, [r4, #20]
35c0: 425b negs r3, r3
35c2: 61a3 str r3, [r4, #24]
35c4: 2000 movs r0, #0
35c6: 6923 ldr r3, [r4, #16]
35c8: 4283 cmp r3, r0
35ca: d1be bne.n 354a <__swsetup_r+0x3e>
35cc: 230c movs r3, #12
35ce: 5ee2 ldrsh r2, [r4, r3]
35d0: 0613 lsls r3, r2, #24
35d2: d5ba bpl.n 354a <__swsetup_r+0x3e>
35d4: 2340 movs r3, #64 ; 0x40
35d6: 4313 orrs r3, r2
35d8: 81a3 strh r3, [r4, #12]
35da: 3801 subs r0, #1
35dc: e7b5 b.n 354a <__swsetup_r+0x3e>
35de: 0792 lsls r2, r2, #30
35e0: d400 bmi.n 35e4 <__swsetup_r+0xd8>
35e2: 6963 ldr r3, [r4, #20]
35e4: 60a3 str r3, [r4, #8]
35e6: e7ed b.n 35c4 <__swsetup_r+0xb8>
35e8: 20000018 .word 0x20000018
35ec: 000038cc .word 0x000038cc
35f0: 000038ec .word 0x000038ec
35f4: 000038ac .word 0x000038ac
000035f8 <_close_r>:
35f8: 2300 movs r3, #0
35fa: b570 push {r4, r5, r6, lr}
35fc: 4c06 ldr r4, [pc, #24] ; (3618 <_close_r+0x20>)
35fe: 0005 movs r5, r0
3600: 0008 movs r0, r1
3602: 6023 str r3, [r4, #0]
3604: f7fe fba8 bl 1d58 <_close>
3608: 1c43 adds r3, r0, #1
360a: d103 bne.n 3614 <_close_r+0x1c>
360c: 6823 ldr r3, [r4, #0]
360e: 2b00 cmp r3, #0
3610: d000 beq.n 3614 <_close_r+0x1c>
3612: 602b str r3, [r5, #0]
3614: bd70 pop {r4, r5, r6, pc}
3616: 46c0 nop ; (mov r8, r8)
3618: 2000029c .word 0x2000029c
0000361c <_fstat_r>:
361c: 2300 movs r3, #0
361e: b570 push {r4, r5, r6, lr}
3620: 4c06 ldr r4, [pc, #24] ; (363c <_fstat_r+0x20>)
3622: 0005 movs r5, r0
3624: 0008 movs r0, r1
3626: 0011 movs r1, r2
3628: 6023 str r3, [r4, #0]
362a: f7fe fb98 bl 1d5e <_fstat>
362e: 1c43 adds r3, r0, #1
3630: d103 bne.n 363a <_fstat_r+0x1e>
3632: 6823 ldr r3, [r4, #0]
3634: 2b00 cmp r3, #0
3636: d000 beq.n 363a <_fstat_r+0x1e>
3638: 602b str r3, [r5, #0]
363a: bd70 pop {r4, r5, r6, pc}
363c: 2000029c .word 0x2000029c
00003640 <_isatty_r>:
3640: 2300 movs r3, #0
3642: b570 push {r4, r5, r6, lr}
3644: 4c06 ldr r4, [pc, #24] ; (3660 <_isatty_r+0x20>)
3646: 0005 movs r5, r0
3648: 0008 movs r0, r1
364a: 6023 str r3, [r4, #0]
364c: f7fe fb8c bl 1d68 <_isatty>
3650: 1c43 adds r3, r0, #1
3652: d103 bne.n 365c <_isatty_r+0x1c>
3654: 6823 ldr r3, [r4, #0]
3656: 2b00 cmp r3, #0
3658: d000 beq.n 365c <_isatty_r+0x1c>
365a: 602b str r3, [r5, #0]
365c: bd70 pop {r4, r5, r6, pc}
365e: 46c0 nop ; (mov r8, r8)
3660: 2000029c .word 0x2000029c
00003664 <_lseek_r>:
3664: b570 push {r4, r5, r6, lr}
3666: 0005 movs r5, r0
3668: 0008 movs r0, r1
366a: 0011 movs r1, r2
366c: 2200 movs r2, #0
366e: 4c06 ldr r4, [pc, #24] ; (3688 <_lseek_r+0x24>)
3670: 6022 str r2, [r4, #0]
3672: 001a movs r2, r3
3674: f7fe fb7a bl 1d6c <_lseek>
3678: 1c43 adds r3, r0, #1
367a: d103 bne.n 3684 <_lseek_r+0x20>
367c: 6823 ldr r3, [r4, #0]
367e: 2b00 cmp r3, #0
3680: d000 beq.n 3684 <_lseek_r+0x20>
3682: 602b str r3, [r5, #0]
3684: bd70 pop {r4, r5, r6, pc}
3686: 46c0 nop ; (mov r8, r8)
3688: 2000029c .word 0x2000029c
0000368c <memchr>:
368c: b2c9 uxtb r1, r1
368e: 1882 adds r2, r0, r2
3690: 4290 cmp r0, r2
3692: d101 bne.n 3698 <memchr+0xc>
3694: 2000 movs r0, #0
3696: 4770 bx lr
3698: 7803 ldrb r3, [r0, #0]
369a: 428b cmp r3, r1
369c: d0fb beq.n 3696 <memchr+0xa>
369e: 3001 adds r0, #1
36a0: e7f6 b.n 3690 <memchr+0x4>
000036a2 <__malloc_lock>:
36a2: 4770 bx lr
000036a4 <__malloc_unlock>:
36a4: 4770 bx lr
...
000036a8 <_read_r>:
36a8: b570 push {r4, r5, r6, lr}
36aa: 0005 movs r5, r0
36ac: 0008 movs r0, r1
36ae: 0011 movs r1, r2
36b0: 2200 movs r2, #0
36b2: 4c06 ldr r4, [pc, #24] ; (36cc <_read_r+0x24>)
36b4: 6022 str r2, [r4, #0]
36b6: 001a movs r2, r3
36b8: f7fd fab4 bl c24 <_read>
36bc: 1c43 adds r3, r0, #1
36be: d103 bne.n 36c8 <_read_r+0x20>
36c0: 6823 ldr r3, [r4, #0]
36c2: 2b00 cmp r3, #0
36c4: d000 beq.n 36c8 <_read_r+0x20>
36c6: 602b str r3, [r5, #0]
36c8: bd70 pop {r4, r5, r6, pc}
36ca: 46c0 nop ; (mov r8, r8)
36cc: 2000029c .word 0x2000029c
36d0: 000002fa .word 0x000002fa
36d4: 00000540 .word 0x00000540
36d8: 00000540 .word 0x00000540
36dc: 00000540 .word 0x00000540
36e0: 00000540 .word 0x00000540
36e4: 00000540 .word 0x00000540
36e8: 00000540 .word 0x00000540
36ec: 00000540 .word 0x00000540
36f0: 00000540 .word 0x00000540
36f4: 00000540 .word 0x00000540
36f8: 00000540 .word 0x00000540
36fc: 00000540 .word 0x00000540
3700: 00000540 .word 0x00000540
3704: 00000540 .word 0x00000540
3708: 00000540 .word 0x00000540
370c: 00000540 .word 0x00000540
3710: 000002e2 .word 0x000002e2
3714: 00000540 .word 0x00000540
3718: 00000540 .word 0x00000540
371c: 00000540 .word 0x00000540
3720: 00000540 .word 0x00000540
3724: 00000540 .word 0x00000540
3728: 00000540 .word 0x00000540
372c: 00000540 .word 0x00000540
3730: 00000540 .word 0x00000540
3734: 00000540 .word 0x00000540
3738: 00000540 .word 0x00000540
373c: 00000540 .word 0x00000540
3740: 00000540 .word 0x00000540
3744: 00000540 .word 0x00000540
3748: 00000540 .word 0x00000540
374c: 00000540 .word 0x00000540
3750: 000002f2 .word 0x000002f2
3754: 00000540 .word 0x00000540
3758: 00000540 .word 0x00000540
375c: 00000540 .word 0x00000540
3760: 00000540 .word 0x00000540
3764: 00000540 .word 0x00000540
3768: 00000540 .word 0x00000540
376c: 00000540 .word 0x00000540
3770: 00000540 .word 0x00000540
3774: 00000540 .word 0x00000540
3778: 00000540 .word 0x00000540
377c: 00000540 .word 0x00000540
3780: 00000540 .word 0x00000540
3784: 00000540 .word 0x00000540
3788: 00000540 .word 0x00000540
378c: 00000540 .word 0x00000540
3790: 000002ea .word 0x000002ea
3794: 00000302 .word 0x00000302
3798: 000002ca .word 0x000002ca
379c: 000002da .word 0x000002da
37a0: 000002d2 .word 0x000002d2
37a4: 00000002 .word 0x00000002
37a8: 00000003 .word 0x00000003
37ac: 00000028 .word 0x00000028
37b0: 00000029 .word 0x00000029
37b4: 00000004 .word 0x00000004
37b8: 00000005 .word 0x00000005
37bc: 00000006 .word 0x00000006
37c0: 00000007 .word 0x00000007
37c4: 00000020 .word 0x00000020
37c8: 00000021 .word 0x00000021
37cc: 00000022 .word 0x00000022
37d0: 00000023 .word 0x00000023
37d4: 00000024 .word 0x00000024
37d8: 00000025 .word 0x00000025
37dc: 00000026 .word 0x00000026
37e0: 00000027 .word 0x00000027
37e4: 00000008 .word 0x00000008
37e8: 00000009 .word 0x00000009
37ec: 0000000a .word 0x0000000a
37f0: 0000000b .word 0x0000000b
37f4: 42000800 .word 0x42000800
37f8: 42000c00 .word 0x42000c00
37fc: 42001000 .word 0x42001000
3800: 42001400 .word 0x42001400
3804: 42001800 .word 0x42001800
3808: 42001c00 .word 0x42001c00
380c: 000016be .word 0x000016be
3810: 000016ba .word 0x000016ba
3814: 000016ba .word 0x000016ba
3818: 00001720 .word 0x00001720
381c: 00001720 .word 0x00001720
3820: 000016d2 .word 0x000016d2
3824: 000016c4 .word 0x000016c4
3828: 000016d8 .word 0x000016d8
382c: 0000170e .word 0x0000170e
3830: 000017a8 .word 0x000017a8
3834: 00001788 .word 0x00001788
3838: 00001788 .word 0x00001788
383c: 00001814 .word 0x00001814
3840: 0000179a .word 0x0000179a
3844: 000017b6 .word 0x000017b6
3848: 0000178c .word 0x0000178c
384c: 000017c4 .word 0x000017c4
3850: 00001804 .word 0x00001804
3854: 746c6f56 .word 0x746c6f56
3858: 3a656761 .word 0x3a656761
385c: 2e642520 .word 0x2e642520
3860: 64333025 .word 0x64333025
3864: 00000a0d .word 0x00000a0d
3868: 0000208c .word 0x0000208c
386c: 00001fdc .word 0x00001fdc
3870: 00001fdc .word 0x00001fdc
3874: 00001fda .word 0x00001fda
3878: 0000207e .word 0x0000207e
387c: 0000207e .word 0x0000207e
3880: 00002074 .word 0x00002074
3884: 00001fda .word 0x00001fda
3888: 0000207e .word 0x0000207e
388c: 00002074 .word 0x00002074
3890: 0000207e .word 0x0000207e
3894: 00001fda .word 0x00001fda
3898: 00002084 .word 0x00002084
389c: 00002084 .word 0x00002084
38a0: 00002084 .word 0x00002084
38a4: 00002114 .word 0x00002114
000038a8 <_global_impure_ptr>:
38a8: 2000001c ...
000038ac <__sf_fake_stderr>:
...
000038cc <__sf_fake_stdin>:
...
000038ec <__sf_fake_stdout>:
...
390c: 2b302d23 6c680020 6665004c 47464567 #-0+ .hlL.efgEFG
391c: 32313000 36353433 41393837 45444342 .0123456789ABCDE
392c: 31300046 35343332 39383736 64636261 F.0123456789abcd
393c: 00006665 ef..
00003940 <_init>:
3940: b5f8 push {r3, r4, r5, r6, r7, lr}
3942: 46c0 nop ; (mov r8, r8)
3944: bcf8 pop {r3, r4, r5, r6, r7}
3946: bc08 pop {r3}
3948: 469e mov lr, r3
394a: 4770 bx lr
0000394c <__init_array_start>:
394c: 000000dd .word 0x000000dd
00003950 <_fini>:
3950: b5f8 push {r3, r4, r5, r6, r7, lr}
3952: 46c0 nop ; (mov r8, r8)
3954: bcf8 pop {r3, r4, r5, r6, r7}
3956: bc08 pop {r3}
3958: 469e mov lr, r3
395a: 4770 bx lr
0000395c <__fini_array_start>:
395c: 000000b5 .word 0x000000b5
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