/* Auto-generated config file hpl_oscctrl_config.h */ #ifndef HPL_OSCCTRL_CONFIG_H #define HPL_OSCCTRL_CONFIG_H // <<< Use Configuration Wizard in Context Menu >>> // External Multipurpose Crystal Oscillator Configuration // Indicates whether configuration for XOSC0 is enabled or not // enable_xosc0 #ifndef CONF_XOSC0_CONFIG #define CONF_XOSC0_CONFIG 0 #endif // Frequency <8000000-48000000> // Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. // xosc0_frequency #ifndef CONF_XOSC_FREQUENCY #define CONF_XOSC0_FREQUENCY 12000000 #endif // External Multipurpose Crystal Oscillator Control // Oscillator enable // Indicates whether External Multipurpose Crystal Oscillator is enabled or not // xosc0_arch_enable #ifndef CONF_XOSC0_ENABLE #define CONF_XOSC0_ENABLE 0 #endif // Start-Up Time // <0x0=>31us // <0x1=>61us // <0x2=>122us // <0x3=>244us // <0x4=>488us // <0x5=>977us // <0x6=>1953us // <0x7=>3906us // <0x8=>7813us // <0x9=>15625us // <0xA=>31250us // <0xB=>62500us // <0xC=>125000us // <0xD=>250000us // <0xE=>500000us // <0xF=>1000000us // xosc0_arch_startup #ifndef CONF_XOSC0_STARTUP #define CONF_XOSC0_STARTUP 0 #endif // Clock Switch Back // Indicates whether Clock Switch Back is enabled or not // xosc0_arch_swben #ifndef CONF_XOSC0_SWBEN #define CONF_XOSC0_SWBEN 0 #endif // Clock Failure Detector // Indicates whether Clock Failure Detector is enabled or not // xosc0_arch_cfden #ifndef CONF_XOSC0_CFDEN #define CONF_XOSC0_CFDEN 0 #endif // Automatic Loop Control Enable // Indicates whether Automatic Loop Control is enabled or not // xosc0_arch_enalc #ifndef CONF_XOSC0_ENALC #define CONF_XOSC0_ENALC 0 #endif // Low Buffer Gain Enable // Indicates whether Low Buffer Gain is enabled or not // xosc0_arch_lowbufgain #ifndef CONF_XOSC0_LOWBUFGAIN #define CONF_XOSC0_LOWBUFGAIN 0 #endif // On Demand Control // Indicates whether On Demand Control is enabled or not // xosc0_arch_ondemand #ifndef CONF_XOSC0_ONDEMAND #define CONF_XOSC0_ONDEMAND 0 #endif // Run in Standby // Indicates whether Run in Standby is enabled or not // xosc0_arch_runstdby #ifndef CONF_XOSC0_RUNSTDBY #define CONF_XOSC0_RUNSTDBY 0 #endif // Crystal connected to XIN/XOUT Enable // Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not // xosc0_arch_xtalen #ifndef CONF_XOSC0_XTALEN #define CONF_XOSC0_XTALEN 0 #endif // // #if CONF_XOSC0_FREQUENCY >= 32000000 #define CONF_XOSC0_CFDPRESC 0x0 #define CONF_XOSC0_IMULT 0x7 #define CONF_XOSC0_IPTAT 0x3 #elif CONF_XOSC0_FREQUENCY >= 24000000 #define CONF_XOSC0_CFDPRESC 0x1 #define CONF_XOSC0_IMULT 0x6 #define CONF_XOSC0_IPTAT 0x3 #elif CONF_XOSC0_FREQUENCY >= 16000000 #define CONF_XOSC0_CFDPRESC 0x2 #define CONF_XOSC0_IMULT 0x5 #define CONF_XOSC0_IPTAT 0x3 #elif CONF_XOSC0_FREQUENCY >= 8000000 #define CONF_XOSC0_CFDPRESC 0x3 #define CONF_XOSC0_IMULT 0x4 #define CONF_XOSC0_IPTAT 0x3 #endif // External Multipurpose Crystal Oscillator Configuration // Indicates whether configuration for XOSC1 is enabled or not // enable_xosc1 #ifndef CONF_XOSC1_CONFIG #define CONF_XOSC1_CONFIG 1 #endif // Frequency <8000000-48000000> // Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. // xosc1_frequency #ifndef CONF_XOSC_FREQUENCY #define CONF_XOSC1_FREQUENCY 12000000 #endif // External Multipurpose Crystal Oscillator Control // Oscillator enable // Indicates whether External Multipurpose Crystal Oscillator is enabled or not // xosc1_arch_enable #ifndef CONF_XOSC1_ENABLE #define CONF_XOSC1_ENABLE 1 #endif // Start-Up Time // <0x0=>31us // <0x1=>61us // <0x2=>122us // <0x3=>244us // <0x4=>488us // <0x5=>977us // <0x6=>1953us // <0x7=>3906us // <0x8=>7813us // <0x9=>15625us // <0xA=>31250us // <0xB=>62500us // <0xC=>125000us // <0xD=>250000us // <0xE=>500000us // <0xF=>1000000us // xosc1_arch_startup #ifndef CONF_XOSC1_STARTUP #define CONF_XOSC1_STARTUP 0 #endif // Clock Switch Back // Indicates whether Clock Switch Back is enabled or not // xosc1_arch_swben #ifndef CONF_XOSC1_SWBEN #define CONF_XOSC1_SWBEN 0 #endif // Clock Failure Detector // Indicates whether Clock Failure Detector is enabled or not // xosc1_arch_cfden #ifndef CONF_XOSC1_CFDEN #define CONF_XOSC1_CFDEN 0 #endif // Automatic Loop Control Enable // Indicates whether Automatic Loop Control is enabled or not // xosc1_arch_enalc #ifndef CONF_XOSC1_ENALC #define CONF_XOSC1_ENALC 0 #endif // Low Buffer Gain Enable // Indicates whether Low Buffer Gain is enabled or not // xosc1_arch_lowbufgain #ifndef CONF_XOSC1_LOWBUFGAIN #define CONF_XOSC1_LOWBUFGAIN 0 #endif // On Demand Control // Indicates whether On Demand Control is enabled or not // xosc1_arch_ondemand #ifndef CONF_XOSC1_ONDEMAND #define CONF_XOSC1_ONDEMAND 0 #endif // Run in Standby // Indicates whether Run in Standby is enabled or not // xosc1_arch_runstdby #ifndef CONF_XOSC1_RUNSTDBY #define CONF_XOSC1_RUNSTDBY 0 #endif // Crystal connected to XIN/XOUT Enable // Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not // xosc1_arch_xtalen #ifndef CONF_XOSC1_XTALEN #define CONF_XOSC1_XTALEN 1 #endif // // #if CONF_XOSC1_FREQUENCY >= 32000000 #define CONF_XOSC1_CFDPRESC 0x0 #define CONF_XOSC1_IMULT 0x7 #define CONF_XOSC1_IPTAT 0x3 #elif CONF_XOSC1_FREQUENCY >= 24000000 #define CONF_XOSC1_CFDPRESC 0x1 #define CONF_XOSC1_IMULT 0x6 #define CONF_XOSC1_IPTAT 0x3 #elif CONF_XOSC1_FREQUENCY >= 16000000 #define CONF_XOSC1_CFDPRESC 0x2 #define CONF_XOSC1_IMULT 0x5 #define CONF_XOSC1_IPTAT 0x3 #elif CONF_XOSC1_FREQUENCY >= 8000000 #define CONF_XOSC1_CFDPRESC 0x3 #define CONF_XOSC1_IMULT 0x4 #define CONF_XOSC1_IPTAT 0x3 #endif // DFLL Configuration // Indicates whether configuration for DFLL is enabled or not // enable_dfll #ifndef CONF_DFLL_CONFIG #define CONF_DFLL_CONFIG 0 #endif // Reference Clock Source // Generic clock generator 0 // Generic clock generator 1 // Generic clock generator 2 // Generic clock generator 3 // Generic clock generator 4 // Generic clock generator 5 // Generic clock generator 6 // Generic clock generator 7 // Generic clock generator 8 // Generic clock generator 9 // Generic clock generator 10 // Generic clock generator 11 // Select the clock source // dfll_ref_clock #ifndef CONF_DFLL_GCLK #define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK3_Val #endif // Digital Frequency Locked Loop Control // DFLL Enable // Indicates whether DFLL is enabled or not // dfll_arch_enable #ifndef CONF_DFLL_ENABLE #define CONF_DFLL_ENABLE 0 #endif // On Demand Control // Indicates whether On Demand Control is enabled or not // dfll_arch_ondemand #ifndef CONF_DFLL_ONDEMAND #define CONF_DFLL_ONDEMAND 0 #endif // Run in Standby // Indicates whether Run in Standby is enabled or not // dfll_arch_runstdby #ifndef CONF_DFLL_RUNSTDBY #define CONF_DFLL_RUNSTDBY 0 #endif // USB Clock Recovery Mode // Indicates whether USB Clock Recovery Mode is enabled or not // dfll_arch_usbcrm #ifndef CONF_DFLL_USBCRM #define CONF_DFLL_USBCRM 0 #endif // Wait Lock // Indicates whether Wait Lock is enabled or not // dfll_arch_waitlock #ifndef CONF_DFLL_WAITLOCK #define CONF_DFLL_WAITLOCK 1 #endif // Bypass Coarse Lock // Indicates whether Bypass Coarse Lock is enabled or not // dfll_arch_bplckc #ifndef CONF_DFLL_BPLCKC #define CONF_DFLL_BPLCKC 0 #endif // Quick Lock Disable // Indicates whether Quick Lock Disable is enabled or not // dfll_arch_qldis #ifndef CONF_DFLL_QLDIS #define CONF_DFLL_QLDIS 0 #endif // Chill Cycle Disable // Indicates whether Chill Cycle Disable is enabled or not // dfll_arch_ccdis #ifndef CONF_DFLL_CCDIS #define CONF_DFLL_CCDIS 0 #endif // Lose Lock After Wake // Indicates whether Lose Lock After Wake is enabled or not // dfll_arch_llaw #ifndef CONF_DFLL_LLAW #define CONF_DFLL_LLAW 0 #endif // Stable DFLL Frequency // Indicates whether Stable DFLL Frequency is enabled or not // dfll_arch_stable #ifndef CONF_DFLL_STABLE #define CONF_DFLL_STABLE 0 #endif // Operating Mode Selection // <0=>Open Loop Mode // <1=>Closed Loop Mode // dfll_mode #ifndef CONF_DFLL_MODE #define CONF_DFLL_MODE 0x0 #endif // Coarse Maximum Step <0x0-0x1F> // dfll_arch_cstep #ifndef CONF_DFLL_CSTEP #define CONF_DFLL_CSTEP 0x1 #endif // Fine Maximum Step <0x0-0xFF> // dfll_arch_fstep #ifndef CONF_DFLL_FSTEP #define CONF_DFLL_FSTEP 0x1 #endif // DFLL Multiply Factor <0x0-0xFFFF> // dfll_mul #ifndef CONF_DFLL_MUL #define CONF_DFLL_MUL 0x0 #endif // DFLL Calibration Overwrite // Indicates whether Overwrite Calibration value of DFLL // dfll_arch_calibration #ifndef CONF_DFLL_OVERWRITE_CALIBRATION #define CONF_DFLL_OVERWRITE_CALIBRATION 0 #endif // Coarse Value <0x0-0x3F> // dfll_arch_coarse #ifndef CONF_DFLL_COARSE #define CONF_DFLL_COARSE (0x1f / 4) #endif // Fine Value <0x0-0xFF> // dfll_arch_fine #ifndef CONF_DFLL_FINE #define CONF_DFLL_FINE (0x80) #endif // // // // FDPLL0 Configuration // Indicates whether configuration for FDPLL0 is enabled or not // enable_fdpll0 #ifndef CONF_FDPLL0_CONFIG #define CONF_FDPLL0_CONFIG 0 #endif // Reference Clock Source // 32kHz External Crystal Oscillator (XOSC32K) // External Crystal Oscillator 8-48MHz (XOSC0) // External Crystal Oscillator 8-48MHz (XOSC1) // Generic clock generator 0 // Generic clock generator 1 // Generic clock generator 2 // Generic clock generator 3 // Generic clock generator 4 // Generic clock generator 5 // Generic clock generator 6 // Generic clock generator 7 // Generic clock generator 8 // Generic clock generator 9 // Generic clock generator 10 // Generic clock generator 11 // Select the clock source. // fdpll0_ref_clock #ifndef CONF_FDPLL0_GCLK #define CONF_FDPLL0_GCLK GCLK_GENCTRL_SRC_XOSC32K #endif // Digital Phase Locked Loop Control // Enable // Indicates whether Digital Phase Locked Loop is enabled or not // fdpll0_arch_enable #ifndef CONF_FDPLL0_ENABLE #define CONF_FDPLL0_ENABLE 0 #endif // On Demand Control // Indicates whether On Demand Control is enabled or not // fdpll0_arch_ondemand #ifndef CONF_FDPLL0_ONDEMAND #define CONF_FDPLL0_ONDEMAND 0 #endif // Run in Standby // Indicates whether Run in Standby is enabled or not // fdpll0_arch_runstdby #ifndef CONF_FDPLL0_RUNSTDBY #define CONF_FDPLL0_RUNSTDBY 0 #endif // Loop Divider Ratio Fractional Part <0x0-0x1F> // Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register // fdpll0_ldrfrac #ifndef CONF_FDPLL0_LDRFRAC #define CONF_FDPLL0_LDRFRAC 0xd #endif // Loop Divider Ratio Integer Part <0x0-0x1FFF> // Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register // fdpll0_ldr #ifndef CONF_FDPLL0_LDR #define CONF_FDPLL0_LDR 0x5b7 #endif // Clock Divider <0x0-0x7FF> // This Clock divider is only for XOSC clock input to DPLL // fdpll0_clock_div #ifndef CONF_FDPLL0_DIV #define CONF_FDPLL0_DIV 0x0 #endif // DCO Filter Enable // Indicates whether DCO Filter Enable is enabled or not // fdpll0_arch_dcoen #ifndef CONF_FDPLL0_DCOEN #define CONF_FDPLL0_DCOEN 0 #endif // Sigma-Delta DCO Filter Selection <0x0-0x7> // fdpll0_clock_dcofilter #ifndef CONF_FDPLL0_DCOFILTER #define CONF_FDPLL0_DCOFILTER 0x0 #endif // Lock Bypass // Indicates whether Lock Bypass is enabled or not // fdpll0_arch_lbypass #ifndef CONF_FDPLL0_LBYPASS #define CONF_FDPLL0_LBYPASS 0 #endif // Lock Time // <0x0=>No time-out, automatic lock // <0x4=>The Time-out if no lock within 800 us // <0x5=>The Time-out if no lock within 900 us // <0x6=>The Time-out if no lock within 1 ms // <0x7=>The Time-out if no lock within 11 ms // fdpll0_arch_ltime #ifndef CONF_FDPLL0_LTIME #define CONF_FDPLL0_LTIME 0x0 #endif // Reference Clock Selection // <0x0=>GCLK clock reference // <0x1=>XOSC32K clock reference // <0x2=>XOSC0 clock reference // <0x3=>XOSC1 clock reference // fdpll0_arch_refclk #ifndef CONF_FDPLL0_REFCLK #define CONF_FDPLL0_REFCLK 0x1 #endif // Wake Up Fast // Indicates whether Wake Up Fast is enabled or not // fdpll0_arch_wuf #ifndef CONF_FDPLL0_WUF #define CONF_FDPLL0_WUF 0 #endif // Proportional Integral Filter Selection <0x0-0xF> // fdpll0_arch_filter #ifndef CONF_FDPLL0_FILTER #define CONF_FDPLL0_FILTER 0x0 #endif // // // FDPLL1 Configuration // Indicates whether configuration for FDPLL1 is enabled or not // enable_fdpll1 #ifndef CONF_FDPLL1_CONFIG #define CONF_FDPLL1_CONFIG 0 #endif // Reference Clock Source // 32kHz External Crystal Oscillator (XOSC32K) // External Crystal Oscillator 8-48MHz (XOSC0) // External Crystal Oscillator 8-48MHz (XOSC1) // Generic clock generator 0 // Generic clock generator 1 // Generic clock generator 2 // Generic clock generator 3 // Generic clock generator 4 // Generic clock generator 5 // Generic clock generator 6 // Generic clock generator 7 // Generic clock generator 8 // Generic clock generator 9 // Generic clock generator 10 // Generic clock generator 11 // Select the clock source. // fdpll1_ref_clock #ifndef CONF_FDPLL1_GCLK #define CONF_FDPLL1_GCLK GCLK_GENCTRL_SRC_XOSC32K #endif // Digital Phase Locked Loop Control // Enable // Indicates whether Digital Phase Locked Loop is enabled or not // fdpll1_arch_enable #ifndef CONF_FDPLL1_ENABLE #define CONF_FDPLL1_ENABLE 0 #endif // On Demand Control // Indicates whether On Demand Control is enabled or not // fdpll1_arch_ondemand #ifndef CONF_FDPLL1_ONDEMAND #define CONF_FDPLL1_ONDEMAND 0 #endif // Run in Standby // Indicates whether Run in Standby is enabled or not // fdpll1_arch_runstdby #ifndef CONF_FDPLL1_RUNSTDBY #define CONF_FDPLL1_RUNSTDBY 0 #endif // Loop Divider Ratio Fractional Part <0x0-0x1F> // Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register // fdpll1_ldrfrac #ifndef CONF_FDPLL1_LDRFRAC #define CONF_FDPLL1_LDRFRAC 0xd #endif // Loop Divider Ratio Integer Part <0x0-0x1FFF> // Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register // fdpll1_ldr #ifndef CONF_FDPLL1_LDR #define CONF_FDPLL1_LDR 0x5b7 #endif // Clock Divider <0x0-0x7FF> // This Clock divider is only for XOSC clock input to DPLL // fdpll1_clock_div #ifndef CONF_FDPLL1_DIV #define CONF_FDPLL1_DIV 0x0 #endif // DCO Filter Enable // Indicates whether DCO Filter Enable is enabled or not // fdpll1_arch_dcoen #ifndef CONF_FDPLL1_DCOEN #define CONF_FDPLL1_DCOEN 0 #endif // Sigma-Delta DCO Filter Selection <0x0-0x7> // fdpll1_clock_dcofilter #ifndef CONF_FDPLL1_DCOFILTER #define CONF_FDPLL1_DCOFILTER 0x0 #endif // Lock Bypass // Indicates whether Lock Bypass is enabled or not // fdpll1_arch_lbypass #ifndef CONF_FDPLL1_LBYPASS #define CONF_FDPLL1_LBYPASS 0 #endif // Lock Time // <0x0=>No time-out, automatic lock // <0x4=>The Time-out if no lock within 800 us // <0x5=>The Time-out if no lock within 900 us // <0x6=>The Time-out if no lock within 1 ms // <0x7=>The Time-out if no lock within 11 ms // fdpll1_arch_ltime #ifndef CONF_FDPLL1_LTIME #define CONF_FDPLL1_LTIME 0x0 #endif // Reference Clock Selection // <0x0=>GCLK clock reference // <0x1=>XOSC32K clock reference // <0x2=>XOSC0 clock reference // <0x3=>XOSC1 clock reference // fdpll1_arch_refclk #ifndef CONF_FDPLL1_REFCLK #define CONF_FDPLL1_REFCLK 0x1 #endif // Wake Up Fast // Indicates whether Wake Up Fast is enabled or not // fdpll1_arch_wuf #ifndef CONF_FDPLL1_WUF #define CONF_FDPLL1_WUF 0 #endif // Proportional Integral Filter Selection <0x0-0xF> // fdpll1_arch_filter #ifndef CONF_FDPLL1_FILTER #define CONF_FDPLL1_FILTER 0x0 #endif // // // <<< end of configuration section >>> #endif // HPL_OSCCTRL_CONFIG_H