eP-GFX.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .text 000010fc 00000000 00000000 00010000 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 1 .relocate 00000008 20000000 000010fc 00020000 2**1 CONTENTS, ALLOC, LOAD, DATA 2 .bkupram 00000000 47000000 47000000 00020008 2**0 CONTENTS 3 .qspi 00000000 04000000 04000000 00020008 2**0 CONTENTS 4 .bss 000000d0 20000008 00001108 00020008 2**3 ALLOC 5 .stack 0000c000 200000d8 000011d8 00020008 2**0 ALLOC 6 .ARM.attributes 0000002e 00000000 00000000 00020008 2**0 CONTENTS, READONLY 7 .comment 0000001e 00000000 00000000 00020036 2**0 CONTENTS, READONLY 8 .debug_info 000291fc 00000000 00000000 00020054 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 9 .debug_abbrev 00003708 00000000 00000000 00049250 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 10 .debug_loc 0000d0fa 00000000 00000000 0004c958 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 11 .debug_aranges 00000c78 00000000 00000000 00059a52 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 12 .debug_ranges 00001df0 00000000 00000000 0005a6ca 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_macro 0000ec09 00000000 00000000 0005c4ba 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_line 000172ea 00000000 00000000 0006b0c3 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_str 001227b8 00000000 00000000 000823ad 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_frame 000023ec 00000000 00000000 001a4b68 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 00000000 : 0: d8 c0 00 20 55 07 00 00 53 07 00 00 53 07 00 00 ... U...S...S... 10: 53 07 00 00 53 07 00 00 53 07 00 00 00 00 00 00 S...S...S....... ... 2c: 53 07 00 00 53 07 00 00 00 00 00 00 53 07 00 00 S...S.......S... 3c: 53 07 00 00 53 07 00 00 53 07 00 00 53 07 00 00 S...S...S...S... 4c: 53 07 00 00 53 07 00 00 53 07 00 00 53 07 00 00 S...S...S...S... 5c: 53 07 00 00 53 07 00 00 53 07 00 00 53 07 00 00 S...S...S...S... 6c: 95 08 00 00 53 07 00 00 53 07 00 00 53 07 00 00 ....S...S...S... 7c: 53 07 00 00 53 07 00 00 53 07 00 00 53 07 00 00 S...S...S...S... 8c: 53 07 00 00 53 07 00 00 53 07 00 00 53 07 00 00 S...S...S...S... 9c: 53 07 00 00 53 07 00 00 53 07 00 00 53 07 00 00 S...S...S...S... ac: 53 07 00 00 53 07 00 00 53 07 00 00 53 07 00 00 S...S...S...S... bc: 53 07 00 00 53 07 00 00 53 07 00 00 53 07 00 00 S...S...S...S... cc: 53 07 00 00 53 07 00 00 53 07 00 00 53 07 00 00 S...S...S...S... dc: 53 07 00 00 53 07 00 00 53 07 00 00 00 00 00 00 S...S...S....... ... f4: 19 07 00 00 53 07 00 00 53 07 00 00 53 07 00 00 ....S...S...S... 104: 53 07 00 00 53 07 00 00 53 07 00 00 53 07 00 00 S...S...S...S... 114: 53 07 00 00 53 07 00 00 53 07 00 00 53 07 00 00 S...S...S...S... 124: 53 07 00 00 53 07 00 00 53 07 00 00 53 07 00 00 S...S...S...S... 134: 53 07 00 00 53 07 00 00 53 07 00 00 53 07 00 00 S...S...S...S... 144: 53 07 00 00 53 07 00 00 53 07 00 00 53 07 00 00 S...S...S...S... 154: 53 07 00 00 53 07 00 00 53 07 00 00 53 07 00 00 S...S...S...S... 164: 53 07 00 00 53 07 00 00 53 07 00 00 53 07 00 00 S...S...S...S... 174: 53 07 00 00 53 07 00 00 53 07 00 00 53 07 00 00 S...S...S...S... 184: 53 07 00 00 53 07 00 00 53 07 00 00 53 07 00 00 S...S...S...S... 194: 53 07 00 00 53 07 00 00 53 07 00 00 53 07 00 00 S...S...S...S... 1a4: 53 07 00 00 53 07 00 00 53 07 00 00 53 07 00 00 S...S...S...S... 1b4: 53 07 00 00 53 07 00 00 53 07 00 00 53 07 00 00 S...S...S...S... 1c4: 53 07 00 00 53 07 00 00 53 07 00 00 53 07 00 00 S...S...S...S... 1d4: 53 07 00 00 53 07 00 00 53 07 00 00 53 07 00 00 S...S...S...S... 1e4: 53 07 00 00 53 07 00 00 53 07 00 00 53 07 00 00 S...S...S...S... 1f4: 53 07 00 00 53 07 00 00 53 07 00 00 53 07 00 00 S...S...S...S... 204: 53 07 00 00 53 07 00 00 53 07 00 00 53 07 00 00 S...S...S...S... 214: 53 07 00 00 53 07 00 00 53 07 00 00 53 07 00 00 S...S...S...S... 224: 53 07 00 00 53 07 00 00 53 07 00 00 53 07 00 00 S...S...S...S... 234: 53 07 00 00 53 07 00 00 53 07 00 00 53 07 00 00 S...S...S...S... 244: 53 07 00 00 53 07 00 00 53 07 00 00 53 07 00 00 S...S...S...S... 254: 53 07 00 00 53 07 00 00 53 07 00 00 53 07 00 00 S...S...S...S... 00000264 <__do_global_dtors_aux>: 264: b510 push {r4, lr} 266: 4c05 ldr r4, [pc, #20] ; (27c <__do_global_dtors_aux+0x18>) 268: 7823 ldrb r3, [r4, #0] 26a: b933 cbnz r3, 27a <__do_global_dtors_aux+0x16> 26c: 4b04 ldr r3, [pc, #16] ; (280 <__do_global_dtors_aux+0x1c>) 26e: b113 cbz r3, 276 <__do_global_dtors_aux+0x12> 270: 4804 ldr r0, [pc, #16] ; (284 <__do_global_dtors_aux+0x20>) 272: f3af 8000 nop.w 276: 2301 movs r3, #1 278: 7023 strb r3, [r4, #0] 27a: bd10 pop {r4, pc} 27c: 20000008 .word 0x20000008 280: 00000000 .word 0x00000000 284: 000010fc .word 0x000010fc 00000288 : 288: b508 push {r3, lr} 28a: 4b03 ldr r3, [pc, #12] ; (298 ) 28c: b11b cbz r3, 296 28e: 4903 ldr r1, [pc, #12] ; (29c ) 290: 4803 ldr r0, [pc, #12] ; (2a0 ) 292: f3af 8000 nop.w 296: bd08 pop {r3, pc} 298: 00000000 .word 0x00000000 29c: 2000000c .word 0x2000000c 2a0: 000010fc .word 0x000010fc 000002a4 : } /** \brief Initialize Calendar */ int32_t calendar_init(struct calendar_descriptor *const calendar, const void *hw) { 2a4: b538 push {r3, r4, r5, lr} int32_t ret = 0; /* Sanity check arguments */ ASSERT(calendar); 2a6: 4604 mov r4, r0 2a8: 3800 subs r0, #0 2aa: 4b0c ldr r3, [pc, #48] ; (2dc ) { 2ac: 460d mov r5, r1 ASSERT(calendar); 2ae: bf18 it ne 2b0: 2001 movne r0, #1 2b2: 490b ldr r1, [pc, #44] ; (2e0 ) 2b4: f44f 72e0 mov.w r2, #448 ; 0x1c0 2b8: 4798 blx r3 if (calendar->device.hw == hw) { 2ba: 6823 ldr r3, [r4, #0] 2bc: 42ab cmp r3, r5 2be: d008 beq.n 2d2 /* Already initialized with current configuration */ return ERR_NONE; } else if (calendar->device.hw != NULL) { 2c0: b94b cbnz r3, 2d6 /* Initialized with another configuration */ return ERR_ALREADY_INITIALIZED; } calendar->device.hw = (void *)hw; ret = _calendar_init(&calendar->device); 2c2: 4b08 ldr r3, [pc, #32] ; (2e4 ) calendar->device.hw = (void *)hw; 2c4: 6025 str r5, [r4, #0] ret = _calendar_init(&calendar->device); 2c6: 4620 mov r0, r4 2c8: 4798 blx r3 calendar->base_year = DEFAULT_BASE_YEAR; 2ca: f240 73b2 movw r3, #1970 ; 0x7b2 2ce: 61a3 str r3, [r4, #24] return ret; } 2d0: bd38 pop {r3, r4, r5, pc} return ERR_NONE; 2d2: 2000 movs r0, #0 2d4: e7fc b.n 2d0 return ERR_ALREADY_INITIALIZED; 2d6: f06f 0011 mvn.w r0, #17 2da: e7f9 b.n 2d0 2dc: 000004b9 .word 0x000004b9 2e0: 00000fdc .word 0x00000fdc 2e4: 00000819 .word 0x00000819 000002e8 : } void sd_mmc_stack_init(void) { sd_mmc_init(&IO_BUS, SDMMC_cd, SDMMC_wp); 2e8: 4a02 ldr r2, [pc, #8] ; (2f4 ) 2ea: 4803 ldr r0, [pc, #12] ; (2f8 ) 2ec: 4b03 ldr r3, [pc, #12] ; (2fc ) 2ee: 1d11 adds r1, r2, #4 2f0: 4718 bx r3 2f2: bf00 nop 2f4: 20000000 .word 0x20000000 2f8: 200000c0 .word 0x200000c0 2fc: 00000301 .word 0x00000301 00000300 : uint8_t addr_cis[4]; /* Read CIS area address in CCCR area */ addr_old = SDIO_CCCR_CIS_PTR; for (i = 0; i < 4; i++) { sdio_cmd52(SDIO_CMD52_READ_FLAG, SDIO_CIA, addr_old, 0, &addr_cis[i]); 300: b510 push {r4, lr} 302: 4b04 ldr r3, [pc, #16] ; (314 ) 304: 2404 movs r4, #4 addr_old++; 306: 769c strb r4, [r3, #26] sdio_cmd52(SDIO_CMD52_READ_FLAG, SDIO_CIA, addr_old, 0, &addr_cis[i]); 308: 24ff movs r4, #255 ; 0xff for (i = 0; i < 4; i++) { 30a: 711c strb r4, [r3, #4] 30c: e9c3 0102 strd r0, r1, [r3, #8] 310: 635a str r2, [r3, #52] ; 0x34 } addr_old = addr_cis[0] + (addr_cis[1] << 8) + (addr_cis[2] << 16) + (addr_cis[3] << 24); 312: bd10 pop {r4, pc} 314: 20000024 .word 0x20000024 00000318 : ASSERT(spi); spi->func = (struct _spi_m_sync_hpl_interface *)func; } int32_t spi_m_sync_init(struct spi_m_sync_descriptor *spi, void *const hw) { 318: b538 push {r3, r4, r5, lr} 31a: 460d mov r5, r1 int32_t rc = 0; ASSERT(spi && hw); 31c: 4604 mov r4, r0 31e: b110 cbz r0, 326 320: 1e08 subs r0, r1, #0 322: bf18 it ne 324: 2001 movne r0, #1 326: 490a ldr r1, [pc, #40] ; (350 ) 328: 4b0a ldr r3, [pc, #40] ; (354 ) 32a: 2241 movs r2, #65 ; 0x41 32c: 4798 blx r3 spi->dev.prvt = (void *)hw; 32e: 4620 mov r0, r4 rc = _spi_m_sync_init(&spi->dev, hw); 330: 4b09 ldr r3, [pc, #36] ; (358 ) spi->dev.prvt = (void *)hw; 332: f840 5f04 str.w r5, [r0, #4]! rc = _spi_m_sync_init(&spi->dev, hw); 336: 4629 mov r1, r5 338: 4798 blx r3 if (rc < 0) { 33a: 2800 cmp r0, #0 33c: db07 blt.n 34e return rc; } spi->flags = SPI_DEACTIVATE_NEXT; 33e: f44f 4300 mov.w r3, #32768 ; 0x8000 342: 82a3 strh r3, [r4, #20] spi->io.read = _spi_m_sync_io_read; 344: 4b05 ldr r3, [pc, #20] ; (35c ) 346: 6123 str r3, [r4, #16] spi->io.write = _spi_m_sync_io_write; 348: 4b05 ldr r3, [pc, #20] ; (360 ) 34a: 60e3 str r3, [r4, #12] return ERR_NONE; 34c: 2000 movs r0, #0 } 34e: bd38 pop {r3, r4, r5, pc} 350: 00000ff6 .word 0x00000ff6 354: 000004b9 .word 0x000004b9 358: 00000d55 .word 0x00000d55 35c: 000003d9 .word 0x000003d9 360: 000003a1 .word 0x000003a1 00000364 : return spi_m_sync_transfer(spi, &xfer); } int32_t spi_m_sync_transfer(struct spi_m_sync_descriptor *const spi, const struct spi_xfer *p_xfer) { 364: b530 push {r4, r5, lr} 366: 460c mov r4, r1 368: b085 sub sp, #20 struct spi_msg msg; ASSERT(spi && p_xfer); 36a: 4605 mov r5, r0 36c: b110 cbz r0, 374 36e: 1e08 subs r0, r1, #0 370: bf18 it ne 372: 2001 movne r0, #1 374: 22b4 movs r2, #180 ; 0xb4 376: 4907 ldr r1, [pc, #28] ; (394 ) 378: 4b07 ldr r3, [pc, #28] ; (398 ) 37a: 4798 blx r3 msg.txbuf = p_xfer->txbuf; 37c: 6823 ldr r3, [r4, #0] 37e: 9301 str r3, [sp, #4] msg.rxbuf = p_xfer->rxbuf; 380: 6863 ldr r3, [r4, #4] 382: 9302 str r3, [sp, #8] msg.size = p_xfer->size; 384: 68a3 ldr r3, [r4, #8] 386: 9303 str r3, [sp, #12] return _spi_m_sync_trans(&spi->dev, &msg); 388: a901 add r1, sp, #4 38a: 4b04 ldr r3, [pc, #16] ; (39c ) 38c: 1d28 adds r0, r5, #4 38e: 4798 blx r3 } 390: b005 add sp, #20 392: bd30 pop {r4, r5, pc} 394: 00000ff6 .word 0x00000ff6 398: 000004b9 .word 0x000004b9 39c: 00000e89 .word 0x00000e89 000003a0 <_spi_m_sync_io_write>: { 3a0: b57f push {r0, r1, r2, r3, r4, r5, r6, lr} ASSERT(io); 3a2: 4604 mov r4, r0 3a4: 3800 subs r0, #0 3a6: bf18 it ne 3a8: 2001 movne r0, #1 { 3aa: 460e mov r6, r1 3ac: 4615 mov r5, r2 ASSERT(io); 3ae: 4907 ldr r1, [pc, #28] ; (3cc <_spi_m_sync_io_write+0x2c>) 3b0: 4b07 ldr r3, [pc, #28] ; (3d0 <_spi_m_sync_io_write+0x30>) 3b2: 22a4 movs r2, #164 ; 0xa4 3b4: 4798 blx r3 xfer.rxbuf = 0; 3b6: 2300 movs r3, #0 xfer.txbuf = (uint8_t *)buf; 3b8: e9cd 6301 strd r6, r3, [sp, #4] return spi_m_sync_transfer(spi, &xfer); 3bc: a901 add r1, sp, #4 3be: 4b05 ldr r3, [pc, #20] ; (3d4 <_spi_m_sync_io_write+0x34>) xfer.size = length; 3c0: 9503 str r5, [sp, #12] return spi_m_sync_transfer(spi, &xfer); 3c2: f1a4 000c sub.w r0, r4, #12 3c6: 4798 blx r3 } 3c8: b004 add sp, #16 3ca: bd70 pop {r4, r5, r6, pc} 3cc: 00000ff6 .word 0x00000ff6 3d0: 000004b9 .word 0x000004b9 3d4: 00000365 .word 0x00000365 000003d8 <_spi_m_sync_io_read>: { 3d8: b57f push {r0, r1, r2, r3, r4, r5, r6, lr} ASSERT(io); 3da: 4604 mov r4, r0 3dc: 3800 subs r0, #0 3de: bf18 it ne 3e0: 2001 movne r0, #1 { 3e2: 460e mov r6, r1 3e4: 4615 mov r5, r2 ASSERT(io); 3e6: 4907 ldr r1, [pc, #28] ; (404 <_spi_m_sync_io_read+0x2c>) 3e8: 4b07 ldr r3, [pc, #28] ; (408 <_spi_m_sync_io_read+0x30>) 3ea: 2288 movs r2, #136 ; 0x88 3ec: 4798 blx r3 xfer.txbuf = 0; 3ee: 2300 movs r3, #0 3f0: 9301 str r3, [sp, #4] return spi_m_sync_transfer(spi, &xfer); 3f2: a901 add r1, sp, #4 3f4: 4b05 ldr r3, [pc, #20] ; (40c <_spi_m_sync_io_read+0x34>) xfer.rxbuf = buf; 3f6: 9602 str r6, [sp, #8] return spi_m_sync_transfer(spi, &xfer); 3f8: f1a4 000c sub.w r0, r4, #12 xfer.size = length; 3fc: 9503 str r5, [sp, #12] return spi_m_sync_transfer(spi, &xfer); 3fe: 4798 blx r3 } 400: b004 add sp, #16 402: bd70 pop {r4, r5, r6, pc} 404: 00000ff6 .word 0x00000ff6 408: 000004b9 .word 0x000004b9 40c: 00000365 .word 0x00000365 00000410 : /** * \brief Initialize MCI low level driver. */ int32_t mci_sync_init(struct mci_sync_desc *mci, void *hw) { 410: b570 push {r4, r5, r6, lr} 412: 460d mov r5, r1 ASSERT(mci && hw); 414: 4604 mov r4, r0 416: b110 cbz r0, 41e 418: 1e08 subs r0, r1, #0 41a: bf18 it ne 41c: 2001 movne r0, #1 41e: 4905 ldr r1, [pc, #20] ; (434 ) 420: 4b05 ldr r3, [pc, #20] ; (438 ) 422: 2231 movs r2, #49 ; 0x31 424: 4798 blx r3 return _mci_sync_init(&mci->device, hw); 426: 4629 mov r1, r5 428: 4620 mov r0, r4 42a: 4b04 ldr r3, [pc, #16] ; (43c ) } 42c: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} return _mci_sync_init(&mci->device, hw); 430: 4718 bx r3 432: bf00 nop 434: 00001012 .word 0x00001012 438: 000004b9 .word 0x000004b9 43c: 00000599 .word 0x00000599 00000440 <_init_chip>: } static inline void hri_nvmctrl_set_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) { NVMCTRL_CRITICAL_SECTION_ENTER(); ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_RWS(mask); 440: 4a09 ldr r2, [pc, #36] ; (468 <_init_chip+0x28>) 442: 8813 ldrh r3, [r2, #0] /** * \brief Initialize the hardware abstraction layer */ void _init_chip(void) { 444: b510 push {r4, lr} 446: b29b uxth r3, r3 448: 8013 strh r3, [r2, #0] hri_nvmctrl_set_CTRLA_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE); _osc32kctrl_init_sources(); 44a: 4b08 ldr r3, [pc, #32] ; (46c <_init_chip+0x2c>) 44c: 4798 blx r3 _oscctrl_init_sources(); 44e: 4b08 ldr r3, [pc, #32] ; (470 <_init_chip+0x30>) 450: 4798 blx r3 _mclk_init(); 452: 4b08 ldr r3, [pc, #32] ; (474 <_init_chip+0x34>) 454: 4798 blx r3 #if _GCLK_INIT_1ST _gclk_init_generators_by_fref(_GCLK_INIT_1ST); #endif _oscctrl_init_referenced_generators(); 456: 4b08 ldr r3, [pc, #32] ; (478 <_init_chip+0x38>) 458: 4798 blx r3 #endif #if CONF_CMCC_ENABLE cache_init(); #endif } 45a: e8bd 4010 ldmia.w sp!, {r4, lr} _gclk_init_generators_by_fref(_GCLK_INIT_LAST); 45e: 4b07 ldr r3, [pc, #28] ; (47c <_init_chip+0x3c>) 460: f640 70ff movw r0, #4095 ; 0xfff 464: 4718 bx r3 466: bf00 nop 468: 41004000 .word 0x41004000 46c: 000007f1 .word 0x000007f1 470: 000004c1 .word 0x000004c1 474: 0000070d .word 0x0000070d 478: 000004d9 .word 0x000004d9 47c: 00000481 .word 0x00000481 00000480 <_gclk_init_generators_by_fref>: void _gclk_init_generators_by_fref(uint32_t bm) { #if CONF_GCLK_GENERATOR_0_CONFIG == 1 if (bm & (1ul << 0)) { 480: 07c2 lsls r2, r0, #31 482: d507 bpl.n 494 <_gclk_init_generators_by_fref+0x14> } static inline void hri_gclk_write_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) { GCLK_CRITICAL_SECTION_ENTER(); ((Gclk *)hw)->GENCTRL[index].reg = data; 484: 4b09 ldr r3, [pc, #36] ; (4ac <_gclk_init_generators_by_fref+0x2c>) 486: 4a0a ldr r2, [pc, #40] ; (4b0 <_gclk_init_generators_by_fref+0x30>) 488: 621a str r2, [r3, #32] while (((Gclk *)hw)->SYNCBUSY.reg & reg) { 48a: f643 72fd movw r2, #16381 ; 0x3ffd 48e: 6859 ldr r1, [r3, #4] 490: 4211 tst r1, r2 492: d1fc bne.n 48e <_gclk_init_generators_by_fref+0xe> | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE); } #endif #if CONF_GCLK_GENERATOR_3_CONFIG == 1 if (bm & (1ul << 3)) { 494: 0703 lsls r3, r0, #28 496: d507 bpl.n 4a8 <_gclk_init_generators_by_fref+0x28> ((Gclk *)hw)->GENCTRL[index].reg = data; 498: 4b04 ldr r3, [pc, #16] ; (4ac <_gclk_init_generators_by_fref+0x2c>) 49a: 4a06 ldr r2, [pc, #24] ; (4b4 <_gclk_init_generators_by_fref+0x34>) 49c: 62da str r2, [r3, #44] ; 0x2c while (((Gclk *)hw)->SYNCBUSY.reg & reg) { 49e: f643 72fd movw r2, #16381 ; 0x3ffd 4a2: 6859 ldr r1, [r3, #4] 4a4: 4211 tst r1, r2 4a6: d1fc bne.n 4a2 <_gclk_init_generators_by_fref+0x22> | (CONF_GCLK_GEN_11_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_11_OE << GCLK_GENCTRL_OE_Pos) | (CONF_GCLK_GEN_11_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_11_IDC << GCLK_GENCTRL_IDC_Pos) | (CONF_GCLK_GENERATOR_11_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_11_SOURCE); } #endif } 4a8: 4770 bx lr 4aa: bf00 nop 4ac: 40001c00 .word 0x40001c00 4b0: 00010101 .word 0x00010101 4b4: 00010105 .word 0x00010105 000004b8 : /** * \brief Assert function */ void assert(const bool condition, const char *const file, const int line) { if (!(condition)) { 4b8: b900 cbnz r0, 4bc __asm("BKPT #0"); 4ba: be00 bkpt 0x0000 } (void)file; (void)line; } 4bc: 4770 bx lr ... 000004c0 <_oscctrl_init_sources>: } static inline void hri_oscctrl_write_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t data) { OSCCTRL_CRITICAL_SECTION_ENTER(); ((Oscctrl *)hw)->XOSCCTRL[index].reg = data; 4c0: 4b03 ldr r3, [pc, #12] ; (4d0 <_oscctrl_init_sources+0x10>) 4c2: 4a04 ldr r2, [pc, #16] ; (4d4 <_oscctrl_init_sources+0x14>) 4c4: 619a str r2, [r3, #24] return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCRDY1) >> OSCCTRL_STATUS_XOSCRDY1_Pos; 4c6: 691a ldr r2, [r3, #16] | (CONF_XOSC1_XTALEN << OSCCTRL_XOSCCTRL_XTALEN_Pos) | (CONF_XOSC1_ENABLE << OSCCTRL_XOSCCTRL_ENABLE_Pos)); #endif #if CONF_XOSC1_CONFIG == 1 #if CONF_XOSC1_ENABLE == 1 while (!hri_oscctrl_get_STATUS_XOSCRDY1_bit(hw)) 4c8: 0792 lsls r2, r2, #30 4ca: d5fc bpl.n 4c6 <_oscctrl_init_sources+0x6> hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(hw, 1); #endif #endif (void)hw; } 4cc: 4770 bx lr 4ce: bf00 nop 4d0: 40001000 .word 0x40001000 4d4: 03002606 .word 0x03002606 000004d8 <_oscctrl_init_referenced_generators>: tmp = ((Gclk *)hw)->GENCTRL[index].reg; 4d8: 4a2c ldr r2, [pc, #176] ; (58c <_oscctrl_init_referenced_generators+0xb4>) 4da: 6a13 ldr r3, [r2, #32] tmp &= ~GCLK_GENCTRL_SRC_Msk; 4dc: f023 030f bic.w r3, r3, #15 tmp |= GCLK_GENCTRL_SRC(data); 4e0: f043 0304 orr.w r3, r3, #4 ((Gclk *)hw)->GENCTRL[index].reg = tmp; 4e4: 6213 str r3, [r2, #32] while (((Gclk *)hw)->SYNCBUSY.reg & reg) { 4e6: f643 73fd movw r3, #16381 ; 0x3ffd 4ea: 6851 ldr r1, [r2, #4] 4ec: 4219 tst r1, r3 4ee: d1fc bne.n 4ea <_oscctrl_init_referenced_generators+0x12> return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL0) >> GCLK_SYNCBUSY_GENCTRL0_Pos; 4f0: 6853 ldr r3, [r2, #4] { void *hw = (void *)OSCCTRL; #if CONF_DFLL_CONFIG == 1 hri_gclk_write_GENCTRL_SRC_bf(GCLK, 0, GCLK_GENCTRL_SRC_OSCULP32K); while (hri_gclk_get_SYNCBUSY_GENCTRL0_bit(GCLK)) 4f2: 0758 lsls r0, r3, #29 4f4: f3c3 0180 ubfx r1, r3, #2, #1 4f8: d4fa bmi.n 4f0 <_oscctrl_init_referenced_generators+0x18> } static inline void hri_oscctrl_write_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t data) { OSCCTRL_CRITICAL_SECTION_ENTER(); ((Oscctrl *)hw)->DFLLCTRLA.reg = data; 4fa: 4b25 ldr r3, [pc, #148] ; (590 <_oscctrl_init_referenced_generators+0xb8>) } static inline void hri_oscctrl_write_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t data) { OSCCTRL_CRITICAL_SECTION_ENTER(); ((Oscctrl *)hw)->DFLLMUL.reg = data; 4fc: 4a25 ldr r2, [pc, #148] ; (594 <_oscctrl_init_referenced_generators+0xbc>) ((Oscctrl *)hw)->DFLLCTRLA.reg = data; 4fe: 7719 strb r1, [r3, #28] ((Oscctrl *)hw)->DFLLMUL.reg = data; 500: 629a str r2, [r3, #40] ; 0x28 } static inline bool hri_oscctrl_get_DFLLSYNC_DFLLMUL_bit(const void *const hw) { uint8_t tmp; tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; 502: f893 202c ldrb.w r2, [r3, #44] ; 0x2c #endif hri_oscctrl_write_DFLLMUL_reg(hw, OSCCTRL_DFLLMUL_CSTEP(CONF_DFLL_CSTEP) | OSCCTRL_DFLLMUL_FSTEP(CONF_DFLL_FSTEP) | OSCCTRL_DFLLMUL_MUL(CONF_DFLL_MUL)); while (hri_oscctrl_get_DFLLSYNC_DFLLMUL_bit(hw)) 506: f3c2 1100 ubfx r1, r2, #4, #1 50a: 06d2 lsls r2, r2, #27 50c: d4f9 bmi.n 502 <_oscctrl_init_referenced_generators+0x2a> ((Oscctrl *)hw)->DFLLCTRLB.reg = data; 50e: f883 1020 strb.w r1, [r3, #32] tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; 512: 4b1f ldr r3, [pc, #124] ; (590 <_oscctrl_init_referenced_generators+0xb8>) 514: f893 202c ldrb.w r2, [r3, #44] ; 0x2c ; hri_oscctrl_write_DFLLCTRLB_reg(hw, 0); while (hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(hw)) 518: 0750 lsls r0, r2, #29 51a: d4fb bmi.n 514 <_oscctrl_init_referenced_generators+0x3c> ((Oscctrl *)hw)->DFLLCTRLA.reg = data; 51c: 2202 movs r2, #2 51e: 771a strb r2, [r3, #28] tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; 520: 4b1b ldr r3, [pc, #108] ; (590 <_oscctrl_init_referenced_generators+0xb8>) 522: f893 202c ldrb.w r2, [r3, #44] ; 0x2c ; tmp = (CONF_DFLL_RUNSTDBY << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos) | OSCCTRL_DFLLCTRLA_ENABLE; hri_oscctrl_write_DFLLCTRLA_reg(hw, tmp); while (hri_oscctrl_get_DFLLSYNC_ENABLE_bit(hw)) 526: 0791 lsls r1, r2, #30 528: d4fb bmi.n 522 <_oscctrl_init_referenced_generators+0x4a> return ((Oscctrl *)hw)->DFLLVAL.reg; 52a: 6a5a ldr r2, [r3, #36] ; 0x24 ((Oscctrl *)hw)->DFLLVAL.reg = data; 52c: 625a str r2, [r3, #36] ; 0x24 tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; 52e: 4b18 ldr r3, [pc, #96] ; (590 <_oscctrl_init_referenced_generators+0xb8>) 530: f893 202c ldrb.w r2, [r3, #44] ; 0x2c #if CONF_DFLL_OVERWRITE_CALIBRATION == 1 hri_oscctrl_write_DFLLVAL_reg(hw, OSCCTRL_DFLLVAL_COARSE(CONF_DFLL_COARSE) | OSCCTRL_DFLLVAL_FINE(CONF_DFLL_FINE)); #endif hri_oscctrl_write_DFLLVAL_reg(hw, hri_oscctrl_read_DFLLVAL_reg(hw)); while (hri_oscctrl_get_DFLLSYNC_DFLLVAL_bit(hw)) 534: 0712 lsls r2, r2, #28 536: d4fb bmi.n 530 <_oscctrl_init_referenced_generators+0x58> ((Oscctrl *)hw)->DFLLCTRLB.reg = data; 538: 229f movs r2, #159 ; 0x9f 53a: f883 2020 strb.w r2, [r3, #32] tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; 53e: 4b14 ldr r3, [pc, #80] ; (590 <_oscctrl_init_referenced_generators+0xb8>) 540: f893 202c ldrb.w r2, [r3, #44] ; 0x2c tmp = (CONF_DFLL_WAITLOCK << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos) | (CONF_DFLL_BPLCKC << OSCCTRL_DFLLCTRLB_BPLCKC_Pos) | (CONF_DFLL_QLDIS << OSCCTRL_DFLLCTRLB_QLDIS_Pos) | (CONF_DFLL_CCDIS << OSCCTRL_DFLLCTRLB_CCDIS_Pos) | (CONF_DFLL_USBCRM << OSCCTRL_DFLLCTRLB_USBCRM_Pos) | (CONF_DFLL_LLAW << OSCCTRL_DFLLCTRLB_LLAW_Pos) | (CONF_DFLL_STABLE << OSCCTRL_DFLLCTRLB_STABLE_Pos) | (CONF_DFLL_MODE << OSCCTRL_DFLLCTRLB_MODE_Pos) | 0; hri_oscctrl_write_DFLLCTRLB_reg(hw, tmp); while (hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(hw)) 544: 0750 lsls r0, r2, #29 546: d4fb bmi.n 540 <_oscctrl_init_referenced_generators+0x68> tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; 548: f893 2020 ldrb.w r2, [r3, #32] (CONF_FDPLL1_RUNSTDBY << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos) | (CONF_FDPLL1_ENABLE << OSCCTRL_DPLLCTRLA_ENABLE_Pos)); #endif #if CONF_DFLL_CONFIG == 1 if (hri_oscctrl_get_DFLLCTRLB_MODE_bit(hw)) { 54c: 07d1 lsls r1, r2, #31 54e: d519 bpl.n 584 <_oscctrl_init_referenced_generators+0xac> tmp = ((Oscctrl *)hw)->STATUS.reg; 550: 691a ldr r2, [r3, #16] tmp &= mask; 552: f402 6210 and.w r2, r2, #2304 ; 0x900 hri_oscctrl_status_reg_t status_mask = OSCCTRL_STATUS_DFLLRDY | OSCCTRL_STATUS_DFLLLCKC; while (hri_oscctrl_get_STATUS_reg(hw, status_mask) != status_mask) 556: f5b2 6f10 cmp.w r2, #2304 ; 0x900 55a: d1f9 bne.n 550 <_oscctrl_init_referenced_generators+0x78> return ((Gclk *)hw)->SYNCBUSY.reg; 55c: 4a0b ldr r2, [pc, #44] ; (58c <_oscctrl_init_referenced_generators+0xb4>) 55e: 6853 ldr r3, [r2, #4] hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(hw, 1); #endif #endif #if CONF_DFLL_CONFIG == 1 while (hri_gclk_read_SYNCBUSY_reg(GCLK)) 560: 2b00 cmp r3, #0 562: d1fc bne.n 55e <_oscctrl_init_referenced_generators+0x86> tmp = ((Gclk *)hw)->GENCTRL[index].reg; 564: 6a13 ldr r3, [r2, #32] tmp &= ~GCLK_GENCTRL_SRC_Msk; 566: f023 030f bic.w r3, r3, #15 tmp |= GCLK_GENCTRL_SRC(data); 56a: f043 0301 orr.w r3, r3, #1 ((Gclk *)hw)->GENCTRL[index].reg = tmp; 56e: 6213 str r3, [r2, #32] while (((Gclk *)hw)->SYNCBUSY.reg & reg) { 570: f643 73fd movw r3, #16381 ; 0x3ffd 574: 6851 ldr r1, [r2, #4] 576: 4219 tst r1, r3 578: d1fc bne.n 574 <_oscctrl_init_referenced_generators+0x9c> return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL0) >> GCLK_SYNCBUSY_GENCTRL0_Pos; 57a: 4a04 ldr r2, [pc, #16] ; (58c <_oscctrl_init_referenced_generators+0xb4>) 57c: 6853 ldr r3, [r2, #4] ; hri_gclk_write_GENCTRL_SRC_bf(GCLK, 0, CONF_GCLK_GEN_0_SOURCE); while (hri_gclk_get_SYNCBUSY_GENCTRL0_bit(GCLK)) 57e: 075b lsls r3, r3, #29 580: d4fc bmi.n 57c <_oscctrl_init_referenced_generators+0xa4> ; #endif (void)hw; } 582: 4770 bx lr return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRDY) >> OSCCTRL_STATUS_DFLLRDY_Pos; 584: 691a ldr r2, [r3, #16] while (!hri_oscctrl_get_STATUS_DFLLRDY_bit(hw)) 586: 05d2 lsls r2, r2, #23 588: d5fc bpl.n 584 <_oscctrl_init_referenced_generators+0xac> 58a: e7e7 b.n 55c <_oscctrl_init_referenced_generators+0x84> 58c: 40001c00 .word 0x40001c00 590: 40001000 .word 0x40001000 594: 04010000 .word 0x04010000 00000598 <_mci_sync_init>: /** * \brief Initialize MCI low level driver. */ int32_t _mci_sync_init(struct _mci_sync_device *const mci_dev, void *const hw) { 598: b538 push {r3, r4, r5, lr} 59a: 460c mov r4, r1 ASSERT(mci_dev && hw); 59c: 4605 mov r5, r0 59e: b110 cbz r0, 5a6 <_mci_sync_init+0xe> 5a0: 1e08 subs r0, r1, #0 5a2: bf18 it ne 5a4: 2001 movne r0, #1 5a6: 4b12 ldr r3, [pc, #72] ; (5f0 <_mci_sync_init+0x58>) 5a8: 4912 ldr r1, [pc, #72] ; (5f4 <_mci_sync_init+0x5c>) 5aa: 22d8 movs r2, #216 ; 0xd8 5ac: 4798 blx r3 } static inline void hri_sdhc_set_SRR_SWRSTALL_bit(const void *const hw) { SDHC_CRITICAL_SECTION_ENTER(); ((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTALL; 5ae: f894 302f ldrb.w r3, [r4, #47] ; 0x2f mci_dev->hw = hw; 5b2: 602c str r4, [r5, #0] 5b4: f043 0301 orr.w r3, r3, #1 5b8: f884 302f strb.w r3, [r4, #47] ; 0x2f } static inline bool hri_sdhc_get_SRR_SWRSTALL_bit(const void *const hw) { uint8_t tmp; tmp = ((Sdhc *)hw)->SRR.reg; 5bc: f894 002f ldrb.w r0, [r4, #47] ; 0x2f hri_sdhc_set_SRR_SWRSTALL_bit(hw); while (hri_sdhc_get_SRR_SWRSTALL_bit(hw)) 5c0: f010 0001 ands.w r0, r0, #1 5c4: d1fa bne.n 5bc <_mci_sync_init+0x24> ((Sdhc *)hw)->TCR.reg = data; 5c6: 230e movs r3, #14 5c8: f884 302e strb.w r3, [r4, #46] ; 0x2e ((Sdhc *)hw)->PCR.reg = data; 5cc: 230f movs r3, #15 5ce: f884 3029 strb.w r3, [r4, #41] ; 0x29 } static inline void hri_sdhc_set_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) { SDHC_CRITICAL_SECTION_ENTER(); ((Sdhc *)hw)->NISTER.reg |= mask; 5d2: 8ea3 ldrh r3, [r4, #52] ; 0x34 5d4: b29b uxth r3, r3 5d6: ea6f 2353 mvn.w r3, r3, lsr #9 5da: ea6f 2343 mvn.w r3, r3, lsl #9 5de: 86a3 strh r3, [r4, #52] ; 0x34 } static inline void hri_sdhc_set_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) { SDHC_CRITICAL_SECTION_ENTER(); ((Sdhc *)hw)->EISTER.reg |= mask; 5e0: 8ee3 ldrh r3, [r4, #54] ; 0x36 5e2: b29b uxth r3, r3 5e4: ea6f 2393 mvn.w r3, r3, lsr #10 5e8: ea6f 2383 mvn.w r3, r3, lsl #10 5ec: 86e3 strh r3, [r4, #54] ; 0x36 hri_sdhc_set_NISTER_reg(hw, SDHC_NISTER_MASK); hri_sdhc_set_EISTER_reg(hw, SDHC_EISTER_MASK); return ERR_NONE; } 5ee: bd38 pop {r3, r4, r5, pc} 5f0: 000004b9 .word 0x000004b9 5f4: 0000102c .word 0x0000102c 000005f8 : * \param[in] length The number of bytes to write * * \return The number of bytes written. */ static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) { 5f8: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 5fc: 460e mov r6, r1 5fe: 4615 mov r5, r2 uint32_t offset = 0; struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io); ASSERT(io_descr && buf && length); 600: 4604 mov r4, r0 602: b118 cbz r0, 60c 604: b329 cbz r1, 652 606: 1e10 subs r0, r2, #0 608: bf18 it ne 60a: 2001 movne r0, #1 60c: 4912 ldr r1, [pc, #72] ; (658 ) 60e: 4b13 ldr r3, [pc, #76] ; (65c ) while (!_usart_sync_is_ready_to_send(&descr->device)) 610: 4f13 ldr r7, [pc, #76] ; (660 ) ASSERT(io_descr && buf && length); 612: 22f1 movs r2, #241 ; 0xf1 614: 4798 blx r3 while (!_usart_sync_is_ready_to_send(&descr->device)) 616: 3408 adds r4, #8 618: 46b9 mov r9, r7 61a: 4620 mov r0, r4 61c: 47b8 blx r7 61e: 2800 cmp r0, #0 620: d0fb beq.n 61a ; do { _usart_sync_write_byte(&descr->device, buf[offset]); 622: f8df 8044 ldr.w r8, [pc, #68] ; 668 uint32_t offset = 0; 626: 2700 movs r7, #0 _usart_sync_write_byte(&descr->device, buf[offset]); 628: 5df1 ldrb r1, [r6, r7] 62a: 4620 mov r0, r4 62c: 47c0 blx r8 while (!_usart_sync_is_ready_to_send(&descr->device)) 62e: 4620 mov r0, r4 630: 47c8 blx r9 632: 2800 cmp r0, #0 634: d0fb beq.n 62e ; } while (++offset < length); 636: 3701 adds r7, #1 638: 42bd cmp r5, r7 63a: d8f5 bhi.n 628 63c: 2d00 cmp r5, #0 while (!_usart_sync_is_transmit_done(&descr->device)) 63e: 4e09 ldr r6, [pc, #36] ; (664 ) } while (++offset < length); 640: bf08 it eq 642: 2501 moveq r5, #1 while (!_usart_sync_is_transmit_done(&descr->device)) 644: 4620 mov r0, r4 646: 47b0 blx r6 648: 2800 cmp r0, #0 64a: d0fb beq.n 644 ; return (int32_t)offset; } 64c: 4628 mov r0, r5 64e: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} ASSERT(io_descr && buf && length); 652: 4608 mov r0, r1 654: e7da b.n 60c 656: bf00 nop 658: 00001043 .word 0x00001043 65c: 000004b9 .word 0x000004b9 660: 00000d37 .word 0x00000d37 664: 00000d41 .word 0x00000d41 668: 00000d29 .word 0x00000d29 0000066c : * \param[in] length The size of a buffer * * \return The number of bytes read. */ static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) { 66c: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 670: 460e mov r6, r1 672: 4615 mov r5, r2 uint32_t offset = 0; struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io); ASSERT(io_descr && buf && length); 674: 4604 mov r4, r0 676: b118 cbz r0, 680 678: b1e9 cbz r1, 6b6 67a: 1e10 subs r0, r2, #0 67c: bf18 it ne 67e: 2001 movne r0, #1 680: 490e ldr r1, [pc, #56] ; (6bc ) 682: 4b0f ldr r3, [pc, #60] ; (6c0 ) do { while (!_usart_sync_is_byte_received(&descr->device)) 684: f8df 903c ldr.w r9, [pc, #60] ; 6c4 ; buf[offset] = _usart_sync_read_byte(&descr->device); 688: f8df 803c ldr.w r8, [pc, #60] ; 6c8 ASSERT(io_descr && buf && length); 68c: f44f 7286 mov.w r2, #268 ; 0x10c 690: 4798 blx r3 uint32_t offset = 0; 692: 2700 movs r7, #0 while (!_usart_sync_is_byte_received(&descr->device)) 694: 3408 adds r4, #8 696: 4620 mov r0, r4 698: 47c8 blx r9 69a: 2800 cmp r0, #0 69c: d0fb beq.n 696 buf[offset] = _usart_sync_read_byte(&descr->device); 69e: 4620 mov r0, r4 6a0: 47c0 blx r8 6a2: 55f0 strb r0, [r6, r7] } while (++offset < length); 6a4: 3701 adds r7, #1 6a6: 42bd cmp r5, r7 6a8: d8f5 bhi.n 696 6aa: 2d00 cmp r5, #0 return (int32_t)offset; } 6ac: bf14 ite ne 6ae: 4628 movne r0, r5 6b0: 2001 moveq r0, #1 6b2: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} ASSERT(io_descr && buf && length); 6b6: 4608 mov r0, r1 6b8: e7e2 b.n 680 6ba: bf00 nop 6bc: 00001043 .word 0x00001043 6c0: 000004b9 .word 0x000004b9 6c4: 00000d4b .word 0x00000d4b 6c8: 00000d2f .word 0x00000d2f 000006cc : { 6cc: b538 push {r3, r4, r5, lr} 6ce: 460d mov r5, r1 ASSERT(descr && hw); 6d0: 4604 mov r4, r0 6d2: b110 cbz r0, 6da 6d4: 1e08 subs r0, r1, #0 6d6: bf18 it ne 6d8: 2001 movne r0, #1 6da: 4907 ldr r1, [pc, #28] ; (6f8 ) 6dc: 4b07 ldr r3, [pc, #28] ; (6fc ) 6de: 2234 movs r2, #52 ; 0x34 6e0: 4798 blx r3 init_status = _usart_sync_init(&descr->device, hw); 6e2: 4b07 ldr r3, [pc, #28] ; (700 ) 6e4: 4629 mov r1, r5 6e6: f104 0008 add.w r0, r4, #8 6ea: 4798 blx r3 if (init_status) { 6ec: b918 cbnz r0, 6f6 descr->io.read = usart_sync_read; 6ee: 4b05 ldr r3, [pc, #20] ; (704 ) 6f0: 6063 str r3, [r4, #4] descr->io.write = usart_sync_write; 6f2: 4b05 ldr r3, [pc, #20] ; (708 ) 6f4: 6023 str r3, [r4, #0] } 6f6: bd38 pop {r3, r4, r5, pc} 6f8: 00001043 .word 0x00001043 6fc: 000004b9 .word 0x000004b9 700: 00000cfd .word 0x00000cfd 704: 0000066d .word 0x0000066d 708: 000005f9 .word 0x000005f9 0000070c <_mclk_init>: } static inline void hri_mclk_write_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t data) { MCLK_CRITICAL_SECTION_ENTER(); ((Mclk *)hw)->CPUDIV.reg = data; 70c: 4b01 ldr r3, [pc, #4] ; (714 <_mclk_init+0x8>) 70e: 2201 movs r2, #1 710: 715a strb r2, [r3, #5] */ void _mclk_init(void) { void *hw = (void *)MCLK; hri_mclk_write_CPUDIV_reg(hw, MCLK_CPUDIV_DIV(CONF_MCLK_CPUDIV)); } 712: 4770 bx lr 714: 40000800 .word 0x40000800 00000718 : return tmp; } static inline hri_ramecc_intflag_reg_t hri_ramecc_read_INTFLAG_reg(const void *const hw) { return ((Ramecc *)hw)->INTFLAG.reg; 718: 4a0b ldr r2, [pc, #44] ; (748 ) 71a: 7893 ldrb r3, [r2, #2] /** * \internal RAMECC interrupt handler */ void RAMECC_Handler(void) { 71c: b082 sub sp, #8 71e: b2db uxtb r3, r3 struct _ramecc_device *dev = (struct _ramecc_device *)&device; volatile uint32_t int_mask = hri_ramecc_read_INTFLAG_reg(RAMECC); 720: 9301 str r3, [sp, #4] if (int_mask & RAMECC_INTFLAG_DUALE && dev->ramecc_cb.dual_bit_err) { 722: 9b01 ldr r3, [sp, #4] 724: 0799 lsls r1, r3, #30 726: d505 bpl.n 734 728: 4b08 ldr r3, [pc, #32] ; (74c ) 72a: 681b ldr r3, [r3, #0] 72c: b113 cbz r3, 734 return tmp; } static inline hri_ramecc_erraddr_reg_t hri_ramecc_read_ERRADDR_reg(const void *const hw) { return ((Ramecc *)hw)->ERRADDR.reg; 72e: 6850 ldr r0, [r2, #4] } else if (int_mask & RAMECC_INTFLAG_SINGLEE && dev->ramecc_cb.single_bit_err) { dev->ramecc_cb.single_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC)); } else { return; } } 730: b002 add sp, #8 dev->ramecc_cb.single_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC)); 732: 4718 bx r3 } else if (int_mask & RAMECC_INTFLAG_SINGLEE && dev->ramecc_cb.single_bit_err) { 734: 9b01 ldr r3, [sp, #4] 736: 07db lsls r3, r3, #31 738: d504 bpl.n 744 73a: 4b04 ldr r3, [pc, #16] ; (74c ) 73c: 685b ldr r3, [r3, #4] 73e: b10b cbz r3, 744 740: 4a01 ldr r2, [pc, #4] ; (748 ) 742: e7f4 b.n 72e } 744: b002 add sp, #8 746: 4770 bx lr 748: 41020000 .word 0x41020000 74c: 20000060 .word 0x20000060 00000750 : #include "diskio_start.h" void diskio_init(void) { } 750: 4770 bx lr 00000752 : /** * \brief Default interrupt handler for unused IRQs. */ void Dummy_Handler(void) { while (1) { 752: e7fe b.n 752 00000754 : if (pSrc != pDest) { 754: 4918 ldr r1, [pc, #96] ; (7b8 ) 756: 4819 ldr r0, [pc, #100] ; (7bc ) 758: 4281 cmp r1, r0 { 75a: b510 push {r4, lr} if (pSrc != pDest) { 75c: d00a beq.n 774 *pDest++ = *pSrc++; 75e: 4b18 ldr r3, [pc, #96] ; (7c0 ) 760: 1cda adds r2, r3, #3 762: 1a12 subs r2, r2, r0 764: f022 0203 bic.w r2, r2, #3 768: 1ec4 subs r4, r0, #3 76a: 42a3 cmp r3, r4 76c: bf38 it cc 76e: 2200 movcc r2, #0 770: 4b14 ldr r3, [pc, #80] ; (7c4 ) 772: 4798 blx r3 *pDest++ = 0; 774: 4b14 ldr r3, [pc, #80] ; (7c8 ) 776: 4815 ldr r0, [pc, #84] ; (7cc ) 778: 1cda adds r2, r3, #3 77a: 1a12 subs r2, r2, r0 77c: 1ec1 subs r1, r0, #3 77e: f022 0203 bic.w r2, r2, #3 782: 4299 cmp r1, r3 784: bf88 it hi 786: 2200 movhi r2, #0 788: 4b11 ldr r3, [pc, #68] ; (7d0 ) 78a: 2100 movs r1, #0 78c: 4798 blx r3 SCB->VTOR = ((uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk); 78e: 4a11 ldr r2, [pc, #68] ; (7d4 ) 790: 4b11 ldr r3, [pc, #68] ; (7d8 ) 792: f022 027f bic.w r2, r2, #127 ; 0x7f 796: 609a str r2, [r3, #8] SCB->CPACR |= (0xFu << 20); 798: f8d3 2088 ldr.w r2, [r3, #136] ; 0x88 79c: f442 0270 orr.w r2, r2, #15728640 ; 0xf00000 7a0: f8c3 2088 str.w r2, [r3, #136] ; 0x88 \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); 7a4: f3bf 8f4f dsb sy __ASM volatile ("isb 0xF":::"memory"); 7a8: f3bf 8f6f isb sy __libc_init_array(); 7ac: 4b0b ldr r3, [pc, #44] ; (7dc ) 7ae: 4798 blx r3 main(); 7b0: 4b0b ldr r3, [pc, #44] ; (7e0 ) 7b2: 4798 blx r3 while (1) 7b4: e7fe b.n 7b4 7b6: bf00 nop 7b8: 000010fc .word 0x000010fc 7bc: 20000000 .word 0x20000000 7c0: 20000008 .word 0x20000008 7c4: 00000fb1 .word 0x00000fb1 7c8: 200000d8 .word 0x200000d8 7cc: 20000008 .word 0x20000008 7d0: 00000fcd .word 0x00000fcd 7d4: 00000000 .word 0x00000000 7d8: e000ed00 .word 0xe000ed00 7dc: 00000f69 .word 0x00000f69 7e0: 000007e5 .word 0x000007e5 000007e4
: #include int main(void) { 7e4: b508 push {r3, lr} /* Initializes MCU, drivers and middleware */ atmel_start_init(); 7e6: 4b01 ldr r3, [pc, #4] ; (7ec ) 7e8: 4798 blx r3 /* Replace with your application code */ while (1) { 7ea: e7fe b.n 7ea 7ec: 00000f49 .word 0x00000f49 000007f0 <_osc32kctrl_init_sources>: } static inline void hri_osc32kctrl_write_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) { OSC32KCTRL_CRITICAL_SECTION_ENTER(); ((Osc32kctrl *)hw)->XOSC32K.reg = data; 7f0: 4b06 ldr r3, [pc, #24] ; (80c <_osc32kctrl_init_sources+0x1c>) 7f2: f242 0286 movw r2, #8326 ; 0x2086 7f6: 829a strh r2, [r3, #20] } static inline void hri_osc32kctrl_write_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t data) { OSC32KCTRL_CRITICAL_SECTION_ENTER(); ((Osc32kctrl *)hw)->CFDCTRL.reg = data; 7f8: 2200 movs r2, #0 7fa: 759a strb r2, [r3, #22] } static inline void hri_osc32kctrl_write_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t data) { OSC32KCTRL_CRITICAL_SECTION_ENTER(); ((Osc32kctrl *)hw)->EVCTRL.reg = data; 7fc: 75da strb r2, [r3, #23] } static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_CALIB_bf(const void *const hw) { uint32_t tmp; tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; 7fe: 69da ldr r2, [r3, #28] calib = hri_osc32kctrl_read_OSCULP32K_CALIB_bf(hw); hri_osc32kctrl_write_OSCULP32K_reg(hw, #if CONF_OSCULP32K_CALIB_ENABLE == 1 OSC32KCTRL_OSCULP32K_CALIB(CONF_OSCULP32K_CALIB) #else OSC32KCTRL_OSCULP32K_CALIB(calib) 800: f402 527c and.w r2, r2, #16128 ; 0x3f00 } static inline void hri_osc32kctrl_write_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data) { OSC32KCTRL_CRITICAL_SECTION_ENTER(); ((Osc32kctrl *)hw)->OSCULP32K.reg = data; 804: 61da str r2, [r3, #28] ((Osc32kctrl *)hw)->RTCCTRL.reg = data; 806: 2201 movs r2, #1 808: 741a strb r2, [r3, #16] #endif #endif hri_osc32kctrl_write_RTCCTRL_reg(hw, OSC32KCTRL_RTCCTRL_RTCSEL(CONF_RTCCTRL)); (void)calib; } 80a: 4770 bx lr 80c: 40001400 .word 0x40001400 00000810 : typedef uint8_t hri_rtcalarm_mask_reg_t; typedef uint8_t hri_rtcmode2_mask_reg_t; static inline void hri_rtcmode0_wait_for_sync(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg) { while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) { 810: 6903 ldr r3, [r0, #16] 812: 420b tst r3, r1 814: d1fc bne.n 810 }; } 816: 4770 bx lr 00000818 <_calendar_init>: /** * \brief Initializes the RTC module with given configurations. */ int32_t _calendar_init(struct calendar_dev *const dev) { 818: b510 push {r4, lr} ASSERT(dev && dev->hw); 81a: 4604 mov r4, r0 81c: b118 cbz r0, 826 <_calendar_init+0xe> 81e: 6800 ldr r0, [r0, #0] 820: 3800 subs r0, #0 822: bf18 it ne 824: 2001 movne r0, #1 826: 4917 ldr r1, [pc, #92] ; (884 <_calendar_init+0x6c>) 828: 4b17 ldr r3, [pc, #92] ; (888 <_calendar_init+0x70>) 82a: 222f movs r2, #47 ; 0x2f 82c: 4798 blx r3 _rtc_dev = dev; 82e: 4b17 ldr r3, [pc, #92] ; (88c <_calendar_init+0x74>) } static inline bool hri_rtcmode0_get_CTRLA_ENABLE_bit(const void *const hw) { uint16_t tmp; hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); 830: 6820 ldr r0, [r4, #0] 832: 4a17 ldr r2, [pc, #92] ; (890 <_calendar_init+0x78>) 834: 601c str r4, [r3, #0] 836: f248 0103 movw r1, #32771 ; 0x8003 83a: 4790 blx r2 tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; 83c: 8803 ldrh r3, [r0, #0] if (hri_rtcmode0_get_CTRLA_ENABLE_bit(dev->hw)) { 83e: 079b lsls r3, r3, #30 840: d50a bpl.n 858 <_calendar_init+0x40> #if !CONF_RTC_INIT_RESET return ERR_DENIED; #else hri_rtcmode0_clear_CTRLA_ENABLE_bit(dev->hw); 842: 6820 ldr r0, [r4, #0] } static inline void hri_rtcmode0_clear_CTRLA_ENABLE_bit(const void *const hw) { RTC_CRITICAL_SECTION_ENTER(); ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE; 844: 8803 ldrh r3, [r0, #0] 846: f023 0302 bic.w r3, r3, #2 84a: 041b lsls r3, r3, #16 84c: 0c1b lsrs r3, r3, #16 84e: 8003 strh r3, [r0, #0] hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); 850: 4790 blx r2 hri_rtcmode0_wait_for_sync(dev->hw, RTC_MODE0_SYNCBUSY_ENABLE); 852: 6820 ldr r0, [r4, #0] 854: 2102 movs r1, #2 856: 4790 blx r2 #endif } hri_rtcmode0_set_CTRLA_SWRST_bit(dev->hw); 858: 6820 ldr r0, [r4, #0] ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_SWRST; 85a: 8803 ldrh r3, [r0, #0] 85c: b29b uxth r3, r3 85e: f043 0301 orr.w r3, r3, #1 862: 8003 strh r3, [r0, #0] hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST); 864: 2101 movs r1, #1 866: 4790 blx r2 hri_rtcmode0_wait_for_sync(dev->hw, RTC_MODE0_SYNCBUSY_SWRST); 868: 6820 ldr r0, [r4, #0] 86a: 4790 blx r2 | (CONF_RTC_COMPE0 << RTC_MODE0_EVCTRL_CMPEO_Pos) | (CONF_RTC_COMPE1 << RTC_MODE0_EVCTRL_CMPEO1_Pos) | (CONF_RTC_TAMPEREO << RTC_MODE0_EVCTRL_TAMPEREO_Pos) | (CONF_RTC_TAMPEVEI << RTC_MODE0_EVCTRL_TAMPEVEI_Pos) | (CONF_RTC_OVFEO << RTC_MODE0_EVCTRL_OVFEO_Pos)); #endif hri_rtcmode0_write_CTRLA_reg(dev->hw, RTC_MODE0_CTRLA_PRESCALER(CONF_RTC_PRESCALER) | RTC_MODE0_CTRLA_COUNTSYNC); 86c: 6820 ldr r0, [r4, #0] } static inline void hri_rtcmode0_write_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t data) { RTC_CRITICAL_SECTION_ENTER(); ((Rtc *)hw)->MODE0.CTRLA.reg = data; 86e: f44f 4301 mov.w r3, #33024 ; 0x8100 872: 8003 strh r3, [r0, #0] hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); 874: f248 0103 movw r1, #32771 ; 0x8003 878: 4790 blx r2 hri_rtc_write_TAMPCTRL_reg( dev->hw, 87a: 6823 ldr r3, [r4, #0] } static inline void hri_rtc_write_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t data) { RTC_CRITICAL_SECTION_ENTER(); ((Rtc *)hw)->MODE0.TAMPCTRL.reg = data; 87c: 2000 movs r0, #0 87e: 6618 str r0, [r3, #96] ; 0x60 | (CONF_RTC_TAMPER_INACT_2 == TAMPER_MODE_ACTL) | (CONF_RTC_TAMPER_INACT_3 == TAMPER_MODE_ACTL) | (CONF_RTC_TAMPER_INACT_4 == TAMPER_MODE_ACTL)) { hri_rtcmode0_set_CTRLB_RTCOUT_bit(dev->hw); } return ERR_NONE; } 880: bd10 pop {r4, pc} 882: bf00 nop 884: 0000105f .word 0x0000105f 888: 000004b9 .word 0x000004b9 88c: 20000070 .word 0x20000070 890: 00000811 .word 0x00000811 00000894 : /** * \brief Rtc interrupt handler */ void RTC_Handler(void) { _rtc_interrupt_handler(_rtc_dev); 894: 4b0d ldr r3, [pc, #52] ; (8cc ) { 896: b510 push {r4, lr} _rtc_interrupt_handler(_rtc_dev); 898: 681c ldr r4, [r3, #0] uint16_t interrupt_status = hri_rtcmode0_read_INTFLAG_reg(dev->hw); 89a: 6822 ldr r2, [r4, #0] return ((Rtc *)hw)->MODE0.INTFLAG.reg; 89c: 8991 ldrh r1, [r2, #12] return ((Rtc *)hw)->MODE0.INTENSET.reg; 89e: 8953 ldrh r3, [r2, #10] 8a0: b29b uxth r3, r3 if ((interrupt_status & interrupt_enabled) & RTC_MODE2_INTFLAG_ALARM0) { 8a2: 400b ands r3, r1 8a4: 05da lsls r2, r3, #23 8a6: d507 bpl.n 8b8 dev->callback(dev); 8a8: 6863 ldr r3, [r4, #4] 8aa: 4620 mov r0, r4 8ac: 4798 blx r3 hri_rtcmode0_clear_interrupt_CMP0_bit(dev->hw); 8ae: 6823 ldr r3, [r4, #0] ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; 8b0: f44f 7280 mov.w r2, #256 ; 0x100 ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER; 8b4: 819a strh r2, [r3, #12] } 8b6: bd10 pop {r4, pc} } else if ((interrupt_status & interrupt_enabled) & RTC_MODE2_INTFLAG_TAMPER) { 8b8: 045b lsls r3, r3, #17 8ba: d5fc bpl.n 8b6 dev->callback_tamper(dev); 8bc: 68a3 ldr r3, [r4, #8] 8be: 4620 mov r0, r4 8c0: 4798 blx r3 hri_rtcmode0_clear_interrupt_TAMPER_bit(dev->hw); 8c2: 6823 ldr r3, [r4, #0] 8c4: f44f 4280 mov.w r2, #16384 ; 0x4000 8c8: e7f4 b.n 8b4 8ca: bf00 nop 8cc: 20000070 .word 0x20000070 000008d0 : * GPIO_DIRECTION_OFF = Disables the pin * (low power state) */ static inline void gpio_set_pin_direction(const uint8_t pin, const enum gpio_direction direction) { _gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction); 8d0: f000 031f and.w r3, r0, #31 { 8d4: b530 push {r4, r5, lr} _gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction); 8d6: 2501 movs r5, #1 8d8: 409d lsls r5, r3 ((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~data; } static inline void hri_port_clear_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) { ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask; 8da: 0940 lsrs r0, r0, #5 8dc: 4b0d ldr r3, [pc, #52] ; (914 ) 8de: 01c0 lsls r0, r0, #7 * \brief Set direction on port with mask */ static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, const enum gpio_direction direction) { switch (direction) { 8e0: 2902 cmp r1, #2 PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); break; case GPIO_DIRECTION_IN: hri_port_clear_DIR_reg(PORT, port, mask); hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN | (mask & 0xffff)); 8e2: b2ac uxth r4, r5 hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN | ((mask & 0xffff0000) >> 16)); 8e4: ea4f 4215 mov.w r2, r5, lsr #16 ((Port *)hw)->Group[submodule_index].DIRSET.reg = mask; 8e8: 4403 add r3, r0 switch (direction) { 8ea: d00b beq.n 904 hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN | (mask & 0xffff)); 8ec: f044 4480 orr.w r4, r4, #1073741824 ; 0x40000000 8f0: f444 3400 orr.w r4, r4, #131072 ; 0x20000 hri_port_write_WRCONFIG_reg(PORT, 8f4: f042 4240 orr.w r2, r2, #3221225472 ; 0xc0000000 ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask; 8f8: 605d str r5, [r3, #4] 8fa: f442 3200 orr.w r2, r2, #131072 ; 0x20000 static inline void hri_port_write_WRCONFIG_reg(const void *const hw, uint8_t submodule_index, hri_port_wrconfig_reg_t data) { PORT_CRITICAL_SECTION_ENTER(); ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; 8fe: 629c str r4, [r3, #40] ; 0x28 900: 629a str r2, [r3, #40] ; 0x28 } 902: bd30 pop {r4, r5, pc} break; case GPIO_DIRECTION_OUT: hri_port_set_DIR_reg(PORT, port, mask); hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); 904: f044 4480 orr.w r4, r4, #1073741824 ; 0x40000000 ((Port *)hw)->Group[submodule_index].DIRSET.reg = mask; 908: 609d str r5, [r3, #8] hri_port_write_WRCONFIG_reg( 90a: f042 4240 orr.w r2, r2, #3221225472 ; 0xc0000000 ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; 90e: 629c str r4, [r3, #40] ; 0x28 910: e7f6 b.n 900 912: bf00 nop 914: 41008000 .word 0x41008000 00000918 : ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; 918: 0942 lsrs r2, r0, #5 91a: f000 031f and.w r3, r0, #31 91e: eb03 13c2 add.w r3, r3, r2, lsl #7 922: f103 4382 add.w r3, r3, #1090519040 ; 0x41000000 926: f503 4300 add.w r3, r3, #32768 ; 0x8000 92a: f893 2040 ldrb.w r2, [r3, #64] ; 0x40 92e: f002 02fb and.w r2, r2, #251 ; 0xfb 932: f883 2040 strb.w r2, [r3, #64] ; 0x40 } 936: 4770 bx lr 00000938 <_gpio_set_pin_function>: /** * \brief Set gpio pin function */ static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function) { uint8_t port = GPIO_PORT(gpio); 938: 0943 lsrs r3, r0, #5 tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; 93a: 01db lsls r3, r3, #7 93c: f103 4382 add.w r3, r3, #1090519040 ; 0x41000000 { 940: b530 push {r4, r5, lr} 942: f503 4300 add.w r3, r3, #32768 ; 0x8000 uint8_t pin = GPIO_PIN(gpio); 946: f000 041f and.w r4, r0, #31 94a: 191d adds r5, r3, r4 94c: eb03 0354 add.w r3, r3, r4, lsr #1 950: f895 2040 ldrb.w r2, [r5, #64] ; 0x40 tmp &= ~PORT_PINCFG_PMUXEN; 954: f002 02fe and.w r2, r2, #254 ; 0xfe tmp |= value << PORT_PINCFG_PMUXEN_Pos; 958: f042 0201 orr.w r2, r2, #1 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; 95c: f885 2040 strb.w r2, [r5, #64] ; 0x40 } else { hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, true); if (pin & 1) { // Odd numbered pin hri_port_write_PMUX_PMUXO_bf(PORT, port, pin >> 1, function & 0xffff); 960: b2ca uxtb r2, r1 tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; 962: f893 1030 ldrb.w r1, [r3, #48] ; 0x30 if (pin & 1) { 966: f010 0f01 tst.w r0, #1 tmp &= ~PORT_PMUX_PMUXO_Msk; 96a: bf1b ittet ne 96c: f001 010f andne.w r1, r1, #15 tmp |= PORT_PMUX_PMUXO(data); 970: ea41 1102 orrne.w r1, r1, r2, lsl #4 tmp &= ~PORT_PMUX_PMUXE_Msk; 974: f001 01f0 andeq.w r1, r1, #240 ; 0xf0 tmp |= PORT_PMUX_PMUXO(data); 978: b2c9 uxtbne r1, r1 tmp |= PORT_PMUX_PMUXE(data); 97a: bf08 it eq 97c: 4311 orreq r1, r2 ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; 97e: f883 1030 strb.w r1, [r3, #48] ; 0x30 } else { // Even numbered pin hri_port_write_PMUX_PMUXE_bf(PORT, port, pin >> 1, function & 0xffff); } } } 982: bd30 pop {r4, r5, pc} 00000984 : } static inline void hri_mclk_set_APBAMASK_RTC_bit(const void *const hw) { MCLK_CRITICAL_SECTION_ENTER(); ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RTC; 984: 4a02 ldr r2, [pc, #8] ; (990 ) 986: 6953 ldr r3, [r2, #20] 988: f443 7300 orr.w r3, r3, #512 ; 0x200 98c: 6153 str r3, [r2, #20] struct mci_sync_desc IO_BUS; void CALENDER_INTERFACE_CLOCK_init(void) { hri_mclk_set_APBAMASK_RTC_bit(MCLK); } 98e: 4770 bx lr 990: 40000800 .word 0x40000800 00000994 : void CALENDER_INTERFACE_init(void) { 994: b510 push {r4, lr} CALENDER_INTERFACE_CLOCK_init(); 996: 4b04 ldr r3, [pc, #16] ; (9a8 ) calendar_init(&CALENDER_INTERFACE, RTC); 998: 4904 ldr r1, [pc, #16] ; (9ac ) 99a: 4805 ldr r0, [pc, #20] ; (9b0 ) CALENDER_INTERFACE_CLOCK_init(); 99c: 4798 blx r3 } 99e: e8bd 4010 ldmia.w sp!, {r4, lr} calendar_init(&CALENDER_INTERFACE, RTC); 9a2: 4b04 ldr r3, [pc, #16] ; (9b4 ) 9a4: 4718 bx r3 9a6: bf00 nop 9a8: 00000985 .word 0x00000985 9ac: 40002400 .word 0x40002400 9b0: 20000078 .word 0x20000078 9b4: 000002a5 .word 0x000002a5 000009b8 : void USART_0_PORT_init(void) { 9b8: b510 push {r4, lr} _gpio_set_pin_function(pin, function); 9ba: 4c05 ldr r4, [pc, #20] ; (9d0 ) 9bc: 4905 ldr r1, [pc, #20] ; (9d4 ) 9be: 2004 movs r0, #4 9c0: 47a0 blx r4 9c2: 4623 mov r3, r4 9c4: 4904 ldr r1, [pc, #16] ; (9d8 ) gpio_set_pin_function(DBG_TX, PINMUX_PA04D_SERCOM0_PAD0); gpio_set_pin_function(DBG_RX, PINMUX_PA05D_SERCOM0_PAD1); } 9c6: e8bd 4010 ldmia.w sp!, {r4, lr} 9ca: 2005 movs r0, #5 9cc: 4718 bx r3 9ce: bf00 nop 9d0: 00000939 .word 0x00000939 9d4: 00040003 .word 0x00040003 9d8: 00050003 .word 0x00050003 000009dc : } static inline void hri_gclk_write_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data) { GCLK_CRITICAL_SECTION_ENTER(); ((Gclk *)hw)->PCHCTRL[index].reg = data; 9dc: 4b06 ldr r3, [pc, #24] ; (9f8 ) 9de: 2240 movs r2, #64 ; 0x40 9e0: f8c3 209c str.w r2, [r3, #156] ; 0x9c 9e4: 2243 movs r2, #67 ; 0x43 9e6: f8c3 208c str.w r2, [r3, #140] ; 0x8c } static inline void hri_mclk_set_APBAMASK_SERCOM0_bit(const void *const hw) { MCLK_CRITICAL_SECTION_ENTER(); ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SERCOM0; 9ea: 4a04 ldr r2, [pc, #16] ; (9fc ) 9ec: 6953 ldr r3, [r2, #20] 9ee: f443 5380 orr.w r3, r3, #4096 ; 0x1000 9f2: 6153 str r3, [r2, #20] { hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_CORE, CONF_GCLK_SERCOM0_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_SLOW, CONF_GCLK_SERCOM0_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); hri_mclk_set_APBAMASK_SERCOM0_bit(MCLK); } 9f4: 4770 bx lr 9f6: bf00 nop 9f8: 40001c00 .word 0x40001c00 9fc: 40000800 .word 0x40000800 00000a00 : void USART_0_init(void) { a00: b510 push {r4, lr} USART_0_CLOCK_init(); a02: 4b05 ldr r3, [pc, #20] ; (a18 ) usart_sync_init(&USART_0, SERCOM0, (void *)NULL); a04: 4905 ldr r1, [pc, #20] ; (a1c ) a06: 4806 ldr r0, [pc, #24] ; (a20 ) USART_0_CLOCK_init(); a08: 4798 blx r3 usart_sync_init(&USART_0, SERCOM0, (void *)NULL); a0a: 4b06 ldr r3, [pc, #24] ; (a24 ) a0c: 2200 movs r2, #0 a0e: 4798 blx r3 USART_0_PORT_init(); } a10: e8bd 4010 ldmia.w sp!, {r4, lr} USART_0_PORT_init(); a14: 4b04 ldr r3, [pc, #16] ; (a28 ) a16: 4718 bx r3 a18: 000009dd .word 0x000009dd a1c: 40003000 .word 0x40003000 a20: 20000098 .word 0x20000098 a24: 000006cd .word 0x000006cd a28: 000009b9 .word 0x000009b9 00000a2c : void SPI_0_PORT_init(void) { a2c: b570 push {r4, r5, r6, lr} ((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask; a2e: 4e12 ldr r6, [pc, #72] ; (a78 ) // Low // High false); // Set pin direction to output gpio_set_pin_direction(PC16, GPIO_DIRECTION_OUT); a30: 4d12 ldr r5, [pc, #72] ; (a7c ) a32: 4c13 ldr r4, [pc, #76] ; (a80 ) a34: f44f 3380 mov.w r3, #65536 ; 0x10000 a38: f8c6 3114 str.w r3, [r6, #276] ; 0x114 a3c: 2102 movs r1, #2 a3e: 2050 movs r0, #80 ; 0x50 a40: 47a8 blx r5 a42: f501 01a0 add.w r1, r1, #5242880 ; 0x500000 a46: 2050 movs r0, #80 ; 0x50 a48: 47a0 blx r4 a4a: f44f 3300 mov.w r3, #131072 ; 0x20000 a4e: f8c6 3114 str.w r3, [r6, #276] ; 0x114 // Low // High false); // Set pin direction to output gpio_set_pin_direction(PC17, GPIO_DIRECTION_OUT); a52: 2102 movs r1, #2 a54: 2051 movs r0, #81 ; 0x51 a56: 47a8 blx r5 a58: f501 01a2 add.w r1, r1, #5308416 ; 0x510000 a5c: 2051 movs r0, #81 ; 0x51 a5e: 47a0 blx r4 gpio_set_pin_function(PC17, PINMUX_PC17C_SERCOM6_PAD1); // Set pin direction to input gpio_set_pin_direction(PC18, GPIO_DIRECTION_IN); a60: 2101 movs r1, #1 a62: 2052 movs r0, #82 ; 0x52 a64: 47a8 blx r5 gpio_set_pin_pull_mode(PC18, a66: 4b07 ldr r3, [pc, #28] ; (a84 ) a68: 4907 ldr r1, [pc, #28] ; (a88 ) a6a: 2052 movs r0, #82 ; 0x52 a6c: 4798 blx r3 a6e: 4623 mov r3, r4 // Pull-up // Pull-down GPIO_PULL_OFF); gpio_set_pin_function(PC18, PINMUX_PC18C_SERCOM6_PAD2); } a70: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} a74: 4718 bx r3 a76: bf00 nop a78: 41008000 .word 0x41008000 a7c: 000008d1 .word 0x000008d1 a80: 00000939 .word 0x00000939 a84: 00000919 .word 0x00000919 a88: 00520002 .word 0x00520002 00000a8c : a8c: 4b06 ldr r3, [pc, #24] ; (aa8 ) a8e: 2240 movs r2, #64 ; 0x40 a90: f8c3 2110 str.w r2, [r3, #272] ; 0x110 a94: 2243 movs r2, #67 ; 0x43 a96: f8c3 208c str.w r2, [r3, #140] ; 0x8c } static inline void hri_mclk_set_APBDMASK_SERCOM6_bit(const void *const hw) { MCLK_CRITICAL_SECTION_ENTER(); ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM6; a9a: 4a04 ldr r2, [pc, #16] ; (aac ) a9c: 6a13 ldr r3, [r2, #32] a9e: f043 0304 orr.w r3, r3, #4 aa2: 6213 str r3, [r2, #32] { hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM6_GCLK_ID_CORE, CONF_GCLK_SERCOM6_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM6_GCLK_ID_SLOW, CONF_GCLK_SERCOM6_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); hri_mclk_set_APBDMASK_SERCOM6_bit(MCLK); } aa4: 4770 bx lr aa6: bf00 nop aa8: 40001c00 .word 0x40001c00 aac: 40000800 .word 0x40000800 00000ab0 : void SPI_0_init(void) { ab0: b510 push {r4, lr} SPI_0_CLOCK_init(); ab2: 4b05 ldr r3, [pc, #20] ; (ac8 ) spi_m_sync_init(&SPI_0, SERCOM6); ab4: 4905 ldr r1, [pc, #20] ; (acc ) ab6: 4806 ldr r0, [pc, #24] ; (ad0 ) SPI_0_CLOCK_init(); ab8: 4798 blx r3 spi_m_sync_init(&SPI_0, SERCOM6); aba: 4b06 ldr r3, [pc, #24] ; (ad4 ) abc: 4798 blx r3 SPI_0_PORT_init(); } abe: e8bd 4010 ldmia.w sp!, {r4, lr} SPI_0_PORT_init(); ac2: 4b05 ldr r3, [pc, #20] ; (ad8 ) ac4: 4718 bx r3 ac6: bf00 nop ac8: 00000a8d .word 0x00000a8d acc: 43000800 .word 0x43000800 ad0: 200000a4 .word 0x200000a4 ad4: 00000319 .word 0x00000319 ad8: 00000a2d .word 0x00000a2d 00000adc : void IO_BUS_PORT_init(void) { adc: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} ae0: 4e21 ldr r6, [pc, #132] ; (b68 ) gpio_set_pin_direction(PB11, ae2: 4f22 ldr r7, [pc, #136] ; (b6c ) // pad_initial_level // Low // High false); gpio_set_pin_pull_mode(PB11, ae4: 4d22 ldr r5, [pc, #136] ; (b70 ) ae6: 4c23 ldr r4, [pc, #140] ; (b74 ) ae8: f44f 6900 mov.w r9, #2048 ; 0x800 gpio_set_pin_direction(PB11, aec: 2102 movs r1, #2 aee: 202b movs r0, #43 ; 0x2b af0: 47b8 blx r7 gpio_set_pin_pull_mode(PB11, af2: 202b movs r0, #43 ; 0x2b af4: 4920 ldr r1, [pc, #128] ; (b78 ) af6: f8c6 9094 str.w r9, [r6, #148] ; 0x94 afa: 47a8 blx r5 afc: 47a0 blx r4 // L // M // N PINMUX_PB11I_SDHC0_SDCK); gpio_set_pin_direction(PA08, afe: 2102 movs r1, #2 b00: 2008 movs r0, #8 b02: 47b8 blx r7 b04: f44f 7380 mov.w r3, #256 ; 0x100 b08: 6173 str r3, [r6, #20] // pad_initial_level // Low // High false); gpio_set_pin_pull_mode(PA08, b0a: 2008 movs r0, #8 b0c: f04f 1108 mov.w r1, #524296 ; 0x80008 b10: 47a8 blx r5 b12: 47a0 blx r4 // L // M // N PINMUX_PA08I_SDHC0_SDCMD); gpio_set_pin_direction(PA09, b14: 2102 movs r1, #2 b16: 2009 movs r0, #9 b18: 47b8 blx r7 b1a: f44f 7300 mov.w r3, #512 ; 0x200 b1e: 6173 str r3, [r6, #20] // pad_initial_level // Low // High false); gpio_set_pin_pull_mode(PA09, b20: 2009 movs r0, #9 b22: 4916 ldr r1, [pc, #88] ; (b7c ) b24: 47a8 blx r5 b26: f44f 6880 mov.w r8, #1024 ; 0x400 b2a: 47a0 blx r4 // L // M // N PINMUX_PA09I_SDHC0_SDDAT0); gpio_set_pin_direction(PA10, b2c: 2102 movs r1, #2 b2e: 200a movs r0, #10 b30: 47b8 blx r7 // pad_initial_level // Low // High false); gpio_set_pin_pull_mode(PA10, b32: 200a movs r0, #10 b34: 4912 ldr r1, [pc, #72] ; (b80 ) b36: f8c6 8014 str.w r8, [r6, #20] b3a: 47a8 blx r5 b3c: 47a0 blx r4 // L // M // N PINMUX_PA10I_SDHC0_SDDAT1); gpio_set_pin_direction(PA11, b3e: 2102 movs r1, #2 b40: 200b movs r0, #11 b42: 47b8 blx r7 // pad_initial_level // Low // High false); gpio_set_pin_pull_mode(PA11, b44: 200b movs r0, #11 b46: 490f ldr r1, [pc, #60] ; (b84 ) b48: f8c6 9014 str.w r9, [r6, #20] b4c: 47a8 blx r5 b4e: 47a0 blx r4 // L // M // N PINMUX_PA11I_SDHC0_SDDAT2); gpio_set_pin_direction(PB10, b50: 2102 movs r1, #2 b52: 202a movs r0, #42 ; 0x2a b54: 47b8 blx r7 b56: f8c6 8094 str.w r8, [r6, #148] ; 0x94 // pad_initial_level // Low // High false); gpio_set_pin_pull_mode(PB10, b5a: 202a movs r0, #42 ; 0x2a b5c: 47a8 blx r5 b5e: 490a ldr r1, [pc, #40] ; (b88 ) b60: 4623 mov r3, r4 // K // L // M // N PINMUX_PB10I_SDHC0_SDDAT3); } b62: e8bd 47f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, lr} b66: 4718 bx r3 b68: 41008000 .word 0x41008000 b6c: 000008d1 .word 0x000008d1 b70: 00000919 .word 0x00000919 b74: 00000939 .word 0x00000939 b78: 002b0008 .word 0x002b0008 b7c: 00090008 .word 0x00090008 b80: 000a0008 .word 0x000a0008 b84: 000b0008 .word 0x000b0008 b88: 002a0008 .word 0x002a0008 00000b8c : ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_SDHC0; b8c: 4a05 ldr r2, [pc, #20] ; (ba4 ) b8e: 6913 ldr r3, [r2, #16] b90: f443 4300 orr.w r3, r3, #32768 ; 0x8000 b94: 6113 str r3, [r2, #16] b96: 4b04 ldr r3, [pc, #16] ; (ba8 ) b98: 2240 movs r2, #64 ; 0x40 b9a: f8c3 2134 str.w r2, [r3, #308] ; 0x134 b9e: f8c3 208c str.w r2, [r3, #140] ; 0x8c void IO_BUS_CLOCK_init(void) { hri_mclk_set_AHBMASK_SDHC0_bit(MCLK); hri_gclk_write_PCHCTRL_reg(GCLK, SDHC0_GCLK_ID, CONF_GCLK_SDHC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); hri_gclk_write_PCHCTRL_reg(GCLK, SDHC0_GCLK_ID_SLOW, CONF_GCLK_SDHC0_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); } ba2: 4770 bx lr ba4: 40000800 .word 0x40000800 ba8: 40001c00 .word 0x40001c00 00000bac : void IO_BUS_init(void) { bac: b510 push {r4, lr} IO_BUS_CLOCK_init(); bae: 4b05 ldr r3, [pc, #20] ; (bc4 ) mci_sync_init(&IO_BUS, SDHC0); bb0: 4805 ldr r0, [pc, #20] ; (bc8 ) IO_BUS_CLOCK_init(); bb2: 4798 blx r3 mci_sync_init(&IO_BUS, SDHC0); bb4: f04f 418a mov.w r1, #1157627904 ; 0x45000000 bb8: 4b04 ldr r3, [pc, #16] ; (bcc ) bba: 4798 blx r3 IO_BUS_PORT_init(); } bbc: e8bd 4010 ldmia.w sp!, {r4, lr} IO_BUS_PORT_init(); bc0: 4b03 ldr r3, [pc, #12] ; (bd0 ) bc2: 4718 bx r3 bc4: 00000b8d .word 0x00000b8d bc8: 200000c0 .word 0x200000c0 bcc: 00000411 .word 0x00000411 bd0: 00000add .word 0x00000add 00000bd4 : void system_init(void) { bd4: b510 push {r4, lr} * Currently the following initialization functions are supported: * - System clock initialization */ static inline void init_mcu(void) { _init_chip(); bd6: 4b06 ldr r3, [pc, #24] ; (bf0 ) bd8: 4798 blx r3 init_mcu(); CALENDER_INTERFACE_init(); bda: 4b06 ldr r3, [pc, #24] ; (bf4 ) bdc: 4798 blx r3 USART_0_init(); bde: 4b06 ldr r3, [pc, #24] ; (bf8 ) be0: 4798 blx r3 SPI_0_init(); be2: 4b06 ldr r3, [pc, #24] ; (bfc ) be4: 4798 blx r3 IO_BUS_init(); } be6: e8bd 4010 ldmia.w sp!, {r4, lr} IO_BUS_init(); bea: 4b05 ldr r3, [pc, #20] ; (c00 ) bec: 4718 bx r3 bee: bf00 nop bf0: 00000441 .word 0x00000441 bf4: 00000995 .word 0x00000995 bf8: 00000a01 .word 0x00000a01 bfc: 00000ab1 .word 0x00000ab1 c00: 00000bad .word 0x00000bad 00000c04 : return ((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg; } static inline void hri_sercomspi_wait_for_sync(const void *const hw, hri_sercomspi_syncbusy_reg_t reg) { while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) { c04: 69c3 ldr r3, [r0, #28] c06: 420b tst r3, r1 c08: d1fc bne.n c04 }; } c0a: 4770 bx lr 00000c0c : return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg; } static inline void hri_sercomusart_wait_for_sync(const void *const hw, hri_sercomusart_syncbusy_reg_t reg) { while (((Sercom *)hw)->USART.SYNCBUSY.reg & reg) { c0c: 69c3 ldr r3, [r0, #28] c0e: 420b tst r3, r1 c10: d1fc bne.n c0c }; } c12: 4770 bx lr 00000c14 : } static inline void hri_sercomspi_clear_CTRLA_ENABLE_bit(const void *const hw) { SERCOM_CRITICAL_SECTION_ENTER(); ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE; c14: 6802 ldr r2, [r0, #0] hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); c16: 4b03 ldr r3, [pc, #12] ; (c24 ) ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE; c18: f022 0202 bic.w r2, r2, #2 c1c: 6002 str r2, [r0, #0] hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); c1e: 2103 movs r1, #3 c20: 4718 bx r3 c22: bf00 nop c24: 00000c05 .word 0x00000c05 00000c28 : } static inline void hri_sercomusart_clear_CTRLA_ENABLE_bit(const void *const hw) { SERCOM_CRITICAL_SECTION_ENTER(); ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE; c28: 6802 ldr r2, [r0, #0] hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); c2a: 4b03 ldr r3, [pc, #12] ; (c38 ) ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE; c2c: f022 0202 bic.w r2, r2, #2 c30: 6002 str r2, [r0, #0] hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); c32: 2103 movs r1, #3 c34: 4718 bx r3 c36: bf00 nop c38: 00000c0d .word 0x00000c0d 00000c3c <_sercom_get_hardware_index>: /** * \brief Retrieve ordinal number of the given sercom hardware instance */ static uint8_t _sercom_get_hardware_index(const void *const hw) { c3c: b570 push {r4, r5, r6, lr} Sercom *const sercom_modules[] = SERCOM_INSTS; c3e: 4d0c ldr r5, [pc, #48] ; (c70 <_sercom_get_hardware_index+0x34>) { c40: 4606 mov r6, r0 Sercom *const sercom_modules[] = SERCOM_INSTS; c42: cd0f ldmia r5!, {r0, r1, r2, r3} { c44: b088 sub sp, #32 Sercom *const sercom_modules[] = SERCOM_INSTS; c46: 466c mov r4, sp c48: c40f stmia r4!, {r0, r1, r2, r3} c4a: e895 000f ldmia.w r5, {r0, r1, r2, r3} c4e: e884 000f stmia.w r4, {r0, r1, r2, r3} /* Find index for SERCOM instance. */ for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) { c52: 466a mov r2, sp c54: 2300 movs r3, #0 if ((uint32_t)hw == (uint32_t)sercom_modules[i]) { c56: f852 1b04 ldr.w r1, [r2], #4 c5a: 42b1 cmp r1, r6 c5c: d102 bne.n c64 <_sercom_get_hardware_index+0x28> return i; c5e: b2d8 uxtb r0, r3 } } return 0; } c60: b008 add sp, #32 c62: bd70 pop {r4, r5, r6, pc} for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) { c64: 3301 adds r3, #1 c66: 2b08 cmp r3, #8 c68: d1f5 bne.n c56 <_sercom_get_hardware_index+0x1a> return 0; c6a: 2000 movs r0, #0 c6c: e7f8 b.n c60 <_sercom_get_hardware_index+0x24> c6e: bf00 nop c70: 00001090 .word 0x00001090 00000c74 <_usart_init>: * \param[in] hw The pointer to hardware instance * * \return The status of initialization */ static int32_t _usart_init(void *const hw) { c74: b538 push {r3, r4, r5, lr} uint8_t sercom_offset = _sercom_get_hardware_index(hw); c76: 4b1a ldr r3, [pc, #104] ; (ce0 <_usart_init+0x6c>) { c78: 4604 mov r4, r0 uint8_t sercom_offset = _sercom_get_hardware_index(hw); c7a: 4798 blx r3 if (_usarts[i].number == sercom_offset) { c7c: b128 cbz r0, c8a <_usart_init+0x16> ASSERT(false); c7e: 4919 ldr r1, [pc, #100] ; (ce4 <_usart_init+0x70>) c80: 4b19 ldr r3, [pc, #100] ; (ce8 <_usart_init+0x74>) c82: f240 2247 movw r2, #583 ; 0x247 c86: 2000 movs r0, #0 c88: 4798 blx r3 return ((Sercom *)hw)->USART.SYNCBUSY.reg & reg; c8a: 69e3 ldr r3, [r4, #28] c8c: 4d17 ldr r5, [pc, #92] ; (cec <_usart_init+0x78>) uint8_t i = _get_sercom_index(hw); if (!hri_sercomusart_is_syncing(hw, SERCOM_USART_SYNCBUSY_SWRST)) { c8e: f013 0f01 tst.w r3, #1 c92: d10e bne.n cb2 <_usart_init+0x3e> static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) { uint32_t tmp; hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); c94: 2103 movs r1, #3 c96: 4620 mov r0, r4 c98: 47a8 blx r5 tmp = ((Sercom *)hw)->USART.CTRLA.reg; c9a: 6823 ldr r3, [r4, #0] uint32_t mode = _usarts[i].ctrl_a & SERCOM_USART_CTRLA_MODE_Msk; if (hri_sercomusart_get_CTRLA_reg(hw, SERCOM_USART_CTRLA_ENABLE)) { c9c: 079b lsls r3, r3, #30 c9e: d503 bpl.n ca8 <_usart_init+0x34> hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); ca0: 4b13 ldr r3, [pc, #76] ; (cf0 <_usart_init+0x7c>) ca2: 4798 blx r3 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); ca4: 2102 movs r1, #2 ca6: 47a8 blx r5 } static inline void hri_sercomusart_write_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t data) { SERCOM_CRITICAL_SECTION_ENTER(); ((Sercom *)hw)->USART.CTRLA.reg = data; ca8: 2305 movs r3, #5 caa: 6023 str r3, [r4, #0] hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); cac: 2103 movs r1, #3 cae: 4620 mov r0, r4 cb0: 47a8 blx r5 } hri_sercomusart_write_CTRLA_reg(hw, SERCOM_USART_CTRLA_SWRST | mode); } hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); cb2: 4620 mov r0, r4 cb4: 2101 movs r1, #1 cb6: 47a8 blx r5 ((Sercom *)hw)->USART.CTRLA.reg = data; cb8: 4b0e ldr r3, [pc, #56] ; (cf4 <_usart_init+0x80>) cba: 6023 str r3, [r4, #0] hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); cbc: 2103 movs r1, #3 cbe: 47a8 blx r5 } static inline void hri_sercomusart_write_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t data) { SERCOM_CRITICAL_SECTION_ENTER(); ((Sercom *)hw)->USART.CTRLB.reg = data; cc0: f44f 3340 mov.w r3, #196608 ; 0x30000 cc4: 6063 str r3, [r4, #4] hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); cc6: 211f movs r1, #31 cc8: 47a8 blx r5 } static inline void hri_sercomusart_write_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t data) { SERCOM_CRITICAL_SECTION_ENTER(); ((Sercom *)hw)->USART.CTRLC.reg = data; cca: 4b0b ldr r3, [pc, #44] ; (cf8 <_usart_init+0x84>) ccc: 60a3 str r3, [r4, #8] } static inline void hri_sercomusart_write_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t data) { SERCOM_CRITICAL_SECTION_ENTER(); ((Sercom *)hw)->USART.BAUD.reg = data; cce: f64f 43b9 movw r3, #64697 ; 0xfcb9 cd2: 81a3 strh r3, [r4, #12] } static inline void hri_sercomusart_write_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t data) { SERCOM_CRITICAL_SECTION_ENTER(); ((Sercom *)hw)->USART.RXPL.reg = data; cd4: 2300 movs r3, #0 cd6: 73a3 strb r3, [r4, #14] hri_sercomusart_write_RXPL_reg(hw, _usarts[i].rxpl); hri_sercomusart_write_DBGCTRL_reg(hw, _usarts[i].debug_ctrl); return ERR_NONE; } cd8: 4618 mov r0, r3 } static inline void hri_sercomusart_write_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t data) { SERCOM_CRITICAL_SECTION_ENTER(); ((Sercom *)hw)->USART.DBGCTRL.reg = data; cda: f884 3030 strb.w r3, [r4, #48] ; 0x30 cde: bd38 pop {r3, r4, r5, pc} ce0: 00000c3d .word 0x00000c3d ce4: 00001074 .word 0x00001074 ce8: 000004b9 .word 0x000004b9 cec: 00000c0d .word 0x00000c0d cf0: 00000c29 .word 0x00000c29 cf4: 40100004 .word 0x40100004 cf8: 00700002 .word 0x00700002 00000cfc <_usart_sync_init>: { cfc: b570 push {r4, r5, r6, lr} ASSERT(device); cfe: 4605 mov r5, r0 d00: 3800 subs r0, #0 { d02: 460c mov r4, r1 ASSERT(device); d04: 4b05 ldr r3, [pc, #20] ; (d1c <_usart_sync_init+0x20>) d06: 4906 ldr r1, [pc, #24] ; (d20 <_usart_sync_init+0x24>) d08: bf18 it ne d0a: 2001 movne r0, #1 d0c: 22bb movs r2, #187 ; 0xbb d0e: 4798 blx r3 device->hw = hw; d10: 602c str r4, [r5, #0] return _usart_init(hw); d12: 4620 mov r0, r4 d14: 4b03 ldr r3, [pc, #12] ; (d24 <_usart_sync_init+0x28>) } d16: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} return _usart_init(hw); d1a: 4718 bx r3 d1c: 000004b9 .word 0x000004b9 d20: 00001074 .word 0x00001074 d24: 00000c75 .word 0x00000c75 00000d28 <_usart_sync_write_byte>: hri_sercomusart_write_DATA_reg(device->hw, data); d28: 6803 ldr r3, [r0, #0] ((Sercom *)hw)->USART.DATA.reg = data; d2a: 6299 str r1, [r3, #40] ; 0x28 } d2c: 4770 bx lr 00000d2e <_usart_sync_read_byte>: return hri_sercomusart_read_DATA_reg(device->hw); d2e: 6803 ldr r3, [r0, #0] return ((Sercom *)hw)->USART.DATA.reg; d30: 6a98 ldr r0, [r3, #40] ; 0x28 } d32: b2c0 uxtb r0, r0 d34: 4770 bx lr 00000d36 <_usart_sync_is_ready_to_send>: return hri_sercomusart_get_interrupt_DRE_bit(device->hw); d36: 6803 ldr r3, [r0, #0] return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; d38: 7e18 ldrb r0, [r3, #24] } d3a: f000 0001 and.w r0, r0, #1 d3e: 4770 bx lr 00000d40 <_usart_sync_is_transmit_done>: return hri_sercomusart_get_interrupt_TXC_bit(device->hw); d40: 6803 ldr r3, [r0, #0] return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; d42: 7e18 ldrb r0, [r3, #24] } d44: f3c0 0040 ubfx r0, r0, #1, #1 d48: 4770 bx lr 00000d4a <_usart_sync_is_byte_received>: return hri_sercomusart_get_interrupt_RXC_bit(device->hw); d4a: 6803 ldr r3, [r0, #0] return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; d4c: 7e18 ldrb r0, [r3, #24] } d4e: f3c0 0080 ubfx r0, r0, #2, #1 d52: 4770 bx lr 00000d54 <_spi_m_sync_init>: return NULL; } int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw) { d54: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} uint8_t n = _sercom_get_hardware_index((const void *)hw_addr); d58: 4b44 ldr r3, [pc, #272] ; (e6c <_spi_m_sync_init+0x118>) return NULL; d5a: 4d45 ldr r5, [pc, #276] ; (e70 <_spi_m_sync_init+0x11c>) { d5c: 4607 mov r7, r0 uint8_t n = _sercom_get_hardware_index((const void *)hw_addr); d5e: 4608 mov r0, r1 { d60: 460c mov r4, r1 uint8_t n = _sercom_get_hardware_index((const void *)hw_addr); d62: 4798 blx r3 return NULL; d64: 2806 cmp r0, #6 d66: bf18 it ne d68: 2500 movne r5, #0 const struct sercomspi_regs_cfg *regs = _spi_get_regs((uint32_t)hw); ASSERT(dev && hw); d6a: 2f00 cmp r7, #0 d6c: d05d beq.n e2a <_spi_m_sync_init+0xd6> d6e: 1e20 subs r0, r4, #0 d70: bf18 it ne d72: 2001 movne r0, #1 d74: 4e3f ldr r6, [pc, #252] ; (e74 <_spi_m_sync_init+0x120>) d76: 4940 ldr r1, [pc, #256] ; (e78 <_spi_m_sync_init+0x124>) d78: f640 123f movw r2, #2367 ; 0x93f d7c: 47b0 blx r6 if (regs == NULL) { d7e: 46b0 mov r8, r6 d80: 2d00 cmp r5, #0 d82: d070 beq.n e66 <_spi_m_sync_init+0x112> return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg; d84: 69e3 ldr r3, [r4, #28] d86: 4e3d ldr r6, [pc, #244] ; (e7c <_spi_m_sync_init+0x128>) return ERR_INVALID_ARG; } if (!hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { d88: f013 0f01 tst.w r3, #1 d8c: d113 bne.n db6 <_spi_m_sync_init+0x62> hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); d8e: 2103 movs r1, #3 d90: 4620 mov r0, r4 uint32_t mode = regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk; d92: f8d5 9000 ldr.w r9, [r5] d96: 47b0 blx r6 tmp = ((Sercom *)hw)->SPI.CTRLA.reg; d98: 6823 ldr r3, [r4, #0] if (hri_sercomspi_get_CTRLA_reg(hw, SERCOM_SPI_CTRLA_ENABLE)) { d9a: 079b lsls r3, r3, #30 uint32_t mode = regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk; d9c: f009 091c and.w r9, r9, #28 if (hri_sercomspi_get_CTRLA_reg(hw, SERCOM_SPI_CTRLA_ENABLE)) { da0: d503 bpl.n daa <_spi_m_sync_init+0x56> hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); da2: 4b37 ldr r3, [pc, #220] ; (e80 <_spi_m_sync_init+0x12c>) da4: 4798 blx r3 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_ENABLE); da6: 2102 movs r1, #2 da8: 47b0 blx r6 } hri_sercomspi_write_CTRLA_reg(hw, SERCOM_SPI_CTRLA_SWRST | mode); daa: f049 0301 orr.w r3, r9, #1 ((Sercom *)hw)->SPI.CTRLA.reg = data; dae: 6023 str r3, [r4, #0] hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); db0: 2103 movs r1, #3 db2: 4620 mov r0, r4 db4: 47b0 blx r6 } hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); db6: 2101 movs r1, #1 db8: 4620 mov r0, r4 dba: 47b0 blx r6 dev->prvt = hw; if ((regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk) == SERCOM_USART_CTRLA_MODE_SPI_SLAVE) { dbc: 682b ldr r3, [r5, #0] dbe: f8df 90c4 ldr.w r9, [pc, #196] ; e84 <_spi_m_sync_init+0x130> dev->prvt = hw; dc2: 603c str r4, [r7, #0] if ((regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk) == SERCOM_USART_CTRLA_MODE_SPI_SLAVE) { dc4: f003 031c and.w r3, r3, #28 dc8: 2b08 cmp r3, #8 dca: d130 bne.n e2e <_spi_m_sync_init+0xda> ASSERT(hw && regs); dcc: 492a ldr r1, [pc, #168] ; (e78 <_spi_m_sync_init+0x124>) dce: 2001 movs r0, #1 dd0: f640 121d movw r2, #2333 ; 0x91d dd4: 47c0 blx r8 hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST)); dd6: 682b ldr r3, [r5, #0] hri_sercomspi_write_CTRLA_reg( dd8: ea03 0309 and.w r3, r3, r9 ((Sercom *)hw)->SPI.CTRLA.reg = data; ddc: 6023 str r3, [r4, #0] hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); dde: 2103 movs r1, #3 de0: 4620 mov r0, r4 de2: 47b0 blx r6 (regs->ctrlb & ~(SERCOM_SPI_CTRLB_MSSEN)) de4: 686b ldr r3, [r5, #4] | (SERCOM_SPI_CTRLB_RXEN | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN)); de6: f423 3308 bic.w r3, r3, #139264 ; 0x22000 dea: f423 7310 bic.w r3, r3, #576 ; 0x240 hri_sercomspi_write_CTRLB_reg(hw, dee: f443 3300 orr.w r3, r3, #131072 ; 0x20000 df2: f443 7310 orr.w r3, r3, #576 ; 0x240 ((Sercom *)hw)->SPI.CTRLB.reg = data; df6: 6063 str r3, [r4, #4] hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); df8: 2117 movs r1, #23 dfa: 47b0 blx r6 hri_sercomspi_write_ADDR_reg(hw, regs->addr); dfc: 68ab ldr r3, [r5, #8] ((Sercom *)hw)->SPI.ADDR.reg = data; dfe: 6263 str r3, [r4, #36] ; 0x24 hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl); e00: 7b6b ldrb r3, [r5, #13] ((Sercom *)hw)->SPI.DBGCTRL.reg = data; e02: f884 3030 strb.w r3, [r4, #48] ; 0x30 return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg; e06: 69e3 ldr r3, [r4, #28] while (hri_sercomspi_is_syncing(hw, 0xFFFFFFFF)) e08: 2b00 cmp r3, #0 e0a: d1fc bne.n e06 <_spi_m_sync_init+0xb2> } else { _spi_load_regs_master(hw, regs); } /* Load character size from default hardware configuration */ dev->char_size = ((regs->ctrlb & SERCOM_SPI_CTRLB_CHSIZE_Msk) == 0) ? 1 : 2; e0c: 686b ldr r3, [r5, #4] e0e: f013 0f07 tst.w r3, #7 e12: bf0c ite eq e14: 2301 moveq r3, #1 e16: 2302 movne r3, #2 e18: 713b strb r3, [r7, #4] dev->dummy_byte = regs->dummy_byte; e1a: 7bab ldrb r3, [r5, #14] e1c: 7bea ldrb r2, [r5, #15] e1e: ea43 2302 orr.w r3, r3, r2, lsl #8 e22: 80fb strh r3, [r7, #6] return ERR_NONE; e24: 2000 movs r0, #0 } e26: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} ASSERT(dev && hw); e2a: 4638 mov r0, r7 e2c: e7a2 b.n d74 <_spi_m_sync_init+0x20> ASSERT(hw && regs); e2e: 4912 ldr r1, [pc, #72] ; (e78 <_spi_m_sync_init+0x124>) e30: 2001 movs r0, #1 e32: f640 1209 movw r2, #2313 ; 0x909 e36: 47c0 blx r8 hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST)); e38: 682b ldr r3, [r5, #0] hri_sercomspi_write_CTRLA_reg( e3a: ea03 0309 and.w r3, r3, r9 ((Sercom *)hw)->SPI.CTRLA.reg = data; e3e: 6023 str r3, [r4, #0] hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); e40: 2103 movs r1, #3 e42: 4620 mov r0, r4 e44: 47b0 blx r6 (regs->ctrlb e46: 686b ldr r3, [r5, #4] | (SERCOM_SPI_CTRLB_RXEN)); e48: f423 3338 bic.w r3, r3, #188416 ; 0x2e000 e4c: f423 7310 bic.w r3, r3, #576 ; 0x240 hri_sercomspi_write_CTRLB_reg( e50: f443 3300 orr.w r3, r3, #131072 ; 0x20000 ((Sercom *)hw)->SPI.CTRLB.reg = data; e54: 6063 str r3, [r4, #4] hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); e56: 2117 movs r1, #23 e58: 47b0 blx r6 hri_sercomspi_write_BAUD_reg(hw, regs->baud); e5a: 7b2b ldrb r3, [r5, #12] ((Sercom *)hw)->SPI.BAUD.reg = data; e5c: 7323 strb r3, [r4, #12] hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl); e5e: 7b6b ldrb r3, [r5, #13] ((Sercom *)hw)->SPI.DBGCTRL.reg = data; e60: f884 3030 strb.w r3, [r4, #48] ; 0x30 } e64: e7d2 b.n e0c <_spi_m_sync_init+0xb8> return ERR_INVALID_ARG; e66: f06f 000c mvn.w r0, #12 e6a: e7dc b.n e26 <_spi_m_sync_init+0xd2> e6c: 00000c3d .word 0x00000c3d e70: 000010c8 .word 0x000010c8 e74: 000004b9 .word 0x000004b9 e78: 00001074 .word 0x00001074 e7c: 00000c05 .word 0x00000c05 e80: 00000c15 .word 0x00000c15 e84: fffffefc .word 0xfffffefc 00000e88 <_spi_m_sync_trans>: return ERR_NONE; } int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg) { e88: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} void * hw = dev->prvt; e8c: 6804 ldr r4, [r0, #0] int32_t rc = 0; struct _spi_trans_ctrl ctrl = {msg->txbuf, msg->rxbuf, 0, 0, dev->char_size}; e8e: f890 8004 ldrb.w r8, [r0, #4] ASSERT(dev && hw); e92: 4b2a ldr r3, [pc, #168] ; (f3c <_spi_m_sync_trans+0xb4>) { e94: 4607 mov r7, r0 ASSERT(dev && hw); e96: 1e20 subs r0, r4, #0 struct _spi_trans_ctrl ctrl = {msg->txbuf, msg->rxbuf, 0, 0, dev->char_size}; e98: e9d1 6500 ldrd r6, r5, [r1] ASSERT(dev && hw); e9c: f640 22a3 movw r2, #2723 ; 0xaa3 ea0: bf18 it ne ea2: 2001 movne r0, #1 { ea4: 4689 mov r9, r1 ASSERT(dev && hw); ea6: 4926 ldr r1, [pc, #152] ; (f40 <_spi_m_sync_trans+0xb8>) ea8: 4798 blx r3 return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg; eaa: 69e2 ldr r2, [r4, #28] /* If settings are not applied (pending), we can not go on */ if (hri_sercomspi_is_syncing( eac: f012 0207 ands.w r2, r2, #7 eb0: d13e bne.n f30 <_spi_m_sync_trans+0xa8> hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); eb2: 4b24 ldr r3, [pc, #144] ; (f44 <_spi_m_sync_trans+0xbc>) eb4: 2103 movs r1, #3 eb6: 4620 mov r0, r4 eb8: 4798 blx r3 tmp = ((Sercom *)hw)->SPI.CTRLA.reg; eba: 6823 ldr r3, [r4, #0] hw, (SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE | SERCOM_SPI_SYNCBUSY_CTRLB))) { return ERR_BUSY; } /* SPI must be enabled to start synchronous transfer */ if (!hri_sercomspi_get_CTRLA_ENABLE_bit(hw)) { ebc: 0799 lsls r1, r3, #30 ebe: d53a bpl.n f36 <_spi_m_sync_trans+0xae> struct _spi_trans_ctrl ctrl = {msg->txbuf, msg->rxbuf, 0, 0, dev->char_size}; ec0: 4611 mov r1, r2 return ((Sercom *)hw)->SPI.INTFLAG.reg; ec2: 7e23 ldrb r3, [r4, #24] ec4: b2d8 uxtb r0, r3 if (!(iflag & SERCOM_SPI_INTFLAG_RXC)) { ec6: 075b lsls r3, r3, #29 ec8: d40f bmi.n eea <_spi_m_sync_trans+0x62> uint32_t iflag = hri_sercomspi_read_INTFLAG_reg(hw); if (!_spi_rx_check_and_receive(hw, iflag, &ctrl)) { /* In master mode, do not start next byte before previous byte received * to make better output waveform */ if (ctrl.rxcnt >= ctrl.txcnt) { eca: 428a cmp r2, r1 ecc: d818 bhi.n f00 <_spi_m_sync_trans+0x78> if (!(SERCOM_SPI_INTFLAG_DRE & iflag)) { ece: 07c3 lsls r3, r0, #31 ed0: d516 bpl.n f00 <_spi_m_sync_trans+0x78> _spi_tx_check_and_send(hw, iflag, &ctrl, dev->dummy_byte); ed2: 88fb ldrh r3, [r7, #6] if (ctrl->txbuf) { ed4: b136 cbz r6, ee4 <_spi_m_sync_trans+0x5c> if (ctrl->char_size > 1) { ed6: f1b8 0f01 cmp.w r8, #1 data = *ctrl->txbuf++; eda: 7833 ldrb r3, [r6, #0] data |= (*ctrl->txbuf) << 8; edc: bf8c ite hi ede: f836 3b02 ldrhhi.w r3, [r6], #2 data = *ctrl->txbuf++; ee2: 3601 addls r6, #1 ctrl->txcnt++; ee4: 3201 adds r2, #1 ((Sercom *)hw)->SPI.DATA.reg = data; ee6: 62a3 str r3, [r4, #40] ; 0x28 } ee8: e00a b.n f00 <_spi_m_sync_trans+0x78> return ((Sercom *)hw)->SPI.DATA.reg; eea: 6aa3 ldr r3, [r4, #40] ; 0x28 if (ctrl->rxbuf) { eec: b13d cbz r5, efe <_spi_m_sync_trans+0x76> if (ctrl->char_size > 1) { eee: f1b8 0f01 cmp.w r8, #1 *ctrl->rxbuf++ = (uint8_t)data; ef2: 702b strb r3, [r5, #0] *ctrl->rxbuf++ = (uint8_t)(data >> 8); ef4: bf85 ittet hi ef6: 0a1b lsrhi r3, r3, #8 ef8: 706b strbhi r3, [r5, #1] *ctrl->rxbuf++ = (uint8_t)data; efa: 3501 addls r5, #1 *ctrl->rxbuf++ = (uint8_t)(data >> 8); efc: 3502 addhi r5, #2 ctrl->rxcnt++; efe: 3101 adds r1, #1 if (SERCOM_SPI_INTFLAG_ERROR & iflag) { f00: 0600 lsls r0, r0, #24 f02: d407 bmi.n f14 <_spi_m_sync_trans+0x8c> rc = _spi_err_check(iflag, hw); if (rc < 0) { break; } if (ctrl.txcnt >= msg->size && ctrl.rxcnt >= msg->size) { f04: f8d9 3008 ldr.w r3, [r9, #8] f08: 4293 cmp r3, r2 f0a: d8da bhi.n ec2 <_spi_m_sync_trans+0x3a> f0c: 428b cmp r3, r1 f0e: d8d8 bhi.n ec2 <_spi_m_sync_trans+0x3a> rc = ctrl.txcnt; f10: 4610 mov r0, r2 while (!(hri_sercomspi_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE))) { f12: e006 b.n f22 <_spi_m_sync_trans+0x9a> } static inline void hri_sercomspi_clear_STATUS_reg(const void *const hw, hri_sercomspi_status_reg_t mask) { SERCOM_CRITICAL_SECTION_ENTER(); ((Sercom *)hw)->SPI.STATUS.reg = mask; f14: f64f 73ff movw r3, #65535 ; 0xffff f18: 8363 strh r3, [r4, #26] ((Sercom *)hw)->SPI.INTFLAG.reg = mask; f1a: 2380 movs r3, #128 ; 0x80 f1c: 7623 strb r3, [r4, #24] return ERR_OVERFLOW; f1e: f06f 0012 mvn.w r0, #18 tmp = ((Sercom *)hw)->SPI.INTFLAG.reg; f22: 7e23 ldrb r3, [r4, #24] while (!(hri_sercomspi_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE))) { f24: 079b lsls r3, r3, #30 f26: d0fc beq.n f22 <_spi_m_sync_trans+0x9a> ((Sercom *)hw)->SPI.INTFLAG.reg = mask; f28: 2303 movs r3, #3 f2a: 7623 strb r3, [r4, #24] } /* Wait until SPI bus idle */ _spi_wait_bus_idle(hw); return rc; } f2c: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} return ERR_BUSY; f30: f06f 0003 mvn.w r0, #3 f34: e7fa b.n f2c <_spi_m_sync_trans+0xa4> return ERR_NOT_INITIALIZED; f36: f06f 0013 mvn.w r0, #19 f3a: e7f7 b.n f2c <_spi_m_sync_trans+0xa4> f3c: 000004b9 .word 0x000004b9 f40: 00001074 .word 0x00001074 f44: 00000c05 .word 0x00000c05 00000f48 : /** * Initializes MCU, drivers and middleware in the project **/ void atmel_start_init(void) { f48: b510 push {r4, lr} system_init(); f4a: 4b04 ldr r3, [pc, #16] ; (f5c ) f4c: 4798 blx r3 sd_mmc_stack_init(); f4e: 4b04 ldr r3, [pc, #16] ; (f60 ) f50: 4798 blx r3 diskio_init(); } f52: e8bd 4010 ldmia.w sp!, {r4, lr} diskio_init(); f56: 4b03 ldr r3, [pc, #12] ; (f64 ) f58: 4718 bx r3 f5a: bf00 nop f5c: 00000bd5 .word 0x00000bd5 f60: 000002e9 .word 0x000002e9 f64: 00000751 .word 0x00000751 00000f68 <__libc_init_array>: f68: b570 push {r4, r5, r6, lr} f6a: 4d0d ldr r5, [pc, #52] ; (fa0 <__libc_init_array+0x38>) f6c: 4c0d ldr r4, [pc, #52] ; (fa4 <__libc_init_array+0x3c>) f6e: 1b64 subs r4, r4, r5 f70: 10a4 asrs r4, r4, #2 f72: 2600 movs r6, #0 f74: 42a6 cmp r6, r4 f76: d109 bne.n f8c <__libc_init_array+0x24> f78: 4d0b ldr r5, [pc, #44] ; (fa8 <__libc_init_array+0x40>) f7a: 4c0c ldr r4, [pc, #48] ; (fac <__libc_init_array+0x44>) f7c: f000 f8ae bl 10dc <_init> f80: 1b64 subs r4, r4, r5 f82: 10a4 asrs r4, r4, #2 f84: 2600 movs r6, #0 f86: 42a6 cmp r6, r4 f88: d105 bne.n f96 <__libc_init_array+0x2e> f8a: bd70 pop {r4, r5, r6, pc} f8c: f855 3b04 ldr.w r3, [r5], #4 f90: 4798 blx r3 f92: 3601 adds r6, #1 f94: e7ee b.n f74 <__libc_init_array+0xc> f96: f855 3b04 ldr.w r3, [r5], #4 f9a: 4798 blx r3 f9c: 3601 adds r6, #1 f9e: e7f2 b.n f86 <__libc_init_array+0x1e> fa0: 000010e8 .word 0x000010e8 fa4: 000010e8 .word 0x000010e8 fa8: 000010e8 .word 0x000010e8 fac: 000010ec .word 0x000010ec 00000fb0 : fb0: 440a add r2, r1 fb2: 4291 cmp r1, r2 fb4: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff fb8: d100 bne.n fbc fba: 4770 bx lr fbc: b510 push {r4, lr} fbe: f811 4b01 ldrb.w r4, [r1], #1 fc2: f803 4f01 strb.w r4, [r3, #1]! fc6: 4291 cmp r1, r2 fc8: d1f9 bne.n fbe fca: bd10 pop {r4, pc} 00000fcc : fcc: 4402 add r2, r0 fce: 4603 mov r3, r0 fd0: 4293 cmp r3, r2 fd2: d100 bne.n fd6 fd4: 4770 bx lr fd6: f803 1b01 strb.w r1, [r3], #1 fda: e7f9 b.n fd0 fdc: 682f2e2e .word 0x682f2e2e fe0: 732f6c61 .word 0x732f6c61 fe4: 682f6372 .word 0x682f6372 fe8: 635f6c61 .word 0x635f6c61 fec: 6e656c61 .word 0x6e656c61 ff0: 2e726164 .word 0x2e726164 ff4: 0063 .short 0x0063 ff6: 2e2e .short 0x2e2e ff8: 6c61682f .word 0x6c61682f ffc: 6372732f .word 0x6372732f 1000: 6c61682f .word 0x6c61682f 1004: 6970735f .word 0x6970735f 1008: 735f6d5f .word 0x735f6d5f 100c: 2e636e79 .word 0x2e636e79 1010: 0063 .short 0x0063 1012: 2e2e .short 0x2e2e 1014: 6c61682f .word 0x6c61682f 1018: 6372732f .word 0x6372732f 101c: 6c61682f .word 0x6c61682f 1020: 69636d5f .word 0x69636d5f 1024: 6e79735f .word 0x6e79735f 1028: 00632e63 .word 0x00632e63 102c: 682f2e2e .word 0x682f2e2e 1030: 732f6c70 .word 0x732f6c70 1034: 2f636864 .word 0x2f636864 1038: 5f6c7068 .word 0x5f6c7068 103c: 63686473 .word 0x63686473 1040: 632e .short 0x632e 1042: 00 .byte 0x00 1043: 2e .byte 0x2e 1044: 61682f2e .word 0x61682f2e 1048: 72732f6c .word 0x72732f6c 104c: 61682f63 .word 0x61682f63 1050: 73755f6c .word 0x73755f6c 1054: 5f747261 .word 0x5f747261 1058: 636e7973 .word 0x636e7973 105c: 632e .short 0x632e 105e: 00 .byte 0x00 105f: 2e .byte 0x2e 1060: 70682f2e .word 0x70682f2e 1064: 74722f6c .word 0x74722f6c 1068: 70682f63 .word 0x70682f63 106c: 74725f6c .word 0x74725f6c 1070: 00632e63 .word 0x00632e63 1074: 682f2e2e .word 0x682f2e2e 1078: 732f6c70 .word 0x732f6c70 107c: 6f637265 .word 0x6f637265 1080: 70682f6d .word 0x70682f6d 1084: 65735f6c .word 0x65735f6c 1088: 6d6f6372 .word 0x6d6f6372 108c: 0000632e .word 0x0000632e 1090: 40003000 .word 0x40003000 1094: 40003400 .word 0x40003400 1098: 41012000 .word 0x41012000 109c: 41014000 .word 0x41014000 10a0: 43000000 .word 0x43000000 10a4: 43000400 .word 0x43000400 10a8: 43000800 .word 0x43000800 10ac: 43000c00 .word 0x43000c00 000010b0 <_i2cms>: ... 000010c8 : 10c8: 0020000c 00020000 00000000 01ff00fe .. ............. 10d8: 00000006 .... 000010dc <_init>: 10dc: b5f8 push {r3, r4, r5, r6, r7, lr} 10de: bf00 nop 10e0: bcf8 pop {r3, r4, r5, r6, r7} 10e2: bc08 pop {r3} 10e4: 469e mov lr, r3 10e6: 4770 bx lr 000010e8 <__frame_dummy_init_array_entry>: 10e8: 0289 0000 .... 000010ec <_fini>: 10ec: b5f8 push {r3, r4, r5, r6, r7, lr} 10ee: bf00 nop 10f0: bcf8 pop {r3, r4, r5, r6, r7} 10f2: bc08 pop {r3} 10f4: 469e mov lr, r3 10f6: 4770 bx lr 000010f8 <__do_global_dtors_aux_fini_array_entry>: 10f8: 0265 0000 e...