test1.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .text 000015ac 00000000 00000000 00010000 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 1 .relocate 00000000 20000000 20000000 000115ac 2**0 CONTENTS 2 .bkupram 00000000 47000000 47000000 000115ac 2**0 CONTENTS 3 .qspi 00000000 04000000 04000000 000115ac 2**0 CONTENTS 4 .bss 000000d8 20000000 20000000 00020000 2**2 ALLOC 5 .stack 00010000 200000d8 200000d8 00020000 2**0 ALLOC 6 .ARM.attributes 0000002e 00000000 00000000 000115ac 2**0 CONTENTS, READONLY 7 .comment 00000064 00000000 00000000 000115da 2**0 CONTENTS, READONLY 8 .debug_info 0001ba43 00000000 00000000 0001163e 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 9 .debug_abbrev 000031d2 00000000 00000000 0002d081 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 10 .debug_loclists 00006082 00000000 00000000 00030253 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 11 .debug_aranges 00000a70 00000000 00000000 000362d5 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 12 .debug_rnglists 00000d78 00000000 00000000 00036d45 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_macro 0000b5d9 00000000 00000000 00037abd 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_line 0001370d 00000000 00000000 00043096 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_str 00119a71 00000000 00000000 000567a3 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_frame 00001b9c 00000000 00000000 00170214 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 00000000 : } static inline void hri_eic_clear_CTRLA_ENABLE_bit(const void *const hw) { EIC_CRITICAL_SECTION_ENTER(); ((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_ENABLE; 0: d8 00 01 20 71 0c 00 00 6d 0c 00 00 6d 0c 00 00 ... q...m...m... hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); 10: 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 00 00 00 00 m...m...m....... ... int32_t timer_add_task(struct timer_descriptor *const descr, struct timer_task *const task) { ASSERT(descr && task); descr->flags |= TIMER_FLAG_QUEUE_IS_TAKEN; if (is_list_element(&descr->tasks, task)) { 2c: 6d 0c 00 00 6d 0c 00 00 00 00 00 00 6d 0c 00 00 m...m.......m... descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; 3c: 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 m...m...m...m... ASSERT(false); return ERR_ALREADY_INITIALIZED; } task->time_label = descr->time; 4c: 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 m...m...m...m... timer_add_timer_task(&descr->tasks, task, descr->time); descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; 5c: 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 m...m...m...m... if (descr->flags & TIMER_FLAG_INTERRUPT_TRIGERRED) { CRITICAL_SECTION_ENTER() 6c: 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 m...m...m...m... descr->flags &= ~TIMER_FLAG_INTERRUPT_TRIGERRED; _timer_set_irq(&descr->device); CRITICAL_SECTION_LEAVE() 7c: 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 m...m...m...m... } return ERR_NONE; 8c: 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 m...m...m...m... 9c: 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 m...m...m...m... static inline void hri_sercomi2cm_write_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) { uint32_t tmp; SERCOM_CRITICAL_SECTION_ENTER(); tmp = ((Sercom *)hw)->I2CM.BAUD.reg; ac: 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 m...m...m...m... if (i2c_dev->service.mode == I2C_STANDARD_MODE) { tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) / (2 * baudrate)); hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); } else if (i2c_dev->service.mode == I2C_FASTMODE) { tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) bc: 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 m...m...m...m... cc: 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 m...m...m...m... dc: 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 00 00 00 00 m...m...m....... ... f4: 29 05 00 00 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 )...m...m...m... / (2 * baudrate)); 104: 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 m...m...m...m... tmp &= ~SERCOM_I2CM_BAUD_BAUD_Msk; tmp |= SERCOM_I2CM_BAUD_BAUD(data); 114: 6d 0c 00 00 c9 0b 00 00 35 0c 00 00 3d 0c 00 00 m.......5...=... hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); } else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) { tmp = (clkrate - 2 * baudrate) / (2 * baudrate); 124: 45 0c 00 00 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 E...m...m...m... static inline void hri_sercomi2cm_write_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) { uint32_t tmp; SERCOM_CRITICAL_SECTION_ENTER(); tmp = ((Sercom *)hw)->I2CM.BAUD.reg; tmp &= ~SERCOM_I2CM_BAUD_HSBAUD_Msk; 134: 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 m...m...m...m... return ERR_DENIED; 144: 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 m...m...m...m... hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp); } else { /* error baudrate */ return ERR_INVALID_ARG; 154: 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 m...m...m...m... 164: 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 m...m...m...m... 174: 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 m...m...m...m... 184: 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 m...m...m...m... 194: 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 m...m...m...m... 1a4: 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 m...m...m...m... 1b4: 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 m...m...m...m... 1c4: 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 m...m...m...m... 1d4: 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 m...m...m...m... 1e4: 6d 0c 00 00 6d 0c 00 00 a1 13 00 00 6d 0c 00 00 m...m.......m... 1f4: 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 m...m...m...m... 204: 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 m...m...m...m... 214: 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 m...m...m...m... 224: 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 m...m...m...m... 234: 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 m...m...m...m... 244: 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 m...m...m...m... 254: 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 6d 0c 00 00 m...m...m...m... 00000264 : 264: 4803 ldr r0, [pc, #12] ; (274 ) 266: 4b04 ldr r3, [pc, #16] ; (278 ) 268: 4283 cmp r3, r0 26a: d002 beq.n 272 26c: 4b03 ldr r3, [pc, #12] ; (27c ) 26e: b103 cbz r3, 272 270: 4718 bx r3 272: 4770 bx lr 274: 000015ac .word 0x000015ac 278: 000015ac .word 0x000015ac 27c: 00000000 .word 0x00000000 00000280 : 280: 4805 ldr r0, [pc, #20] ; (298 ) 282: 4b06 ldr r3, [pc, #24] ; (29c ) 284: 1a1b subs r3, r3, r0 286: 0fd9 lsrs r1, r3, #31 288: eb01 01a3 add.w r1, r1, r3, asr #2 28c: 1049 asrs r1, r1, #1 28e: d002 beq.n 296 290: 4b03 ldr r3, [pc, #12] ; (2a0 ) 292: b103 cbz r3, 296 294: 4718 bx r3 296: 4770 bx lr 298: 000015ac .word 0x000015ac 29c: 000015ac .word 0x000015ac 2a0: 00000000 .word 0x00000000 000002a4 <__do_global_dtors_aux>: 2a4: b510 push {r4, lr} 2a6: 4c06 ldr r4, [pc, #24] ; (2c0 <__do_global_dtors_aux+0x1c>) 2a8: 7823 ldrb r3, [r4, #0] 2aa: b943 cbnz r3, 2be <__do_global_dtors_aux+0x1a> 2ac: f7ff ffda bl 264 2b0: 4b04 ldr r3, [pc, #16] ; (2c4 <__do_global_dtors_aux+0x20>) 2b2: b113 cbz r3, 2ba <__do_global_dtors_aux+0x16> 2b4: 4804 ldr r0, [pc, #16] ; (2c8 <__do_global_dtors_aux+0x24>) 2b6: f3af 8000 nop.w 2ba: 2301 movs r3, #1 2bc: 7023 strb r3, [r4, #0] 2be: bd10 pop {r4, pc} 2c0: 20000000 .word 0x20000000 2c4: 00000000 .word 0x00000000 2c8: 000015ac .word 0x000015ac 000002cc : 2cc: b508 push {r3, lr} 2ce: 4b04 ldr r3, [pc, #16] ; (2e0 ) 2d0: b11b cbz r3, 2da 2d2: 4904 ldr r1, [pc, #16] ; (2e4 ) 2d4: 4804 ldr r0, [pc, #16] ; (2e8 ) 2d6: f3af 8000 nop.w 2da: e8bd 4008 ldmia.w sp!, {r3, lr} 2de: e7cf b.n 280 2e0: 00000000 .word 0x00000000 2e4: 20000004 .word 0x20000004 2e8: 000015ac .word 0x000015ac 000002ec : while (((Eic *)hw)->SYNCBUSY.reg & reg) { 2ec: 4a02 ldr r2, [pc, #8] ; (2f8 ) 2ee: 6853 ldr r3, [r2, #4] 2f0: 4203 tst r3, r0 2f2: d1fc bne.n 2ee } 2f4: 4770 bx lr 2f6: bf00 nop 2f8: 40002800 .word 0x40002800 000002fc <_ext_irq_init>: return ((Eic *)hw)->SYNCBUSY.reg & reg; 2fc: 4917 ldr r1, [pc, #92] ; (35c <_ext_irq_init+0x60>) /** * \brief Initialize external interrupt module */ int32_t _ext_irq_init(void (*cb)(const uint32_t pin)) { 2fe: b538 push {r3, r4, r5, lr} 300: 684b ldr r3, [r1, #4] 302: 4d17 ldr r5, [pc, #92] ; (360 <_ext_irq_init+0x64>) if (!hri_eic_is_syncing(EIC, EIC_SYNCBUSY_SWRST)) { 304: f013 0f01 tst.w r3, #1 308: d110 bne.n 32c <_ext_irq_init+0x30> } static inline hri_eic_ctrla_reg_t hri_eic_get_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) { uint8_t tmp; hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); 30a: 2003 movs r0, #3 30c: 47a8 blx r5 tmp = ((Eic *)hw)->CTRLA.reg; 30e: 780b ldrb r3, [r1, #0] if (hri_eic_get_CTRLA_reg(EIC, EIC_CTRLA_ENABLE)) { 310: 079b lsls r3, r3, #30 312: d506 bpl.n 322 <_ext_irq_init+0x26> ((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_ENABLE; 314: 780b ldrb r3, [r1, #0] 316: f003 03fd and.w r3, r3, #253 ; 0xfd 31a: 700b strb r3, [r1, #0] hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); 31c: 47a8 blx r5 hri_eic_clear_CTRLA_ENABLE_bit(EIC); hri_eic_wait_for_sync(EIC, EIC_SYNCBUSY_ENABLE); 31e: 2002 movs r0, #2 320: 47a8 blx r5 } static inline void hri_eic_write_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t data) { EIC_CRITICAL_SECTION_ENTER(); ((Eic *)hw)->CTRLA.reg = data; 322: 4b0e ldr r3, [pc, #56] ; (35c <_ext_irq_init+0x60>) 324: 2201 movs r2, #1 326: 701a strb r2, [r3, #0] hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); 328: 2003 movs r0, #3 32a: 47a8 blx r5 tmp = ((Eic *)hw)->CTRLA.reg; 32c: 490b ldr r1, [pc, #44] ; (35c <_ext_irq_init+0x60>) } hri_eic_write_CTRLA_reg(EIC, EIC_CTRLA_SWRST); } hri_eic_wait_for_sync(EIC, EIC_SYNCBUSY_SWRST); 32e: 2001 movs r0, #1 330: 47a8 blx r5 332: 780b ldrb r3, [r1, #0] tmp &= ~EIC_CTRLA_CKSEL; 334: f003 03ef and.w r3, r3, #239 ; 0xef } static inline void hri_eic_write_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t data) { EIC_CRITICAL_SECTION_ENTER(); ((Eic *)hw)->NMICTRL.reg = data; 338: 2400 movs r4, #0 ((Eic *)hw)->CTRLA.reg = tmp; 33a: 700b strb r3, [r1, #0] hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); 33c: 2003 movs r0, #3 33e: 47a8 blx r5 ((Eic *)hw)->NMICTRL.reg = data; 340: 704c strb r4, [r1, #1] } static inline void hri_eic_write_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t data) { EIC_CRITICAL_SECTION_ENTER(); ((Eic *)hw)->EVCTRL.reg = data; 342: 608c str r4, [r1, #8] } static inline void hri_eic_write_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t data) { EIC_CRITICAL_SECTION_ENTER(); ((Eic *)hw)->ASYNCH.reg = data; 344: 618c str r4, [r1, #24] } static inline void hri_eic_write_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t data) { EIC_CRITICAL_SECTION_ENTER(); ((Eic *)hw)->DEBOUNCEN.reg = data; 346: 630c str r4, [r1, #48] ; 0x30 } static inline void hri_eic_write_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t data) { EIC_CRITICAL_SECTION_ENTER(); ((Eic *)hw)->DPRESCALER.reg = data; 348: 634c str r4, [r1, #52] ; 0x34 ((Eic *)hw)->CONFIG[index].reg = data; 34a: 61cc str r4, [r1, #28] 34c: 620c str r4, [r1, #32] ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_ENABLE; 34e: 780b ldrb r3, [r1, #0] 350: f043 0302 orr.w r3, r3, #2 354: 700b strb r3, [r1, #0] hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); 356: 47a8 blx r5 hri_eic_set_CTRLA_ENABLE_bit(EIC); callback = cb; return ERR_NONE; } 358: 4620 mov r0, r4 35a: bd38 pop {r3, r4, r5, pc} 35c: 40002800 .word 0x40002800 360: 000002ed .word 0x000002ed 00000364 : * \param[in] head The pointer to the head of timer task list * \param[in] task The pointer to task to add * \param[in] time Current timer time */ static void timer_add_timer_task(struct list_descriptor *list, struct timer_task *const new_task, const uint32_t time) { 364: b5f0 push {r4, r5, r6, r7, lr} * \return A pointer to the head of the given list or NULL if the list is * empty */ static inline void *list_get_head(const struct list_descriptor *const list) { return (void *)list->head; 366: 6805 ldr r5, [r0, #0] struct timer_task *it, *prev = NULL, *head = (struct timer_task *)list_get_head(list); if (!head) { 368: b91d cbnz r5, 372 list_insert_as_head(list, new_task); 36a: 4b0f ldr r3, [pc, #60] ; (3a8 ) if (it == head) { list_insert_as_head(list, new_task); } else { list_insert_after(prev, new_task); } } 36c: e8bd 40f0 ldmia.w sp!, {r4, r5, r6, r7, lr} list_insert_after(prev, new_task); 370: 4718 bx r3 if (time_left >= new_task->interval) 372: f8d1 c008 ldr.w ip, [r1, #8] 376: 462c mov r4, r5 struct timer_task *it, *prev = NULL, *head = (struct timer_task *)list_get_head(list); 378: 2600 movs r6, #0 time_left = it->interval - (0xFFFFFFFF - it->time_label) - time; 37a: f1c2 0e01 rsb lr, r2, #1 time_left = it->interval - (time - it->time_label); 37e: e9d4 3701 ldrd r3, r7, [r4, #4] if (it->time_label <= time) { 382: 4293 cmp r3, r2 time_left = it->interval - (time - it->time_label); 384: bf95 itete ls 386: 19db addls r3, r3, r7 time_left = it->interval - (0xFFFFFFFF - it->time_label) - time; 388: 4473 addhi r3, lr time_left = it->interval - (time - it->time_label); 38a: 1a9b subls r3, r3, r2 time_left = it->interval - (0xFFFFFFFF - it->time_label) - time; 38c: 19db addhi r3, r3, r7 if (time_left >= new_task->interval) 38e: 459c cmp ip, r3 390: d907 bls.n 3a2 * \return A pointer to the next list element or NULL if there is not next * element */ static inline void *list_get_next_element(const void *const element) { return element ? ((struct list_element *)element)->next : NULL; 392: 6823 ldr r3, [r4, #0] for (it = head; it; it = (struct timer_task *)list_get_next_element(it)) { 394: 4626 mov r6, r4 396: b913 cbnz r3, 39e list_insert_after(prev, new_task); 398: 4b04 ldr r3, [pc, #16] ; (3ac ) 39a: 4630 mov r0, r6 39c: e7e6 b.n 36c 39e: 461c mov r4, r3 3a0: e7ed b.n 37e if (it == head) { 3a2: 42a5 cmp r5, r4 3a4: d0e1 beq.n 36a 3a6: e7f7 b.n 398 3a8: 00000571 .word 0x00000571 3ac: 0000059d .word 0x0000059d 000003b0 : /** * \internal Process interrupts */ static void timer_process_counted(struct _timer_device *device) { 3b0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} struct timer_descriptor *timer = CONTAINER_OF(device, struct timer_descriptor, device); struct timer_task * it = (struct timer_task *)list_get_head(&timer->tasks); uint32_t time = ++timer->time; 3b4: e9d0 6504 ldrd r6, r5, [r0, #16] if ((timer->flags & TIMER_FLAG_QUEUE_IS_TAKEN) || (timer->flags & TIMER_FLAG_INTERRUPT_TRIGERRED)) { 3b8: 7e03 ldrb r3, [r0, #24] uint32_t time = ++timer->time; 3ba: 3601 adds r6, #1 if ((timer->flags & TIMER_FLAG_QUEUE_IS_TAKEN) || (timer->flags & TIMER_FLAG_INTERRUPT_TRIGERRED)) { 3bc: 07da lsls r2, r3, #31 { 3be: 4604 mov r4, r0 uint32_t time = ++timer->time; 3c0: 6106 str r6, [r0, #16] if ((timer->flags & TIMER_FLAG_QUEUE_IS_TAKEN) || (timer->flags & TIMER_FLAG_INTERRUPT_TRIGERRED)) { 3c2: d41f bmi.n 404 3c4: 7e03 ldrb r3, [r0, #24] 3c6: 079b lsls r3, r3, #30 3c8: d41c bmi.n 404 } while (it && ((time - it->time_label) >= it->interval)) { struct timer_task *tmp = it; list_remove_head(&timer->tasks); 3ca: f8df 8044 ldr.w r8, [pc, #68] ; 410 if (TIMER_TASK_REPEAT == tmp->mode) { tmp->time_label = time; timer_add_timer_task(&timer->tasks, tmp, time); 3ce: f8df 9044 ldr.w r9, [pc, #68] ; 414 list_remove_head(&timer->tasks); 3d2: f100 0714 add.w r7, r0, #20 while (it && ((time - it->time_label) >= it->interval)) { 3d6: b1cd cbz r5, 40c 3d8: 686b ldr r3, [r5, #4] 3da: 68aa ldr r2, [r5, #8] 3dc: 1af3 subs r3, r6, r3 3de: 4293 cmp r3, r2 3e0: d314 bcc.n 40c list_remove_head(&timer->tasks); 3e2: 4638 mov r0, r7 3e4: 47c0 blx r8 if (TIMER_TASK_REPEAT == tmp->mode) { 3e6: 7c2b ldrb r3, [r5, #16] 3e8: 2b01 cmp r3, #1 3ea: d104 bne.n 3f6 tmp->time_label = time; 3ec: 606e str r6, [r5, #4] timer_add_timer_task(&timer->tasks, tmp, time); 3ee: 4632 mov r2, r6 3f0: 4629 mov r1, r5 3f2: 4638 mov r0, r7 3f4: 47c8 blx r9 return (void *)list->head; 3f6: f8d4 a014 ldr.w sl, [r4, #20] } it = (struct timer_task *)list_get_head(&timer->tasks); tmp->cb(tmp); 3fa: 68eb ldr r3, [r5, #12] 3fc: 4628 mov r0, r5 3fe: 4798 blx r3 it = (struct timer_task *)list_get_head(&timer->tasks); 400: 4655 mov r5, sl 402: e7e8 b.n 3d6 timer->flags |= TIMER_FLAG_INTERRUPT_TRIGERRED; 404: 7e23 ldrb r3, [r4, #24] 406: f043 0302 orr.w r3, r3, #2 40a: 7623 strb r3, [r4, #24] } } 40c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 410: 000005a5 .word 0x000005a5 414: 00000365 .word 0x00000365 00000418 : { 418: b538 push {r3, r4, r5, lr} 41a: 460d mov r5, r1 ASSERT(descr && hw); 41c: 4604 mov r4, r0 41e: b110 cbz r0, 426 420: 1e08 subs r0, r1, #0 422: bf18 it ne 424: 2001 movne r0, #1 426: 223b movs r2, #59 ; 0x3b 428: 4905 ldr r1, [pc, #20] ; (440 ) 42a: 4b06 ldr r3, [pc, #24] ; (444 ) 42c: 4798 blx r3 _timer_init(&descr->device, hw); 42e: 4b06 ldr r3, [pc, #24] ; (448 ) 430: 4629 mov r1, r5 432: 4620 mov r0, r4 434: 4798 blx r3 descr->device.timer_cb.period_expired = timer_process_counted; 436: 4b05 ldr r3, [pc, #20] ; (44c ) 438: 6023 str r3, [r4, #0] descr->time = 0; 43a: 2000 movs r0, #0 43c: 6120 str r0, [r4, #16] } 43e: bd38 pop {r3, r4, r5, pc} 440: 0000144c .word 0x0000144c 444: 000005b1 .word 0x000005b1 448: 00001261 .word 0x00001261 44c: 000003b1 .word 0x000003b1 00000450 : /** * \brief Sync version of I2C I/O write */ static int32_t i2c_m_sync_write(struct io_descriptor *io, const uint8_t *buf, const uint16_t n) { 450: b51f push {r0, r1, r2, r3, r4, lr} struct i2c_m_sync_desc *i2c = CONTAINER_OF(io, struct i2c_m_sync_desc, io); struct _i2c_m_msg msg; int32_t ret; msg.addr = i2c->slave_addr; 452: 8903 ldrh r3, [r0, #8] 454: f8ad 3004 strh.w r3, [sp, #4] msg.len = n; msg.flags = I2C_M_STOP; 458: f44f 4300 mov.w r3, #32768 ; 0x8000 45c: f8ad 3006 strh.w r3, [sp, #6] msg.buffer = (uint8_t *)buf; 460: 9103 str r1, [sp, #12] ret = _i2c_m_sync_transfer(&i2c->device, &msg); 462: 4b05 ldr r3, [pc, #20] ; (478 ) msg.len = n; 464: 9202 str r2, [sp, #8] ret = _i2c_m_sync_transfer(&i2c->device, &msg); 466: a901 add r1, sp, #4 468: 3814 subs r0, #20 { 46a: 4614 mov r4, r2 ret = _i2c_m_sync_transfer(&i2c->device, &msg); 46c: 4798 blx r3 if (ret) { return ret; } return n; } 46e: 2800 cmp r0, #0 470: bf08 it eq 472: 4620 moveq r0, r4 474: b004 add sp, #16 476: bd10 pop {r4, pc} 478: 00000a5d .word 0x00000a5d 0000047c : { 47c: b51f push {r0, r1, r2, r3, r4, lr} msg.addr = i2c->slave_addr; 47e: 8903 ldrh r3, [r0, #8] 480: f8ad 3004 strh.w r3, [sp, #4] msg.flags = I2C_M_STOP | I2C_M_RD; 484: f248 0301 movw r3, #32769 ; 0x8001 488: f8ad 3006 strh.w r3, [sp, #6] msg.buffer = buf; 48c: 9103 str r1, [sp, #12] ret = _i2c_m_sync_transfer(&i2c->device, &msg); 48e: 4b05 ldr r3, [pc, #20] ; (4a4 ) msg.len = n; 490: 9202 str r2, [sp, #8] ret = _i2c_m_sync_transfer(&i2c->device, &msg); 492: a901 add r1, sp, #4 494: 3814 subs r0, #20 { 496: 4614 mov r4, r2 ret = _i2c_m_sync_transfer(&i2c->device, &msg); 498: 4798 blx r3 } 49a: 2800 cmp r0, #0 49c: bf08 it eq 49e: 4620 moveq r0, r4 4a0: b004 add sp, #16 4a2: bd10 pop {r4, pc} 4a4: 00000a5d .word 0x00000a5d 000004a8 : /** * \brief Sync version of i2c initialize */ int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw) { 4a8: b538 push {r3, r4, r5, lr} int32_t init_status; ASSERT(i2c); 4aa: 4604 mov r4, r0 4ac: 3800 subs r0, #0 4ae: bf18 it ne 4b0: 2001 movne r0, #1 4b2: 4b07 ldr r3, [pc, #28] ; (4d0 ) { 4b4: 460d mov r5, r1 ASSERT(i2c); 4b6: 225e movs r2, #94 ; 0x5e 4b8: 4906 ldr r1, [pc, #24] ; (4d4 ) 4ba: 4798 blx r3 init_status = _i2c_m_sync_init(&i2c->device, hw); 4bc: 4b06 ldr r3, [pc, #24] ; (4d8 ) 4be: 4629 mov r1, r5 4c0: 4620 mov r0, r4 4c2: 4798 blx r3 if (init_status) { 4c4: b918 cbnz r0, 4ce return init_status; } /* Init I/O */ i2c->io.read = i2c_m_sync_read; 4c6: 4b05 ldr r3, [pc, #20] ; (4dc ) 4c8: 61a3 str r3, [r4, #24] i2c->io.write = i2c_m_sync_write; 4ca: 4b05 ldr r3, [pc, #20] ; (4e0 ) 4cc: 6163 str r3, [r4, #20] return ERR_NONE; } 4ce: bd38 pop {r3, r4, r5, pc} 4d0: 000005b1 .word 0x000005b1 4d4: 00001463 .word 0x00001463 4d8: 00000a31 .word 0x00000a31 4dc: 0000047d .word 0x0000047d 4e0: 00000451 .word 0x00000451 000004e4 <_init_chip>: } static inline void hri_nvmctrl_set_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) { NVMCTRL_CRITICAL_SECTION_ENTER(); ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_RWS(mask); 4e4: 4a0a ldr r2, [pc, #40] ; (510 <_init_chip+0x2c>) 4e6: 8813 ldrh r3, [r2, #0] 4e8: b29b uxth r3, r3 /** * \brief Initialize the hardware abstraction layer */ void _init_chip(void) { 4ea: b510 push {r4, lr} 4ec: f443 63a0 orr.w r3, r3, #1280 ; 0x500 4f0: 8013 strh r3, [r2, #0] hri_nvmctrl_set_CTRLA_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE); _osc32kctrl_init_sources(); 4f2: 4b08 ldr r3, [pc, #32] ; (514 <_init_chip+0x30>) 4f4: 4798 blx r3 _oscctrl_init_sources(); 4f6: 4b08 ldr r3, [pc, #32] ; (518 <_init_chip+0x34>) 4f8: 4798 blx r3 _mclk_init(); 4fa: 4b08 ldr r3, [pc, #32] ; (51c <_init_chip+0x38>) 4fc: 4798 blx r3 #if _GCLK_INIT_1ST _gclk_init_generators_by_fref(_GCLK_INIT_1ST); #endif _oscctrl_init_referenced_generators(); 4fe: 4b08 ldr r3, [pc, #32] ; (520 <_init_chip+0x3c>) 500: 4798 blx r3 #endif #if CONF_CMCC_ENABLE cache_init(); #endif } 502: e8bd 4010 ldmia.w sp!, {r4, lr} _gclk_init_generators_by_fref(_GCLK_INIT_LAST); 506: 4b07 ldr r3, [pc, #28] ; (524 <_init_chip+0x40>) 508: f640 70ff movw r0, #4095 ; 0xfff 50c: 4718 bx r3 50e: bf00 nop 510: 41004000 .word 0x41004000 514: 00000d0d .word 0x00000d0d 518: 000005b7 .word 0x000005b7 51c: 000005f5 .word 0x000005f5 520: 000005b9 .word 0x000005b9 524: 00000c4d .word 0x00000c4d 00000528 : return tmp; } static inline hri_ramecc_intflag_reg_t hri_ramecc_read_INTFLAG_reg(const void *const hw) { return ((Ramecc *)hw)->INTFLAG.reg; 528: 4a0b ldr r2, [pc, #44] ; (558 ) 52a: 7893 ldrb r3, [r2, #2] /** * \internal RAMECC interrupt handler */ void RAMECC_Handler(void) { 52c: b082 sub sp, #8 52e: b2db uxtb r3, r3 struct _ramecc_device *dev = (struct _ramecc_device *)&device; volatile uint32_t int_mask = hri_ramecc_read_INTFLAG_reg(RAMECC); 530: 9301 str r3, [sp, #4] if (int_mask & RAMECC_INTFLAG_DUALE && dev->ramecc_cb.dual_bit_err) { 532: 9b01 ldr r3, [sp, #4] 534: 0799 lsls r1, r3, #30 536: d505 bpl.n 544 538: 4b08 ldr r3, [pc, #32] ; (55c ) 53a: 681b ldr r3, [r3, #0] 53c: b113 cbz r3, 544 return tmp; } static inline hri_ramecc_erraddr_reg_t hri_ramecc_read_ERRADDR_reg(const void *const hw) { return ((Ramecc *)hw)->ERRADDR.reg; 53e: 6850 ldr r0, [r2, #4] } else if (int_mask & RAMECC_INTFLAG_SINGLEE && dev->ramecc_cb.single_bit_err) { dev->ramecc_cb.single_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC)); } else { return; } } 540: b002 add sp, #8 dev->ramecc_cb.single_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC)); 542: 4718 bx r3 } else if (int_mask & RAMECC_INTFLAG_SINGLEE && dev->ramecc_cb.single_bit_err) { 544: 9b01 ldr r3, [sp, #4] 546: 07db lsls r3, r3, #31 548: d504 bpl.n 554 54a: 4b04 ldr r3, [pc, #16] ; (55c ) 54c: 685b ldr r3, [r3, #4] 54e: b10b cbz r3, 554 550: 4a01 ldr r2, [pc, #4] ; (558 ) 552: e7f4 b.n 53e } 554: b002 add sp, #8 556: 4770 bx lr 558: 41020000 .word 0x41020000 55c: 2000001c .word 0x2000001c 00000560 : * \brief Check whether element belongs to list */ bool is_list_element(const struct list_descriptor *const list, const void *const element) { struct list_element *it; for (it = list->head; it; it = it->next) { 560: 6800 ldr r0, [r0, #0] 562: b900 cbnz r0, 566 564: 4770 bx lr if (it == element) { 566: 4288 cmp r0, r1 568: d1fa bne.n 560 return true; 56a: 2001 movs r0, #1 } } return false; } 56c: 4770 bx lr ... 00000570 : /** * \brief Insert an element as list head */ void list_insert_as_head(struct list_descriptor *const list, void *const element) { 570: b538 push {r3, r4, r5, lr} ASSERT(!is_list_element(list, element)); 572: 4b07 ldr r3, [pc, #28] ; (590 ) { 574: 4604 mov r4, r0 ASSERT(!is_list_element(list, element)); 576: 4798 blx r3 578: f080 0001 eor.w r0, r0, #1 { 57c: 460d mov r5, r1 ASSERT(!is_list_element(list, element)); 57e: 4b05 ldr r3, [pc, #20] ; (594 ) 580: 4905 ldr r1, [pc, #20] ; (598 ) 582: 2239 movs r2, #57 ; 0x39 584: b2c0 uxtb r0, r0 586: 4798 blx r3 ((struct list_element *)element)->next = list->head; 588: 6823 ldr r3, [r4, #0] 58a: 602b str r3, [r5, #0] list->head = (struct list_element *)element; 58c: 6025 str r5, [r4, #0] } 58e: bd38 pop {r3, r4, r5, pc} 590: 00000561 .word 0x00000561 594: 000005b1 .word 0x000005b1 598: 0000147f .word 0x0000147f 0000059c : /** * \brief Insert an element after the given list element */ void list_insert_after(void *const after, void *const element) { ((struct list_element *)element)->next = ((struct list_element *)after)->next; 59c: 6803 ldr r3, [r0, #0] 59e: 600b str r3, [r1, #0] ((struct list_element *)after)->next = (struct list_element *)element; 5a0: 6001 str r1, [r0, #0] } 5a2: 4770 bx lr 000005a4 : /** * \brief Removes list head */ void *list_remove_head(struct list_descriptor *const list) { if (list->head) { 5a4: 6803 ldr r3, [r0, #0] 5a6: b10b cbz r3, 5ac struct list_element *tmp = list->head; list->head = list->head->next; 5a8: 681a ldr r2, [r3, #0] 5aa: 6002 str r2, [r0, #0] return (void *)tmp; } return NULL; } 5ac: 4618 mov r0, r3 5ae: 4770 bx lr 000005b0 : /** * \brief Assert function */ void assert(const bool condition, const char *const file, const int line) { if (!(condition)) { 5b0: b900 cbnz r0, 5b4 __asm("BKPT #0"); 5b2: be00 bkpt 0x0000 } (void)file; (void)line; } 5b4: 4770 bx lr 000005b6 <_oscctrl_init_sources>: hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(hw, 1); #endif #endif (void)hw; } 5b6: 4770 bx lr 000005b8 <_oscctrl_init_referenced_generators>: static inline void hri_oscctrl_write_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllratio_reg_t data) { OSCCTRL_CRITICAL_SECTION_ENTER(); ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = data; 5b8: 4b0c ldr r3, [pc, #48] ; (5ec <_oscctrl_init_referenced_generators+0x34>) 5ba: 4a0d ldr r2, [pc, #52] ; (5f0 <_oscctrl_init_referenced_generators+0x38>) 5bc: 635a str r2, [r3, #52] ; 0x34 while (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & reg) { 5be: 6bda ldr r2, [r3, #60] ; 0x3c 5c0: f012 0f06 tst.w r2, #6 5c4: d1fb bne.n 5be <_oscctrl_init_referenced_generators+0x6> static inline void hri_oscctrl_write_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t data) { OSCCTRL_CRITICAL_SECTION_ENTER(); ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = data; 5c6: f44f 6202 mov.w r2, #2080 ; 0x820 5ca: 639a str r2, [r3, #56] ; 0x38 ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = data; 5cc: 2202 movs r2, #2 5ce: f883 2030 strb.w r2, [r3, #48] ; 0x30 while (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & reg) { 5d2: 4a06 ldr r2, [pc, #24] ; (5ec <_oscctrl_init_referenced_generators+0x34>) 5d4: 6bd3 ldr r3, [r2, #60] ; 0x3c 5d6: 0798 lsls r0, r3, #30 5d8: d4fc bmi.n 5d4 <_oscctrl_init_referenced_generators+0x1c> return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK) 5da: 4b04 ldr r3, [pc, #16] ; (5ec <_oscctrl_init_referenced_generators+0x34>) 5dc: 6c1a ldr r2, [r3, #64] ; 0x40 #endif #endif #if CONF_FDPLL0_CONFIG == 1 #if CONF_FDPLL0_ENABLE == 1 while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw, 0) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw, 0))) 5de: 07d1 lsls r1, r2, #31 5e0: d402 bmi.n 5e8 <_oscctrl_init_referenced_generators+0x30> return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY) 5e2: 6c1a ldr r2, [r3, #64] ; 0x40 5e4: 0792 lsls r2, r2, #30 5e6: d5f9 bpl.n 5dc <_oscctrl_init_referenced_generators+0x24> hri_gclk_write_GENCTRL_SRC_bf(GCLK, 0, CONF_GCLK_GEN_0_SOURCE); while (hri_gclk_get_SYNCBUSY_GENCTRL0_bit(GCLK)) ; #endif (void)hw; } 5e8: 4770 bx lr 5ea: bf00 nop 5ec: 40001000 .word 0x40001000 5f0: 00010e4d .word 0x00010e4d 000005f4 <_mclk_init>: } static inline void hri_mclk_write_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t data) { MCLK_CRITICAL_SECTION_ENTER(); ((Mclk *)hw)->CPUDIV.reg = data; 5f4: 4b01 ldr r3, [pc, #4] ; (5fc <_mclk_init+0x8>) 5f6: 2201 movs r2, #1 5f8: 715a strb r2, [r3, #5] */ void _mclk_init(void) { void *hw = (void *)MCLK; hri_mclk_write_CPUDIV_reg(hw, MCLK_CPUDIV_DIV(CONF_MCLK_CPUDIV)); } 5fa: 4770 bx lr 5fc: 40000800 .word 0x40000800 00000600 : while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) { 600: 69c3 ldr r3, [r0, #28] 602: 420b tst r3, r1 604: d1fc bne.n 600 } 606: 4770 bx lr 00000608 : ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE; 608: 6802 ldr r2, [r0, #0] hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); 60a: 4b03 ldr r3, [pc, #12] ; (618 ) ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE; 60c: f022 0202 bic.w r2, r2, #2 610: 6002 str r2, [r0, #0] hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); 612: 2103 movs r1, #3 614: 4718 bx r3 616: bf00 nop 618: 00000601 .word 0x00000601 0000061c : ((Sercom *)hw)->I2CM.CTRLA.reg = data; 61c: 6001 str r1, [r0, #0] hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); 61e: 4b01 ldr r3, [pc, #4] ; (624 ) 620: 2103 movs r1, #3 622: 4718 bx r3 624: 00000601 .word 0x00000601 00000628 <_sercom_get_hardware_index>: { 628: b570 push {r4, r5, r6, lr} Sercom *const sercom_modules[] = SERCOM_INSTS; 62a: 4d0c ldr r5, [pc, #48] ; (65c <_sercom_get_hardware_index+0x34>) { 62c: 4606 mov r6, r0 Sercom *const sercom_modules[] = SERCOM_INSTS; 62e: cd0f ldmia r5!, {r0, r1, r2, r3} { 630: b088 sub sp, #32 Sercom *const sercom_modules[] = SERCOM_INSTS; 632: 466c mov r4, sp 634: c40f stmia r4!, {r0, r1, r2, r3} 636: e895 000f ldmia.w r5, {r0, r1, r2, r3} 63a: e884 000f stmia.w r4, {r0, r1, r2, r3} for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) { 63e: 466a mov r2, sp 640: 2300 movs r3, #0 if ((uint32_t)hw == (uint32_t)sercom_modules[i]) { 642: f852 1b04 ldr.w r1, [r2], #4 646: 42b1 cmp r1, r6 648: d102 bne.n 650 <_sercom_get_hardware_index+0x28> return i; 64a: b2d8 uxtb r0, r3 } 64c: b008 add sp, #32 64e: bd70 pop {r4, r5, r6, pc} for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) { 650: 3301 adds r3, #1 652: 2b08 cmp r3, #8 654: d1f5 bne.n 642 <_sercom_get_hardware_index+0x1a> return 0; 656: 2000 movs r0, #0 658: e7f8 b.n 64c <_sercom_get_hardware_index+0x24> 65a: bf00 nop 65c: 000014b8 .word 0x000014b8 00000660 <_sercom_get_irq_num>: { 660: b508 push {r3, lr} return SERCOM0_0_IRQn + (_sercom_get_hardware_index(hw) << 2); 662: 4b03 ldr r3, [pc, #12] ; (670 <_sercom_get_irq_num+0x10>) 664: 4798 blx r3 666: 0080 lsls r0, r0, #2 668: 302e adds r0, #46 ; 0x2e } 66a: f000 00fe and.w r0, r0, #254 ; 0xfe 66e: bd08 pop {r3, pc} 670: 00000629 .word 0x00000629 00000674 <__NVIC_EnableIRQ>: */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 674: 0941 lsrs r1, r0, #5 676: 4a04 ldr r2, [pc, #16] ; (688 <__NVIC_EnableIRQ+0x14>) 678: f000 001f and.w r0, r0, #31 67c: 2301 movs r3, #1 67e: 4083 lsls r3, r0 680: f842 3021 str.w r3, [r2, r1, lsl #2] } } 684: 4770 bx lr 686: bf00 nop 688: e000e100 .word 0xe000e100 0000068c <__NVIC_DisableIRQ>: */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 68c: 0943 lsrs r3, r0, #5 68e: 4906 ldr r1, [pc, #24] ; (6a8 <__NVIC_DisableIRQ+0x1c>) 690: f000 001f and.w r0, r0, #31 694: 3320 adds r3, #32 696: 2201 movs r2, #1 698: 4082 lsls r2, r0 69a: f841 2023 str.w r2, [r1, r3, lsl #2] \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); 69e: f3bf 8f4f dsb sy __ASM volatile ("isb 0xF":::"memory"); 6a2: f3bf 8f6f isb sy __DSB(); __ISB(); } } 6a6: 4770 bx lr 6a8: e000e100 .word 0xe000e100 000006ac <__NVIC_ClearPendingIRQ>: */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 6ac: 0943 lsrs r3, r0, #5 6ae: 4904 ldr r1, [pc, #16] ; (6c0 <__NVIC_ClearPendingIRQ+0x14>) 6b0: f000 001f and.w r0, r0, #31 6b4: 2201 movs r2, #1 6b6: 3360 adds r3, #96 ; 0x60 6b8: 4082 lsls r2, r0 6ba: f841 2023 str.w r2, [r1, r3, lsl #2] } } 6be: 4770 bx lr 6c0: e000e100 .word 0xe000e100 000006c4 <_get_i2cm_index>: { 6c4: b508 push {r3, lr} uint8_t sercom_offset = _sercom_get_hardware_index(hw); 6c6: 4b07 ldr r3, [pc, #28] ; (6e4 <_get_i2cm_index+0x20>) 6c8: 4798 blx r3 if (_i2cms[i].number == sercom_offset) { 6ca: 2803 cmp r0, #3 6cc: d008 beq.n 6e0 <_get_i2cm_index+0x1c> ASSERT(false); 6ce: 2000 movs r0, #0 6d0: 4905 ldr r1, [pc, #20] ; (6e8 <_get_i2cm_index+0x24>) 6d2: 4b06 ldr r3, [pc, #24] ; (6ec <_get_i2cm_index+0x28>) 6d4: f240 32ce movw r2, #974 ; 0x3ce 6d8: 4798 blx r3 6da: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff } 6de: bd08 pop {r3, pc} return i; 6e0: 2000 movs r0, #0 6e2: e7fc b.n 6de <_get_i2cm_index+0x1a> 6e4: 00000629 .word 0x00000629 6e8: 0000149d .word 0x0000149d 6ec: 000005b1 .word 0x000005b1 000006f0 <_sercom_i2c_send_stop>: ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask); 6f0: 6842 ldr r2, [r0, #4] hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); 6f2: 4b03 ldr r3, [pc, #12] ; (700 <_sercom_i2c_send_stop+0x10>) ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask); 6f4: f442 3240 orr.w r2, r2, #196608 ; 0x30000 6f8: 6042 str r2, [r0, #4] hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); 6fa: 2104 movs r1, #4 6fc: 4718 bx r3 6fe: bf00 nop 700: 00000601 .word 0x00000601 00000704 <_sercom_i2c_sync_analyse_flags>: { 704: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 708: 460d mov r5, r1 70a: 4614 mov r4, r2 ((Sercom *)hw)->I2CM.STATUS.reg |= mask; } static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_reg(const void *const hw) { hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); 70c: 2104 movs r1, #4 70e: 4a53 ldr r2, [pc, #332] ; (85c <_sercom_i2c_sync_analyse_flags+0x158>) tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; 710: f8d0 8000 ldr.w r8, [r0] hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); 714: 4790 blx r2 return ((Sercom *)hw)->I2CM.STATUS.reg; 716: 8b43 ldrh r3, [r0, #26] if (flags & MB_FLAG) { 718: f015 0f01 tst.w r5, #1 { 71c: 4606 mov r6, r0 71e: b29b uxth r3, r3 if (flags & MB_FLAG) { 720: 4617 mov r7, r2 722: d060 beq.n 7e6 <_sercom_i2c_sync_analyse_flags+0xe2> if (status & SERCOM_I2CM_STATUS_ARBLOST) { 724: 079d lsls r5, r3, #30 726: d516 bpl.n 756 <_sercom_i2c_sync_analyse_flags+0x52> ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; 728: 2201 movs r2, #1 72a: 7602 strb r2, [r0, #24] msg->flags |= I2C_M_FAIL; 72c: 8862 ldrh r2, [r4, #2] 72e: b292 uxth r2, r2 730: f442 5280 orr.w r2, r2, #4096 ; 0x1000 734: 8062 strh r2, [r4, #2] msg->flags &= ~I2C_M_BUSY; 736: 8862 ldrh r2, [r4, #2] if (status & SERCOM_I2CM_STATUS_BUSERR) { 738: f003 0501 and.w r5, r3, #1 msg->flags &= ~I2C_M_BUSY; 73c: f422 7280 bic.w r2, r2, #256 ; 0x100 740: 0412 lsls r2, r2, #16 if (status & SERCOM_I2CM_STATUS_BUSERR) { 742: f1c5 25ff rsb r5, r5, #4278255360 ; 0xff00ff00 msg->flags &= ~I2C_M_BUSY; 746: 0c12 lsrs r2, r2, #16 if (status & SERCOM_I2CM_STATUS_BUSERR) { 748: f505 057f add.w r5, r5, #16711680 ; 0xff0000 msg->flags &= ~I2C_M_BUSY; 74c: 8062 strh r2, [r4, #2] if (status & SERCOM_I2CM_STATUS_BUSERR) { 74e: 35fc adds r5, #252 ; 0xfc } 750: 4628 mov r0, r5 752: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} if (status & SERCOM_I2CM_STATUS_RXNACK) { 756: f013 0504 ands.w r5, r3, #4 75a: d015 beq.n 788 <_sercom_i2c_sync_analyse_flags+0x84> if (msg->len > 0) { 75c: 6863 ldr r3, [r4, #4] 75e: 2b00 cmp r3, #0 msg->flags |= I2C_M_FAIL; 760: bfc1 itttt gt 762: 8863 ldrhgt r3, [r4, #2] 764: b29b uxthgt r3, r3 766: f443 5380 orrgt.w r3, r3, #4096 ; 0x1000 76a: 8063 strhgt r3, [r4, #2] if (msg->flags & I2C_M_STOP) { 76c: 8863 ldrh r3, [r4, #2] 76e: 041f lsls r7, r3, #16 770: d501 bpl.n 776 <_sercom_i2c_sync_analyse_flags+0x72> _sercom_i2c_send_stop(hw); 772: 4b3b ldr r3, [pc, #236] ; (860 <_sercom_i2c_sync_analyse_flags+0x15c>) 774: 4798 blx r3 msg->flags &= ~I2C_M_BUSY; 776: 8863 ldrh r3, [r4, #2] 778: f423 7380 bic.w r3, r3, #256 ; 0x100 77c: 041b lsls r3, r3, #16 77e: 0c1b lsrs r3, r3, #16 780: 8063 strh r3, [r4, #2] return I2C_NACK; 782: f06f 0501 mvn.w r5, #1 786: e7e3 b.n 750 <_sercom_i2c_sync_analyse_flags+0x4c> if (msg->flags & I2C_M_TEN) { 788: 8863 ldrh r3, [r4, #2] 78a: f413 6780 ands.w r7, r3, #1024 ; 0x400 78e: d013 beq.n 7b8 <_sercom_i2c_sync_analyse_flags+0xb4> ((((msg->addr & TEN_ADDR_MASK) >> 8) | TEN_ADDR_FRAME) << 1) | I2C_M_RD 790: 8827 ldrh r7, [r4, #0] hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); 792: 4790 blx r2 return ((Sercom *)hw)->I2CM.ADDR.reg; 794: 6a43 ldr r3, [r0, #36] ; 0x24 796: 09ff lsrs r7, r7, #7 | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); 798: f007 0706 and.w r7, r7, #6 79c: f403 4380 and.w r3, r3, #16384 ; 0x4000 7a0: 433b orrs r3, r7 hri_sercomi2cm_write_ADDR_reg(hw, 7a2: f043 03f1 orr.w r3, r3, #241 ; 0xf1 ((Sercom *)hw)->I2CM.ADDR.reg = data; 7a6: 6243 str r3, [r0, #36] ; 0x24 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); 7a8: 4790 blx r2 msg->flags &= ~I2C_M_TEN; 7aa: 8863 ldrh r3, [r4, #2] 7ac: f423 6380 bic.w r3, r3, #1024 ; 0x400 msg->flags &= ~I2C_M_BUSY; 7b0: 041b lsls r3, r3, #16 7b2: 0c1b lsrs r3, r3, #16 7b4: 8063 strh r3, [r4, #2] 7b6: e7cb b.n 750 <_sercom_i2c_sync_analyse_flags+0x4c> if (msg->len == 0) { 7b8: 6865 ldr r5, [r4, #4] 7ba: b945 cbnz r5, 7ce <_sercom_i2c_sync_analyse_flags+0xca> if (msg->flags & I2C_M_STOP) { 7bc: 8863 ldrh r3, [r4, #2] 7be: 041e lsls r6, r3, #16 7c0: d501 bpl.n 7c6 <_sercom_i2c_sync_analyse_flags+0xc2> _sercom_i2c_send_stop(hw); 7c2: 4b27 ldr r3, [pc, #156] ; (860 <_sercom_i2c_sync_analyse_flags+0x15c>) 7c4: 4798 blx r3 msg->flags &= ~I2C_M_BUSY; 7c6: 8863 ldrh r3, [r4, #2] 7c8: f423 7380 bic.w r3, r3, #256 ; 0x100 7cc: e7f0 b.n 7b0 <_sercom_i2c_sync_analyse_flags+0xac> hri_sercomi2cm_write_DATA_reg(hw, *msg->buffer); 7ce: f8d4 8008 ldr.w r8, [r4, #8] 7d2: f818 3b01 ldrb.w r3, [r8], #1 ((Sercom *)hw)->I2CM.DATA.reg = data; 7d6: 6283 str r3, [r0, #40] ; 0x28 msg->len--; 7d8: 3d01 subs r5, #1 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); 7da: 4790 blx r2 msg->buffer++; 7dc: f8c4 8008 str.w r8, [r4, #8] msg->len--; 7e0: 6065 str r5, [r4, #4] return I2C_OK; 7e2: 2500 movs r5, #0 } 7e4: e7b4 b.n 750 <_sercom_i2c_sync_analyse_flags+0x4c> } else if (flags & SB_FLAG) { 7e6: f015 0502 ands.w r5, r5, #2 7ea: d0b1 beq.n 750 <_sercom_i2c_sync_analyse_flags+0x4c> if ((msg->len) && !(status & SERCOM_I2CM_STATUS_RXNACK)) { 7ec: 6862 ldr r2, [r4, #4] 7ee: 2a00 cmp r2, #0 7f0: d031 beq.n 856 <_sercom_i2c_sync_analyse_flags+0x152> 7f2: 0759 lsls r1, r3, #29 7f4: d42f bmi.n 856 <_sercom_i2c_sync_analyse_flags+0x152> msg->len--; 7f6: 3a01 subs r2, #1 7f8: f3c8 63c0 ubfx r3, r8, #27, #1 7fc: 6062 str r2, [r4, #4] if ((msg->len == 0 && !sclsm) || (msg->len == 1 && sclsm)) { 7fe: b99a cbnz r2, 828 <_sercom_i2c_sync_analyse_flags+0x124> 800: b1ab cbz r3, 82e <_sercom_i2c_sync_analyse_flags+0x12a> if (msg->flags & I2C_M_STOP) { 802: 8863 ldrh r3, [r4, #2] 804: 041b lsls r3, r3, #16 806: d508 bpl.n 81a <_sercom_i2c_sync_analyse_flags+0x116> ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_SMEN; 808: 6873 ldr r3, [r6, #4] 80a: f423 7380 bic.w r3, r3, #256 ; 0x100 80e: 6073 str r3, [r6, #4] hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); 810: 2104 movs r1, #4 812: 4630 mov r0, r6 814: 47b8 blx r7 _sercom_i2c_send_stop(hw); 816: 4b12 ldr r3, [pc, #72] ; (860 <_sercom_i2c_sync_analyse_flags+0x15c>) 818: 4798 blx r3 msg->flags &= ~I2C_M_BUSY; 81a: 8863 ldrh r3, [r4, #2] 81c: f423 7380 bic.w r3, r3, #256 ; 0x100 820: 041b lsls r3, r3, #16 822: 0c1b lsrs r3, r3, #16 824: 8063 strh r3, [r4, #2] 826: e00b b.n 840 <_sercom_i2c_sync_analyse_flags+0x13c> if ((msg->len == 0 && !sclsm) || (msg->len == 1 && sclsm)) { 828: 2a01 cmp r2, #1 82a: d109 bne.n 840 <_sercom_i2c_sync_analyse_flags+0x13c> 82c: b143 cbz r3, 840 <_sercom_i2c_sync_analyse_flags+0x13c> ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; 82e: 6873 ldr r3, [r6, #4] 830: f443 2380 orr.w r3, r3, #262144 ; 0x40000 834: 6073 str r3, [r6, #4] hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); 836: 2104 movs r1, #4 838: 4630 mov r0, r6 83a: 47b8 blx r7 if (msg->len == 0) { 83c: 2a00 cmp r2, #0 83e: d0e0 beq.n 802 <_sercom_i2c_sync_analyse_flags+0xfe> hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); 840: 2104 movs r1, #4 842: 4630 mov r0, r6 844: 47b8 blx r7 *msg->buffer++ = hri_sercomi2cm_read_DATA_reg(hw); 846: 68a3 ldr r3, [r4, #8] return ((Sercom *)hw)->I2CM.DATA.reg; 848: 6ab2 ldr r2, [r6, #40] ; 0x28 84a: 1c59 adds r1, r3, #1 84c: 60a1 str r1, [r4, #8] 84e: 701a strb r2, [r3, #0] ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; 850: 2302 movs r3, #2 852: 7633 strb r3, [r6, #24] 854: e7c5 b.n 7e2 <_sercom_i2c_sync_analyse_flags+0xde> 856: 2302 movs r3, #2 858: 7633 strb r3, [r6, #24] 85a: e792 b.n 782 <_sercom_i2c_sync_analyse_flags+0x7e> 85c: 00000601 .word 0x00000601 860: 000006f1 .word 0x000006f1 00000864 <_i2c_m_sync_init_impl>: } return ERR_NONE; } static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw) { 864: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 868: 460c mov r4, r1 uint8_t i = _get_i2cm_index(hw); 86a: 4b21 ldr r3, [pc, #132] ; (8f0 <_i2c_m_sync_init_impl+0x8c>) 86c: f8df a08c ldr.w sl, [pc, #140] ; 8fc <_i2c_m_sync_init_impl+0x98> 870: 4d20 ldr r5, [pc, #128] ; (8f4 <_i2c_m_sync_init_impl+0x90>) 872: f8df 908c ldr.w r9, [pc, #140] ; 900 <_i2c_m_sync_init_impl+0x9c> { 876: 4606 mov r6, r0 uint8_t i = _get_i2cm_index(hw); 878: 4608 mov r0, r1 87a: 4798 blx r3 return ((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg; 87c: 69e3 ldr r3, [r4, #28] if (!hri_sercomi2cm_is_syncing(hw, SERCOM_I2CM_SYNCBUSY_SWRST)) { 87e: f013 0f01 tst.w r3, #1 uint8_t i = _get_i2cm_index(hw); 882: b2c7 uxtb r7, r0 if (!hri_sercomi2cm_is_syncing(hw, SERCOM_I2CM_SYNCBUSY_SWRST)) { 884: d113 bne.n 8ae <_i2c_m_sync_init_impl+0x4a> uint32_t mode = _i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_MODE_Msk; 886: 2318 movs r3, #24 888: fb03 a307 mla r3, r3, r7, sl hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); 88c: 2103 movs r1, #3 88e: 6a5b ldr r3, [r3, #36] ; 0x24 890: 4620 mov r0, r4 892: f003 081c and.w r8, r3, #28 896: 47a8 blx r5 tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; 898: 6823 ldr r3, [r4, #0] if (hri_sercomi2cm_get_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_ENABLE)) { 89a: 079b lsls r3, r3, #30 89c: d503 bpl.n 8a6 <_i2c_m_sync_init_impl+0x42> hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); 89e: 4b16 ldr r3, [pc, #88] ; (8f8 <_i2c_m_sync_init_impl+0x94>) 8a0: 4798 blx r3 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_ENABLE); 8a2: 2102 movs r1, #2 8a4: 47a8 blx r5 } hri_sercomi2cm_write_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_SWRST | mode); 8a6: f048 0101 orr.w r1, r8, #1 8aa: 4620 mov r0, r4 8ac: 47c8 blx r9 } hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); hri_sercomi2cm_write_CTRLA_reg(hw, _i2cms[i].ctrl_a); 8ae: 2218 movs r2, #24 8b0: fb02 a207 mla r2, r2, r7, sl hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); 8b4: 4620 mov r0, r4 8b6: 2101 movs r1, #1 8b8: 47a8 blx r5 hri_sercomi2cm_write_CTRLA_reg(hw, _i2cms[i].ctrl_a); 8ba: 6a54 ldr r4, [r2, #36] ; 0x24 8bc: 4621 mov r1, r4 8be: 47c8 blx r9 hri_sercomi2cm_write_CTRLB_reg(hw, _i2cms[i].ctrl_b); 8c0: 6a93 ldr r3, [r2, #40] ; 0x28 ((Sercom *)hw)->I2CM.CTRLB.reg = data; 8c2: 6043 str r3, [r0, #4] hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); 8c4: 2104 movs r1, #4 8c6: 47a8 blx r5 hri_sercomi2cm_write_BAUD_reg(hw, _i2cms[i].baud); 8c8: 6ad3 ldr r3, [r2, #44] ; 0x2c ((Sercom *)hw)->I2CM.BAUD.reg = data; 8ca: 60c3 str r3, [r0, #12] service->mode = (_i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos; 8cc: f3c4 6301 ubfx r3, r4, #24, #2 8d0: 81b3 strh r3, [r6, #12] tmp = ((Sercom *)hw)->I2CM.ADDR.reg; 8d2: 6a43 ldr r3, [r0, #36] ; 0x24 hri_sercomi2cm_write_ADDR_HS_bit(hw, service->mode < I2C_HS ? 0 : 1); 8d4: f3c4 6440 ubfx r4, r4, #25, #1 tmp &= ~SERCOM_I2CM_ADDR_HS; 8d8: f423 4380 bic.w r3, r3, #16384 ; 0x4000 tmp |= value << SERCOM_I2CM_ADDR_HS_Pos; 8dc: ea43 3384 orr.w r3, r3, r4, lsl #14 ((Sercom *)hw)->I2CM.ADDR.reg = tmp; 8e0: 6243 str r3, [r0, #36] ; 0x24 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); 8e2: 47a8 blx r5 service->trise = _i2cms[i].trise; 8e4: 8e53 ldrh r3, [r2, #50] ; 0x32 8e6: 81f3 strh r3, [r6, #14] return ERR_NONE; } 8e8: 2000 movs r0, #0 8ea: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8ee: bf00 nop 8f0: 000006c5 .word 0x000006c5 8f4: 00000601 .word 0x00000601 8f8: 00000609 .word 0x00000609 8fc: 000014b8 .word 0x000014b8 900: 0000061d .word 0x0000061d 00000904 <_usart_init>: { 904: b570 push {r4, r5, r6, lr} uint8_t sercom_offset = _sercom_get_hardware_index(hw); 906: 4b1a ldr r3, [pc, #104] ; (970 <_usart_init+0x6c>) { 908: 4604 mov r4, r0 uint8_t sercom_offset = _sercom_get_hardware_index(hw); 90a: 4798 blx r3 if (_usarts[i].number == sercom_offset) { 90c: 2802 cmp r0, #2 90e: d005 beq.n 91c <_usart_init+0x18> ASSERT(false); 910: 4918 ldr r1, [pc, #96] ; (974 <_usart_init+0x70>) 912: 4b19 ldr r3, [pc, #100] ; (978 <_usart_init+0x74>) 914: f240 226b movw r2, #619 ; 0x26b 918: 2000 movs r0, #0 91a: 4798 blx r3 return ((Sercom *)hw)->USART.SYNCBUSY.reg & reg; 91c: 69e3 ldr r3, [r4, #28] 91e: 4d17 ldr r5, [pc, #92] ; (97c <_usart_init+0x78>) 920: 4e17 ldr r6, [pc, #92] ; (980 <_usart_init+0x7c>) if (!hri_sercomusart_is_syncing(hw, SERCOM_USART_SYNCBUSY_SWRST)) { 922: f013 0f01 tst.w r3, #1 926: d10d bne.n 944 <_usart_init+0x40> hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); 928: 4b16 ldr r3, [pc, #88] ; (984 <_usart_init+0x80>) 92a: 2103 movs r1, #3 92c: 4620 mov r0, r4 92e: 4798 blx r3 tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; 930: 6823 ldr r3, [r4, #0] if (hri_sercomusart_get_CTRLA_reg(hw, SERCOM_USART_CTRLA_ENABLE)) { 932: 079b lsls r3, r3, #30 934: d503 bpl.n 93e <_usart_init+0x3a> hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); 936: 4b14 ldr r3, [pc, #80] ; (988 <_usart_init+0x84>) 938: 4798 blx r3 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); 93a: 2102 movs r1, #2 93c: 47a8 blx r5 hri_sercomusart_write_CTRLA_reg(hw, SERCOM_USART_CTRLA_SWRST | mode); 93e: 2105 movs r1, #5 940: 4620 mov r0, r4 942: 47b0 blx r6 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); 944: 4620 mov r0, r4 946: 2101 movs r1, #1 948: 47a8 blx r5 hri_sercomusart_write_CTRLA_reg(hw, _usarts[i].ctrl_a); 94a: 4910 ldr r1, [pc, #64] ; (98c <_usart_init+0x88>) 94c: 47b0 blx r6 ((Sercom *)hw)->USART.CTRLB.reg = data; 94e: f44f 3340 mov.w r3, #196608 ; 0x30000 952: 6063 str r3, [r4, #4] hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); 954: 211f movs r1, #31 956: 47a8 blx r5 ((Sercom *)hw)->USART.CTRLC.reg = data; 958: 4b0d ldr r3, [pc, #52] ; (990 <_usart_init+0x8c>) 95a: 60a3 str r3, [r4, #8] ((Sercom *)hw)->USART.BAUD.reg = data; 95c: f64f 4311 movw r3, #64529 ; 0xfc11 960: 81a3 strh r3, [r4, #12] ((Sercom *)hw)->USART.RXPL.reg = data; 962: 2300 movs r3, #0 964: 73a3 strb r3, [r4, #14] } 966: 4618 mov r0, r3 ((Sercom *)hw)->USART.DBGCTRL.reg = data; 968: f884 3030 strb.w r3, [r4, #48] ; 0x30 96c: bd70 pop {r4, r5, r6, pc} 96e: bf00 nop 970: 00000629 .word 0x00000629 974: 0000149d .word 0x0000149d 978: 000005b1 .word 0x000005b1 97c: 00000601 .word 0x00000601 980: 0000061d .word 0x0000061d 984: 00000601 .word 0x00000601 988: 00000609 .word 0x00000609 98c: 40100004 .word 0x40100004 990: 00700002 .word 0x00700002 00000994 <_usart_async_init>: { 994: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr} ASSERT(device); 998: 4605 mov r5, r0 99a: 3800 subs r0, #0 99c: bf18 it ne 99e: 2001 movne r0, #1 9a0: 4b14 ldr r3, [pc, #80] ; (9f4 <_usart_async_init+0x60>) { 9a2: 460c mov r4, r1 ASSERT(device); 9a4: 22cb movs r2, #203 ; 0xcb 9a6: 4914 ldr r1, [pc, #80] ; (9f8 <_usart_async_init+0x64>) 9a8: 4798 blx r3 init_status = _usart_init(hw); 9aa: 4b14 ldr r3, [pc, #80] ; (9fc <_usart_async_init+0x68>) 9ac: 4620 mov r0, r4 9ae: 4798 blx r3 if (init_status) { 9b0: 4606 mov r6, r0 9b2: b9d8 cbnz r0, 9ec <_usart_async_init+0x58> if (hw == SERCOM2) { 9b4: 4b12 ldr r3, [pc, #72] ; (a00 <_usart_async_init+0x6c>) device->hw = hw; 9b6: 61ac str r4, [r5, #24] if (hw == SERCOM2) { 9b8: 429c cmp r4, r3 _sercom2_dev = (struct _usart_async_device *)dev; 9ba: bf08 it eq 9bc: 4b11 ldreq r3, [pc, #68] ; (a04 <_usart_async_init+0x70>) NVIC_DisableIRQ((IRQn_Type)irq); 9be: f8df 9050 ldr.w r9, [pc, #80] ; a10 <_usart_async_init+0x7c> _sercom2_dev = (struct _usart_async_device *)dev; 9c2: bf08 it eq 9c4: 601d streq r5, [r3, #0] uint8_t irq = _sercom_get_irq_num(hw); 9c6: 4620 mov r0, r4 9c8: 4b0f ldr r3, [pc, #60] ; (a08 <_usart_async_init+0x74>) NVIC_ClearPendingIRQ((IRQn_Type)irq); 9ca: f8df 8048 ldr.w r8, [pc, #72] ; a14 <_usart_async_init+0x80> NVIC_EnableIRQ((IRQn_Type)irq); 9ce: 4f0f ldr r7, [pc, #60] ; (a0c <_usart_async_init+0x78>) uint8_t irq = _sercom_get_irq_num(hw); 9d0: 4798 blx r3 for (uint32_t i = 0; i < 4; i++) { 9d2: 2400 movs r4, #0 uint8_t irq = _sercom_get_irq_num(hw); 9d4: 4605 mov r5, r0 NVIC_DisableIRQ((IRQn_Type)irq); 9d6: 192b adds r3, r5, r4 9d8: b2d8 uxtb r0, r3 9da: 9001 str r0, [sp, #4] 9dc: 47c8 blx r9 NVIC_ClearPendingIRQ((IRQn_Type)irq); 9de: 9801 ldr r0, [sp, #4] 9e0: 47c0 blx r8 for (uint32_t i = 0; i < 4; i++) { 9e2: 3401 adds r4, #1 NVIC_EnableIRQ((IRQn_Type)irq); 9e4: 9801 ldr r0, [sp, #4] 9e6: 47b8 blx r7 for (uint32_t i = 0; i < 4; i++) { 9e8: 2c04 cmp r4, #4 9ea: d1f4 bne.n 9d6 <_usart_async_init+0x42> } 9ec: 4630 mov r0, r6 9ee: b003 add sp, #12 9f0: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 9f4: 000005b1 .word 0x000005b1 9f8: 0000149d .word 0x0000149d 9fc: 00000905 .word 0x00000905 a00: 41012000 .word 0x41012000 a04: 2000002c .word 0x2000002c a08: 00000661 .word 0x00000661 a0c: 00000675 .word 0x00000675 a10: 0000068d .word 0x0000068d a14: 000006ad .word 0x000006ad 00000a18 <_usart_async_write_byte>: hri_sercomusart_write_DATA_reg(device->hw, data); a18: 6983 ldr r3, [r0, #24] ((Sercom *)hw)->USART.DATA.reg = data; a1a: 6299 str r1, [r3, #40] ; 0x28 } a1c: 4770 bx lr 00000a1e <_usart_async_enable_byte_sent_irq>: hri_sercomusart_set_INTEN_DRE_bit(device->hw); a1e: 6983 ldr r3, [r0, #24] ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; a20: 2201 movs r2, #1 a22: 759a strb r2, [r3, #22] } a24: 4770 bx lr 00000a26 <_usart_async_enable_tx_done_irq>: hri_sercomusart_set_INTEN_TXC_bit(device->hw); a26: 6983 ldr r3, [r0, #24] ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; a28: 2202 movs r2, #2 a2a: 759a strb r2, [r3, #22] } a2c: 4770 bx lr ... 00000a30 <_i2c_m_sync_init>: { a30: b570 push {r4, r5, r6, lr} a32: 4604 mov r4, r0 a34: 460d mov r5, r1 ASSERT(i2c_dev); a36: 4b06 ldr r3, [pc, #24] ; (a50 <_i2c_m_sync_init+0x20>) a38: 4906 ldr r1, [pc, #24] ; (a54 <_i2c_m_sync_init+0x24>) a3a: 2001 movs r0, #1 a3c: f44f 62a8 mov.w r2, #1344 ; 0x540 a40: 4798 blx r3 i2c_dev->hw = hw; a42: 6125 str r5, [r4, #16] return _i2c_m_sync_init_impl(&i2c_dev->service, hw); a44: 4629 mov r1, r5 a46: 4620 mov r0, r4 a48: 4b03 ldr r3, [pc, #12] ; (a58 <_i2c_m_sync_init+0x28>) } a4a: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} return _i2c_m_sync_init_impl(&i2c_dev->service, hw); a4e: 4718 bx r3 a50: 000005b1 .word 0x000005b1 a54: 0000149d .word 0x0000149d a58: 00000865 .word 0x00000865 00000a5c <_i2c_m_sync_transfer>: { a5c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} a60: 4604 mov r4, r0 ASSERT(i2c_dev); a62: f8df 915c ldr.w r9, [pc, #348] ; bc0 <_i2c_m_sync_transfer+0x164> void * hw = i2c_dev->hw; a66: 6907 ldr r7, [r0, #16] { a68: 460e mov r6, r1 ASSERT(i2c_dev); a6a: f44f 62bf mov.w r2, #1528 ; 0x5f8 a6e: 4951 ldr r1, [pc, #324] ; (bb4 <_i2c_m_sync_transfer+0x158>) a70: 2001 movs r0, #1 a72: 47c8 blx r9 ASSERT(i2c_dev->hw); a74: 6920 ldr r0, [r4, #16] a76: 494f ldr r1, [pc, #316] ; (bb4 <_i2c_m_sync_transfer+0x158>) a78: 3800 subs r0, #0 a7a: f240 52f9 movw r2, #1529 ; 0x5f9 a7e: bf18 it ne a80: 2001 movne r0, #1 a82: 47c8 blx r9 ASSERT(msg); a84: 1e30 subs r0, r6, #0 a86: bf18 it ne a88: 2001 movne r0, #1 a8a: 494a ldr r1, [pc, #296] ; (bb4 <_i2c_m_sync_transfer+0x158>) a8c: f240 52fa movw r2, #1530 ; 0x5fa a90: 47c8 blx r9 if (i2c_dev->service.msg.flags & I2C_M_BUSY) { a92: 8863 ldrh r3, [r4, #2] a94: 05d8 lsls r0, r3, #23 a96: d47a bmi.n b8e <_i2c_m_sync_transfer+0x132> msg->flags |= I2C_M_BUSY; a98: 8873 ldrh r3, [r6, #2] hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); a9a: f8df 8128 ldr.w r8, [pc, #296] ; bc4 <_i2c_m_sync_transfer+0x168> a9e: b29b uxth r3, r3 aa0: f443 7380 orr.w r3, r3, #256 ; 0x100 aa4: 8073 strh r3, [r6, #2] i2c_dev->service.msg = *msg; aa6: e896 0007 ldmia.w r6, {r0, r1, r2} ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_SMEN; aaa: 687b ldr r3, [r7, #4] aac: f443 7380 orr.w r3, r3, #256 ; 0x100 ab0: e884 0007 stmia.w r4, {r0, r1, r2} ab4: 607b str r3, [r7, #4] hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); ab6: 2104 movs r1, #4 ab8: 4638 mov r0, r7 aba: 47c0 blx r8 void * hw = i2c_dev->hw; abc: 6925 ldr r5, [r4, #16] ASSERT(i2c_dev); abe: 493d ldr r1, [pc, #244] ; (bb4 <_i2c_m_sync_transfer+0x158>) tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; ac0: f8d5 a000 ldr.w sl, [r5] ac4: f240 52cd movw r2, #1485 ; 0x5cd ac8: 2001 movs r0, #1 aca: 47c8 blx r9 if (msg->len == 1 && sclsm) { acc: 6863 ldr r3, [r4, #4] ace: 2b01 cmp r3, #1 ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; ad0: 686b ldr r3, [r5, #4] ad2: d139 bne.n b48 <_i2c_m_sync_transfer+0xec> ad4: f01a 6f00 tst.w sl, #134217728 ; 0x8000000 ad8: d036 beq.n b48 <_i2c_m_sync_transfer+0xec> ada: f443 2380 orr.w r3, r3, #262144 ; 0x40000 ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; ade: 606b str r3, [r5, #4] hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); ae0: 2104 movs r1, #4 ae2: 4628 mov r0, r5 ae4: 47c0 blx r8 if (msg->addr & I2C_M_TEN) { ae6: 8823 ldrh r3, [r4, #0] ae8: 0559 lsls r1, r3, #21 ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN aea: ea4f 0243 mov.w r2, r3, lsl #1 if (msg->addr & I2C_M_TEN) { aee: d52e bpl.n b4e <_i2c_m_sync_transfer+0xf2> if (msg->flags & I2C_M_RD) { af0: 8863 ldrh r3, [r4, #2] af2: 07db lsls r3, r3, #31 msg->flags |= I2C_M_TEN; af4: bf41 itttt mi af6: 8863 ldrhmi r3, [r4, #2] af8: b29b uxthmi r3, r3 afa: f443 6380 orrmi.w r3, r3, #1024 ; 0x400 afe: 8063 strhmi r3, [r4, #2] hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); b00: 2104 movs r1, #4 b02: 47c0 blx r8 | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); b04: f022 0201 bic.w r2, r2, #1 return ((Sercom *)hw)->I2CM.ADDR.reg; b08: 6a6b ldr r3, [r5, #36] ; 0x24 b0a: 0552 lsls r2, r2, #21 b0c: 0d52 lsrs r2, r2, #21 b0e: f403 4380 and.w r3, r3, #16384 ; 0x4000 b12: 431a orrs r2, r3 hri_sercomi2cm_write_ADDR_reg(hw, b14: f442 4200 orr.w r2, r2, #32768 ; 0x8000 ((Sercom *)hw)->I2CM.ADDR.reg = data; b18: 626a str r2, [r5, #36] ; 0x24 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); b1a: 47c0 blx r8 void * hw = i2c_dev->hw; b1c: 6922 ldr r2, [r4, #16] b1e: f44f 3380 mov.w r3, #65536 ; 0x10000 return ((Sercom *)hw)->I2CM.INTFLAG.reg; b22: 7e11 ldrb r1, [r2, #24] if (timeout-- == 0) { b24: 3b01 subs r3, #1 b26: b2c9 uxtb r1, r1 b28: d001 beq.n b2e <_i2c_m_sync_transfer+0xd2> } while (!(*flags & MB_FLAG) && !(*flags & SB_FLAG)); b2a: 0788 lsls r0, r1, #30 b2c: d0f9 beq.n b22 <_i2c_m_sync_transfer+0xc6> return _sercom_i2c_sync_analyse_flags(hw, flags, msg); b2e: 4628 mov r0, r5 b30: 4622 mov r2, r4 b32: 4d21 ldr r5, [pc, #132] ; (bb8 <_i2c_m_sync_transfer+0x15c>) b34: 47a8 blx r5 if (ret) { b36: b1d0 cbz r0, b6e <_i2c_m_sync_transfer+0x112> i2c_dev->service.msg.flags &= ~I2C_M_BUSY; b38: 8863 ldrh r3, [r4, #2] b3a: f423 7380 bic.w r3, r3, #256 ; 0x100 b3e: 041b lsls r3, r3, #16 b40: 0c1b lsrs r3, r3, #16 b42: 8063 strh r3, [r4, #2] } b44: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; b48: f423 2380 bic.w r3, r3, #262144 ; 0x40000 b4c: e7c7 b.n ade <_i2c_m_sync_transfer+0x82> ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0) b4e: f8b4 9002 ldrh.w r9, [r4, #2] hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); b52: 2104 movs r1, #4 b54: 47c0 blx r8 b56: fa1f f989 uxth.w r9, r9 return ((Sercom *)hw)->I2CM.ADDR.reg; b5a: 6a6b ldr r3, [r5, #36] ; 0x24 b5c: b2d2 uxtb r2, r2 b5e: f009 0901 and.w r9, r9, #1 b62: ea42 0209 orr.w r2, r2, r9 | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); b66: f403 4380 and.w r3, r3, #16384 ; 0x4000 hri_sercomi2cm_write_ADDR_reg(hw, b6a: 431a orrs r2, r3 b6c: e7d4 b.n b18 <_i2c_m_sync_transfer+0xbc> while (i2c_dev->service.msg.flags & I2C_M_BUSY) { b6e: 8863 ldrh r3, [r4, #2] b70: 05da lsls r2, r3, #23 b72: d5e7 bpl.n b44 <_i2c_m_sync_transfer+0xe8> void * hw = i2c_dev->hw; b74: 6922 ldr r2, [r4, #16] b76: f44f 3380 mov.w r3, #65536 ; 0x10000 return ((Sercom *)hw)->I2CM.INTFLAG.reg; b7a: 7e11 ldrb r1, [r2, #24] if (timeout-- == 0) { b7c: 3b01 subs r3, #1 b7e: b2c9 uxtb r1, r1 b80: d008 beq.n b94 <_i2c_m_sync_transfer+0x138> } while (!(*flags & MB_FLAG) && !(*flags & SB_FLAG)); b82: 0788 lsls r0, r1, #30 b84: d0f9 beq.n b7a <_i2c_m_sync_transfer+0x11e> ret = _sercom_i2c_sync_analyse_flags(hw, flags, &i2c_dev->service.msg); b86: 4622 mov r2, r4 b88: 4638 mov r0, r7 b8a: 47a8 blx r5 b8c: e7ef b.n b6e <_i2c_m_sync_transfer+0x112> return I2C_ERR_BUSY; b8e: f06f 0005 mvn.w r0, #5 b92: e7d7 b.n b44 <_i2c_m_sync_transfer+0xe8> if (msg->flags & I2C_M_STOP) { b94: 8873 ldrh r3, [r6, #2] b96: 041b lsls r3, r3, #16 b98: d502 bpl.n ba0 <_i2c_m_sync_transfer+0x144> _sercom_i2c_send_stop(hw); b9a: 4b08 ldr r3, [pc, #32] ; (bbc <_i2c_m_sync_transfer+0x160>) b9c: 4638 mov r0, r7 b9e: 4798 blx r3 i2c_dev->service.msg.flags &= ~I2C_M_BUSY; ba0: 8863 ldrh r3, [r4, #2] ba2: f423 7380 bic.w r3, r3, #256 ; 0x100 ba6: 041b lsls r3, r3, #16 ba8: 0c1b lsrs r3, r3, #16 baa: 8063 strh r3, [r4, #2] return ret; bac: f06f 0004 mvn.w r0, #4 bb0: e7c8 b.n b44 <_i2c_m_sync_transfer+0xe8> bb2: bf00 nop bb4: 0000149d .word 0x0000149d bb8: 00000705 .word 0x00000705 bbc: 000006f1 .word 0x000006f1 bc0: 000005b1 .word 0x000005b1 bc4: 00000601 .word 0x00000601 00000bc8 : /** * \internal Sercom interrupt handler */ void SERCOM2_0_Handler(void) { _sercom_usart_interrupt_handler(_sercom2_dev); bc8: 4b19 ldr r3, [pc, #100] ; (c30 ) bca: 6818 ldr r0, [r3, #0] { bcc: b510 push {r4, lr} void *hw = device->hw; bce: 6984 ldr r4, [r0, #24] return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; bd0: 7e23 ldrb r3, [r4, #24] if (hri_sercomusart_get_interrupt_DRE_bit(hw) && hri_sercomusart_get_INTEN_DRE_bit(hw)) { bd2: 07da lsls r2, r3, #31 bd4: d508 bpl.n be8 return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_DRE) >> SERCOM_USART_INTENSET_DRE_Pos; bd6: 7da3 ldrb r3, [r4, #22] bd8: 07db lsls r3, r3, #31 bda: d505 bpl.n be8 ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; bdc: 2301 movs r3, #1 bde: 7523 strb r3, [r4, #20] device->usart_cb.tx_byte_sent(device); be0: 6803 ldr r3, [r0, #0] } be2: e8bd 4010 ldmia.w sp!, {r4, lr} device->usart_cb.tx_done_cb(device); be6: 4718 bx r3 return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; be8: 7e23 ldrb r3, [r4, #24] } else if (hri_sercomusart_get_interrupt_TXC_bit(hw) && hri_sercomusart_get_INTEN_TXC_bit(hw)) { bea: 0799 lsls r1, r3, #30 bec: d506 bpl.n bfc return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_TXC) >> SERCOM_USART_INTENSET_TXC_Pos; bee: 7da3 ldrb r3, [r4, #22] bf0: 079a lsls r2, r3, #30 bf2: d503 bpl.n bfc ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; bf4: 2302 movs r3, #2 bf6: 7523 strb r3, [r4, #20] device->usart_cb.tx_done_cb(device); bf8: 6883 ldr r3, [r0, #8] bfa: e7f2 b.n be2 return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; bfc: 7e23 ldrb r3, [r4, #24] } else if (hri_sercomusart_get_interrupt_RXC_bit(hw)) { bfe: 075b lsls r3, r3, #29 c00: d50c bpl.n c1c return ((Sercom *)hw)->USART.STATUS.reg; c02: 8b63 ldrh r3, [r4, #26] if (hri_sercomusart_read_STATUS_reg(hw) c04: f003 0337 and.w r3, r3, #55 ; 0x37 c08: b113 cbz r3, c10 ((Sercom *)hw)->USART.STATUS.reg = mask; c0a: 23ff movs r3, #255 ; 0xff c0c: 8363 strh r3, [r4, #26] } c0e: bd10 pop {r4, pc} return ((Sercom *)hw)->USART.DATA.reg; c10: 6aa1 ldr r1, [r4, #40] ; 0x28 device->usart_cb.rx_done_cb(device, hri_sercomusart_read_DATA_reg(hw)); c12: 6843 ldr r3, [r0, #4] } c14: e8bd 4010 ldmia.w sp!, {r4, lr} device->usart_cb.rx_done_cb(device, hri_sercomusart_read_DATA_reg(hw)); c18: b2c9 uxtb r1, r1 c1a: 4718 bx r3 return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; c1c: 7e23 ldrb r3, [r4, #24] } else if (hri_sercomusart_get_interrupt_ERROR_bit(hw)) { c1e: 09db lsrs r3, r3, #7 c20: d0f5 beq.n c0e ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; c22: 2380 movs r3, #128 ; 0x80 c24: 7623 strb r3, [r4, #24] device->usart_cb.error_cb(device); c26: 68c3 ldr r3, [r0, #12] c28: 4798 blx r3 return ((Sercom *)hw)->USART.STATUS.reg; c2a: 8b63 ldrh r3, [r4, #26] c2c: b29b uxth r3, r3 c2e: e7ed b.n c0c c30: 2000002c .word 0x2000002c 00000c34 : c34: 4b00 ldr r3, [pc, #0] ; (c38 ) c36: 4718 bx r3 c38: 00000bc9 .word 0x00000bc9 00000c3c : c3c: 4b00 ldr r3, [pc, #0] ; (c40 ) c3e: 4718 bx r3 c40: 00000bc9 .word 0x00000bc9 00000c44 : c44: 4b00 ldr r3, [pc, #0] ; (c48 ) c46: 4718 bx r3 c48: 00000bc9 .word 0x00000bc9 00000c4c <_gclk_init_generators_by_fref>: void _gclk_init_generators_by_fref(uint32_t bm) { #if CONF_GCLK_GENERATOR_0_CONFIG == 1 if (bm & (1ul << 0)) { c4c: 07c3 lsls r3, r0, #31 c4e: d507 bpl.n c60 <_gclk_init_generators_by_fref+0x14> } static inline void hri_gclk_write_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) { GCLK_CRITICAL_SECTION_ENTER(); ((Gclk *)hw)->GENCTRL[index].reg = data; c50: 4b04 ldr r3, [pc, #16] ; (c64 <_gclk_init_generators_by_fref+0x18>) c52: 4a05 ldr r2, [pc, #20] ; (c68 <_gclk_init_generators_by_fref+0x1c>) c54: 621a str r2, [r3, #32] while (((Gclk *)hw)->SYNCBUSY.reg & reg) { c56: f643 72fd movw r2, #16381 ; 0x3ffd c5a: 6859 ldr r1, [r3, #4] c5c: 4211 tst r1, r2 c5e: d1fc bne.n c5a <_gclk_init_generators_by_fref+0xe> | (CONF_GCLK_GEN_11_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_11_OE << GCLK_GENCTRL_OE_Pos) | (CONF_GCLK_GEN_11_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_11_IDC << GCLK_GENCTRL_IDC_Pos) | (CONF_GCLK_GENERATOR_11_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_11_SOURCE); } #endif } c60: 4770 bx lr c62: bf00 nop c64: 40001c00 .word 0x40001c00 c68: 00010107 .word 0x00010107 00000c6c : /** * \brief Default interrupt handler for unused IRQs. */ void Dummy_Handler(void) { while (1) { c6c: e7fe b.n c6c ... 00000c70 : if (pSrc != pDest) { c70: 4918 ldr r1, [pc, #96] ; (cd4 ) c72: 4819 ldr r0, [pc, #100] ; (cd8 ) c74: 4281 cmp r1, r0 { c76: b510 push {r4, lr} if (pSrc != pDest) { c78: d00a beq.n c90 *pDest++ = *pSrc++; c7a: 4b18 ldr r3, [pc, #96] ; (cdc ) c7c: 1cda adds r2, r3, #3 c7e: 1a12 subs r2, r2, r0 c80: f022 0203 bic.w r2, r2, #3 c84: 1ec4 subs r4, r0, #3 c86: 42a3 cmp r3, r4 c88: bf38 it cc c8a: 2200 movcc r2, #0 c8c: 4b14 ldr r3, [pc, #80] ; (ce0 ) c8e: 4798 blx r3 *pDest++ = 0; c90: 4b14 ldr r3, [pc, #80] ; (ce4 ) c92: 4815 ldr r0, [pc, #84] ; (ce8 ) c94: 1cda adds r2, r3, #3 c96: 1a12 subs r2, r2, r0 c98: 1ec1 subs r1, r0, #3 c9a: f022 0203 bic.w r2, r2, #3 c9e: 4299 cmp r1, r3 ca0: bf88 it hi ca2: 2200 movhi r2, #0 ca4: 4b11 ldr r3, [pc, #68] ; (cec ) ca6: 2100 movs r1, #0 ca8: 4798 blx r3 SCB->VTOR = ((uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk); caa: 4a11 ldr r2, [pc, #68] ; (cf0 ) cac: 4b11 ldr r3, [pc, #68] ; (cf4 ) cae: f022 027f bic.w r2, r2, #127 ; 0x7f cb2: 609a str r2, [r3, #8] SCB->CPACR |= (0xFu << 20); cb4: f8d3 2088 ldr.w r2, [r3, #136] ; 0x88 cb8: f442 0270 orr.w r2, r2, #15728640 ; 0xf00000 cbc: f8c3 2088 str.w r2, [r3, #136] ; 0x88 __ASM volatile ("dsb 0xF":::"memory"); cc0: f3bf 8f4f dsb sy __ASM volatile ("isb 0xF":::"memory"); cc4: f3bf 8f6f isb sy __libc_init_array(); cc8: 4b0b ldr r3, [pc, #44] ; (cf8 ) cca: 4798 blx r3 main(); ccc: 4b0b ldr r3, [pc, #44] ; (cfc ) cce: 4798 blx r3 while (1) cd0: e7fe b.n cd0 cd2: bf00 nop cd4: 000015ac .word 0x000015ac cd8: 20000000 .word 0x20000000 cdc: 20000000 .word 0x20000000 ce0: 00001421 .word 0x00001421 ce4: 200000d8 .word 0x200000d8 ce8: 20000000 .word 0x20000000 cec: 0000143d .word 0x0000143d cf0: 00000000 .word 0x00000000 cf4: e000ed00 .word 0xe000ed00 cf8: 000013d9 .word 0x000013d9 cfc: 00000d01 .word 0x00000d01 00000d00
: #include int x = 5; int main(void) { d00: b508 push {r3, lr} /* Initializes MCU, drivers and middleware */ atmel_start_init(); d02: 4b01 ldr r3, [pc, #4] ; (d08 ) d04: 4798 blx r3 /* Replace with your application code */ while (1) { d06: e7fe b.n d06 d08: 00001201 .word 0x00001201 00000d0c <_osc32kctrl_init_sources>: } static inline void hri_osc32kctrl_write_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) { OSC32KCTRL_CRITICAL_SECTION_ENTER(); ((Osc32kctrl *)hw)->XOSC32K.reg = data; d0c: 4b06 ldr r3, [pc, #24] ; (d28 <_osc32kctrl_init_sources+0x1c>) d0e: f242 328e movw r2, #9102 ; 0x238e d12: 829a strh r2, [r3, #20] } static inline void hri_osc32kctrl_write_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t data) { OSC32KCTRL_CRITICAL_SECTION_ENTER(); ((Osc32kctrl *)hw)->CFDCTRL.reg = data; d14: 2200 movs r2, #0 d16: 759a strb r2, [r3, #22] } static inline void hri_osc32kctrl_write_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t data) { OSC32KCTRL_CRITICAL_SECTION_ENTER(); ((Osc32kctrl *)hw)->EVCTRL.reg = data; d18: 75da strb r2, [r3, #23] } static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_CALIB_bf(const void *const hw) { uint32_t tmp; tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; d1a: 69da ldr r2, [r3, #28] calib = hri_osc32kctrl_read_OSCULP32K_CALIB_bf(hw); hri_osc32kctrl_write_OSCULP32K_reg(hw, #if CONF_OSCULP32K_CALIB_ENABLE == 1 OSC32KCTRL_OSCULP32K_CALIB(CONF_OSCULP32K_CALIB) #else OSC32KCTRL_OSCULP32K_CALIB(calib) d1c: f402 527c and.w r2, r2, #16128 ; 0x3f00 } static inline void hri_osc32kctrl_write_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data) { OSC32KCTRL_CRITICAL_SECTION_ENTER(); ((Osc32kctrl *)hw)->OSCULP32K.reg = data; d20: 61da str r2, [r3, #28] ((Osc32kctrl *)hw)->RTCCTRL.reg = data; d22: 2201 movs r2, #1 d24: 741a strb r2, [r3, #16] #endif #endif hri_osc32kctrl_write_RTCCTRL_reg(hw, OSC32KCTRL_RTCCTRL_RTCSEL(CONF_RTCCTRL)); (void)calib; } d26: 4770 bx lr d28: 40001400 .word 0x40001400 00000d2c <_gpio_set_pin_function>: /** * \brief Set gpio pin function */ static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function) { uint8_t port = GPIO_PORT(gpio); d2c: 0943 lsrs r3, r0, #5 static inline void hri_port_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, bool value) { uint8_t tmp; PORT_CRITICAL_SECTION_ENTER(); tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; d2e: 01db lsls r3, r3, #7 d30: f103 4382 add.w r3, r3, #1090519040 ; 0x41000000 { d34: b530 push {r4, r5, lr} d36: f503 4300 add.w r3, r3, #32768 ; 0x8000 uint8_t pin = GPIO_PIN(gpio); d3a: f000 041f and.w r4, r0, #31 d3e: 191d adds r5, r3, r4 d40: eb03 0354 add.w r3, r3, r4, lsr #1 d44: f895 2040 ldrb.w r2, [r5, #64] ; 0x40 tmp &= ~PORT_PINCFG_PMUXEN; d48: f002 02fe and.w r2, r2, #254 ; 0xfe tmp |= value << PORT_PINCFG_PMUXEN_Pos; d4c: f042 0201 orr.w r2, r2, #1 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; d50: f885 2040 strb.w r2, [r5, #64] ; 0x40 tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; d54: f893 2030 ldrb.w r2, [r3, #48] ; 0x30 hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, false); } else { hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, true); if (pin & 1) { d58: f010 0f01 tst.w r0, #1 // Odd numbered pin hri_port_write_PMUX_PMUXO_bf(PORT, port, pin >> 1, function & 0xffff); d5c: b2c9 uxtb r1, r1 tmp &= ~PORT_PMUX_PMUXO_Msk; d5e: bf1b ittet ne d60: f002 020f andne.w r2, r2, #15 tmp |= PORT_PMUX_PMUXO(data); d64: ea42 1201 orrne.w r2, r2, r1, lsl #4 tmp &= ~PORT_PMUX_PMUXE_Msk; d68: f002 02f0 andeq.w r2, r2, #240 ; 0xf0 tmp |= PORT_PMUX_PMUXO(data); d6c: b2d2 uxtbne r2, r2 tmp |= PORT_PMUX_PMUXE(data); d6e: bf0a itet eq d70: 4311 orreq r1, r2 ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; d72: f883 2030 strbne.w r2, [r3, #48] ; 0x30 ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; d76: f883 1030 strbeq.w r1, [r3, #48] ; 0x30 } else { // Even numbered pin hri_port_write_PMUX_PMUXE_bf(PORT, port, pin >> 1, function & 0xffff); } } } d7a: bd30 pop {r4, r5, pc} 00000d7c : } static inline void hri_gclk_write_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data) { GCLK_CRITICAL_SECTION_ENTER(); ((Gclk *)hw)->PCHCTRL[index].reg = data; d7c: 4b05 ldr r3, [pc, #20] ; (d94 ) d7e: 2240 movs r2, #64 ; 0x40 d80: f8c3 2090 str.w r2, [r3, #144] ; 0x90 } static inline void hri_mclk_set_APBAMASK_EIC_bit(const void *const hw) { MCLK_CRITICAL_SECTION_ENTER(); ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_EIC; d84: 4a04 ldr r2, [pc, #16] ; (d98 ) d86: 6953 ldr r3, [r2, #20] d88: f443 6380 orr.w r3, r3, #1024 ; 0x400 d8c: 6153 str r3, [r2, #20] void EXTERNAL_IRQ_0_init(void) { hri_gclk_write_PCHCTRL_reg(GCLK, EIC_GCLK_ID, CONF_GCLK_EIC_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); hri_mclk_set_APBAMASK_EIC_bit(MCLK); ext_irq_init(); d8e: 4b03 ldr r3, [pc, #12] ; (d9c ) d90: 4718 bx r3 d92: bf00 nop d94: 40001c00 .word 0x40001c00 d98: 40000800 .word 0x40000800 d9c: 00001105 .word 0x00001105 00000da0 : da0: 4b06 ldr r3, [pc, #24] ; (dbc ) da2: 2240 movs r2, #64 ; 0x40 da4: f8c3 20dc str.w r2, [r3, #220] ; 0xdc da8: 2243 movs r2, #67 ; 0x43 daa: f8c3 208c str.w r2, [r3, #140] ; 0x8c } static inline void hri_mclk_set_APBBMASK_SERCOM2_bit(const void *const hw) { MCLK_CRITICAL_SECTION_ENTER(); ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_SERCOM2; dae: 4a04 ldr r2, [pc, #16] ; (dc0 ) db0: 6993 ldr r3, [r2, #24] db2: f443 7300 orr.w r3, r3, #512 ; 0x200 db6: 6193 str r3, [r2, #24] hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK); } db8: 4770 bx lr dba: bf00 nop dbc: 40001c00 .word 0x40001c00 dc0: 40000800 .word 0x40000800 00000dc4 : * \brief USART pinmux initialization function * * Set each required pin to USART functionality */ void USART_0_PORT_init() { dc4: b510 push {r4, lr} * found in the header files for the device * */ static inline void gpio_set_pin_function(const uint32_t pin, uint32_t function) { _gpio_set_pin_function(pin, function); dc6: 4c05 ldr r4, [pc, #20] ; (ddc ) dc8: 4905 ldr r1, [pc, #20] ; (de0 ) dca: 2039 movs r0, #57 ; 0x39 dcc: 47a0 blx r4 dce: 4623 mov r3, r4 dd0: 4904 ldr r1, [pc, #16] ; (de4 ) gpio_set_pin_function(PB25, PINMUX_PB25D_SERCOM2_PAD0); gpio_set_pin_function(PB24, PINMUX_PB24D_SERCOM2_PAD1); } dd2: e8bd 4010 ldmia.w sp!, {r4, lr} dd6: 2038 movs r0, #56 ; 0x38 dd8: 4718 bx r3 dda: bf00 nop ddc: 00000d2d .word 0x00000d2d de0: 00390003 .word 0x00390003 de4: 00380003 .word 0x00380003 00000de8 : * \brief USART initialization function * * Enables USART peripheral, clocks and initializes USART driver */ void USART_0_init(void) { de8: b513 push {r0, r1, r4, lr} USART_0_CLOCK_init(); dea: 4b07 ldr r3, [pc, #28] ; (e08 ) usart_async_init(&USART_0, SERCOM2, USART_0_buffer, USART_0_BUFFER_SIZE, (void *)NULL); dec: 4907 ldr r1, [pc, #28] ; (e0c ) dee: 4c08 ldr r4, [pc, #32] ; (e10 ) USART_0_CLOCK_init(); df0: 4798 blx r3 usart_async_init(&USART_0, SERCOM2, USART_0_buffer, USART_0_BUFFER_SIZE, (void *)NULL); df2: 4a08 ldr r2, [pc, #32] ; (e14 ) df4: 2300 movs r3, #0 df6: 9300 str r3, [sp, #0] df8: 2310 movs r3, #16 dfa: 18d0 adds r0, r2, r3 dfc: 47a0 blx r4 USART_0_PORT_init(); dfe: 4b06 ldr r3, [pc, #24] ; (e18 ) } e00: b002 add sp, #8 e02: e8bd 4010 ldmia.w sp!, {r4, lr} USART_0_PORT_init(); e06: 4718 bx r3 e08: 00000da1 .word 0x00000da1 e0c: 41012000 .word 0x41012000 e10: 00001049 .word 0x00001049 e14: 20000030 .word 0x20000030 e18: 00000dc5 .word 0x00000dc5 00000e1c : void I2C_0_PORT_init(void) { e1c: b570 push {r4, r5, r6, lr} } static inline void hri_port_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) { PORT_CRITICAL_SECTION_ENTER(); ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; e1e: 4c0b ldr r4, [pc, #44] ; (e4c ) e20: 4d0b ldr r5, [pc, #44] ; (e50 ) e22: f894 3056 ldrb.w r3, [r4, #86] ; 0x56 e26: 490b ldr r1, [pc, #44] ; (e54 ) e28: f003 03fb and.w r3, r3, #251 ; 0xfb e2c: f884 3056 strb.w r3, [r4, #86] ; 0x56 e30: 2016 movs r0, #22 e32: 47a8 blx r5 e34: f894 3057 ldrb.w r3, [r4, #87] ; 0x57 e38: 4907 ldr r1, [pc, #28] ; (e58 ) e3a: f003 03fb and.w r3, r3, #251 ; 0xfb e3e: f884 3057 strb.w r3, [r4, #87] ; 0x57 e42: 2017 movs r0, #23 e44: 462b mov r3, r5 // Pull-up // Pull-down GPIO_PULL_OFF); gpio_set_pin_function(PA23, PINMUX_PA23C_SERCOM3_PAD1); } e46: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} e4a: 4718 bx r3 e4c: 41008000 .word 0x41008000 e50: 00000d2d .word 0x00000d2d e54: 00160002 .word 0x00160002 e58: 00170002 .word 0x00170002 00000e5c : e5c: 4b06 ldr r3, [pc, #24] ; (e78 ) e5e: 2240 movs r2, #64 ; 0x40 e60: f8c3 20e0 str.w r2, [r3, #224] ; 0xe0 e64: 2243 movs r2, #67 ; 0x43 e66: f8c3 208c str.w r2, [r3, #140] ; 0x8c } static inline void hri_mclk_set_APBBMASK_SERCOM3_bit(const void *const hw) { MCLK_CRITICAL_SECTION_ENTER(); ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_SERCOM3; e6a: 4a04 ldr r2, [pc, #16] ; (e7c ) e6c: 6993 ldr r3, [r2, #24] e6e: f443 6380 orr.w r3, r3, #1024 ; 0x400 e72: 6193 str r3, [r2, #24] { hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM3_GCLK_ID_CORE, CONF_GCLK_SERCOM3_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM3_GCLK_ID_SLOW, CONF_GCLK_SERCOM3_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); hri_mclk_set_APBBMASK_SERCOM3_bit(MCLK); } e74: 4770 bx lr e76: bf00 nop e78: 40001c00 .word 0x40001c00 e7c: 40000800 .word 0x40000800 00000e80 : void I2C_0_init(void) { e80: b510 push {r4, lr} I2C_0_CLOCK_init(); e82: 4b05 ldr r3, [pc, #20] ; (e98 ) i2c_m_sync_init(&I2C_0, SERCOM3); e84: 4905 ldr r1, [pc, #20] ; (e9c ) e86: 4806 ldr r0, [pc, #24] ; (ea0 ) I2C_0_CLOCK_init(); e88: 4798 blx r3 i2c_m_sync_init(&I2C_0, SERCOM3); e8a: 4b06 ldr r3, [pc, #24] ; (ea4 ) e8c: 4798 blx r3 I2C_0_PORT_init(); } e8e: e8bd 4010 ldmia.w sp!, {r4, lr} I2C_0_PORT_init(); e92: 4b05 ldr r3, [pc, #20] ; (ea8 ) e94: 4718 bx r3 e96: bf00 nop e98: 00000e5d .word 0x00000e5d e9c: 41014000 .word 0x41014000 ea0: 20000090 .word 0x20000090 ea4: 000004a9 .word 0x000004a9 ea8: 00000e1d .word 0x00000e1d 00000eac : timer_init(&TIMER_0, TC0, _tc_get_timer()); } void system_init(void) { eac: b510 push {r4, lr} * Currently the following initialization functions are supported: * - System clock initialization */ static inline void init_mcu(void) { _init_chip(); eae: 4b0d ldr r3, [pc, #52] ; (ee4 ) eb0: 4798 blx r3 init_mcu(); EXTERNAL_IRQ_0_init(); eb2: 4b0d ldr r3, [pc, #52] ; (ee8 ) eb4: 4798 blx r3 USART_0_init(); eb6: 4b0d ldr r3, [pc, #52] ; (eec ) eb8: 4798 blx r3 I2C_0_init(); eba: 4b0d ldr r3, [pc, #52] ; (ef0 ) ebc: 4798 blx r3 ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_TC0; ebe: 4a0d ldr r2, [pc, #52] ; (ef4 ) ec0: 6953 ldr r3, [r2, #20] ec2: f443 4380 orr.w r3, r3, #16384 ; 0x4000 ec6: 6153 str r3, [r2, #20] ec8: 4b0b ldr r3, [pc, #44] ; (ef8 ) eca: 2240 movs r2, #64 ; 0x40 ecc: f8c3 20a4 str.w r2, [r3, #164] ; 0xa4 timer_init(&TIMER_0, TC0, _tc_get_timer()); ed0: 4b0a ldr r3, [pc, #40] ; (efc ) ed2: 4798 blx r3 TIMER_0_init(); } ed4: e8bd 4010 ldmia.w sp!, {r4, lr} timer_init(&TIMER_0, TC0, _tc_get_timer()); ed8: 4602 mov r2, r0 eda: 4909 ldr r1, [pc, #36] ; (f00 ) edc: 4809 ldr r0, [pc, #36] ; (f04 ) ede: 4b0a ldr r3, [pc, #40] ; (f08 ) ee0: 4718 bx r3 ee2: bf00 nop ee4: 000004e5 .word 0x000004e5 ee8: 00000d7d .word 0x00000d7d eec: 00000de9 .word 0x00000de9 ef0: 00000e81 .word 0x00000e81 ef4: 40000800 .word 0x40000800 ef8: 40001c00 .word 0x40001c00 efc: 0000139d .word 0x0000139d f00: 40003800 .word 0x40003800 f04: 200000b0 .word 0x200000b0 f08: 00000419 .word 0x00000419 00000f0c : */ static void usart_transmission_complete(struct _usart_async_device *device) { struct usart_async_descriptor *descr = CONTAINER_OF(device, struct usart_async_descriptor, device); descr->stat = 0; f0c: 2300 movs r3, #0 f0e: 6283 str r3, [r0, #40] ; 0x28 if (descr->usart_cb.tx_done) { f10: 69c3 ldr r3, [r0, #28] f12: b10b cbz r3, f18 descr->usart_cb.tx_done(descr); f14: 3808 subs r0, #8 f16: 4718 bx r3 } } f18: 4770 bx lr 00000f1a : */ static void usart_error(struct _usart_async_device *device) { struct usart_async_descriptor *descr = CONTAINER_OF(device, struct usart_async_descriptor, device); descr->stat = 0; f1a: 2300 movs r3, #0 f1c: 6283 str r3, [r0, #40] ; 0x28 if (descr->usart_cb.error) { f1e: 6a43 ldr r3, [r0, #36] ; 0x24 f20: b10b cbz r3, f26 descr->usart_cb.error(descr); f22: 3808 subs r0, #8 f24: 4718 bx r3 } } f26: 4770 bx lr 00000f28 : { f28: b570 push {r4, r5, r6, lr} f2a: 4604 mov r4, r0 ringbuffer_put(&descr->rx, data); f2c: 4b05 ldr r3, [pc, #20] ; (f44 ) f2e: f1a0 0508 sub.w r5, r0, #8 f32: 302c adds r0, #44 ; 0x2c f34: 4798 blx r3 if (descr->usart_cb.rx_done) { f36: 6a23 ldr r3, [r4, #32] f38: b11b cbz r3, f42 descr->usart_cb.rx_done(descr); f3a: 4628 mov r0, r5 } f3c: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} descr->usart_cb.rx_done(descr); f40: 4718 bx r3 } f42: bd70 pop {r4, r5, r6, pc} f44: 000011a1 .word 0x000011a1 00000f48 : { f48: b570 push {r4, r5, r6, lr} f4a: 460e mov r6, r1 f4c: 4615 mov r5, r2 ASSERT(descr && buf && length); f4e: 4604 mov r4, r0 f50: b118 cbz r0, f5a f52: b1d9 cbz r1, f8c f54: 1e10 subs r0, r2, #0 f56: bf18 it ne f58: 2001 movne r0, #1 f5a: 4b0f ldr r3, [pc, #60] ; (f98 ) f5c: 490f ldr r1, [pc, #60] ; (f9c ) f5e: f240 123b movw r2, #315 ; 0x13b f62: 4798 blx r3 if (descr->tx_por != descr->tx_buffer_length) { f64: f8b4 2044 ldrh.w r2, [r4, #68] ; 0x44 f68: f8b4 304c ldrh.w r3, [r4, #76] ; 0x4c f6c: 429a cmp r2, r3 f6e: d10f bne.n f90 descr->tx_por = 0; f70: 2300 movs r3, #0 f72: f8a4 3044 strh.w r3, [r4, #68] ; 0x44 descr->stat = USART_ASYNC_STATUS_BUSY; f76: 2301 movs r3, #1 f78: 6323 str r3, [r4, #48] ; 0x30 _usart_async_enable_byte_sent_irq(&descr->device); f7a: f104 0008 add.w r0, r4, #8 f7e: 4b08 ldr r3, [pc, #32] ; (fa0 ) descr->tx_buffer = (uint8_t *)buf; f80: 64a6 str r6, [r4, #72] ; 0x48 descr->tx_buffer_length = length; f82: f8a4 504c strh.w r5, [r4, #76] ; 0x4c _usart_async_enable_byte_sent_irq(&descr->device); f86: 4798 blx r3 return (int32_t)length; f88: 4628 mov r0, r5 } f8a: bd70 pop {r4, r5, r6, pc} ASSERT(descr && buf && length); f8c: 4608 mov r0, r1 f8e: e7e4 b.n f5a return ERR_NO_RESOURCE; f90: f06f 001b mvn.w r0, #27 f94: e7f9 b.n f8a f96: bf00 nop f98: 000005b1 .word 0x000005b1 f9c: 00001501 .word 0x00001501 fa0: 00000a1f .word 0x00000a1f 00000fa4 : if (descr->tx_por != descr->tx_buffer_length) { fa4: 8f83 ldrh r3, [r0, #60] ; 0x3c fa6: f8b0 2044 ldrh.w r2, [r0, #68] ; 0x44 faa: 429a cmp r2, r3 { fac: b510 push {r4, lr} fae: 4604 mov r4, r0 if (descr->tx_por != descr->tx_buffer_length) { fb0: d00a beq.n fc8 _usart_async_write_byte(&descr->device, descr->tx_buffer[descr->tx_por++]); fb2: 6c02 ldr r2, [r0, #64] ; 0x40 fb4: 1c59 adds r1, r3, #1 fb6: 8781 strh r1, [r0, #60] ; 0x3c fb8: 5cd1 ldrb r1, [r2, r3] fba: 4b04 ldr r3, [pc, #16] ; (fcc ) fbc: 4798 blx r3 _usart_async_enable_byte_sent_irq(&descr->device); fbe: 4b04 ldr r3, [pc, #16] ; (fd0 ) fc0: 4620 mov r0, r4 } fc2: e8bd 4010 ldmia.w sp!, {r4, lr} _usart_async_enable_tx_done_irq(&descr->device); fc6: 4718 bx r3 fc8: 4b02 ldr r3, [pc, #8] ; (fd4 ) fca: e7fa b.n fc2 fcc: 00000a19 .word 0x00000a19 fd0: 00000a1f .word 0x00000a1f fd4: 00000a27 .word 0x00000a27 00000fd8 : { fd8: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr} fdc: 460e mov r6, r1 fde: 4617 mov r7, r2 ASSERT(descr && buf && length); fe0: 4604 mov r4, r0 fe2: b118 cbz r0, fec fe4: b1e9 cbz r1, 1022 fe6: 1e10 subs r0, r2, #0 fe8: bf18 it ne fea: 2001 movne r0, #1 fec: 4910 ldr r1, [pc, #64] ; (1030 ) fee: 4b11 ldr r3, [pc, #68] ; (1034 ) ringbuffer_get(&descr->rx, &buf[was_read++]); ff0: f8df 9050 ldr.w r9, [pc, #80] ; 1044 ASSERT(descr && buf && length); ff4: f44f 72ac mov.w r2, #344 ; 0x158 ff8: 4798 blx r3 num = ringbuffer_num(&descr->rx); ffa: 3434 adds r4, #52 ; 0x34 CRITICAL_SECTION_ENTER() ffc: 4b0e ldr r3, [pc, #56] ; (1038 ) ffe: a801 add r0, sp, #4 1000: 4798 blx r3 num = ringbuffer_num(&descr->rx); 1002: 4b0e ldr r3, [pc, #56] ; (103c ) 1004: 4620 mov r0, r4 1006: 4798 blx r3 CRITICAL_SECTION_LEAVE() 1008: 4b0d ldr r3, [pc, #52] ; (1040 ) num = ringbuffer_num(&descr->rx); 100a: 4680 mov r8, r0 CRITICAL_SECTION_LEAVE() 100c: a801 add r0, sp, #4 100e: 4798 blx r3 while ((was_read < num) && (was_read < length)) { 1010: 2500 movs r5, #0 1012: 45a8 cmp r8, r5 1014: d001 beq.n 101a 1016: 42bd cmp r5, r7 1018: d105 bne.n 1026 } 101a: 4628 mov r0, r5 101c: b003 add sp, #12 101e: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} ASSERT(descr && buf && length); 1022: 4608 mov r0, r1 1024: e7e2 b.n fec ringbuffer_get(&descr->rx, &buf[was_read++]); 1026: 1971 adds r1, r6, r5 1028: 4620 mov r0, r4 102a: 47c8 blx r9 102c: 3501 adds r5, #1 102e: e7f0 b.n 1012 1030: 00001501 .word 0x00001501 1034: 000005b1 .word 0x000005b1 1038: 000013bd .word 0x000013bd 103c: 000011e1 .word 0x000011e1 1040: 000013cb .word 0x000013cb 1044: 00001161 .word 0x00001161 00001048 : { 1048: b5f8 push {r3, r4, r5, r6, r7, lr} 104a: 460d mov r5, r1 104c: 4616 mov r6, r2 104e: 461f mov r7, r3 ASSERT(descr && hw && rx_buffer && rx_buffer_length); 1050: 4604 mov r4, r0 1052: b120 cbz r0, 105e 1054: b309 cbz r1, 109a 1056: b312 cbz r2, 109e 1058: 1e18 subs r0, r3, #0 105a: bf18 it ne 105c: 2001 movne r0, #1 105e: 4912 ldr r1, [pc, #72] ; (10a8 ) 1060: 4b12 ldr r3, [pc, #72] ; (10ac ) 1062: 223a movs r2, #58 ; 0x3a 1064: 4798 blx r3 if (ERR_NONE != ringbuffer_init(&descr->rx, rx_buffer, rx_buffer_length)) { 1066: 4b12 ldr r3, [pc, #72] ; (10b0 ) 1068: 463a mov r2, r7 106a: 4631 mov r1, r6 106c: f104 0034 add.w r0, r4, #52 ; 0x34 1070: 4798 blx r3 1072: b9b0 cbnz r0, 10a2 init_status = _usart_async_init(&descr->device, hw); 1074: 4b0f ldr r3, [pc, #60] ; (10b4 ) 1076: 4629 mov r1, r5 1078: f104 0008 add.w r0, r4, #8 107c: 4798 blx r3 if (init_status) { 107e: b958 cbnz r0, 1098 descr->io.read = usart_async_read; 1080: 4b0d ldr r3, [pc, #52] ; (10b8 ) 1082: 6063 str r3, [r4, #4] descr->io.write = usart_async_write; 1084: 4b0d ldr r3, [pc, #52] ; (10bc ) 1086: 6023 str r3, [r4, #0] descr->device.usart_cb.tx_byte_sent = usart_process_byte_sent; 1088: 4b0d ldr r3, [pc, #52] ; (10c0 ) 108a: 60a3 str r3, [r4, #8] descr->device.usart_cb.rx_done_cb = usart_fill_rx_buffer; 108c: 4b0d ldr r3, [pc, #52] ; (10c4 ) 108e: 60e3 str r3, [r4, #12] descr->device.usart_cb.tx_done_cb = usart_transmission_complete; 1090: 4b0d ldr r3, [pc, #52] ; (10c8 ) 1092: 6123 str r3, [r4, #16] descr->device.usart_cb.error_cb = usart_error; 1094: 4b0d ldr r3, [pc, #52] ; (10cc ) 1096: 6163 str r3, [r4, #20] } 1098: bdf8 pop {r3, r4, r5, r6, r7, pc} ASSERT(descr && hw && rx_buffer && rx_buffer_length); 109a: 4608 mov r0, r1 109c: e7df b.n 105e 109e: 4610 mov r0, r2 10a0: e7dd b.n 105e return ERR_INVALID_ARG; 10a2: f06f 000c mvn.w r0, #12 10a6: e7f7 b.n 1098 10a8: 00001501 .word 0x00001501 10ac: 000005b1 .word 0x000005b1 10b0: 00001125 .word 0x00001125 10b4: 00000995 .word 0x00000995 10b8: 00000fd9 .word 0x00000fd9 10bc: 00000f49 .word 0x00000f49 10c0: 00000fa5 .word 0x00000fa5 10c4: 00000f29 .word 0x00000f29 10c8: 00000f0d .word 0x00000f0d 10cc: 00000f1b .word 0x00000f1b 000010d0 : middle = (upper + lower) >> 1; if (middle >= EXT_IRQ_AMOUNT) { return; } if (ext_irqs[middle].pin == pin) { 10d0: 490b ldr r1, [pc, #44] ; (1100 ) { 10d2: b430 push {r4, r5} if (ext_irqs[middle].pin == pin) { 10d4: 684d ldr r5, [r1, #4] uint8_t lower = 0, middle, upper = EXT_IRQ_AMOUNT; 10d6: 2201 movs r2, #1 10d8: 2300 movs r3, #0 while (upper >= lower) { 10da: 429a cmp r2, r3 10dc: d201 bcs.n 10e2 lower = middle + 1; } else { upper = middle - 1; } } } 10de: bc30 pop {r4, r5} 10e0: 4770 bx lr middle = (upper + lower) >> 1; 10e2: 18d4 adds r4, r2, r3 if (middle >= EXT_IRQ_AMOUNT) { 10e4: 0864 lsrs r4, r4, #1 10e6: d1fa bne.n 10de if (ext_irqs[middle].pin == pin) { 10e8: 4285 cmp r5, r0 10ea: d104 bne.n 10f6 if (ext_irqs[middle].cb) { 10ec: 680b ldr r3, [r1, #0] 10ee: 2b00 cmp r3, #0 10f0: d0f5 beq.n 10de } 10f2: bc30 pop {r4, r5} ext_irqs[middle].cb(); 10f4: 4718 bx r3 upper = middle - 1; 10f6: bf2c ite cs 10f8: 22ff movcs r2, #255 ; 0xff lower = middle + 1; 10fa: 2301 movcc r3, #1 10fc: e7ed b.n 10da 10fe: bf00 nop 1100: 200000cc .word 0x200000cc 00001104 : ext_irqs[i].pin = 0xFFFFFFFF; 1104: 4b04 ldr r3, [pc, #16] ; (1118 ) return _ext_irq_init(process_ext_irq); 1106: 4805 ldr r0, [pc, #20] ; (111c ) ext_irqs[i].cb = NULL; 1108: 2200 movs r2, #0 110a: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff 110e: e9c3 2100 strd r2, r1, [r3] return _ext_irq_init(process_ext_irq); 1112: 4b03 ldr r3, [pc, #12] ; (1120 ) 1114: 4718 bx r3 1116: bf00 nop 1118: 200000cc .word 0x200000cc 111c: 000010d1 .word 0x000010d1 1120: 000002fd .word 0x000002fd 00001124 : /** * \brief Ringbuffer init */ int32_t ringbuffer_init(struct ringbuffer *const rb, void *buf, uint32_t size) { 1124: b570 push {r4, r5, r6, lr} 1126: 460e mov r6, r1 1128: 4614 mov r4, r2 ASSERT(rb && buf && size); 112a: 4605 mov r5, r0 112c: b118 cbz r0, 1136 112e: b189 cbz r1, 1154 1130: 1e10 subs r0, r2, #0 1132: bf18 it ne 1134: 2001 movne r0, #1 1136: 4908 ldr r1, [pc, #32] ; (1158 ) 1138: 4b08 ldr r3, [pc, #32] ; (115c ) 113a: 2228 movs r2, #40 ; 0x28 113c: 4798 blx r3 /* * buf size must be aligned to power of 2 */ if ((size & (size - 1)) != 0) { 113e: 1e63 subs r3, r4, #1 1140: ea13 0004 ands.w r0, r3, r4 return ERR_INVALID_ARG; } /* size - 1 is faster in calculation */ rb->size = size - 1; rb->read_index = 0; 1144: bf03 ittte eq 1146: e9c5 3001 strdeq r3, r0, [r5, #4] rb->write_index = rb->read_index; 114a: 60e8 streq r0, [r5, #12] rb->buf = (uint8_t *)buf; 114c: 602e streq r6, [r5, #0] return ERR_INVALID_ARG; 114e: f06f 000c mvnne.w r0, #12 return ERR_NONE; } 1152: bd70 pop {r4, r5, r6, pc} ASSERT(rb && buf && size); 1154: 4608 mov r0, r1 1156: e7ee b.n 1136 1158: 0000151e .word 0x0000151e 115c: 000005b1 .word 0x000005b1 00001160 : /** * \brief Get one byte from ringbuffer * */ int32_t ringbuffer_get(struct ringbuffer *const rb, uint8_t *data) { 1160: b538 push {r3, r4, r5, lr} 1162: 460d mov r5, r1 ASSERT(rb && data); 1164: 4604 mov r4, r0 1166: b110 cbz r0, 116e 1168: 1e08 subs r0, r1, #0 116a: bf18 it ne 116c: 2001 movne r0, #1 116e: 4b0a ldr r3, [pc, #40] ; (1198 ) 1170: 490a ldr r1, [pc, #40] ; (119c ) 1172: 2240 movs r2, #64 ; 0x40 1174: 4798 blx r3 if (rb->write_index != rb->read_index) { 1176: e9d4 3202 ldrd r3, r2, [r4, #8] 117a: 429a cmp r2, r3 117c: d009 beq.n 1192 *data = rb->buf[rb->read_index & rb->size]; 117e: 6862 ldr r2, [r4, #4] 1180: 4013 ands r3, r2 1182: 6822 ldr r2, [r4, #0] 1184: 5cd3 ldrb r3, [r2, r3] 1186: 702b strb r3, [r5, #0] rb->read_index++; 1188: 68a3 ldr r3, [r4, #8] 118a: 3301 adds r3, #1 118c: 60a3 str r3, [r4, #8] return ERR_NONE; 118e: 2000 movs r0, #0 } return ERR_NOT_FOUND; } 1190: bd38 pop {r3, r4, r5, pc} return ERR_NOT_FOUND; 1192: f06f 0009 mvn.w r0, #9 1196: e7fb b.n 1190 1198: 000005b1 .word 0x000005b1 119c: 0000151e .word 0x0000151e 000011a0 : /** * \brief Put one byte to ringbuffer * */ int32_t ringbuffer_put(struct ringbuffer *const rb, uint8_t data) { 11a0: b538 push {r3, r4, r5, lr} 11a2: 4604 mov r4, r0 11a4: 460d mov r5, r1 ASSERT(rb); 11a6: 4b0c ldr r3, [pc, #48] ; (11d8 ) 11a8: 490c ldr r1, [pc, #48] ; (11dc ) 11aa: 2251 movs r2, #81 ; 0x51 11ac: 2001 movs r0, #1 11ae: 4798 blx r3 rb->buf[rb->write_index & rb->size] = data; 11b0: 68e3 ldr r3, [r4, #12] 11b2: 6862 ldr r2, [r4, #4] 11b4: 4013 ands r3, r2 11b6: 6822 ldr r2, [r4, #0] 11b8: 54d5 strb r5, [r2, r3] /* * buffer full strategy: new data will overwrite the oldest data in * the buffer */ if ((rb->write_index - rb->read_index) > rb->size) { 11ba: e9d4 2101 ldrd r2, r1, [r4, #4] 11be: 68e3 ldr r3, [r4, #12] 11c0: 1a59 subs r1, r3, r1 11c2: 4291 cmp r1, r2 rb->read_index = rb->write_index - rb->size; 11c4: bf88 it hi 11c6: 1a9a subhi r2, r3, r2 } rb->write_index++; 11c8: f103 0301 add.w r3, r3, #1 rb->read_index = rb->write_index - rb->size; 11cc: bf88 it hi 11ce: 60a2 strhi r2, [r4, #8] rb->write_index++; 11d0: 60e3 str r3, [r4, #12] return ERR_NONE; } 11d2: 2000 movs r0, #0 11d4: bd38 pop {r3, r4, r5, pc} 11d6: bf00 nop 11d8: 000005b1 .word 0x000005b1 11dc: 0000151e .word 0x0000151e 000011e0 : /** * \brief Return the element number of ringbuffer */ uint32_t ringbuffer_num(const struct ringbuffer *const rb) { 11e0: b510 push {r4, lr} ASSERT(rb); 11e2: 4905 ldr r1, [pc, #20] ; (11f8 ) 11e4: 4b05 ldr r3, [pc, #20] ; (11fc ) { 11e6: 4604 mov r4, r0 ASSERT(rb); 11e8: 2267 movs r2, #103 ; 0x67 11ea: 2001 movs r0, #1 11ec: 4798 blx r3 return rb->write_index - rb->read_index; 11ee: e9d4 3002 ldrd r3, r0, [r4, #8] } 11f2: 1ac0 subs r0, r0, r3 11f4: bd10 pop {r4, pc} 11f6: bf00 nop 11f8: 0000151e .word 0x0000151e 11fc: 000005b1 .word 0x000005b1 00001200 : /** * Initializes MCU, drivers and middleware in the project **/ void atmel_start_init(void) { system_init(); 1200: 4b00 ldr r3, [pc, #0] ; (1204 ) 1202: 4718 bx r3 1204: 00000ead .word 0x00000ead 00001208 : typedef uint8_t hri_tccount8_per_reg_t; typedef uint8_t hri_tccount8_perbuf_reg_t; static inline void hri_tc_wait_for_sync(const void *const hw, hri_tc_syncbusy_reg_t reg) { while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) { 1208: 6903 ldr r3, [r0, #16] 120a: 420b tst r3, r1 120c: d1fc bne.n 1208 }; } 120e: 4770 bx lr 00001210 : * \param[in] hw The pointer to hardware instance * * \return The index of TC configuration */ static int8_t get_tc_index(const void *const hw) { 1210: b570 push {r4, r5, r6, lr} * \param[in] hw The pointer to hardware instance */ static inline uint8_t _get_hardware_offset(const void *const hw) { /* List of available TC modules. */ Tc *const tc_modules[TC_INST_NUM] = TC_INSTS; 1212: 4d10 ldr r5, [pc, #64] ; (1254 ) { 1214: 4606 mov r6, r0 Tc *const tc_modules[TC_INST_NUM] = TC_INSTS; 1216: cd0f ldmia r5!, {r0, r1, r2, r3} { 1218: b088 sub sp, #32 Tc *const tc_modules[TC_INST_NUM] = TC_INSTS; 121a: 466c mov r4, sp 121c: c40f stmia r4!, {r0, r1, r2, r3} 121e: e895 000f ldmia.w r5, {r0, r1, r2, r3} 1222: e884 000f stmia.w r4, {r0, r1, r2, r3} /* Find index for TC instance. */ for (uint32_t i = 0; i < TC_INST_NUM; i++) { 1226: 466a mov r2, sp 1228: 2000 movs r0, #0 if ((uint32_t)hw == (uint32_t)tc_modules[i]) { 122a: f852 1b04 ldr.w r1, [r2], #4 122e: 42b1 cmp r1, r6 1230: d102 bne.n 1238 if (_tcs[i].number == index) { 1232: b930 cbnz r0, 1242 } 1234: b008 add sp, #32 1236: bd70 pop {r4, r5, r6, pc} for (uint32_t i = 0; i < TC_INST_NUM; i++) { 1238: 3001 adds r0, #1 123a: 2808 cmp r0, #8 123c: d1f5 bne.n 122a return i; 123e: 2000 movs r0, #0 1240: e7f8 b.n 1234 ASSERT(false); 1242: 2000 movs r0, #0 1244: 4904 ldr r1, [pc, #16] ; (1258 ) 1246: 4b05 ldr r3, [pc, #20] ; (125c ) 1248: f44f 729e mov.w r2, #316 ; 0x13c 124c: 4798 blx r3 124e: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 1252: e7ef b.n 1234 1254: 00001558 .word 0x00001558 1258: 00001542 .word 0x00001542 125c: 000005b1 .word 0x000005b1 00001260 <_timer_init>: { 1260: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} int8_t i = get_tc_index(hw); 1264: 4b45 ldr r3, [pc, #276] ; (137c <_timer_init+0x11c>) { 1266: 4681 mov r9, r0 int8_t i = get_tc_index(hw); 1268: 4608 mov r0, r1 { 126a: 460c mov r4, r1 int8_t i = get_tc_index(hw); 126c: 4798 blx r3 ASSERT(ARRAY_SIZE(_tcs)); 126e: 4b44 ldr r3, [pc, #272] ; (1380 <_timer_init+0x120>) 1270: 4944 ldr r1, [pc, #272] ; (1384 <_timer_init+0x124>) device->hw = hw; 1272: f8c9 400c str.w r4, [r9, #12] ASSERT(ARRAY_SIZE(_tcs)); 1276: 228d movs r2, #141 ; 0x8d int8_t i = get_tc_index(hw); 1278: 4680 mov r8, r0 ASSERT(ARRAY_SIZE(_tcs)); 127a: 2001 movs r0, #1 127c: 4798 blx r3 static inline bool hri_tc_is_syncing(const void *const hw, hri_tc_syncbusy_reg_t reg) { return ((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg; 127e: 6923 ldr r3, [r4, #16] 1280: 4a41 ldr r2, [pc, #260] ; (1388 <_timer_init+0x128>) if (!hri_tc_is_syncing(hw, TC_SYNCBUSY_SWRST)) { 1282: f013 0f01 tst.w r3, #1 1286: d111 bne.n 12ac <_timer_init+0x4c> } static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) { uint32_t tmp; hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); 1288: 2103 movs r1, #3 128a: 4620 mov r0, r4 128c: 4790 blx r2 tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; 128e: 6823 ldr r3, [r4, #0] if (hri_tc_get_CTRLA_reg(hw, TC_CTRLA_ENABLE)) { 1290: 079b lsls r3, r3, #30 1292: d506 bpl.n 12a2 <_timer_init+0x42> ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE; 1294: 6823 ldr r3, [r4, #0] 1296: f023 0302 bic.w r3, r3, #2 129a: 6023 str r3, [r4, #0] hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); 129c: 4790 blx r2 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_ENABLE); 129e: 2102 movs r1, #2 12a0: 4790 blx r2 } static inline void hri_tc_write_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t data) { TC_CRITICAL_SECTION_ENTER(); ((Tc *)hw)->COUNT16.CTRLA.reg = data; 12a2: 2301 movs r3, #1 12a4: 6023 str r3, [r4, #0] hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); 12a6: 2103 movs r1, #3 12a8: 4620 mov r0, r4 12aa: 4790 blx r2 hri_tc_write_CTRLA_reg(hw, _tcs[i].ctrl_a); 12ac: 4f37 ldr r7, [pc, #220] ; (138c <_timer_init+0x12c>) 12ae: 2514 movs r5, #20 12b0: fb05 7508 mla r5, r5, r8, r7 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); 12b4: 2101 movs r1, #1 12b6: 4620 mov r0, r4 12b8: 4790 blx r2 hri_tc_write_CTRLA_reg(hw, _tcs[i].ctrl_a); 12ba: 6a6e ldr r6, [r5, #36] ; 0x24 ((Tc *)hw)->COUNT16.CTRLA.reg = data; 12bc: 6026 str r6, [r4, #0] hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); 12be: 2103 movs r1, #3 12c0: 4790 blx r2 hri_tc_write_DBGCTRL_reg(hw, _tcs[i].dbg_ctrl); 12c2: f895 302a ldrb.w r3, [r5, #42] ; 0x2a } static inline void hri_tc_write_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t data) { TC_CRITICAL_SECTION_ENTER(); ((Tc *)hw)->COUNT16.DBGCTRL.reg = data; 12c6: 73e3 strb r3, [r4, #15] if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) { 12c8: f006 060c and.w r6, r6, #12 hri_tc_write_EVCTRL_reg(hw, _tcs[i].event_ctrl); 12cc: 8d2b ldrh r3, [r5, #40] ; 0x28 ((Tc *)hw)->COUNT16.EVCTRL.reg = data; 12ce: 80e3 strh r3, [r4, #6] if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) { 12d0: 2e08 cmp r6, #8 ((Tc *)hw)->COUNT16.WAVE.reg = data; 12d2: f04f 0301 mov.w r3, #1 12d6: 7323 strb r3, [r4, #12] 12d8: d13a bne.n 1350 <_timer_init+0xf0> hri_tccount32_write_CC_reg(hw, 0, _tcs[i].cc0); 12da: 6aeb ldr r3, [r5, #44] ; 0x2c } static inline void hri_tccount32_write_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data) { TC_CRITICAL_SECTION_ENTER(); ((Tc *)hw)->COUNT32.CC[index].reg = data; 12dc: 61e3 str r3, [r4, #28] hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); 12de: 21c0 movs r1, #192 ; 0xc0 12e0: 4790 blx r2 ((Tc *)hw)->COUNT32.CC[index].reg = data; 12e2: 2300 movs r3, #0 12e4: 6223 str r3, [r4, #32] hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); 12e6: 4790 blx r2 ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF; 12e8: 2301 movs r3, #1 12ea: 7263 strb r3, [r4, #9] if (hw == TC0) { 12ec: 4b28 ldr r3, [pc, #160] ; (1390 <_timer_init+0x130>) 12ee: 429c cmp r4, r3 _tc0_dev = (struct _timer_device *)dev; 12f0: bf04 itt eq 12f2: 4b28 ldreq r3, [pc, #160] ; (1394 <_timer_init+0x134>) 12f4: f8c3 9000 streq.w r9, [r3] NVIC_DisableIRQ(_tcs[i].irq); 12f8: 2314 movs r3, #20 12fa: fb03 7308 mla r3, r3, r8, r7 12fe: f9b3 3022 ldrsh.w r3, [r3, #34] ; 0x22 if ((int32_t)(IRQn) >= 0) 1302: 2b00 cmp r3, #0 1304: db0d blt.n 1322 <_timer_init+0xc2> NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1306: 095a lsrs r2, r3, #5 1308: 2101 movs r1, #1 130a: f003 031f and.w r3, r3, #31 130e: 4099 lsls r1, r3 1310: f102 0320 add.w r3, r2, #32 1314: 4a20 ldr r2, [pc, #128] ; (1398 <_timer_init+0x138>) 1316: f842 1023 str.w r1, [r2, r3, lsl #2] __ASM volatile ("dsb 0xF":::"memory"); 131a: f3bf 8f4f dsb sy __ASM volatile ("isb 0xF":::"memory"); 131e: f3bf 8f6f isb sy NVIC_ClearPendingIRQ(_tcs[i].irq); 1322: 2314 movs r3, #20 1324: fb03 7008 mla r0, r3, r8, r7 1328: f9b0 3022 ldrsh.w r3, [r0, #34] ; 0x22 if ((int32_t)(IRQn) >= 0) 132c: 2b00 cmp r3, #0 132e: db0c blt.n 134a <_timer_init+0xea> NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1330: f003 011f and.w r1, r3, #31 1334: 095b lsrs r3, r3, #5 1336: 009b lsls r3, r3, #2 1338: f103 4360 add.w r3, r3, #3758096384 ; 0xe0000000 133c: f503 4361 add.w r3, r3, #57600 ; 0xe100 1340: 2201 movs r2, #1 1342: 408a lsls r2, r1 1344: f8c3 2180 str.w r2, [r3, #384] ; 0x180 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1348: 601a str r2, [r3, #0] } 134a: 2000 movs r0, #0 134c: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} } else if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT16) { 1350: b92e cbnz r6, 135e <_timer_init+0xfe> hri_tccount16_write_CC_reg(hw, 0, (uint16_t)_tcs[i].cc0); 1352: 8dab ldrh r3, [r5, #44] ; 0x2c ((Tc *)hw)->COUNT16.CC[index].reg = data; 1354: 83a3 strh r3, [r4, #28] hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); 1356: 21c0 movs r1, #192 ; 0xc0 1358: 4790 blx r2 ((Tc *)hw)->COUNT16.CC[index].reg = data; 135a: 83e6 strh r6, [r4, #30] hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); 135c: e7c3 b.n 12e6 <_timer_init+0x86> } else if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT8) { 135e: 2e04 cmp r6, #4 1360: d1c2 bne.n 12e8 <_timer_init+0x88> hri_tccount8_write_CC_reg(hw, 0, (uint8_t)_tcs[i].cc0); 1362: f895 302c ldrb.w r3, [r5, #44] ; 0x2c ((Tc *)hw)->COUNT8.CC[index].reg = data; 1366: 7723 strb r3, [r4, #28] hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); 1368: 21c0 movs r1, #192 ; 0xc0 136a: 4790 blx r2 ((Tc *)hw)->COUNT8.CC[index].reg = data; 136c: 2300 movs r3, #0 136e: 7763 strb r3, [r4, #29] hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); 1370: 4790 blx r2 hri_tccount8_write_PER_reg(hw, _tcs[i].per); 1372: f895 302b ldrb.w r3, [r5, #43] ; 0x2b ((Tc *)hw)->COUNT8.PER.reg = data; 1376: 76e3 strb r3, [r4, #27] hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); 1378: 2120 movs r1, #32 137a: e7b4 b.n 12e6 <_timer_init+0x86> 137c: 00001211 .word 0x00001211 1380: 000005b1 .word 0x000005b1 1384: 00001542 .word 0x00001542 1388: 00001209 .word 0x00001209 138c: 00001558 .word 0x00001558 1390: 40003800 .word 0x40003800 1394: 200000d4 .word 0x200000d4 1398: e000e100 .word 0xe000e100 0000139c <_tc_get_timer>: } 139c: 2000 movs r0, #0 139e: 4770 bx lr 000013a0 : tc_interrupt_handler(_tc0_dev); 13a0: 4b05 ldr r3, [pc, #20] ; (13b8 ) 13a2: 6818 ldr r0, [r3, #0] void *const hw = device->hw; 13a4: 68c3 ldr r3, [r0, #12] return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; 13a6: 7a9a ldrb r2, [r3, #10] if (hri_tc_get_interrupt_OVF_bit(hw)) { 13a8: 07d2 lsls r2, r2, #31 13aa: d503 bpl.n 13b4 ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF; 13ac: 2201 movs r2, #1 13ae: 729a strb r2, [r3, #10] device->timer_cb.period_expired(device); 13b0: 6803 ldr r3, [r0, #0] 13b2: 4718 bx r3 } 13b4: 4770 bx lr 13b6: bf00 nop 13b8: 200000d4 .word 0x200000d4 000013bc : __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 13bc: f3ef 8310 mrs r3, PRIMASK /** * \brief Disable interrupts, enter critical section */ void atomic_enter_critical(hal_atomic_t volatile *atomic) { *atomic = __get_PRIMASK(); 13c0: 6003 str r3, [r0, #0] __ASM volatile ("cpsid i" : : : "memory"); 13c2: b672 cpsid i \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ __STATIC_FORCEINLINE void __DMB(void) { __ASM volatile ("dmb 0xF":::"memory"); 13c4: f3bf 8f5f dmb sy __disable_irq(); __DMB(); } 13c8: 4770 bx lr 000013ca : 13ca: f3bf 8f5f dmb sy * \brief Exit atomic section */ void atomic_leave_critical(hal_atomic_t volatile *atomic) { __DMB(); __set_PRIMASK(*atomic); 13ce: 6803 ldr r3, [r0, #0] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 13d0: f383 8810 msr PRIMASK, r3 } 13d4: 4770 bx lr ... 000013d8 <__libc_init_array>: 13d8: b570 push {r4, r5, r6, lr} 13da: 4d0d ldr r5, [pc, #52] ; (1410 <__libc_init_array+0x38>) 13dc: 4c0d ldr r4, [pc, #52] ; (1414 <__libc_init_array+0x3c>) 13de: 1b64 subs r4, r4, r5 13e0: 10a4 asrs r4, r4, #2 13e2: 2600 movs r6, #0 13e4: 42a6 cmp r6, r4 13e6: d109 bne.n 13fc <__libc_init_array+0x24> 13e8: 4d0b ldr r5, [pc, #44] ; (1418 <__libc_init_array+0x40>) 13ea: 4c0c ldr r4, [pc, #48] ; (141c <__libc_init_array+0x44>) 13ec: f000 f8ce bl 158c <_init> 13f0: 1b64 subs r4, r4, r5 13f2: 10a4 asrs r4, r4, #2 13f4: 2600 movs r6, #0 13f6: 42a6 cmp r6, r4 13f8: d105 bne.n 1406 <__libc_init_array+0x2e> 13fa: bd70 pop {r4, r5, r6, pc} 13fc: f855 3b04 ldr.w r3, [r5], #4 1400: 4798 blx r3 1402: 3601 adds r6, #1 1404: e7ee b.n 13e4 <__libc_init_array+0xc> 1406: f855 3b04 ldr.w r3, [r5], #4 140a: 4798 blx r3 140c: 3601 adds r6, #1 140e: e7f2 b.n 13f6 <__libc_init_array+0x1e> 1410: 00001598 .word 0x00001598 1414: 00001598 .word 0x00001598 1418: 00001598 .word 0x00001598 141c: 0000159c .word 0x0000159c 00001420 : 1420: 440a add r2, r1 1422: 4291 cmp r1, r2 1424: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff 1428: d100 bne.n 142c 142a: 4770 bx lr 142c: b510 push {r4, lr} 142e: f811 4b01 ldrb.w r4, [r1], #1 1432: f803 4f01 strb.w r4, [r3, #1]! 1436: 4291 cmp r1, r2 1438: d1f9 bne.n 142e 143a: bd10 pop {r4, pc} 0000143c : 143c: 4402 add r2, r0 143e: 4603 mov r3, r0 1440: 4293 cmp r3, r2 1442: d100 bne.n 1446 1444: 4770 bx lr 1446: f803 1b01 strb.w r1, [r3], #1 144a: e7f9 b.n 1440 144c: 682f2e2e .word 0x682f2e2e 1450: 732f6c61 .word 0x732f6c61 1454: 682f6372 .word 0x682f6372 1458: 745f6c61 .word 0x745f6c61 145c: 72656d69 .word 0x72656d69 1460: 632e .short 0x632e 1462: 00 .byte 0x00 1463: 2e .byte 0x2e 1464: 61682f2e .word 0x61682f2e 1468: 72732f6c .word 0x72732f6c 146c: 61682f63 .word 0x61682f63 1470: 32695f6c .word 0x32695f6c 1474: 5f6d5f63 .word 0x5f6d5f63 1478: 636e7973 .word 0x636e7973 147c: 632e .short 0x632e 147e: 00 .byte 0x00 147f: 2e .byte 0x2e 1480: 61682f2e .word 0x61682f2e 1484: 74752f6c .word 0x74752f6c 1488: 2f736c69 .word 0x2f736c69 148c: 2f637273 .word 0x2f637273 1490: 6c697475 .word 0x6c697475 1494: 696c5f73 .word 0x696c5f73 1498: 632e7473 .word 0x632e7473 149c: 00 .byte 0x00 149d: 2e .byte 0x2e 149e: 2f2e .short 0x2f2e 14a0: 2f6c7068 .word 0x2f6c7068 14a4: 63726573 .word 0x63726573 14a8: 682f6d6f .word 0x682f6d6f 14ac: 735f6c70 .word 0x735f6c70 14b0: 6f637265 .word 0x6f637265 14b4: 00632e6d .word 0x00632e6d 14b8: 40003000 .word 0x40003000 14bc: 40003400 .word 0x40003400 14c0: 41012000 .word 0x41012000 14c4: 41014000 .word 0x41014000 14c8: 43000000 .word 0x43000000 14cc: 43000400 .word 0x43000400 14d0: 43000800 .word 0x43000800 14d4: 43000c00 .word 0x43000c00 000014d8 <_i2cms>: 14d8: 00000003 00200014 00000100 000000ff ...... ......... 14e8: 00d70000 07270400 ......'. 000014f0 : ... 1500: 2f2e2e00 2f6c6168 2f637273 5f6c6168 .../hal/src/hal_ 1510: 72617375 73615f74 2e636e79 2e2e0063 usart_async.c... 1520: 6c61682f 6974752f 732f736c 752f6372 /hal/utils/src/u 1530: 736c6974 6e69725f 66756267 2e726566 tils_ringbuffer. 1540: 2e2e0063 6c70682f 2f63742f 5f6c7068 c.../hpl/tc/hpl_ 1550: 632e6374 00000000 40003800 40003c00 tc.c.....8.@.<.@ 1560: 4101a000 4101c000 42001400 42001800 ...A...A...B...B 1570: 43001400 43001800 ...C...C 00001578 <_tcs>: 1578: 006b0000 00000308 00000000 00003a97 ..k..........:.. 1588: 00000000 .... 0000158c <_init>: 158c: b5f8 push {r3, r4, r5, r6, r7, lr} 158e: bf00 nop 1590: bcf8 pop {r3, r4, r5, r6, r7} 1592: bc08 pop {r3} 1594: 469e mov lr, r3 1596: 4770 bx lr 00001598 <__frame_dummy_init_array_entry>: 1598: 02cd 0000 .... 0000159c <_fini>: 159c: b5f8 push {r3, r4, r5, r6, r7, lr} 159e: bf00 nop 15a0: bcf8 pop {r3, r4, r5, r6, r7} 15a2: bc08 pop {r3} 15a4: 469e mov lr, r3 15a6: 4770 bx lr 000015a8 <__do_global_dtors_aux_fini_array_entry>: 15a8: 02a5 0000 ....