From df5085aeb60fda90f5016e4eb9e89aaa845e5300 Mon Sep 17 00:00:00 2001
From: Penguin <penguin@epenguin.net>
Date: Sun, 15 Mar 2020 18:44:01 -0500
Subject: [PATCH] finished making e54 symbol... snapeda one was garbage

---
 electrical/same54_dev_board/fp-info-cache     |   1 +
 .../same54_dev_board-cache.lib                | 153 ++++++++++++++++++
 .../same54_dev_board.kicad_pcb                | 110 +++++++++++++
 .../same54_dev_board.kicad_pcb-bak            |   1 +
 .../same54_dev_board/same54_dev_board.pro     |  33 ++++
 .../same54_dev_board/same54_dev_board.sch     |  38 +++++
 .../same54_dev_board/same54_dev_board.sch-bak |   4 +
 7 files changed, 340 insertions(+)
 create mode 100644 electrical/same54_dev_board/fp-info-cache
 create mode 100644 electrical/same54_dev_board/same54_dev_board-cache.lib
 create mode 100644 electrical/same54_dev_board/same54_dev_board.kicad_pcb
 create mode 100644 electrical/same54_dev_board/same54_dev_board.kicad_pcb-bak
 create mode 100644 electrical/same54_dev_board/same54_dev_board.pro
 create mode 100644 electrical/same54_dev_board/same54_dev_board.sch
 create mode 100644 electrical/same54_dev_board/same54_dev_board.sch-bak

diff --git a/electrical/same54_dev_board/fp-info-cache b/electrical/same54_dev_board/fp-info-cache
new file mode 100644
index 00000000..18748286
--- /dev/null
+++ b/electrical/same54_dev_board/fp-info-cache
@@ -0,0 +1 @@
+0
diff --git a/electrical/same54_dev_board/same54_dev_board-cache.lib b/electrical/same54_dev_board/same54_dev_board-cache.lib
new file mode 100644
index 00000000..aa69c200
--- /dev/null
+++ b/electrical/same54_dev_board/same54_dev_board-cache.lib
@@ -0,0 +1,153 @@
+EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# p_ATSAME54P20A-AU_p_ATSAME54P20A-AU
+#
+DEF p_ATSAME54P20A-AU_p_ATSAME54P20A-AU U 0 40 Y Y 5 L N
+F0 "U" 0 -2600 50 H V C CNN
+F1 "p_ATSAME54P20A-AU_p_ATSAME54P20A-AU" 0 1050 50 H V C CNN
+F2 "" -1200 1250 50 H I C CNN
+F3 "" -1200 1250 50 H I C CNN
+DRAW
+T 0 0 950 50 0 1 0 "Port A" Normal 0 C C
+T 0 0 800 50 0 2 0 "Port B" Normal 0 C C
+T 0 0 750 50 0 3 0 "Port C" Normal 0 C C
+T 0 0 850 50 0 4 0 "Port D" Normal 0 C C
+T 0 50 650 50 0 5 0 "Power Bus" Normal 0 C C
+S -450 1000 400 -2150 1 1 0 f
+S -500 900 500 -2550 2 1 0 f
+S -450 850 450 -2250 3 1 0 f
+S -400 900 400 -150 4 1 0 f
+S -800 750 800 -1450 5 1 0 f
+X XIN32/PA00 1 600 750 200 L 50 50 1 1 B
+X PA03 10 600 450 200 L 50 50 1 1 B
+X PA27 113 600 -1850 200 L 50 50 1 1 B
+X SWCLK/PA30 119 600 -1950 200 L 50 50 1 1 B
+X SWDIO/PA31 120 600 -2050 200 L 50 50 1 1 B
+X XOUT32/PA01 2 600 650 200 L 50 50 1 1 B
+X PA04 21 600 350 200 L 50 50 1 1 B
+X PA05 22 600 250 200 L 50 50 1 1 B
+X PA06 23 600 150 200 L 50 50 1 1 B
+X PA07 24 600 50 200 L 50 50 1 1 B
+X PA08 33 600 -50 200 L 50 50 1 1 B
+X PA09 34 600 -150 200 L 50 50 1 1 B
+X PA10 35 600 -250 200 L 50 50 1 1 B
+X PA11 36 600 -350 200 L 50 50 1 1 B
+X PA12 60 600 -450 200 L 50 50 1 1 B
+X PA13 61 600 -550 200 L 50 50 1 1 B
+X XIN0/PA14 62 600 -650 200 L 50 50 1 1 B
+X XOUT0/PA15 63 600 -750 200 L 50 50 1 1 B
+X PA16 66 600 -850 200 L 50 50 1 1 B
+X PA17 67 600 -950 200 L 50 50 1 1 B
+X PA18 68 600 -1050 200 L 50 50 1 1 B
+X PA19 69 600 -1150 200 L 50 50 1 1 B
+X PA20 88 600 -1250 200 L 50 50 1 1 B
+X PA21 89 600 -1350 200 L 50 50 1 1 B
+X PA02 9 600 550 200 L 50 50 1 1 B
+X PA22 92 600 -1450 200 L 50 50 1 1 B
+X PA23 93 600 -1550 200 L 50 50 1 1 B
+X PA24 94 600 -1650 200 L 50 50 1 1 B
+X PA25 95 600 -1750 200 L 50 50 1 1 B
+X PB24 100 700 -1750 197 L 50 50 2 1 B
+X PB25 101 700 -1850 197 L 50 50 2 1 B
+X PB26 102 700 -1950 197 L 50 50 2 1 B
+X PB27 103 700 -2050 197 L 50 50 2 1 B
+X PB28 104 700 -2150 197 L 50 50 2 1 B
+X PB29 105 700 -2250 197 L 50 50 2 1 B
+X PB04 11 700 250 197 L 50 50 2 1 B
+X PB05 12 700 150 197 L 50 50 2 1 B
+X SWO/PB30 121 700 -2350 197 L 50 50 2 1 B
+X PB31 122 700 -2450 197 L 50 50 2 1 B
+X PB00 125 700 650 197 L 50 50 2 1 B
+X PB01 126 700 550 197 L 50 50 2 1 B
+X PB02 127 700 450 197 L 50 50 2 1 B
+X PB03 128 700 350 197 L 50 50 2 1 B
+X PB06 17 700 50 197 L 50 50 2 1 B
+X PB07 18 700 -50 197 L 50 50 2 1 B
+X PB08 19 700 -150 197 L 50 50 2 1 B
+X PB09 20 700 -250 197 L 50 50 2 1 B
+X PB10 39 700 -350 197 L 50 50 2 1 B
+X PB11 40 700 -450 197 L 50 50 2 1 B
+X PB12 41 700 -550 197 L 50 50 2 1 B
+X PB13 42 700 -650 197 L 50 50 2 1 B
+X PB14 43 700 -750 197 L 50 50 2 1 B
+X PB15 44 700 -850 197 L 50 50 2 1 B
+X PB16 82 700 -950 197 L 50 50 2 1 B
+X PB17 83 700 -1050 197 L 50 50 2 1 B
+X PB18 84 700 -1150 197 L 50 50 2 1 B
+X PB19 85 700 -1250 197 L 50 50 2 1 B
+X PB20 86 700 -1350 197 L 50 50 2 1 B
+X PB21 87 700 -1450 197 L 50 50 2 1 B
+X XIN1/PB22 98 700 -1550 197 L 50 50 2 1 B
+X XOUT1/PB23 99 700 -1650 197 L 50 50 2 1 B
+X PC24 108 650 -1550 197 L 50 50 3 1 B
+X PC25 109 650 -1650 197 L 50 50 3 1 B
+X PC26 110 650 -1750 197 L 50 50 3 1 B
+X PC27 111 650 -1850 197 L 50 50 3 1 B
+X PC28 112 650 -1950 197 L 50 50 3 1 B
+X PC30 123 650 -2050 197 L 50 50 3 1 B
+X PC31 124 650 -2150 197 L 50 50 3 1 B
+X PC04 27 650 250 197 L 50 50 3 1 B
+X PC05 28 650 150 197 L 50 50 3 1 B
+X PC06 29 650 50 197 L 50 50 3 1 B
+X PC00 3 650 650 197 L 50 50 3 1 B
+X PC07 30 650 -50 197 L 50 50 3 1 B
+X PC01 4 650 550 197 L 50 50 3 1 B
+X PC10 52 650 -150 197 L 50 50 3 1 B
+X PC11 55 650 -250 197 L 50 50 3 1 B
+X PC12 56 650 -350 197 L 50 50 3 1 B
+X PC13 57 650 -450 197 L 50 50 3 1 B
+X PC14 58 650 -550 197 L 50 50 3 1 B
+X PC15 59 650 -650 197 L 50 50 3 1 B
+X PC02 7 650 450 197 L 50 50 3 1 B
+X PC16 70 650 -750 197 L 50 50 3 1 B
+X PC17 71 650 -850 197 L 50 50 3 1 B
+X PC18 72 650 -950 197 L 50 50 3 1 B
+X PC19 73 650 -1050 197 L 50 50 3 1 B
+X PC20 74 650 -1150 197 L 50 50 3 1 B
+X PC21 75 650 -1250 197 L 50 50 3 1 B
+X PC22 76 650 -1350 197 L 50 50 3 1 B
+X PC23 77 650 -1450 197 L 50 50 3 1 B
+X PC03 8 650 350 197 L 50 50 3 1 B
+X PD00 13 600 750 197 L 50 50 4 1 B
+X PD01 16 600 650 197 L 50 50 4 1 B
+X PD08 47 600 550 197 L 50 50 4 1 B
+X PD09 48 600 450 197 L 50 50 4 1 B
+X PD10 49 600 350 197 L 50 50 4 1 B
+X PD11 50 600 250 197 L 50 50 4 1 B
+X PD12 51 600 150 197 L 50 50 4 1 B
+X PD20 80 600 50 197 L 50 50 4 1 B
+X PD21 81 600 -50 197 L 50 50 4 1 B
+X VDDIO7 107 -1000 -900 197 R 50 50 5 1 W
+X ~RESET 114 -1000 650 197 R 50 50 5 1 B
+X VDDCORE 115 -1000 -1150 197 R 50 50 5 1 W
+X GNDIO 116 1000 -850 197 L 50 50 5 1 W
+X VSW 117 -1000 -1300 197 R 50 50 5 1 W
+X VDDIO8 118 -1000 -1000 197 R 50 50 5 1 W
+X GNDANA1 14 1000 -500 197 L 50 50 5 1 W
+X VDDANA2 15 -1000 300 197 R 50 50 5 1 B
+X GNDANA2 25 1000 -600 197 L 50 50 5 1 W
+X VDDANA3 26 -1000 200 197 R 50 50 5 1 B
+X VDDIOB1 32 -1000 0 197 R 50 50 5 1 B
+X VDDIOB2 37 -1000 -100 197 R 50 50 5 1 B
+X VDDIO1 46 -1000 -300 197 R 50 50 5 1 W
+X GND1 5 1000 650 197 L 50 50 5 1 W
+X GND10 5 1000 -250 197 L 50 50 5 1 W
+X GND2 5 1000 550 197 L 50 50 5 1 W
+X GND3 5 1000 450 197 L 50 50 5 1 W
+X GND4 5 1000 350 197 L 50 50 5 1 W
+X GND5 5 1000 250 197 L 50 50 5 1 W
+X GND6 5 1000 150 197 L 50 50 5 1 W
+X GND7 5 1000 50 197 L 50 50 5 1 W
+X GND8 5 1000 -50 197 L 50 50 5 1 W
+X GND9 5 1000 -150 197 L 50 50 5 1 W
+X VDDIO2 54 -1000 -400 197 R 50 50 5 1 W
+X VDDANA1 6 -1000 400 197 R 50 50 5 1 B
+X VDDIO3 65 -1000 -500 197 R 50 50 5 1 W
+X VDDIO4 79 -1000 -600 197 R 50 50 5 1 W
+X VDDIO5 91 -1000 -700 197 R 50 50 5 1 W
+X VDDIO6 97 -1000 -800 197 R 50 50 5 1 W
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/electrical/same54_dev_board/same54_dev_board.kicad_pcb b/electrical/same54_dev_board/same54_dev_board.kicad_pcb
new file mode 100644
index 00000000..c2b1bdcd
--- /dev/null
+++ b/electrical/same54_dev_board/same54_dev_board.kicad_pcb
@@ -0,0 +1,110 @@
+(kicad_pcb (version 20171130) (host pcbnew "(5.1.5)-3")
+
+  (general
+    (thickness 1.6)
+    (drawings 5)
+    (tracks 0)
+    (zones 0)
+    (modules 0)
+    (nets 1)
+  )
+
+  (page A4)
+  (layers
+    (0 F.Cu signal)
+    (31 B.Cu signal)
+    (32 B.Adhes user)
+    (33 F.Adhes user)
+    (34 B.Paste user)
+    (35 F.Paste user)
+    (36 B.SilkS user)
+    (37 F.SilkS user)
+    (38 B.Mask user)
+    (39 F.Mask user)
+    (40 Dwgs.User user)
+    (41 Cmts.User user)
+    (42 Eco1.User user)
+    (43 Eco2.User user)
+    (44 Edge.Cuts user)
+    (45 Margin user)
+    (46 B.CrtYd user)
+    (47 F.CrtYd user)
+    (48 B.Fab user)
+    (49 F.Fab user)
+  )
+
+  (setup
+    (last_trace_width 0.25)
+    (trace_clearance 0.2)
+    (zone_clearance 0.508)
+    (zone_45_only no)
+    (trace_min 0.2)
+    (via_size 0.8)
+    (via_drill 0.4)
+    (via_min_size 0.4)
+    (via_min_drill 0.3)
+    (uvia_size 0.3)
+    (uvia_drill 0.1)
+    (uvias_allowed no)
+    (uvia_min_size 0.2)
+    (uvia_min_drill 0.1)
+    (edge_width 0.05)
+    (segment_width 0.2)
+    (pcb_text_width 0.3)
+    (pcb_text_size 1.5 1.5)
+    (mod_edge_width 0.12)
+    (mod_text_size 1 1)
+    (mod_text_width 0.15)
+    (pad_size 1.524 1.524)
+    (pad_drill 0.762)
+    (pad_to_mask_clearance 0.051)
+    (solder_mask_min_width 0.25)
+    (aux_axis_origin 0 0)
+    (visible_elements FFFFFF7F)
+    (pcbplotparams
+      (layerselection 0x010fc_ffffffff)
+      (usegerberextensions false)
+      (usegerberattributes false)
+      (usegerberadvancedattributes false)
+      (creategerberjobfile false)
+      (excludeedgelayer true)
+      (linewidth 0.100000)
+      (plotframeref false)
+      (viasonmask false)
+      (mode 1)
+      (useauxorigin false)
+      (hpglpennumber 1)
+      (hpglpenspeed 20)
+      (hpglpendiameter 15.000000)
+      (psnegative false)
+      (psa4output false)
+      (plotreference true)
+      (plotvalue true)
+      (plotinvisibletext false)
+      (padsonsilk false)
+      (subtractmaskfromsilk false)
+      (outputformat 1)
+      (mirror false)
+      (drillshape 1)
+      (scaleselection 1)
+      (outputdirectory ""))
+  )
+
+  (net 0 "")
+
+  (net_class Default "This is the default net class."
+    (clearance 0.2)
+    (trace_width 0.25)
+    (via_dia 0.8)
+    (via_drill 0.4)
+    (uvia_dia 0.3)
+    (uvia_drill 0.1)
+  )
+
+  (gr_line (start 50.8 50.8) (end 53.34 50.8) (layer Edge.Cuts) (width 0.05) (tstamp 5E6E9EBC))
+  (gr_line (start 50.8 134.62) (end 50.8 50.8) (layer Edge.Cuts) (width 0.05))
+  (gr_line (start 228.6 134.62) (end 50.8 134.62) (layer Edge.Cuts) (width 0.05))
+  (gr_line (start 228.6 50.8) (end 228.6 134.62) (layer Edge.Cuts) (width 0.05))
+  (gr_line (start 53.34 50.8) (end 228.6 50.8) (layer Edge.Cuts) (width 0.05))
+
+)
diff --git a/electrical/same54_dev_board/same54_dev_board.kicad_pcb-bak b/electrical/same54_dev_board/same54_dev_board.kicad_pcb-bak
new file mode 100644
index 00000000..02c8ecb0
--- /dev/null
+++ b/electrical/same54_dev_board/same54_dev_board.kicad_pcb-bak
@@ -0,0 +1 @@
+(kicad_pcb (version 4) (host kicad "dummy file") )
diff --git a/electrical/same54_dev_board/same54_dev_board.pro b/electrical/same54_dev_board/same54_dev_board.pro
new file mode 100644
index 00000000..152769cb
--- /dev/null
+++ b/electrical/same54_dev_board/same54_dev_board.pro
@@ -0,0 +1,33 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
diff --git a/electrical/same54_dev_board/same54_dev_board.sch b/electrical/same54_dev_board/same54_dev_board.sch
new file mode 100644
index 00000000..49670178
--- /dev/null
+++ b/electrical/same54_dev_board/same54_dev_board.sch
@@ -0,0 +1,38 @@
+EESchema Schematic File Version 4
+EELAYER 30 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L p_ATSAME54P20A-AU:p_ATSAME54P20A-AU U?
+U 1 1 5E73E542
+P 1500 2100
+F 0 "U?" H 1583 3265 50  0000 C CNN
+F 1 "p_ATSAME54P20A-AU" H 1583 3174 50  0000 C CNN
+F 2 "" H 300 3350 50  0001 C CNN
+F 3 "" H 300 3350 50  0001 C CNN
+	1    1500 2100
+	1    0    0    -1  
+$EndComp
+$Comp
+L p_ATSAME54P20A-AU:p_ATSAME54P20A-AU U?
+U 2 1 5E742312
+P 3350 1900
+F 0 "U?" H 3458 2965 50  0000 C CNN
+F 1 "p_ATSAME54P20A-AU" H 3458 2874 50  0000 C CNN
+F 2 "" H 2150 3150 50  0001 C CNN
+F 3 "" H 2150 3150 50  0001 C CNN
+	2    3350 1900
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/electrical/same54_dev_board/same54_dev_board.sch-bak b/electrical/same54_dev_board/same54_dev_board.sch-bak
new file mode 100644
index 00000000..fff8c689
--- /dev/null
+++ b/electrical/same54_dev_board/same54_dev_board.sch-bak
@@ -0,0 +1,4 @@
+EESchema Schematic File Version 2
+EELAYER 25 0
+EELAYER END
+$EndSCHEMATC